[pcsx_rearmed.git] / libpcsxcore / r3000a.c

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
* R3000A CPU functions.
*/

#include "r3000a.h"
#include "cdrom.h"
#include "mdec.h"
#include "gte.h"
#include "psxinterpreter.h"
#include "../include/compiler_features.h"

R3000Acpu *psxCpu = NULL;
#ifdef DRC_DISABLE
psxRegisters psxRegs;
#endif

int psxInit() {
	SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);

#ifndef DRC_DISABLE
	if (Config.Cpu == CPU_INTERPRETER) {
		psxCpu = &psxInt;
	} else psxCpu = &psxRec;
#else
	Config.Cpu = CPU_INTERPRETER;
	psxCpu = &psxInt;
#endif

	Log = 0;

	if (psxMemInit() == -1) return -1;

	return psxCpu->Init();
}

void psxReset() {
	boolean introBypassed = FALSE;
	psxMemReset();

	memset(&psxRegs, 0, sizeof(psxRegs));

	psxRegs.pc = 0xbfc00000; // Start in bootstrap

	psxRegs.CP0.n.SR   = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
	psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
	if (Config.HLE) {
		psxRegs.CP0.n.SR |= 1u << 30;    // COP2 enabled
		psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
	}

	psxCpu->ApplyConfig();
	psxCpu->Reset();

	psxHwReset();
	psxBiosInit();

	if (!Config.HLE) {
		psxExecuteBios();
		if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
			BiosBootBypass();
			introBypassed = TRUE;
		}
	}
	if (Config.HLE || introBypassed)
		psxBiosSetupBootState();

#ifdef EMU_LOG
	EMU_LOG("*BIOS END*\n");
#endif
	Log = 0;
}

void psxShutdown() {
	psxBiosShutdown();

	psxCpu->Shutdown();

	psxMemShutdown();
}

// cp0 is passed separately for lightrec to be less messy
void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
	u32 opcode = intFakeFetch(psxRegs.pc);
	
	if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
		// "hokuto no ken" / "Crash Bandicot 2" ...
		// BIOS does not allow to return to GTE instructions
		// (just skips it, supposedly because it's scheduled already)
		// so we execute it here
		psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
		psxRegs.code = opcode;
		psxCP2[opcode & 0x3f](cp2);
	}

	// Set the Cause
	cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;

	// Set the EPC & PC
	cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;

	if (cp0->n.SR & 0x400000)
		psxRegs.pc = 0xbfc00180;
	else
		psxRegs.pc = 0x80000080;

	// Set the SR
	cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
}

void psxBranchTest() {
	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
		psxRcntUpdate();

	if (psxRegs.interrupt) {
		if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SIO);
				sioInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDR);
				cdrInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
				cdrPlayReadInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
				gpuInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
				mdec1Interrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
				spuInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
				mdec0Interrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
				gpuotcInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
				cdrDmaInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
				cdrLidSeekInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
				irq10Interrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
				spuUpdate();
			}
		}
	}

	psxRegs.CP0.n.Cause &= ~0x400;
	if (psxHu32(0x1070) & psxHu32(0x1074))
		psxRegs.CP0.n.Cause |= 0x400;
	if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
		psxException(0, 0, &psxRegs.CP0);
}

void psxJumpTest() {
	if (!Config.HLE && Config.PsxOut) {
		u32 call = psxRegs.GPR.n.t1 & 0xff;
		switch (psxRegs.pc & 0x1fffff) {
			case 0xa0:
#ifdef PSXBIOS_LOG
				if (call != 0x28 && call != 0xe) {
					PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
#endif
				if (biosA0[call])
					biosA0[call]();
				break;
			case 0xb0:
#ifdef PSXBIOS_LOG
				if (call != 0x17 && call != 0xb) {
					PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
#endif
				if (biosB0[call])
					biosB0[call]();
				break;
			case 0xc0:
#ifdef PSXBIOS_LOG
				PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
#endif
				if (biosC0[call])
					biosC0[call]();
				break;
		}
	}
}

void psxExecuteBios() {
	int i;
	for (i = 0; i < 5000000; i++) {
		psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
		if ((psxRegs.pc & 0xff800000) == 0x80000000)
			break;
	}
	if (psxRegs.pc != 0x80030000)
		SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
}

// irq10 stuff, very preliminary
static int irq10count;

static void psxScheduleIrq10One(u32 cycles_abs) {
	// schedule relative to frame start
	u32 c = cycles_abs - rcnts[3].cycleStart;
	assert((s32)c >= 0);
	psxRegs.interrupt |= 1 << PSXINT_IRQ10;
	psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
	psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
	new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
}

void irq10Interrupt() {
	u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
		+ psxRegs.intCycle[PSXINT_IRQ10].cycle;

	psxHu32ref(0x1070) |= SWAPu32(0x400);

#if 0
	s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
	printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
		(s32)((float)framec / (PSXCLK / 60 / 263.0f)),
		irq10count, psxRegs.cycle - prevc,
		(psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
#endif
	if (--irq10count > 0) {
		u32 cycles_per_line = Config.PsxType
			? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
		psxScheduleIrq10One(prevc + cycles_per_line);
	}
}

void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
	//printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
	u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
	u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
	cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
	cycles += x_cycles;
	psxScheduleIrq10One(cycles);
	irq10count = irq_count;
}
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* R3000A CPU functions.
	22	*/
	23
	24	#include "r3000a.h"
	25	#include "cdrom.h"
	26	#include "mdec.h"
	27	#include "gte.h"
61ad2a61	28	#include "psxinterpreter.h"
905b7c25	29	#include "../include/compiler_features.h"
ef79bbde P	30
ef79bbde P	31	R3000Acpu *psxCpu = NULL;
41e82ad4	32	#ifdef DRC_DISABLE
ef79bbde	33	psxRegisters psxRegs;
41e82ad4	34	#endif
ef79bbde P	35
ef79bbde P	36	int psxInit() {
7a8d521f	37	SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
ef79bbde	38
41e82ad4	39	#ifndef DRC_DISABLE
ef79bbde P	40	if (Config.Cpu == CPU_INTERPRETER) {
	41	psxCpu = &psxInt;
	42	} else psxCpu = &psxRec;
	43	#else
61ad2a61	44	Config.Cpu = CPU_INTERPRETER;
ef79bbde P	45	psxCpu = &psxInt;
	46	#endif
	47
	48	Log = 0;
	49
	50	if (psxMemInit() == -1) return -1;
	51
	52	return psxCpu->Init();
	53	}
	54
	55	void psxReset() {
14b3bd95	56	boolean introBypassed = FALSE;
ef79bbde P	57	psxMemReset();
	58
	59	memset(&psxRegs, 0, sizeof(psxRegs));
	60
	61	psxRegs.pc = 0xbfc00000; // Start in bootstrap
	62
bc7c5acb	63	psxRegs.CP0.n.SR = 0x10600000; // COP0 enabled \| BEV = 1 \| TS = 1
bc7c5acb	64	psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
7650b754	65	if (Config.HLE) {
	66	psxRegs.CP0.n.SR \|= 1u << 30; // COP2 enabled
	67	psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
	68	}
ef79bbde	69
d5aeda23	70	psxCpu->ApplyConfig();
c24732c0	71	psxCpu->Reset();
c24732c0	72
ef79bbde P	73	psxHwReset();
	74	psxBiosInit();
	75
7b75929b	76	if (!Config.HLE) {
ef79bbde	77	psxExecuteBios();
14b3bd95	78	if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
7b75929b	79	BiosBootBypass();
14b3bd95	80	introBypassed = TRUE;
14b3bd95	81	}
7b75929b	82	}
14b3bd95	83	if (Config.HLE \|\| introBypassed)
14b3bd95	84	psxBiosSetupBootState();
ef79bbde P	85
	86	#ifdef EMU_LOG
	87	EMU_LOG("BIOS END\n");
	88	#endif
	89	Log = 0;
	90	}
	91
	92	void psxShutdown() {
ef79bbde P	93	psxBiosShutdown();
	94
	95	psxCpu->Shutdown();
7a8d521f	96
7a8d521f	97	psxMemShutdown();
ef79bbde P	98	}
ef79bbde P	99
6d75addf	100	// cp0 is passed separately for lightrec to be less messy
bc7c5acb	101	void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
905b7c25	102	u32 opcode = intFakeFetch(psxRegs.pc);
943a507a	103
3d1c03e7	104	if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
665e364a	105	// "hokuto no ken" / "Crash Bandicot 2" ...
	106	// BIOS does not allow to return to GTE instructions
	107	// (just skips it, supposedly because it's scheduled already)
62656449	108	// so we execute it here
bc7c5acb	109	psxCP2Regs cp2 = (psxCP2Regs )(cp0 + 1);
905b7c25	110	psxRegs.code = opcode;
905b7c25	111	psxCP2[opcode & 0x3f](cp2);
665e364a	112	}
665e364a	113
ef79bbde	114	// Set the Cause
0b1da491	115	cp0->n.Cause = (bdt << 30) \| (cp0->n.Cause & 0x700) \| cause;
ef79bbde P	116
ef79bbde P	117	// Set the EPC & PC
bc7c5acb	118	cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
ef79bbde	119
bc7c5acb	120	if (cp0->n.SR & 0x400000)
ef79bbde P	121	psxRegs.pc = 0xbfc00180;
	122	else
	123	psxRegs.pc = 0x80000080;
	124
bc7c5acb	125	// Set the SR
bc7c5acb	126	cp0->n.SR = (cp0->n.SR & ~0x3f) \| ((cp0->n.SR & 0x0f) << 2);
ef79bbde P	127	}
	128
	129	void psxBranchTest() {
	130	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
	131	psxRcntUpdate();
	132
	133	if (psxRegs.interrupt) {
d014a471	134	if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
d28b54b1	135	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
d28b54b1	136	psxRegs.interrupt &= ~(1 << PSXINT_SIO);
ef79bbde P	137	sioInterrupt();
	138	}
	139	}
d28b54b1	140	if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
	141	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
	142	psxRegs.interrupt &= ~(1 << PSXINT_CDR);
ef79bbde P	143	cdrInterrupt();
	144	}
	145	}
d28b54b1	146	if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
	147	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
	148	psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
480e570b	149	cdrPlayReadInterrupt();
ef79bbde P	150	}
ef79bbde P	151	}
d28b54b1	152	if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
	153	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
	154	psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
ef79bbde P	155	gpuInterrupt();
	156	}
	157	}
d28b54b1	158	if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
	159	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
	160	psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
ef79bbde P	161	mdec1Interrupt();
	162	}
	163	}
d28b54b1	164	if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
	165	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
	166	psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
ef79bbde P	167	spuInterrupt();
	168	}
	169	}
528ad661	170	if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
	171	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
	172	psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
	173	mdec0Interrupt();
	174	}
	175	}
57a757ce	176	if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
	177	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
	178	psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
	179	gpuotcInterrupt();
	180	}
	181	}
9f8b032d	182	if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
	183	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
	184	psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
	185	cdrDmaInterrupt();
	186	}
	187	}
	188	if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
	189	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
	190	psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
	191	cdrLidSeekInterrupt();
	192	}
	193	}
11d23573	194	if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
	195	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
	196	psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
	197	irq10Interrupt();
	198	}
	199	}
2b30c129	200	if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
	201	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
	202	psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
	203	spuUpdate();
	204	}
	205	}
ef79bbde P	206	}
ef79bbde P	207
0b1da491	208	psxRegs.CP0.n.Cause &= ~0x400;
	209	if (psxHu32(0x1070) & psxHu32(0x1074))
	210	psxRegs.CP0.n.Cause \|= 0x400;
	211	if (((psxRegs.CP0.n.Cause \| 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
	212	psxException(0, 0, &psxRegs.CP0);
ef79bbde P	213	}
	214
	215	void psxJumpTest() {
	216	if (!Config.HLE && Config.PsxOut) {
	217	u32 call = psxRegs.GPR.n.t1 & 0xff;
	218	switch (psxRegs.pc & 0x1fffff) {
	219	case 0xa0:
	220	#ifdef PSXBIOS_LOG
	221	if (call != 0x28 && call != 0xe) {
	222	PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
	223	#endif
	224	if (biosA0[call])
	225	biosA0[call]();
	226	break;
	227	case 0xb0:
	228	#ifdef PSXBIOS_LOG
	229	if (call != 0x17 && call != 0xb) {
	230	PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
	231	#endif
	232	if (biosB0[call])
	233	biosB0[call]();
	234	break;
	235	case 0xc0:
	236	#ifdef PSXBIOS_LOG
	237	PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
	238	#endif
	239	if (biosC0[call])
	240	biosC0[call]();
	241	break;
	242	}
	243	}
	244	}
	245
	246	void psxExecuteBios() {
7b75929b	247	int i;
da65071f	248	for (i = 0; i < 5000000; i++) {
	249	psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
	250	if ((psxRegs.pc & 0xff800000) == 0x80000000)
	251	break;
	252	}
	253	if (psxRegs.pc != 0x80030000)
	254	SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
ef79bbde P	255	}
ef79bbde P	256
11d23573	257	// irq10 stuff, very preliminary
	258	static int irq10count;
	259
	260	static void psxScheduleIrq10One(u32 cycles_abs) {
	261	// schedule relative to frame start
	262	u32 c = cycles_abs - rcnts[3].cycleStart;
	263	assert((s32)c >= 0);
	264	psxRegs.interrupt \|= 1 << PSXINT_IRQ10;
	265	psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
	266	psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
a004140a	267	new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
11d23573	268	}
	269
	270	void irq10Interrupt() {
	271	u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
	272	+ psxRegs.intCycle[PSXINT_IRQ10].cycle;
	273
	274	psxHu32ref(0x1070) \|= SWAPu32(0x400);
	275
	276	#if 0
	277	s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
	278	printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
	279	(s32)((float)framec / (PSXCLK / 60 / 263.0f)),
	280	irq10count, psxRegs.cycle - prevc,
	281	(psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
	282	#endif
1351a8fb	283	if (--irq10count > 0) {
	284	u32 cycles_per_line = Config.PsxType
	285	? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
	286	psxScheduleIrq10One(prevc + cycles_per_line);
	287	}
11d23573	288	}
	289
	290	void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
	291	//printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
	292	u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
	293	u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
	294	cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
	295	cycles += x_cycles;
	296	psxScheduleIrq10One(cycles);
	297	irq10count = irq_count;
	298	}