1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
137 #define MMREG 38 // Pointer to memory_map
138 #define ROREG 39 // ram offset (if rdram!=0x80000000)
140 #define FTEMP 40 // FPU temporary register
141 #define PTEMP 41 // Prefetch temporary register
142 #define TLREG 42 // TLB mapping offset
143 #define RHASH 43 // Return address hash
144 #define RHTBL 44 // Return address hash table address
145 #define RTEMP 45 // JR/JALR address register
147 #define AGEN1 46 // Address generation temporary register
148 #define AGEN2 47 // Address generation temporary register
149 #define MGEN1 48 // Maptable address generation temporary register
150 #define MGEN2 49 // Maptable address generation temporary register
151 #define BTREG 50 // Branch target temporary register
153 /* instruction types */
154 #define NOP 0 // No operation
155 #define LOAD 1 // Load
156 #define STORE 2 // Store
157 #define LOADLR 3 // Unaligned load
158 #define STORELR 4 // Unaligned store
159 #define MOV 5 // Move
160 #define ALU 6 // Arithmetic/logic
161 #define MULTDIV 7 // Multiply/divide
162 #define SHIFT 8 // Shift by register
163 #define SHIFTIMM 9// Shift by immediate
164 #define IMM16 10 // 16-bit immediate
165 #define RJUMP 11 // Unconditional jump to register
166 #define UJUMP 12 // Unconditional jump
167 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
168 #define SJUMP 14 // Conditional branch (regimm format)
169 #define COP0 15 // Coprocessor 0
170 #define COP1 16 // Coprocessor 1
171 #define C1LS 17 // Coprocessor 1 load/store
172 #define FJUMP 18 // Conditional branch (floating point)
173 #define FLOAT 19 // Floating point unit
174 #define FCONV 20 // Convert integer to float
175 #define FCOMP 21 // Floating point compare (sets FSREG)
176 #define SYSCALL 22// SYSCALL
177 #define OTHER 23 // Other
178 #define SPAN 24 // Branch/delay slot spans 2 pages
179 #define NI 25 // Not implemented
180 #define HLECALL 26// PCSX fake opcodes for HLE
181 #define COP2 27 // Coprocessor 2 move
182 #define C2LS 28 // Coprocessor 2 load/store
183 #define C2OP 29 // Coprocessor 2 operation
184 #define INTCALL 30// Call interpreter to handle rare corner cases
193 #define LOADBU_STUB 7
194 #define LOADHU_STUB 8
195 #define STOREB_STUB 9
196 #define STOREH_STUB 10
197 #define STOREW_STUB 11
198 #define STORED_STUB 12
199 #define STORELR_STUB 13
200 #define INVCODE_STUB 14
208 int new_recompile_block(int addr);
209 void *get_addr_ht(u_int vaddr);
210 void invalidate_block(u_int block);
211 void invalidate_addr(u_int addr);
212 void remove_hash(int vaddr);
215 void dyna_linker_ds();
217 void verify_code_vm();
218 void verify_code_ds();
221 void fp_exception_ds();
223 void jump_syscall_hle();
227 void new_dyna_leave();
232 void read_nomem_new();
233 void read_nomemb_new();
234 void read_nomemh_new();
235 void read_nomemd_new();
236 void write_nomem_new();
237 void write_nomemb_new();
238 void write_nomemh_new();
239 void write_nomemd_new();
240 void write_rdram_new();
241 void write_rdramb_new();
242 void write_rdramh_new();
243 void write_rdramd_new();
244 extern u_int memory_map[1048576];
246 // Needed by assembler
247 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
248 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
249 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
250 void load_all_regs(signed char i_regmap[]);
251 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
252 void load_regs_entry(int t);
253 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
257 //#define DEBUG_CYCLE_COUNT 1
260 //#define assem_debug printf
261 //#define inv_debug printf
262 #define assem_debug nullf
263 #define inv_debug nullf
265 static void tlb_hacks()
269 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
273 switch (ROM_HEADER->Country_code&0xFF)
285 // Unknown country code
289 u_int rom_addr=(u_int)rom;
291 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
292 // in the lower 4G of memory to use this hack. Copy it if necessary.
293 if((void *)rom>(void *)0xffffffff) {
294 munmap(ROM_COPY, 67108864);
295 if(mmap(ROM_COPY, 12582912,
296 PROT_READ | PROT_WRITE,
297 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
298 -1, 0) <= 0) {printf("mmap() failed\n");}
299 memcpy(ROM_COPY,rom,12582912);
300 rom_addr=(u_int)ROM_COPY;
304 for(n=0x7F000;n<0x80000;n++) {
305 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
312 static u_int get_page(u_int vaddr)
315 u_int page=(vaddr^0x80000000)>>12;
317 u_int page=vaddr&~0xe0000000;
318 if (page < 0x1000000)
319 page &= ~0x0e00000; // RAM mirrors
323 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
325 if(page>2048) page=2048+(page&2047);
329 static u_int get_vpage(u_int vaddr)
331 u_int vpage=(vaddr^0x80000000)>>12;
333 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
335 if(vpage>2048) vpage=2048+(vpage&2047);
339 // Get address from virtual address
340 // This is called from the recompiled JR/JALR instructions
341 void *get_addr(u_int vaddr)
343 u_int page=get_page(vaddr);
344 u_int vpage=get_vpage(vaddr);
345 struct ll_entry *head;
346 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
349 if(head->vaddr==vaddr&&head->reg32==0) {
350 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
351 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
354 ht_bin[1]=(int)head->addr;
360 head=jump_dirty[vpage];
362 if(head->vaddr==vaddr&&head->reg32==0) {
363 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
364 // Don't restore blocks which are about to expire from the cache
365 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
366 if(verify_dirty(head->addr)) {
367 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
368 invalid_code[vaddr>>12]=0;
369 memory_map[vaddr>>12]|=0x40000000;
372 if(tlb_LUT_r[vaddr>>12]) {
373 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
374 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
377 restore_candidate[vpage>>3]|=1<<(vpage&7);
379 else restore_candidate[page>>3]|=1<<(page&7);
380 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
381 if(ht_bin[0]==vaddr) {
382 ht_bin[1]=(int)head->addr; // Replace existing entry
388 ht_bin[1]=(int)head->addr;
396 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
397 int r=new_recompile_block(vaddr);
398 if(r==0) return get_addr(vaddr);
399 // Execute in unmapped page, generate pagefault execption
401 Cause=(vaddr<<31)|0x8;
402 EPC=(vaddr&1)?vaddr-5:vaddr;
404 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
405 EntryHi=BadVAddr&0xFFFFE000;
406 return get_addr_ht(0x80000000);
408 // Look up address in hash table first
409 void *get_addr_ht(u_int vaddr)
411 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
412 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
413 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
414 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
415 return get_addr(vaddr);
418 void *get_addr_32(u_int vaddr,u_int flags)
421 return get_addr(vaddr);
423 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
426 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
427 u_int page=get_page(vaddr);
428 u_int vpage=get_vpage(vaddr);
429 struct ll_entry *head;
432 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
433 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
437 ht_bin[1]=(int)head->addr;
439 }else if(ht_bin[2]==-1) {
440 ht_bin[3]=(int)head->addr;
443 //ht_bin[3]=ht_bin[1];
444 //ht_bin[2]=ht_bin[0];
445 //ht_bin[1]=(int)head->addr;
452 head=jump_dirty[vpage];
454 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
455 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
456 // Don't restore blocks which are about to expire from the cache
457 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
458 if(verify_dirty(head->addr)) {
459 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
460 invalid_code[vaddr>>12]=0;
461 memory_map[vaddr>>12]|=0x40000000;
464 if(tlb_LUT_r[vaddr>>12]) {
465 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
466 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
469 restore_candidate[vpage>>3]|=1<<(vpage&7);
471 else restore_candidate[page>>3]|=1<<(page&7);
473 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
475 ht_bin[1]=(int)head->addr;
477 }else if(ht_bin[2]==-1) {
478 ht_bin[3]=(int)head->addr;
481 //ht_bin[3]=ht_bin[1];
482 //ht_bin[2]=ht_bin[0];
483 //ht_bin[1]=(int)head->addr;
491 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
492 int r=new_recompile_block(vaddr);
493 if(r==0) return get_addr(vaddr);
494 // Execute in unmapped page, generate pagefault execption
496 Cause=(vaddr<<31)|0x8;
497 EPC=(vaddr&1)?vaddr-5:vaddr;
499 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
500 EntryHi=BadVAddr&0xFFFFE000;
501 return get_addr_ht(0x80000000);
505 void clear_all_regs(signed char regmap[])
508 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
511 signed char get_reg(signed char regmap[],int r)
514 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
518 // Find a register that is available for two consecutive cycles
519 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
522 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
526 int count_free_regs(signed char regmap[])
530 for(hr=0;hr<HOST_REGS;hr++)
532 if(hr!=EXCLUDE_REG) {
533 if(regmap[hr]<0) count++;
539 void dirty_reg(struct regstat *cur,signed char reg)
543 for (hr=0;hr<HOST_REGS;hr++) {
544 if((cur->regmap[hr]&63)==reg) {
550 // If we dirty the lower half of a 64 bit register which is now being
551 // sign-extended, we need to dump the upper half.
552 // Note: Do this only after completion of the instruction, because
553 // some instructions may need to read the full 64-bit value even if
554 // overwriting it (eg SLTI, DSRA32).
555 static void flush_dirty_uppers(struct regstat *cur)
558 for (hr=0;hr<HOST_REGS;hr++) {
559 if((cur->dirty>>hr)&1) {
562 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
567 void set_const(struct regstat *cur,signed char reg,uint64_t value)
571 for (hr=0;hr<HOST_REGS;hr++) {
572 if(cur->regmap[hr]==reg) {
574 cur->constmap[hr]=value;
576 else if((cur->regmap[hr]^64)==reg) {
578 cur->constmap[hr]=value>>32;
583 void clear_const(struct regstat *cur,signed char reg)
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 cur->isconst&=~(1<<hr);
594 int is_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 return (cur->isconst>>hr)&1;
605 uint64_t get_const(struct regstat *cur,signed char reg)
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if(cur->regmap[hr]==reg) {
611 return cur->constmap[hr];
614 printf("Unknown constant in r%d\n",reg);
618 // Least soon needed registers
619 // Look at the next ten instructions and see which registers
620 // will be used. Try not to reallocate these.
621 void lsn(u_char hsn[], int i, int *preferred_reg)
631 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
633 // Don't go past an unconditonal jump
640 if(rs1[i+j]) hsn[rs1[i+j]]=j;
641 if(rs2[i+j]) hsn[rs2[i+j]]=j;
642 if(rt1[i+j]) hsn[rt1[i+j]]=j;
643 if(rt2[i+j]) hsn[rt2[i+j]]=j;
644 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
645 // Stores can allocate zero
649 // On some architectures stores need invc_ptr
650 #if defined(HOST_IMM8)
651 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
655 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
663 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
665 // Follow first branch
666 int t=(ba[i+b]-start)>>2;
667 j=7-b;if(t+j>=slen) j=slen-t-1;
670 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
671 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
672 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
673 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
676 // TODO: preferred register based on backward branch
678 // Delay slot should preferably not overwrite branch conditions or cycle count
679 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
680 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
681 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
687 // Coprocessor load/store needs FTEMP, even if not declared
688 if(itype[i]==C1LS||itype[i]==C2LS) {
691 // Load L/R also uses FTEMP as a temporary register
692 if(itype[i]==LOADLR) {
695 // Also SWL/SWR/SDL/SDR
696 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
699 // Don't remove the TLB registers either
700 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
703 // Don't remove the miniht registers
704 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 // We only want to allocate registers if we're going to use them again soon
712 int needed_again(int r, int i)
718 u_char hsn[MAXREG+1];
721 memset(hsn,10,sizeof(hsn));
722 lsn(hsn,i,&preferred_reg);
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
737 // Don't go past an unconditonal jump
741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
761 // Follow first branch
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 for(hr=0;hr<HOST_REGS;hr++) {
776 if(hr!=EXCLUDE_REG) {
777 if(rn<hsn[hr]) return 1;
783 // Try to match register allocations at the end of a loop with those
785 int loop_reg(int i, int r, int hr)
794 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
796 // Don't go past an unconditonal jump
803 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
808 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
809 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
810 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
812 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
814 int t=(ba[i+k]-start)>>2;
815 int reg=get_reg(regs[t].regmap_entry,r);
816 if(reg>=0) return reg;
817 //reg=get_reg(regs[t+1].regmap_entry,r);
818 //if(reg>=0) return reg;
826 // Allocate every register, preserving source/target regs
827 void alloc_all(struct regstat *cur,int i)
831 for(hr=0;hr<HOST_REGS;hr++) {
832 if(hr!=EXCLUDE_REG) {
833 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
834 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
837 cur->dirty&=~(1<<hr);
840 if((cur->regmap[hr]&63)==0)
843 cur->dirty&=~(1<<hr);
850 void div64(int64_t dividend,int64_t divisor)
854 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
855 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
857 void divu64(uint64_t dividend,uint64_t divisor)
861 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
862 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
865 void mult64(uint64_t m1,uint64_t m2)
867 unsigned long long int op1, op2, op3, op4;
868 unsigned long long int result1, result2, result3, result4;
869 unsigned long long int temp1, temp2, temp3, temp4;
885 op1 = op2 & 0xFFFFFFFF;
886 op2 = (op2 >> 32) & 0xFFFFFFFF;
887 op3 = op4 & 0xFFFFFFFF;
888 op4 = (op4 >> 32) & 0xFFFFFFFF;
891 temp2 = (temp1 >> 32) + op1 * op4;
893 temp4 = (temp3 >> 32) + op2 * op4;
895 result1 = temp1 & 0xFFFFFFFF;
896 result2 = temp2 + (temp3 & 0xFFFFFFFF);
897 result3 = (result2 >> 32) + temp4;
898 result4 = (result3 >> 32);
900 lo = result1 | (result2 << 32);
901 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
910 void multu64(uint64_t m1,uint64_t m2)
912 unsigned long long int op1, op2, op3, op4;
913 unsigned long long int result1, result2, result3, result4;
914 unsigned long long int temp1, temp2, temp3, temp4;
916 op1 = m1 & 0xFFFFFFFF;
917 op2 = (m1 >> 32) & 0xFFFFFFFF;
918 op3 = m2 & 0xFFFFFFFF;
919 op4 = (m2 >> 32) & 0xFFFFFFFF;
922 temp2 = (temp1 >> 32) + op1 * op4;
924 temp4 = (temp3 >> 32) + op2 * op4;
926 result1 = temp1 & 0xFFFFFFFF;
927 result2 = temp2 + (temp3 & 0xFFFFFFFF);
928 result3 = (result2 >> 32) + temp4;
929 result4 = (result3 >> 32);
931 lo = result1 | (result2 << 32);
932 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
934 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
935 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
938 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
946 else original=loaded;
949 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
952 original>>=64-(bits^56);
953 original<<=64-(bits^56);
957 else original=loaded;
962 #include "assem_x86.c"
965 #include "assem_x64.c"
968 #include "assem_arm.c"
971 // Add virtual address mapping to linked list
972 void ll_add(struct ll_entry **head,int vaddr,void *addr)
974 struct ll_entry *new_entry;
975 new_entry=malloc(sizeof(struct ll_entry));
976 assert(new_entry!=NULL);
977 new_entry->vaddr=vaddr;
979 new_entry->addr=addr;
980 new_entry->next=*head;
984 // Add virtual address mapping for 32-bit compiled block
985 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
987 ll_add(head,vaddr,addr);
989 (*head)->reg32=reg32;
993 // Check if an address is already compiled
994 // but don't return addresses which are about to expire from the cache
995 void *check_addr(u_int vaddr)
997 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
998 if(ht_bin[0]==vaddr) {
999 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1002 if(ht_bin[2]==vaddr) {
1003 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1006 u_int page=get_page(vaddr);
1007 struct ll_entry *head;
1010 if(head->vaddr==vaddr&&head->reg32==0) {
1011 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1012 // Update existing entry with current address
1013 if(ht_bin[0]==vaddr) {
1014 ht_bin[1]=(int)head->addr;
1017 if(ht_bin[2]==vaddr) {
1018 ht_bin[3]=(int)head->addr;
1021 // Insert into hash table with low priority.
1022 // Don't evict existing entries, as they are probably
1023 // addresses that are being accessed frequently.
1025 ht_bin[1]=(int)head->addr;
1027 }else if(ht_bin[2]==-1) {
1028 ht_bin[3]=(int)head->addr;
1039 void remove_hash(int vaddr)
1041 //printf("remove hash: %x\n",vaddr);
1042 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1043 if(ht_bin[2]==vaddr) {
1044 ht_bin[2]=ht_bin[3]=-1;
1046 if(ht_bin[0]==vaddr) {
1047 ht_bin[0]=ht_bin[2];
1048 ht_bin[1]=ht_bin[3];
1049 ht_bin[2]=ht_bin[3]=-1;
1053 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1055 struct ll_entry *next;
1057 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1058 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1060 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1061 remove_hash((*head)->vaddr);
1068 head=&((*head)->next);
1073 // Remove all entries from linked list
1074 void ll_clear(struct ll_entry **head)
1076 struct ll_entry *cur;
1077 struct ll_entry *next;
1088 // Dereference the pointers and remove if it matches
1089 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1092 int ptr=get_pointer(head->addr);
1093 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1094 if(((ptr>>shift)==(addr>>shift)) ||
1095 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1097 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1098 u_int host_addr=(u_int)kill_pointer(head->addr);
1100 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1110 struct ll_entry *head;
1111 struct ll_entry *next;
1115 inv_debug("INVALIDATE: %x\n",head->vaddr);
1116 remove_hash(head->vaddr);
1121 head=jump_out[page];
1124 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1125 u_int host_addr=(u_int)kill_pointer(head->addr);
1127 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1134 void invalidate_block(u_int block)
1136 u_int page=get_page(block<<12);
1137 u_int vpage=get_vpage(block<<12);
1138 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1139 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1142 struct ll_entry *head;
1143 head=jump_dirty[vpage];
1144 //printf("page=%d vpage=%d\n",page,vpage);
1147 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1148 get_bounds((int)head->addr,&start,&end);
1149 //printf("start: %x end: %x\n",start,end);
1150 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1151 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1152 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1153 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1157 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1158 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1159 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1160 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1167 //printf("first=%d last=%d\n",first,last);
1168 invalidate_page(page);
1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1173 invalidate_page(first);
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1183 // Don't trap writes
1184 invalid_code[block]=1;
1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1199 memset(mini_ht,-1,sizeof(mini_ht));
1202 void invalidate_addr(u_int addr)
1204 invalidate_block(addr>>12);
1206 // This is called when loading a save state.
1207 // Anything could have changed, so invalidate everything.
1208 void invalidate_all_pages()
1211 for(page=0;page<4096;page++)
1212 invalidate_page(page);
1213 for(page=0;page<1048576;page++)
1214 if(!invalid_code[page]) {
1215 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1216 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1219 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1222 memset(mini_ht,-1,sizeof(mini_ht));
1226 for(page=0;page<0x100000;page++) {
1227 if(tlb_LUT_r[page]) {
1228 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1229 if(!tlb_LUT_w[page]||!invalid_code[page])
1230 memory_map[page]|=0x40000000; // Write protect
1232 else memory_map[page]=-1;
1233 if(page==0x80000) page=0xC0000;
1239 // Add an entry to jump_out after making a link
1240 void add_link(u_int vaddr,void *src)
1242 u_int page=get_page(vaddr);
1243 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1244 ll_add(jump_out+page,vaddr,src);
1245 //int ptr=get_pointer(src);
1246 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1249 // If a code block was found to be unmodified (bit was set in
1250 // restore_candidate) and it remains unmodified (bit is clear
1251 // in invalid_code) then move the entries for that 4K page from
1252 // the dirty list to the clean list.
1253 void clean_blocks(u_int page)
1255 struct ll_entry *head;
1256 inv_debug("INV: clean_blocks page=%d\n",page);
1257 head=jump_dirty[page];
1259 if(!invalid_code[head->vaddr>>12]) {
1260 // Don't restore blocks which are about to expire from the cache
1261 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1263 if(verify_dirty((int)head->addr)) {
1264 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1267 get_bounds((int)head->addr,&start,&end);
1268 if(start-(u_int)rdram<RAM_SIZE) {
1269 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1270 inv|=invalid_code[i];
1273 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1274 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1275 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1276 if(addr<start||addr>=end) inv=1;
1278 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1282 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1283 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1286 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1288 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1289 //printf("page=%x, addr=%x\n",page,head->vaddr);
1290 //assert(head->vaddr>>12==(page|0x80000));
1291 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1292 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1294 if(ht_bin[0]==head->vaddr) {
1295 ht_bin[1]=(int)clean_addr; // Replace existing entry
1297 if(ht_bin[2]==head->vaddr) {
1298 ht_bin[3]=(int)clean_addr; // Replace existing entry
1311 void mov_alloc(struct regstat *current,int i)
1313 // Note: Don't need to actually alloc the source registers
1314 if((~current->is32>>rs1[i])&1) {
1315 //alloc_reg64(current,i,rs1[i]);
1316 alloc_reg64(current,i,rt1[i]);
1317 current->is32&=~(1LL<<rt1[i]);
1319 //alloc_reg(current,i,rs1[i]);
1320 alloc_reg(current,i,rt1[i]);
1321 current->is32|=(1LL<<rt1[i]);
1323 clear_const(current,rs1[i]);
1324 clear_const(current,rt1[i]);
1325 dirty_reg(current,rt1[i]);
1328 void shiftimm_alloc(struct regstat *current,int i)
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1335 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1337 alloc_reg(current,i,rt1[i]);
1338 current->is32|=1LL<<rt1[i];
1339 dirty_reg(current,rt1[i]);
1342 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1345 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1346 alloc_reg64(current,i,rt1[i]);
1347 current->is32&=~(1LL<<rt1[i]);
1348 dirty_reg(current,rt1[i]);
1351 if(opcode2[i]==0x3c) // DSLL32
1354 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1355 alloc_reg64(current,i,rt1[i]);
1356 current->is32&=~(1LL<<rt1[i]);
1357 dirty_reg(current,rt1[i]);
1360 if(opcode2[i]==0x3e) // DSRL32
1363 alloc_reg64(current,i,rs1[i]);
1365 alloc_reg64(current,i,rt1[i]);
1366 current->is32&=~(1LL<<rt1[i]);
1368 alloc_reg(current,i,rt1[i]);
1369 current->is32|=1LL<<rt1[i];
1371 dirty_reg(current,rt1[i]);
1374 if(opcode2[i]==0x3f) // DSRA32
1377 alloc_reg64(current,i,rs1[i]);
1378 alloc_reg(current,i,rt1[i]);
1379 current->is32|=1LL<<rt1[i];
1380 dirty_reg(current,rt1[i]);
1385 void shift_alloc(struct regstat *current,int i)
1388 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1390 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1391 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1392 alloc_reg(current,i,rt1[i]);
1393 if(rt1[i]==rs2[i]) {
1394 alloc_reg_temp(current,i,-1);
1395 minimum_free_regs[i]=1;
1397 current->is32|=1LL<<rt1[i];
1398 } else { // DSLLV/DSRLV/DSRAV
1399 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1400 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1403 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1406 minimum_free_regs[i]=1;
1409 clear_const(current,rs1[i]);
1410 clear_const(current,rs2[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1416 void alu_alloc(struct regstat *current,int i)
1418 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1420 if(rs1[i]&&rs2[i]) {
1421 alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rs2[i]);
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1428 alloc_reg(current,i,rt1[i]);
1430 current->is32|=1LL<<rt1[i];
1432 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1434 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1440 alloc_reg(current,i,rs1[i]);
1441 alloc_reg(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1445 current->is32|=1LL<<rt1[i];
1447 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1449 if(rs1[i]&&rs2[i]) {
1450 alloc_reg(current,i,rs1[i]);
1451 alloc_reg(current,i,rs2[i]);
1455 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1456 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1458 alloc_reg(current,i,rt1[i]);
1459 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1461 if(!((current->uu>>rt1[i])&1)) {
1462 alloc_reg64(current,i,rt1[i]);
1464 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1465 if(rs1[i]&&rs2[i]) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1471 // Is is really worth it to keep 64-bit values in registers?
1473 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1474 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1478 current->is32&=~(1LL<<rt1[i]);
1480 current->is32|=1LL<<rt1[i];
1484 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1486 if(rs1[i]&&rs2[i]) {
1487 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1488 alloc_reg64(current,i,rs1[i]);
1489 alloc_reg64(current,i,rs2[i]);
1490 alloc_reg64(current,i,rt1[i]);
1492 alloc_reg(current,i,rs1[i]);
1493 alloc_reg(current,i,rs2[i]);
1494 alloc_reg(current,i,rt1[i]);
1498 alloc_reg(current,i,rt1[i]);
1499 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1500 // DADD used as move, or zeroing
1501 // If we have a 64-bit source, then make the target 64 bits too
1502 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1503 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1504 alloc_reg64(current,i,rt1[i]);
1505 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1506 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1507 alloc_reg64(current,i,rt1[i]);
1509 if(opcode2[i]>=0x2e&&rs2[i]) {
1510 // DSUB used as negation - 64-bit result
1511 // If we have a 32-bit register, extend it to 64 bits
1512 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1513 alloc_reg64(current,i,rt1[i]);
1517 if(rs1[i]&&rs2[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs1[i])&1)
1522 current->is32|=1LL<<rt1[i];
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs2[i])&1)
1526 current->is32|=1LL<<rt1[i];
1528 current->is32|=1LL<<rt1[i];
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1538 void imm16_alloc(struct regstat *current,int i)
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1542 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1543 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1544 current->is32&=~(1LL<<rt1[i]);
1545 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1546 // TODO: Could preserve the 32-bit flag if the immediate is zero
1547 alloc_reg64(current,i,rt1[i]);
1548 alloc_reg64(current,i,rs1[i]);
1550 clear_const(current,rs1[i]);
1551 clear_const(current,rt1[i]);
1553 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1554 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1555 current->is32|=1LL<<rt1[i];
1556 clear_const(current,rs1[i]);
1557 clear_const(current,rt1[i]);
1559 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1560 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1561 if(rs1[i]!=rt1[i]) {
1562 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1567 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1568 if(is_const(current,rs1[i])) {
1569 int v=get_const(current,rs1[i]);
1570 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1571 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1572 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1574 else clear_const(current,rt1[i]);
1576 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1577 if(is_const(current,rs1[i])) {
1578 int v=get_const(current,rs1[i]);
1579 set_const(current,rt1[i],v+imm[i]);
1581 else clear_const(current,rt1[i]);
1582 current->is32|=1LL<<rt1[i];
1585 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1586 current->is32|=1LL<<rt1[i];
1588 dirty_reg(current,rt1[i]);
1591 void load_alloc(struct regstat *current,int i)
1593 clear_const(current,rt1[i]);
1594 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1595 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1596 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1598 alloc_reg(current,i,rt1[i]);
1599 if(get_reg(current->regmap,rt1[i])<0) {
1600 // dummy load, but we still need a register to calculate the address
1601 alloc_reg_temp(current,i,-1);
1602 minimum_free_regs[i]=1;
1604 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1609 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1611 current->is32&=~(1LL<<rt1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 alloc_all(current,i);
1614 alloc_reg64(current,i,FTEMP);
1615 minimum_free_regs[i]=HOST_REGS;
1617 else current->is32|=1LL<<rt1[i];
1618 dirty_reg(current,rt1[i]);
1619 // If using TLB, need a register for pointer to the mapping table
1620 if(using_tlb) alloc_reg(current,i,TLREG);
1621 // LWL/LWR need a temporary register for the old value
1622 if(opcode[i]==0x22||opcode[i]==0x26)
1624 alloc_reg(current,i,FTEMP);
1625 alloc_reg_temp(current,i,-1);
1626 minimum_free_regs[i]=1;
1631 // Load to r0 (dummy load)
1632 // but we still need a register to calculate the address
1633 if(opcode[i]==0x22||opcode[i]==0x26)
1635 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1637 alloc_reg_temp(current,i,-1);
1638 minimum_free_regs[i]=1;
1639 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641 alloc_all(current,i);
1642 alloc_reg64(current,i,FTEMP);
1643 minimum_free_regs[i]=HOST_REGS;
1648 void store_alloc(struct regstat *current,int i)
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1665 alloc_reg(current,i,FTEMP);
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
1669 minimum_free_regs[i]=1;
1672 void c1ls_alloc(struct regstat *current,int i)
1674 //clear_const(current,rs1[i]); // FIXME
1675 clear_const(current,rt1[i]);
1676 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1677 alloc_reg(current,i,CSREG); // Status
1678 alloc_reg(current,i,FTEMP);
1679 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1680 alloc_reg64(current,i,FTEMP);
1682 // If using TLB, need a register for pointer to the mapping table
1683 if(using_tlb) alloc_reg(current,i,TLREG);
1684 #if defined(HOST_IMM8)
1685 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1686 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1687 alloc_reg(current,i,INVCP);
1689 // We need a temporary register for address generation
1690 alloc_reg_temp(current,i,-1);
1693 void c2ls_alloc(struct regstat *current,int i)
1695 clear_const(current,rt1[i]);
1696 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1697 alloc_reg(current,i,FTEMP);
1698 // If using TLB, need a register for pointer to the mapping table
1699 if(using_tlb) alloc_reg(current,i,TLREG);
1700 #if defined(HOST_IMM8)
1701 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1702 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1703 alloc_reg(current,i,INVCP);
1705 // We need a temporary register for address generation
1706 alloc_reg_temp(current,i,-1);
1707 minimum_free_regs[i]=1;
1710 #ifndef multdiv_alloc
1711 void multdiv_alloc(struct regstat *current,int i)
1718 // case 0x1D: DMULTU
1721 clear_const(current,rs1[i]);
1722 clear_const(current,rs2[i]);
1725 if((opcode2[i]&4)==0) // 32-bit
1727 current->u&=~(1LL<<HIREG);
1728 current->u&=~(1LL<<LOREG);
1729 alloc_reg(current,i,HIREG);
1730 alloc_reg(current,i,LOREG);
1731 alloc_reg(current,i,rs1[i]);
1732 alloc_reg(current,i,rs2[i]);
1733 current->is32|=1LL<<HIREG;
1734 current->is32|=1LL<<LOREG;
1735 dirty_reg(current,HIREG);
1736 dirty_reg(current,LOREG);
1740 current->u&=~(1LL<<HIREG);
1741 current->u&=~(1LL<<LOREG);
1742 current->uu&=~(1LL<<HIREG);
1743 current->uu&=~(1LL<<LOREG);
1744 alloc_reg64(current,i,HIREG);
1745 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1746 alloc_reg64(current,i,rs1[i]);
1747 alloc_reg64(current,i,rs2[i]);
1748 alloc_all(current,i);
1749 current->is32&=~(1LL<<HIREG);
1750 current->is32&=~(1LL<<LOREG);
1751 dirty_reg(current,HIREG);
1752 dirty_reg(current,LOREG);
1753 minimum_free_regs[i]=HOST_REGS;
1758 // Multiply by zero is zero.
1759 // MIPS does not have a divide by zero exception.
1760 // The result is undefined, we return zero.
1761 alloc_reg(current,i,HIREG);
1762 alloc_reg(current,i,LOREG);
1763 current->is32|=1LL<<HIREG;
1764 current->is32|=1LL<<LOREG;
1765 dirty_reg(current,HIREG);
1766 dirty_reg(current,LOREG);
1771 void cop0_alloc(struct regstat *current,int i)
1773 if(opcode2[i]==0) // MFC0
1776 clear_const(current,rt1[i]);
1777 alloc_all(current,i);
1778 alloc_reg(current,i,rt1[i]);
1779 current->is32|=1LL<<rt1[i];
1780 dirty_reg(current,rt1[i]);
1783 else if(opcode2[i]==4) // MTC0
1786 clear_const(current,rs1[i]);
1787 alloc_reg(current,i,rs1[i]);
1788 alloc_all(current,i);
1791 alloc_all(current,i); // FIXME: Keep r0
1793 alloc_reg(current,i,0);
1798 // TLBR/TLBWI/TLBWR/TLBP/ERET
1799 assert(opcode2[i]==0x10);
1800 alloc_all(current,i);
1802 minimum_free_regs[i]=HOST_REGS;
1805 void cop1_alloc(struct regstat *current,int i)
1807 alloc_reg(current,i,CSREG); // Load status
1808 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1811 clear_const(current,rt1[i]);
1813 alloc_reg64(current,i,rt1[i]); // DMFC1
1814 current->is32&=~(1LL<<rt1[i]);
1816 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1817 current->is32|=1LL<<rt1[i];
1819 dirty_reg(current,rt1[i]);
1821 alloc_reg_temp(current,i,-1);
1823 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1826 clear_const(current,rs1[i]);
1828 alloc_reg64(current,i,rs1[i]); // DMTC1
1830 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1831 alloc_reg_temp(current,i,-1);
1835 alloc_reg(current,i,0);
1836 alloc_reg_temp(current,i,-1);
1839 minimum_free_regs[i]=1;
1841 void fconv_alloc(struct regstat *current,int i)
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
1845 minimum_free_regs[i]=1;
1847 void float_alloc(struct regstat *current,int i)
1849 alloc_reg(current,i,CSREG); // Load status
1850 alloc_reg_temp(current,i,-1);
1851 minimum_free_regs[i]=1;
1853 void c2op_alloc(struct regstat *current,int i)
1855 alloc_reg_temp(current,i,-1);
1857 void fcomp_alloc(struct regstat *current,int i)
1859 alloc_reg(current,i,CSREG); // Load status
1860 alloc_reg(current,i,FSREG); // Load flags
1861 dirty_reg(current,FSREG); // Flag will be modified
1862 alloc_reg_temp(current,i,-1);
1863 minimum_free_regs[i]=1;
1866 void syscall_alloc(struct regstat *current,int i)
1868 alloc_cc(current,i);
1869 dirty_reg(current,CCREG);
1870 alloc_all(current,i);
1871 minimum_free_regs[i]=HOST_REGS;
1875 void delayslot_alloc(struct regstat *current,int i)
1886 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1887 printf("Disabled speculative precompilation\n");
1891 imm16_alloc(current,i);
1895 load_alloc(current,i);
1899 store_alloc(current,i);
1902 alu_alloc(current,i);
1905 shift_alloc(current,i);
1908 multdiv_alloc(current,i);
1911 shiftimm_alloc(current,i);
1914 mov_alloc(current,i);
1917 cop0_alloc(current,i);
1921 cop1_alloc(current,i);
1924 c1ls_alloc(current,i);
1927 c2ls_alloc(current,i);
1930 fconv_alloc(current,i);
1933 float_alloc(current,i);
1936 fcomp_alloc(current,i);
1939 c2op_alloc(current,i);
1944 // Special case where a branch and delay slot span two pages in virtual memory
1945 static void pagespan_alloc(struct regstat *current,int i)
1948 current->wasconst=0;
1950 minimum_free_regs[i]=HOST_REGS;
1951 alloc_all(current,i);
1952 alloc_cc(current,i);
1953 dirty_reg(current,CCREG);
1954 if(opcode[i]==3) // JAL
1956 alloc_reg(current,i,31);
1957 dirty_reg(current,31);
1959 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1961 alloc_reg(current,i,rs1[i]);
1963 alloc_reg(current,i,rt1[i]);
1964 dirty_reg(current,rt1[i]);
1967 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1969 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1970 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1971 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1978 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1980 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1981 if(!((current->is32>>rs1[i])&1))
1983 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1987 if(opcode[i]==0x11) // BC1
1989 alloc_reg(current,i,FSREG);
1990 alloc_reg(current,i,CSREG);
1995 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1997 stubs[stubcount][0]=type;
1998 stubs[stubcount][1]=addr;
1999 stubs[stubcount][2]=retaddr;
2000 stubs[stubcount][3]=a;
2001 stubs[stubcount][4]=b;
2002 stubs[stubcount][5]=c;
2003 stubs[stubcount][6]=d;
2004 stubs[stubcount][7]=e;
2008 // Write out a single register
2009 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2012 for(hr=0;hr<HOST_REGS;hr++) {
2013 if(hr!=EXCLUDE_REG) {
2014 if((regmap[hr]&63)==r) {
2017 emit_storereg(r,hr);
2019 if((is32>>regmap[hr])&1) {
2020 emit_sarimm(hr,31,hr);
2021 emit_storereg(r|64,hr);
2025 emit_storereg(r|64,hr);
2035 //if(!tracedebug) return 0;
2038 for(i=0;i<2097152;i++) {
2039 unsigned int temp=sum;
2042 sum^=((u_int *)rdram)[i];
2051 sum^=((u_int *)reg)[i];
2059 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2061 #ifndef DISABLE_COP1
2064 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2074 void memdebug(int i)
2076 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2077 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2080 //if(Count>=-2084597794) {
2081 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2083 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2084 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2085 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2088 printf("TRACE: %x\n",(&i)[-1]);
2092 printf("TRACE: %x \n",(&j)[10]);
2093 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2097 //printf("TRACE: %x\n",(&i)[-1]);
2100 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2102 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2105 void alu_assemble(int i,struct regstat *i_regs)
2107 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2109 signed char s1,s2,t;
2110 t=get_reg(i_regs->regmap,rt1[i]);
2112 s1=get_reg(i_regs->regmap,rs1[i]);
2113 s2=get_reg(i_regs->regmap,rs2[i]);
2114 if(rs1[i]&&rs2[i]) {
2117 if(opcode2[i]&2) emit_sub(s1,s2,t);
2118 else emit_add(s1,s2,t);
2121 if(s1>=0) emit_mov(s1,t);
2122 else emit_loadreg(rs1[i],t);
2126 if(opcode2[i]&2) emit_neg(s2,t);
2127 else emit_mov(s2,t);
2130 emit_loadreg(rs2[i],t);
2131 if(opcode2[i]&2) emit_neg(t,t);
2134 else emit_zeroreg(t);
2138 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2140 signed char s1l,s2l,s1h,s2h,tl,th;
2141 tl=get_reg(i_regs->regmap,rt1[i]);
2142 th=get_reg(i_regs->regmap,rt1[i]|64);
2144 s1l=get_reg(i_regs->regmap,rs1[i]);
2145 s2l=get_reg(i_regs->regmap,rs2[i]);
2146 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2147 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2148 if(rs1[i]&&rs2[i]) {
2151 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2152 else emit_adds(s1l,s2l,tl);
2154 #ifdef INVERTED_CARRY
2155 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2157 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2159 else emit_add(s1h,s2h,th);
2163 if(s1l>=0) emit_mov(s1l,tl);
2164 else emit_loadreg(rs1[i],tl);
2166 if(s1h>=0) emit_mov(s1h,th);
2167 else emit_loadreg(rs1[i]|64,th);
2172 if(opcode2[i]&2) emit_negs(s2l,tl);
2173 else emit_mov(s2l,tl);
2176 emit_loadreg(rs2[i],tl);
2177 if(opcode2[i]&2) emit_negs(tl,tl);
2180 #ifdef INVERTED_CARRY
2181 if(s2h>=0) emit_mov(s2h,th);
2182 else emit_loadreg(rs2[i]|64,th);
2184 emit_adcimm(-1,th); // x86 has inverted carry flag
2189 if(s2h>=0) emit_rscimm(s2h,0,th);
2191 emit_loadreg(rs2[i]|64,th);
2192 emit_rscimm(th,0,th);
2195 if(s2h>=0) emit_mov(s2h,th);
2196 else emit_loadreg(rs2[i]|64,th);
2203 if(th>=0) emit_zeroreg(th);
2208 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2210 signed char s1l,s1h,s2l,s2h,t;
2211 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2213 t=get_reg(i_regs->regmap,rt1[i]);
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2218 s2l=get_reg(i_regs->regmap,rs2[i]);
2219 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2220 if(rs2[i]==0) // rx<r0
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1h,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2228 else if(rs1[i]==0) // r0<rx
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz64_32(s2h,s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz64_32(s2h,s2l,t);
2237 assert(s1l>=0);assert(s1h>=0);
2238 assert(s2l>=0);assert(s2h>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2242 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2246 t=get_reg(i_regs->regmap,rt1[i]);
2249 s1l=get_reg(i_regs->regmap,rs1[i]);
2250 s2l=get_reg(i_regs->regmap,rs2[i]);
2251 if(rs2[i]==0) // rx<r0
2254 if(opcode2[i]==0x2a) // SLT
2255 emit_shrimm(s1l,31,t);
2256 else // SLTU (unsigned can not be less than zero)
2259 else if(rs1[i]==0) // r0<rx
2262 if(opcode2[i]==0x2a) // SLT
2263 emit_set_gz32(s2l,t);
2264 else // SLTU (set if not zero)
2265 emit_set_nz32(s2l,t);
2268 assert(s1l>=0);assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_if_less32(s1l,s2l,t);
2272 emit_set_if_carry32(s1l,s2l,t);
2278 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2280 signed char s1l,s1h,s2l,s2h,th,tl;
2281 tl=get_reg(i_regs->regmap,rt1[i]);
2282 th=get_reg(i_regs->regmap,rt1[i]|64);
2283 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2287 s1l=get_reg(i_regs->regmap,rs1[i]);
2288 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2289 s2l=get_reg(i_regs->regmap,rs2[i]);
2290 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2291 if(rs1[i]&&rs2[i]) {
2292 assert(s1l>=0);assert(s1h>=0);
2293 assert(s2l>=0);assert(s2h>=0);
2294 if(opcode2[i]==0x24) { // AND
2295 emit_and(s1l,s2l,tl);
2296 emit_and(s1h,s2h,th);
2298 if(opcode2[i]==0x25) { // OR
2299 emit_or(s1l,s2l,tl);
2300 emit_or(s1h,s2h,th);
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2304 emit_xor(s1h,s2h,th);
2306 if(opcode2[i]==0x27) { // NOR
2307 emit_or(s1l,s2l,tl);
2308 emit_or(s1h,s2h,th);
2315 if(opcode2[i]==0x24) { // AND
2319 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2321 if(s1l>=0) emit_mov(s1l,tl);
2322 else emit_loadreg(rs1[i],tl);
2323 if(s1h>=0) emit_mov(s1h,th);
2324 else emit_loadreg(rs1[i]|64,th);
2328 if(s2l>=0) emit_mov(s2l,tl);
2329 else emit_loadreg(rs2[i],tl);
2330 if(s2h>=0) emit_mov(s2h,th);
2331 else emit_loadreg(rs2[i]|64,th);
2338 if(opcode2[i]==0x27) { // NOR
2340 if(s1l>=0) emit_not(s1l,tl);
2342 emit_loadreg(rs1[i],tl);
2345 if(s1h>=0) emit_not(s1h,th);
2347 emit_loadreg(rs1[i]|64,th);
2353 if(s2l>=0) emit_not(s2l,tl);
2355 emit_loadreg(rs2[i],tl);
2358 if(s2h>=0) emit_not(s2h,th);
2360 emit_loadreg(rs2[i]|64,th);
2376 s1l=get_reg(i_regs->regmap,rs1[i]);
2377 s2l=get_reg(i_regs->regmap,rs2[i]);
2378 if(rs1[i]&&rs2[i]) {
2381 if(opcode2[i]==0x24) { // AND
2382 emit_and(s1l,s2l,tl);
2384 if(opcode2[i]==0x25) { // OR
2385 emit_or(s1l,s2l,tl);
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2390 if(opcode2[i]==0x27) { // NOR
2391 emit_or(s1l,s2l,tl);
2397 if(opcode2[i]==0x24) { // AND
2400 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2402 if(s1l>=0) emit_mov(s1l,tl);
2403 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2407 if(s2l>=0) emit_mov(s2l,tl);
2408 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2410 else emit_zeroreg(tl);
2412 if(opcode2[i]==0x27) { // NOR
2414 if(s1l>=0) emit_not(s1l,tl);
2416 emit_loadreg(rs1[i],tl);
2422 if(s2l>=0) emit_not(s2l,tl);
2424 emit_loadreg(rs2[i],tl);
2428 else emit_movimm(-1,tl);
2437 void imm16_assemble(int i,struct regstat *i_regs)
2439 if (opcode[i]==0x0f) { // LUI
2442 t=get_reg(i_regs->regmap,rt1[i]);
2445 if(!((i_regs->isconst>>t)&1))
2446 emit_movimm(imm[i]<<16,t);
2450 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2453 t=get_reg(i_regs->regmap,rt1[i]);
2454 s=get_reg(i_regs->regmap,rs1[i]);
2459 if(!((i_regs->isconst>>t)&1)) {
2461 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2462 emit_addimm(t,imm[i],t);
2464 if(!((i_regs->wasconst>>s)&1))
2465 emit_addimm(s,imm[i],t);
2467 emit_movimm(constmap[i][s]+imm[i],t);
2473 if(!((i_regs->isconst>>t)&1))
2474 emit_movimm(imm[i],t);
2479 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2481 signed char sh,sl,th,tl;
2482 th=get_reg(i_regs->regmap,rt1[i]|64);
2483 tl=get_reg(i_regs->regmap,rt1[i]);
2484 sh=get_reg(i_regs->regmap,rs1[i]|64);
2485 sl=get_reg(i_regs->regmap,rs1[i]);
2491 emit_addimm64_32(sh,sl,imm[i],th,tl);
2494 emit_addimm(sl,imm[i],tl);
2497 emit_movimm(imm[i],tl);
2498 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2503 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2505 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2506 signed char sh,sl,t;
2507 t=get_reg(i_regs->regmap,rt1[i]);
2508 sh=get_reg(i_regs->regmap,rs1[i]|64);
2509 sl=get_reg(i_regs->regmap,rs1[i]);
2513 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2514 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2515 if(opcode[i]==0x0a) { // SLTI
2517 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2518 emit_slti32(t,imm[i],t);
2520 emit_slti32(sl,imm[i],t);
2525 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2526 emit_sltiu32(t,imm[i],t);
2528 emit_sltiu32(sl,imm[i],t);
2533 if(opcode[i]==0x0a) // SLTI
2534 emit_slti64_32(sh,sl,imm[i],t);
2536 emit_sltiu64_32(sh,sl,imm[i],t);
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
2541 if(opcode[i]==0x0a) // SLTI
2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2553 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2555 signed char sh,sl,th,tl;
2556 th=get_reg(i_regs->regmap,rt1[i]|64);
2557 tl=get_reg(i_regs->regmap,rt1[i]);
2558 sh=get_reg(i_regs->regmap,rs1[i]|64);
2559 sl=get_reg(i_regs->regmap,rs1[i]);
2560 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2561 if(opcode[i]==0x0c) //ANDI
2565 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2566 emit_andimm(tl,imm[i],tl);
2568 if(!((i_regs->wasconst>>sl)&1))
2569 emit_andimm(sl,imm[i],tl);
2571 emit_movimm(constmap[i][sl]&imm[i],tl);
2576 if(th>=0) emit_zeroreg(th);
2582 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2586 emit_loadreg(rs1[i]|64,th);
2591 if(opcode[i]==0x0d) //ORI
2593 emit_orimm(tl,imm[i],tl);
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_orimm(sl,imm[i],tl);
2598 emit_movimm(constmap[i][sl]|imm[i],tl);
2600 if(opcode[i]==0x0e) //XORI
2602 emit_xorimm(tl,imm[i],tl);
2604 if(!((i_regs->wasconst>>sl)&1))
2605 emit_xorimm(sl,imm[i],tl);
2607 emit_movimm(constmap[i][sl]^imm[i],tl);
2611 emit_movimm(imm[i],tl);
2612 if(th>=0) emit_zeroreg(th);
2620 void shiftimm_assemble(int i,struct regstat *i_regs)
2622 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2626 t=get_reg(i_regs->regmap,rt1[i]);
2627 s=get_reg(i_regs->regmap,rs1[i]);
2636 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2638 if(opcode2[i]==0) // SLL
2640 emit_shlimm(s<0?t:s,imm[i],t);
2642 if(opcode2[i]==2) // SRL
2644 emit_shrimm(s<0?t:s,imm[i],t);
2646 if(opcode2[i]==3) // SRA
2648 emit_sarimm(s<0?t:s,imm[i],t);
2652 if(s>=0 && s!=t) emit_mov(s,t);
2656 //emit_storereg(rt1[i],t); //DEBUG
2659 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2662 signed char sh,sl,th,tl;
2663 th=get_reg(i_regs->regmap,rt1[i]|64);
2664 tl=get_reg(i_regs->regmap,rt1[i]);
2665 sh=get_reg(i_regs->regmap,rs1[i]|64);
2666 sl=get_reg(i_regs->regmap,rs1[i]);
2671 if(th>=0) emit_zeroreg(th);
2678 if(opcode2[i]==0x38) // DSLL
2680 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2681 emit_shlimm(sl,imm[i],tl);
2683 if(opcode2[i]==0x3a) // DSRL
2685 emit_shrdimm(sl,sh,imm[i],tl);
2686 if(th>=0) emit_shrimm(sh,imm[i],th);
2688 if(opcode2[i]==0x3b) // DSRA
2690 emit_shrdimm(sl,sh,imm[i],tl);
2691 if(th>=0) emit_sarimm(sh,imm[i],th);
2695 if(sl!=tl) emit_mov(sl,tl);
2696 if(th>=0&&sh!=th) emit_mov(sh,th);
2702 if(opcode2[i]==0x3c) // DSLL32
2705 signed char sl,tl,th;
2706 tl=get_reg(i_regs->regmap,rt1[i]);
2707 th=get_reg(i_regs->regmap,rt1[i]|64);
2708 sl=get_reg(i_regs->regmap,rs1[i]);
2717 emit_shlimm(th,imm[i]&31,th);
2722 if(opcode2[i]==0x3e) // DSRL32
2725 signed char sh,tl,th;
2726 tl=get_reg(i_regs->regmap,rt1[i]);
2727 th=get_reg(i_regs->regmap,rt1[i]|64);
2728 sh=get_reg(i_regs->regmap,rs1[i]|64);
2732 if(th>=0) emit_zeroreg(th);
2735 emit_shrimm(tl,imm[i]&31,tl);
2740 if(opcode2[i]==0x3f) // DSRA32
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 sh=get_reg(i_regs->regmap,rs1[i]|64);
2751 emit_sarimm(tl,imm[i]&31,tl);
2758 #ifndef shift_assemble
2759 void shift_assemble(int i,struct regstat *i_regs)
2761 printf("Need shift_assemble for this architecture.\n");
2766 void load_assemble(int i,struct regstat *i_regs)
2768 int s,th,tl,addr,map=-1;
2771 int memtarget=0,c=0;
2773 th=get_reg(i_regs->regmap,rt1[i]|64);
2774 tl=get_reg(i_regs->regmap,rt1[i]);
2775 s=get_reg(i_regs->regmap,rs1[i]);
2777 for(hr=0;hr<HOST_REGS;hr++) {
2778 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2780 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2782 c=(i_regs->wasconst>>s)&1;
2783 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2784 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2792 // could be FIFO, must perform the read
2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2799 if(offset||s<0||c) addr=tl;
2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2807 if(th>=0) reglist&=~(1<<th);
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2814 //#define R29_HACK 1
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2820 emit_cmpimm(addr,RAM_SIZE);
2822 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2823 // Hint to branch predictor that the branch is unlikely to be taken
2825 emit_jno_unlikely(0);
2833 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2834 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2835 map=get_reg(i_regs->regmap,TLREG);
2837 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2838 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2840 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2841 if (opcode[i]==0x20) { // LB
2844 #ifdef HOST_IMM_ADDR32
2846 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2850 //emit_xorimm(addr,3,tl);
2851 //gen_tlb_addr_r(tl,map);
2852 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2854 #ifdef BIG_ENDIAN_MIPS
2855 if(!c) emit_xorimm(addr,3,tl);
2856 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2860 emit_movsbl_indexed_tlb(x,a,map,tl);
2864 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2867 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2869 if (opcode[i]==0x21) { // LH
2872 #ifdef HOST_IMM_ADDR32
2874 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2879 #ifdef BIG_ENDIAN_MIPS
2880 if(!c) emit_xorimm(addr,2,tl);
2881 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2886 //emit_movswl_indexed_tlb(x,tl,map,tl);
2889 gen_tlb_addr_r(a,map);
2890 emit_movswl_indexed(x,a,tl);
2893 emit_movswl_indexed(x,a,tl);
2895 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2901 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2904 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2906 if (opcode[i]==0x23) { // LW
2909 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2910 #ifdef HOST_IMM_ADDR32
2912 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2915 emit_readword_indexed_tlb(0,addr,map,tl);
2918 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2921 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2923 if (opcode[i]==0x24) { // LBU
2926 #ifdef HOST_IMM_ADDR32
2928 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2932 //emit_xorimm(addr,3,tl);
2933 //gen_tlb_addr_r(tl,map);
2934 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2936 #ifdef BIG_ENDIAN_MIPS
2937 if(!c) emit_xorimm(addr,3,tl);
2938 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2942 emit_movzbl_indexed_tlb(x,a,map,tl);
2946 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2949 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951 if (opcode[i]==0x25) { // LHU
2954 #ifdef HOST_IMM_ADDR32
2956 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2961 #ifdef BIG_ENDIAN_MIPS
2962 if(!c) emit_xorimm(addr,2,tl);
2963 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2968 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2971 gen_tlb_addr_r(a,map);
2972 emit_movzwl_indexed(x,a,tl);
2975 emit_movzwl_indexed(x,a,tl);
2977 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2983 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2988 if (opcode[i]==0x27) { // LWU
2992 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2993 #ifdef HOST_IMM_ADDR32
2995 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2998 emit_readword_indexed_tlb(0,addr,map,tl);
3001 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3004 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008 if (opcode[i]==0x37) { // LD
3011 //gen_tlb_addr_r(tl,map);
3012 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3013 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3014 #ifdef HOST_IMM_ADDR32
3016 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3019 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3022 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3025 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3028 //emit_storereg(rt1[i],tl); // DEBUG
3029 //if(opcode[i]==0x23)
3030 //if(opcode[i]==0x24)
3031 //if(opcode[i]==0x23||opcode[i]==0x24)
3032 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3036 emit_readword((int)&last_count,ECX);
3038 if(get_reg(i_regs->regmap,CCREG)<0)
3039 emit_loadreg(CCREG,HOST_CCREG);
3040 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3041 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3042 emit_writeword(HOST_CCREG,(int)&Count);
3045 if(get_reg(i_regs->regmap,CCREG)<0)
3046 emit_loadreg(CCREG,0);
3048 emit_mov(HOST_CCREG,0);
3050 emit_addimm(0,2*ccadj[i],0);
3051 emit_writeword(0,(int)&Count);
3053 emit_call((int)memdebug);
3055 restore_regs(0x100f);
3059 #ifndef loadlr_assemble
3060 void loadlr_assemble(int i,struct regstat *i_regs)
3062 printf("Need loadlr_assemble for this architecture.\n");
3067 void store_assemble(int i,struct regstat *i_regs)
3072 int jaddr=0,jaddr2,type;
3073 int memtarget=0,c=0;
3074 int agr=AGEN1+(i&1);
3076 th=get_reg(i_regs->regmap,rs2[i]|64);
3077 tl=get_reg(i_regs->regmap,rs2[i]);
3078 s=get_reg(i_regs->regmap,rs1[i]);
3079 temp=get_reg(i_regs->regmap,agr);
3080 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3083 c=(i_regs->wasconst>>s)&1;
3084 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3085 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3089 for(hr=0;hr<HOST_REGS;hr++) {
3090 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3092 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3093 if(offset||s<0||c) addr=temp;
3098 // Strmnnrmn's speed hack
3100 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3102 emit_cmpimm(addr,RAM_SIZE);
3103 #ifdef DESTRUCTIVE_SHIFT
3104 if(s==addr) emit_mov(s,temp);
3107 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3111 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3112 // Hint to branch predictor that the branch is unlikely to be taken
3114 emit_jno_unlikely(0);
3122 if (opcode[i]==0x28) x=3; // SB
3123 if (opcode[i]==0x29) x=2; // SH
3124 map=get_reg(i_regs->regmap,TLREG);
3126 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3127 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3130 if (opcode[i]==0x28) { // SB
3133 #ifdef BIG_ENDIAN_MIPS
3134 if(!c) emit_xorimm(addr,3,temp);
3135 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3139 //gen_tlb_addr_w(temp,map);
3140 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3141 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3145 if (opcode[i]==0x29) { // SH
3148 #ifdef BIG_ENDIAN_MIPS
3149 if(!c) emit_xorimm(addr,2,temp);
3150 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3155 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3158 gen_tlb_addr_w(a,map);
3159 emit_writehword_indexed(tl,x,a);
3161 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3165 if (opcode[i]==0x2B) { // SW
3167 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3171 if (opcode[i]==0x3F) { // SD
3175 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3180 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3201 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3202 emit_callne(invalidate_addr_reg[addr]);
3206 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3211 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3212 } else if(c&&!memtarget) {
3213 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3215 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3216 //if(opcode[i]==0x2B || opcode[i]==0x28)
3217 //if(opcode[i]==0x2B || opcode[i]==0x29)
3218 //if(opcode[i]==0x2B)
3219 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3223 emit_readword((int)&last_count,ECX);
3225 if(get_reg(i_regs->regmap,CCREG)<0)
3226 emit_loadreg(CCREG,HOST_CCREG);
3227 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3228 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3229 emit_writeword(HOST_CCREG,(int)&Count);
3232 if(get_reg(i_regs->regmap,CCREG)<0)
3233 emit_loadreg(CCREG,0);
3235 emit_mov(HOST_CCREG,0);
3237 emit_addimm(0,2*ccadj[i],0);
3238 emit_writeword(0,(int)&Count);
3240 emit_call((int)memdebug);
3242 restore_regs(0x100f);
3246 void storelr_assemble(int i,struct regstat *i_regs)
3253 int case1,case2,case3;
3254 int done0,done1,done2;
3256 int agr=AGEN1+(i&1);
3258 th=get_reg(i_regs->regmap,rs2[i]|64);
3259 tl=get_reg(i_regs->regmap,rs2[i]);
3260 s=get_reg(i_regs->regmap,rs1[i]);
3261 temp=get_reg(i_regs->regmap,agr);
3262 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3265 c=(i_regs->isconst>>s)&1;
3266 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3267 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3270 for(hr=0;hr<HOST_REGS;hr++) {
3271 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3276 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3277 if(!offset&&s!=temp) emit_mov(s,temp);
3283 if(!memtarget||!rs1[i]) {
3289 int map=get_reg(i_regs->regmap,ROREG);
3290 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3291 gen_tlb_addr_w(temp,map);
3293 if((u_int)rdram!=0x80000000)
3294 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3297 int map=get_reg(i_regs->regmap,TLREG);
3299 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3300 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3301 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3302 if(!jaddr&&!memtarget) {
3306 gen_tlb_addr_w(temp,map);
3309 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3310 temp2=get_reg(i_regs->regmap,FTEMP);
3311 if(!rs2[i]) temp2=th=tl;
3314 #ifndef BIG_ENDIAN_MIPS
3315 emit_xorimm(temp,3,temp);
3317 emit_testimm(temp,2);
3320 emit_testimm(temp,1);
3324 if (opcode[i]==0x2A) { // SWL
3325 emit_writeword_indexed(tl,0,temp);
3327 if (opcode[i]==0x2E) { // SWR
3328 emit_writebyte_indexed(tl,3,temp);
3330 if (opcode[i]==0x2C) { // SDL
3331 emit_writeword_indexed(th,0,temp);
3332 if(rs2[i]) emit_mov(tl,temp2);
3334 if (opcode[i]==0x2D) { // SDR
3335 emit_writebyte_indexed(tl,3,temp);
3336 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3341 set_jump_target(case1,(int)out);
3342 if (opcode[i]==0x2A) { // SWL
3343 // Write 3 msb into three least significant bytes
3344 if(rs2[i]) emit_rorimm(tl,8,tl);
3345 emit_writehword_indexed(tl,-1,temp);
3346 if(rs2[i]) emit_rorimm(tl,16,tl);
3347 emit_writebyte_indexed(tl,1,temp);
3348 if(rs2[i]) emit_rorimm(tl,8,tl);
3350 if (opcode[i]==0x2E) { // SWR
3351 // Write two lsb into two most significant bytes
3352 emit_writehword_indexed(tl,1,temp);
3354 if (opcode[i]==0x2C) { // SDL
3355 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3356 // Write 3 msb into three least significant bytes
3357 if(rs2[i]) emit_rorimm(th,8,th);
3358 emit_writehword_indexed(th,-1,temp);
3359 if(rs2[i]) emit_rorimm(th,16,th);
3360 emit_writebyte_indexed(th,1,temp);
3361 if(rs2[i]) emit_rorimm(th,8,th);
3363 if (opcode[i]==0x2D) { // SDR
3364 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3365 // Write two lsb into two most significant bytes
3366 emit_writehword_indexed(tl,1,temp);
3371 set_jump_target(case2,(int)out);
3372 emit_testimm(temp,1);
3375 if (opcode[i]==0x2A) { // SWL
3376 // Write two msb into two least significant bytes
3377 if(rs2[i]) emit_rorimm(tl,16,tl);
3378 emit_writehword_indexed(tl,-2,temp);
3379 if(rs2[i]) emit_rorimm(tl,16,tl);