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drc: rm unneeded writebacks in stubs, as suggested by Ari64
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
619e5ded 137#define MMREG 38 // Pointer to memory_map
138#define ROREG 39 // ram offset (if rdram!=0x80000000)
139#define TEMPREG 40
140#define FTEMP 40 // FPU temporary register
141#define PTEMP 41 // Prefetch temporary register
142#define TLREG 42 // TLB mapping offset
143#define RHASH 43 // Return address hash
144#define RHTBL 44 // Return address hash table address
145#define RTEMP 45 // JR/JALR address register
146#define MAXREG 45
147#define AGEN1 46 // Address generation temporary register
148#define AGEN2 47 // Address generation temporary register
149#define MGEN1 48 // Maptable address generation temporary register
150#define MGEN2 49 // Maptable address generation temporary register
151#define BTREG 50 // Branch target temporary register
57871462 152
153 /* instruction types */
154#define NOP 0 // No operation
155#define LOAD 1 // Load
156#define STORE 2 // Store
157#define LOADLR 3 // Unaligned load
158#define STORELR 4 // Unaligned store
159#define MOV 5 // Move
160#define ALU 6 // Arithmetic/logic
161#define MULTDIV 7 // Multiply/divide
162#define SHIFT 8 // Shift by register
163#define SHIFTIMM 9// Shift by immediate
164#define IMM16 10 // 16-bit immediate
165#define RJUMP 11 // Unconditional jump to register
166#define UJUMP 12 // Unconditional jump
167#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
168#define SJUMP 14 // Conditional branch (regimm format)
169#define COP0 15 // Coprocessor 0
170#define COP1 16 // Coprocessor 1
171#define C1LS 17 // Coprocessor 1 load/store
172#define FJUMP 18 // Conditional branch (floating point)
173#define FLOAT 19 // Floating point unit
174#define FCONV 20 // Convert integer to float
175#define FCOMP 21 // Floating point compare (sets FSREG)
176#define SYSCALL 22// SYSCALL
177#define OTHER 23 // Other
178#define SPAN 24 // Branch/delay slot spans 2 pages
179#define NI 25 // Not implemented
7139f3c8 180#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 181#define COP2 27 // Coprocessor 2 move
182#define C2LS 28 // Coprocessor 2 load/store
183#define C2OP 29 // Coprocessor 2 operation
1e973cb0 184#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 185
186 /* stubs */
187#define CC_STUB 1
188#define FP_STUB 2
189#define LOADB_STUB 3
190#define LOADH_STUB 4
191#define LOADW_STUB 5
192#define LOADD_STUB 6
193#define LOADBU_STUB 7
194#define LOADHU_STUB 8
195#define STOREB_STUB 9
196#define STOREH_STUB 10
197#define STOREW_STUB 11
198#define STORED_STUB 12
199#define STORELR_STUB 13
200#define INVCODE_STUB 14
201
202 /* branch codes */
203#define TAKEN 1
204#define NOTTAKEN 2
205#define NULLDS 3
206
207// asm linkage
208int new_recompile_block(int addr);
209void *get_addr_ht(u_int vaddr);
210void invalidate_block(u_int block);
211void invalidate_addr(u_int addr);
212void remove_hash(int vaddr);
213void jump_vaddr();
214void dyna_linker();
215void dyna_linker_ds();
216void verify_code();
217void verify_code_vm();
218void verify_code_ds();
219void cc_interrupt();
220void fp_exception();
221void fp_exception_ds();
222void jump_syscall();
7139f3c8 223void jump_syscall_hle();
57871462 224void jump_eret();
7139f3c8 225void jump_hlecall();
1e973cb0 226void jump_intcall();
7139f3c8 227void new_dyna_leave();
57871462 228
229// TLB
230void TLBWI_new();
231void TLBWR_new();
232void read_nomem_new();
233void read_nomemb_new();
234void read_nomemh_new();
235void read_nomemd_new();
236void write_nomem_new();
237void write_nomemb_new();
238void write_nomemh_new();
239void write_nomemd_new();
240void write_rdram_new();
241void write_rdramb_new();
242void write_rdramh_new();
243void write_rdramd_new();
244extern u_int memory_map[1048576];
245
246// Needed by assembler
247void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
248void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
249void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
250void load_all_regs(signed char i_regmap[]);
251void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
252void load_regs_entry(int t);
253void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
254
255int tracedebug=0;
256
257//#define DEBUG_CYCLE_COUNT 1
258
259void nullf() {}
260//#define assem_debug printf
261//#define inv_debug printf
262#define assem_debug nullf
263#define inv_debug nullf
264
94d23bb9 265static void tlb_hacks()
57871462 266{
94d23bb9 267#ifndef DISABLE_TLB
57871462 268 // Goldeneye hack
269 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
270 {
271 u_int addr;
272 int n;
273 switch (ROM_HEADER->Country_code&0xFF)
274 {
275 case 0x45: // U
276 addr=0x34b30;
277 break;
278 case 0x4A: // J
279 addr=0x34b70;
280 break;
281 case 0x50: // E
282 addr=0x329f0;
283 break;
284 default:
285 // Unknown country code
286 addr=0;
287 break;
288 }
289 u_int rom_addr=(u_int)rom;
290 #ifdef ROM_COPY
291 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
292 // in the lower 4G of memory to use this hack. Copy it if necessary.
293 if((void *)rom>(void *)0xffffffff) {
294 munmap(ROM_COPY, 67108864);
295 if(mmap(ROM_COPY, 12582912,
296 PROT_READ | PROT_WRITE,
297 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
298 -1, 0) <= 0) {printf("mmap() failed\n");}
299 memcpy(ROM_COPY,rom,12582912);
300 rom_addr=(u_int)ROM_COPY;
301 }
302 #endif
303 if(addr) {
304 for(n=0x7F000;n<0x80000;n++) {
305 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
306 }
307 }
308 }
94d23bb9 309#endif
57871462 310}
311
94d23bb9 312static u_int get_page(u_int vaddr)
57871462 313{
0ce47d46 314#ifndef PCSX
57871462 315 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 316#else
317 u_int page=vaddr&~0xe0000000;
318 if (page < 0x1000000)
319 page &= ~0x0e00000; // RAM mirrors
320 page>>=12;
321#endif
94d23bb9 322#ifndef DISABLE_TLB
57871462 323 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 324#endif
57871462 325 if(page>2048) page=2048+(page&2047);
94d23bb9 326 return page;
327}
328
329static u_int get_vpage(u_int vaddr)
330{
331 u_int vpage=(vaddr^0x80000000)>>12;
332#ifndef DISABLE_TLB
57871462 333 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 334#endif
57871462 335 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 336 return vpage;
337}
338
339// Get address from virtual address
340// This is called from the recompiled JR/JALR instructions
341void *get_addr(u_int vaddr)
342{
343 u_int page=get_page(vaddr);
344 u_int vpage=get_vpage(vaddr);
57871462 345 struct ll_entry *head;
346 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
347 head=jump_in[page];
348 while(head!=NULL) {
349 if(head->vaddr==vaddr&&head->reg32==0) {
350 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
351 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
352 ht_bin[3]=ht_bin[1];
353 ht_bin[2]=ht_bin[0];
354 ht_bin[1]=(int)head->addr;
355 ht_bin[0]=vaddr;
356 return head->addr;
357 }
358 head=head->next;
359 }
360 head=jump_dirty[vpage];
361 while(head!=NULL) {
362 if(head->vaddr==vaddr&&head->reg32==0) {
363 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
364 // Don't restore blocks which are about to expire from the cache
365 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
366 if(verify_dirty(head->addr)) {
367 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
368 invalid_code[vaddr>>12]=0;
369 memory_map[vaddr>>12]|=0x40000000;
370 if(vpage<2048) {
94d23bb9 371#ifndef DISABLE_TLB
57871462 372 if(tlb_LUT_r[vaddr>>12]) {
373 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
374 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
375 }
94d23bb9 376#endif
57871462 377 restore_candidate[vpage>>3]|=1<<(vpage&7);
378 }
379 else restore_candidate[page>>3]|=1<<(page&7);
380 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
381 if(ht_bin[0]==vaddr) {
382 ht_bin[1]=(int)head->addr; // Replace existing entry
383 }
384 else
385 {
386 ht_bin[3]=ht_bin[1];
387 ht_bin[2]=ht_bin[0];
388 ht_bin[1]=(int)head->addr;
389 ht_bin[0]=vaddr;
390 }
391 return head->addr;
392 }
393 }
394 head=head->next;
395 }
396 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
397 int r=new_recompile_block(vaddr);
398 if(r==0) return get_addr(vaddr);
399 // Execute in unmapped page, generate pagefault execption
400 Status|=2;
401 Cause=(vaddr<<31)|0x8;
402 EPC=(vaddr&1)?vaddr-5:vaddr;
403 BadVAddr=(vaddr&~1);
404 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
405 EntryHi=BadVAddr&0xFFFFE000;
406 return get_addr_ht(0x80000000);
407}
408// Look up address in hash table first
409void *get_addr_ht(u_int vaddr)
410{
411 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
412 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
413 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
414 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
415 return get_addr(vaddr);
416}
417
418void *get_addr_32(u_int vaddr,u_int flags)
419{
7139f3c8 420#ifdef FORCE32
421 return get_addr(vaddr);
560e4a12 422#else
57871462 423 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
426 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 427 u_int page=get_page(vaddr);
428 u_int vpage=get_vpage(vaddr);
57871462 429 struct ll_entry *head;
430 head=jump_in[page];
431 while(head!=NULL) {
432 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
433 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
434 if(head->reg32==0) {
435 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
436 if(ht_bin[0]==-1) {
437 ht_bin[1]=(int)head->addr;
438 ht_bin[0]=vaddr;
439 }else if(ht_bin[2]==-1) {
440 ht_bin[3]=(int)head->addr;
441 ht_bin[2]=vaddr;
442 }
443 //ht_bin[3]=ht_bin[1];
444 //ht_bin[2]=ht_bin[0];
445 //ht_bin[1]=(int)head->addr;
446 //ht_bin[0]=vaddr;
447 }
448 return head->addr;
449 }
450 head=head->next;
451 }
452 head=jump_dirty[vpage];
453 while(head!=NULL) {
454 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
455 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
456 // Don't restore blocks which are about to expire from the cache
457 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
458 if(verify_dirty(head->addr)) {
459 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
460 invalid_code[vaddr>>12]=0;
461 memory_map[vaddr>>12]|=0x40000000;
462 if(vpage<2048) {
94d23bb9 463#ifndef DISABLE_TLB
57871462 464 if(tlb_LUT_r[vaddr>>12]) {
465 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
466 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
467 }
94d23bb9 468#endif
57871462 469 restore_candidate[vpage>>3]|=1<<(vpage&7);
470 }
471 else restore_candidate[page>>3]|=1<<(page&7);
472 if(head->reg32==0) {
473 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
474 if(ht_bin[0]==-1) {
475 ht_bin[1]=(int)head->addr;
476 ht_bin[0]=vaddr;
477 }else if(ht_bin[2]==-1) {
478 ht_bin[3]=(int)head->addr;
479 ht_bin[2]=vaddr;
480 }
481 //ht_bin[3]=ht_bin[1];
482 //ht_bin[2]=ht_bin[0];
483 //ht_bin[1]=(int)head->addr;
484 //ht_bin[0]=vaddr;
485 }
486 return head->addr;
487 }
488 }
489 head=head->next;
490 }
491 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
492 int r=new_recompile_block(vaddr);
493 if(r==0) return get_addr(vaddr);
494 // Execute in unmapped page, generate pagefault execption
495 Status|=2;
496 Cause=(vaddr<<31)|0x8;
497 EPC=(vaddr&1)?vaddr-5:vaddr;
498 BadVAddr=(vaddr&~1);
499 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
500 EntryHi=BadVAddr&0xFFFFE000;
501 return get_addr_ht(0x80000000);
560e4a12 502#endif
57871462 503}
504
505void clear_all_regs(signed char regmap[])
506{
507 int hr;
508 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
509}
510
511signed char get_reg(signed char regmap[],int r)
512{
513 int hr;
514 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
515 return -1;
516}
517
518// Find a register that is available for two consecutive cycles
519signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
520{
521 int hr;
522 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
523 return -1;
524}
525
526int count_free_regs(signed char regmap[])
527{
528 int count=0;
529 int hr;
530 for(hr=0;hr<HOST_REGS;hr++)
531 {
532 if(hr!=EXCLUDE_REG) {
533 if(regmap[hr]<0) count++;
534 }
535 }
536 return count;
537}
538
539void dirty_reg(struct regstat *cur,signed char reg)
540{
541 int hr;
542 if(!reg) return;
543 for (hr=0;hr<HOST_REGS;hr++) {
544 if((cur->regmap[hr]&63)==reg) {
545 cur->dirty|=1<<hr;
546 }
547 }
548}
549
550// If we dirty the lower half of a 64 bit register which is now being
551// sign-extended, we need to dump the upper half.
552// Note: Do this only after completion of the instruction, because
553// some instructions may need to read the full 64-bit value even if
554// overwriting it (eg SLTI, DSRA32).
555static void flush_dirty_uppers(struct regstat *cur)
556{
557 int hr,reg;
558 for (hr=0;hr<HOST_REGS;hr++) {
559 if((cur->dirty>>hr)&1) {
560 reg=cur->regmap[hr];
561 if(reg>=64)
562 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
563 }
564 }
565}
566
567void set_const(struct regstat *cur,signed char reg,uint64_t value)
568{
569 int hr;
570 if(!reg) return;
571 for (hr=0;hr<HOST_REGS;hr++) {
572 if(cur->regmap[hr]==reg) {
573 cur->isconst|=1<<hr;
574 cur->constmap[hr]=value;
575 }
576 else if((cur->regmap[hr]^64)==reg) {
577 cur->isconst|=1<<hr;
578 cur->constmap[hr]=value>>32;
579 }
580 }
581}
582
583void clear_const(struct regstat *cur,signed char reg)
584{
585 int hr;
586 if(!reg) return;
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 cur->isconst&=~(1<<hr);
590 }
591 }
592}
593
594int is_const(struct regstat *cur,signed char reg)
595{
596 int hr;
597 if(!reg) return 1;
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 return (cur->isconst>>hr)&1;
601 }
602 }
603 return 0;
604}
605uint64_t get_const(struct regstat *cur,signed char reg)
606{
607 int hr;
608 if(!reg) return 0;
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if(cur->regmap[hr]==reg) {
611 return cur->constmap[hr];
612 }
613 }
614 printf("Unknown constant in r%d\n",reg);
615 exit(1);
616}
617
618// Least soon needed registers
619// Look at the next ten instructions and see which registers
620// will be used. Try not to reallocate these.
621void lsn(u_char hsn[], int i, int *preferred_reg)
622{
623 int j;
624 int b=-1;
625 for(j=0;j<9;j++)
626 {
627 if(i+j>=slen) {
628 j=slen-i-1;
629 break;
630 }
631 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
632 {
633 // Don't go past an unconditonal jump
634 j++;
635 break;
636 }
637 }
638 for(;j>=0;j--)
639 {
640 if(rs1[i+j]) hsn[rs1[i+j]]=j;
641 if(rs2[i+j]) hsn[rs2[i+j]]=j;
642 if(rt1[i+j]) hsn[rt1[i+j]]=j;
643 if(rt2[i+j]) hsn[rt2[i+j]]=j;
644 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
645 // Stores can allocate zero
646 hsn[rs1[i+j]]=j;
647 hsn[rs2[i+j]]=j;
648 }
649 // On some architectures stores need invc_ptr
650 #if defined(HOST_IMM8)
b9b61529 651 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 652 hsn[INVCP]=j;
653 }
654 #endif
655 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
656 {
657 hsn[CCREG]=j;
658 b=j;
659 }
660 }
661 if(b>=0)
662 {
663 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
664 {
665 // Follow first branch
666 int t=(ba[i+b]-start)>>2;
667 j=7-b;if(t+j>=slen) j=slen-t-1;
668 for(;j>=0;j--)
669 {
670 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
671 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
672 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
673 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
674 }
675 }
676 // TODO: preferred register based on backward branch
677 }
678 // Delay slot should preferably not overwrite branch conditions or cycle count
679 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
680 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
681 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
682 hsn[CCREG]=1;
683 // ...or hash tables
684 hsn[RHASH]=1;
685 hsn[RHTBL]=1;
686 }
687 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 688 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 689 hsn[FTEMP]=0;
690 }
691 // Load L/R also uses FTEMP as a temporary register
692 if(itype[i]==LOADLR) {
693 hsn[FTEMP]=0;
694 }
b7918751 695 // Also SWL/SWR/SDL/SDR
696 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 697 hsn[FTEMP]=0;
698 }
699 // Don't remove the TLB registers either
b9b61529 700 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 701 hsn[TLREG]=0;
702 }
703 // Don't remove the miniht registers
704 if(itype[i]==UJUMP||itype[i]==RJUMP)
705 {
706 hsn[RHASH]=0;
707 hsn[RHTBL]=0;
708 }
709}
710
711// We only want to allocate registers if we're going to use them again soon
712int needed_again(int r, int i)
713{
714 int j;
715 int b=-1;
716 int rn=10;
717 int hr;
718 u_char hsn[MAXREG+1];
719 int preferred_reg;
720
721 memset(hsn,10,sizeof(hsn));
722 lsn(hsn,i,&preferred_reg);
723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
775 for(hr=0;hr<HOST_REGS;hr++) {
776 if(hr!=EXCLUDE_REG) {
777 if(rn<hsn[hr]) return 1;
778 }
779 }
780 return 0;
781}
782
783// Try to match register allocations at the end of a loop with those
784// at the beginning
785int loop_reg(int i, int r, int hr)
786{
787 int j,k;
788 for(j=0;j<9;j++)
789 {
790 if(i+j>=slen) {
791 j=slen-i-1;
792 break;
793 }
794 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
795 {
796 // Don't go past an unconditonal jump
797 j++;
798 break;
799 }
800 }
801 k=0;
802 if(i>0){
803 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
804 k--;
805 }
806 for(;k<j;k++)
807 {
808 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
809 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
810 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
811 {
812 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
813 {
814 int t=(ba[i+k]-start)>>2;
815 int reg=get_reg(regs[t].regmap_entry,r);
816 if(reg>=0) return reg;
817 //reg=get_reg(regs[t+1].regmap_entry,r);
818 //if(reg>=0) return reg;
819 }
820 }
821 }
822 return hr;
823}
824
825
826// Allocate every register, preserving source/target regs
827void alloc_all(struct regstat *cur,int i)
828{
829 int hr;
830
831 for(hr=0;hr<HOST_REGS;hr++) {
832 if(hr!=EXCLUDE_REG) {
833 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
834 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
835 {
836 cur->regmap[hr]=-1;
837 cur->dirty&=~(1<<hr);
838 }
839 // Don't need zeros
840 if((cur->regmap[hr]&63)==0)
841 {
842 cur->regmap[hr]=-1;
843 cur->dirty&=~(1<<hr);
844 }
845 }
846 }
847}
848
849
850void div64(int64_t dividend,int64_t divisor)
851{
852 lo=dividend/divisor;
853 hi=dividend%divisor;
854 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
855 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856}
857void divu64(uint64_t dividend,uint64_t divisor)
858{
859 lo=dividend/divisor;
860 hi=dividend%divisor;
861 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
862 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
863}
864
865void mult64(uint64_t m1,uint64_t m2)
866{
867 unsigned long long int op1, op2, op3, op4;
868 unsigned long long int result1, result2, result3, result4;
869 unsigned long long int temp1, temp2, temp3, temp4;
870 int sign = 0;
871
872 if (m1 < 0)
873 {
874 op2 = -m1;
875 sign = 1 - sign;
876 }
877 else op2 = m1;
878 if (m2 < 0)
879 {
880 op4 = -m2;
881 sign = 1 - sign;
882 }
883 else op4 = m2;
884
885 op1 = op2 & 0xFFFFFFFF;
886 op2 = (op2 >> 32) & 0xFFFFFFFF;
887 op3 = op4 & 0xFFFFFFFF;
888 op4 = (op4 >> 32) & 0xFFFFFFFF;
889
890 temp1 = op1 * op3;
891 temp2 = (temp1 >> 32) + op1 * op4;
892 temp3 = op2 * op3;
893 temp4 = (temp3 >> 32) + op2 * op4;
894
895 result1 = temp1 & 0xFFFFFFFF;
896 result2 = temp2 + (temp3 & 0xFFFFFFFF);
897 result3 = (result2 >> 32) + temp4;
898 result4 = (result3 >> 32);
899
900 lo = result1 | (result2 << 32);
901 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
902 if (sign)
903 {
904 hi = ~hi;
905 if (!lo) hi++;
906 else lo = ~lo + 1;
907 }
908}
909
910void multu64(uint64_t m1,uint64_t m2)
911{
912 unsigned long long int op1, op2, op3, op4;
913 unsigned long long int result1, result2, result3, result4;
914 unsigned long long int temp1, temp2, temp3, temp4;
915
916 op1 = m1 & 0xFFFFFFFF;
917 op2 = (m1 >> 32) & 0xFFFFFFFF;
918 op3 = m2 & 0xFFFFFFFF;
919 op4 = (m2 >> 32) & 0xFFFFFFFF;
920
921 temp1 = op1 * op3;
922 temp2 = (temp1 >> 32) + op1 * op4;
923 temp3 = op2 * op3;
924 temp4 = (temp3 >> 32) + op2 * op4;
925
926 result1 = temp1 & 0xFFFFFFFF;
927 result2 = temp2 + (temp3 & 0xFFFFFFFF);
928 result3 = (result2 >> 32) + temp4;
929 result4 = (result3 >> 32);
930
931 lo = result1 | (result2 << 32);
932 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
933
934 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
935 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
936}
937
938uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
939{
940 if(bits) {
941 original<<=64-bits;
942 original>>=64-bits;
943 loaded<<=bits;
944 original|=loaded;
945 }
946 else original=loaded;
947 return original;
948}
949uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
950{
951 if(bits^56) {
952 original>>=64-(bits^56);
953 original<<=64-(bits^56);
954 loaded>>=bits^56;
955 original|=loaded;
956 }
957 else original=loaded;
958 return original;
959}
960
961#ifdef __i386__
962#include "assem_x86.c"
963#endif
964#ifdef __x86_64__
965#include "assem_x64.c"
966#endif
967#ifdef __arm__
968#include "assem_arm.c"
969#endif
970
971// Add virtual address mapping to linked list
972void ll_add(struct ll_entry **head,int vaddr,void *addr)
973{
974 struct ll_entry *new_entry;
975 new_entry=malloc(sizeof(struct ll_entry));
976 assert(new_entry!=NULL);
977 new_entry->vaddr=vaddr;
978 new_entry->reg32=0;
979 new_entry->addr=addr;
980 new_entry->next=*head;
981 *head=new_entry;
982}
983
984// Add virtual address mapping for 32-bit compiled block
985void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
986{
7139f3c8 987 ll_add(head,vaddr,addr);
988#ifndef FORCE32
989 (*head)->reg32=reg32;
990#endif
57871462 991}
992
993// Check if an address is already compiled
994// but don't return addresses which are about to expire from the cache
995void *check_addr(u_int vaddr)
996{
997 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
998 if(ht_bin[0]==vaddr) {
999 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1001 }
1002 if(ht_bin[2]==vaddr) {
1003 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1005 }
94d23bb9 1006 u_int page=get_page(vaddr);
57871462 1007 struct ll_entry *head;
1008 head=jump_in[page];
1009 while(head!=NULL) {
1010 if(head->vaddr==vaddr&&head->reg32==0) {
1011 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1012 // Update existing entry with current address
1013 if(ht_bin[0]==vaddr) {
1014 ht_bin[1]=(int)head->addr;
1015 return head->addr;
1016 }
1017 if(ht_bin[2]==vaddr) {
1018 ht_bin[3]=(int)head->addr;
1019 return head->addr;
1020 }
1021 // Insert into hash table with low priority.
1022 // Don't evict existing entries, as they are probably
1023 // addresses that are being accessed frequently.
1024 if(ht_bin[0]==-1) {
1025 ht_bin[1]=(int)head->addr;
1026 ht_bin[0]=vaddr;
1027 }else if(ht_bin[2]==-1) {
1028 ht_bin[3]=(int)head->addr;
1029 ht_bin[2]=vaddr;
1030 }
1031 return head->addr;
1032 }
1033 }
1034 head=head->next;
1035 }
1036 return 0;
1037}
1038
1039void remove_hash(int vaddr)
1040{
1041 //printf("remove hash: %x\n",vaddr);
1042 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1043 if(ht_bin[2]==vaddr) {
1044 ht_bin[2]=ht_bin[3]=-1;
1045 }
1046 if(ht_bin[0]==vaddr) {
1047 ht_bin[0]=ht_bin[2];
1048 ht_bin[1]=ht_bin[3];
1049 ht_bin[2]=ht_bin[3]=-1;
1050 }
1051}
1052
1053void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1054{
1055 struct ll_entry *next;
1056 while(*head) {
1057 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1058 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1059 {
1060 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1061 remove_hash((*head)->vaddr);
1062 next=(*head)->next;
1063 free(*head);
1064 *head=next;
1065 }
1066 else
1067 {
1068 head=&((*head)->next);
1069 }
1070 }
1071}
1072
1073// Remove all entries from linked list
1074void ll_clear(struct ll_entry **head)
1075{
1076 struct ll_entry *cur;
1077 struct ll_entry *next;
1078 if(cur=*head) {
1079 *head=0;
1080 while(cur) {
1081 next=cur->next;
1082 free(cur);
1083 cur=next;
1084 }
1085 }
1086}
1087
1088// Dereference the pointers and remove if it matches
1089void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1090{
1091 while(head) {
1092 int ptr=get_pointer(head->addr);
1093 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1094 if(((ptr>>shift)==(addr>>shift)) ||
1095 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1096 {
5088bb70 1097 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1098 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1099 #ifdef __arm__
1100 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1101 #endif
57871462 1102 }
1103 head=head->next;
1104 }
1105}
1106
1107// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1108void invalidate_page(u_int page)
57871462 1109{
57871462 1110 struct ll_entry *head;
1111 struct ll_entry *next;
1112 head=jump_in[page];
1113 jump_in[page]=0;
1114 while(head!=NULL) {
1115 inv_debug("INVALIDATE: %x\n",head->vaddr);
1116 remove_hash(head->vaddr);
1117 next=head->next;
1118 free(head);
1119 head=next;
1120 }
1121 head=jump_out[page];
1122 jump_out[page]=0;
1123 while(head!=NULL) {
1124 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1125 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1126 #ifdef __arm__
1127 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1128 #endif
57871462 1129 next=head->next;
1130 free(head);
1131 head=next;
1132 }
57871462 1133}
1134void invalidate_block(u_int block)
1135{
94d23bb9 1136 u_int page=get_page(block<<12);
1137 u_int vpage=get_vpage(block<<12);
57871462 1138 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1139 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1140 u_int first,last;
1141 first=last=page;
1142 struct ll_entry *head;
1143 head=jump_dirty[vpage];
1144 //printf("page=%d vpage=%d\n",page,vpage);
1145 while(head!=NULL) {
1146 u_int start,end;
1147 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1148 get_bounds((int)head->addr,&start,&end);
1149 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1150 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1151 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1152 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1153 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1154 }
1155 }
90ae6d4e 1156#ifndef DISABLE_TLB
57871462 1157 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1158 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1159 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1160 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1161 }
1162 }
90ae6d4e 1163#endif
57871462 1164 }
1165 head=head->next;
1166 }
1167 //printf("first=%d last=%d\n",first,last);
f76eeef9 1168 invalidate_page(page);
57871462 1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1172 while(first<page) {
1173 invalidate_page(first);
1174 first++;
1175 }
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1178 }
dd3a91a1 1179 #ifdef __arm__
1180 do_clear_cache();
1181 #endif
57871462 1182
1183 // Don't trap writes
1184 invalid_code[block]=1;
94d23bb9 1185#ifndef DISABLE_TLB
57871462 1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1194 }
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1196#endif
f76eeef9 1197
57871462 1198 #ifdef USE_MINI_HT
1199 memset(mini_ht,-1,sizeof(mini_ht));
1200 #endif
1201}
1202void invalidate_addr(u_int addr)
1203{
1204 invalidate_block(addr>>12);
1205}
dd3a91a1 1206// This is called when loading a save state.
1207// Anything could have changed, so invalidate everything.
57871462 1208void invalidate_all_pages()
1209{
1210 u_int page,n;
1211 for(page=0;page<4096;page++)
1212 invalidate_page(page);
1213 for(page=0;page<1048576;page++)
1214 if(!invalid_code[page]) {
1215 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1216 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1217 }
1218 #ifdef __arm__
1219 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1220 #endif
1221 #ifdef USE_MINI_HT
1222 memset(mini_ht,-1,sizeof(mini_ht));
1223 #endif
94d23bb9 1224 #ifndef DISABLE_TLB
57871462 1225 // TLB
1226 for(page=0;page<0x100000;page++) {
1227 if(tlb_LUT_r[page]) {
1228 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1229 if(!tlb_LUT_w[page]||!invalid_code[page])
1230 memory_map[page]|=0x40000000; // Write protect
1231 }
1232 else memory_map[page]=-1;
1233 if(page==0x80000) page=0xC0000;
1234 }
1235 tlb_hacks();
94d23bb9 1236 #endif
57871462 1237}
1238
1239// Add an entry to jump_out after making a link
1240void add_link(u_int vaddr,void *src)
1241{
94d23bb9 1242 u_int page=get_page(vaddr);
57871462 1243 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1244 ll_add(jump_out+page,vaddr,src);
1245 //int ptr=get_pointer(src);
1246 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1247}
1248
1249// If a code block was found to be unmodified (bit was set in
1250// restore_candidate) and it remains unmodified (bit is clear
1251// in invalid_code) then move the entries for that 4K page from
1252// the dirty list to the clean list.
1253void clean_blocks(u_int page)
1254{
1255 struct ll_entry *head;
1256 inv_debug("INV: clean_blocks page=%d\n",page);
1257 head=jump_dirty[page];
1258 while(head!=NULL) {
1259 if(!invalid_code[head->vaddr>>12]) {
1260 // Don't restore blocks which are about to expire from the cache
1261 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262 u_int start,end;
1263 if(verify_dirty((int)head->addr)) {
1264 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1265 u_int i;
1266 u_int inv=0;
1267 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1268 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1269 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1270 inv|=invalid_code[i];
1271 }
1272 }
1273 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1274 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1275 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1276 if(addr<start||addr>=end) inv=1;
1277 }
4cb76aa4 1278 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1279 inv=1;
1280 }
1281 if(!inv) {
1282 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1283 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1284 u_int ppage=page;
94d23bb9 1285#ifndef DISABLE_TLB
57871462 1286 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1287#endif
57871462 1288 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1289 //printf("page=%x, addr=%x\n",page,head->vaddr);
1290 //assert(head->vaddr>>12==(page|0x80000));
1291 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1292 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1293 if(!head->reg32) {
1294 if(ht_bin[0]==head->vaddr) {
1295 ht_bin[1]=(int)clean_addr; // Replace existing entry
1296 }
1297 if(ht_bin[2]==head->vaddr) {
1298 ht_bin[3]=(int)clean_addr; // Replace existing entry
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 }
1306 head=head->next;
1307 }
1308}
1309
1310
1311void mov_alloc(struct regstat *current,int i)
1312{
1313 // Note: Don't need to actually alloc the source registers
1314 if((~current->is32>>rs1[i])&1) {
1315 //alloc_reg64(current,i,rs1[i]);
1316 alloc_reg64(current,i,rt1[i]);
1317 current->is32&=~(1LL<<rt1[i]);
1318 } else {
1319 //alloc_reg(current,i,rs1[i]);
1320 alloc_reg(current,i,rt1[i]);
1321 current->is32|=(1LL<<rt1[i]);
1322 }
1323 clear_const(current,rs1[i]);
1324 clear_const(current,rt1[i]);
1325 dirty_reg(current,rt1[i]);
1326}
1327
1328void shiftimm_alloc(struct regstat *current,int i)
1329{
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1333 {
1334 if(rt1[i]) {
1335 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1336 else lt1[i]=rs1[i];
1337 alloc_reg(current,i,rt1[i]);
1338 current->is32|=1LL<<rt1[i];
1339 dirty_reg(current,rt1[i]);
1340 }
1341 }
1342 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1343 {
1344 if(rt1[i]) {
1345 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1346 alloc_reg64(current,i,rt1[i]);
1347 current->is32&=~(1LL<<rt1[i]);
1348 dirty_reg(current,rt1[i]);
1349 }
1350 }
1351 if(opcode2[i]==0x3c) // DSLL32
1352 {
1353 if(rt1[i]) {
1354 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1355 alloc_reg64(current,i,rt1[i]);
1356 current->is32&=~(1LL<<rt1[i]);
1357 dirty_reg(current,rt1[i]);
1358 }
1359 }
1360 if(opcode2[i]==0x3e) // DSRL32
1361 {
1362 if(rt1[i]) {
1363 alloc_reg64(current,i,rs1[i]);
1364 if(imm[i]==32) {
1365 alloc_reg64(current,i,rt1[i]);
1366 current->is32&=~(1LL<<rt1[i]);
1367 } else {
1368 alloc_reg(current,i,rt1[i]);
1369 current->is32|=1LL<<rt1[i];
1370 }
1371 dirty_reg(current,rt1[i]);
1372 }
1373 }
1374 if(opcode2[i]==0x3f) // DSRA32
1375 {
1376 if(rt1[i]) {
1377 alloc_reg64(current,i,rs1[i]);
1378 alloc_reg(current,i,rt1[i]);
1379 current->is32|=1LL<<rt1[i];
1380 dirty_reg(current,rt1[i]);
1381 }
1382 }
1383}
1384
1385void shift_alloc(struct regstat *current,int i)
1386{
1387 if(rt1[i]) {
1388 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1389 {
1390 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1391 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1392 alloc_reg(current,i,rt1[i]);
e1190b87 1393 if(rt1[i]==rs2[i]) {
1394 alloc_reg_temp(current,i,-1);
1395 minimum_free_regs[i]=1;
1396 }
57871462 1397 current->is32|=1LL<<rt1[i];
1398 } else { // DSLLV/DSRLV/DSRAV
1399 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1400 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1403 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1404 {
57871462 1405 alloc_reg_temp(current,i,-1);
e1190b87 1406 minimum_free_regs[i]=1;
1407 }
57871462 1408 }
1409 clear_const(current,rs1[i]);
1410 clear_const(current,rs2[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1413 }
1414}
1415
1416void alu_alloc(struct regstat *current,int i)
1417{
1418 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1419 if(rt1[i]) {
1420 if(rs1[i]&&rs2[i]) {
1421 alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rs2[i]);
1423 }
1424 else {
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427 }
1428 alloc_reg(current,i,rt1[i]);
1429 }
1430 current->is32|=1LL<<rt1[i];
1431 }
1432 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1433 if(rt1[i]) {
1434 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1435 {
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1439 } else {
1440 alloc_reg(current,i,rs1[i]);
1441 alloc_reg(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1443 }
1444 }
1445 current->is32|=1LL<<rt1[i];
1446 }
1447 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1448 if(rt1[i]) {
1449 if(rs1[i]&&rs2[i]) {
1450 alloc_reg(current,i,rs1[i]);
1451 alloc_reg(current,i,rs2[i]);
1452 }
1453 else
1454 {
1455 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1456 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1457 }
1458 alloc_reg(current,i,rt1[i]);
1459 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1460 {
1461 if(!((current->uu>>rt1[i])&1)) {
1462 alloc_reg64(current,i,rt1[i]);
1463 }
1464 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1465 if(rs1[i]&&rs2[i]) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 }
1469 else
1470 {
1471 // Is is really worth it to keep 64-bit values in registers?
1472 #ifdef NATIVE_64BIT
1473 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1474 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1475 #endif
1476 }
1477 }
1478 current->is32&=~(1LL<<rt1[i]);
1479 } else {
1480 current->is32|=1LL<<rt1[i];
1481 }
1482 }
1483 }
1484 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1485 if(rt1[i]) {
1486 if(rs1[i]&&rs2[i]) {
1487 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1488 alloc_reg64(current,i,rs1[i]);
1489 alloc_reg64(current,i,rs2[i]);
1490 alloc_reg64(current,i,rt1[i]);
1491 } else {
1492 alloc_reg(current,i,rs1[i]);
1493 alloc_reg(current,i,rs2[i]);
1494 alloc_reg(current,i,rt1[i]);
1495 }
1496 }
1497 else {
1498 alloc_reg(current,i,rt1[i]);
1499 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1500 // DADD used as move, or zeroing
1501 // If we have a 64-bit source, then make the target 64 bits too
1502 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1503 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1504 alloc_reg64(current,i,rt1[i]);
1505 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1506 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1507 alloc_reg64(current,i,rt1[i]);
1508 }
1509 if(opcode2[i]>=0x2e&&rs2[i]) {
1510 // DSUB used as negation - 64-bit result
1511 // If we have a 32-bit register, extend it to 64 bits
1512 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1513 alloc_reg64(current,i,rt1[i]);
1514 }
1515 }
1516 }
1517 if(rs1[i]&&rs2[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1519 } else if(rs1[i]) {
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs1[i])&1)
1522 current->is32|=1LL<<rt1[i];
1523 } else if(rs2[i]) {
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs2[i])&1)
1526 current->is32|=1LL<<rt1[i];
1527 } else {
1528 current->is32|=1LL<<rt1[i];
1529 }
1530 }
1531 }
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1536}
1537
1538void imm16_alloc(struct regstat *current,int i)
1539{
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 else lt1[i]=rs1[i];
1542 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1543 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1544 current->is32&=~(1LL<<rt1[i]);
1545 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1546 // TODO: Could preserve the 32-bit flag if the immediate is zero
1547 alloc_reg64(current,i,rt1[i]);
1548 alloc_reg64(current,i,rs1[i]);
1549 }
1550 clear_const(current,rs1[i]);
1551 clear_const(current,rt1[i]);
1552 }
1553 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1554 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1555 current->is32|=1LL<<rt1[i];
1556 clear_const(current,rs1[i]);
1557 clear_const(current,rt1[i]);
1558 }
1559 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1560 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1561 if(rs1[i]!=rt1[i]) {
1562 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1565 }
1566 }
1567 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1568 if(is_const(current,rs1[i])) {
1569 int v=get_const(current,rs1[i]);
1570 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1571 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1572 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1573 }
1574 else clear_const(current,rt1[i]);
1575 }
1576 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1577 if(is_const(current,rs1[i])) {
1578 int v=get_const(current,rs1[i]);
1579 set_const(current,rt1[i],v+imm[i]);
1580 }
1581 else clear_const(current,rt1[i]);
1582 current->is32|=1LL<<rt1[i];
1583 }
1584 else {
1585 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1586 current->is32|=1LL<<rt1[i];
1587 }
1588 dirty_reg(current,rt1[i]);
1589}
1590
1591void load_alloc(struct regstat *current,int i)
1592{
1593 clear_const(current,rt1[i]);
1594 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1595 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1596 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1597 if(rt1[i]) {
1598 alloc_reg(current,i,rt1[i]);
535d208a 1599 if(get_reg(current->regmap,rt1[i])<0) {
1600 // dummy load, but we still need a register to calculate the address
1601 alloc_reg_temp(current,i,-1);
e1190b87 1602 minimum_free_regs[i]=1;
535d208a 1603 }
57871462 1604 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 }
1609 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1610 {
1611 current->is32&=~(1LL<<rt1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 alloc_all(current,i);
1614 alloc_reg64(current,i,FTEMP);
e1190b87 1615 minimum_free_regs[i]=HOST_REGS;
57871462 1616 }
1617 else current->is32|=1LL<<rt1[i];
1618 dirty_reg(current,rt1[i]);
1619 // If using TLB, need a register for pointer to the mapping table
1620 if(using_tlb) alloc_reg(current,i,TLREG);
1621 // LWL/LWR need a temporary register for the old value
1622 if(opcode[i]==0x22||opcode[i]==0x26)
1623 {
1624 alloc_reg(current,i,FTEMP);
1625 alloc_reg_temp(current,i,-1);
e1190b87 1626 minimum_free_regs[i]=1;
57871462 1627 }
1628 }
1629 else
1630 {
1631 // Load to r0 (dummy load)
1632 // but we still need a register to calculate the address
535d208a 1633 if(opcode[i]==0x22||opcode[i]==0x26)
1634 {
1635 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1636 }
57871462 1637 alloc_reg_temp(current,i,-1);
e1190b87 1638 minimum_free_regs[i]=1;
535d208a 1639 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1640 {
1641 alloc_all(current,i);
1642 alloc_reg64(current,i,FTEMP);
e1190b87 1643 minimum_free_regs[i]=HOST_REGS;
535d208a 1644 }
57871462 1645 }
1646}
1647
1648void store_alloc(struct regstat *current,int i)
1649{
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1657 }
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1663 #endif
b7918751 1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1665 alloc_reg(current,i,FTEMP);
1666 }
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
e1190b87 1669 minimum_free_regs[i]=1;
57871462 1670}
1671
1672void c1ls_alloc(struct regstat *current,int i)
1673{
1674 //clear_const(current,rs1[i]); // FIXME
1675 clear_const(current,rt1[i]);
1676 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1677 alloc_reg(current,i,CSREG); // Status
1678 alloc_reg(current,i,FTEMP);
1679 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1680 alloc_reg64(current,i,FTEMP);
1681 }
1682 // If using TLB, need a register for pointer to the mapping table
1683 if(using_tlb) alloc_reg(current,i,TLREG);
1684 #if defined(HOST_IMM8)
1685 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1686 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1687 alloc_reg(current,i,INVCP);
1688 #endif
1689 // We need a temporary register for address generation
1690 alloc_reg_temp(current,i,-1);
1691}
1692
b9b61529 1693void c2ls_alloc(struct regstat *current,int i)
1694{
1695 clear_const(current,rt1[i]);
1696 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1697 alloc_reg(current,i,FTEMP);
1698 // If using TLB, need a register for pointer to the mapping table
1699 if(using_tlb) alloc_reg(current,i,TLREG);
1700 #if defined(HOST_IMM8)
1701 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1702 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1703 alloc_reg(current,i,INVCP);
1704 #endif
1705 // We need a temporary register for address generation
1706 alloc_reg_temp(current,i,-1);
e1190b87 1707 minimum_free_regs[i]=1;
b9b61529 1708}
1709
57871462 1710#ifndef multdiv_alloc
1711void multdiv_alloc(struct regstat *current,int i)
1712{
1713 // case 0x18: MULT
1714 // case 0x19: MULTU
1715 // case 0x1A: DIV
1716 // case 0x1B: DIVU
1717 // case 0x1C: DMULT
1718 // case 0x1D: DMULTU
1719 // case 0x1E: DDIV
1720 // case 0x1F: DDIVU
1721 clear_const(current,rs1[i]);
1722 clear_const(current,rs2[i]);
1723 if(rs1[i]&&rs2[i])
1724 {
1725 if((opcode2[i]&4)==0) // 32-bit
1726 {
1727 current->u&=~(1LL<<HIREG);
1728 current->u&=~(1LL<<LOREG);
1729 alloc_reg(current,i,HIREG);
1730 alloc_reg(current,i,LOREG);
1731 alloc_reg(current,i,rs1[i]);
1732 alloc_reg(current,i,rs2[i]);
1733 current->is32|=1LL<<HIREG;
1734 current->is32|=1LL<<LOREG;
1735 dirty_reg(current,HIREG);
1736 dirty_reg(current,LOREG);
1737 }
1738 else // 64-bit
1739 {
1740 current->u&=~(1LL<<HIREG);
1741 current->u&=~(1LL<<LOREG);
1742 current->uu&=~(1LL<<HIREG);
1743 current->uu&=~(1LL<<LOREG);
1744 alloc_reg64(current,i,HIREG);
1745 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1746 alloc_reg64(current,i,rs1[i]);
1747 alloc_reg64(current,i,rs2[i]);
1748 alloc_all(current,i);
1749 current->is32&=~(1LL<<HIREG);
1750 current->is32&=~(1LL<<LOREG);
1751 dirty_reg(current,HIREG);
1752 dirty_reg(current,LOREG);
e1190b87 1753 minimum_free_regs[i]=HOST_REGS;
57871462 1754 }
1755 }
1756 else
1757 {
1758 // Multiply by zero is zero.
1759 // MIPS does not have a divide by zero exception.
1760 // The result is undefined, we return zero.
1761 alloc_reg(current,i,HIREG);
1762 alloc_reg(current,i,LOREG);
1763 current->is32|=1LL<<HIREG;
1764 current->is32|=1LL<<LOREG;
1765 dirty_reg(current,HIREG);
1766 dirty_reg(current,LOREG);
1767 }
1768}
1769#endif
1770
1771void cop0_alloc(struct regstat *current,int i)
1772{
1773 if(opcode2[i]==0) // MFC0
1774 {
1775 if(rt1[i]) {
1776 clear_const(current,rt1[i]);
1777 alloc_all(current,i);
1778 alloc_reg(current,i,rt1[i]);
1779 current->is32|=1LL<<rt1[i];
1780 dirty_reg(current,rt1[i]);
1781 }
1782 }
1783 else if(opcode2[i]==4) // MTC0
1784 {
1785 if(rs1[i]){
1786 clear_const(current,rs1[i]);
1787 alloc_reg(current,i,rs1[i]);
1788 alloc_all(current,i);
1789 }
1790 else {
1791 alloc_all(current,i); // FIXME: Keep r0
1792 current->u&=~1LL;
1793 alloc_reg(current,i,0);
1794 }
1795 }
1796 else
1797 {
1798 // TLBR/TLBWI/TLBWR/TLBP/ERET
1799 assert(opcode2[i]==0x10);
1800 alloc_all(current,i);
1801 }
e1190b87 1802 minimum_free_regs[i]=HOST_REGS;
57871462 1803}
1804
1805void cop1_alloc(struct regstat *current,int i)
1806{
1807 alloc_reg(current,i,CSREG); // Load status
1808 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1809 {
7de557a6 1810 if(rt1[i]){
1811 clear_const(current,rt1[i]);
1812 if(opcode2[i]==1) {
1813 alloc_reg64(current,i,rt1[i]); // DMFC1
1814 current->is32&=~(1LL<<rt1[i]);
1815 }else{
1816 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1817 current->is32|=1LL<<rt1[i];
1818 }
1819 dirty_reg(current,rt1[i]);
57871462 1820 }
57871462 1821 alloc_reg_temp(current,i,-1);
1822 }
1823 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1824 {
1825 if(rs1[i]){
1826 clear_const(current,rs1[i]);
1827 if(opcode2[i]==5)
1828 alloc_reg64(current,i,rs1[i]); // DMTC1
1829 else
1830 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1831 alloc_reg_temp(current,i,-1);
1832 }
1833 else {
1834 current->u&=~1LL;
1835 alloc_reg(current,i,0);
1836 alloc_reg_temp(current,i,-1);
1837 }
1838 }
e1190b87 1839 minimum_free_regs[i]=1;
57871462 1840}
1841void fconv_alloc(struct regstat *current,int i)
1842{
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
e1190b87 1845 minimum_free_regs[i]=1;
57871462 1846}
1847void float_alloc(struct regstat *current,int i)
1848{
1849 alloc_reg(current,i,CSREG); // Load status
1850 alloc_reg_temp(current,i,-1);
e1190b87 1851 minimum_free_regs[i]=1;
57871462 1852}
b9b61529 1853void c2op_alloc(struct regstat *current,int i)
1854{
1855 alloc_reg_temp(current,i,-1);
1856}
57871462 1857void fcomp_alloc(struct regstat *current,int i)
1858{
1859 alloc_reg(current,i,CSREG); // Load status
1860 alloc_reg(current,i,FSREG); // Load flags
1861 dirty_reg(current,FSREG); // Flag will be modified
1862 alloc_reg_temp(current,i,-1);
e1190b87 1863 minimum_free_regs[i]=1;
57871462 1864}
1865
1866void syscall_alloc(struct regstat *current,int i)
1867{
1868 alloc_cc(current,i);
1869 dirty_reg(current,CCREG);
1870 alloc_all(current,i);
e1190b87 1871 minimum_free_regs[i]=HOST_REGS;
57871462 1872 current->isconst=0;
1873}
1874
1875void delayslot_alloc(struct regstat *current,int i)
1876{
1877 switch(itype[i]) {
1878 case UJUMP:
1879 case CJUMP:
1880 case SJUMP:
1881 case RJUMP:
1882 case FJUMP:
1883 case SYSCALL:
7139f3c8 1884 case HLECALL:
57871462 1885 case SPAN:
1886 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1887 printf("Disabled speculative precompilation\n");
1888 stop_after_jal=1;
1889 break;
1890 case IMM16:
1891 imm16_alloc(current,i);
1892 break;
1893 case LOAD:
1894 case LOADLR:
1895 load_alloc(current,i);
1896 break;
1897 case STORE:
1898 case STORELR:
1899 store_alloc(current,i);
1900 break;
1901 case ALU:
1902 alu_alloc(current,i);
1903 break;
1904 case SHIFT:
1905 shift_alloc(current,i);
1906 break;
1907 case MULTDIV:
1908 multdiv_alloc(current,i);
1909 break;
1910 case SHIFTIMM:
1911 shiftimm_alloc(current,i);
1912 break;
1913 case MOV:
1914 mov_alloc(current,i);
1915 break;
1916 case COP0:
1917 cop0_alloc(current,i);
1918 break;
1919 case COP1:
b9b61529 1920 case COP2:
57871462 1921 cop1_alloc(current,i);
1922 break;
1923 case C1LS:
1924 c1ls_alloc(current,i);
1925 break;
b9b61529 1926 case C2LS:
1927 c2ls_alloc(current,i);
1928 break;
57871462 1929 case FCONV:
1930 fconv_alloc(current,i);
1931 break;
1932 case FLOAT:
1933 float_alloc(current,i);
1934 break;
1935 case FCOMP:
1936 fcomp_alloc(current,i);
1937 break;
b9b61529 1938 case C2OP:
1939 c2op_alloc(current,i);
1940 break;
57871462 1941 }
1942}
1943
1944// Special case where a branch and delay slot span two pages in virtual memory
1945static void pagespan_alloc(struct regstat *current,int i)
1946{
1947 current->isconst=0;
1948 current->wasconst=0;
1949 regs[i].wasconst=0;
e1190b87 1950 minimum_free_regs[i]=HOST_REGS;
57871462 1951 alloc_all(current,i);
1952 alloc_cc(current,i);
1953 dirty_reg(current,CCREG);
1954 if(opcode[i]==3) // JAL
1955 {
1956 alloc_reg(current,i,31);
1957 dirty_reg(current,31);
1958 }
1959 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1960 {
1961 alloc_reg(current,i,rs1[i]);
5067f341 1962 if (rt1[i]!=0) {
1963 alloc_reg(current,i,rt1[i]);
1964 dirty_reg(current,rt1[i]);
57871462 1965 }
1966 }
1967 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1968 {
1969 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1970 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1971 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1972 {
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1975 }
1976 }
1977 else
1978 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1979 {
1980 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1981 if(!((current->is32>>rs1[i])&1))
1982 {
1983 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1984 }
1985 }
1986 else
1987 if(opcode[i]==0x11) // BC1
1988 {
1989 alloc_reg(current,i,FSREG);
1990 alloc_reg(current,i,CSREG);
1991 }
1992 //else ...
1993}
1994
1995add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1996{
1997 stubs[stubcount][0]=type;
1998 stubs[stubcount][1]=addr;
1999 stubs[stubcount][2]=retaddr;
2000 stubs[stubcount][3]=a;
2001 stubs[stubcount][4]=b;
2002 stubs[stubcount][5]=c;
2003 stubs[stubcount][6]=d;
2004 stubs[stubcount][7]=e;
2005 stubcount++;
2006}
2007
2008// Write out a single register
2009void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2010{
2011 int hr;
2012 for(hr=0;hr<HOST_REGS;hr++) {
2013 if(hr!=EXCLUDE_REG) {
2014 if((regmap[hr]&63)==r) {
2015 if((dirty>>hr)&1) {
2016 if(regmap[hr]<64) {
2017 emit_storereg(r,hr);
24385cae 2018#ifndef FORCE32
57871462 2019 if((is32>>regmap[hr])&1) {
2020 emit_sarimm(hr,31,hr);
2021 emit_storereg(r|64,hr);
2022 }
24385cae 2023#endif
57871462 2024 }else{
2025 emit_storereg(r|64,hr);
2026 }
2027 }
2028 }
2029 }
2030 }
2031}
2032
2033int mchecksum()
2034{
2035 //if(!tracedebug) return 0;
2036 int i;
2037 int sum=0;
2038 for(i=0;i<2097152;i++) {
2039 unsigned int temp=sum;
2040 sum<<=1;
2041 sum|=(~temp)>>31;
2042 sum^=((u_int *)rdram)[i];
2043 }
2044 return sum;
2045}
2046int rchecksum()
2047{
2048 int i;
2049 int sum=0;
2050 for(i=0;i<64;i++)
2051 sum^=((u_int *)reg)[i];
2052 return sum;
2053}
57871462 2054void rlist()
2055{
2056 int i;
2057 printf("TRACE: ");
2058 for(i=0;i<32;i++)
2059 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2060 printf("\n");
3d624f89 2061#ifndef DISABLE_COP1
57871462 2062 printf("TRACE: ");
2063 for(i=0;i<32;i++)
2064 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2065 printf("\n");
3d624f89 2066#endif
57871462 2067}
2068
2069void enabletrace()
2070{
2071 tracedebug=1;
2072}
2073
2074void memdebug(int i)
2075{
2076 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2077 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2078 //rlist();
2079 //if(tracedebug) {
2080 //if(Count>=-2084597794) {
2081 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2082 //if(0) {
2083 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2084 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2085 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2086 rlist();
2087 #ifdef __i386__
2088 printf("TRACE: %x\n",(&i)[-1]);
2089 #endif
2090 #ifdef __arm__
2091 int j;
2092 printf("TRACE: %x \n",(&j)[10]);
2093 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2094 #endif
2095 //fflush(stdout);
2096 }
2097 //printf("TRACE: %x\n",(&i)[-1]);
2098}
2099
2100void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2101{
2102 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2103}
2104
2105void alu_assemble(int i,struct regstat *i_regs)
2106{
2107 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2108 if(rt1[i]) {
2109 signed char s1,s2,t;
2110 t=get_reg(i_regs->regmap,rt1[i]);
2111 if(t>=0) {
2112 s1=get_reg(i_regs->regmap,rs1[i]);
2113 s2=get_reg(i_regs->regmap,rs2[i]);
2114 if(rs1[i]&&rs2[i]) {
2115 assert(s1>=0);
2116 assert(s2>=0);
2117 if(opcode2[i]&2) emit_sub(s1,s2,t);
2118 else emit_add(s1,s2,t);
2119 }
2120 else if(rs1[i]) {
2121 if(s1>=0) emit_mov(s1,t);
2122 else emit_loadreg(rs1[i],t);
2123 }
2124 else if(rs2[i]) {
2125 if(s2>=0) {
2126 if(opcode2[i]&2) emit_neg(s2,t);
2127 else emit_mov(s2,t);
2128 }
2129 else {
2130 emit_loadreg(rs2[i],t);
2131 if(opcode2[i]&2) emit_neg(t,t);
2132 }
2133 }
2134 else emit_zeroreg(t);
2135 }
2136 }
2137 }
2138 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2139 if(rt1[i]) {
2140 signed char s1l,s2l,s1h,s2h,tl,th;
2141 tl=get_reg(i_regs->regmap,rt1[i]);
2142 th=get_reg(i_regs->regmap,rt1[i]|64);
2143 if(tl>=0) {
2144 s1l=get_reg(i_regs->regmap,rs1[i]);
2145 s2l=get_reg(i_regs->regmap,rs2[i]);
2146 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2147 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2148 if(rs1[i]&&rs2[i]) {
2149 assert(s1l>=0);
2150 assert(s2l>=0);
2151 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2152 else emit_adds(s1l,s2l,tl);
2153 if(th>=0) {
2154 #ifdef INVERTED_CARRY
2155 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2156 #else
2157 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2158 #endif
2159 else emit_add(s1h,s2h,th);
2160 }
2161 }
2162 else if(rs1[i]) {
2163 if(s1l>=0) emit_mov(s1l,tl);
2164 else emit_loadreg(rs1[i],tl);
2165 if(th>=0) {
2166 if(s1h>=0) emit_mov(s1h,th);
2167 else emit_loadreg(rs1[i]|64,th);
2168 }
2169 }
2170 else if(rs2[i]) {
2171 if(s2l>=0) {
2172 if(opcode2[i]&2) emit_negs(s2l,tl);
2173 else emit_mov(s2l,tl);
2174 }
2175 else {
2176 emit_loadreg(rs2[i],tl);
2177 if(opcode2[i]&2) emit_negs(tl,tl);
2178 }
2179 if(th>=0) {
2180 #ifdef INVERTED_CARRY
2181 if(s2h>=0) emit_mov(s2h,th);
2182 else emit_loadreg(rs2[i]|64,th);
2183 if(opcode2[i]&2) {
2184 emit_adcimm(-1,th); // x86 has inverted carry flag
2185 emit_not(th,th);
2186 }
2187 #else
2188 if(opcode2[i]&2) {
2189 if(s2h>=0) emit_rscimm(s2h,0,th);
2190 else {
2191 emit_loadreg(rs2[i]|64,th);
2192 emit_rscimm(th,0,th);
2193 }
2194 }else{
2195 if(s2h>=0) emit_mov(s2h,th);
2196 else emit_loadreg(rs2[i]|64,th);
2197 }
2198 #endif
2199 }
2200 }
2201 else {
2202 emit_zeroreg(tl);
2203 if(th>=0) emit_zeroreg(th);
2204 }
2205 }
2206 }
2207 }
2208 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2209 if(rt1[i]) {
2210 signed char s1l,s1h,s2l,s2h,t;
2211 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2212 {
2213 t=get_reg(i_regs->regmap,rt1[i]);
2214 //assert(t>=0);
2215 if(t>=0) {
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2218 s2l=get_reg(i_regs->regmap,rs2[i]);
2219 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2220 if(rs2[i]==0) // rx<r0
2221 {
2222 assert(s1h>=0);
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1h,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2226 emit_zeroreg(t);
2227 }
2228 else if(rs1[i]==0) // r0<rx
2229 {
2230 assert(s2h>=0);
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz64_32(s2h,s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz64_32(s2h,s2l,t);
2235 }
2236 else {
2237 assert(s1l>=0);assert(s1h>=0);
2238 assert(s2l>=0);assert(s2h>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2241 else // SLTU
2242 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2243 }
2244 }
2245 } else {
2246 t=get_reg(i_regs->regmap,rt1[i]);
2247 //assert(t>=0);
2248 if(t>=0) {
2249 s1l=get_reg(i_regs->regmap,rs1[i]);
2250 s2l=get_reg(i_regs->regmap,rs2[i]);
2251 if(rs2[i]==0) // rx<r0
2252 {
2253 assert(s1l>=0);
2254 if(opcode2[i]==0x2a) // SLT
2255 emit_shrimm(s1l,31,t);
2256 else // SLTU (unsigned can not be less than zero)
2257 emit_zeroreg(t);
2258 }
2259 else if(rs1[i]==0) // r0<rx
2260 {
2261 assert(s2l>=0);
2262 if(opcode2[i]==0x2a) // SLT
2263 emit_set_gz32(s2l,t);
2264 else // SLTU (set if not zero)
2265 emit_set_nz32(s2l,t);
2266 }
2267 else{
2268 assert(s1l>=0);assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_if_less32(s1l,s2l,t);
2271 else // SLTU
2272 emit_set_if_carry32(s1l,s2l,t);
2273 }
2274 }
2275 }
2276 }
2277 }
2278 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2279 if(rt1[i]) {
2280 signed char s1l,s1h,s2l,s2h,th,tl;
2281 tl=get_reg(i_regs->regmap,rt1[i]);
2282 th=get_reg(i_regs->regmap,rt1[i]|64);
2283 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2284 {
2285 assert(tl>=0);
2286 if(tl>=0) {
2287 s1l=get_reg(i_regs->regmap,rs1[i]);
2288 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2289 s2l=get_reg(i_regs->regmap,rs2[i]);
2290 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2291 if(rs1[i]&&rs2[i]) {
2292 assert(s1l>=0);assert(s1h>=0);
2293 assert(s2l>=0);assert(s2h>=0);
2294 if(opcode2[i]==0x24) { // AND
2295 emit_and(s1l,s2l,tl);
2296 emit_and(s1h,s2h,th);
2297 } else
2298 if(opcode2[i]==0x25) { // OR
2299 emit_or(s1l,s2l,tl);
2300 emit_or(s1h,s2h,th);
2301 } else
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2304 emit_xor(s1h,s2h,th);
2305 } else
2306 if(opcode2[i]==0x27) { // NOR
2307 emit_or(s1l,s2l,tl);
2308 emit_or(s1h,s2h,th);
2309 emit_not(tl,tl);
2310 emit_not(th,th);
2311 }
2312 }
2313 else
2314 {
2315 if(opcode2[i]==0x24) { // AND
2316 emit_zeroreg(tl);
2317 emit_zeroreg(th);
2318 } else
2319 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2320 if(rs1[i]){
2321 if(s1l>=0) emit_mov(s1l,tl);
2322 else emit_loadreg(rs1[i],tl);
2323 if(s1h>=0) emit_mov(s1h,th);
2324 else emit_loadreg(rs1[i]|64,th);
2325 }
2326 else
2327 if(rs2[i]){
2328 if(s2l>=0) emit_mov(s2l,tl);
2329 else emit_loadreg(rs2[i],tl);
2330 if(s2h>=0) emit_mov(s2h,th);
2331 else emit_loadreg(rs2[i]|64,th);
2332 }
2333 else{
2334 emit_zeroreg(tl);
2335 emit_zeroreg(th);
2336 }
2337 } else
2338 if(opcode2[i]==0x27) { // NOR
2339 if(rs1[i]){
2340 if(s1l>=0) emit_not(s1l,tl);
2341 else{
2342 emit_loadreg(rs1[i],tl);
2343 emit_not(tl,tl);
2344 }
2345 if(s1h>=0) emit_not(s1h,th);
2346 else{
2347 emit_loadreg(rs1[i]|64,th);
2348 emit_not(th,th);
2349 }
2350 }
2351 else
2352 if(rs2[i]){
2353 if(s2l>=0) emit_not(s2l,tl);
2354 else{
2355 emit_loadreg(rs2[i],tl);
2356 emit_not(tl,tl);
2357 }
2358 if(s2h>=0) emit_not(s2h,th);
2359 else{
2360 emit_loadreg(rs2[i]|64,th);
2361 emit_not(th,th);
2362 }
2363 }
2364 else {
2365 emit_movimm(-1,tl);
2366 emit_movimm(-1,th);
2367 }
2368 }
2369 }
2370 }
2371 }
2372 else
2373 {
2374 // 32 bit
2375 if(tl>=0) {
2376 s1l=get_reg(i_regs->regmap,rs1[i]);
2377 s2l=get_reg(i_regs->regmap,rs2[i]);
2378 if(rs1[i]&&rs2[i]) {
2379 assert(s1l>=0);
2380 assert(s2l>=0);
2381 if(opcode2[i]==0x24) { // AND
2382 emit_and(s1l,s2l,tl);
2383 } else
2384 if(opcode2[i]==0x25) { // OR
2385 emit_or(s1l,s2l,tl);
2386 } else
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2389 } else
2390 if(opcode2[i]==0x27) { // NOR
2391 emit_or(s1l,s2l,tl);
2392 emit_not(tl,tl);
2393 }
2394 }
2395 else
2396 {
2397 if(opcode2[i]==0x24) { // AND
2398 emit_zeroreg(tl);
2399 } else
2400 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2401 if(rs1[i]){
2402 if(s1l>=0) emit_mov(s1l,tl);
2403 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2404 }
2405 else
2406 if(rs2[i]){
2407 if(s2l>=0) emit_mov(s2l,tl);
2408 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2409 }
2410 else emit_zeroreg(tl);
2411 } else
2412 if(opcode2[i]==0x27) { // NOR
2413 if(rs1[i]){
2414 if(s1l>=0) emit_not(s1l,tl);
2415 else {
2416 emit_loadreg(rs1[i],tl);
2417 emit_not(tl,tl);
2418 }
2419 }
2420 else
2421 if(rs2[i]){
2422 if(s2l>=0) emit_not(s2l,tl);
2423 else {
2424 emit_loadreg(rs2[i],tl);
2425 emit_not(tl,tl);
2426 }
2427 }
2428 else emit_movimm(-1,tl);
2429 }
2430 }
2431 }
2432 }
2433 }
2434 }
2435}
2436
2437void imm16_assemble(int i,struct regstat *i_regs)
2438{
2439 if (opcode[i]==0x0f) { // LUI
2440 if(rt1[i]) {
2441 signed char t;
2442 t=get_reg(i_regs->regmap,rt1[i]);
2443 //assert(t>=0);
2444 if(t>=0) {
2445 if(!((i_regs->isconst>>t)&1))
2446 emit_movimm(imm[i]<<16,t);
2447 }
2448 }
2449 }
2450 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2451 if(rt1[i]) {
2452 signed char s,t;
2453 t=get_reg(i_regs->regmap,rt1[i]);
2454 s=get_reg(i_regs->regmap,rs1[i]);
2455 if(rs1[i]) {
2456 //assert(t>=0);
2457 //assert(s>=0);
2458 if(t>=0) {
2459 if(!((i_regs->isconst>>t)&1)) {
2460 if(s<0) {
2461 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2462 emit_addimm(t,imm[i],t);
2463 }else{
2464 if(!((i_regs->wasconst>>s)&1))
2465 emit_addimm(s,imm[i],t);
2466 else
2467 emit_movimm(constmap[i][s]+imm[i],t);
2468 }
2469 }
2470 }
2471 } else {
2472 if(t>=0) {
2473 if(!((i_regs->isconst>>t)&1))
2474 emit_movimm(imm[i],t);
2475 }
2476 }
2477 }
2478 }
2479 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2480 if(rt1[i]) {
2481 signed char sh,sl,th,tl;
2482 th=get_reg(i_regs->regmap,rt1[i]|64);
2483 tl=get_reg(i_regs->regmap,rt1[i]);
2484 sh=get_reg(i_regs->regmap,rs1[i]|64);
2485 sl=get_reg(i_regs->regmap,rs1[i]);
2486 if(tl>=0) {
2487 if(rs1[i]) {
2488 assert(sh>=0);
2489 assert(sl>=0);
2490 if(th>=0) {
2491 emit_addimm64_32(sh,sl,imm[i],th,tl);
2492 }
2493 else {
2494 emit_addimm(sl,imm[i],tl);
2495 }
2496 } else {
2497 emit_movimm(imm[i],tl);
2498 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2499 }
2500 }
2501 }
2502 }
2503 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2504 if(rt1[i]) {
2505 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2506 signed char sh,sl,t;
2507 t=get_reg(i_regs->regmap,rt1[i]);
2508 sh=get_reg(i_regs->regmap,rs1[i]|64);
2509 sl=get_reg(i_regs->regmap,rs1[i]);
2510 //assert(t>=0);
2511 if(t>=0) {
2512 if(rs1[i]>0) {
2513 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2514 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2515 if(opcode[i]==0x0a) { // SLTI
2516 if(sl<0) {
2517 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2518 emit_slti32(t,imm[i],t);
2519 }else{
2520 emit_slti32(sl,imm[i],t);
2521 }
2522 }
2523 else { // SLTIU
2524 if(sl<0) {
2525 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2526 emit_sltiu32(t,imm[i],t);
2527 }else{
2528 emit_sltiu32(sl,imm[i],t);
2529 }
2530 }
2531 }else{ // 64-bit
2532 assert(sl>=0);
2533 if(opcode[i]==0x0a) // SLTI
2534 emit_slti64_32(sh,sl,imm[i],t);
2535 else // SLTIU
2536 emit_sltiu64_32(sh,sl,imm[i],t);
2537 }
2538 }else{
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
2541 if(opcode[i]==0x0a) // SLTI
2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2544 else // SLTIU
2545 {
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2548 }
2549 }
2550 }
2551 }
2552 }
2553 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2554 if(rt1[i]) {
2555 signed char sh,sl,th,tl;
2556 th=get_reg(i_regs->regmap,rt1[i]|64);
2557 tl=get_reg(i_regs->regmap,rt1[i]);
2558 sh=get_reg(i_regs->regmap,rs1[i]|64);
2559 sl=get_reg(i_regs->regmap,rs1[i]);
2560 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2561 if(opcode[i]==0x0c) //ANDI
2562 {
2563 if(rs1[i]) {
2564 if(sl<0) {
2565 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2566 emit_andimm(tl,imm[i],tl);
2567 }else{
2568 if(!((i_regs->wasconst>>sl)&1))
2569 emit_andimm(sl,imm[i],tl);
2570 else
2571 emit_movimm(constmap[i][sl]&imm[i],tl);
2572 }
2573 }
2574 else
2575 emit_zeroreg(tl);
2576 if(th>=0) emit_zeroreg(th);
2577 }
2578 else
2579 {
2580 if(rs1[i]) {
2581 if(sl<0) {
2582 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2583 }
2584 if(th>=0) {
2585 if(sh<0) {
2586 emit_loadreg(rs1[i]|64,th);
2587 }else{
2588 emit_mov(sh,th);
2589 }
2590 }
2591 if(opcode[i]==0x0d) //ORI
2592 if(sl<0) {
2593 emit_orimm(tl,imm[i],tl);
2594 }else{
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_orimm(sl,imm[i],tl);
2597 else
2598 emit_movimm(constmap[i][sl]|imm[i],tl);
2599 }
2600 if(opcode[i]==0x0e) //XORI
2601 if(sl<0) {
2602 emit_xorimm(tl,imm[i],tl);
2603 }else{
2604 if(!((i_regs->wasconst>>sl)&1))
2605 emit_xorimm(sl,imm[i],tl);
2606 else
2607 emit_movimm(constmap[i][sl]^imm[i],tl);
2608 }
2609 }
2610 else {
2611 emit_movimm(imm[i],tl);
2612 if(th>=0) emit_zeroreg(th);
2613 }
2614 }
2615 }
2616 }
2617 }
2618}
2619
2620void shiftimm_assemble(int i,struct regstat *i_regs)
2621{
2622 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2623 {
2624 if(rt1[i]) {
2625 signed char s,t;
2626 t=get_reg(i_regs->regmap,rt1[i]);
2627 s=get_reg(i_regs->regmap,rs1[i]);
2628 //assert(t>=0);
2629 if(t>=0){
2630 if(rs1[i]==0)
2631 {
2632 emit_zeroreg(t);
2633 }
2634 else
2635 {
2636 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2637 if(imm[i]) {
2638 if(opcode2[i]==0) // SLL
2639 {
2640 emit_shlimm(s<0?t:s,imm[i],t);
2641 }
2642 if(opcode2[i]==2) // SRL
2643 {
2644 emit_shrimm(s<0?t:s,imm[i],t);
2645 }
2646 if(opcode2[i]==3) // SRA
2647 {
2648 emit_sarimm(s<0?t:s,imm[i],t);
2649 }
2650 }else{
2651 // Shift by zero
2652 if(s>=0 && s!=t) emit_mov(s,t);
2653 }
2654 }
2655 }
2656 //emit_storereg(rt1[i],t); //DEBUG
2657 }
2658 }
2659 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2660 {
2661 if(rt1[i]) {
2662 signed char sh,sl,th,tl;
2663 th=get_reg(i_regs->regmap,rt1[i]|64);
2664 tl=get_reg(i_regs->regmap,rt1[i]);
2665 sh=get_reg(i_regs->regmap,rs1[i]|64);
2666 sl=get_reg(i_regs->regmap,rs1[i]);
2667 if(tl>=0) {
2668 if(rs1[i]==0)
2669 {
2670 emit_zeroreg(tl);
2671 if(th>=0) emit_zeroreg(th);
2672 }
2673 else
2674 {
2675 assert(sl>=0);
2676 assert(sh>=0);
2677 if(imm[i]) {
2678 if(opcode2[i]==0x38) // DSLL
2679 {
2680 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2681 emit_shlimm(sl,imm[i],tl);
2682 }
2683 if(opcode2[i]==0x3a) // DSRL
2684 {
2685 emit_shrdimm(sl,sh,imm[i],tl);
2686 if(th>=0) emit_shrimm(sh,imm[i],th);
2687 }
2688 if(opcode2[i]==0x3b) // DSRA
2689 {
2690 emit_shrdimm(sl,sh,imm[i],tl);
2691 if(th>=0) emit_sarimm(sh,imm[i],th);
2692 }
2693 }else{
2694 // Shift by zero
2695 if(sl!=tl) emit_mov(sl,tl);
2696 if(th>=0&&sh!=th) emit_mov(sh,th);
2697 }
2698 }
2699 }
2700 }
2701 }
2702 if(opcode2[i]==0x3c) // DSLL32
2703 {
2704 if(rt1[i]) {
2705 signed char sl,tl,th;
2706 tl=get_reg(i_regs->regmap,rt1[i]);
2707 th=get_reg(i_regs->regmap,rt1[i]|64);
2708 sl=get_reg(i_regs->regmap,rs1[i]);
2709 if(th>=0||tl>=0){
2710 assert(tl>=0);
2711 assert(th>=0);
2712 assert(sl>=0);
2713 emit_mov(sl,th);
2714 emit_zeroreg(tl);
2715 if(imm[i]>32)
2716 {
2717 emit_shlimm(th,imm[i]&31,th);
2718 }
2719 }
2720 }
2721 }
2722 if(opcode2[i]==0x3e) // DSRL32
2723 {
2724 if(rt1[i]) {
2725 signed char sh,tl,th;
2726 tl=get_reg(i_regs->regmap,rt1[i]);
2727 th=get_reg(i_regs->regmap,rt1[i]|64);
2728 sh=get_reg(i_regs->regmap,rs1[i]|64);
2729 if(tl>=0){
2730 assert(sh>=0);
2731 emit_mov(sh,tl);
2732 if(th>=0) emit_zeroreg(th);
2733 if(imm[i]>32)
2734 {
2735 emit_shrimm(tl,imm[i]&31,tl);
2736 }
2737 }
2738 }
2739 }
2740 if(opcode2[i]==0x3f) // DSRA32
2741 {
2742 if(rt1[i]) {
2743 signed char sh,tl;
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 sh=get_reg(i_regs->regmap,rs1[i]|64);
2746 if(tl>=0){
2747 assert(sh>=0);
2748 emit_mov(sh,tl);
2749 if(imm[i]>32)
2750 {
2751 emit_sarimm(tl,imm[i]&31,tl);
2752 }
2753 }
2754 }
2755 }
2756}
2757
2758#ifndef shift_assemble
2759void shift_assemble(int i,struct regstat *i_regs)
2760{
2761 printf("Need shift_assemble for this architecture.\n");
2762 exit(1);
2763}
2764#endif
2765
2766void load_assemble(int i,struct regstat *i_regs)
2767{
2768 int s,th,tl,addr,map=-1;
2769 int offset;
2770 int jaddr=0;
5bf843dc 2771 int memtarget=0,c=0;
57871462 2772 u_int hr,reglist=0;
2773 th=get_reg(i_regs->regmap,rt1[i]|64);
2774 tl=get_reg(i_regs->regmap,rt1[i]);
2775 s=get_reg(i_regs->regmap,rs1[i]);
2776 offset=imm[i];
2777 for(hr=0;hr<HOST_REGS;hr++) {
2778 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2779 }
2780 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2781 if(s>=0) {
2782 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2783 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2784 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2785 }
57871462 2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2789#ifdef PCSX
f18c0f46 2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2791 ||rt1[i]==0) {
5bf843dc 2792 // could be FIFO, must perform the read
f18c0f46 2793 // ||dummy read
5bf843dc 2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2796 assert(tl>=0);
5bf843dc 2797 }
f18c0f46 2798#endif
5bf843dc 2799 if(offset||s<0||c) addr=tl;
2800 else addr=s;
535d208a 2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2802 if(tl>=0) {
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2806 reglist&=~(1<<tl);
2807 if(th>=0) reglist&=~(1<<th);
2808 if(!using_tlb) {
2809 if(!c) {
2810 #ifdef RAM_OFFSET
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2813 #endif
57871462 2814//#define R29_HACK 1
535d208a 2815 #ifdef R29_HACK
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2818 #endif
2819 {
2820 emit_cmpimm(addr,RAM_SIZE);
2821 jaddr=(int)out;
2822 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2823 // Hint to branch predictor that the branch is unlikely to be taken
2824 if(rs1[i]>=28)
2825 emit_jno_unlikely(0);
2826 else
57871462 2827 #endif
535d208a 2828 emit_jno(0);
57871462 2829 }
535d208a 2830 }
2831 }else{ // using tlb
2832 int x=0;
2833 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2834 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2835 map=get_reg(i_regs->regmap,TLREG);
2836 assert(map>=0);
2837 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2838 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2839 }
2840 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2841 if (opcode[i]==0x20) { // LB
2842 if(!c||memtarget) {
2843 if(!dummy) {
57871462 2844 #ifdef HOST_IMM_ADDR32
2845 if(c)
2846 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2847 else
2848 #endif
2849 {
2850 //emit_xorimm(addr,3,tl);
2851 //gen_tlb_addr_r(tl,map);
2852 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2853 int x=0,a=tl;
2002a1db 2854#ifdef BIG_ENDIAN_MIPS
57871462 2855 if(!c) emit_xorimm(addr,3,tl);
2856 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2857#else
535d208a 2858 if(!c) a=addr;
2002a1db 2859#endif
535d208a 2860 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2861 }
57871462 2862 }
535d208a 2863 if(jaddr)
2864 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2865 }
535d208a 2866 else
2867 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2868 }
2869 if (opcode[i]==0x21) { // LH
2870 if(!c||memtarget) {
2871 if(!dummy) {
57871462 2872 #ifdef HOST_IMM_ADDR32
2873 if(c)
2874 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2875 else
2876 #endif
2877 {
535d208a 2878 int x=0,a=tl;
2002a1db 2879#ifdef BIG_ENDIAN_MIPS
57871462 2880 if(!c) emit_xorimm(addr,2,tl);
2881 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2882#else
535d208a 2883 if(!c) a=addr;
2002a1db 2884#endif
57871462 2885 //#ifdef
2886 //emit_movswl_indexed_tlb(x,tl,map,tl);
2887 //else
2888 if(map>=0) {
535d208a 2889 gen_tlb_addr_r(a,map);
2890 emit_movswl_indexed(x,a,tl);
2891 }else{
2892 #ifdef RAM_OFFSET
2893 emit_movswl_indexed(x,a,tl);
2894 #else
2895 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2896 #endif
2897 }
57871462 2898 }
57871462 2899 }
535d208a 2900 if(jaddr)
2901 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2902 }
535d208a 2903 else
2904 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2905 }
2906 if (opcode[i]==0x23) { // LW
2907 if(!c||memtarget) {
2908 if(!dummy) {
57871462 2909 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2910 #ifdef HOST_IMM_ADDR32
2911 if(c)
2912 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2913 else
2914 #endif
2915 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2916 }
535d208a 2917 if(jaddr)
2918 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2919 }
535d208a 2920 else
2921 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2922 }
2923 if (opcode[i]==0x24) { // LBU
2924 if(!c||memtarget) {
2925 if(!dummy) {
57871462 2926 #ifdef HOST_IMM_ADDR32
2927 if(c)
2928 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2929 else
2930 #endif
2931 {
2932 //emit_xorimm(addr,3,tl);
2933 //gen_tlb_addr_r(tl,map);
2934 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2935 int x=0,a=tl;
2002a1db 2936#ifdef BIG_ENDIAN_MIPS
57871462 2937 if(!c) emit_xorimm(addr,3,tl);
2938 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2939#else
535d208a 2940 if(!c) a=addr;
2002a1db 2941#endif
535d208a 2942 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2943 }
57871462 2944 }
535d208a 2945 if(jaddr)
2946 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2947 }
535d208a 2948 else
2949 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950 }
2951 if (opcode[i]==0x25) { // LHU
2952 if(!c||memtarget) {
2953 if(!dummy) {
57871462 2954 #ifdef HOST_IMM_ADDR32
2955 if(c)
2956 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2957 else
2958 #endif
2959 {
535d208a 2960 int x=0,a=tl;
2002a1db 2961#ifdef BIG_ENDIAN_MIPS
57871462 2962 if(!c) emit_xorimm(addr,2,tl);
2963 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2964#else
535d208a 2965 if(!c) a=addr;
2002a1db 2966#endif
57871462 2967 //#ifdef
2968 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2969 //#else
2970 if(map>=0) {
535d208a 2971 gen_tlb_addr_r(a,map);
2972 emit_movzwl_indexed(x,a,tl);
2973 }else{
2974 #ifdef RAM_OFFSET
2975 emit_movzwl_indexed(x,a,tl);
2976 #else
2977 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2978 #endif
2979 }
57871462 2980 }
2981 }
535d208a 2982 if(jaddr)
2983 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2984 }
535d208a 2985 else
2986 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2987 }
2988 if (opcode[i]==0x27) { // LWU
2989 assert(th>=0);
2990 if(!c||memtarget) {
2991 if(!dummy) {
57871462 2992 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2993 #ifdef HOST_IMM_ADDR32
2994 if(c)
2995 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2996 else
2997 #endif
2998 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2999 }
535d208a 3000 if(jaddr)
3001 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3002 }
3003 else {
3004 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3005 }
535d208a 3006 emit_zeroreg(th);
3007 }
3008 if (opcode[i]==0x37) { // LD
3009 if(!c||memtarget) {
3010 if(!dummy) {
57871462 3011 //gen_tlb_addr_r(tl,map);
3012 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3013 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3014 #ifdef HOST_IMM_ADDR32
3015 if(c)
3016 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3017 else
3018 #endif
3019 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 3020 }
535d208a 3021 if(jaddr)
3022 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3023 }
535d208a 3024 else
3025 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3026 }
535d208a 3027 }
3028 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3029 //if(opcode[i]==0x23)
3030 //if(opcode[i]==0x24)
3031 //if(opcode[i]==0x23||opcode[i]==0x24)
3032 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3033 {
3034 //emit_pusha();
3035 save_regs(0x100f);
3036 emit_readword((int)&last_count,ECX);
3037 #ifdef __i386__
3038 if(get_reg(i_regs->regmap,CCREG)<0)
3039 emit_loadreg(CCREG,HOST_CCREG);
3040 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3041 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3042 emit_writeword(HOST_CCREG,(int)&Count);
3043 #endif
3044 #ifdef __arm__
3045 if(get_reg(i_regs->regmap,CCREG)<0)
3046 emit_loadreg(CCREG,0);
3047 else
3048 emit_mov(HOST_CCREG,0);
3049 emit_add(0,ECX,0);
3050 emit_addimm(0,2*ccadj[i],0);
3051 emit_writeword(0,(int)&Count);
3052 #endif
3053 emit_call((int)memdebug);
3054 //emit_popa();
3055 restore_regs(0x100f);
3056 }/**/
3057}
3058
3059#ifndef loadlr_assemble
3060void loadlr_assemble(int i,struct regstat *i_regs)
3061{
3062 printf("Need loadlr_assemble for this architecture.\n");
3063 exit(1);
3064}
3065#endif
3066
3067void store_assemble(int i,struct regstat *i_regs)
3068{
3069 int s,th,tl,map=-1;
3070 int addr,temp;
3071 int offset;
3072 int jaddr=0,jaddr2,type;
666a299d 3073 int memtarget=0,c=0;
57871462 3074 int agr=AGEN1+(i&1);
3075 u_int hr,reglist=0;
3076 th=get_reg(i_regs->regmap,rs2[i]|64);
3077 tl=get_reg(i_regs->regmap,rs2[i]);
3078 s=get_reg(i_regs->regmap,rs1[i]);
3079 temp=get_reg(i_regs->regmap,agr);
3080 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3081 offset=imm[i];
3082 if(s>=0) {
3083 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3084 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3085 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3086 }
3087 assert(tl>=0);
3088 assert(temp>=0);
3089 for(hr=0;hr<HOST_REGS;hr++) {
3090 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3091 }
3092 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3093 if(offset||s<0||c) addr=temp;
3094 else addr=s;
3095 if(!using_tlb) {
3096 if(!c) {
3097 #ifdef R29_HACK
3098 // Strmnnrmn's speed hack
3099 memtarget=1;
4cb76aa4 3100 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3101 #endif
4cb76aa4 3102 emit_cmpimm(addr,RAM_SIZE);
57871462 3103 #ifdef DESTRUCTIVE_SHIFT
3104 if(s==addr) emit_mov(s,temp);
3105 #endif
3106 #ifdef R29_HACK
4cb76aa4 3107 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3108 #endif
3109 {
3110 jaddr=(int)out;
3111 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3112 // Hint to branch predictor that the branch is unlikely to be taken
3113 if(rs1[i]>=28)
3114 emit_jno_unlikely(0);
3115 else
3116 #endif
3117 emit_jno(0);
3118 }
3119 }
3120 }else{ // using tlb
3121 int x=0;
3122 if (opcode[i]==0x28) x=3; // SB
3123 if (opcode[i]==0x29) x=2; // SH
3124 map=get_reg(i_regs->regmap,TLREG);
3125 assert(map>=0);
3126 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3127 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3128 }
3129
3130 if (opcode[i]==0x28) { // SB
3131 if(!c||memtarget) {
97a238a6 3132 int x=0,a=temp;
2002a1db 3133#ifdef BIG_ENDIAN_MIPS
57871462 3134 if(!c) emit_xorimm(addr,3,temp);
3135 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3136#else
97a238a6 3137 if(!c) a=addr;
2002a1db 3138#endif
57871462 3139 //gen_tlb_addr_w(temp,map);
3140 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3141 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3142 }
3143 type=STOREB_STUB;
3144 }
3145 if (opcode[i]==0x29) { // SH
3146 if(!c||memtarget) {
97a238a6 3147 int x=0,a=temp;
2002a1db 3148#ifdef BIG_ENDIAN_MIPS
57871462 3149 if(!c) emit_xorimm(addr,2,temp);
3150 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3151#else
97a238a6 3152 if(!c) a=addr;
2002a1db 3153#endif
57871462 3154 //#ifdef
3155 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3156 //#else
3157 if(map>=0) {
97a238a6 3158 gen_tlb_addr_w(a,map);
3159 emit_writehword_indexed(tl,x,a);
57871462 3160 }else
97a238a6 3161 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3162 }
3163 type=STOREH_STUB;
3164 }
3165 if (opcode[i]==0x2B) { // SW
3166 if(!c||memtarget)
3167 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3169 type=STOREW_STUB;
3170 }
3171 if (opcode[i]==0x3F) { // SD
3172 if(!c||memtarget) {
3173 if(rs2[i]) {
3174 assert(th>=0);
3175 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3178 }else{
3179 // Store zero
3180 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3183 }
3184 }
3185 type=STORED_STUB;
3186 }
57871462 3187 if(!using_tlb) {
3188 if(!c||memtarget) {
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3192 addr=temp;
3193 #endif
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3196 assert(ir>=0);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198 #else
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200 #endif
0bbd1454 3201 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3202 emit_callne(invalidate_addr_reg[addr]);
3203 #else
57871462 3204 jaddr2=(int)out;
3205 emit_jne(0);
3206 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3207 #endif
57871462 3208 }
3209 }
3eaa7048 3210 if(jaddr) {
3211 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3212 } else if(c&&!memtarget) {
3213 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3214 }
57871462 3215 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3216 //if(opcode[i]==0x2B || opcode[i]==0x28)
3217 //if(opcode[i]==0x2B || opcode[i]==0x29)
3218 //if(opcode[i]==0x2B)
3219 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3220 {
3221 //emit_pusha();
3222 save_regs(0x100f);
3223 emit_readword((int)&last_count,ECX);
3224 #ifdef __i386__
3225 if(get_reg(i_regs->regmap,CCREG)<0)
3226 emit_loadreg(CCREG,HOST_CCREG);
3227 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3228 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3229 emit_writeword(HOST_CCREG,(int)&Count);
3230 #endif
3231 #ifdef __arm__
3232 if(get_reg(i_regs->regmap,CCREG)<0)
3233 emit_loadreg(CCREG,0);
3234 else
3235 emit_mov(HOST_CCREG,0);
3236 emit_add(0,ECX,0);
3237 emit_addimm(0,2*ccadj[i],0);
3238 emit_writeword(0,(int)&Count);
3239 #endif
3240 emit_call((int)memdebug);
3241 //emit_popa();
3242 restore_regs(0x100f);
3243 }/**/
3244}
3245
3246void storelr_assemble(int i,struct regstat *i_regs)
3247{
3248 int s,th,tl;
3249 int temp;
3250 int temp2;
3251 int offset;
3252 int jaddr=0,jaddr2;
3253 int case1,case2,case3;
3254 int done0,done1,done2;
3255 int memtarget,c=0;
fab5d06d 3256 int agr=AGEN1+(i&1);
57871462 3257 u_int hr,reglist=0;
3258 th=get_reg(i_regs->regmap,rs2[i]|64);
3259 tl=get_reg(i_regs->regmap,rs2[i]);
3260 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3261 temp=get_reg(i_regs->regmap,agr);
3262 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3263 offset=imm[i];
3264 if(s>=0) {
3265 c=(i_regs->isconst>>s)&1;
4cb76aa4 3266 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3267 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3268 }
3269 assert(tl>=0);
3270 for(hr=0;hr<HOST_REGS;hr++) {
3271 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3272 }
535d208a 3273 assert(temp>=0);
3274 if(!using_tlb) {
3275 if(!c) {
3276 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3277 if(!offset&&s!=temp) emit_mov(s,temp);
3278 jaddr=(int)out;
3279 emit_jno(0);
3280 }
3281 else
3282 {
3283 if(!memtarget||!rs1[i]) {
57871462 3284 jaddr=(int)out;
3285 emit_jmp(0);
3286 }
57871462 3287 }
535d208a 3288 #ifdef RAM_OFFSET
3289 int map=get_reg(i_regs->regmap,ROREG);
3290 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3291 gen_tlb_addr_w(temp,map);
3292 #else
3293 if((u_int)rdram!=0x80000000)
3294 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3295 #endif
3296 }else{ // using tlb
3297 int map=get_reg(i_regs->regmap,TLREG);
3298 assert(map>=0);
3299 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3300 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3301 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3302 if(!jaddr&&!memtarget) {
3303 jaddr=(int)out;
3304 emit_jmp(0);
57871462 3305 }
535d208a 3306 gen_tlb_addr_w(temp,map);
3307 }
3308
3309 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3310 temp2=get_reg(i_regs->regmap,FTEMP);
3311 if(!rs2[i]) temp2=th=tl;
3312 }
57871462 3313
2002a1db 3314#ifndef BIG_ENDIAN_MIPS
3315 emit_xorimm(temp,3,temp);
3316#endif
535d208a 3317 emit_testimm(temp,2);
3318 case2=(int)out;
3319 emit_jne(0);
3320 emit_testimm(temp,1);
3321 case1=(int)out;
3322 emit_jne(0);
3323 // 0
3324 if (opcode[i]==0x2A) { // SWL
3325 emit_writeword_indexed(tl,0,temp);
3326 }
3327 if (opcode[i]==0x2E) { // SWR
3328 emit_writebyte_indexed(tl,3,temp);
3329 }
3330 if (opcode[i]==0x2C) { // SDL
3331 emit_writeword_indexed(th,0,temp);
3332 if(rs2[i]) emit_mov(tl,temp2);
3333 }
3334 if (opcode[i]==0x2D) { // SDR
3335 emit_writebyte_indexed(tl,3,temp);
3336 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3337 }
3338 done0=(int)out;
3339 emit_jmp(0);
3340 // 1
3341 set_jump_target(case1,(int)out);
3342 if (opcode[i]==0x2A) { // SWL
3343 // Write 3 msb into three least significant bytes
3344 if(rs2[i]) emit_rorimm(tl,8,tl);
3345 emit_writehword_indexed(tl,-1,temp);
3346 if(rs2[i]) emit_rorimm(tl,16,tl);
3347 emit_writebyte_indexed(tl,1,temp);
3348 if(rs2[i]) emit_rorimm(tl,8,tl);
3349 }
3350 if (opcode[i]==0x2E) { // SWR
3351 // Write two lsb into two most significant bytes
3352 emit_writehword_indexed(tl,1,temp);
3353 }
3354 if (opcode[i]==0x2C) { // SDL
3355 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3356 // Write 3 msb into three least significant bytes
3357 if(rs2[i]) emit_rorimm(th,8,th);
3358 emit_writehword_indexed(th,-1,temp);
3359 if(rs2[i]) emit_rorimm(th,16,th);
3360 emit_writebyte_indexed(th,1,temp);
3361 if(rs2[i]) emit_rorimm(th,8,th);
3362 }
3363 if (opcode[i]==0x2D) { // SDR
3364 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3365 // Write two lsb into two most significant bytes
3366 emit_writehword_indexed(tl,1,temp);
3367 }
3368 done1=(int)out;
3369 emit_jmp(0);
3370 // 2
3371 set_jump_target(case2,(int)out);
3372 emit_testimm(temp,1);
3373 case3=(int)out;
3374 emit_jne(0);
3375 if (opcode[i]==0x2A) { // SWL
3376 // Write two msb into two least significant bytes
3377 if(rs2[i]) emit_rorimm(tl,16,tl);
3378 emit_writehword_indexed(tl,-2,temp);
3379 if(rs2[i]) emit_rorimm(tl,16,tl);
3380 }
3381 if (opcode[i]==0x2E) { // SWR
3382 // Write 3 lsb into three most significant bytes
3383 emit_writebyte_indexed(tl,-1,temp);
3384 if(rs2[i]) emit_rorimm(tl,8,tl);
3385 emit_writehword_indexed(tl,0,temp);
3386 if(rs2[i]) emit_rorimm(tl,24,tl);
3387 }
3388 if (opcode[i]==0x2C) { // SDL
3389 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3390 // Write two msb into two least significant bytes
3391 if(rs2[i]) emit_rorimm(th,16,th);
3392 emit_writehword_indexed(th,-2,temp);
3393 if(rs2[i]) emit_rorimm(th,16,th);
3394 }
3395 if (opcode[i]==0x2D) { // SDR
3396 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3397 // Write 3 lsb into three most significant bytes
3398 emit_writebyte_indexed(tl,-1,temp);
3399 if(rs2[i]) emit_rorimm(tl,8,tl);
3400 emit_writehword_indexed(tl,0,temp);
3401 if(rs2[i]) emit_rorimm(tl,24,tl);
3402 }
3403 done2=(int)out;
3404 emit_jmp(0);
3405 // 3
3406 set_jump_target(case3,(int)out);
3407 if (opcode[i]==0x2A) { // SWL
3408 // Write msb into least significant byte
3409 if(rs2[i]) emit_rorimm(tl,24,tl);
3410 emit_writebyte_indexed(tl,-3,temp);
3411 if(rs2[i]) emit_rorimm(tl,8,tl);
3412 }
3413 if (opcode[i]==0x2E) { // SWR
3414 // Write entire word
3415 emit_writeword_indexed(tl,-3,temp);
3416 }
3417 if (opcode[i]==0x2C) { // SDL
3418 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3419 // Write msb into least significant byte
3420 if(rs2[i]) emit_rorimm(th,24,th);
3421 emit_writebyte_indexed(th,-3,temp);
3422 if(rs2[i]) emit_rorimm(th,8,th);
3423 }
3424 if (opcode[i]==0x2D) { // SDR
3425 if(rs2[i]) emit_mov(th,temp2);
3426 // Write entire word
3427 emit_writeword_indexed(tl,-3,temp);
3428 }
3429 set_jump_target(done0,(int)out);
3430 set_jump_target(done1,(int)out);
3431 set_jump_target(done2,(int)out);
3432 if (opcode[i]==0x2C) { // SDL
3433 emit_testimm(temp,4);
57871462 3434 done0=(int)out;
57871462 3435 emit_jne(0);
535d208a 3436 emit_andimm(temp,~3,temp);
3437 emit_writeword_indexed(temp2,4,temp);
3438 set_jump_target(done0,(int)out);
3439 }
3440 if (opcode[i]==0x2D) { // SDR
3441 emit_testimm(temp,4);
3442 done0=(int)out;
3443 emit_jeq(0);
3444 emit_andimm(temp,~3,temp);
3445 emit_writeword_indexed(temp2,-4,temp);
57871462 3446 set_jump_target(done0,(int)out);
57871462 3447 }
535d208a 3448 if(!c||!memtarget)
3449 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3450 if(!using_tlb) {
535d208a 3451 #ifdef RAM_OFFSET
3452 int map=get_reg(i_regs->regmap,ROREG);
3453 if(map<0) map=HOST_TEMPREG;
3454 gen_orig_addr_w(temp,map);
3455 #else
57871462 3456 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3457 #endif
57871462 3458 #if defined(HOST_IMM8)
3459 int ir=get_reg(i_regs->regmap,INVCP);
3460 assert(ir>=0);
3461 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3462 #else
3463 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3464 #endif
535d208a 3465 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3466 emit_callne(invalidate_addr_reg[temp]);
3467 #else
57871462 3468 jaddr2=(int)out;
3469 emit_jne(0);
3470 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3471 #endif
57871462 3472 }
3473 /*
3474 emit_pusha();
3475 //save_regs(0x100f);
3476 emit_readword((int)&last_count,ECX);
3477 if(get_reg(i_regs->regmap,CCREG)<0)
3478 emit_loadreg(CCREG,HOST_CCREG);
3479 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3480 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3481 emit_writeword(HOST_CCREG,(int)&Count);
3482 emit_call((int)memdebug);
3483 emit_popa();
3484 //restore_regs(0x100f);
3485 /**/
3486}
3487
3488void c1ls_assemble(int i,struct regstat *i_regs)
3489{
3d624f89 3490#ifndef DISABLE_COP1
57871462 3491 int s,th,tl;
3492 int temp,ar;
3493 int map=-1;
3494 int offset;
3495 int c=0;
3496 int jaddr,jaddr2=0,jaddr3,type;
3497 int agr=AGEN1+(i&1);
3498 u_int hr,reglist=0;
3499 th=get_reg(i_regs->regmap,FTEMP|64);
3500 tl=get_reg(i_regs->regmap,FTEMP);
3501 s=get_reg(i_regs->regmap,rs1[i]);
3502 temp=get_reg(i_regs->regmap,agr);
3503 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3504 offset=imm[i];
3505 assert(tl>=0);
3506 assert(rs1[i]>0);
3507 assert(temp>=0);
3508 for(hr=0;hr<HOST_REGS;hr++) {
3509 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3510 }
3511 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3512 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3513 {
3514 // Loads use a temporary register which we need to save
3515 reglist|=1<<temp;
3516 }
3517 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3518 ar=temp;
3519 else // LWC1/LDC1
3520 ar=tl;
3521 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3522 //else c=(i_regs->wasconst>>s)&1;
3523 if(s>=0) c=(i_regs->wasconst>>s)&1;
3524 // Check cop1 unusable
3525 if(!cop1_usable) {
3526 signed char rs=get_reg(i_regs->regmap,CSREG);
3527 assert(rs>=0);
3528 emit_testimm(rs,0x20000000);
3529 jaddr=(int)out;
3530 emit_jeq(0);
3531 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3532 cop1_usable=1;
3533 }
3534 if (opcode[i]==0x39) { // SWC1 (get float address)
3535 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3536 }
3537 if (opcode[i]==0x3D) { // SDC1 (get double address)
3538 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3539 }
3540 // Generate address + offset
3541 if(!using_tlb) {
3542 if(!c)
4cb76aa4 3543 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3544 }
3545 else
3546 {
3547 map=get_reg(i_regs->regmap,TLREG);
3548 assert(map>=0);
3549 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3550 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3551 }
3552 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3553 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3554 }
3555 }
3556 if (opcode[i]==0x39) { // SWC1 (read float)
3557 emit_readword_indexed(0,tl,tl);
3558 }
3559 if (opcode[i]==0x3D) { // SDC1 (read double)
3560 emit_readword_indexed(4,tl,th);
3561 emit_readword_indexed(0,tl,tl);
3562 }
3563 if (opcode[i]==0x31) { // LWC1 (get target address)
3564 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3565 }
3566 if (opcode[i]==0x35) { // LDC1 (get target address)
3567 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3568 }
3569 if(!using_tlb) {
3570 if(!c) {
3571 jaddr2=(int)out;
3572 emit_jno(0);
3573 }
4cb76aa4 3574 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3575 jaddr2=(int)out;
3576 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3577 }
3578 #ifdef DESTRUCTIVE_SHIFT
3579 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3580 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3581 }
3582 #endif
3583 }else{
3584 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3585 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3586 }
3587 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3588 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3589 }
3590 }
3591 if (opcode[i]==0x31) { // LWC1
3592 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3593 //gen_tlb_addr_r(ar,map);
3594 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3595 #ifdef HOST_IMM_ADDR32
3596 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3597 else
3598 #endif
3599 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3600 type=LOADW_STUB;
3601 }
3602 if (opcode[i]==0x35) { // LDC1
3603 assert(th>=0);
3604 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3605 //gen_tlb_addr_r(ar,map);
3606 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3607 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3608 #ifdef HOST_IMM_ADDR32
3609 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3610 else
3611 #endif
3612 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3613 type=LOADD_STUB;
3614 }
3615 if (opcode[i]==0x39) { // SWC1
3616 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3617 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3618 type=STOREW_STUB;
3619 }
3620 if (opcode[i]==0x3D) { // SDC1
3621 assert(th>=0);
3622 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3623 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3624 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3625 type=STORED_STUB;
3626 }
3627 if(!using_tlb) {
3628 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3629 #ifndef DESTRUCTIVE_SHIFT
3630 temp=offset||c||s<0?ar:s;
3631 #endif
3632 #if defined(HOST_IMM8)
3633 int ir=get_reg(i_regs->regmap,INVCP);
3634 assert(ir>=0);
3635 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3636 #else
3637 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3638 #endif
0bbd1454 3639 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3640 emit_callne(invalidate_addr_reg[temp]);
3641 #else
57871462 3642 jaddr3=(int)out;
3643 emit_jne(0);
3644 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3645 #endif
57871462 3646 }
3647 }
3648 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3649 if (opcode[i]==0x31) { // LWC1 (write float)
3650 emit_writeword_indexed(tl,0,temp);
3651 }
3652 if (opcode[i]==0x35) { // LDC1 (write double)
3653 emit_writeword_indexed(th,4,temp);
3654 emit_writeword_indexed(tl,0,temp);
3655 }
3656 //if(opcode[i]==0x39)
3657 /*if(opcode[i]==0x39||opcode[i]==0x31)
3658 {
3659 emit_pusha();
3660 emit_readword((int)&last_count,ECX);
3661 if(get_reg(i_regs->regmap,CCREG)<0)
3662 emit_loadreg(CCREG,HOST_CCREG);
3663 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3664 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3665 emit_writeword(HOST_CCREG,(int)&Count);
3666 emit_call((int)memdebug);
3667 emit_popa();
3668 }/**/
3d624f89 3669#else
3670 cop1_unusable(i, i_regs);
3671#endif
57871462 3672}
3673
b9b61529 3674void c2ls_assemble(int i,struct regstat *i_regs)
3675{
3676 int s,tl;
3677 int ar;
3678 int offset;
1fd1aceb 3679 int memtarget=0,c=0;
b9b61529 3680 int jaddr,jaddr2=0,jaddr3,type;
3681 int agr=AGEN1+(i&1);
3682 u_int hr,reglist=0;
3683 u_int copr=(source[i]>>16)&0x1f;
3684 s=get_reg(i_regs->regmap,rs1[i]);
3685 tl=get_reg(i_regs->regmap,FTEMP);
3686 offset=imm[i];
3687 assert(rs1[i]>0);
3688 assert(tl>=0);
3689 assert(!using_tlb);
3690
3691 for(hr=0;hr<HOST_REGS;hr++) {
3692 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3693 }
3694 if(i_regs->regmap[HOST_CCREG]==CCREG)
3695 reglist&=~(1<<HOST_CCREG);
3696
3697 // get the address
3698 if (opcode[i]==0x3a) { // SWC2
3699 ar=get_reg(i_regs->regmap,agr);
3700 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3701 reglist|=1<<ar;
3702 } else { // LWC2
3703 ar=tl;
3704 }
1fd1aceb 3705 if(s>=0) c=(i_regs->wasconst>>s)&1;
3706 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3707 if (!offset&&!c&&s>=0) ar=s;
3708 assert(ar>=0);
3709
3710 if (opcode[i]==0x3a) { // SWC2
3711 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3712 type=STOREW_STUB;
b9b61529 3713 }
1fd1aceb 3714 else
b9b61529 3715 type=LOADW_STUB;
1fd1aceb 3716
3717 if(c&&!memtarget) {
3718 jaddr2=(int)out;
3719 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3720 }
1fd1aceb 3721 else {
3722 if(!c) {
3723 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3724 jaddr2=(int)out;
3725 emit_jno(0);
3726 }
3727 if (opcode[i]==0x32) { // LWC2
3728 #ifdef HOST_IMM_ADDR32
3729 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3730 else
3731 #endif
3732 emit_readword_indexed(0,ar,tl);
3733 }
3734 if (opcode[i]==0x3a) { // SWC2
3735 #ifdef DESTRUCTIVE_SHIFT
3736 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3737 #endif
3738 emit_writeword_indexed(tl,0,ar);
3739 }
b9b61529 3740 }
3741 if(jaddr2)
3742 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3743 if (opcode[i]==0x3a) { // SWC2
3744#if defined(HOST_IMM8)
3745 int ir=get_reg(i_regs->regmap,INVCP);
3746 assert(ir>=0);
3747 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3748#else
3749 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3750#endif
0bbd1454 3751 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3752 emit_callne(invalidate_addr_reg[ar]);
3753 #else
b9b61529 3754 jaddr3=(int)out;
3755 emit_jne(0);
3756 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3757 #endif
b9b61529 3758 }
3759 if (opcode[i]==0x32) { // LWC2
3760 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3761 }
3762}
3763
57871462 3764#ifndef multdiv_assemble
3765void multdiv_assemble(int i,struct regstat *i_regs)
3766{
3767 printf("Need multdiv_assemble for this architecture.\n");
3768 exit(1);
3769}
3770#endif
3771
3772void mov_assemble(int i,struct regstat *i_regs)
3773{
3774 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3775 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3776 if(rt1[i]) {
3777 signed char sh,sl,th,tl;
3778 th=get_reg(i_regs->regmap,rt1[i]|64);
3779 tl=get_reg(i_regs->regmap,rt1[i]);
3780 //assert(tl>=0);
3781 if(tl>=0) {
3782 sh=get_reg(i_regs->regmap,rs1[i]|64);
3783 sl=get_reg(i_regs->regmap,rs1[i]);
3784 if(sl>=0) emit_mov(sl,tl);
3785 else emit_loadreg(rs1[i],tl);
3786 if(th>=0) {
3787 if(sh>=0) emit_mov(sh,th);
3788 else emit_loadreg(rs1[i]|64,th);
3789 }
3790 }
3791 }
3792}
3793
3794#ifndef fconv_assemble
3795void fconv_assemble(int i,struct regstat *i_regs)
3796{
3797 printf("Need fconv_assemble for this architecture.\n");
3798 exit(1);
3799}
3800#endif
3801
3802#if 0
3803void float_assemble(int i,struct regstat *i_regs)
3804{
3805 printf("Need float_assemble for this architecture.\n");
3806 exit(1);
3807}
3808#endif
3809
3810void syscall_assemble(int i,struct regstat *i_regs)
3811{
3812 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3813 assert(ccreg==HOST_CCREG);
3814 assert(!is_delayslot);
3815 emit_movimm(start+i*4,EAX); // Get PC
3816 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3817 emit_jmp((int)jump_syscall_hle); // XXX
3818}
3819
3820void hlecall_assemble(int i,struct regstat *i_regs)
3821{
3822 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3823 assert(ccreg==HOST_CCREG);
3824 assert(!is_delayslot);
3825 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3826 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3827 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3828 emit_jmp((int)jump_hlecall);
57871462 3829}
3830
1e973cb0 3831void intcall_assemble(int i,struct regstat *i_regs)
3832{
3833 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3834 assert(ccreg==HOST_CCREG);
3835 assert(!is_delayslot);
3836 emit_movimm(start+i*4,0); // Get PC
3837 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3838 emit_jmp((int)jump_intcall);
3839}
3840
57871462 3841void ds_assemble(int i,struct regstat *i_regs)
3842{
3843 is_delayslot=1;
3844 switch(itype[i]) {
3845 case ALU:
3846 alu_assemble(i,i_regs);break;
3847 case IMM16:
3848 imm16_assemble(i,i_regs);break;
3849 case SHIFT:
3850 shift_assemble(i,i_regs);break;
3851 case SHIFTIMM:
3852 shiftimm_assemble(i,i_regs);break;
3853 case LOAD:
3854 load_assemble(i,i_regs);break;
3855 case LOADLR:
3856 loadlr_assemble(i,i_regs);break;
3857 case STORE:
3858 store_assemble(i,i_regs);break;
3859 case STORELR:
3860 storelr_assemble(i,i_regs);break;
3861 case COP0:
3862 cop0_assemble(i,i_regs);break;
3863 case COP1:
3864 cop1_assemble(i,i_regs);break;
3865 case C1LS:
3866 c1ls_assemble(i,i_regs);break;
b9b61529 3867 case COP2:
3868 cop2_assemble(i,i_regs);break;
3869 case C2LS:
3870 c2ls_assemble(i,i_regs);break;
3871 case C2OP:
3872 c2op_assemble(i,i_regs);break;
57871462 3873 case FCONV:
3874 fconv_assemble(i,i_regs);break;
3875 case FLOAT:
3876 float_assemble(i,i_regs);break;
3877 case FCOMP:
3878 fcomp_assemble(i,i_regs);break;
3879 case MULTDIV:
3880 multdiv_assemble(i,i_regs);break;
3881 case MOV:
3882 mov_assemble(i,i_regs);break;
3883 case SYSCALL:
7139f3c8 3884 case HLECALL:
1e973cb0 3885 case INTCALL:
57871462 3886 case SPAN:
3887 case UJUMP:
3888 case RJUMP:
3889 case CJUMP:
3890 case SJUMP:
3891 case FJUMP:
3892 printf("Jump in the delay slot. This is probably a bug.\n");
3893 }
3894 is_delayslot=0;
3895}
3896
3897// Is the branch target a valid internal jump?
3898int internal_branch(uint64_t i_is32,int addr)
3899{
3900 if(addr&1) return 0; // Indirect (register) jump
3901 if(addr>=start && addr<start+slen*4-4)
3902 {
3903 int t=(addr-start)>>2;
3904 // Delay slots are not valid branch targets
3905 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3906 // 64 -> 32 bit transition requires a recompile
3907 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3908 {
3909 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3910 else printf("optimizable: yes\n");
3911 }*/
3912 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3913#ifndef FORCE32
57871462 3914 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3915 else
3916#endif
3917 return 1;
57871462 3918 }
3919 return 0;
3920}
3921
3922#ifndef wb_invalidate
3923void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3924 uint64_t u,uint64_t uu)
3925{
3926 int hr;
3927 for(hr=0;hr<HOST_REGS;hr++) {
3928 if(hr!=EXCLUDE_REG) {
3929 if(pre[hr]!=entry[hr]) {
3930 if(pre[hr]>=0) {
3931 if((dirty>>hr)&1) {
3932 if(get_reg(entry,pre[hr])<0) {
3933 if(pre[hr]<64) {
3934 if(!((u>>pre[hr])&1)) {
3935 emit_storereg(pre[hr],hr);
3936 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3937 emit_sarimm(hr,31,hr);
3938 emit_storereg(pre[hr]|64,hr);
3939 }
3940 }
3941 }else{
3942 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3943 emit_storereg(pre[hr],hr);
3944 }
3945 }
3946 }
3947 }
3948 }
3949 }
3950 }
3951 }
3952 // Move from one register to another (no writeback)
3953 for(hr=0;hr<HOST_REGS;hr++) {
3954 if(hr!=EXCLUDE_REG) {
3955 if(pre[hr]!=entry[hr]) {
3956 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3957 int nr;
3958 if((nr=get_reg(entry,pre[hr]))>=0) {
3959 emit_mov(hr,nr);
3960 }
3961 }
3962 }
3963 }
3964 }
3965}
3966#endif
3967
3968// Load the specified registers
3969// This only loads the registers given as arguments because
3970// we don't want to load things that will be overwritten
3971void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3972{
3973 int hr;
3974 // Load 32-bit regs
3975 for(hr=0;hr<HOST_REGS;hr++) {
3976 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3977 if(entry[hr]!=regmap[hr]) {
3978 if(regmap[hr]==rs1||regmap[hr]==rs2)
3979 {
3980 if(regmap[hr]==0) {
3981 emit_zeroreg(hr);
3982 }
3983 else
3984 {
3985 emit_loadreg(regmap[hr],hr);
3986 }
3987 }
3988 }
3989 }
3990 }
3991 //Load 64-bit regs
3992 for(hr=0;hr<HOST_REGS;hr++) {
3993 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3994 if(entry[hr]!=regmap[hr]) {
3995 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3996 {
3997 assert(regmap[hr]!=64);
3998 if((is32>>(regmap[hr]&63))&1) {
3999 int lr=get_reg(regmap,regmap[hr]-64);
4000 if(lr>=0)
4001 emit_sarimm(lr,31,hr);
4002 else
4003 emit_loadreg(regmap[hr],hr);
4004 }
4005 else
4006 {
4007 emit_loadreg(regmap[hr],hr);
4008 }
4009 }
4010 }
4011 }
4012 }
4013}
4014
4015// Load registers prior to the start of a loop
4016// so that they are not loaded within the loop
4017static void loop_preload(signed char pre[],signed char entry[])
4018{
4019 int hr;
4020 for(hr=0;hr<HOST_REGS;hr++) {
4021 if(hr!=EXCLUDE_REG) {
4022 if(pre[hr]!=entry[hr]) {
4023 if(entry[hr]>=0) {
4024 if(get_reg(pre,entry[hr])<0) {
4025 assem_debug("loop preload:\n");
4026 //printf("loop preload: %d\n",hr);
4027 if(entry[hr]==0) {
4028 emit_zeroreg(hr);
4029 }
4030 else if(entry[hr]<TEMPREG)
4031 {
4032 emit_loadreg(entry[hr],hr);
4033 }
4034 else if(entry[hr]-64<TEMPREG)
4035 {
4036 emit_loadreg(entry[hr],hr);
4037 }
4038 }
4039 }
4040 }
4041 }
4042 }
4043}
4044
4045// Generate address for load/store instruction
b9b61529 4046// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4047void address_generation(int i,struct regstat *i_regs,signed char entry[])
4048{
b9b61529 4049 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
57871462 4050 int ra;
4051 int agr=AGEN1+(i&1);
4052 int mgr=MGEN1+(i&1);
4053 if(itype[i]==LOAD) {
4054 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4055 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4056 assert(ra>=0);
57871462 4057 }
4058 if(itype[i]==LOADLR) {
4059 ra=get_reg(i_regs->regmap,FTEMP);
4060 }
4061 if(itype[i]==STORE||itype[i]==STORELR) {
4062 ra=get_reg(i_regs->regmap,agr);
4063 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4064 }
b9b61529 4065 if(itype[i]==C1LS||itype[i]==C2LS) {
4066 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4067 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4068 else { // SWC1/SDC1/SWC2/SDC2
57871462 4069 ra=get_reg(i_regs->regmap,agr);
4070 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4071 }
4072 }
4073 int rs=get_reg(i_regs->regmap,rs1[i]);
4074 int rm=get_reg(i_regs->regmap,TLREG);
4075 if(ra>=0) {
4076 int offset=imm[i];
4077 int c=(i_regs->wasconst>>rs)&1;
4078 if(rs1[i]==0) {
4079 // Using r0 as a base address
4080 /*if(rm>=0) {
4081 if(!entry||entry[rm]!=mgr) {
4082 generate_map_const(offset,rm);
4083 } // else did it in the previous cycle
4084 }*/
4085 if(!entry||entry[ra]!=agr) {
4086 if (opcode[i]==0x22||opcode[i]==0x26) {
4087 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4088 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4089 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4090 }else{
4091 emit_movimm(offset,ra);
4092 }
4093 } // else did it in the previous cycle
4094 }
4095 else if(rs<0) {
4096 if(!entry||entry[ra]!=rs1[i])
4097 emit_loadreg(rs1[i],ra);
4098 //if(!entry||entry[ra]!=rs1[i])
4099 // printf("poor load scheduling!\n");
4100 }
4101 else if(c) {
4102 if(rm>=0) {
4103 if(!entry||entry[rm]!=mgr) {
b9b61529 4104 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4105 // Stores to memory go thru the mapper to detect self-modifying
4106 // code, loads don't.
4107 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4108 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4109 generate_map_const(constmap[i][rs]+offset,rm);
4110 }else{
4111 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4112 generate_map_const(constmap[i][rs]+offset,rm);
4113 }
4114 }
4115 }
4116 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4117 if(!entry||entry[ra]!=agr) {
4118 if (opcode[i]==0x22||opcode[i]==0x26) {
4119 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4120 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4121 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4122 }else{
4123 #ifdef HOST_IMM_ADDR32
b9b61529 4124 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4125 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4126 #endif
4127 emit_movimm(constmap[i][rs]+offset,ra);
4128 }
4129 } // else did it in the previous cycle
4130 } // else load_consts already did it
4131 }
4132 if(offset&&!c&&rs1[i]) {
4133 if(rs>=0) {
4134 emit_addimm(rs,offset,ra);
4135 }else{
4136 emit_addimm(ra,offset,ra);
4137 }
4138 }
4139 }
4140 }
4141 // Preload constants for next instruction
b9b61529 4142 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4143 int agr,ra;
4144 #ifndef HOST_IMM_ADDR32
4145 // Mapper entry
4146 agr=MGEN1+((i+1)&1);
4147 ra=get_reg(i_regs->regmap,agr);
4148 if(ra>=0) {
4149 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4150 int offset=imm[i+1];
4151 int c=(regs[i+1].wasconst>>rs)&1;
4152 if(c) {
b9b61529 4153 if(itype[i+1]==STORE||itype[i+1]==STORELR
4154 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4155 // Stores to memory go thru the mapper to detect self-modifying
4156 // code, loads don't.
4157 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4158 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4159 generate_map_const(constmap[i+1][rs]+offset,ra);
4160 }else{
4161 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4162 generate_map_const(constmap[i+1][rs]+offset,ra);
4163 }
4164 }
4165 /*else if(rs1[i]==0) {
4166 generate_map_const(offset,ra);
4167 }*/
4168 }
4169 #endif
4170 // Actual address
4171 agr=AGEN1+((i+1)&1);
4172 ra=get_reg(i_regs->regmap,agr);
4173 if(ra>=0) {
4174 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4175 int offset=imm[i+1];
4176 int c=(regs[i+1].wasconst>>rs)&1;
4177 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4178 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4179 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4180 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4181 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4182 }else{
4183 #ifdef HOST_IMM_ADDR32
b9b61529 4184 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4185 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4186 #endif
4187 emit_movimm(constmap[i+1][rs]+offset,ra);
4188 }
4189 }
4190 else if(rs1[i+1]==0) {
4191 // Using r0 as a base address
4192 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4193 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4194 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4195 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4196 }else{
4197 emit_movimm(offset,ra);
4198 }
4199 }
4200 }
4201 }
4202}
4203
4204int get_final_value(int hr, int i, int *value)
4205{
4206 int reg=regs[i].regmap[hr];
4207 while(i<slen-1) {
4208 if(regs[i+1].regmap[hr]!=reg) break;
4209 if(!((regs[i+1].isconst>>hr)&1)) break;
4210 if(bt[i+1]) break;
4211 i++;
4212 }
4213 if(i<slen-1) {
4214 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4215 *value=constmap[i][hr];
4216 return 1;
4217 }
4218 if(!bt[i+1]) {
4219 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4220 // Load in delay slot, out-of-order execution
4221 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4222 {
4223 #ifdef HOST_IMM_ADDR32
4224 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4225 #endif
4226 // Precompute load address
4227 *value=constmap[i][hr]+imm[i+2];
4228 return 1;
4229 }
4230 }
4231 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4232 {
4233 #ifdef HOST_IMM_ADDR32
4234 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4235 #endif
4236 // Precompute load address
4237 *value=constmap[i][hr]+imm[i+1];
4238 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4239 return 1;
4240 }
4241 }
4242 }
4243 *value=constmap[i][hr];
4244 //printf("c=%x\n",(int)constmap[i][hr]);
4245 if(i==slen-1) return 1;
4246 if(reg<64) {
4247 return !((unneeded_reg[i+1]>>reg)&1);
4248 }else{
4249 return !((unneeded_reg_upper[i+1]>>reg)&1);
4250 }
4251}
4252
4253// Load registers with known constants
4254void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4255{
4256 int hr;
4257 // Load 32-bit regs
4258 for(hr=0;hr<HOST_REGS;hr++) {
4259 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4260 //if(entry[hr]!=regmap[hr]) {
4261 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4262 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4263 int value;
4264 if(get_final_value(hr,i,&value)) {
4265 if(value==0) {
4266 emit_zeroreg(hr);
4267 }
4268 else {
4269 emit_movimm(value,hr);
4270 }
4271 }
4272 }
4273 }
4274 }
4275 }
4276 // Load 64-bit regs
4277 for(hr=0;hr<HOST_REGS;hr++) {
4278 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4279 //if(entry[hr]!=regmap[hr]) {
4280 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4281 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4282 if((is32>>(regmap[hr]&63))&1) {
4283 int lr=get_reg(regmap,regmap[hr]-64);
4284 assert(lr>=0);
4285 emit_sarimm(lr,31,hr);
4286 }
4287 else
4288 {
4289 int value;
4290 if(get_final_value(hr,i,&value)) {
4291 if(value==0) {
4292 emit_zeroreg(hr);
4293 }
4294 else {
4295 emit_movimm(value,hr);
4296 }
4297 }
4298 }
4299 }
4300 }
4301 }
4302 }
4303}
4304void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4305{
4306 int hr;
4307 // Load 32-bit regs
4308 for(hr=0;hr<HOST_REGS;hr++) {
4309 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4310 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4311 int value=constmap[i][hr];
4312 if(value==0) {
4313 emit_zeroreg(hr);
4314 }
4315 else {
4316 emit_movimm(value,hr);
4317 }
4318 }
4319 }
4320 }
4321 // Load 64-bit regs
4322 for(hr=0;hr<HOST_REGS;hr++) {
4323 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4324 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4325 if((is32>>(regmap[hr]&63))&1) {
4326 int lr=get_reg(regmap,regmap[hr]-64);
4327 assert(lr>=0);
4328 emit_sarimm(lr,31,hr);
4329 }
4330 else
4331 {
4332 int value=constmap[i][hr];
4333 if(value==0) {
4334 emit_zeroreg(hr);
4335 }
4336 else {
4337 emit_movimm(value,hr);
4338 }
4339 }
4340 }
4341 }
4342 }
4343}
4344
4345// Write out all dirty registers (except cycle count)
4346void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4347{
4348 int hr;
4349 for(hr=0;hr<HOST_REGS;hr++) {
4350 if(hr!=EXCLUDE_REG) {
4351 if(i_regmap[hr]>0) {
4352 if(i_regmap[hr]!=CCREG) {
4353 if((i_dirty>>hr)&1) {
4354 if(i_regmap[hr]<64) {
4355 emit_storereg(i_regmap[hr],hr);
24385cae 4356#ifndef FORCE32
57871462 4357 if( ((i_is32>>i_regmap[hr])&1) ) {
4358 #ifdef DESTRUCTIVE_WRITEBACK
4359 emit_sarimm(hr,31,hr);
4360 emit_storereg(i_regmap[hr]|64,hr);
4361 #else
4362 emit_sarimm(hr,31,HOST_TEMPREG);
4363 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4364 #endif
4365 }
24385cae 4366#endif
57871462 4367 }else{
4368 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4369 emit_storereg(i_regmap[hr],hr);
4370 }
4371 }
4372 }
4373 }
4374 }
4375 }
4376 }
4377}
4378// Write out dirty registers that we need to reload (pair with load_needed_regs)
4379// This writes the registers not written by store_regs_bt
4380void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4381{
4382 int hr;
4383 int t=(addr-start)>>2;
4384 for(hr=0;hr<HOST_REGS;hr++) {
4385 if(hr!=EXCLUDE_REG) {
4386 if(i_regmap[hr]>0) {
4387 if(i_regmap[hr]!=CCREG) {
4388 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4389 if((i_dirty>>hr)&1) {
4390 if(i_regmap[hr]<64) {
4391 emit_storereg(i_regmap[hr],hr);
24385cae 4392#ifndef FORCE32
57871462 4393 if( ((i_is32>>i_regmap[hr])&1) ) {
4394 #ifdef DESTRUCTIVE_WRITEBACK
4395 emit_sarimm(hr,31,hr);
4396 emit_storereg(i_regmap[hr]|64,hr);
4397 #else
4398 emit_sarimm(hr,31,HOST_TEMPREG);
4399 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4400 #endif
4401 }
24385cae 4402#endif
57871462 4403 }else{
4404 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4405 emit_storereg(i_regmap[hr],hr);
4406 }
4407 }
4408 }
4409 }
4410 }
4411 }
4412 }
4413 }
4414}
4415
4416// Load all registers (except cycle count)
4417void load_all_regs(signed char i_regmap[])
4418{
4419 int hr;
4420 for(hr=0;hr<HOST_REGS;hr++) {
4421 if(hr!=EXCLUDE_REG) {
4422 if(i_regmap[hr]==0) {
4423 emit_zeroreg(hr);
4424 }
4425 else
4426 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4427 {
4428 emit_loadreg(i_regmap[hr],hr);
4429 }
4430 }
4431 }
4432}
4433
4434// Load all current registers also needed by next instruction
4435void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4436{
4437 int hr;
4438 for(hr=0;hr<HOST_REGS;hr++) {
4439 if(hr!=EXCLUDE_REG) {
4440 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4441 if(i_regmap[hr]==0) {
4442 emit_zeroreg(hr);
4443 }
4444 else
4445 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4446 {
4447 emit_loadreg(i_regmap[hr],hr);
4448 }
4449 }
4450 }
4451 }
4452}
4453
4454// Load all regs, storing cycle count if necessary
4455void load_regs_entry(int t)
4456{
4457 int hr;
4458 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4459 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4460 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4461 emit_storereg(CCREG,HOST_CCREG);
4462 }
4463 // Load 32-bit regs
4464 for(hr=0;hr<HOST_REGS;hr++) {
4465 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4466 if(regs[t].regmap_entry[hr]==0) {
4467 emit_zeroreg(hr);
4468 }
4469 else if(regs[t].regmap_entry[hr]!=CCREG)
4470 {
4471 emit_loadreg(regs[t].regmap_entry[hr],hr);
4472 }
4473 }
4474 }
4475 // Load 64-bit regs
4476 for(hr=0;hr<HOST_REGS;hr++) {
4477 if(regs[t].regmap_entry[hr]>=64) {
4478 assert(regs[t].regmap_entry[hr]!=64);
4479 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4480 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4481 if(lr<0) {
4482 emit_loadreg(regs[t].regmap_entry[hr],hr);
4483 }
4484 else
4485 {
4486 emit_sarimm(lr,31,hr);
4487 }
4488 }
4489 else
4490 {
4491 emit_loadreg(regs[t].regmap_entry[hr],hr);
4492 }
4493 }
4494 }
4495}
4496
4497// Store dirty registers prior to branch
4498void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4499{
4500 if(internal_branch(i_is32,addr))
4501 {
4502 int t=(addr-start)>>2;
4503 int hr;
4504 for(hr=0;hr<HOST_REGS;hr++) {
4505 if(hr!=EXCLUDE_REG) {
4506 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4507 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4508 if((i_dirty>>hr)&1) {
4509 if(i_regmap[hr]<64) {
4510 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4511 emit_storereg(i_regmap[hr],hr);
4512 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4513 #ifdef DESTRUCTIVE_WRITEBACK
4514 emit_sarimm(hr,31,hr);
4515 emit_storereg(i_regmap[hr]|64,hr);
4516 #else
4517 emit_sarimm(hr,31,HOST_TEMPREG);
4518 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4519 #endif
4520 }
4521 }
4522 }else{
4523 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4524 emit_storereg(i_regmap[hr],hr);
4525 }
4526 }
4527 }
4528 }
4529 }
4530 }
4531 }
4532 }
4533 else
4534 {
4535 // Branch out of this block, write out all dirty regs
4536 wb_dirtys(i_regmap,i_is32,i_dirty);
4537 }
4538}
4539
4540// Load all needed registers for branch target
4541void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4542{
4543 //if(addr>=start && addr<(start+slen*4))
4544 if(internal_branch(i_is32,addr))
4545 {
4546 int t=(addr-start)>>2;
4547 int hr;
4548 // Store the cycle count before loading something else
4549 if(i_regmap[HOST_CCREG]!=CCREG) {
4550 assert(i_regmap[HOST_CCREG]==-1);
4551 }
4552 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4553 emit_storereg(CCREG,HOST_CCREG);
4554 }
4555 // Load 32-bit regs
4556 for(hr=0;hr<HOST_REGS;hr++) {
4557 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4558 #ifdef DESTRUCTIVE_WRITEBACK
4559 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4560 #else
4561 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4562 #endif
4563 if(regs[t].regmap_entry[hr]==0) {
4564 emit_zeroreg(hr);
4565 }
4566 else if(regs[t].regmap_entry[hr]!=CCREG)
4567 {
4568 emit_loadreg(regs[t].regmap_entry[hr],hr);
4569 }
4570 }
4571 }
4572 }
4573 //Load 64-bit regs
4574 for(hr=0;hr<HOST_REGS;hr++) {
4575 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4576 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4577 assert(regs[t].regmap_entry[hr]!=64);
4578 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4579 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4580 if(lr<0) {
4581 emit_loadreg(regs[t].regmap_entry[hr],hr);
4582 }
4583 else
4584 {
4585 emit_sarimm(lr,31,hr);
4586 }
4587 }
4588 else
4589 {
4590 emit_loadreg(regs[t].regmap_entry[hr],hr);
4591 }
4592 }
4593 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4594 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4595 assert(lr>=0);
4596 emit_sarimm(lr,31,hr);
4597 }
4598 }
4599 }
4600 }
4601}
4602
4603int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4604{
4605 if(addr>=start && addr<start+slen*4-4)
4606 {
4607 int t=(addr-start)>>2;
4608 int hr;
4609 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4610 for(hr=0;hr<HOST_REGS;hr++)
4611 {
4612 if(hr!=EXCLUDE_REG)
4613 {
4614 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4615 {
4616 if(regs[t].regmap_entry[hr]!=-1)
4617 {
4618 return 0;
4619 }
4620 else
4621 if((i_dirty>>hr)&1)
4622 {
4623 if(i_regmap[hr]<64)
4624 {
4625 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4626 return 0;
4627 }
4628 else
4629 {
4630 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4631 return 0;
4632 }
4633 }
4634 }
4635 else // Same register but is it 32-bit or dirty?
4636 if(i_regmap[hr]>=0)
4637 {
4638 if(!((regs[t].dirty>>hr)&1))
4639 {
4640 if((i_dirty>>hr)&1)
4641 {
4642 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4643 {
4644 //printf("%x: dirty no match\n",addr);
4645 return 0;
4646 }
4647 }
4648 }
4649 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4650 {
4651 //printf("%x: is32 no match\n",addr);
4652 return 0;
4653 }
4654 }
4655 }
4656 }
4657 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4658#ifndef FORCE32
57871462 4659 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4660#endif
57871462 4661 // Delay slots are not valid branch targets
4662 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4663 // Delay slots require additional processing, so do not match
4664 if(is_ds[t]) return 0;
4665 }
4666 else
4667 {
4668 int hr;
4669 for(hr=0;hr<HOST_REGS;hr++)
4670 {
4671 if(hr!=EXCLUDE_REG)
4672 {
4673 if(i_regmap[hr]>=0)
4674 {
4675 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4676 {
4677 if((i_dirty>>hr)&1)
4678 {
4679 return 0;
4680 }
4681 }
4682 }
4683 }
4684 }
4685 }
4686 return 1;
4687}
4688
4689// Used when a branch jumps into the delay slot of another branch
4690void ds_assemble_entry(int i)
4691{
4692 int t=(ba[i]-start)>>2;
4693 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4694 assem_debug("Assemble delay slot at %x\n",ba[i]);
4695 assem_debug("<->\n");
4696 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4697 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4698 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4699 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4700 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4701 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4702 cop1_usable=0;
4703 is_delayslot=0;
4704 switch(itype[t]) {
4705 case ALU:
4706 alu_assemble(t,&regs[t]);break;
4707 case IMM16:
4708 imm16_assemble(t,&regs[t]);break;
4709 case SHIFT:
4710 shift_assemble(t,&regs[t]);break;
4711 case SHIFTIMM:
4712 shiftimm_assemble(t,&regs[t]);break;
4713 case LOAD:
4714 load_assemble(t,&regs[t]);break;
4715 case LOADLR:
4716 loadlr_assemble(t,&regs[t]);break;
4717 case STORE:
4718 store_assemble(t,&regs[t]);break;
4719 case STORELR:
4720 storelr_assemble(t,&regs[t]);break;
4721 case COP0:
4722 cop0_assemble(t,&regs[t]);break;
4723 case COP1:
4724 cop1_assemble(t,&regs[t]);break;
4725 case C1LS:
4726 c1ls_assemble(t,&regs[t]);break;
b9b61529 4727 case COP2:
4728 cop2_assemble(t,&regs[t]);break;
4729 case C2LS:
4730 c2ls_assemble(t,&regs[t]);break;
4731 case C2OP:
4732 c2op_assemble(t,&regs[t]);break;
57871462 4733 case FCONV:
4734 fconv_assemble(t,&regs[t]);break;
4735 case FLOAT:
4736 float_assemble(t,&regs[t]);break;
4737 case FCOMP:
4738 fcomp_assemble(t,&regs[t]);break;
4739 case MULTDIV:
4740 multdiv_assemble(t,&regs[t]);break;
4741 case MOV:
4742 mov_assemble(t,&regs[t]);break;
4743 case SYSCALL:
7139f3c8 4744 case HLECALL:
1e973cb0 4745 case INTCALL:
57871462 4746 case SPAN:
4747 case UJUMP:
4748 case RJUMP:
4749 case CJUMP:
4750 case SJUMP:
4751 case FJUMP:
4752 printf("Jump in the delay slot. This is probably a bug.\n");
4753 }
4754 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4755 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4756 if(internal_branch(regs[t].is32,ba[i]+4))
4757 assem_debug("branch: internal\n");
4758 else
4759 assem_debug("branch: external\n");
4760 assert(internal_branch(regs[t].is32,ba[i]+4));
4761 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4762 emit_jmp(0);
4763}
4764
4765void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4766{
4767 int count;
4768 int jaddr;
4769 int idle=0;
4770 if(itype[i]==RJUMP)
4771 {
4772 *adj=0;
4773 }
4774 //if(ba[i]>=start && ba[i]<(start+slen*4))
4775 if(internal_branch(branch_regs[i].is32,ba[i]))
4776 {
4777 int t=(ba[i]-start)>>2;
4778 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4779 else *adj=ccadj[t];
4780 }
4781 else
4782 {
4783 *adj=0;
4784 }
4785 count=ccadj[i];
4786 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4787 // Idle loop
4788 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4789 idle=(int)out;
4790 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4791 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4792 jaddr=(int)out;
4793 emit_jmp(0);
4794 }
4795 else if(*adj==0||invert) {
4796 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4797 jaddr=(int)out;
4798 emit_jns(0);
4799 }
4800 else
4801 {
4802 emit_cmpimm(HOST_CCREG,-2*(count+2));
4803 jaddr=(int)out;
4804 emit_jns(0);
4805 }
4806 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4807}
4808
4809void do_ccstub(int n)
4810{
4811 literal_pool(256);
4812 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4813 set_jump_target(stubs[n][1],(int)out);
4814 int i=stubs[n][4];
4815 if(stubs[n][6]==NULLDS) {
4816 // Delay slot instruction is nullified ("likely" branch)
4817 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4818 }
4819 else if(stubs[n][6]!=TAKEN) {
4820 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4821 }
4822 else {
4823 if(internal_branch(branch_regs[i].is32,ba[i]))
4824 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4825 }
4826 if(stubs[n][5]!=-1)
4827 {
4828 // Save PC as return address
4829 emit_movimm(stubs[n][5],EAX);
4830 emit_writeword(EAX,(int)&pcaddr);
4831 }
4832 else
4833 {
4834 // Return address depends on which way the branch goes
4835 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4836 {
4837 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4838 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4839 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4840 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4841 if(rs1[i]==0)
4842 {
4843 s1l=s2l;s1h=s2h;
4844 s2l=s2h=-1;
4845 }
4846 else if(rs2[i]==0)
4847 {
4848 s2l=s2h=-1;
4849 }
4850 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4851 s1h=s2h=-1;
4852 }
4853 assert(s1l>=0);
4854 #ifdef DESTRUCTIVE_WRITEBACK
4855 if(rs1[i]) {
4856 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4857 emit_loadreg(rs1[i],s1l);
4858 }
4859 else {
4860 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4861 emit_loadreg(rs2[i],s1l);
4862 }
4863 if(s2l>=0)
4864 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4865 emit_loadreg(rs2[i],s2l);
4866 #endif
4867 int hr=0;
4868 int addr,alt,ntaddr;
4869 while(hr<HOST_REGS)
4870 {
4871 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4872 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4873 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4874 {
4875 addr=hr++;break;
4876 }
4877 hr++;
4878 }
4879 while(hr<HOST_REGS)
4880 {
4881 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4882 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4883 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4884 {
4885 alt=hr++;break;
4886 }
4887 hr++;
4888 }
4889 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4890 {
4891 while(hr<HOST_REGS)
4892 {
4893 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4894 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4895 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4896 {
4897 ntaddr=hr;break;
4898 }
4899 hr++;
4900 }
4901 assert(hr<HOST_REGS);
4902 }
4903 if((opcode[i]&0x2f)==4) // BEQ
4904 {
4905 #ifdef HAVE_CMOV_IMM
4906 if(s1h<0) {
4907 if(s2l>=0) emit_cmp(s1l,s2l);
4908 else emit_test(s1l,s1l);
4909 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4910 }
4911 else
4912 #endif
4913 {
4914 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4915 if(s1h>=0) {
4916 if(s2h>=0) emit_cmp(s1h,s2h);
4917 else emit_test(s1h,s1h);
4918 emit_cmovne_reg(alt,addr);
4919 }
4920 if(s2l>=0) emit_cmp(s1l,s2l);
4921 else emit_test(s1l,s1l);
4922 emit_cmovne_reg(alt,addr);
4923 }
4924 }
4925 if((opcode[i]&0x2f)==5) // BNE
4926 {
4927 #ifdef HAVE_CMOV_IMM
4928 if(s1h<0) {
4929 if(s2l>=0) emit_cmp(s1l,s2l);
4930 else emit_test(s1l,s1l);
4931 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4932 }
4933 else
4934 #endif
4935 {
4936 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4937 if(s1h>=0) {
4938 if(s2h>=0) emit_cmp(s1h,s2h);
4939 else emit_test(s1h,s1h);
4940 emit_cmovne_reg(alt,addr);
4941 }
4942 if(s2l>=0) emit_cmp(s1l,s2l);
4943 else emit_test(s1l,s1l);
4944 emit_cmovne_reg(alt,addr);
4945 }
4946 }
4947 if((opcode[i]&0x2f)==6) // BLEZ
4948 {
4949 //emit_movimm(ba[i],alt);
4950 //emit_movimm(start+i*4+8,addr);
4951 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4952 emit_cmpimm(s1l,1);
4953 if(s1h>=0) emit_mov(addr,ntaddr);
4954 emit_cmovl_reg(alt,addr);
4955 if(s1h>=0) {
4956 emit_test(s1h,s1h);
4957 emit_cmovne_reg(ntaddr,addr);
4958 emit_cmovs_reg(alt,addr);
4959 }
4960 }
4961 if((opcode[i]&0x2f)==7) // BGTZ
4962 {
4963 //emit_movimm(ba[i],addr);
4964 //emit_movimm(start+i*4+8,ntaddr);
4965 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4966 emit_cmpimm(s1l,1);
4967 if(s1h>=0) emit_mov(addr,alt);
4968 emit_cmovl_reg(ntaddr,addr);
4969 if(s1h>=0) {
4970 emit_test(s1h,s1h);
4971 emit_cmovne_reg(alt,addr);
4972 emit_cmovs_reg(ntaddr,addr);
4973 }
4974 }
4975 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4976 {
4977 //emit_movimm(ba[i],alt);
4978 //emit_movimm(start+i*4+8,addr);
4979 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4980 if(s1h>=0) emit_test(s1h,s1h);
4981 else emit_test(s1l,s1l);
4982 emit_cmovs_reg(alt,addr);
4983 }
4984 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4985 {
4986 //emit_movimm(ba[i],addr);
4987 //emit_movimm(start+i*4+8,alt);
4988 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4989 if(s1h>=0) emit_test(s1h,s1h);
4990 else emit_test(s1l,s1l);
4991 emit_cmovs_reg(alt,addr);
4992 }
4993 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4994 if(source[i]&0x10000) // BC1T
4995 {
4996 //emit_movimm(ba[i],alt);
4997 //emit_movimm(start+i*4+8,addr);
4998 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4999 emit_testimm(s1l,0x800000);
5000 emit_cmovne_reg(alt,addr);
5001 }
5002 else // BC1F
5003 {
5004 //emit_movimm(ba[i],addr);
5005 //emit_movimm(start+i*4+8,alt);
5006 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5007 emit_testimm(s1l,0x800000);
5008 emit_cmovne_reg(alt,addr);
5009 }
5010 }
5011 emit_writeword(addr,(int)&pcaddr);
5012 }
5013 else
5014 if(itype[i]==RJUMP)
5015 {
5016 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5017 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5018 r=get_reg(branch_regs[i].regmap,RTEMP);
5019 }
5020 emit_writeword(r,(int)&pcaddr);
5021 }
5022 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5023 }
5024 // Update cycle count
5025 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5026 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5027 emit_call((int)cc_interrupt);
5028 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5029 if(stubs[n][6]==TAKEN) {
5030 if(internal_branch(branch_regs[i].is32,ba[i]))
5031 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5032 else if(itype[i]==RJUMP) {
5033 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5034 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5035 else
5036 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5037 }
5038 }else if(stubs[n][6]==NOTTAKEN) {
5039 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5040 else load_all_regs(branch_regs[i].regmap);
5041 }else if(stubs[n][6]==NULLDS) {
5042 // Delay slot instruction is nullified ("likely" branch)
5043 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5044 else load_all_regs(regs[i].regmap);
5045 }else{
5046 load_all_regs(branch_regs[i].regmap);
5047 }
5048 emit_jmp(stubs[n][2]); // return address
5049
5050 /* This works but uses a lot of memory...
5051 emit_readword((int)&last_count,ECX);
5052 emit_add(HOST_CCREG,ECX,EAX);
5053 emit_writeword(EAX,(int)&Count);
5054 emit_call((int)gen_interupt);
5055 emit_readword((int)&Count,HOST_CCREG);
5056 emit_readword((int)&next_interupt,EAX);
5057 emit_readword((int)&pending_exception,EBX);
5058 emit_writeword(EAX,(int)&last_count);
5059 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5060 emit_test(EBX,EBX);
5061 int jne_instr=(int)out;
5062 emit_jne(0);
5063 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5064 load_all_regs(branch_regs[i].regmap);
5065 emit_jmp(stubs[n][2]); // return address
5066 set_jump_target(jne_instr,(int)out);
5067 emit_readword((int)&pcaddr,EAX);
5068 // Call get_addr_ht instead of doing the hash table here.
5069 // This code is executed infrequently and takes up a lot of space
5070 // so smaller is better.
5071 emit_storereg(CCREG,HOST_CCREG);
5072 emit_pushreg(EAX);
5073 emit_call((int)get_addr_ht);
5074 emit_loadreg(CCREG,HOST_CCREG);
5075 emit_addimm(ESP,4,ESP);
5076 emit_jmpreg(EAX);*/
5077}
5078
5079add_to_linker(int addr,int target,int ext)
5080{
5081 link_addr[linkcount][0]=addr;
5082 link_addr[linkcount][1]=target;
5083 link_addr[linkcount][2]=ext;
5084 linkcount++;
5085}
5086
5087void ujump_assemble(int i,struct regstat *i_regs)
5088{
5089 signed char *i_regmap=i_regs->regmap;
5090 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5091 address_generation(i+1,i_regs,regs[i].regmap_entry);
5092 #ifdef REG_PREFETCH
5093 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5094 if(rt1[i]==31&&temp>=0)
5095 {
5096 int return_address=start+i*4+8;
5097 if(get_reg(branch_regs[i].regmap,31)>0)
5098 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5099 }
5100 #endif
5101 ds_assemble(i+1,i_regs);
5102 uint64_t bc_unneeded=branch_regs[i].u;
5103 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5104 bc_unneeded|=1|(1LL<<rt1[i]);
5105 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5106 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5107 bc_unneeded,bc_unneeded_upper);
5108 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5109 if(rt1[i]==31) {
5110 int rt;
5111 unsigned int return_address;
5112 assert(rt1[i+1]!=31);
5113 assert(rt2[i+1]!=31);
5114 rt=get_reg(branch_regs[i].regmap,31);
5115 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5116 //assert(rt>=0);
5117 return_address=start+i*4+8;
5118 if(rt>=0) {
5119 #ifdef USE_MINI_HT
5120 if(internal_branch(branch_regs[i].is32,return_address)) {
5121 int temp=rt+1;
5122 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5123 branch_regs[i].regmap[temp]>=0)
5124 {
5125 temp=get_reg(branch_regs[i].regmap,-1);
5126 }
5127 #ifdef HOST_TEMPREG
5128 if(temp<0) temp=HOST_TEMPREG;
5129 #endif
5130 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5131 else emit_movimm(return_address,rt);
5132 }
5133 else
5134 #endif
5135 {
5136 #ifdef REG_PREFETCH
5137 if(temp>=0)
5138 {
5139 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5140 }
5141 #endif
5142 emit_movimm(return_address,rt); // PC into link register
5143 #ifdef IMM_PREFETCH
5144 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5145 #endif
5146 }
5147 }
5148 }
5149 int cc,adj;
5150 cc=get_reg(branch_regs[i].regmap,CCREG);
5151 assert(cc==HOST_CCREG);
5152 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5153 #ifdef REG_PREFETCH
5154 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5155 #endif
5156 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5157 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5158 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5159 if(internal_branch(branch_regs[i].is32,ba[i]))
5160 assem_debug("branch: internal\n");
5161 else
5162 assem_debug("branch: external\n");
5163 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5164 ds_assemble_entry(i);
5165 }
5166 else {
5167 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5168 emit_jmp(0);
5169 }
5170}
5171
5172void rjump_assemble(int i,struct regstat *i_regs)
5173{
5174 signed char *i_regmap=i_regs->regmap;
5175 int temp;
5176 int rs,cc,adj;
5177 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5178 assert(rs>=0);
5179 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5180 // Delay slot abuse, make a copy of the branch address register
5181 temp=get_reg(branch_regs[i].regmap,RTEMP);
5182 assert(temp>=0);
5183 assert(regs[i].regmap[temp]==RTEMP);
5184 emit_mov(rs,temp);
5185 rs=temp;
5186 }
5187 address_generation(i+1,i_regs,regs[i].regmap_entry);
5188 #ifdef REG_PREFETCH
5189 if(rt1[i]==31)
5190 {
5191 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5192 int return_address=start+i*4+8;
5193 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5194 }
5195 }
5196 #endif
5197 #ifdef USE_MINI_HT
5198 if(rs1[i]==31) {
5199 int rh=get_reg(regs[i].regmap,RHASH);
5200 if(rh>=0) do_preload_rhash(rh);
5201 }
5202 #endif
5203 ds_assemble(i+1,i_regs);
5204 uint64_t bc_unneeded=branch_regs[i].u;
5205 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5206 bc_unneeded|=1|(1LL<<rt1[i]);
5207 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5208 bc_unneeded&=~(1LL<<rs1[i]);
5209 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5210 bc_unneeded,bc_unneeded_upper);
5211 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5212 if(rt1[i]!=0) {
57871462 5213 int rt,return_address;
5067f341 5214 assert(rt1[i+1]!=rt1[i]);
5215 assert(rt2[i+1]!=rt1[i]);
5216 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5217 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5218 assert(rt>=0);
5219 return_address=start+i*4+8;
5220 #ifdef REG_PREFETCH
5221 if(temp>=0)
5222 {
5223 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5224 }
5225 #endif
5226 emit_movimm(return_address,rt); // PC into link register
5227 #ifdef IMM_PREFETCH
5228 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5229 #endif
5230 }
5231 cc=get_reg(branch_regs[i].regmap,CCREG);
5232 assert(cc==HOST_CCREG);
5233 #ifdef USE_MINI_HT
5234 int rh=get_reg(branch_regs[i].regmap,RHASH);
5235 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5236 if(rs1[i]==31) {
5237 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5238 do_preload_rhtbl(ht);
5239 do_rhash(rs,rh);
5240 }
5241 #endif
5242 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5243 #ifdef DESTRUCTIVE_WRITEBACK
5244 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5245 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5246 emit_loadreg(rs1[i],rs);
5247 }
5248 }
5249 #endif
5250 #ifdef REG_PREFETCH
5251 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5252 #endif
5253 #ifdef USE_MINI_HT
5254 if(rs1[i]==31) {
5255 do_miniht_load(ht,rh);
5256 }
5257 #endif
5258 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5259 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5260 //assert(adj==0);
5261 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5262 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5263 emit_jns(0);
5264 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5265 #ifdef USE_MINI_HT
5266 if(rs1[i]==31) {
5267 do_miniht_jump(rs,rh,ht);
5268 }
5269 else
5270 #endif
5271 {
5272 //if(rs!=EAX) emit_mov(rs,EAX);
5273 //emit_jmp((int)jump_vaddr_eax);
5274 emit_jmp(jump_vaddr_reg[rs]);
5275 }
5276 /* Check hash table
5277 temp=!rs;
5278 emit_mov(rs,temp);
5279 emit_shrimm(rs,16,rs);
5280 emit_xor(temp,rs,rs);
5281 emit_movzwl_reg(rs,rs);
5282 emit_shlimm(rs,4,rs);
5283 emit_cmpmem_indexed((int)hash_table,rs,temp);
5284 emit_jne((int)out+14);
5285 emit_readword_indexed((int)hash_table+4,rs,rs);
5286 emit_jmpreg(rs);
5287 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5288 emit_addimm_no_flags(8,rs);
5289 emit_jeq((int)out-17);
5290 // No hit on hash table, call compiler
5291 emit_pushreg(temp);
5292//DEBUG >
5293#ifdef DEBUG_CYCLE_COUNT
5294 emit_readword((int)&last_count,ECX);
5295 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5296 emit_readword((int)&next_interupt,ECX);
5297 emit_writeword(HOST_CCREG,(int)&Count);
5298 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5299 emit_writeword(ECX,(int)&last_count);
5300#endif
5301//DEBUG <
5302 emit_storereg(CCREG,HOST_CCREG);
5303 emit_call((int)get_addr);
5304 emit_loadreg(CCREG,HOST_CCREG);
5305 emit_addimm(ESP,4,ESP);
5306 emit_jmpreg(EAX);*/
5307 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5308 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5309 #endif
5310}
5311
5312void cjump_assemble(int i,struct regstat *i_regs)
5313{
5314 signed char *i_regmap=i_regs->regmap;
5315 int cc;
5316 int match;
5317 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5318 assem_debug("match=%d\n",match);
5319 int s1h,s1l,s2h,s2l;
5320 int prev_cop1_usable=cop1_usable;
5321 int unconditional=0,nop=0;
5322 int only32=0;
57871462 5323 int invert=0;
5324 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5325 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5326 if(!match) invert=1;
5327 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5328 if(i>(ba[i]-start)>>2) invert=1;
5329 #endif
e1190b87 5330
5331 if(ooo[i]) {
57871462 5332 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5333 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5334 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5335 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5336 }
5337 else {
5338 s1l=get_reg(i_regmap,rs1[i]);
5339 s1h=get_reg(i_regmap,rs1[i]|64);
5340 s2l=get_reg(i_regmap,rs2[i]);
5341 s2h=get_reg(i_regmap,rs2[i]|64);
5342 }
5343 if(rs1[i]==0&&rs2[i]==0)
5344 {
5345 if(opcode[i]&1) nop=1;
5346 else unconditional=1;
5347 //assert(opcode[i]!=5);
5348 //assert(opcode[i]!=7);
5349 //assert(opcode[i]!=0x15);
5350 //assert(opcode[i]!=0x17);
5351 }
5352 else if(rs1[i]==0)
5353 {
5354 s1l=s2l;s1h=s2h;
5355 s2l=s2h=-1;
5356 only32=(regs[i].was32>>rs2[i])&1;
5357 }
5358 else if(rs2[i]==0)
5359 {
5360 s2l=s2h=-1;
5361 only32=(regs[i].was32>>rs1[i])&1;
5362 }
5363 else {
5364 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5365 }
5366
e1190b87 5367 if(ooo[i]) {
57871462 5368 // Out of order execution (delay slot first)
5369 //printf("OOOE\n");
5370 address_generation(i+1,i_regs,regs[i].regmap_entry);
5371 ds_assemble(i+1,i_regs);
5372 int adj;
5373 uint64_t bc_unneeded=branch_regs[i].u;
5374 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5375 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5376 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5377 bc_unneeded|=1;
5378 bc_unneeded_upper|=1;
5379 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5380 bc_unneeded,bc_unneeded_upper);
5381 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5382 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5383 cc=get_reg(branch_regs[i].regmap,CCREG);
5384 assert(cc==HOST_CCREG);
5385 if(unconditional)
5386 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5387 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5388 //assem_debug("cycle count (adj)\n");
5389 if(unconditional) {
5390 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5391 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5392 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5393 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5394 if(internal)
5395 assem_debug("branch: internal\n");
5396 else
5397 assem_debug("branch: external\n");
5398 if(internal&&is_ds[(ba[i]-start)>>2]) {
5399 ds_assemble_entry(i);
5400 }
5401 else {
5402 add_to_linker((int)out,ba[i],internal);
5403 emit_jmp(0);
5404 }
5405 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5406 if(((u_int)out)&7) emit_addnop(0);
5407 #endif
5408 }
5409 }
5410 else if(nop) {
5411 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5412 int jaddr=(int)out;
5413 emit_jns(0);
5414 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5415 }
5416 else {
5417 int taken=0,nottaken=0,nottaken1=0;
5418 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5419 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5420 if(!only32)
5421 {
5422 assert(s1h>=0);
5423 if(opcode[i]==4) // BEQ
5424 {
5425 if(s2h>=0) emit_cmp(s1h,s2h);
5426 else emit_test(s1h,s1h);
5427 nottaken1=(int)out;
5428 emit_jne(1);
5429 }
5430 if(opcode[i]==5) // BNE
5431 {
5432 if(s2h>=0) emit_cmp(s1h,s2h);
5433 else emit_test(s1h,s1h);
5434 if(invert) taken=(int)out;
5435 else add_to_linker((int)out,ba[i],internal);
5436 emit_jne(0);
5437 }
5438 if(opcode[i]==6) // BLEZ
5439 {
5440 emit_test(s1h,s1h);
5441 if(invert) taken=(int)out;
5442 else add_to_linker((int)out,ba[i],internal);
5443 emit_js(0);
5444 nottaken1=(int)out;
5445 emit_jne(1);
5446 }
5447 if(opcode[i]==7) // BGTZ
5448 {
5449 emit_test(s1h,s1h);
5450 nottaken1=(int)out;
5451 emit_js(1);
5452 if(invert) taken=(int)out;
5453 else add_to_linker((int)out,ba[i],internal);
5454 emit_jne(0);
5455 }
5456 } // if(!only32)
5457
5458 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5459 assert(s1l>=0);
5460 if(opcode[i]==4) // BEQ
5461 {
5462 if(s2l>=0) emit_cmp(s1l,s2l);
5463 else emit_test(s1l,s1l);
5464 if(invert){
5465 nottaken=(int)out;
5466 emit_jne(1);
5467 }else{
5468 add_to_linker((int)out,ba[i],internal);
5469 emit_jeq(0);
5470 }
5471 }
5472 if(opcode[i]==5) // BNE
5473 {
5474 if(s2l>=0) emit_cmp(s1l,s2l);
5475 else emit_test(s1l,s1l);
5476 if(invert){
5477 nottaken=(int)out;
5478 emit_jeq(1);
5479 }else{
5480 add_to_linker((int)out,ba[i],internal);
5481 emit_jne(0);
5482 }
5483 }
5484 if(opcode[i]==6) // BLEZ
5485 {
5486 emit_cmpimm(s1l,1);
5487 if(invert){
5488 nottaken=(int)out;
5489 emit_jge(1);
5490 }else{
5491 add_to_linker((int)out,ba[i],internal);
5492 emit_jl(0);
5493 }
5494 }
5495 if(opcode[i]==7) // BGTZ
5496 {
5497 emit_cmpimm(s1l,1);
5498 if(invert){
5499 nottaken=(int)out;
5500 emit_jl(1);
5501 }else{
5502 add_to_linker((int)out,ba[i],internal);
5503 emit_jge(0);
5504 }
5505 }
5506 if(invert) {
5507 if(taken) set_jump_target(taken,(int)out);
5508 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5509 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5510 if(adj) {
5511 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5512 add_to_linker((int)out,ba[i],internal);
5513 }else{
5514 emit_addnop(13);
5515 add_to_linker((int)out,ba[i],internal*2);
5516 }
5517 emit_jmp(0);
5518 }else
5519 #endif
5520 {
5521 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5522 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5523 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5524 if(internal)
5525 assem_debug("branch: internal\n");
5526 else
5527 assem_debug("branch: external\n");
5528 if(internal&&is_ds[(ba[i]-start)>>2]) {
5529 ds_assemble_entry(i);
5530 }
5531 else {
5532 add_to_linker((int)out,ba[i],internal);
5533 emit_jmp(0);
5534 }
5535 }
5536 set_jump_target(nottaken,(int)out);
5537 }
5538
5539 if(nottaken1) set_jump_target(nottaken1,(int)out);
5540 if(adj) {
5541 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5542 }
5543 } // (!unconditional)
5544 } // if(ooo)
5545 else
5546 {
5547 // In-order execution (branch first)
5548 //if(likely[i]) printf("IOL\n");
5549 //else
5550 //printf("IOE\n");
5551 int taken=0,nottaken=0,nottaken1=0;
5552 if(!unconditional&&!nop) {
5553 if(!only32)
5554 {
5555 assert(s1h>=0);
5556 if((opcode[i]&0x2f)==4) // BEQ
5557 {
5558 if(s2h>=0) emit_cmp(s1h,s2h);
5559 else emit_test(s1h,s1h);
5560 nottaken1=(int)out;
5561 emit_jne(2);
5562 }
5563 if((opcode[i]&0x2f)==5) // BNE
5564 {
5565 if(s2h>=0) emit_cmp(s1h,s2h);
5566 else emit_test(s1h,s1h);
5567 taken=(int)out;
5568 emit_jne(1);
5569 }
5570 if((opcode[i]&0x2f)==6) // BLEZ
5571 {
5572 emit_test(s1h,s1h);
5573 taken=(int)out;
5574 emit_js(1);
5575 nottaken1=(int)out;
5576 emit_jne(2);
5577 }
5578 if((opcode[i]&0x2f)==7) // BGTZ
5579 {
5580 emit_test(s1h,s1h);
5581 nottaken1=(int)out;
5582 emit_js(2);
5583 taken=(int)out;
5584 emit_jne(1);
5585 }
5586 } // if(!only32)
5587
5588 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5589 assert(s1l>=0);
5590 if((opcode[i]&0x2f)==4) // BEQ
5591 {
5592 if(s2l>=0) emit_cmp(s1l,s2l);
5593 else emit_test(s1l,s1l);
5594 nottaken=(int)out;
5595 emit_jne(2);
5596 }
5597 if((opcode[i]&0x2f)==5) // BNE
5598 {
5599 if(s2l>=0) emit_cmp(s1l,s2l);
5600 else emit_test(s1l,s1l);
5601 nottaken=(int)out;
5602 emit_jeq(2);
5603 }
5604 if((opcode[i]&0x2f)==6) // BLEZ
5605 {
5606 emit_cmpimm(s1l,1);
5607 nottaken=(int)out;
5608 emit_jge(2);
5609 }
5610 if((opcode[i]&0x2f)==7) // BGTZ
5611 {
5612 emit_cmpimm(s1l,1);
5613 nottaken=(int)out;
5614 emit_jl(2);
5615 }
5616 } // if(!unconditional)
5617 int adj;
5618 uint64_t ds_unneeded=branch_regs[i].u;
5619 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5620 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5621 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5622 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5623 ds_unneeded|=1;
5624 ds_unneeded_upper|=1;
5625 // branch taken
5626 if(!nop) {
5627 if(taken) set_jump_target(taken,(int)out);
5628 assem_debug("1:\n");
5629 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5630 ds_unneeded,ds_unneeded_upper);
5631 // load regs
5632 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5633 address_generation(i+1,&branch_regs[i],0);
5634 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5635 ds_assemble(i+1,&branch_regs[i]);
5636 cc=get_reg(branch_regs[i].regmap,CCREG);
5637 if(cc==-1) {
5638 emit_loadreg(CCREG,cc=HOST_CCREG);
5639 // CHECK: Is the following instruction (fall thru) allocated ok?
5640 }
5641 assert(cc==HOST_CCREG);
5642 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5643 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5644 assem_debug("cycle count (adj)\n");
5645 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5646 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5647 if(internal)
5648 assem_debug("branch: internal\n");
5649 else
5650 assem_debug("branch: external\n");
5651 if(internal&&is_ds[(ba[i]-start)>>2]) {
5652 ds_assemble_entry(i);
5653 }
5654 else {
5655 add_to_linker((int)out,ba[i],internal);
5656 emit_jmp(0);
5657 }
5658 }
5659 // branch not taken
5660 cop1_usable=prev_cop1_usable;
5661 if(!unconditional) {
5662 if(nottaken1) set_jump_target(nottaken1,(int)out);
5663 set_jump_target(nottaken,(int)out);
5664 assem_debug("2:\n");
5665 if(!likely[i]) {
5666 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5667 ds_unneeded,ds_unneeded_upper);
5668 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5669 address_generation(i+1,&branch_regs[i],0);
5670 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5671 ds_assemble(i+1,&branch_regs[i]);
5672 }
5673 cc=get_reg(branch_regs[i].regmap,CCREG);
5674 if(cc==-1&&!likely[i]) {
5675 // Cycle count isn't in a register, temporarily load it then write it out
5676 emit_loadreg(CCREG,HOST_CCREG);
5677 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5678 int jaddr=(int)out;
5679 emit_jns(0);
5680 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5681 emit_storereg(CCREG,HOST_CCREG);
5682 }
5683 else{
5684 cc=get_reg(i_regmap,CCREG);
5685 assert(cc==HOST_CCREG);
5686 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5687 int jaddr=(int)out;
5688 emit_jns(0);
5689 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5690 }
5691 }
5692 }
5693}
5694
5695void sjump_assemble(int i,struct regstat *i_regs)
5696{
5697 signed char *i_regmap=i_regs->regmap;
5698 int cc;
5699 int match;
5700 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5701 assem_debug("smatch=%d\n",match);
5702 int s1h,s1l;
5703 int prev_cop1_usable=cop1_usable;
5704 int unconditional=0,nevertaken=0;
5705 int only32=0;
57871462 5706 int invert=0;
5707 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5708 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5709 if(!match) invert=1;
5710 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5711 if(i>(ba[i]-start)>>2) invert=1;
5712 #endif
5713
5714 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5715 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5716
e1190b87 5717 if(ooo[i]) {
57871462 5718 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5719 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5720 }
5721 else {
5722 s1l=get_reg(i_regmap,rs1[i]);
5723 s1h=get_reg(i_regmap,rs1[i]|64);
5724 }
5725 if(rs1[i]==0)
5726 {
5727 if(opcode2[i]&1) unconditional=1;
5728 else nevertaken=1;
5729 // These are never taken (r0 is never less than zero)
5730 //assert(opcode2[i]!=0);
5731 //assert(opcode2[i]!=2);
5732 //assert(opcode2[i]!=0x10);
5733 //assert(opcode2[i]!=0x12);
5734 }
5735 else {
5736 only32=(regs[i].was32>>rs1[i])&1;
5737 }
5738
e1190b87 5739 if(ooo[i]) {
57871462 5740 // Out of order execution (delay slot first)
5741 //printf("OOOE\n");
5742 address_generation(i+1,i_regs,regs[i].regmap_entry);
5743 ds_assemble(i+1,i_regs);
5744 int adj;
5745 uint64_t bc_unneeded=branch_regs[i].u;
5746 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5747 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5748 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5749 bc_unneeded|=1;
5750 bc_unneeded_upper|=1;
5751 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5752 bc_unneeded,bc_unneeded_upper);
5753 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5754 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5755 if(rt1[i]==31) {
5756 int rt,return_address;
57871462 5757 rt=get_reg(branch_regs[i].regmap,31);
5758 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5759 if(rt>=0) {
5760 // Save the PC even if the branch is not taken
5761 return_address=start+i*4+8;
5762 emit_movimm(return_address,rt); // PC into link register
5763 #ifdef IMM_PREFETCH
5764 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5765 #endif
5766 }
5767 }
5768 cc=get_reg(branch_regs[i].regmap,CCREG);
5769 assert(cc==HOST_CCREG);
5770 if(unconditional)
5771 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5772 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5773 assem_debug("cycle count (adj)\n");
5774 if(unconditional) {
5775 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5776 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5777 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5778 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5779 if(internal)
5780 assem_debug("branch: internal\n");
5781 else
5782 assem_debug("branch: external\n");
5783 if(internal&&is_ds[(ba[i]-start)>>2]) {
5784 ds_assemble_entry(i);
5785 }
5786 else {
5787 add_to_linker((int)out,ba[i],internal);
5788 emit_jmp(0);
5789 }
5790 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5791 if(((u_int)out)&7) emit_addnop(0);
5792 #endif
5793 }
5794 }
5795 else if(nevertaken) {
5796 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5797 int jaddr=(int)out;
5798 emit_jns(0);
5799 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5800 }
5801 else {
5802 int nottaken=0;
5803 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5804 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5805 if(!only32)
5806 {
5807 assert(s1h>=0);
df894a3a 5808 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5809 {
5810 emit_test(s1h,s1h);
5811 if(invert){
5812 nottaken=(int)out;
5813 emit_jns(1);
5814 }else{
5815 add_to_linker((int)out,ba[i],internal);
5816 emit_js(0);
5817 }
5818 }
df894a3a 5819 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5820 {
5821 emit_test(s1h,s1h);
5822 if(invert){
5823 nottaken=(int)out;
5824 emit_js(1);
5825 }else{
5826 add_to_linker((int)out,ba[i],internal);
5827 emit_jns(0);
5828 }
5829 }
5830 } // if(!only32)
5831 else
5832 {
5833 assert(s1l>=0);
df894a3a 5834 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5835 {
5836 emit_test(s1l,s1l);
5837 if(invert){
5838 nottaken=(int)out;
5839 emit_jns(1);
5840 }else{
5841 add_to_linker((int)out,ba[i],internal);
5842 emit_js(0);
5843 }
5844 }
df894a3a 5845 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5846 {
5847 emit_test(s1l,s1l);
5848 if(invert){
5849 nottaken=(int)out;
5850 emit_js(1);
5851 }else{
5852 add_to_linker((int)out,ba[i],internal);
5853 emit_jns(0);
5854 }
5855 }
5856 } // if(!only32)
5857
5858 if(invert) {
5859 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5860 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5861 if(adj) {
5862 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5863 add_to_linker((int)out,ba[i],internal);
5864 }else{
5865 emit_addnop(13);
5866 add_to_linker((int)out,ba[i],internal*2);
5867 }
5868 emit_jmp(0);
5869 }else
5870 #endif
5871 {
5872 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5873 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5874 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5875 if(internal)
5876 assem_debug("branch: internal\n");
5877 else
5878 assem_debug("branch: external\n");
5879 if(internal&&is_ds[(ba[i]-start)>>2]) {
5880 ds_assemble_entry(i);
5881 }
5882 else {
5883 add_to_linker((int)out,ba[i],internal);
5884 emit_jmp(0);
5885 }
5886 }
5887 set_jump_target(nottaken,(int)out);
5888 }
5889
5890 if(adj) {
5891 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5892 }
5893 } // (!unconditional)
5894 } // if(ooo)
5895 else
5896 {
5897 // In-order execution (branch first)
5898 //printf("IOE\n");
5899 int nottaken=0;
a6491170 5900 if(rt1[i]==31) {
5901 int rt,return_address;
a6491170 5902 rt=get_reg(branch_regs[i].regmap,31);
5903 if(rt>=0) {
5904 // Save the PC even if the branch is not taken
5905 return_address=start+i*4+8;
5906 emit_movimm(return_address,rt); // PC into link register
5907 #ifdef IMM_PREFETCH
5908 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5909 #endif
5910 }
5911 }
57871462 5912 if(!unconditional) {
5913 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5914 if(!only32)
5915 {
5916 assert(s1h>=0);
a6491170 5917 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5918 {
5919 emit_test(s1h,s1h);
5920 nottaken=(int)out;
5921 emit_jns(1);
5922 }
a6491170 5923 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5924 {
5925 emit_test(s1h,s1h);
5926 nottaken=(int)out;
5927 emit_js(1);
5928 }
5929 } // if(!only32)
5930 else
5931 {
5932 assert(s1l>=0);
a6491170 5933 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5934 {
5935 emit_test(s1l,s1l);
5936 nottaken=(int)out;
5937 emit_jns(1);
5938 }
a6491170 5939 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5940 {
5941 emit_test(s1l,s1l);
5942 nottaken=(int)out;
5943 emit_js(1);
5944 }
5945 }
5946 } // if(!unconditional)
5947 int adj;
5948 uint64_t ds_unneeded=branch_regs[i].u;
5949 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5950 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5951 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5952 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5953 ds_unneeded|=1;
5954 ds_unneeded_upper|=1;
5955 // branch taken
5956 if(!nevertaken) {
5957 //assem_debug("1:\n");
5958 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5959 ds_unneeded,ds_unneeded_upper);
5960 // load regs
5961 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5962 address_generation(i+1,&branch_regs[i],0);
5963 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5964 ds_assemble(i+1,&branch_regs[i]);
5965 cc=get_reg(branch_regs[i].regmap,CCREG);
5966 if(cc==-1) {
5967 emit_loadreg(CCREG,cc=HOST_CCREG);
5968 // CHECK: Is the following instruction (fall thru) allocated ok?
5969 }
5970 assert(cc==HOST_CCREG);
5971 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5972 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5973 assem_debug("cycle count (adj)\n");
5974 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5975 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5976 if(internal)
5977 assem_debug("branch: internal\n");
5978 else
5979 assem_debug("branch: external\n");
5980 if(internal&&is_ds[(ba[i]-start)>>2]) {
5981 ds_assemble_entry(i);
5982 }
5983 else {
5984 add_to_linker((int)out,ba[i],internal);
5985 emit_jmp(0);
5986 }
5987 }
5988 // branch not taken
5989 cop1_usable=prev_cop1_usable;
5990 if(!unconditional) {
5991 set_jump_target(nottaken,(int)out);
5992 assem_debug("1:\n");
5993 if(!likely[i]) {
5994 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5995 ds_unneeded,ds_unneeded_upper);
5996 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5997 address_generation(i+1,&branch_regs[i],0);
5998 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5999 ds_assemble(i+1,&branch_regs[i]);
6000 }
6001 cc=get_reg(branch_regs[i].regmap,CCREG);
6002 if(cc==-1&&!likely[i]) {
6003 // Cycle count isn't in a register, temporarily load it then write it out
6004 emit_loadreg(CCREG,HOST_CCREG);
6005 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6006 int jaddr=(int)out;
6007 emit_jns(0);
6008 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6009 emit_storereg(CCREG,HOST_CCREG);
6010 }
6011 else{
6012 cc=get_reg(i_regmap,CCREG);
6013 assert(cc==HOST_CCREG);
6014 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6015 int jaddr=(int)out;
6016 emit_jns(0);
6017 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6018 }
6019 }
6020 }
6021}
6022
6023void fjump_assemble(int i,struct regstat *i_regs)
6024{
6025 signed char *i_regmap=i_regs->regmap;
6026 int cc;
6027 int match;
6028 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6029 assem_debug("fmatch=%d\n",match);
6030 int fs,cs;
6031 int eaddr;
57871462 6032 int invert=0;
6033 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6034 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6035 if(!match) invert=1;
6036 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6037 if(i>(ba[i]-start)>>2) invert=1;
6038 #endif
6039
e1190b87 6040 if(ooo[i]) {
57871462 6041 fs=get_reg(branch_regs[i].regmap,FSREG);
6042 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6043 }
6044 else {
6045 fs=get_reg(i_regmap,FSREG);
6046 }
6047
6048 // Check cop1 unusable
6049 if(!cop1_usable) {
6050 cs=get_reg(i_regmap,CSREG);
6051 assert(cs>=0);
6052 emit_testimm(cs,0x20000000);
6053 eaddr=(int)out;
6054 emit_jeq(0);
6055 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6056 cop1_usable=1;
6057 }
6058
e1190b87 6059 if(ooo[i]) {
57871462 6060 // Out of order execution (delay slot first)
6061 //printf("OOOE\n");
6062 ds_assemble(i+1,i_regs);
6063 int adj;
6064 uint64_t bc_unneeded=branch_regs[i].u;
6065 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6066 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6067 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6068 bc_unneeded|=1;
6069 bc_unneeded_upper|=1;
6070 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6071 bc_unneeded,bc_unneeded_upper);
6072 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6073 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6074 cc=get_reg(branch_regs[i].regmap,CCREG);
6075 assert(cc==HOST_CCREG);
6076 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6077 assem_debug("cycle count (adj)\n");
6078 if(1) {
6079 int nottaken=0;
6080 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6081 if(1) {
6082 assert(fs>=0);
6083 emit_testimm(fs,0x800000);
6084 if(source[i]&0x10000) // BC1T
6085 {
6086 if(invert){
6087 nottaken=(int)out;
6088 emit_jeq(1);
6089 }else{
6090 add_to_linker((int)out,ba[i],internal);
6091 emit_jne(0);
6092 }
6093 }
6094 else // BC1F
6095 if(invert){
6096 nottaken=(int)out;
6097 emit_jne(1);
6098 }else{
6099 add_to_linker((int)out,ba[i],internal);
6100 emit_jeq(0);
6101 }
6102 {
6103 }
6104 } // if(!only32)
6105
6106 if(invert) {
6107 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6108 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6109 else if(match) emit_addnop(13);
6110 #endif
6111 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6112 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6113 if(internal)
6114 assem_debug("branch: internal\n");
6115 else
6116 assem_debug("branch: external\n");
6117 if(internal&&is_ds[(ba[i]-start)>>2]) {
6118 ds_assemble_entry(i);
6119 }
6120 else {
6121 add_to_linker((int)out,ba[i],internal);
6122 emit_jmp(0);
6123 }
6124 set_jump_target(nottaken,(int)out);
6125 }
6126
6127 if(adj) {
6128 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6129 }
6130 } // (!unconditional)
6131 } // if(ooo)
6132 else
6133 {
6134 // In-order execution (branch first)
6135 //printf("IOE\n");
6136 int nottaken=0;
6137 if(1) {
6138 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6139 if(1) {
6140 assert(fs>=0);
6141 emit_testimm(fs,0x800000);
6142 if(source[i]&0x10000) // BC1T
6143 {
6144 nottaken=(int)out;
6145 emit_jeq(1);
6146 }
6147 else // BC1F
6148 {
6149 nottaken=(int)out;
6150 emit_jne(1);
6151 }
6152 }
6153 } // if(!unconditional)
6154 int adj;
6155 uint64_t ds_unneeded=branch_regs[i].u;
6156 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6157 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6158 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6159 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6160 ds_unneeded|=1;
6161 ds_unneeded_upper|=1;
6162 // branch taken
6163 //assem_debug("1:\n");
6164 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6165 ds_unneeded,ds_unneeded_upper);
6166 // load regs
6167 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6168 address_generation(i+1,&branch_regs[i],0);
6169 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6170 ds_assemble(i+1,&branch_regs[i]);
6171 cc=get_reg(branch_regs[i].regmap,CCREG);
6172 if(cc==-1) {
6173 emit_loadreg(CCREG,cc=HOST_CCREG);
6174 // CHECK: Is the following instruction (fall thru) allocated ok?
6175 }
6176 assert(cc==HOST_CCREG);
6177 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6179 assem_debug("cycle count (adj)\n");
6180 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6181 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6182 if(internal)
6183 assem_debug("branch: internal\n");
6184 else
6185 assem_debug("branch: external\n");
6186 if(internal&&is_ds[(ba[i]-start)>>2]) {
6187 ds_assemble_entry(i);
6188 }
6189 else {
6190 add_to_linker((int)out,ba[i],internal);
6191 emit_jmp(0);
6192 }
6193
6194 // branch not taken
6195 if(1) { // <- FIXME (don't need this)
6196 set_jump_target(nottaken,(int)out);
6197 assem_debug("1:\n");
6198 if(!likely[i]) {
6199 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6200 ds_unneeded,ds_unneeded_upper);
6201 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6202 address_generation(i+1,&branch_regs[i],0);
6203 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6204 ds_assemble(i+1,&branch_regs[i]);
6205 }
6206 cc=get_reg(branch_regs[i].regmap,CCREG);
6207 if(cc==-1&&!likely[i]) {
6208 // Cycle count isn't in a register, temporarily load it then write it out
6209 emit_loadreg(CCREG,HOST_CCREG);
6210 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6211 int jaddr=(int)out;
6212 emit_jns(0);
6213 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6214 emit_storereg(CCREG,HOST_CCREG);
6215 }
6216 else{
6217 cc=get_reg(i_regmap,CCREG);
6218 assert(cc==HOST_CCREG);
6219 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6220 int jaddr=(int)out;
6221 emit_jns(0);
6222 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6223 }
6224 }
6225 }
6226}
6227
6228static void pagespan_assemble(int i,struct regstat *i_regs)
6229{
6230 int s1l=get_reg(i_regs->regmap,rs1[i]);
6231 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6232 int s2l=get_reg(i_regs->regmap,rs2[i]);
6233 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6234 void *nt_branch=NULL;
6235 int taken=0;
6236 int nottaken=0;
6237 int unconditional=0;
6238 if(rs1[i]==0)
6239 {
6240 s1l=s2l;s1h=s2h;
6241 s2l=s2h=-1;
6242 }
6243 else if(rs2[i]==0)
6244 {
6245 s2l=s2h=-1;
6246 }
6247 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6248 s1h=s2h=-1;
6249 }
6250 int hr=0;
6251 int addr,alt,ntaddr;
6252 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6253 else {
6254 while(hr<HOST_REGS)
6255 {
6256 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6257 (i_regs->regmap[hr]&63)!=rs1[i] &&
6258 (i_regs->regmap[hr]&63)!=rs2[i] )
6259 {
6260 addr=hr++;break;
6261 }
6262 hr++;
6263 }
6264 }
6265 while(hr<HOST_REGS)
6266 {
6267 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6268 (i_regs->regmap[hr]&63)!=rs1[i] &&
6269 (i_regs->regmap[hr]&63)!=rs2[i] )
6270 {
6271 alt=hr++;break;
6272 }
6273 hr++;
6274 }
6275 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6276 {
6277 while(hr<HOST_REGS)
6278 {
6279 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6280 (i_regs->regmap[hr]&63)!=rs1[i] &&
6281 (i_regs->regmap[hr]&63)!=rs2[i] )
6282 {
6283 ntaddr=hr;break;
6284 }
6285 hr++;
6286 }
6287 }
6288 assert(hr<HOST_REGS);
6289 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6290 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6291 }
6292 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6293 if(opcode[i]==2) // J
6294 {
6295 unconditional=1;
6296 }
6297 if(opcode[i]==3) // JAL
6298 {
6299 // TODO: mini_ht
6300 int rt=get_reg(i_regs->regmap,31);
6301 emit_movimm(start+i*4+8,rt);
6302 unconditional=1;
6303 }
6304 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6305 {
6306 emit_mov(s1l,addr);
6307 if(opcode2[i]==9) // JALR
6308 {
5067f341 6309 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6310 emit_movimm(start+i*4+8,rt);
6311 }
6312 }
6313 if((opcode[i]&0x3f)==4) // BEQ
6314 {
6315 if(rs1[i]==rs2[i])
6316 {
6317 unconditional=1;
6318 }
6319 else
6320 #ifdef HAVE_CMOV_IMM
6321 if(s1h<0) {
6322 if(s2l>=0) emit_cmp(s1l,s2l);
6323 else emit_test(s1l,s1l);
6324 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6325 }
6326 else
6327 #endif
6328 {
6329 assert(s1l>=0);
6330 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6331 if(s1h>=0) {
6332 if(s2h>=0) emit_cmp(s1h,s2h);
6333 else emit_test(s1h,s1h);
6334 emit_cmovne_reg(alt,addr);
6335 }
6336 if(s2l>=0) emit_cmp(s1l,s2l);
6337 else emit_test(s1l,s1l);
6338 emit_cmovne_reg(alt,addr);
6339 }
6340 }
6341 if((opcode[i]&0x3f)==5) // BNE
6342 {
6343 #ifdef HAVE_CMOV_IMM
6344 if(s1h<0) {
6345 if(s2l>=0) emit_cmp(s1l,s2l);
6346 else emit_test(s1l,s1l);
6347 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6348 }
6349 else
6350 #endif
6351 {
6352 assert(s1l>=0);
6353 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6354 if(s1h>=0) {
6355 if(s2h>=0) emit_cmp(s1h,s2h);
6356 else emit_test(s1h,s1h);
6357 emit_cmovne_reg(alt,addr);
6358 }
6359 if(s2l>=0) emit_cmp(s1l,s2l);
6360 else emit_test(s1l,s1l);
6361 emit_cmovne_reg(alt,addr);
6362 }
6363 }
6364 if((opcode[i]&0x3f)==0x14) // BEQL
6365 {
6366 if(s1h>=0) {
6367 if(s2h>=0) emit_cmp(s1h,s2h);
6368 else emit_test(s1h,s1h);
6369 nottaken=(int)out;
6370 emit_jne(0);
6371 }
6372 if(s2l>=0) emit_cmp(s1l,s2l);
6373 else emit_test(s1l,s1l);
6374 if(nottaken) set_jump_target(nottaken,(int)out);
6375 nottaken=(int)out;
6376 emit_jne(0);
6377 }
6378 if((opcode[i]&0x3f)==0x15) // BNEL
6379 {
6380 if(s1h>=0) {
6381 if(s2h>=0) emit_cmp(s1h,s2h);
6382 else emit_test(s1h,s1h);
6383 taken=(int)out;
6384 emit_jne(0);
6385 }
6386 if(s2l>=0) emit_cmp(s1l,s2l);
6387 else emit_test(s1l,s1l);
6388 nottaken=(int)out;
6389 emit_jeq(0);
6390 if(taken) set_jump_target(taken,(int)out);
6391 }
6392 if((opcode[i]&0x3f)==6) // BLEZ
6393 {
6394 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6395 emit_cmpimm(s1l,1);
6396 if(s1h>=0) emit_mov(addr,ntaddr);
6397 emit_cmovl_reg(alt,addr);
6398 if(s1h>=0) {
6399 emit_test(s1h,s1h);
6400 emit_cmovne_reg(ntaddr,addr);
6401 emit_cmovs_reg(alt,addr);
6402 }
6403 }
6404 if((opcode[i]&0x3f)==7) // BGTZ
6405 {
6406 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6407 emit_cmpimm(s1l,1);
6408 if(s1h>=0) emit_mov(addr,alt);
6409 emit_cmovl_reg(ntaddr,addr);
6410 if(s1h>=0) {
6411 emit_test(s1h,s1h);
6412 emit_cmovne_reg(alt,addr);
6413 emit_cmovs_reg(ntaddr,addr);
6414 }
6415 }
6416 if((opcode[i]&0x3f)==0x16) // BLEZL
6417 {
6418 assert((opcode[i]&0x3f)!=0x16);
6419 }
6420 if((opcode[i]&0x3f)==0x17) // BGTZL
6421 {
6422 assert((opcode[i]&0x3f)!=0x17);
6423 }
6424 assert(opcode[i]!=1); // BLTZ/BGEZ
6425
6426 //FIXME: Check CSREG
6427 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6428 if((source[i]&0x30000)==0) // BC1F
6429 {
6430 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6431 emit_testimm(s1l,0x800000);
6432 emit_cmovne_reg(alt,addr);
6433 }
6434 if((source[i]&0x30000)==0x10000) // BC1T
6435 {
6436 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6437 emit_testimm(s1l,0x800000);
6438 emit_cmovne_reg(alt,addr);
6439 }
6440 if((source[i]&0x30000)==0x20000) // BC1FL
6441 {
6442 emit_testimm(s1l,0x800000);
6443 nottaken=(int)out;
6444 emit_jne(0);
6445 }
6446 if((source[i]&0x30000)==0x30000) // BC1TL
6447 {
6448 emit_testimm(s1l,0x800000);
6449 nottaken=(int)out;
6450 emit_jeq(0);
6451 }
6452 }
6453
6454 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6455 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6456 if(likely[i]||unconditional)
6457 {
6458 emit_movimm(ba[i],HOST_BTREG);
6459 }
6460 else if(addr!=HOST_BTREG)
6461 {
6462 emit_mov(addr,HOST_BTREG);
6463 }
6464 void *branch_addr=out;
6465 emit_jmp(0);
6466 int target_addr=start+i*4+5;
6467 void *stub=out;
6468 void *compiled_target_addr=check_addr(target_addr);
6469 emit_extjump_ds((int)branch_addr,target_addr);
6470 if(compiled_target_addr) {
6471 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6472 add_link(target_addr,stub);
6473 }
6474 else set_jump_target((int)branch_addr,(int)stub);
6475 if(likely[i]) {
6476 // Not-taken path
6477 set_jump_target((int)nottaken,(int)out);
6478 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6479 void *branch_addr=out;
6480 emit_jmp(0);
6481 int target_addr=start+i*4+8;
6482 void *stub=out;
6483 void *compiled_target_addr=check_addr(target_addr);
6484 emit_extjump_ds((int)branch_addr,target_addr);
6485 if(compiled_target_addr) {
6486 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6487 add_link(target_addr,stub);
6488 }
6489 else set_jump_target((int)branch_addr,(int)stub);
6490 }
6491}
6492
6493// Assemble the delay slot for the above
6494static void pagespan_ds()
6495{
6496 assem_debug("initial delay slot:\n");
6497 u_int vaddr=start+1;
94d23bb9 6498 u_int page=get_page(vaddr);
6499 u_int vpage=get_vpage(vaddr);
57871462 6500 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6501 do_dirty_stub_ds();
6502 ll_add(jump_in+page,vaddr,(void *)out);
6503 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6504 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6505 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6506 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6507 emit_writeword(HOST_BTREG,(int)&branch_target);
6508 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6509 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6510 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6511 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6512 cop1_usable=0;
6513 is_delayslot=0;
6514 switch(itype[0]) {
6515 case ALU:
6516 alu_assemble(0,&regs[0]);break;
6517 case IMM16:
6518 imm16_assemble(0,&regs[0]);break;
6519 case SHIFT:
6520 shift_assemble(0,&regs[0]);break;
6521 case SHIFTIMM:
6522 shiftimm_assemble(0,&regs[0]);break;
6523 case LOAD:
6524 load_assemble(0,&regs[0]);break;
6525 case LOADLR:
6526 loadlr_assemble(0,&regs[0]);break;
6527 case STORE:
6528 store_assemble(0,&regs[0]);break;
6529 case STORELR:
6530 storelr_assemble(0,&regs[0]);break;
6531 case COP0:
6532 cop0_assemble(0,&regs[0]);break;
6533 case COP1:
6534 cop1_assemble(0,&regs[0]);break;
6535 case C1LS:
6536 c1ls_assemble(0,&regs[0]);break;
b9b61529 6537 case COP2:
6538 cop2_assemble(0,&regs[0]);break;
6539 case C2LS:
6540 c2ls_assemble(0,&regs[0]);break;
6541 case C2OP:
6542 c2op_assemble(0,&regs[0]);break;
57871462 6543 case FCONV:
6544 fconv_assemble(0,&regs[0]);break;
6545 case FLOAT:
6546 float_assemble(0,&regs[0]);break;
6547 case FCOMP:
6548 fcomp_assemble(0,&regs[0]);break;
6549 case MULTDIV:
6550 multdiv_assemble(0,&regs[0]);break;
6551 case MOV:
6552 mov_assemble(0,&regs[0]);break;
6553 case SYSCALL:
7139f3c8 6554 case HLECALL:
1e973cb0 6555 case INTCALL:
57871462 6556 case SPAN:
6557 case UJUMP:
6558 case RJUMP:
6559 case CJUMP:
6560 case SJUMP:
6561 case FJUMP:
6562 printf("Jump in the delay slot. This is probably a bug.\n");
6563 }
6564 int btaddr=get_reg(regs[0].regmap,BTREG);
6565 if(btaddr<0) {
6566 btaddr=get_reg(regs[0].regmap,-1);
6567 emit_readword((int)&branch_target,btaddr);
6568 }
6569 assert(btaddr!=HOST_CCREG);
6570 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6571#ifdef HOST_IMM8
6572 emit_movimm(start+4,HOST_TEMPREG);
6573 emit_cmp(btaddr,HOST_TEMPREG);
6574#else
6575 emit_cmpimm(btaddr,start+4);
6576#endif
6577 int branch=(int)out;
6578 emit_jeq(0);
6579 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6580 emit_jmp(jump_vaddr_reg[btaddr]);
6581 set_jump_target(branch,(int)out);
6582 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6583 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6584}
6585
6586// Basic liveness analysis for MIPS registers
6587void unneeded_registers(int istart,int iend,int r)
6588{
6589 int i;
6590 uint64_t u,uu,b,bu;
6591 uint64_t temp_u,temp_uu;
6592 uint64_t tdep;
6593 if(iend==slen-1) {
6594 u=1;uu=1;
6595 }else{
6596 u=unneeded_reg[iend+1];
6597 uu=unneeded_reg_upper[iend+1];
6598 u=1;uu=1;
6599 }
6600 for (i=iend;i>=istart;i--)
6601 {
6602 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6603 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6604 {
6605 // If subroutine call, flag return address as a possible branch target
6606 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6607
6608 if(ba[i]<start || ba[i]>=(start+slen*4))
6609 {
6610 // Branch out of this block, flush all regs
6611 u=1;
6612 uu=1;
6613 /* Hexagon hack
6614 if(itype[i]==UJUMP&&rt1[i]==31)
6615 {
6616 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6617 }
6618 if(itype[i]==RJUMP&&rs1[i]==31)
6619 {
6620 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6621 }
4cb76aa4 6622 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6623 if(itype[i]==UJUMP&&rt1[i]==31)
6624 {
6625 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6626 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6627 }
6628 if(itype[i]==RJUMP&&rs1[i]==31)
6629 {
6630 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6631 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6632 }
6633 }*/
6634 branch_unneeded_reg[i]=u;
6635 branch_unneeded_reg_upper[i]=uu;
6636 // Merge in delay slot
6637 tdep=(~uu>>rt1[i+1])&1;
6638 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6639 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6640 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6641 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6642 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6643 u|=1;uu|=1;
6644 // If branch is "likely" (and conditional)
6645 // then we skip the delay slot on the fall-thru path
6646 if(likely[i]) {
6647 if(i<slen-1) {
6648 u&=unneeded_reg[i+2];
6649 uu&=unneeded_reg_upper[i+2];
6650 }
6651 else
6652 {
6653 u=1;
6654 uu=1;
6655 }
6656 }
6657 }
6658 else
6659 {
6660 // Internal branch, flag target
6661 bt[(ba[i]-start)>>2]=1;
6662 if(ba[i]<=start+i*4) {
6663 // Backward branch
6664 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6665 {
6666 // Unconditional branch
6667 temp_u=1;temp_uu=1;
6668 } else {
6669 // Conditional branch (not taken case)
6670 temp_u=unneeded_reg[i+2];
6671 temp_uu=unneeded_reg_upper[i+2];
6672 }
6673 // Merge in delay slot
6674 tdep=(~temp_uu>>rt1[i+1])&1;
6675 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6676 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6677 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6678 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6679 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6680 temp_u|=1;temp_uu|=1;
6681 // If branch is "likely" (and conditional)
6682 // then we skip the delay slot on the fall-thru path
6683 if(likely[i]) {
6684 if(i<slen-1) {
6685 temp_u&=unneeded_reg[i+2];
6686 temp_uu&=unneeded_reg_upper[i+2];
6687 }
6688 else
6689 {
6690 temp_u=1;
6691 temp_uu=1;
6692 }
6693 }
6694 tdep=(~temp_uu>>rt1[i])&1;
6695 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6696 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6697 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6698 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6699 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6700 temp_u|=1;temp_uu|=1;
6701 unneeded_reg[i]=temp_u;
6702 unneeded_reg_upper[i]=temp_uu;
6703 // Only go three levels deep. This recursion can take an
6704 // excessive amount of time if there are a lot of nested loops.
6705 if(r<2) {
6706 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6707 }else{
6708 unneeded_reg[(ba[i]-start)>>2]=1;
6709 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6710 }
6711 } /*else*/ if(1) {
6712 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6713 {
6714 // Unconditional branch
6715 u=unneeded_reg[(ba[i]-start)>>2];
6716 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6717 branch_unneeded_reg[i]=u;
6718 branch_unneeded_reg_upper[i]=uu;
6719 //u=1;
6720 //uu=1;
6721 //branch_unneeded_reg[i]=u;
6722 //branch_unneeded_reg_upper[i]=uu;
6723 // Merge in delay slot
6724 tdep=(~uu>>rt1[i+1])&1;
6725 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6726 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6727 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6728 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6729 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6730 u|=1;uu|=1;
6731 } else {
6732 // Conditional branch
6733 b=unneeded_reg[(ba[i]-start)>>2];
6734 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6735 branch_unneeded_reg[i]=b;
6736 branch_unneeded_reg_upper[i]=bu;
6737 //b=1;
6738 //bu=1;
6739 //branch_unneeded_reg[i]=b;
6740 //branch_unneeded_reg_upper[i]=bu;
6741 // Branch delay slot
6742 tdep=(~uu>>rt1[i+1])&1;
6743 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6744 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6745 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6746 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6747 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6748 b|=1;bu|=1;
6749 // If branch is "likely" then we skip the
6750 // delay slot on the fall-thru path
6751 if(likely[i]) {
6752 u=b;
6753 uu=bu;
6754 if(i<slen-1) {
6755 u&=unneeded_reg[i+2];
6756 uu&=unneeded_reg_upper[i+2];
6757 //u=1;
6758 //uu=1;
6759 }
6760 } else {
6761 u&=b;
6762 uu&=bu;
6763 //u=1;
6764 //uu=1;
6765 }
6766 if(i<slen-1) {
6767 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6768 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6769 //branch_unneeded_reg[i]=1;
6770 //branch_unneeded_reg_upper[i]=1;
6771 } else {
6772 branch_unneeded_reg[i]=1;
6773 branch_unneeded_reg_upper[i]=1;
6774 }
6775 }
6776 }
6777 }
6778 }
1e973cb0 6779 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6780 {
6781 // SYSCALL instruction (software interrupt)
6782 u=1;
6783 uu=1;
6784 }
6785 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6786 {
6787 // ERET instruction (return from interrupt)
6788 u=1;
6789 uu=1;
6790 }
6791 //u=uu=1; // DEBUG
6792 tdep=(~uu>>rt1[i])&1;
6793 // Written registers are unneeded
6794 u|=1LL<<rt1[i];
6795 u|=1LL<<rt2[i];
6796 uu|=1LL<<rt1[i];
6797 uu|=1LL<<rt2[i];
6798 // Accessed registers are needed
6799 u&=~(1LL<<rs1[i]);
6800 u&=~(1LL<<rs2[i]);
6801 uu&=~(1LL<<us1[i]);
6802 uu&=~(1LL<<us2[i]);
6803 // Source-target dependencies
6804 uu&=~(tdep<<dep1[i]);
6805 uu&=~(tdep<<dep2[i]);
6806 // R0 is always unneeded
6807 u|=1;uu|=1;
6808 // Save it
6809 unneeded_reg[i]=u;
6810 unneeded_reg_upper[i]=uu;
6811 /*
6812 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6813 printf("U:");
6814 int r;
6815 for(r=1;r<=CCREG;r++) {
6816 if((unneeded_reg[i]>>r)&1) {
6817 if(r==HIREG) printf(" HI");
6818 else if(r==LOREG) printf(" LO");
6819 else printf(" r%d",r);
6820 }
6821 }
6822 printf(" UU:");
6823 for(r=1;r<=CCREG;r++) {
6824 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6825 if(r==HIREG) printf(" HI");
6826 else if(r==LOREG) printf(" LO");
6827 else printf(" r%d",r);
6828 }
6829 }
6830 printf("\n");*/
6831 }
252c20fc 6832#ifdef FORCE32
6833 for (i=iend;i>=istart;i--)
6834 {
6835 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6836 }
6837#endif
57871462 6838}
6839
6840// Identify registers which are likely to contain 32-bit values
6841// This is used to predict whether any branches will jump to a
6842// location with 64-bit values in registers.
6843static void provisional_32bit()
6844{
6845 int i,j;
6846 uint64_t is32=1;
6847 uint64_t lastbranch=1;
6848
6849 for(i=0;i<slen;i++)
6850 {
6851 if(i>0) {
6852 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6853 if(i>1) is32=lastbranch;
6854 else is32=1;
6855 }
6856 }
6857 if(i>1)
6858 {
6859 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6860 if(likely[i-2]) {
6861 if(i>2) is32=lastbranch;
6862 else is32=1;
6863 }
6864 }
6865 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6866 {
6867 if(rs1[i-2]==0||rs2[i-2]==0)
6868 {
6869 if(rs1[i-2]) {
6870 is32|=1LL<<rs1[i-2];
6871 }
6872 if(rs2[i-2]) {
6873 is32|=1LL<<rs2[i-2];
6874 }
6875 }
6876 }
6877 }
6878 // If something jumps here with 64-bit values
6879 // then promote those registers to 64 bits
6880 if(bt[i])
6881 {
6882 uint64_t temp_is32=is32;
6883 for(j=i-1;j>=0;j--)
6884 {
6885 if(ba[j]==start+i*4)
6886 //temp_is32&=branch_regs[j].is32;
6887 temp_is32&=p32[j];
6888 }
6889 for(j=i;j<slen;j++)
6890 {
6891 if(ba[j]==start+i*4)
6892 temp_is32=1;
6893 }
6894 is32=temp_is32;
6895 }
6896 int type=itype[i];
6897 int op=opcode[i];
6898 int op2=opcode2[i];
6899 int rt=rt1[i];
6900 int s1=rs1[i];
6901 int s2=rs2[i];
6902 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6903 // Branches don't write registers, consider the delay slot instead.
6904 type=itype[i+1];
6905 op=opcode[i+1];
6906 op2=opcode2[i+1];
6907 rt=rt1[i+1];
6908 s1=rs1[i+1];
6909 s2=rs2[i+1];
6910 lastbranch=is32;
6911 }
6912 switch(type) {
6913 case LOAD:
6914 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6915 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6916 is32&=~(1LL<<rt);
6917 else
6918 is32|=1LL<<rt;
6919 break;
6920 case STORE:
6921 case STORELR:
6922 break;
6923 case LOADLR:
6924 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6925 if(op==0x22) is32|=1LL<<rt; // LWL
6926 break;
6927 case IMM16:
6928 if (op==0x08||op==0x09|| // ADDI/ADDIU
6929 op==0x0a||op==0x0b|| // SLTI/SLTIU
6930 op==0x0c|| // ANDI
6931 op==0x0f) // LUI
6932 {
6933 is32|=1LL<<rt;
6934 }
6935 if(op==0x18||op==0x19) { // DADDI/DADDIU
6936 is32&=~(1LL<<rt);
6937 //if(imm[i]==0)
6938 // is32|=((is32>>s1)&1LL)<<rt;
6939 }
6940 if(op==0x0d||op==0x0e) { // ORI/XORI
6941 uint64_t sr=((is32>>s1)&1LL);
6942 is32&=~(1LL<<rt);
6943 is32|=sr<<rt;
6944 }
6945 break;
6946 case UJUMP:
6947 break;
6948 case RJUMP:
6949 break;
6950 case CJUMP:
6951 break;
6952 case SJUMP:
6953 break;
6954 case FJUMP:
6955 break;
6956 case ALU:
6957 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6958 is32|=1LL<<rt;
6959 }
6960 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6961 is32|=1LL<<rt;
6962 }
6963 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6964 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6965 is32&=~(1LL<<rt);
6966 is32|=sr<<rt;
6967 }
6968 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6969 if(s1==0&&s2==0) {
6970 is32|=1LL<<rt;
6971 }
6972 else if(s2==0) {
6973 uint64_t sr=((is32>>s1)&1LL);
6974 is32&=~(1LL<<rt);
6975 is32|=sr<<rt;
6976 }
6977 else if(s1==0) {
6978 uint64_t sr=((is32>>s2)&1LL);
6979 is32&=~(1LL<<rt);
6980 is32|=sr<<rt;
6981 }
6982 else {
6983 is32&=~(1LL<<rt);
6984 }
6985 }
6986 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6987 if(s1==0&&s2==0) {
6988 is32|=1LL<<rt;
6989 }
6990 else if(s2==0) {
6991 uint64_t sr=((is32>>s1)&1LL);
6992 is32&=~(1LL<<rt);
6993 is32|=sr<<rt;
6994 }
6995 else {
6996 is32&=~(1LL<<rt);
6997 }
6998 }
6999 break;
7000 case MULTDIV:
7001 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7002 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7003 }
7004 else {
7005 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7006 }
7007 break;
7008 case MOV:
7009 {
7010 uint64_t sr=((is32>>s1)&1LL);
7011 is32&=~(1LL<<rt);
7012 is32|=sr<<rt;
7013 }
7014 break;
7015 case SHIFT:
7016 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7017 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7018 break;
7019 case SHIFTIMM:
7020 is32|=1LL<<rt;
7021 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7022 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7023 break;
7024 case COP0:
7025 if(op2==0) is32|=1LL<<rt; // MFC0
7026 break;
7027 case COP1:
b9b61529 7028 case COP2:
57871462 7029 if(op2==0) is32|=1LL<<rt; // MFC1
7030 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7031 if(op2==2) is32|=1LL<<rt; // CFC1
7032 break;
7033 case C1LS:
b9b61529 7034 case C2LS:
57871462 7035 break;
7036 case FLOAT:
7037 case FCONV:
7038 break;
7039 case FCOMP:
7040 break;
b9b61529 7041 case C2OP:
57871462 7042 case SYSCALL:
7139f3c8 7043 case HLECALL:
57871462 7044 break;
7045 default:
7046 break;
7047 }
7048 is32|=1;
7049 p32[i]=is32;
7050
7051 if(i>0)
7052 {
7053 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7054 {
7055 if(rt1[i-1]==31) // JAL/JALR
7056 {
7057 // Subroutine call will return here, don't alloc any registers
7058 is32=1;
7059 }
7060 else if(i+1<slen)
7061 {
7062 // Internal branch will jump here, match registers to caller
7063 is32=0x3FFFFFFFFLL;
7064 }
7065 }
7066 }
7067 }
7068}
7069
7070// Identify registers which may be assumed to contain 32-bit values
7071// and where optimizations will rely on this.
7072// This is used to determine whether backward branches can safely
7073// jump to a location with 64-bit values in registers.
7074static void provisional_r32()
7075{
7076 u_int r32=0;
7077 int i;
7078
7079 for (i=slen-1;i>=0;i--)
7080 {
7081 int hr;
7082 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7083 {
7084 if(ba[i]<start || ba[i]>=(start+slen*4))
7085 {
7086 // Branch out of this block, don't need anything
7087 r32=0;
7088 }
7089 else
7090 {
7091 // Internal branch
7092 // Need whatever matches the target
7093 // (and doesn't get overwritten by the delay slot instruction)
7094 r32=0;
7095 int t=(ba[i]-start)>>2;
7096 if(ba[i]>start+i*4) {
7097 // Forward branch
7098 //if(!(requires_32bit[t]&~regs[i].was32))
7099 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7100 if(!(pr32[t]&~regs[i].was32))
7101 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7102 }else{
7103 // Backward branch
7104 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7105 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7106 }
7107 }
7108 // Conditional branch may need registers for following instructions
7109 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7110 {
7111 if(i<slen-2) {
7112 //r32|=requires_32bit[i+2];
7113 r32|=pr32[i+2];
7114 r32&=regs[i].was32;
7115 // Mark this address as a branch target since it may be called
7116 // upon return from interrupt
7117 //bt[i+2]=1;
7118 }
7119 }
7120 // Merge in delay slot
7121 if(!likely[i]) {
7122 // These are overwritten unless the branch is "likely"
7123 // and the delay slot is nullified if not taken
7124 r32&=~(1LL<<rt1[i+1]);
7125 r32&=~(1LL<<rt2[i+1]);
7126 }
7127 // Assume these are needed (delay slot)
7128 if(us1[i+1]>0)
7129 {
7130 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7131 }
7132 if(us2[i+1]>0)
7133 {
7134 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7135 }
7136 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7137 {
7138 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7139 }
7140 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7141 {
7142 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7143 }
7144 }
1e973cb0 7145 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7146 {
7147 // SYSCALL instruction (software interrupt)
7148 r32=0;
7149 }
7150 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7151 {
7152 // ERET instruction (return from interrupt)
7153 r32=0;
7154 }
7155 // Check 32 bits
7156 r32&=~(1LL<<rt1[i]);
7157 r32&=~(1LL<<rt2[i]);
7158 if(us1[i]>0)
7159 {
7160 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7161 }
7162 if(us2[i]>0)
7163 {
7164 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7165 }
7166 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7167 {
7168 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7169 }
7170 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7171 {
7172 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7173 }
7174 //requires_32bit[i]=r32;
7175 pr32[i]=r32;
7176
7177 // Dirty registers which are 32-bit, require 32-bit input
7178 // as they will be written as 32-bit values
7179 for(hr=0;hr<HOST_REGS;hr++)
7180 {
7181 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7182 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7183 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7184 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7185 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7186 }
7187 }
7188 }
7189 }
7190}
7191
7192// Write back dirty registers as soon as we will no longer modify them,
7193// so that we don't end up with lots of writes at the branches.
7194void clean_registers(int istart,int iend,int wr)
7195{
7196 int i;
7197 int r;
7198 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7199 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7200 if(iend==slen-1) {
7201 will_dirty_i=will_dirty_next=0;
7202 wont_dirty_i=wont_dirty_next=0;
7203 }else{
7204 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7205 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7206 }
7207 for (i=iend;i>=istart;i--)
7208 {
7209 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7210 {
7211 if(ba[i]<start || ba[i]>=(start+slen*4))
7212 {
7213 // Branch out of this block, flush all regs
7214 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7215 {
7216 // Unconditional branch
7217 will_dirty_i=0;
7218 wont_dirty_i=0;
7219 // Merge in delay slot (will dirty)
7220 for(r=0;r<HOST_REGS;r++) {
7221 if(r!=EXCLUDE_REG) {
7222 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7223 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7224 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7225 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7226 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7227 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7228 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7229 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7230 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7231 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7232 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7233 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7234 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7235 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7236 }
7237 }
7238 }
7239 else
7240 {
7241 // Conditional branch
7242 will_dirty_i=0;
7243 wont_dirty_i=wont_dirty_next;
7244 // Merge in delay slot (will dirty)
7245 for(r=0;r<HOST_REGS;r++) {
7246 if(r!=EXCLUDE_REG) {
7247 if(!likely[i]) {
7248 // Might not dirty if likely branch is not taken
7249 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7250 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7251 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7252 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7253 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7254 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7255 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7256 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7257 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7258 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7259 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7260 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7261 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7262 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7263 }
7264 }
7265 }
7266 }
7267 // Merge in delay slot (wont dirty)
7268 for(r=0;r<HOST_REGS;r++) {
7269 if(r!=EXCLUDE_REG) {
7270 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7271 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7272 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7273 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7274 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7275 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7276 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7277 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7278 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7279 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7280 }
7281 }
7282 if(wr) {
7283 #ifndef DESTRUCTIVE_WRITEBACK
7284 branch_regs[i].dirty&=wont_dirty_i;
7285 #endif
7286 branch_regs[i].dirty|=will_dirty_i;
7287 }
7288 }
7289 else
7290 {
7291 // Internal branch
7292 if(ba[i]<=start+i*4) {
7293 // Backward branch
7294 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7295 {
7296 // Unconditional branch
7297 temp_will_dirty=0;
7298 temp_wont_dirty=0;
7299 // Merge in delay slot (will dirty)
7300 for(r=0;r<HOST_REGS;r++) {
7301 if(r!=EXCLUDE_REG) {
7302 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7303 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7304 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7307 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7308 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7309 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7310 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7311 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7312 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7313 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7314 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7315 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7316 }
7317 }
7318 } else {
7319 // Conditional branch (not taken case)
7320 temp_will_dirty=will_dirty_next;
7321 temp_wont_dirty=wont_dirty_next;
7322 // Merge in delay slot (will dirty)
7323 for(r=0;r<HOST_REGS;r++) {
7324 if(r!=EXCLUDE_REG) {
7325 if(!likely[i]) {
7326 // Will not dirty if likely branch is not taken
7327 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7328 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7329 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7330 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7331 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7332 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7333 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7334 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7335 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7336 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7337 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7338 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7339 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7340 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7341 }
7342 }
7343 }
7344 }
7345 // Merge in delay slot (wont dirty)
7346 for(r=0;r<HOST_REGS;r++) {
7347 if(r!=EXCLUDE_REG) {
7348 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7349 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7350 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7351 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7352 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7353 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7354 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7355 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7356 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7357 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7358 }
7359 }
7360 // Deal with changed mappings
7361 if(i<iend) {
7362 for(r=0;r<HOST_REGS;r++) {
7363 if(r!=EXCLUDE_REG) {
7364 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7365 temp_will_dirty&=~(1<<r);
7366 temp_wont_dirty&=~(1<<r);
7367 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7368 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7369 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7370 } else {
7371 temp_will_dirty|=1<<r;
7372 temp_wont_dirty|=1<<r;
7373 }
7374 }
7375 }
7376 }
7377 }
7378 if(wr) {
7379 will_dirty[i]=temp_will_dirty;
7380 wont_dirty[i]=temp_wont_dirty;
7381 clean_registers((ba[i]-start)>>2,i-1,0);
7382 }else{
7383 // Limit recursion. It can take an excessive amount
7384 // of time if there are a lot of nested loops.
7385 will_dirty[(ba[i]-start)>>2]=0;
7386 wont_dirty[(ba[i]-start)>>2]=-1;
7387 }
7388 }
7389 /*else*/ if(1)
7390 {
7391 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7392 {
7393 // Unconditional branch
7394 will_dirty_i=0;
7395 wont_dirty_i=0;
7396 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7397 for(r=0;r<HOST_REGS;r++) {
7398 if(r!=EXCLUDE_REG) {
7399 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7400 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7401 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7402 }
7403 }
7404 }
7405 //}
7406 // Merge in delay slot
7407 for(r=0;r<HOST_REGS;r++) {
7408 if(r!=EXCLUDE_REG) {
7409 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7412 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7413 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7414 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7415 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7416 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7423 }
7424 }
7425 } else {
7426 // Conditional branch
7427 will_dirty_i=will_dirty_next;
7428 wont_dirty_i=wont_dirty_next;
7429 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7430 for(r=0;r<HOST_REGS;r++) {
7431 if(r!=EXCLUDE_REG) {
7432 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7433 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7434 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7435 }
7436 else
7437 {
7438 will_dirty_i&=~(1<<r);
7439 }
7440 // Treat delay slot as part of branch too
7441 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7442 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7443 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7444 }
7445 else
7446 {
7447 will_dirty[i+1]&=~(1<<r);
7448 }*/
7449 }
7450 }
7451 //}
7452 // Merge in delay slot
7453 for(r=0;r<HOST_REGS;r++) {
7454 if(r!=EXCLUDE_REG) {
7455 if(!likely[i]) {
7456 // Might not dirty if likely branch is not taken
7457 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7458 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7462 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7463 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7464 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7465 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7469 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7471 }
7472 }
7473 }
7474 }
7475 // Merge in delay slot
7476 for(r=0;r<HOST_REGS;r++) {
7477 if(r!=EXCLUDE_REG) {
7478 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7479 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7480 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7481 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7482 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7483 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7484 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7485 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7486 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7487 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7488 }
7489 }
7490 if(wr) {
7491 #ifndef DESTRUCTIVE_WRITEBACK
7492 branch_regs[i].dirty&=wont_dirty_i;
7493 #endif
7494 branch_regs[i].dirty|=will_dirty_i;
7495 }
7496 }
7497 }
7498 }
1e973cb0 7499 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7500 {
7501 // SYSCALL instruction (software interrupt)
7502 will_dirty_i=0;
7503 wont_dirty_i=0;
7504 }
7505 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7506 {
7507 // ERET instruction (return from interrupt)
7508 will_dirty_i=0;
7509 wont_dirty_i=0;
7510 }
7511 will_dirty_next=will_dirty_i;
7512 wont_dirty_next=wont_dirty_i;
7513 for(r=0;r<HOST_REGS;r++) {
7514 if(r!=EXCLUDE_REG) {
7515 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7518 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7519 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7520 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7521 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7522 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7523 if(i>istart) {
7524 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7525 {
7526 // Don't store a register immediately after writing it,
7527 // may prevent dual-issue.
7528 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7530 }
7531 }
7532 }
7533 }
7534 // Save it
7535 will_dirty[i]=will_dirty_i;
7536 wont_dirty[i]=wont_dirty_i;
7537 // Mark registers that won't be dirtied as not dirty
7538 if(wr) {
7539 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7540 for(r=0;r<HOST_REGS;r++) {
7541 if((will_dirty_i>>r)&1) {
7542 printf(" r%d",r);
7543 }
7544 }
7545 printf("\n");*/
7546
7547 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7548 regs[i].dirty|=will_dirty_i;
7549 #ifndef DESTRUCTIVE_WRITEBACK
7550 regs[i].dirty&=wont_dirty_i;
7551 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7552 {
7553 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7554 for(r=0;r<HOST_REGS;r++) {
7555 if(r!=EXCLUDE_REG) {
7556 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7557 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7558 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7559 }
7560 }
7561 }
7562 }
7563 else
7564 {
7565 if(i<iend) {
7566 for(r=0;r<HOST_REGS;r++) {
7567 if(r!=EXCLUDE_REG) {
7568 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7569 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7570 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7571 }
7572 }
7573 }
7574 }
7575 #endif
7576 //}
7577 }
7578 // Deal with changed mappings
7579 temp_will_dirty=will_dirty_i;
7580 temp_wont_dirty=wont_dirty_i;
7581 for(r=0;r<HOST_REGS;r++) {
7582 if(r!=EXCLUDE_REG) {
7583 int nr;
7584 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7585 if(wr) {
7586 #ifndef DESTRUCTIVE_WRITEBACK
7587 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7588 #endif
7589 regs[i].wasdirty|=will_dirty_i&(1<<r);
7590 }
7591 }
7592 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7593 // Register moved to a different register
7594 will_dirty_i&=~(1<<r);
7595 wont_dirty_i&=~(1<<r);
7596 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7597 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7598 if(wr) {
7599 #ifndef DESTRUCTIVE_WRITEBACK
7600 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7601 #endif
7602 regs[i].wasdirty|=will_dirty_i&(1<<r);
7603 }
7604 }
7605 else {
7606 will_dirty_i&=~(1<<r);
7607 wont_dirty_i&=~(1<<r);
7608 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7609 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7610 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7611 } else {
7612 wont_dirty_i|=1<<r;
7613 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7614 }
7615 }
7616 }
7617 }
7618 }
7619}
7620
7621 /* disassembly */
7622void disassemble_inst(int i)
7623{
7624 if (bt[i]) printf("*"); else printf(" ");
7625 switch(itype[i]) {
7626 case UJUMP:
7627 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7628 case CJUMP:
7629 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7630 case SJUMP:
7631 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7632 case FJUMP:
7633 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7634 case RJUMP:
74426039 7635 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7636 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7637 else
7638 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7639 break;
57871462 7640 case SPAN:
7641 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7642 case IMM16:
7643 if(opcode[i]==0xf) //LUI
7644 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7645 else
7646 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7647 break;
7648 case LOAD:
7649 case LOADLR:
7650 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7651 break;
7652 case STORE:
7653 case STORELR:
7654 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7655 break;
7656 case ALU:
7657 case SHIFT:
7658 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7659 break;
7660 case MULTDIV:
7661 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7662 break;
7663 case SHIFTIMM:
7664 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7665 break;
7666 case MOV:
7667 if((opcode2[i]&0x1d)==0x10)
7668 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7669 else if((opcode2[i]&0x1d)==0x11)
7670 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7671 else
7672 printf (" %x: %s\n",start+i*4,insn[i]);
7673 break;
7674 case COP0:
7675 if(opcode2[i]==0)
7676 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7677 else if(opcode2[i]==4)
7678 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7679 else printf (" %x: %s\n",start+i*4,insn[i]);
7680 break;
7681 case COP1:
7682 if(opcode2[i]<3)
7683 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7684 else if(opcode2[i]>3)
7685 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7686 else printf (" %x: %s\n",start+i*4,insn[i]);
7687 break;
b9b61529 7688 case COP2:
7689 if(opcode2[i]<3)
7690 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7691 else if(opcode2[i]>3)
7692 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7693 else printf (" %x: %s\n",start+i*4,insn[i]);
7694 break;
57871462 7695 case C1LS:
7696 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7697 break;
b9b61529 7698 case C2LS:
7699 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7700 break;
1e973cb0 7701 case INTCALL:
7702 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7703 break;
57871462 7704 default:
7705 //printf (" %s %8x\n",insn[i],source[i]);
7706 printf (" %x: %s\n",start+i*4,insn[i]);
7707 }
7708}
7709
dc990066 7710// clear the state completely, instead of just marking
7711// things invalid like invalidate_all_pages() does
7712void new_dynarec_clear_full()
57871462 7713{
57871462 7714 int n;
7715 for(n=0x80000;n<0x80800;n++)
7716 invalid_code[n]=1;
7717 for(n=0;n<65536;n++)
7718 hash_table[n][0]=hash_table[n][2]=-1;
7719 memset(mini_ht,-1,sizeof(mini_ht));
7720 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7721 memset(shadow,0,sizeof(shadow));
57871462 7722 copy=shadow;
7723 expirep=16384; // Expiry pointer, +2 blocks
7724 pending_exception=0;
7725 literalcount=0;
57871462 7726 stop_after_jal=0;
7727 // TLB
7728 using_tlb=0;
7729 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7730 memory_map[n]=-1;
7731 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7732 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7733 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7734 memory_map[n]=-1;
dc990066 7735 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7736 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7737 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7738}
7739
7740void new_dynarec_init()
7741{
7742 printf("Init new dynarec\n");
7743 out=(u_char *)BASE_ADDR;
7744 if (mmap (out, 1<<TARGET_SIZE_2,
7745 PROT_READ | PROT_WRITE | PROT_EXEC,
7746 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7747 -1, 0) <= 0) {printf("mmap() failed\n");}
7748#ifdef MUPEN64
7749 rdword=&readmem_dword;
7750 fake_pc.f.r.rs=&readmem_dword;
7751 fake_pc.f.r.rt=&readmem_dword;
7752 fake_pc.f.r.rd=&readmem_dword;
7753#endif
7754 int n;
7755 new_dynarec_clear_full();
7756#ifdef HOST_IMM8
7757 // Copy this into local area so we don't have to put it in every literal pool
7758 invc_ptr=invalid_code;
7759#endif
24385cae 7760#ifdef MUPEN64
57871462 7761 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7762 writemem[n] = write_nomem_new;
7763 writememb[n] = write_nomemb_new;
7764 writememh[n] = write_nomemh_new;
24385cae 7765#ifndef FORCE32
57871462 7766 writememd[n] = write_nomemd_new;
24385cae 7767#endif
57871462 7768 readmem[n] = read_nomem_new;
7769 readmemb[n] = read_nomemb_new;
7770 readmemh[n] = read_nomemh_new;
24385cae 7771#ifndef FORCE32
57871462 7772 readmemd[n] = read_nomemd_new;
24385cae 7773#endif
57871462 7774 }
7775 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7776 writemem[n] = write_rdram_new;
7777 writememb[n] = write_rdramb_new;
7778 writememh[n] = write_rdramh_new;
24385cae 7779#ifndef FORCE32
57871462 7780 writememd[n] = write_rdramd_new;
24385cae 7781#endif
57871462 7782 }
7783 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7784 writemem[n] = write_nomem_new;
7785 writememb[n] = write_nomemb_new;
7786 writememh[n] = write_nomemh_new;
24385cae 7787#ifndef FORCE32
57871462 7788 writememd[n] = write_nomemd_new;
24385cae 7789#endif
57871462 7790 readmem[n] = read_nomem_new;
7791 readmemb[n] = read_nomemb_new;
7792 readmemh[n] = read_nomemh_new;
24385cae 7793#ifndef FORCE32
57871462 7794 readmemd[n] = read_nomemd_new;
24385cae 7795#endif
57871462 7796 }
24385cae 7797#endif
57871462 7798 tlb_hacks();
7799 arch_init();
7800}
7801
7802void new_dynarec_cleanup()
7803{
7804 int n;
7805 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7806 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7807 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7808 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7809 #ifdef ROM_COPY
7810 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7811 #endif
7812}
7813
7814int new_recompile_block(int addr)
7815{
7816/*
7817 if(addr==0x800cd050) {
7818 int block;
7819 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7820 int n;
7821 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7822 }
7823*/
7824 //if(Count==365117028) tracedebug=1;
7825 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7826 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7827 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7828 //if(debug)
7829 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7830 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7831 /*if(Count>=312978186) {
7832 rlist();
7833 }*/
7834 //rlist();
7835 start = (u_int)addr&~3;
7836 //assert(((u_int)addr&1)==0);
7139f3c8 7837#ifdef PCSX
9ad4d757 7838 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7839 {
7139f3c8 7840 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7841 u_int beginning=(u_int)out;
7139f3c8 7842 u_int page=get_page(start);
7139f3c8 7843 invalid_code[start>>12]=0;
7844 emit_movimm(start,0);
7845 emit_writeword(0,(int)&pcaddr);
bb5285ef 7846 emit_jmp((int)new_dyna_leave);
7847#ifdef __arm__
7848 __clear_cache((void *)beginning,out);
7849#endif
9ad4d757 7850 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7851 return 0;
7852 }
560e4a12 7853 else if ((u_int)addr < 0x00200000 ||
7854 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7855 // used for BIOS calls mostly?
560e4a12 7856 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7857 pagelimit = (addr&0xa0000000)|0x00200000;
7858 }
7859 else if (!Config.HLE && (
7860/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7861 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7862 // BIOS
7863 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7864 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7865 }
7866 else
7867#endif
3d624f89 7868#ifdef MUPEN64
57871462 7869 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7870 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7871 pagelimit = 0xa4001000;
7872 }
3d624f89 7873 else
7874#endif
4cb76aa4 7875 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7876 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7877 pagelimit = 0x80000000+RAM_SIZE;
57871462 7878 }
90ae6d4e 7879#ifndef DISABLE_TLB
57871462 7880 else if ((signed int)addr >= (signed int)0xC0000000) {
7881 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7882 //if(tlb_LUT_r[start>>12])
7883 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7884 if((signed int)memory_map[start>>12]>=0) {
7885 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7886 pagelimit=(start+4096)&0xFFFFF000;
7887 int map=memory_map[start>>12];
7888 int i;
7889 for(i=0;i<5;i++) {
7890 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7891 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7892 }
7893 assem_debug("pagelimit=%x\n",pagelimit);
7894 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7895 }
7896 else {
7897 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7898 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7899 return -1; // Caller will invoke exception handler
57871462 7900 }
7901 //printf("source= %x\n",(int)source);
7902 }
90ae6d4e 7903#endif
57871462 7904 else {
7905 printf("Compile at bogus memory address: %x \n", (int)addr);
7906 exit(1);
7907 }
7908
7909 /* Pass 1: disassemble */
7910 /* Pass 2: register dependencies, branch targets */
7911 /* Pass 3: register allocation */
7912 /* Pass 4: branch dependencies */
7913 /* Pass 5: pre-alloc */
7914 /* Pass 6: optimize clean/dirty state */
7915 /* Pass 7: flag 32-bit registers */
7916 /* Pass 8: assembly */
7917 /* Pass 9: linker */
7918 /* Pass 10: garbage collection / free memory */
7919
7920 int i,j;
7921 int done=0;
7922 unsigned int type,op,op2;
7923
7924 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7925
7926 /* Pass 1 disassembly */
7927
7928 for(i=0;!done;i++) {
e1190b87 7929 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7930 minimum_free_regs[i]=0;
57871462 7931 opcode[i]=op=source[i]>>26;
7932 switch(op)
7933 {
7934 case 0x00: strcpy(insn[i],"special"); type=NI;
7935 op2=source[i]&0x3f;
7936 switch(op2)
7937 {
7938 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7939 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7940 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7941 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7942 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7943 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7944 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7945 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7946 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7947 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7948 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7949 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7950 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7951 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7952 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7953 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7954 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7955 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7956 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7957 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7958 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7959 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7960 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7961 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7962 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7963 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7964 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7965 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7966 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7967 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7968 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7969 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7970 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7971 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7972 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7973 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7974 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7975 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7976 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7977 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7978 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7979 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7980 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7981 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7982 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7983 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7984 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7985 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7986 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7987 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7988 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7989 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7990 }
7991 break;
7992 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7993 op2=(source[i]>>16)&0x1f;
7994 switch(op2)
7995 {
7996 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7997 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7998 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7999 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8000 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8001 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8002 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8003 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8004 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8005 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8006 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8007 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8008 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8009 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8010 }
8011 break;
8012 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8013 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8014 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8015 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8016 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8017 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8018 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8019 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8020 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8021 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8022 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8023 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8024 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8025 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8026 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8027 op2=(source[i]>>21)&0x1f;
8028 switch(op2)
8029 {
8030 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8031 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8032 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8033 switch(source[i]&0x3f)
8034 {
8035 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8036 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8037 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8038 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8039#ifdef PCSX
8040 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8041#else
57871462 8042 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8043#endif
57871462 8044 }
8045 }
8046 break;
8047 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8048 op2=(source[i]>>21)&0x1f;
8049 switch(op2)
8050 {
8051 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8052 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8053 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8054 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8055 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8056 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8057 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8058 switch((source[i]>>16)&0x3)
8059 {
8060 case 0x00: strcpy(insn[i],"BC1F"); break;
8061 case 0x01: strcpy(insn[i],"BC1T"); break;
8062 case 0x02: strcpy(insn[i],"BC1FL"); break;
8063 case 0x03: strcpy(insn[i],"BC1TL"); break;
8064 }
8065 break;
8066 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8067 switch(source[i]&0x3f)
8068 {
8069 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8070 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8071 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8072 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8073 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8074 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8075 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8076 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8077 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8078 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8079 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8080 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8081 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8082 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8083 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8084 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8085 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8086 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8087 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8088 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8089 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8090 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8091 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8092 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8093 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8094 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8095 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8096 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8097 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8098 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8099 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8100 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8101 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8102 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8103 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8104 }
8105 break;
8106 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8107 switch(source[i]&0x3f)
8108 {
8109 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8110 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8111 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8112 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8113 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8114 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8115 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8116 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8117 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8118 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8119 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8120 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8121 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8122 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8123 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8124 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8125 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8126 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8127 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8128 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8129 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8130 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8131 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8132 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8133 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8134 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8135 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8136 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8137 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8138 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8139 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8140 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8141 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8142 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8143 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8144 }
8145 break;
8146 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8147 switch(source[i]&0x3f)
8148 {
8149 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8150 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8151 }
8152 break;
8153 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8154 switch(source[i]&0x3f)
8155 {
8156 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8157 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8158 }
8159 break;
8160 }
8161 break;
909168d6 8162#ifndef FORCE32
57871462 8163 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8164 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8165 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8166 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8167 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8168 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8169 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8170 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8171#endif
57871462 8172 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8173 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8174 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8175 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8176 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8177 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8178 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8179 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8180 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8181 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8182 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8183 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8184#ifndef FORCE32
57871462 8185 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8186 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8187#endif
57871462 8188 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8189 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8190 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8191 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8192#ifndef FORCE32
57871462 8193 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8194 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8195 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8196#endif
57871462 8197 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8198 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8199#ifndef FORCE32
57871462 8200 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8201 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8202 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8203#endif
b9b61529 8204#ifdef PCSX
8205 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8206 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8207 op2=(source[i]>>21)&0x1f;
c7abc864 8208 if (source[i]&0x3f) {
8209 if (gte_handlers[source[i]&0x3f]!=NULL) {
8210 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8211 type=C2OP;
8212 }
8213 }
8214 else switch(op2)
b9b61529 8215 {
8216 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8217 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8218 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8219 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8220 }
8221 break;
8222 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8223 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8224 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8225#endif
90ae6d4e 8226 default: strcpy(insn[i],"???"); type=NI;
75dec299 8227 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8228 break;
57871462 8229 }
1e973cb0 8230#ifdef PCSX
8231 /* detect branch in delay slot early */
8232 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8233 opcode[i+1]=source[i+1]>>26;
8234 opcode2[i+1]=source[i+1]&0x3f;
8235 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8236 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8237 // don't handle first branch and call interpreter if it's hit
8238 type=INTCALL;
8239 }
8240 }
8241#endif
57871462 8242 itype[i]=type;
8243 opcode2[i]=op2;
8244 /* Get registers/immediates */
8245 lt1[i]=0;
8246 us1[i]=0;
8247 us2[i]=0;
8248 dep1[i]=0;
8249 dep2[i]=0;
8250 switch(type) {
8251 case LOAD:
8252 rs1[i]=(source[i]>>21)&0x1f;
8253 rs2[i]=0;
8254 rt1[i]=(source[i]>>16)&0x1f;
8255 rt2[i]=0;
8256 imm[i]=(short)source[i];
8257 break;
8258 case STORE:
8259 case STORELR:
8260 rs1[i]=(source[i]>>21)&0x1f;
8261 rs2[i]=(source[i]>>16)&0x1f;
8262 rt1[i]=0;
8263 rt2[i]=0;
8264 imm[i]=(short)source[i];
8265 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8266 break;
8267 case LOADLR:
8268 // LWL/LWR only load part of the register,
8269 // therefore the target register must be treated as a source too
8270 rs1[i]=(source[i]>>21)&0x1f;
8271 rs2[i]=(source[i]>>16)&0x1f;
8272 rt1[i]=(source[i]>>16)&0x1f;
8273 rt2[i]=0;
8274 imm[i]=(short)source[i];
8275 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8276 if(op==0x26) dep1[i]=rt1[i]; // LWR
8277 break;
8278 case IMM16:
8279 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8280 else rs1[i]=(source[i]>>21)&0x1f;
8281 rs2[i]=0;
8282 rt1[i]=(source[i]>>16)&0x1f;
8283 rt2[i]=0;
8284 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8285 imm[i]=(unsigned short)source[i];
8286 }else{
8287 imm[i]=(short)source[i];
8288 }
8289 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8290 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8291 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8292 break;
8293 case UJUMP:
8294 rs1[i]=0;
8295 rs2[i]=0;
8296 rt1[i]=0;
8297 rt2[i]=0;
8298 // The JAL instruction writes to r31.
8299 if (op&1) {
8300 rt1[i]=31;
8301 }
8302 rs2[i]=CCREG;
8303 break;
8304 case RJUMP:
8305 rs1[i]=(source[i]>>21)&0x1f;
8306 rs2[i]=0;
8307 rt1[i]=0;
8308 rt2[i]=0;
5067f341 8309 // The JALR instruction writes to rd.
57871462 8310 if (op2&1) {
5067f341 8311 rt1[i]=(source[i]>>11)&0x1f;
57871462 8312 }
8313 rs2[i]=CCREG;
8314 break;
8315 case CJUMP:
8316 rs1[i]=(source[i]>>21)&0x1f;
8317 rs2[i]=(source[i]>>16)&0x1f;
8318 rt1[i]=0;
8319 rt2[i]=0;
8320 if(op&2) { // BGTZ/BLEZ
8321 rs2[i]=0;
8322 }
8323 us1[i]=rs1[i];
8324 us2[i]=rs2[i];
8325 likely[i]=op>>4;
8326 break;
8327 case SJUMP:
8328 rs1[i]=(source[i]>>21)&0x1f;
8329 rs2[i]=CCREG;
8330 rt1[i]=0;
8331 rt2[i]=0;
8332 us1[i]=rs1[i];
8333 if(op2&0x10) { // BxxAL
8334 rt1[i]=31;
8335 // NOTE: If the branch is not taken, r31 is still overwritten
8336 }
8337 likely[i]=(op2&2)>>1;
8338 break;
8339 case FJUMP:
8340 rs1[i]=FSREG;
8341 rs2[i]=CSREG;
8342 rt1[i]=0;
8343 rt2[i]=0;
8344 likely[i]=((source[i])>>17)&1;
8345 break;
8346 case ALU:
8347 rs1[i]=(source[i]>>21)&0x1f; // source
8348 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8349 rt1[i]=(source[i]>>11)&0x1f; // destination
8350 rt2[i]=0;
8351 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8352 us1[i]=rs1[i];us2[i]=rs2[i];
8353 }
8354 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8355 dep1[i]=rs1[i];dep2[i]=rs2[i];
8356 }
8357 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8358 dep1[i]=rs1[i];dep2[i]=rs2[i];
8359 }
8360 break;
8361 case MULTDIV:
8362 rs1[i]=(source[i]>>21)&0x1f; // source
8363 rs2[i]=(source[i]>>16)&0x1f; // divisor
8364 rt1[i]=HIREG;
8365 rt2[i]=LOREG;
8366 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8367 us1[i]=rs1[i];us2[i]=rs2[i];
8368 }
8369 break;
8370 case MOV:
8371 rs1[i]=0;
8372 rs2[i]=0;
8373 rt1[i]=0;
8374 rt2[i]=0;
8375 if(op2==0x10) rs1[i]=HIREG; // MFHI
8376 if(op2==0x11) rt1[i]=HIREG; // MTHI
8377 if(op2==0x12) rs1[i]=LOREG; // MFLO
8378 if(op2==0x13) rt1[i]=LOREG; // MTLO
8379 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8380 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8381 dep1[i]=rs1[i];
8382 break;
8383 case SHIFT:
8384 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8385 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8386 rt1[i]=(source[i]>>11)&0x1f; // destination
8387 rt2[i]=0;
8388 // DSLLV/DSRLV/DSRAV are 64-bit
8389 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8390 break;
8391 case SHIFTIMM:
8392 rs1[i]=(source[i]>>16)&0x1f;
8393 rs2[i]=0;
8394 rt1[i]=(source[i]>>11)&0x1f;
8395 rt2[i]=0;
8396 imm[i]=(source[i]>>6)&0x1f;
8397 // DSxx32 instructions
8398 if(op2>=0x3c) imm[i]|=0x20;
8399 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8400 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8401 break;
8402 case COP0:
8403 rs1[i]=0;
8404 rs2[i]=0;
8405 rt1[i]=0;
8406 rt2[i]=0;
8407 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8408 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8409 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8410 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8411 break;
8412 case COP1:
b9b61529 8413 case COP2:
57871462 8414 rs1[i]=0;
8415 rs2[i]=0;
8416 rt1[i]=0;
8417 rt2[i]=0;
8418 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8419 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8420 if(op2==5) us1[i]=rs1[i]; // DMTC1
8421 rs2[i]=CSREG;
8422 break;
8423 case C1LS:
8424 rs1[i]=(source[i]>>21)&0x1F;
8425 rs2[i]=CSREG;
8426 rt1[i]=0;
8427 rt2[i]=0;
8428 imm[i]=(short)source[i];
8429 break;
b9b61529 8430 case C2LS:
8431 rs1[i]=(source[i]>>21)&0x1F;
8432 rs2[i]=0;
8433 rt1[i]=0;
8434 rt2[i]=0;
8435 imm[i]=(short)source[i];
8436 break;
57871462 8437 case FLOAT:
8438 case FCONV:
8439 rs1[i]=0;
8440 rs2[i]=CSREG;
8441 rt1[i]=0;
8442 rt2[i]=0;
8443 break;
8444 case FCOMP:
8445 rs1[i]=FSREG;
8446 rs2[i]=CSREG;
8447 rt1[i]=FSREG;
8448 rt2[i]=0;
8449 break;
8450 case SYSCALL:
7139f3c8 8451 case HLECALL:
1e973cb0 8452 case INTCALL:
57871462 8453 rs1[i]=CCREG;
8454 rs2[i]=0;
8455 rt1[i]=0;
8456 rt2[i]=0;
8457 break;
8458 default:
8459 rs1[i]=0;
8460 rs2[i]=0;
8461 rt1[i]=0;
8462 rt2[i]=0;
8463 }
8464 /* Calculate branch target addresses */
8465 if(type==UJUMP)
8466 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8467 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8468 ba[i]=start+i*4+8; // Ignore never taken branch
8469 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8470 ba[i]=start+i*4+8; // Ignore never taken branch
8471 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8472 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8473 else ba[i]=-1;
8474 /* Is this the end of the block? */
8475 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
26869094 8476#ifdef PCSX
8477 // check for link register access in delay slot
8478 int rt1_=rt1[i-1];
8479 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8480 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8481 ba[i-1]=-1;
8482 itype[i-1]=INTCALL;
8483 done=2;
8484 }
8485 else
8486#endif
5067f341 8487 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8488 done=2;
57871462 8489 }
8490 else {
8491 if(stop_after_jal) done=1;
8492 // Stop on BREAK
8493 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8494 }
8495 // Don't recompile stuff that's already compiled
8496 if(check_addr(start+i*4+4)) done=1;
8497 // Don't get too close to the limit
8498 if(i>MAXBLOCK/2) done=1;
8499 }
75dec299 8500 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8501 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8502 if(done==2) {
8503 // Does the block continue due to a branch?
8504 for(j=i-1;j>=0;j--)
8505 {
8506 if(ba[j]==start+i*4+4) done=j=0;
8507 if(ba[j]==start+i*4+8) done=j=0;
8508 }
8509 }
75dec299 8510 //assert(i<MAXBLOCK-1);
57871462 8511 if(start+i*4==pagelimit-4) done=1;
8512 assert(start+i*4<pagelimit);
8513 if (i==MAXBLOCK-1) done=1;
8514 // Stop if we're compiling junk
8515 if(itype[i]==NI&&opcode[i]==0x11) {
8516 done=stop_after_jal=1;
8517 printf("Disabled speculative precompilation\n");
8518 }
8519 }
8520 slen=i;
8521 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8522 if(start+i*4==pagelimit) {
8523 itype[i-1]=SPAN;
8524 }
8525 }
8526 assert(slen>0);
8527
8528 /* Pass 2 - Register dependencies and branch targets */
8529
8530 unneeded_registers(0,slen-1,0);
8531
8532 /* Pass 3 - Register allocation */
8533
8534 struct regstat current; // Current register allocations/status
8535 current.is32=1;
8536 current.dirty=0;
8537 current.u=unneeded_reg[0];
8538 current.uu=unneeded_reg_upper[0];
8539 clear_all_regs(current.regmap);
8540 alloc_reg(&current,0,CCREG);
8541 dirty_reg(&current,CCREG);
8542 current.isconst=0;
8543 current.wasconst=0;
8544 int ds=0;
8545 int cc=0;
8546 int hr;
6ebf4adf 8547
8548#ifndef FORCE32
57871462 8549 provisional_32bit();
6ebf4adf 8550#endif
57871462 8551 if((u_int)addr&1) {
8552 // First instruction is delay slot
8553 cc=-1;
8554 bt[1]=1;
8555 ds=1;
8556 unneeded_reg[0]=1;
8557 unneeded_reg_upper[0]=1;
8558 current.regmap[HOST_BTREG]=BTREG;
8559 }
8560
8561 for(i=0;i<slen;i++)
8562 {
8563 if(bt[i])
8564 {
8565 int hr;
8566 for(hr=0;hr<HOST_REGS;hr++)
8567 {
8568 // Is this really necessary?
8569 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8570 }
8571 current.isconst=0;
8572 }
8573 if(i>1)
8574 {
8575 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8576 {
8577 if(rs1[i-2]==0||rs2[i-2]==0)
8578 {
8579 if(rs1[i-2]) {
8580 current.is32|=1LL<<rs1[i-2];
8581 int hr=get_reg(current.regmap,rs1[i-2]|64);
8582 if(hr>=0) current.regmap[hr]=-1;
8583 }
8584 if(rs2[i-2]) {
8585 current.is32|=1LL<<rs2[i-2];
8586 int hr=get_reg(current.regmap,rs2[i-2]|64);
8587 if(hr>=0) current.regmap[hr]=-1;
8588 }
8589 }
8590 }
8591 }
6ebf4adf 8592#ifndef FORCE32
57871462 8593 // If something jumps here with 64-bit values
8594 // then promote those registers to 64 bits
8595 if(bt[i])
8596 {
8597 uint64_t temp_is32=current.is32;
8598 for(j=i-1;j>=0;j--)
8599 {
8600 if(ba[j]==start+i*4)
8601 temp_is32&=branch_regs[j].is32;
8602 }
8603 for(j=i;j<slen;j++)
8604 {
8605 if(ba[j]==start+i*4)
8606 //temp_is32=1;
8607 temp_is32&=p32[j];
8608 }
8609 if(temp_is32!=current.is32) {
8610 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8611 #ifdef DESTRUCTIVE_WRITEBACK
8612 for(hr=0;hr<HOST_REGS;hr++)
8613 {
8614 int r=current.regmap[hr];
8615 if(r>0&&r<64)
8616 {
8617 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8618 temp_is32|=1LL<<r;
8619 //printf("restore %d\n",r);
8620 }
8621 }
8622 }
8623 #endif
8624 current.is32=temp_is32;
8625 }
8626 }
6ebf4adf 8627#else
24385cae 8628 current.is32=-1LL;
8629#endif
8630
57871462 8631 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8632 regs[i].wasconst=current.isconst;
8633 regs[i].was32=current.is32;
8634 regs[i].wasdirty=current.dirty;
6ebf4adf 8635 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8636 // To change a dirty register from 32 to 64 bits, we must write
8637 // it out during the previous cycle (for branches, 2 cycles)
8638 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8639 {
8640 uint64_t temp_is32=current.is32;
8641 for(j=i-1;j>=0;j--)
8642 {
8643 if(ba[j]==start+i*4+4)
8644 temp_is32&=branch_regs[j].is32;
8645 }
8646 for(j=i;j<slen;j++)
8647 {
8648 if(ba[j]==start+i*4+4)
8649 //temp_is32=1;
8650 temp_is32&=p32[j];
8651 }
8652 if(temp_is32!=current.is32) {
8653 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8654 for(hr=0;hr<HOST_REGS;hr++)
8655 {
8656 int r=current.regmap[hr];
8657 if(r>0)
8658 {
8659 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8660 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8661 {
8662 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8663 {
8664 //printf("dump %d/r%d\n",hr,r);
8665 current.regmap[hr]=-1;
8666 if(get_reg(current.regmap,r|64)>=0)
8667 current.regmap[get_reg(current.regmap,r|64)]=-1;
8668 }
8669 }
8670 }
8671 }
8672 }
8673 }
8674 }
8675 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8676 {
8677 uint64_t temp_is32=current.is32;
8678 for(j=i-1;j>=0;j--)
8679 {
8680 if(ba[j]==start+i*4+8)
8681 temp_is32&=branch_regs[j].is32;
8682 }
8683 for(j=i;j<slen;j++)
8684 {
8685 if(ba[j]==start+i*4+8)
8686 //temp_is32=1;
8687 temp_is32&=p32[j];
8688 }
8689 if(temp_is32!=current.is32) {
8690 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8691 for(hr=0;hr<HOST_REGS;hr++)
8692 {
8693 int r=current.regmap[hr];
8694 if(r>0)
8695 {
8696 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8697 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8698 {
8699 //printf("dump %d/r%d\n",hr,r);
8700 current.regmap[hr]=-1;
8701 if(get_reg(current.regmap,r|64)>=0)
8702 current.regmap[get_reg(current.regmap,r|64)]=-1;
8703 }
8704 }
8705 }
8706 }
8707 }
8708 }
8709 #endif
8710 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8711 if(i+1<slen) {
8712 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8713 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8714 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8715 current.u|=1;
8716 current.uu|=1;
8717 } else {
8718 current.u=1;
8719 current.uu=1;
8720 }
8721 } else {
8722 if(i+1<slen) {
8723 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8724 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8725 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8726 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8727 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8728 current.u|=1;
8729 current.uu|=1;
8730 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8731 }
8732 is_ds[i]=ds;
8733 if(ds) {
8734 ds=0; // Skip delay slot, already allocated as part of branch
8735 // ...but we need to alloc it in case something jumps here
8736 if(i+1<slen) {
8737 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8738 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8739 }else{
8740 current.u=branch_unneeded_reg[i-1];
8741 current.uu=branch_unneeded_reg_upper[i-1];
8742 }
8743 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8744 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8745 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8746 current.u|=1;
8747 current.uu|=1;
8748 struct regstat temp;
8749 memcpy(&temp,&current,sizeof(current));
8750 temp.wasdirty=temp.dirty;
8751 temp.was32=temp.is32;
8752 // TODO: Take into account unconditional branches, as below
8753 delayslot_alloc(&temp,i);
8754 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8755 regs[i].wasdirty=temp.wasdirty;
8756 regs[i].was32=temp.was32;
8757 regs[i].dirty=temp.dirty;
8758 regs[i].is32=temp.is32;
8759 regs[i].isconst=0;
8760 regs[i].wasconst=0;
8761 current.isconst=0;
8762 // Create entry (branch target) regmap
8763 for(hr=0;hr<HOST_REGS;hr++)
8764 {
8765 int r=temp.regmap[hr];
8766 if(r>=0) {
8767 if(r!=regmap_pre[i][hr]) {
8768 regs[i].regmap_entry[hr]=-1;
8769 }
8770 else
8771 {
8772 if(r<64){
8773 if((current.u>>r)&1) {
8774 regs[i].regmap_entry[hr]=-1;
8775 regs[i].regmap[hr]=-1;
8776 //Don't clear regs in the delay slot as the branch might need them
8777 //current.regmap[hr]=-1;
8778 }else
8779 regs[i].regmap_entry[hr]=r;
8780 }
8781 else {
8782 if((current.uu>>(r&63))&1) {
8783 regs[i].regmap_entry[hr]=-1;
8784 regs[i].regmap[hr]=-1;
8785 //Don't clear regs in the delay slot as the branch might need them
8786 //current.regmap[hr]=-1;
8787 }else
8788 regs[i].regmap_entry[hr]=r;
8789 }
8790 }
8791 } else {
8792 // First instruction expects CCREG to be allocated
8793 if(i==0&&hr==HOST_CCREG)
8794 regs[i].regmap_entry[hr]=CCREG;
8795 else
8796 regs[i].regmap_entry[hr]=-1;
8797 }
8798 }
8799 }
8800 else { // Not delay slot
8801 switch(itype[i]) {
8802 case UJUMP:
8803 //current.isconst=0; // DEBUG
8804 //current.wasconst=0; // DEBUG
8805 //regs[i].wasconst=0; // DEBUG
8806 clear_const(&current,rt1[i]);
8807 alloc_cc(&current,i);
8808 dirty_reg(&current,CCREG);
8809 if (rt1[i]==31) {
8810 alloc_reg(&current,i,31);
8811 dirty_reg(&current,31);
68b3faee 8812 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
076655d1 8813 assert(rt1[i+1]!=rt1[i]);
57871462 8814 #ifdef REG_PREFETCH
8815 alloc_reg(&current,i,PTEMP);
8816 #endif
8817 //current.is32|=1LL<<rt1[i];
8818 }
e1190b87 8819 ooo[i]=1;
57871462 8820 delayslot_alloc(&current,i+1);
8821 //current.isconst=0; // DEBUG
8822 ds=1;
8823 //printf("i=%d, isconst=%x\n",i,current.isconst);
8824 break;
8825 case RJUMP:
8826 //current.isconst=0;
8827 //current.wasconst=0;
8828 //regs[i].wasconst=0;
8829 clear_const(&current,rs1[i]);
8830 clear_const(&current,rt1[i]);
8831 alloc_cc(&current,i);
8832 dirty_reg(&current,CCREG);
8833 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8834 alloc_reg(&current,i,rs1[i]);
5067f341 8835 if (rt1[i]!=0) {
8836 alloc_reg(&current,i,rt1[i]);
8837 dirty_reg(&current,rt1[i]);
68b3faee 8838 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8839 assert(rt1[i+1]!=rt1[i]);
57871462 8840 #ifdef REG_PREFETCH
8841 alloc_reg(&current,i,PTEMP);
8842 #endif
8843 }
8844 #ifdef USE_MINI_HT
8845 if(rs1[i]==31) { // JALR
8846 alloc_reg(&current,i,RHASH);
8847 #ifndef HOST_IMM_ADDR32
8848 alloc_reg(&current,i,RHTBL);
8849 #endif
8850 }
8851 #endif
8852 delayslot_alloc(&current,i+1);
8853 } else {
8854 // The delay slot overwrites our source register,
8855 // allocate a temporary register to hold the old value.
8856 current.isconst=0;
8857 current.wasconst=0;
8858 regs[i].wasconst=0;
8859 delayslot_alloc(&current,i+1);
8860 current.isconst=0;
8861 alloc_reg(&current,i,RTEMP);
8862 }
8863 //current.isconst=0; // DEBUG
e1190b87 8864 ooo[i]=1;
57871462 8865 ds=1;
8866 break;
8867 case CJUMP:
8868 //current.isconst=0;
8869 //current.wasconst=0;
8870 //regs[i].wasconst=0;
8871 clear_const(&current,rs1[i]);
8872 clear_const(&current,rs2[i]);
8873 if((opcode[i]&0x3E)==4) // BEQ/BNE
8874 {
8875 alloc_cc(&current,i);
8876 dirty_reg(&current,CCREG);
8877 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8878 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8879 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8880 {
8881 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8882 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8883 }
8884 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8885 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8886 // The delay slot overwrites one of our conditions.
8887 // Allocate the branch condition registers instead.
57871462 8888 current.isconst=0;
8889 current.wasconst=0;
8890 regs[i].wasconst=0;
8891 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8892 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8893 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8894 {
8895 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8896 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8897 }
8898 }
e1190b87 8899 else
8900 {
8901 ooo[i]=1;
8902 delayslot_alloc(&current,i+1);
8903 }
57871462 8904 }
8905 else
8906 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8907 {
8908 alloc_cc(&current,i);
8909 dirty_reg(&current,CCREG);
8910 alloc_reg(&current,i,rs1[i]);
8911 if(!(current.is32>>rs1[i]&1))
8912 {
8913 alloc_reg64(&current,i,rs1[i]);
8914 }
8915 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8916 // The delay slot overwrites one of our conditions.
8917 // Allocate the branch condition registers instead.
57871462 8918 current.isconst=0;
8919 current.wasconst=0;
8920 regs[i].wasconst=0;
8921 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8922 if(!((current.is32>>rs1[i])&1))
8923 {
8924 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8925 }
8926 }
e1190b87 8927 else
8928 {
8929 ooo[i]=1;
8930 delayslot_alloc(&current,i+1);
8931 }
57871462 8932 }
8933 else
8934 // Don't alloc the delay slot yet because we might not execute it
8935 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8936 {
8937 current.isconst=0;
8938 current.wasconst=0;
8939 regs[i].wasconst=0;
8940 alloc_cc(&current,i);
8941 dirty_reg(&current,CCREG);
8942 alloc_reg(&current,i,rs1[i]);
8943 alloc_reg(&current,i,rs2[i]);
8944 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8945 {
8946 alloc_reg64(&current,i,rs1[i]);
8947 alloc_reg64(&current,i,rs2[i]);
8948 }
8949 }
8950 else
8951 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8952 {
8953 current.isconst=0;
8954 current.wasconst=0;
8955 regs[i].wasconst=0;
8956 alloc_cc(&current,i);
8957 dirty_reg(&current,CCREG);
8958 alloc_reg(&current,i,rs1[i]);
8959 if(!(current.is32>>rs1[i]&1))
8960 {
8961 alloc_reg64(&current,i,rs1[i]);
8962 }
8963 }
8964 ds=1;
8965 //current.isconst=0;
8966 break;
8967 case SJUMP:
8968 //current.isconst=0;
8969 //current.wasconst=0;
8970 //regs[i].wasconst=0;
8971 clear_const(&current,rs1[i]);
8972 clear_const(&current,rt1[i]);
8973 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8974 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8975 {
8976 alloc_cc(&current,i);
8977 dirty_reg(&current,CCREG);
8978 alloc_reg(&current,i,rs1[i]);
8979 if(!(current.is32>>rs1[i]&1))
8980 {
8981 alloc_reg64(&current,i,rs1[i]);
8982 }
8983 if (rt1[i]==31) { // BLTZAL/BGEZAL
8984 alloc_reg(&current,i,31);
8985 dirty_reg(&current,31);
57871462 8986 //#ifdef REG_PREFETCH
8987 //alloc_reg(&current,i,PTEMP);
8988 //#endif
8989 //current.is32|=1LL<<rt1[i];
8990 }
e1190b87 8991 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8992 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 8993 // Allocate the branch condition registers instead.
57871462 8994 current.isconst=0;
8995 current.wasconst=0;
8996 regs[i].wasconst=0;
8997 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8998 if(!((current.is32>>rs1[i])&1))
8999 {
9000 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9001 }
9002 }
e1190b87 9003 else
9004 {
9005 ooo[i]=1;
9006 delayslot_alloc(&current,i+1);
9007 }
57871462 9008 }
9009 else
9010 // Don't alloc the delay slot yet because we might not execute it
9011 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9012 {
9013 current.isconst=0;
9014 current.wasconst=0;
9015 regs[i].wasconst=0;
9016 alloc_cc(&current,i);
9017 dirty_reg(&current,CCREG);
9018 alloc_reg(&current,i,rs1[i]);
9019 if(!(current.is32>>rs1[i]&1))
9020 {
9021 alloc_reg64(&current,i,rs1[i]);
9022 }
9023 }
9024 ds=1;
9025 //current.isconst=0;
9026 break;
9027 case FJUMP:
9028 current.isconst=0;
9029 current.wasconst=0;
9030 regs[i].wasconst=0;
9031 if(likely[i]==0) // BC1F/BC1T
9032 {
9033 // TODO: Theoretically we can run out of registers here on x86.
9034 // The delay slot can allocate up to six, and we need to check
9035 // CSREG before executing the delay slot. Possibly we can drop
9036 // the cycle count and then reload it after checking that the
9037 // FPU is in a usable state, or don't do out-of-order execution.
9038 alloc_cc(&current,i);
9039 dirty_reg(&current,CCREG);
9040 alloc_reg(&current,i,FSREG);
9041 alloc_reg(&current,i,CSREG);
9042 if(itype[i+1]==FCOMP) {
9043 // The delay slot overwrites the branch condition.
9044 // Allocate the branch condition registers instead.
57871462 9045 alloc_cc(&current,i);
9046 dirty_reg(&current,CCREG);
9047 alloc_reg(&current,i,CSREG);
9048 alloc_reg(&current,i,FSREG);
9049 }
9050 else {
e1190b87 9051 ooo[i]=1;
57871462 9052 delayslot_alloc(&current,i+1);
9053 alloc_reg(&current,i+1,CSREG);
9054 }
9055 }
9056 else
9057 // Don't alloc the delay slot yet because we might not execute it
9058 if(likely[i]) // BC1FL/BC1TL
9059 {
9060 alloc_cc(&current,i);
9061 dirty_reg(&current,CCREG);
9062 alloc_reg(&current,i,CSREG);
9063 alloc_reg(&current,i,FSREG);
9064 }
9065 ds=1;
9066 current.isconst=0;
9067 break;
9068 case IMM16:
9069 imm16_alloc(&current,i);
9070 break;
9071 case LOAD:
9072 case LOADLR:
9073 load_alloc(&current,i);
9074 break;
9075 case STORE:
9076 case STORELR:
9077 store_alloc(&current,i);
9078 break;
9079 case ALU:
9080 alu_alloc(&current,i);
9081 break;
9082 case SHIFT:
9083 shift_alloc(&current,i);
9084 break;
9085 case MULTDIV:
9086 multdiv_alloc(&current,i);
9087 break;
9088 case SHIFTIMM:
9089 shiftimm_alloc(&current,i);
9090 break;
9091 case MOV:
9092 mov_alloc(&current,i);
9093 break;
9094 case COP0:
9095 cop0_alloc(&current,i);
9096 break;
9097 case COP1:
b9b61529 9098 case COP2:
57871462 9099 cop1_alloc(&current,i);
9100 break;
9101 case C1LS:
9102 c1ls_alloc(&current,i);
9103 break;
b9b61529 9104 case C2LS:
9105 c2ls_alloc(&current,i);
9106 break;
9107 case C2OP:
9108 c2op_alloc(&current,i);
9109 break;
57871462 9110 case FCONV:
9111 fconv_alloc(&current,i);
9112 break;
9113 case FLOAT:
9114 float_alloc(&current,i);
9115 break;
9116 case FCOMP:
9117 fcomp_alloc(&current,i);
9118 break;
9119 case SYSCALL:
7139f3c8 9120 case HLECALL:
1e973cb0 9121 case INTCALL:
57871462 9122 syscall_alloc(&current,i);
9123 break;
9124 case SPAN:
9125 pagespan_alloc(&current,i);
9126 break;
9127 }
9128
9129 // Drop the upper half of registers that have become 32-bit
9130 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9131 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9132 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9133 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9134 current.uu|=1;
9135 } else {
9136 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9137 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9138 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9139 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9140 current.uu|=1;
9141 }
9142
9143 // Create entry (branch target) regmap
9144 for(hr=0;hr<HOST_REGS;hr++)
9145 {
9146 int r,or,er;
9147 r=current.regmap[hr];
9148 if(r>=0) {
9149 if(r!=regmap_pre[i][hr]) {
9150 // TODO: delay slot (?)
9151 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9152 if(or<0||(r&63)>=TEMPREG){
9153 regs[i].regmap_entry[hr]=-1;
9154 }
9155 else
9156 {
9157 // Just move it to a different register
9158 regs[i].regmap_entry[hr]=r;
9159 // If it was dirty before, it's still dirty
9160 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9161 }
9162 }
9163 else
9164 {
9165 // Unneeded
9166 if(r==0){
9167 regs[i].regmap_entry[hr]=0;
9168 }
9169 else
9170 if(r<64){
9171 if((current.u>>r)&1) {
9172 regs[i].regmap_entry[hr]=-1;
9173 //regs[i].regmap[hr]=-1;
9174 current.regmap[hr]=-1;
9175 }else
9176 regs[i].regmap_entry[hr]=r;
9177 }
9178 else {
9179 if((current.uu>>(r&63))&1) {
9180 regs[i].regmap_entry[hr]=-1;
9181 //regs[i].regmap[hr]=-1;
9182 current.regmap[hr]=-1;
9183 }else
9184 regs[i].regmap_entry[hr]=r;
9185 }
9186 }
9187 } else {
9188 // Branches expect CCREG to be allocated at the target
9189 if(regmap_pre[i][hr]==CCREG)
9190 regs[i].regmap_entry[hr]=CCREG;
9191 else
9192 regs[i].regmap_entry[hr]=-1;
9193 }
9194 }
9195 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9196 }
9197 /* Branch post-alloc */
9198 if(i>0)
9199 {
9200 current.was32=current.is32;
9201 current.wasdirty=current.dirty;
9202 switch(itype[i-1]) {
9203 case UJUMP:
9204 memcpy(&branch_regs[i-1],&current,sizeof(current));
9205 branch_regs[i-1].isconst=0;
9206 branch_regs[i-1].wasconst=0;
9207 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9208 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9209 alloc_cc(&branch_regs[i-1],i-1);
9210 dirty_reg(&branch_regs[i-1],CCREG);
9211 if(rt1[i-1]==31) { // JAL
9212 alloc_reg(&branch_regs[i-1],i-1,31);
9213 dirty_reg(&branch_regs[i-1],31);
9214 branch_regs[i-1].is32|=1LL<<31;
9215 }
9216 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9217 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9218 break;
9219 case RJUMP:
9220 memcpy(&branch_regs[i-1],&current,sizeof(current));
9221 branch_regs[i-1].isconst=0;
9222 branch_regs[i-1].wasconst=0;
9223 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9224 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9225 alloc_cc(&branch_regs[i-1],i-1);
9226 dirty_reg(&branch_regs[i-1],CCREG);
9227 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9228 if(rt1[i-1]!=0) { // JALR
9229 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9230 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9231 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9232 }
9233 #ifdef USE_MINI_HT
9234 if(rs1[i-1]==31) { // JALR
9235 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9236 #ifndef HOST_IMM_ADDR32
9237 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9238 #endif
9239 }
9240 #endif
9241 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9242 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9243 break;
9244 case CJUMP:
9245 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9246 {
9247 alloc_cc(&current,i-1);
9248 dirty_reg(&current,CCREG);
9249 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9250 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9251 // The delay slot overwrote one of our conditions
9252 // Delay slot goes after the test (in order)
9253 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9254 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9255 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9256 current.u|=1;
9257 current.uu|=1;
9258 delayslot_alloc(&current,i);
9259 current.isconst=0;
9260 }
9261 else
9262 {
9263 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9264 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9265 // Alloc the branch condition registers
9266 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9267 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9268 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9269 {
9270 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9271 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9272 }
9273 }
9274 memcpy(&branch_regs[i-1],&current,sizeof(current));
9275 branch_regs[i-1].isconst=0;
9276 branch_regs[i-1].wasconst=0;
9277 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9278 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9279 }
9280 else
9281 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9282 {
9283 alloc_cc(&current,i-1);
9284 dirty_reg(&current,CCREG);
9285 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9286 // The delay slot overwrote the branch condition
9287 // Delay slot goes after the test (in order)
9288 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9289 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9290 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9291 current.u|=1;
9292 current.uu|=1;
9293 delayslot_alloc(&current,i);
9294 current.isconst=0;
9295 }
9296 else
9297 {
9298 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9299 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9300 // Alloc the branch condition register
9301 alloc_reg(&current,i-1,rs1[i-1]);
9302 if(!(current.is32>>rs1[i-1]&1))
9303 {
9304 alloc_reg64(&current,i-1,rs1[i-1]);
9305 }
9306 }
9307 memcpy(&branch_regs[i-1],&current,sizeof(current));
9308 branch_regs[i-1].isconst=0;
9309 branch_regs[i-1].wasconst=0;
9310 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9311 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9312 }
9313 else
9314 // Alloc the delay slot in case the branch is taken
9315 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9316 {
9317 memcpy(&branch_regs[i-1],&current,sizeof(current));
9318 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9319 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9320 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9321 alloc_cc(&branch_regs[i-1],i);
9322 dirty_reg(&branch_regs[i-1],CCREG);
9323 delayslot_alloc(&branch_regs[i-1],i);
9324 branch_regs[i-1].isconst=0;
9325 alloc_reg(&current,i,CCREG); // Not taken path
9326 dirty_reg(&current,CCREG);
9327 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9328 }
9329 else
9330 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9331 {
9332 memcpy(&branch_regs[i-1],&current,sizeof(current));
9333 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9334 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9335 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9336 alloc_cc(&branch_regs[i-1],i);
9337 dirty_reg(&branch_regs[i-1],CCREG);
9338 delayslot_alloc(&branch_regs[i-1],i);
9339 branch_regs[i-1].isconst=0;
9340 alloc_reg(&current,i,CCREG); // Not taken path
9341 dirty_reg(&current,CCREG);
9342 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9343 }
9344 break;
9345 case SJUMP:
9346 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9347 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9348 {
9349 alloc_cc(&current,i-1);
9350 dirty_reg(&current,CCREG);
9351 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9352 // The delay slot overwrote the branch condition
9353 // Delay slot goes after the test (in order)
9354 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9355 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9356 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9357 current.u|=1;
9358 current.uu|=1;
9359 delayslot_alloc(&current,i);
9360 current.isconst=0;
9361 }
9362 else
9363 {
9364 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9365 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9366 // Alloc the branch condition register
9367 alloc_reg(&current,i-1,rs1[i-1]);
9368 if(!(current.is32>>rs1[i-1]&1))
9369 {
9370 alloc_reg64(&current,i-1,rs1[i-1]);
9371 }
9372 }
9373 memcpy(&branch_regs[i-1],&current,sizeof(current));
9374 branch_regs[i-1].isconst=0;
9375 branch_regs[i-1].wasconst=0;
9376 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9377 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9378 }
9379 else
9380 // Alloc the delay slot in case the branch is taken
9381 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9382 {
9383 memcpy(&branch_regs[i-1],&current,sizeof(current));
9384 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9385 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9386 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9387 alloc_cc(&branch_regs[i-1],i);
9388 dirty_reg(&branch_regs[i-1],CCREG);
9389 delayslot_alloc(&branch_regs[i-1],i);
9390 branch_regs[i-1].isconst=0;
9391 alloc_reg(&current,i,CCREG); // Not taken path
9392 dirty_reg(&current,CCREG);
9393 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9394 }
9395 // FIXME: BLTZAL/BGEZAL
9396 if(opcode2[i-1]&0x10) { // BxxZAL
9397 alloc_reg(&branch_regs[i-1],i-1,31);
9398 dirty_reg(&branch_regs[i-1],31);
9399 branch_regs[i-1].is32|=1LL<<31;
9400 }
9401 break;
9402 case FJUMP:
9403 if(likely[i-1]==0) // BC1F/BC1T
9404 {
9405 alloc_cc(&current,i-1);
9406 dirty_reg(&current,CCREG);
9407 if(itype[i]==FCOMP) {
9408 // The delay slot overwrote the branch condition
9409 // Delay slot goes after the test (in order)
9410 delayslot_alloc(&current,i);
9411 current.isconst=0;
9412 }
9413 else
9414 {
9415 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9416 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9417 // Alloc the branch condition register
9418 alloc_reg(&current,i-1,FSREG);
9419 }
9420 memcpy(&branch_regs[i-1],&current,sizeof(current));
9421 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9422 }
9423 else // BC1FL/BC1TL
9424 {
9425 // Alloc the delay slot in case the branch is taken
9426 memcpy(&branch_regs[i-1],&current,sizeof(current));
9427 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9428 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9429 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9430 alloc_cc(&branch_regs[i-1],i);
9431 dirty_reg(&branch_regs[i-1],CCREG);
9432 delayslot_alloc(&branch_regs[i-1],i);
9433 branch_regs[i-1].isconst=0;
9434 alloc_reg(&current,i,CCREG); // Not taken path
9435 dirty_reg(&current,CCREG);
9436 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9437 }
9438 break;
9439 }
9440
9441 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9442 {
9443 if(rt1[i-1]==31) // JAL/JALR
9444 {
9445 // Subroutine call will return here, don't alloc any registers
9446 current.is32=1;
9447 current.dirty=0;
9448 clear_all_regs(current.regmap);
9449 alloc_reg(&current,i,CCREG);
9450 dirty_reg(&current,CCREG);
9451 }
9452 else if(i+1<slen)
9453 {
9454 // Internal branch will jump here, match registers to caller
9455 current.is32=0x3FFFFFFFFLL;
9456 current.dirty=0;
9457 clear_all_regs(current.regmap);
9458 alloc_reg(&current,i,CCREG);
9459 dirty_reg(&current,CCREG);
9460 for(j=i-1;j>=0;j--)
9461 {
9462 if(ba[j]==start+i*4+4) {
9463 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9464 current.is32=branch_regs[j].is32;
9465 current.dirty=branch_regs[j].dirty;
9466 break;
9467 }
9468 }
9469 while(j>=0) {
9470 if(ba[j]==start+i*4+4) {
9471 for(hr=0;hr<HOST_REGS;hr++) {
9472 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9473 current.regmap[hr]=-1;
9474 }
9475 current.is32&=branch_regs[j].is32;
9476 current.dirty&=branch_regs[j].dirty;
9477 }
9478 }
9479 j--;
9480 }
9481 }
9482 }
9483 }
9484
9485 // Count cycles in between branches
9486 ccadj[i]=cc;
7139f3c8 9487 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9488 {
9489 cc=0;
9490 }
fb407447 9491#ifdef PCSX
9492 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9493 {
9494 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9495 }
9496 else if(itype[i]==C2LS)
9497 {
9498 cc+=4;
9499 }
9500#endif
57871462 9501 else
9502 {
9503 cc++;
9504 }
9505
9506 flush_dirty_uppers(&current);
9507 if(!is_ds[i]) {
9508 regs[i].is32=current.is32;
9509 regs[i].dirty=current.dirty;
9510 regs[i].isconst=current.isconst;
9511 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9512 }
9513 for(hr=0;hr<HOST_REGS;hr++) {
9514 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9515 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9516 regs[i].wasconst&=~(1<<hr);
9517 }
9518 }
9519 }
9520 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9521 }
9522
9523 /* Pass 4 - Cull unused host registers */
9524
9525 uint64_t nr=0;
9526
9527 for (i=slen-1;i>=0;i--)
9528 {
9529 int hr;
9530 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9531 {
9532 if(ba[i]<start || ba[i]>=(start+slen*4))
9533 {
9534 // Branch out of this block, don't need anything
9535 nr=0;
9536 }
9537 else
9538 {
9539 // Internal branch
9540 // Need whatever matches the target
9541 nr=0;
9542 int t=(ba[i]-start)>>2;
9543 for(hr=0;hr<HOST_REGS;hr++)
9544 {
9545 if(regs[i].regmap_entry[hr]>=0) {
9546 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9547 }
9548 }
9549 }
9550 // Conditional branch may need registers for following instructions
9551 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9552 {
9553 if(i<slen-2) {
9554 nr|=needed_reg[i+2];
9555 for(hr=0;hr<HOST_REGS;hr++)
9556 {
9557 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9558 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9559 }
9560 }
9561 }
9562 // Don't need stuff which is overwritten
9563 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9564 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9565 // Merge in delay slot
9566 for(hr=0;hr<HOST_REGS;hr++)
9567 {
9568 if(!likely[i]) {
9569 // These are overwritten unless the branch is "likely"
9570 // and the delay slot is nullified if not taken
9571 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9572 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9573 }
9574 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9575 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9576 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9577 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9578 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9579 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9580 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9581 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9582 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9583 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9584 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9585 }
9586 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9587 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9588 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9589 }
b9b61529 9590 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9591 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9592 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9593 }
9594 }
9595 }
1e973cb0 9596 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9597 {
9598 // SYSCALL instruction (software interrupt)
9599 nr=0;
9600 }
9601 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9602 {
9603 // ERET instruction (return from interrupt)
9604 nr=0;
9605 }
9606 else // Non-branch
9607 {
9608 if(i<slen-1) {
9609 for(hr=0;hr<HOST_REGS;hr++) {
9610 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9611 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9612 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9613 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9614 }
9615 }
9616 }
9617 for(hr=0;hr<HOST_REGS;hr++)
9618 {
9619 // Overwritten registers are not needed
9620 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9621 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9622 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9623 // Source registers are needed
9624 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9625 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9626 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9627 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9628 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9629 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9630 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9631 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9632 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9633 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9634 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9635 }
9636 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9637 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9638 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9639 }
b9b61529 9640 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9641 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9642 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9643 }
9644 // Don't store a register immediately after writing it,
9645 // may prevent dual-issue.
9646 // But do so if this is a branch target, otherwise we
9647 // might have to load the register before the branch.
9648 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9649 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9650 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9651 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9652 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9653 }
9654 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9655 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9656 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9657 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9658 }
9659 }
9660 }
9661 // Cycle count is needed at branches. Assume it is needed at the target too.
9662 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9663 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9664 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9665 }
9666 // Save it
9667 needed_reg[i]=nr;
9668
9669 // Deallocate unneeded registers
9670 for(hr=0;hr<HOST_REGS;hr++)
9671 {
9672 if(!((nr>>hr)&1)) {
9673 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9674 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9675 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9676 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9677 {
9678 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9679 {
9680 if(likely[i]) {
9681 regs[i].regmap[hr]=-1;
9682 regs[i].isconst&=~(1<<hr);
9683 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9684 }
9685 }
9686 }
9687 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9688 {
9689 int d1=0,d2=0,map=0,temp=0;
9690 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9691 {
9692 d1=dep1[i+1];
9693 d2=dep2[i+1];
9694 }
9695 if(using_tlb) {
9696 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9697 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9698 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9699 map=TLREG;
9700 } else
b9b61529 9701 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9702 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9703 map=INVCP;
9704 }
9705 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9706 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9707 temp=FTEMP;
9708 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9709 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9710 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9711 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9712 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9713 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9714 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9715 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9716 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9717 regs[i].regmap[hr]!=map )
9718 {
9719 regs[i].regmap[hr]=-1;
9720 regs[i].isconst&=~(1<<hr);
9721 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9722 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9723 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9724 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9725 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9726 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9727 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9728 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9729 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9730 branch_regs[i].regmap[hr]!=map)
9731 {
9732 branch_regs[i].regmap[hr]=-1;
9733 branch_regs[i].regmap_entry[hr]=-1;
9734 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9735 {
9736 if(!likely[i]&&i<slen-2) {
9737 regmap_pre[i+2][hr]=-1;
9738 }
9739 }
9740 }
9741 }
9742 }
9743 else
9744 {
9745 // Non-branch
9746 if(i>0)
9747 {
9748 int d1=0,d2=0,map=-1,temp=-1;
9749 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9750 {
9751 d1=dep1[i];
9752 d2=dep2[i];
9753 }
9754 if(using_tlb) {
9755 if(itype[i]==LOAD || itype[i]==LOADLR ||
9756 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9757 itype[i]==C1LS || itype[i]==C2LS)
57871462 9758 map=TLREG;
b9b61529 9759 } else if(itype[i]==STORE || itype[i]==STORELR ||
9760 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9761 map=INVCP;
9762 }
9763 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9764 itype[i]==C1LS || itype[i]==C2LS)
57871462 9765 temp=FTEMP;
9766 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9767 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9768 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9769 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9770 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9771 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9772 {
9773 if(i<slen-1&&!is_ds[i]) {
9774 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9775 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9776 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9777 {
9778 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9779 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9780 }
9781 regmap_pre[i+1][hr]=-1;
9782 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9783 }
9784 regs[i].regmap[hr]=-1;
9785 regs[i].isconst&=~(1<<hr);
9786 }
9787 }
9788 }
9789 }
9790 }
9791 }
9792
9793 /* Pass 5 - Pre-allocate registers */
9794
9795 // If a register is allocated during a loop, try to allocate it for the
9796 // entire loop, if possible. This avoids loading/storing registers
9797 // inside of the loop.
9798
9799 signed char f_regmap[HOST_REGS];
9800 clear_all_regs(f_regmap);
9801 for(i=0;i<slen-1;i++)
9802 {
9803 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9804 {
9805 if(ba[i]>=start && ba[i]<(start+i*4))
9806 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9807 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9808 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9809 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9810 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9811 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9812 {
9813 int t=(ba[i]-start)>>2;
9814 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9815 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9816 for(hr=0;hr<HOST_REGS;hr++)
9817 {
9818 if(regs[i].regmap[hr]>64) {
9819 if(!((regs[i].dirty>>hr)&1))
9820 f_regmap[hr]=regs[i].regmap[hr];
9821 else f_regmap[hr]=-1;
9822 }
b372a952 9823 else if(regs[i].regmap[hr]>=0) {
9824 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9825 // dealloc old register
9826 int n;
9827 for(n=0;n<HOST_REGS;n++)
9828 {
9829 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9830 }
9831 // and alloc new one
9832 f_regmap[hr]=regs[i].regmap[hr];
9833 }
9834 }
57871462 9835 if(branch_regs[i].regmap[hr]>64) {
9836 if(!((branch_regs[i].dirty>>hr)&1))
9837 f_regmap[hr]=branch_regs[i].regmap[hr];
9838 else f_regmap[hr]=-1;
9839 }
b372a952 9840 else if(branch_regs[i].regmap[hr]>=0) {
9841 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9842 // dealloc old register
9843 int n;
9844 for(n=0;n<HOST_REGS;n++)
9845 {
9846 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9847 }
9848 // and alloc new one
9849 f_regmap[hr]=branch_regs[i].regmap[hr];
9850 }
9851 }
e1190b87 9852 if(ooo[i]) {
9853 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9854 f_regmap[hr]=branch_regs[i].regmap[hr];
9855 }else{
9856 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9857 f_regmap[hr]=branch_regs[i].regmap[hr];
9858 }
9859 // Avoid dirty->clean transition
e1190b87 9860 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9861 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9862 #endif
9863 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9864 // case above, however it's always a good idea. We can't hoist the
9865 // load if the register was already allocated, so there's no point
9866 // wasting time analyzing most of these cases. It only "succeeds"
9867 // when the mapping was different and the load can be replaced with
9868 // a mov, which is of negligible benefit. So such cases are
9869 // skipped below.
57871462 9870 if(f_regmap[hr]>0) {
e1190b87 9871 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
57871462 9872 int r=f_regmap[hr];
9873 for(j=t;j<=i;j++)
9874 {
9875 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9876 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9877 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9878 if(r>63) {
9879 // NB This can exclude the case where the upper-half
9880 // register is lower numbered than the lower-half
9881 // register. Not sure if it's worth fixing...
9882 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9883 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9884 if(regs[j].is32&(1LL<<(r&63))) break;
9885 }
9886 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9887 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9888 int k;
9889 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9890 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9891 if(r>63) {
9892 if(get_reg(regs[i].regmap,r&63)<0) break;
9893 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9894 }
9895 k=i;
9896 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9897 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9898 //printf("no free regs for store %x\n",start+(k-1)*4);
9899 break;
57871462 9900 }
57871462 9901 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9902 //printf("no-match due to different register\n");
9903 break;
9904 }
9905 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9906 //printf("no-match due to branch\n");
9907 break;
9908 }
9909 // call/ret fast path assumes no registers allocated
9910 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9911 break;
9912 }
9913 if(r>63) {
9914 // NB This can exclude the case where the upper-half
9915 // register is lower numbered than the lower-half
9916 // register. Not sure if it's worth fixing...
9917 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9918 if(regs[k-1].is32&(1LL<<(r&63))) break;
9919 }
9920 k--;
9921 }
9922 if(i<slen-1) {
9923 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9924 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9925 //printf("bad match after branch\n");
9926 break;
9927 }
9928 }
9929 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9930 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9931 while(k<i) {
9932 regs[k].regmap_entry[hr]=f_regmap[hr];
9933 regs[k].regmap[hr]=f_regmap[hr];
9934 regmap_pre[k+1][hr]=f_regmap[hr];
9935 regs[k].wasdirty&=~(1<<hr);
9936 regs[k].dirty&=~(1<<hr);
9937 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9938 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9939 regs[k].wasconst&=~(1<<hr);
9940 regs[k].isconst&=~(1<<hr);
9941 k++;
9942 }
9943 }
9944 else {
9945 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9946 break;
9947 }
9948 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9949 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9950 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9951 regs[i].regmap_entry[hr]=f_regmap[hr];
9952 regs[i].regmap[hr]=f_regmap[hr];
9953 regs[i].wasdirty&=~(1<<hr);
9954 regs[i].dirty&=~(1<<hr);
9955 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9956 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9957 regs[i].wasconst&=~(1<<hr);
9958 regs[i].isconst&=~(1<<hr);
9959 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9960 branch_regs[i].wasdirty&=~(1<<hr);
9961 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9962 branch_regs[i].regmap[hr]=f_regmap[hr];
9963 branch_regs[i].dirty&=~(1<<hr);
9964 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9965 branch_regs[i].wasconst&=~(1<<hr);
9966 branch_regs[i].isconst&=~(1<<hr);
9967 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9968 regmap_pre[i+2][hr]=f_regmap[hr];
9969 regs[i+2].wasdirty&=~(1<<hr);
9970 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9971 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9972 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9973 }
9974 }
9975 }
9976 for(k=t;k<j;k++) {
e1190b87 9977 // Alloc register clean at beginning of loop,
9978 // but may dirty it in pass 6
57871462 9979 regs[k].regmap_entry[hr]=f_regmap[hr];
9980 regs[k].regmap[hr]=f_regmap[hr];
57871462 9981 regs[k].dirty&=~(1<<hr);
9982 regs[k].wasconst&=~(1<<hr);
9983 regs[k].isconst&=~(1<<hr);
e1190b87 9984 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9985 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9986 branch_regs[k].regmap[hr]=f_regmap[hr];
9987 branch_regs[k].dirty&=~(1<<hr);
9988 branch_regs[k].wasconst&=~(1<<hr);
9989 branch_regs[k].isconst&=~(1<<hr);
9990 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9991 regmap_pre[k+2][hr]=f_regmap[hr];
9992 regs[k+2].wasdirty&=~(1<<hr);
9993 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9994 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9995 }
9996 }
9997 else
9998 {
9999 regmap_pre[k+1][hr]=f_regmap[hr];
10000 regs[k+1].wasdirty&=~(1<<hr);
10001 }
57871462 10002 }
10003 if(regs[j].regmap[hr]==f_regmap[hr])
10004 regs[j].regmap_entry[hr]=f_regmap[hr];
10005 break;
10006 }
10007 if(j==i) break;
10008 if(regs[j].regmap[hr]>=0)
10009 break;
10010 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10011 //printf("no-match due to different register\n");
10012 break;
10013 }
10014 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10015 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10016 break;
10017 }
e1190b87 10018 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10019 {
10020 // Stop on unconditional branch
10021 break;
10022 }
10023 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10024 {
10025 if(ooo[j]) {
10026 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10027 break;
10028 }else{
10029 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10030 break;
10031 }
10032 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10033 //printf("no-match due to different register (branch)\n");
57871462 10034 break;
10035 }
10036 }
e1190b87 10037 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10038 //printf("No free regs for store %x\n",start+j*4);
10039 break;
10040 }
57871462 10041 if(f_regmap[hr]>=64) {
10042 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10043 break;
10044 }
10045 else
10046 {
10047 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10048 break;
10049 }
10050 }
10051 }
10052 }
10053 }
10054 }
10055 }
10056 }
10057 }else{
10058 int count=0;
10059 for(hr=0;hr<HOST_REGS;hr++)
10060 {
10061 if(hr!=EXCLUDE_REG) {
10062 if(regs[i].regmap[hr]>64) {
10063 if(!((regs[i].dirty>>hr)&1))
10064 f_regmap[hr]=regs[i].regmap[hr];
10065 }
b372a952 10066 else if(regs[i].regmap[hr]>=0) {
10067 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10068 // dealloc old register
10069 int n;
10070 for(n=0;n<HOST_REGS;n++)
10071 {
10072 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10073 }
10074 // and alloc new one
10075 f_regmap[hr]=regs[i].regmap[hr];
10076 }
10077 }
57871462 10078 else if(regs[i].regmap[hr]<0) count++;
10079 }
10080 }
10081 // Try to restore cycle count at branch targets
10082 if(bt[i]) {
10083 for(j=i;j<slen-1;j++) {
10084 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10085 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10086 //printf("no free regs for store %x\n",start+j*4);
10087 break;
57871462 10088 }
57871462 10089 }
10090 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10091 int k=i;
10092 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10093 while(k<j) {
10094 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10095 regs[k].regmap[HOST_CCREG]=CCREG;
10096 regmap_pre[k+1][HOST_CCREG]=CCREG;
10097 regs[k+1].wasdirty|=1<<HOST_CCREG;
10098 regs[k].dirty|=1<<HOST_CCREG;
10099 regs[k].wasconst&=~(1<<HOST_CCREG);
10100 regs[k].isconst&=~(1<<HOST_CCREG);
10101 k++;
10102 }
10103 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10104 }
10105 // Work backwards from the branch target
10106 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10107 {
10108 //printf("Extend backwards\n");
10109 int k;
10110 k=i;
10111 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10112 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10113 //printf("no free regs for store %x\n",start+(k-1)*4);
10114 break;
57871462 10115 }
57871462 10116 k--;
10117 }
10118 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10119 //printf("Extend CC, %x ->\n",start+k*4);
10120 while(k<=i) {
10121 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10122 regs[k].regmap[HOST_CCREG]=CCREG;
10123 regmap_pre[k+1][HOST_CCREG]=CCREG;
10124 regs[k+1].wasdirty|=1<<HOST_CCREG;
10125 regs[k].dirty|=1<<HOST_CCREG;
10126 regs[k].wasconst&=~(1<<HOST_CCREG);
10127 regs[k].isconst&=~(1<<HOST_CCREG);
10128 k++;
10129 }
10130 }
10131 else {
10132 //printf("Fail Extend CC, %x ->\n",start+k*4);
10133 }
10134 }
10135 }
10136 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10137 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10138 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10139 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10140 {
10141 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10142 }
10143 }
10144 }
10145
10146 // This allocates registers (if possible) one instruction prior
10147 // to use, which can avoid a load-use penalty on certain CPUs.
10148 for(i=0;i<slen-1;i++)
10149 {
10150 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10151 {
10152 if(!bt[i+1])
10153 {
b9b61529 10154 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10155 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10156 {
10157 if(rs1[i+1]) {
10158 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10159 {
10160 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10161 {
10162 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10163 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10164 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10165 regs[i].isconst&=~(1<<hr);
10166 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10167 constmap[i][hr]=constmap[i+1][hr];
10168 regs[i+1].wasdirty&=~(1<<hr);
10169 regs[i].dirty&=~(1<<hr);
10170 }
10171 }
10172 }
10173 if(rs2[i+1]) {
10174 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10175 {
10176 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10177 {
10178 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10179 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10180 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10181 regs[i].isconst&=~(1<<hr);
10182 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10183 constmap[i][hr]=constmap[i+1][hr];
10184 regs[i+1].wasdirty&=~(1<<hr);
10185 regs[i].dirty&=~(1<<hr);
10186 }
10187 }
10188 }
10189 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10190 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10191 {
10192 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10193 {
10194 regs[i].regmap[hr]=rs1[i+1];
10195 regmap_pre[i+1][hr]=rs1[i+1];
10196 regs[i+1].regmap_entry[hr]=rs1[i+1];
10197 regs[i].isconst&=~(1<<hr);
10198 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10199 constmap[i][hr]=constmap[i+1][hr];
10200 regs[i+1].wasdirty&=~(1<<hr);
10201 regs[i].dirty&=~(1<<hr);
10202 }
10203 }
10204 }
10205 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10206 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10207 {
10208 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10209 {
10210 regs[i].regmap[hr]=rs1[i+1];
10211 regmap_pre[i+1][hr]=rs1[i+1];
10212 regs[i+1].regmap_entry[hr]=rs1[i+1];
10213 regs[i].isconst&=~(1<<hr);
10214 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10215 constmap[i][hr]=constmap[i+1][hr];
10216 regs[i+1].wasdirty&=~(1<<hr);
10217 regs[i].dirty&=~(1<<hr);
10218 }
10219 }
10220 }
10221 #ifndef HOST_IMM_ADDR32
b9b61529 10222 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10223 hr=get_reg(regs[i+1].regmap,TLREG);
10224 if(hr>=0) {
10225 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10226 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10227 int nr;
10228 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10229 {
10230 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10231 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10232 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10233 regs[i].isconst&=~(1<<hr);
10234 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10235 constmap[i][hr]=constmap[i+1][hr];
10236 regs[i+1].wasdirty&=~(1<<hr);
10237 regs[i].dirty&=~(1<<hr);
10238 }
10239 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10240 {
10241 // move it to another register
10242 regs[i+1].regmap[hr]=-1;
10243 regmap_pre[i+2][hr]=-1;
10244 regs[i+1].regmap[nr]=TLREG;
10245 regmap_pre[i+2][nr]=TLREG;
10246 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10247 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10248 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10249 regs[i].isconst&=~(1<<nr);
10250 regs[i+1].isconst&=~(1<<nr);
10251 regs[i].dirty&=~(1<<nr);
10252 regs[i+1].wasdirty&=~(1<<nr);
10253 regs[i+1].dirty&=~(1<<nr);
10254 regs[i+2].wasdirty&=~(1<<nr);
10255 }
10256 }
10257 }
10258 }
10259 #endif
b9b61529 10260 if(itype[i+1]==STORE||itype[i+1]==STORELR
10261 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10262 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10263 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10264 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10265 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10266 assert(hr>=0);
10267 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10268 {
10269 regs[i].regmap[hr]=rs1[i+1];
10270 regmap_pre[i+1][hr]=rs1[i+1];
10271 regs[i+1].regmap_entry[hr]=rs1[i+1];
10272 regs[i].isconst&=~(1<<hr);
10273 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10274 constmap[i][hr]=constmap[i+1][hr];
10275 regs[i+1].wasdirty&=~(1<<hr);
10276 regs[i].dirty&=~(1<<hr);
10277 }
10278 }
10279 }
b9b61529 10280 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10281 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10282 int nr;
10283 hr=get_reg(regs[i+1].regmap,FTEMP);
10284 assert(hr>=0);
10285 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10286 {
10287 regs[i].regmap[hr]=rs1[i+1];
10288 regmap_pre[i+1][hr]=rs1[i+1];
10289 regs[i+1].regmap_entry[hr]=rs1[i+1];
10290 regs[i].isconst&=~(1<<hr);
10291 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10292 constmap[i][hr]=constmap[i+1][hr];
10293 regs[i+1].wasdirty&=~(1<<hr);
10294 regs[i].dirty&=~(1<<hr);
10295 }
10296 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10297 {
10298 // move it to another register
10299 regs[i+1].regmap[hr]=-1;
10300 regmap_pre[i+2][hr]=-1;
10301 regs[i+1].regmap[nr]=FTEMP;
10302 regmap_pre[i+2][nr]=FTEMP;
10303 regs[i].regmap[nr]=rs1[i+1];
10304 regmap_pre[i+1][nr]=rs1[i+1];
10305 regs[i+1].regmap_entry[nr]=rs1[i+1];
10306 regs[i].isconst&=~(1<<nr);
10307 regs[i+1].isconst&=~(1<<nr);
10308 regs[i].dirty&=~(1<<nr);
10309 regs[i+1].wasdirty&=~(1<<nr);
10310 regs[i+1].dirty&=~(1<<nr);
10311 regs[i+2].wasdirty&=~(1<<nr);
10312 }
10313 }
10314 }
b9b61529 10315 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10316 if(itype[i+1]==LOAD)
10317 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10318 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10319 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10320 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10321 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10322 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10323 }
10324 if(hr>=0&&regs[i].regmap[hr]<0) {
10325 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10326 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10327 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10328 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10329 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10330 regs[i].isconst&=~(1<<hr);
10331 regs[i+1].wasdirty&=~(1<<hr);
10332 regs[i].dirty&=~(1<<hr);
10333 }
10334 }
10335 }
10336 }
10337 }
10338 }
10339 }
10340
10341 /* Pass 6 - Optimize clean/dirty state */
10342 clean_registers(0,slen-1,1);
10343
10344 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10345#ifndef FORCE32
57871462 10346 provisional_r32();
10347
10348 u_int r32=0;
10349
10350 for (i=slen-1;i>=0;i--)
10351 {
10352 int hr;
10353 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10354 {
10355 if(ba[i]<start || ba[i]>=(start+slen*4))
10356 {
10357 // Branch out of this block, don't need anything
10358 r32=0;
10359 }
10360 else
10361 {
10362 // Internal branch
10363 // Need whatever matches the target
10364 // (and doesn't get overwritten by the delay slot instruction)
10365 r32=0;
10366 int t=(ba[i]-start)>>2;
10367 if(ba[i]>start+i*4) {
10368 // Forward branch
10369 if(!(requires_32bit[t]&~regs[i].was32))
10370 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10371 }else{
10372 // Backward branch
10373 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10374 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10375 if(!(pr32[t]&~regs[i].was32))
10376 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10377 }
10378 }
10379 // Conditional branch may need registers for following instructions
10380 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10381 {
10382 if(i<slen-2) {
10383 r32|=requires_32bit[i+2];
10384 r32&=regs[i].was32;
10385 // Mark this address as a branch target since it may be called
10386 // upon return from interrupt
10387 bt[i+2]=1;
10388 }
10389 }
10390 // Merge in delay slot
10391 if(!likely[i]) {
10392 // These are overwritten unless the branch is "likely"
10393 // and the delay slot is nullified if not taken
10394 r32&=~(1LL<<rt1[i+1]);
10395 r32&=~(1LL<<rt2[i+1]);
10396 }
10397 // Assume these are needed (delay slot)
10398 if(us1[i+1]>0)
10399 {
10400 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10401 }
10402 if(us2[i+1]>0)
10403 {
10404 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10405 }
10406 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10407 {
10408 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10409 }
10410 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10411 {
10412 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10413 }
10414 }
1e973cb0 10415 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10416 {
10417 // SYSCALL instruction (software interrupt)
10418 r32=0;
10419 }
10420 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10421 {
10422 // ERET instruction (return from interrupt)
10423 r32=0;
10424 }
10425 // Check 32 bits
10426 r32&=~(1LL<<rt1[i]);
10427 r32&=~(1LL<<rt2[i]);
10428 if(us1[i]>0)
10429 {
10430 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10431 }
10432 if(us2[i]>0)
10433 {
10434 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10435 }
10436 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10437 {
10438 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10439 }
10440 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10441 {
10442 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10443 }
10444 requires_32bit[i]=r32;
10445
10446 // Dirty registers which are 32-bit, require 32-bit input
10447 // as they will be written as 32-bit values
10448 for(hr=0;hr<HOST_REGS;hr++)
10449 {
10450 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10451 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10452 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10453 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10454 }
10455 }
10456 }
10457 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10458 }
a28c6ce8 10459#endif
57871462 10460
10461 if(itype[slen-1]==SPAN) {
10462 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10463 }
10464
10465 /* Debug/disassembly */
10466 if((void*)assem_debug==(void*)printf)
10467 for(i=0;i<slen;i++)
10468 {
10469 printf("U:");
10470 int r;
10471 for(r=1;r<=CCREG;r++) {
10472 if((unneeded_reg[i]>>r)&1) {
10473 if(r==HIREG) printf(" HI");
10474 else if(r==LOREG) printf(" LO");
10475 else printf(" r%d",r);
10476 }
10477 }
90ae6d4e 10478#ifndef FORCE32
57871462 10479 printf(" UU:");
10480 for(r=1;r<=CCREG;r++) {
10481 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10482 if(r==HIREG) printf(" HI");
10483 else if(r==LOREG) printf(" LO");
10484 else printf(" r%d",r);
10485 }
10486 }
10487 printf(" 32:");
10488 for(r=0;r<=CCREG;r++) {
10489 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10490 if((regs[i].was32>>r)&1) {
10491 if(r==CCREG) printf(" CC");
10492 else if(r==HIREG) printf(" HI");
10493 else if(r==LOREG) printf(" LO");
10494 else printf(" r%d",r);
10495 }
10496 }
90ae6d4e 10497#endif
57871462 10498 printf("\n");
10499 #if defined(__i386__) || defined(__x86_64__)
10500 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10501 #endif
10502 #ifdef __arm__
10503 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10504 #endif
10505 printf("needs: ");
10506 if(needed_reg[i]&1) printf("eax ");
10507 if((needed_reg[i]>>1)&1) printf("ecx ");
10508 if((needed_reg[i]>>2)&1) printf("edx ");
10509 if((needed_reg[i]>>3)&1) printf("ebx ");
10510 if((needed_reg[i]>>5)&1) printf("ebp ");
10511 if((needed_reg[i]>>6)&1) printf("esi ");
10512 if((needed_reg[i]>>7)&1) printf("edi ");
10513 printf("r:");
10514 for(r=0;r<=CCREG;r++) {
10515 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10516 if((requires_32bit[i]>>r)&1) {
10517 if(r==CCREG) printf(" CC");
10518 else if(r==HIREG) printf(" HI");
10519 else if(r==LOREG) printf(" LO");
10520 else printf(" r%d",r);
10521 }
10522 }
10523 printf("\n");
10524 /*printf("pr:");
10525 for(r=0;r<=CCREG;r++) {
10526 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10527 if((pr32[i]>>r)&1) {
10528 if(r==CCREG) printf(" CC");
10529 else if(r==HIREG) printf(" HI");
10530 else if(r==LOREG) printf(" LO");
10531 else printf(" r%d",r);
10532 }
10533 }
10534 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10535 printf("\n");*/
10536 #if defined(__i386__) || defined(__x86_64__)
10537 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10538 printf("dirty: ");
10539 if(regs[i].wasdirty&1) printf("eax ");
10540 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10541 if((regs[i].wasdirty>>2)&1) printf("edx ");
10542 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10543 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10544 if((regs[i].wasdirty>>6)&1) printf("esi ");
10545 if((regs[i].wasdirty>>7)&1) printf("edi ");
10546 #endif
10547 #ifdef __arm__
10548 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10549 printf("dirty: ");
10550 if(regs[i].wasdirty&1) printf("r0 ");
10551 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10552 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10553 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10554 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10555 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10556 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10557 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10558 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10559 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10560 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10561 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10562 #endif
10563 printf("\n");
10564 disassemble_inst(i);
10565 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10566 #if defined(__i386__) || defined(__x86_64__)
10567 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10568 if(regs[i].dirty&1) printf("eax ");
10569 if((regs[i].dirty>>1)&1) printf("ecx ");
10570 if((regs[i].dirty>>2)&1) printf("edx ");
10571 if((regs[i].dirty>>3)&1) printf("ebx ");
10572 if((regs[i].dirty>>5)&1) printf("ebp ");
10573 if((regs[i].dirty>>6)&1) printf("esi ");
10574 if((regs[i].dirty>>7)&1) printf("edi ");
10575 #endif
10576 #ifdef __arm__
10577 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10578 if(regs[i].dirty&1) printf("r0 ");
10579 if((regs[i].dirty>>1)&1) printf("r1 ");
10580 if((regs[i].dirty>>2)&1) printf("r2 ");
10581 if((regs[i].dirty>>3)&1) printf("r3 ");
10582 if((regs[i].dirty>>4)&1) printf("r4 ");
10583 if((regs[i].dirty>>5)&1) printf("r5 ");
10584 if((regs[i].dirty>>6)&1) printf("r6 ");
10585 if((regs[i].dirty>>7)&1) printf("r7 ");
10586 if((regs[i].dirty>>8)&1) printf("r8 ");
10587 if((regs[i].dirty>>9)&1) printf("r9 ");
10588 if((regs[i].dirty>>10)&1) printf("r10 ");
10589 if((regs[i].dirty>>12)&1) printf("r12 ");
10590 #endif
10591 printf("\n");
10592 if(regs[i].isconst) {
10593 printf("constants: ");
10594 #if defined(__i386__) || defined(__x86_64__)
10595 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10596 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10597 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10598 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10599 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10600 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10601 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10602 #endif
10603 #ifdef __arm__
10604 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10605 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10606 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10607 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10608 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10609 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10610 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10611 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10612 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10613 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10614 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10615 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10616 #endif
10617 printf("\n");
10618 }
90ae6d4e 10619#ifndef FORCE32
57871462 10620 printf(" 32:");
10621 for(r=0;r<=CCREG;r++) {
10622 if((regs[i].is32>>r)&1) {
10623 if(r==CCREG) printf(" CC");
10624 else if(r==HIREG) printf(" HI");
10625 else if(r==LOREG) printf(" LO");
10626 else printf(" r%d",r);
10627 }
10628 }
10629 printf("\n");
90ae6d4e 10630#endif
57871462 10631 /*printf(" p32:");
10632 for(r=0;r<=CCREG;r++) {
10633 if((p32[i]>>r)&1) {
10634 if(r==CCREG) printf(" CC");
10635 else if(r==HIREG) printf(" HI");
10636 else if(r==LOREG) printf(" LO");
10637 else printf(" r%d",r);
10638 }
10639 }
10640 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10641 else printf("\n");*/
10642 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10643 #if defined(__i386__) || defined(__x86_64__)
10644 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10645 if(branch_regs[i].dirty&1) printf("eax ");
10646 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10647 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10648 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10649 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10650 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10651 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10652 #endif
10653 #ifdef __arm__
10654 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10655 if(branch_regs[i].dirty&1) printf("r0 ");
10656 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10657 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10658 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10659 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10660 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10661 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10662 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10663 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10664 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10665 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10666 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10667 #endif
90ae6d4e 10668#ifndef FORCE32
57871462 10669 printf(" 32:");
10670 for(r=0;r<=CCREG;r++) {
10671 if((branch_regs[i].is32>>r)&1) {
10672 if(r==CCREG) printf(" CC");
10673 else if(r==HIREG) printf(" HI");
10674 else if(r==LOREG) printf(" LO");
10675 else printf(" r%d",r);
10676 }
10677 }
10678 printf("\n");
90ae6d4e 10679#endif
57871462 10680 }
10681 }
10682
10683 /* Pass 8 - Assembly */
10684 linkcount=0;stubcount=0;
10685 ds=0;is_delayslot=0;
10686 cop1_usable=0;
10687 uint64_t is32_pre=0;
10688 u_int dirty_pre=0;
10689 u_int beginning=(u_int)out;
10690 if((u_int)addr&1) {
10691 ds=1;
10692 pagespan_ds();
10693 }
9ad4d757 10694 u_int instr_addr0_override=0;
10695
10696#ifdef PCSX
10697 if (start == 0x80030000) {
10698 // nasty hack for fastbios thing
10699 instr_addr0_override=(u_int)out;
10700 emit_movimm(start,0);
10701 emit_readword((int)&pcaddr,1);
10702 emit_writeword(0,(int)&pcaddr);
10703 emit_cmp(0,1);
10704 emit_jne((int)new_dyna_leave);
10705 }
10706#endif
57871462 10707 for(i=0;i<slen;i++)
10708 {
10709 //if(ds) printf("ds: ");
10710 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10711 if(ds) {
10712 ds=0; // Skip delay slot
10713 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10714 instr_addr[i]=0;
10715 } else {
10716 #ifndef DESTRUCTIVE_WRITEBACK
10717 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10718 {
10719 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10720 unneeded_reg[i],unneeded_reg_upper[i]);
10721 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10722 unneeded_reg[i],unneeded_reg_upper[i]);
10723 }
10724 is32_pre=regs[i].is32;
10725 dirty_pre=regs[i].dirty;
10726 #endif
10727 // write back
10728 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10729 {
10730 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10731 unneeded_reg[i],unneeded_reg_upper[i]);
10732 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10733 }
10734 // branch target entry point
10735 instr_addr[i]=(u_int)out;
10736 assem_debug("<->\n");
10737 // load regs
10738 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10739 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10740 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10741 address_generation(i,&regs[i],regs[i].regmap_entry);
10742 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10743 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10744 {
10745 // Load the delay slot registers if necessary
10746 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10747 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10748 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10749 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10750 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10751 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10752 }
10753 else if(i+1<slen)
10754 {
10755 // Preload registers for following instruction
10756 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10757 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10758 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10759 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10760 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10761 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10762 }
10763 // TODO: if(is_ooo(i)) address_generation(i+1);
10764 if(itype[i]==CJUMP||itype[i]==FJUMP)
10765 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10766 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10767 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10768 if(bt[i]) cop1_usable=0;
10769 // assemble
10770 switch(itype[i]) {
10771 case ALU:
10772 alu_assemble(i,&regs[i]);break;
10773 case IMM16:
10774 imm16_assemble(i,&regs[i]);break;
10775 case SHIFT:
10776 shift_assemble(i,&regs[i]);break;
10777 case SHIFTIMM:
10778 shiftimm_assemble(i,&regs[i]);break;
10779 case LOAD:
10780 load_assemble(i,&regs[i]);break;
10781 case LOADLR:
10782 loadlr_assemble(i,&regs[i]);break;
10783 case STORE:
10784 store_assemble(i,&regs[i]);break;
10785 case STORELR:
10786 storelr_assemble(i,&regs[i]);break;
10787 case COP0:
10788 cop0_assemble(i,&regs[i]);break;
10789 case COP1:
10790 cop1_assemble(i,&regs[i]);break;
10791 case C1LS:
10792 c1ls_assemble(i,&regs[i]);break;
b9b61529 10793 case COP2:
10794 cop2_assemble(i,&regs[i]);break;
10795 case C2LS:
10796 c2ls_assemble(i,&regs[i]);break;
10797 case C2OP:
10798 c2op_assemble(i,&regs[i]);break;
57871462 10799 case FCONV:
10800 fconv_assemble(i,&regs[i]);break;
10801 case FLOAT:
10802 float_assemble(i,&regs[i]);break;
10803 case FCOMP:
10804 fcomp_assemble(i,&regs[i]);break;
10805 case MULTDIV:
10806 multdiv_assemble(i,&regs[i]);break;
10807 case MOV:
10808 mov_assemble(i,&regs[i]);break;
10809 case SYSCALL:
10810 syscall_assemble(i,&regs[i]);break;
7139f3c8 10811 case HLECALL:
10812 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10813 case INTCALL:
10814 intcall_assemble(i,&regs[i]);break;
57871462 10815 case UJUMP:
10816 ujump_assemble(i,&regs[i]);ds=1;break;
10817 case RJUMP:
10818 rjump_assemble(i,&regs[i]);ds=1;break;
10819 case CJUMP:
10820 cjump_assemble(i,&regs[i]);ds=1;break;
10821 case SJUMP:
10822 sjump_assemble(i,&regs[i]);ds=1;break;
10823 case FJUMP:
10824 fjump_assemble(i,&regs[i]);ds=1;break;
10825 case SPAN:
10826 pagespan_assemble(i,&regs[i]);break;
10827 }
10828 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10829 literal_pool(1024);
10830 else
10831 literal_pool_jumpover(256);
10832 }
10833 }
10834 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10835 // If the block did not end with an unconditional branch,
10836 // add a jump to the next instruction.
10837 if(i>1) {
10838 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10839 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10840 assert(i==slen);
10841 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10842 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10843 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10844 emit_loadreg(CCREG,HOST_CCREG);
10845 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10846 }
10847 else if(!likely[i-2])
10848 {
10849 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10850 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10851 }
10852 else
10853 {
10854 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10855 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10856 }
10857 add_to_linker((int)out,start+i*4,0);
10858 emit_jmp(0);
10859 }
10860 }
10861 else
10862 {
10863 assert(i>0);
10864 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10865 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10866 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10867 emit_loadreg(CCREG,HOST_CCREG);
10868 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10869 add_to_linker((int)out,start+i*4,0);
10870 emit_jmp(0);
10871 }
10872
10873 // TODO: delay slot stubs?
10874 // Stubs
10875 for(i=0;i<stubcount;i++)
10876 {
10877 switch(stubs[i][0])
10878 {
10879 case LOADB_STUB:
10880 case LOADH_STUB:
10881 case LOADW_STUB:
10882 case LOADD_STUB:
10883 case LOADBU_STUB:
10884 case LOADHU_STUB:
10885 do_readstub(i);break;
10886 case STOREB_STUB:
10887 case STOREH_STUB:
10888 case STOREW_STUB:
10889 case STORED_STUB:
10890 do_writestub(i);break;
10891 case CC_STUB:
10892 do_ccstub(i);break;
10893 case INVCODE_STUB:
10894 do_invstub(i);break;
10895 case FP_STUB:
10896 do_cop1stub(i);break;
10897 case STORELR_STUB:
10898 do_unalignedwritestub(i);break;
10899 }
10900 }
10901
9ad4d757 10902 if (instr_addr0_override)
10903 instr_addr[0] = instr_addr0_override;
10904
57871462 10905 /* Pass 9 - Linker */
10906 for(i=0;i<linkcount;i++)
10907 {
10908 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10909 literal_pool(64);
10910 if(!link_addr[i][2])
10911 {
10912 void *stub=out;
10913 void *addr=check_addr(link_addr[i][1]);
10914 emit_extjump(link_addr[i][0],link_addr[i][1]);
10915 if(addr) {
10916 set_jump_target(link_addr[i][0],(int)addr);
10917 add_link(link_addr[i][1],stub);
10918 }
10919 else set_jump_target(link_addr[i][0],(int)stub);
10920 }
10921 else
10922 {
10923 // Internal branch
10924 int target=(link_addr[i][1]-start)>>2;
10925 assert(target>=0&&target<slen);
10926 assert(instr_addr[target]);
10927 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10928 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10929 //#else
10930 set_jump_target(link_addr[i][0],instr_addr[target]);
10931 //#endif
10932 }
10933 }
10934 // External Branch Targets (jump_in)
10935 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10936 for(i=0;i<slen;i++)
10937 {
10938 if(bt[i]||i==0)
10939 {
10940 if(instr_addr[i]) // TODO - delay slots (=null)
10941 {
10942 u_int vaddr=start+i*4;
94d23bb9 10943 u_int page=get_page(vaddr);
10944 u_int vpage=get_vpage(vaddr);
57871462 10945 literal_pool(256);
10946 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 10947#ifndef FORCE32
57871462 10948 if(!requires_32bit[i])
a28c6ce8 10949#else
10950 if(1)
10951#endif
57871462 10952 {
10953 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10954 assem_debug("jump_in: %x\n",start+i*4);
10955 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10956 int entry_point=do_dirty_stub(i);
10957 ll_add(jump_in+page,vaddr,(void *)entry_point);
10958 // If there was an existing entry in the hash table,
10959 // replace it with the new address.
10960 // Don't add new entries. We'll insert the
10961 // ones that actually get used in check_addr().
10962 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10963 if(ht_bin[0]==vaddr) {
10964 ht_bin[1]=entry_point;
10965 }
10966 if(ht_bin[2]==vaddr) {
10967 ht_bin[3]=entry_point;
10968 }
10969 }
10970 else
10971 {
10972 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10973 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10974 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10975 //int entry_point=(int)out;
10976 ////assem_debug("entry_point: %x\n",entry_point);
10977 //load_regs_entry(i);
10978 //if(entry_point==(int)out)
10979 // entry_point=instr_addr[i];
10980 //else
10981 // emit_jmp(instr_addr[i]);
10982 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10983 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10984 int entry_point=do_dirty_stub(i);
10985 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10986 }
10987 }
10988 }
10989 }
10990 // Write out the literal pool if necessary
10991 literal_pool(0);
10992 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10993 // Align code
10994 if(((u_int)out)&7) emit_addnop(13);
10995 #endif
10996 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10997 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10998 memcpy(copy,source,slen*4);
10999 copy+=slen*4;
11000
11001 #ifdef __arm__
11002 __clear_cache((void *)beginning,out);
11003 #endif
11004
11005 // If we're within 256K of the end of the buffer,
11006 // start over from the beginning. (Is 256K enough?)
11007 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11008
11009 // Trap writes to any of the pages we compiled
11010 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11011 invalid_code[i]=0;
90ae6d4e 11012#ifndef DISABLE_TLB
57871462 11013 memory_map[i]|=0x40000000;
11014 if((signed int)start>=(signed int)0xC0000000) {
11015 assert(using_tlb);
11016 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11017 invalid_code[j]=0;
11018 memory_map[j]|=0x40000000;
11019 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11020 }
90ae6d4e 11021#endif
57871462 11022 }
11023
11024 /* Pass 10 - Free memory by expiring oldest blocks */
11025
11026 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11027 while(expirep!=end)
11028 {
11029 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11030 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11031 inv_debug("EXP: Phase %d\n",expirep);
11032 switch((expirep>>11)&3)
11033 {
11034 case 0:
11035 // Clear jump_in and jump_dirty
11036 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11037 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11038 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11039 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11040 break;
11041 case 1:
11042 // Clear pointers
11043 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11044 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11045 break;
11046 case 2:
11047 // Clear hash table
11048 for(i=0;i<32;i++) {
11049 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11050 if((ht_bin[3]>>shift)==(base>>shift) ||
11051 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11052 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11053 ht_bin[2]=ht_bin[3]=-1;
11054 }
11055 if((ht_bin[1]>>shift)==(base>>shift) ||
11056 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11057 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11058 ht_bin[0]=ht_bin[2];
11059 ht_bin[1]=ht_bin[3];
11060 ht_bin[2]=ht_bin[3]=-1;
11061 }
11062 }
11063 break;
11064 case 3:
11065 // Clear jump_out
dd3a91a1 11066 #ifdef __arm__
11067 if((expirep&2047)==0)
11068 do_clear_cache();
11069 #endif
57871462 11070 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11071 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11072 break;
11073 }
11074 expirep=(expirep+1)&65535;
11075 }
11076 return 0;
11077}
b9b61529 11078
11079// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork