1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
186 #define LOADBU_STUB 7
187 #define LOADHU_STUB 8
188 #define STOREB_STUB 9
189 #define STOREH_STUB 10
190 #define STOREW_STUB 11
191 #define STORED_STUB 12
192 #define STORELR_STUB 13
193 #define INVCODE_STUB 14
201 int new_recompile_block(int addr);
202 void *get_addr_ht(u_int vaddr);
203 void invalidate_block(u_int block);
204 void invalidate_addr(u_int addr);
205 void remove_hash(int vaddr);
208 void dyna_linker_ds();
210 void verify_code_vm();
211 void verify_code_ds();
214 void fp_exception_ds();
221 void read_nomem_new();
222 void read_nomemb_new();
223 void read_nomemh_new();
224 void read_nomemd_new();
225 void write_nomem_new();
226 void write_nomemb_new();
227 void write_nomemh_new();
228 void write_nomemd_new();
229 void write_rdram_new();
230 void write_rdramb_new();
231 void write_rdramh_new();
232 void write_rdramd_new();
233 extern u_int memory_map[1048576];
235 // Needed by assembler
236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
239 void load_all_regs(signed char i_regmap[]);
240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
241 void load_regs_entry(int t);
242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
246 //#define DEBUG_CYCLE_COUNT 1
249 //#define assem_debug printf
250 //#define inv_debug printf
251 #define assem_debug nullf
252 #define inv_debug nullf
254 static void tlb_hacks()
258 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
262 switch (ROM_HEADER->Country_code&0xFF)
274 // Unknown country code
278 u_int rom_addr=(u_int)rom;
280 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
281 // in the lower 4G of memory to use this hack. Copy it if necessary.
282 if((void *)rom>(void *)0xffffffff) {
283 munmap(ROM_COPY, 67108864);
284 if(mmap(ROM_COPY, 12582912,
285 PROT_READ | PROT_WRITE,
286 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
287 -1, 0) <= 0) {printf("mmap() failed\n");}
288 memcpy(ROM_COPY,rom,12582912);
289 rom_addr=(u_int)ROM_COPY;
293 for(n=0x7F000;n<0x80000;n++) {
294 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
301 static u_int get_page(u_int vaddr)
303 u_int page=(vaddr^0x80000000)>>12;
305 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
307 if(page>2048) page=2048+(page&2047);
311 static u_int get_vpage(u_int vaddr)
313 u_int vpage=(vaddr^0x80000000)>>12;
315 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
317 if(vpage>2048) vpage=2048+(vpage&2047);
321 // Get address from virtual address
322 // This is called from the recompiled JR/JALR instructions
323 void *get_addr(u_int vaddr)
325 u_int page=get_page(vaddr);
326 u_int vpage=get_vpage(vaddr);
327 struct ll_entry *head;
328 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
331 if(head->vaddr==vaddr&&head->reg32==0) {
332 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
333 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
336 ht_bin[1]=(int)head->addr;
342 head=jump_dirty[vpage];
344 if(head->vaddr==vaddr&&head->reg32==0) {
345 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
346 // Don't restore blocks which are about to expire from the cache
347 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
348 if(verify_dirty(head->addr)) {
349 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
350 invalid_code[vaddr>>12]=0;
351 memory_map[vaddr>>12]|=0x40000000;
354 if(tlb_LUT_r[vaddr>>12]) {
355 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
356 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
359 restore_candidate[vpage>>3]|=1<<(vpage&7);
361 else restore_candidate[page>>3]|=1<<(page&7);
362 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 if(ht_bin[0]==vaddr) {
364 ht_bin[1]=(int)head->addr; // Replace existing entry
370 ht_bin[1]=(int)head->addr;
378 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
379 int r=new_recompile_block(vaddr);
380 if(r==0) return get_addr(vaddr);
381 // Execute in unmapped page, generate pagefault execption
383 Cause=(vaddr<<31)|0x8;
384 EPC=(vaddr&1)?vaddr-5:vaddr;
386 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
387 EntryHi=BadVAddr&0xFFFFE000;
388 return get_addr_ht(0x80000000);
390 // Look up address in hash table first
391 void *get_addr_ht(u_int vaddr)
393 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
394 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
396 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
397 return get_addr(vaddr);
400 void *get_addr_32(u_int vaddr,u_int flags)
402 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 u_int page=get_page(vaddr);
407 u_int vpage=get_vpage(vaddr);
408 struct ll_entry *head;
411 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
412 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
414 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 ht_bin[1]=(int)head->addr;
418 }else if(ht_bin[2]==-1) {
419 ht_bin[3]=(int)head->addr;
422 //ht_bin[3]=ht_bin[1];
423 //ht_bin[2]=ht_bin[0];
424 //ht_bin[1]=(int)head->addr;
431 head=jump_dirty[vpage];
433 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
434 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435 // Don't restore blocks which are about to expire from the cache
436 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
437 if(verify_dirty(head->addr)) {
438 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
439 invalid_code[vaddr>>12]=0;
440 memory_map[vaddr>>12]|=0x40000000;
443 if(tlb_LUT_r[vaddr>>12]) {
444 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
445 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
448 restore_candidate[vpage>>3]|=1<<(vpage&7);
450 else restore_candidate[page>>3]|=1<<(page&7);
452 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
454 ht_bin[1]=(int)head->addr;
456 }else if(ht_bin[2]==-1) {
457 ht_bin[3]=(int)head->addr;
460 //ht_bin[3]=ht_bin[1];
461 //ht_bin[2]=ht_bin[0];
462 //ht_bin[1]=(int)head->addr;
470 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
471 int r=new_recompile_block(vaddr);
472 if(r==0) return get_addr(vaddr);
473 // Execute in unmapped page, generate pagefault execption
475 Cause=(vaddr<<31)|0x8;
476 EPC=(vaddr&1)?vaddr-5:vaddr;
478 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
479 EntryHi=BadVAddr&0xFFFFE000;
480 return get_addr_ht(0x80000000);
483 void clear_all_regs(signed char regmap[])
486 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
489 signed char get_reg(signed char regmap[],int r)
492 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
496 // Find a register that is available for two consecutive cycles
497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
500 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
504 int count_free_regs(signed char regmap[])
508 for(hr=0;hr<HOST_REGS;hr++)
510 if(hr!=EXCLUDE_REG) {
511 if(regmap[hr]<0) count++;
517 void dirty_reg(struct regstat *cur,signed char reg)
521 for (hr=0;hr<HOST_REGS;hr++) {
522 if((cur->regmap[hr]&63)==reg) {
528 // If we dirty the lower half of a 64 bit register which is now being
529 // sign-extended, we need to dump the upper half.
530 // Note: Do this only after completion of the instruction, because
531 // some instructions may need to read the full 64-bit value even if
532 // overwriting it (eg SLTI, DSRA32).
533 static void flush_dirty_uppers(struct regstat *cur)
536 for (hr=0;hr<HOST_REGS;hr++) {
537 if((cur->dirty>>hr)&1) {
540 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if(cur->regmap[hr]==reg) {
552 cur->constmap[hr]=value;
554 else if((cur->regmap[hr]^64)==reg) {
556 cur->constmap[hr]=value>>32;
561 void clear_const(struct regstat *cur,signed char reg)
565 for (hr=0;hr<HOST_REGS;hr++) {
566 if((cur->regmap[hr]&63)==reg) {
567 cur->isconst&=~(1<<hr);
572 int is_const(struct regstat *cur,signed char reg)
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if((cur->regmap[hr]&63)==reg) {
578 return (cur->isconst>>hr)&1;
583 uint64_t get_const(struct regstat *cur,signed char reg)
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if(cur->regmap[hr]==reg) {
589 return cur->constmap[hr];
592 printf("Unknown constant in r%d\n",reg);
596 // Least soon needed registers
597 // Look at the next ten instructions and see which registers
598 // will be used. Try not to reallocate these.
599 void lsn(u_char hsn[], int i, int *preferred_reg)
609 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
611 // Don't go past an unconditonal jump
618 if(rs1[i+j]) hsn[rs1[i+j]]=j;
619 if(rs2[i+j]) hsn[rs2[i+j]]=j;
620 if(rt1[i+j]) hsn[rt1[i+j]]=j;
621 if(rt2[i+j]) hsn[rt2[i+j]]=j;
622 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
623 // Stores can allocate zero
627 // On some architectures stores need invc_ptr
628 #if defined(HOST_IMM8)
629 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
633 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
641 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
643 // Follow first branch
644 int t=(ba[i+b]-start)>>2;
645 j=7-b;if(t+j>=slen) j=slen-t-1;
648 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
649 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
650 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
651 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
654 // TODO: preferred register based on backward branch
656 // Delay slot should preferably not overwrite branch conditions or cycle count
657 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
658 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
659 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
665 // Coprocessor load/store needs FTEMP, even if not declared
669 // Load L/R also uses FTEMP as a temporary register
670 if(itype[i]==LOADLR) {
673 // Also 64-bit SDL/SDR
674 if(opcode[i]==0x2c||opcode[i]==0x2d) {
677 // Don't remove the TLB registers either
678 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
681 // Don't remove the miniht registers
682 if(itype[i]==UJUMP||itype[i]==RJUMP)
689 // We only want to allocate registers if we're going to use them again soon
690 int needed_again(int r, int i)
696 u_char hsn[MAXREG+1];
699 memset(hsn,10,sizeof(hsn));
700 lsn(hsn,i,&preferred_reg);
702 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
704 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
705 return 0; // Don't need any registers if exiting the block
713 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
715 // Don't go past an unconditonal jump
719 if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
726 if(rs1[i+j]==r) rn=j;
727 if(rs2[i+j]==r) rn=j;
728 if((unneeded_reg[i+j]>>r)&1) rn=10;
729 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
737 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
739 // Follow first branch
741 int t=(ba[i+b]-start)>>2;
742 j=7-b;if(t+j>=slen) j=slen-t-1;
745 if(!((unneeded_reg[t+j]>>r)&1)) {
746 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
747 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
753 for(hr=0;hr<HOST_REGS;hr++) {
754 if(hr!=EXCLUDE_REG) {
755 if(rn<hsn[hr]) return 1;
761 // Try to match register allocations at the end of a loop with those
763 int loop_reg(int i, int r, int hr)
772 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
774 // Don't go past an unconditonal jump
781 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
786 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
787 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
788 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
790 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
792 int t=(ba[i+k]-start)>>2;
793 int reg=get_reg(regs[t].regmap_entry,r);
794 if(reg>=0) return reg;
795 //reg=get_reg(regs[t+1].regmap_entry,r);
796 //if(reg>=0) return reg;
804 // Allocate every register, preserving source/target regs
805 void alloc_all(struct regstat *cur,int i)
809 for(hr=0;hr<HOST_REGS;hr++) {
810 if(hr!=EXCLUDE_REG) {
811 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
812 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
815 cur->dirty&=~(1<<hr);
818 if((cur->regmap[hr]&63)==0)
821 cur->dirty&=~(1<<hr);
828 void div64(int64_t dividend,int64_t divisor)
832 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
833 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
835 void divu64(uint64_t dividend,uint64_t divisor)
839 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
840 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
843 void mult64(uint64_t m1,uint64_t m2)
845 unsigned long long int op1, op2, op3, op4;
846 unsigned long long int result1, result2, result3, result4;
847 unsigned long long int temp1, temp2, temp3, temp4;
863 op1 = op2 & 0xFFFFFFFF;
864 op2 = (op2 >> 32) & 0xFFFFFFFF;
865 op3 = op4 & 0xFFFFFFFF;
866 op4 = (op4 >> 32) & 0xFFFFFFFF;
869 temp2 = (temp1 >> 32) + op1 * op4;
871 temp4 = (temp3 >> 32) + op2 * op4;
873 result1 = temp1 & 0xFFFFFFFF;
874 result2 = temp2 + (temp3 & 0xFFFFFFFF);
875 result3 = (result2 >> 32) + temp4;
876 result4 = (result3 >> 32);
878 lo = result1 | (result2 << 32);
879 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
888 void multu64(uint64_t m1,uint64_t m2)
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
894 op1 = m1 & 0xFFFFFFFF;
895 op2 = (m1 >> 32) & 0xFFFFFFFF;
896 op3 = m2 & 0xFFFFFFFF;
897 op4 = (m2 >> 32) & 0xFFFFFFFF;
900 temp2 = (temp1 >> 32) + op1 * op4;
902 temp4 = (temp3 >> 32) + op2 * op4;
904 result1 = temp1 & 0xFFFFFFFF;
905 result2 = temp2 + (temp3 & 0xFFFFFFFF);
906 result3 = (result2 >> 32) + temp4;
907 result4 = (result3 >> 32);
909 lo = result1 | (result2 << 32);
910 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
913 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
924 else original=loaded;
927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
930 original>>=64-(bits^56);
931 original<<=64-(bits^56);
935 else original=loaded;
940 #include "assem_x86.c"
943 #include "assem_x64.c"
946 #include "assem_arm.c"
949 // Add virtual address mapping to linked list
950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
952 struct ll_entry *new_entry;
953 new_entry=malloc(sizeof(struct ll_entry));
954 assert(new_entry!=NULL);
955 new_entry->vaddr=vaddr;
957 new_entry->addr=addr;
958 new_entry->next=*head;
962 // Add virtual address mapping for 32-bit compiled block
963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
969 new_entry->reg32=reg32;
970 new_entry->addr=addr;
971 new_entry->next=*head;
975 // Check if an address is already compiled
976 // but don't return addresses which are about to expire from the cache
977 void *check_addr(u_int vaddr)
979 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
980 if(ht_bin[0]==vaddr) {
981 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
982 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
984 if(ht_bin[2]==vaddr) {
985 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
986 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
988 u_int page=get_page(vaddr);
989 struct ll_entry *head;
992 if(head->vaddr==vaddr&&head->reg32==0) {
993 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
994 // Update existing entry with current address
995 if(ht_bin[0]==vaddr) {
996 ht_bin[1]=(int)head->addr;
999 if(ht_bin[2]==vaddr) {
1000 ht_bin[3]=(int)head->addr;
1003 // Insert into hash table with low priority.
1004 // Don't evict existing entries, as they are probably
1005 // addresses that are being accessed frequently.
1007 ht_bin[1]=(int)head->addr;
1009 }else if(ht_bin[2]==-1) {
1010 ht_bin[3]=(int)head->addr;
1021 void remove_hash(int vaddr)
1023 //printf("remove hash: %x\n",vaddr);
1024 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025 if(ht_bin[2]==vaddr) {
1026 ht_bin[2]=ht_bin[3]=-1;
1028 if(ht_bin[0]==vaddr) {
1029 ht_bin[0]=ht_bin[2];
1030 ht_bin[1]=ht_bin[3];
1031 ht_bin[2]=ht_bin[3]=-1;
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1037 struct ll_entry *next;
1039 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1040 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1042 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043 remove_hash((*head)->vaddr);
1050 head=&((*head)->next);
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1058 struct ll_entry *cur;
1059 struct ll_entry *next;
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1074 int ptr=get_pointer(head->addr);
1075 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076 if(((ptr>>shift)==(addr>>shift)) ||
1077 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1079 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080 kill_pointer(head->addr);
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1090 struct ll_entry *head;
1091 struct ll_entry *next;
1095 inv_debug("INVALIDATE: %x\n",head->vaddr);
1096 remove_hash(head->vaddr);
1101 head=jump_out[page];
1104 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105 kill_pointer(head->addr);
1113 void invalidate_block(u_int block)
1116 u_int page=get_page(block<<12);
1117 u_int vpage=get_vpage(block<<12);
1118 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1122 struct ll_entry *head;
1123 head=jump_dirty[vpage];
1124 //printf("page=%d vpage=%d\n",page,vpage);
1127 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128 get_bounds((int)head->addr,&start,&end);
1129 //printf("start: %x end: %x\n",start,end);
1130 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1137 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1138 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1139 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1140 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1147 //printf("first=%d last=%d\n",first,last);
1148 modified=invalidate_page(page);
1149 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1150 assert(last<page+5);
1151 // Invalidate the adjacent pages if a block crosses a 4K boundary
1153 invalidate_page(first);
1156 for(first=page+1;first<last;first++) {
1157 invalidate_page(first);
1160 // Don't trap writes
1161 invalid_code[block]=1;
1163 // If there is a valid TLB entry for this page, remove write protect
1164 if(tlb_LUT_w[block]) {
1165 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1166 // CHECK: Is this right?
1167 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1168 u_int real_block=tlb_LUT_w[block]>>12;
1169 invalid_code[real_block]=1;
1170 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1172 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1176 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1179 memset(mini_ht,-1,sizeof(mini_ht));
1182 void invalidate_addr(u_int addr)
1184 invalidate_block(addr>>12);
1186 void invalidate_all_pages()
1189 for(page=0;page<4096;page++)
1190 invalidate_page(page);
1191 for(page=0;page<1048576;page++)
1192 if(!invalid_code[page]) {
1193 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1194 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1197 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1200 memset(mini_ht,-1,sizeof(mini_ht));
1204 for(page=0;page<0x100000;page++) {
1205 if(tlb_LUT_r[page]) {
1206 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1207 if(!tlb_LUT_w[page]||!invalid_code[page])
1208 memory_map[page]|=0x40000000; // Write protect
1210 else memory_map[page]=-1;
1211 if(page==0x80000) page=0xC0000;
1217 // Add an entry to jump_out after making a link
1218 void add_link(u_int vaddr,void *src)
1220 u_int page=get_page(vaddr);
1221 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1222 ll_add(jump_out+page,vaddr,src);
1223 //int ptr=get_pointer(src);
1224 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1227 // If a code block was found to be unmodified (bit was set in
1228 // restore_candidate) and it remains unmodified (bit is clear
1229 // in invalid_code) then move the entries for that 4K page from
1230 // the dirty list to the clean list.
1231 void clean_blocks(u_int page)
1233 struct ll_entry *head;
1234 inv_debug("INV: clean_blocks page=%d\n",page);
1235 head=jump_dirty[page];
1237 if(!invalid_code[head->vaddr>>12]) {
1238 // Don't restore blocks which are about to expire from the cache
1239 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1241 if(verify_dirty((int)head->addr)) {
1242 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1245 get_bounds((int)head->addr,&start,&end);
1246 if(start-(u_int)rdram<0x800000) {
1247 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1248 inv|=invalid_code[i];
1251 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1252 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1253 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1254 if(addr<start||addr>=end) inv=1;
1256 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1260 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1261 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1264 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1266 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1267 //printf("page=%x, addr=%x\n",page,head->vaddr);
1268 //assert(head->vaddr>>12==(page|0x80000));
1269 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1270 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1272 if(ht_bin[0]==head->vaddr) {
1273 ht_bin[1]=(int)clean_addr; // Replace existing entry
1275 if(ht_bin[2]==head->vaddr) {
1276 ht_bin[3]=(int)clean_addr; // Replace existing entry
1289 void mov_alloc(struct regstat *current,int i)
1291 // Note: Don't need to actually alloc the source registers
1292 if((~current->is32>>rs1[i])&1) {
1293 //alloc_reg64(current,i,rs1[i]);
1294 alloc_reg64(current,i,rt1[i]);
1295 current->is32&=~(1LL<<rt1[i]);
1297 //alloc_reg(current,i,rs1[i]);
1298 alloc_reg(current,i,rt1[i]);
1299 current->is32|=(1LL<<rt1[i]);
1301 clear_const(current,rs1[i]);
1302 clear_const(current,rt1[i]);
1303 dirty_reg(current,rt1[i]);
1306 void shiftimm_alloc(struct regstat *current,int i)
1308 clear_const(current,rs1[i]);
1309 clear_const(current,rt1[i]);
1310 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1313 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1315 alloc_reg(current,i,rt1[i]);
1316 current->is32|=1LL<<rt1[i];
1317 dirty_reg(current,rt1[i]);
1320 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1323 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1324 alloc_reg64(current,i,rt1[i]);
1325 current->is32&=~(1LL<<rt1[i]);
1326 dirty_reg(current,rt1[i]);
1329 if(opcode2[i]==0x3c) // DSLL32
1332 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1333 alloc_reg64(current,i,rt1[i]);
1334 current->is32&=~(1LL<<rt1[i]);
1335 dirty_reg(current,rt1[i]);
1338 if(opcode2[i]==0x3e) // DSRL32
1341 alloc_reg64(current,i,rs1[i]);
1343 alloc_reg64(current,i,rt1[i]);
1344 current->is32&=~(1LL<<rt1[i]);
1346 alloc_reg(current,i,rt1[i]);
1347 current->is32|=1LL<<rt1[i];
1349 dirty_reg(current,rt1[i]);
1352 if(opcode2[i]==0x3f) // DSRA32
1355 alloc_reg64(current,i,rs1[i]);
1356 alloc_reg(current,i,rt1[i]);
1357 current->is32|=1LL<<rt1[i];
1358 dirty_reg(current,rt1[i]);
1363 void shift_alloc(struct regstat *current,int i)
1366 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1368 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1369 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1370 alloc_reg(current,i,rt1[i]);
1371 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1372 current->is32|=1LL<<rt1[i];
1373 } else { // DSLLV/DSRLV/DSRAV
1374 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg64(current,i,rt1[i]);
1377 current->is32&=~(1LL<<rt1[i]);
1378 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1379 alloc_reg_temp(current,i,-1);
1381 clear_const(current,rs1[i]);
1382 clear_const(current,rs2[i]);
1383 clear_const(current,rt1[i]);
1384 dirty_reg(current,rt1[i]);
1388 void alu_alloc(struct regstat *current,int i)
1390 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1392 if(rs1[i]&&rs2[i]) {
1393 alloc_reg(current,i,rs1[i]);
1394 alloc_reg(current,i,rs2[i]);
1397 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1398 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1400 alloc_reg(current,i,rt1[i]);
1402 current->is32|=1LL<<rt1[i];
1404 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1406 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1408 alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rs2[i]);
1410 alloc_reg(current,i,rt1[i]);
1412 alloc_reg(current,i,rs1[i]);
1413 alloc_reg(current,i,rs2[i]);
1414 alloc_reg(current,i,rt1[i]);
1417 current->is32|=1LL<<rt1[i];
1419 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1421 if(rs1[i]&&rs2[i]) {
1422 alloc_reg(current,i,rs1[i]);
1423 alloc_reg(current,i,rs2[i]);
1427 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1428 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1430 alloc_reg(current,i,rt1[i]);
1431 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433 if(!((current->uu>>rt1[i])&1)) {
1434 alloc_reg64(current,i,rt1[i]);
1436 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1437 if(rs1[i]&&rs2[i]) {
1438 alloc_reg64(current,i,rs1[i]);
1439 alloc_reg64(current,i,rs2[i]);
1443 // Is is really worth it to keep 64-bit values in registers?
1445 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1446 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1450 current->is32&=~(1LL<<rt1[i]);
1452 current->is32|=1LL<<rt1[i];
1456 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1458 if(rs1[i]&&rs2[i]) {
1459 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1460 alloc_reg64(current,i,rs1[i]);
1461 alloc_reg64(current,i,rs2[i]);
1462 alloc_reg64(current,i,rt1[i]);
1464 alloc_reg(current,i,rs1[i]);
1465 alloc_reg(current,i,rs2[i]);
1466 alloc_reg(current,i,rt1[i]);
1470 alloc_reg(current,i,rt1[i]);
1471 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1472 // DADD used as move, or zeroing
1473 // If we have a 64-bit source, then make the target 64 bits too
1474 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1475 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1476 alloc_reg64(current,i,rt1[i]);
1477 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1478 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1479 alloc_reg64(current,i,rt1[i]);
1481 if(opcode2[i]>=0x2e&&rs2[i]) {
1482 // DSUB used as negation - 64-bit result
1483 // If we have a 32-bit register, extend it to 64 bits
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1489 if(rs1[i]&&rs2[i]) {
1490 current->is32&=~(1LL<<rt1[i]);
1492 current->is32&=~(1LL<<rt1[i]);
1493 if((current->is32>>rs1[i])&1)
1494 current->is32|=1LL<<rt1[i];
1496 current->is32&=~(1LL<<rt1[i]);
1497 if((current->is32>>rs2[i])&1)
1498 current->is32|=1LL<<rt1[i];
1500 current->is32|=1LL<<rt1[i];
1504 clear_const(current,rs1[i]);
1505 clear_const(current,rs2[i]);
1506 clear_const(current,rt1[i]);
1507 dirty_reg(current,rt1[i]);
1510 void imm16_alloc(struct regstat *current,int i)
1512 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1514 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1515 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1516 current->is32&=~(1LL<<rt1[i]);
1517 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1518 // TODO: Could preserve the 32-bit flag if the immediate is zero
1519 alloc_reg64(current,i,rt1[i]);
1520 alloc_reg64(current,i,rs1[i]);
1522 clear_const(current,rs1[i]);
1523 clear_const(current,rt1[i]);
1525 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1526 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1527 current->is32|=1LL<<rt1[i];
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1531 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1532 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1533 if(rs1[i]!=rt1[i]) {
1534 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1535 alloc_reg64(current,i,rt1[i]);
1536 current->is32&=~(1LL<<rt1[i]);
1539 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1540 if(is_const(current,rs1[i])) {
1541 int v=get_const(current,rs1[i]);
1542 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1543 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1544 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1546 else clear_const(current,rt1[i]);
1548 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1549 if(is_const(current,rs1[i])) {
1550 int v=get_const(current,rs1[i]);
1551 set_const(current,rt1[i],v+imm[i]);
1553 else clear_const(current,rt1[i]);
1554 current->is32|=1LL<<rt1[i];
1557 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1558 current->is32|=1LL<<rt1[i];
1560 dirty_reg(current,rt1[i]);
1563 void load_alloc(struct regstat *current,int i)
1565 clear_const(current,rt1[i]);
1566 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1567 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1568 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1570 alloc_reg(current,i,rt1[i]);
1571 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1573 current->is32&=~(1LL<<rt1[i]);
1574 alloc_reg64(current,i,rt1[i]);
1576 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1578 current->is32&=~(1LL<<rt1[i]);
1579 alloc_reg64(current,i,rt1[i]);
1580 alloc_all(current,i);
1581 alloc_reg64(current,i,FTEMP);
1583 else current->is32|=1LL<<rt1[i];
1584 dirty_reg(current,rt1[i]);
1585 // If using TLB, need a register for pointer to the mapping table
1586 if(using_tlb) alloc_reg(current,i,TLREG);
1587 // LWL/LWR need a temporary register for the old value
1588 if(opcode[i]==0x22||opcode[i]==0x26)
1590 alloc_reg(current,i,FTEMP);
1591 alloc_reg_temp(current,i,-1);
1596 // Load to r0 (dummy load)
1597 // but we still need a register to calculate the address
1598 alloc_reg_temp(current,i,-1);
1602 void store_alloc(struct regstat *current,int i)
1604 clear_const(current,rs2[i]);
1605 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1606 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1607 alloc_reg(current,i,rs2[i]);
1608 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1609 alloc_reg64(current,i,rs2[i]);
1610 if(rs2[i]) alloc_reg(current,i,FTEMP);
1612 // If using TLB, need a register for pointer to the mapping table
1613 if(using_tlb) alloc_reg(current,i,TLREG);
1614 #if defined(HOST_IMM8)
1615 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1616 else alloc_reg(current,i,INVCP);
1618 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1619 alloc_reg(current,i,FTEMP);
1621 // We need a temporary register for address generation
1622 alloc_reg_temp(current,i,-1);
1625 void c1ls_alloc(struct regstat *current,int i)
1627 //clear_const(current,rs1[i]); // FIXME
1628 clear_const(current,rt1[i]);
1629 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1630 alloc_reg(current,i,CSREG); // Status
1631 alloc_reg(current,i,FTEMP);
1632 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1633 alloc_reg64(current,i,FTEMP);
1635 // If using TLB, need a register for pointer to the mapping table
1636 if(using_tlb) alloc_reg(current,i,TLREG);
1637 #if defined(HOST_IMM8)
1638 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1639 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1640 alloc_reg(current,i,INVCP);
1642 // We need a temporary register for address generation
1643 alloc_reg_temp(current,i,-1);
1646 #ifndef multdiv_alloc
1647 void multdiv_alloc(struct regstat *current,int i)
1654 // case 0x1D: DMULTU
1657 clear_const(current,rs1[i]);
1658 clear_const(current,rs2[i]);
1661 if((opcode2[i]&4)==0) // 32-bit
1663 current->u&=~(1LL<<HIREG);
1664 current->u&=~(1LL<<LOREG);
1665 alloc_reg(current,i,HIREG);
1666 alloc_reg(current,i,LOREG);
1667 alloc_reg(current,i,rs1[i]);
1668 alloc_reg(current,i,rs2[i]);
1669 current->is32|=1LL<<HIREG;
1670 current->is32|=1LL<<LOREG;
1671 dirty_reg(current,HIREG);
1672 dirty_reg(current,LOREG);
1676 current->u&=~(1LL<<HIREG);
1677 current->u&=~(1LL<<LOREG);
1678 current->uu&=~(1LL<<HIREG);
1679 current->uu&=~(1LL<<LOREG);
1680 alloc_reg64(current,i,HIREG);
1681 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1682 alloc_reg64(current,i,rs1[i]);
1683 alloc_reg64(current,i,rs2[i]);
1684 alloc_all(current,i);
1685 current->is32&=~(1LL<<HIREG);
1686 current->is32&=~(1LL<<LOREG);
1687 dirty_reg(current,HIREG);
1688 dirty_reg(current,LOREG);
1693 // Multiply by zero is zero.
1694 // MIPS does not have a divide by zero exception.
1695 // The result is undefined, we return zero.
1696 alloc_reg(current,i,HIREG);
1697 alloc_reg(current,i,LOREG);
1698 current->is32|=1LL<<HIREG;
1699 current->is32|=1LL<<LOREG;
1700 dirty_reg(current,HIREG);
1701 dirty_reg(current,LOREG);
1706 void cop0_alloc(struct regstat *current,int i)
1708 if(opcode2[i]==0) // MFC0
1711 clear_const(current,rt1[i]);
1712 alloc_all(current,i);
1713 alloc_reg(current,i,rt1[i]);
1714 current->is32|=1LL<<rt1[i];
1715 dirty_reg(current,rt1[i]);
1718 else if(opcode2[i]==4) // MTC0
1721 clear_const(current,rs1[i]);
1722 alloc_reg(current,i,rs1[i]);
1723 alloc_all(current,i);
1726 alloc_all(current,i); // FIXME: Keep r0
1728 alloc_reg(current,i,0);
1733 // TLBR/TLBWI/TLBWR/TLBP/ERET
1734 assert(opcode2[i]==0x10);
1735 alloc_all(current,i);
1739 void cop1_alloc(struct regstat *current,int i)
1741 alloc_reg(current,i,CSREG); // Load status
1742 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1745 clear_const(current,rt1[i]);
1747 alloc_reg64(current,i,rt1[i]); // DMFC1
1748 current->is32&=~(1LL<<rt1[i]);
1750 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1751 current->is32|=1LL<<rt1[i];
1753 dirty_reg(current,rt1[i]);
1754 alloc_reg_temp(current,i,-1);
1756 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1759 clear_const(current,rs1[i]);
1761 alloc_reg64(current,i,rs1[i]); // DMTC1
1763 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1764 alloc_reg_temp(current,i,-1);
1768 alloc_reg(current,i,0);
1769 alloc_reg_temp(current,i,-1);
1773 void fconv_alloc(struct regstat *current,int i)
1775 alloc_reg(current,i,CSREG); // Load status
1776 alloc_reg_temp(current,i,-1);
1778 void float_alloc(struct regstat *current,int i)
1780 alloc_reg(current,i,CSREG); // Load status
1781 alloc_reg_temp(current,i,-1);
1783 void fcomp_alloc(struct regstat *current,int i)
1785 alloc_reg(current,i,CSREG); // Load status
1786 alloc_reg(current,i,FSREG); // Load flags
1787 dirty_reg(current,FSREG); // Flag will be modified
1788 alloc_reg_temp(current,i,-1);
1791 void syscall_alloc(struct regstat *current,int i)
1793 alloc_cc(current,i);
1794 dirty_reg(current,CCREG);
1795 alloc_all(current,i);
1799 void delayslot_alloc(struct regstat *current,int i)
1809 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1810 printf("Disabled speculative precompilation\n");
1814 imm16_alloc(current,i);
1818 load_alloc(current,i);
1822 store_alloc(current,i);
1825 alu_alloc(current,i);
1828 shift_alloc(current,i);
1831 multdiv_alloc(current,i);
1834 shiftimm_alloc(current,i);
1837 mov_alloc(current,i);
1840 cop0_alloc(current,i);
1843 cop1_alloc(current,i);
1846 c1ls_alloc(current,i);
1849 fconv_alloc(current,i);
1852 float_alloc(current,i);
1855 fcomp_alloc(current,i);
1860 // Special case where a branch and delay slot span two pages in virtual memory
1861 static void pagespan_alloc(struct regstat *current,int i)
1864 current->wasconst=0;
1866 alloc_all(current,i);
1867 alloc_cc(current,i);
1868 dirty_reg(current,CCREG);
1869 if(opcode[i]==3) // JAL
1871 alloc_reg(current,i,31);
1872 dirty_reg(current,31);
1874 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1876 alloc_reg(current,i,rs1[i]);
1878 alloc_reg(current,i,31);
1879 dirty_reg(current,31);
1882 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1884 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1885 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1886 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1888 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1889 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1893 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1895 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1896 if(!((current->is32>>rs1[i])&1))
1898 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1902 if(opcode[i]==0x11) // BC1
1904 alloc_reg(current,i,FSREG);
1905 alloc_reg(current,i,CSREG);
1910 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1912 stubs[stubcount][0]=type;
1913 stubs[stubcount][1]=addr;
1914 stubs[stubcount][2]=retaddr;
1915 stubs[stubcount][3]=a;
1916 stubs[stubcount][4]=b;
1917 stubs[stubcount][5]=c;
1918 stubs[stubcount][6]=d;
1919 stubs[stubcount][7]=e;
1923 // Write out a single register
1924 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1927 for(hr=0;hr<HOST_REGS;hr++) {
1928 if(hr!=EXCLUDE_REG) {
1929 if((regmap[hr]&63)==r) {
1932 emit_storereg(r,hr);
1934 if((is32>>regmap[hr])&1) {
1935 emit_sarimm(hr,31,hr);
1936 emit_storereg(r|64,hr);
1940 emit_storereg(r|64,hr);
1950 //if(!tracedebug) return 0;
1953 for(i=0;i<2097152;i++) {
1954 unsigned int temp=sum;
1957 sum^=((u_int *)rdram)[i];
1966 sum^=((u_int *)reg)[i];
1974 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1976 #ifndef DISABLE_COP1
1979 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1989 void memdebug(int i)
1991 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1992 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1995 //if(Count>=-2084597794) {
1996 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1998 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1999 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2000 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2003 printf("TRACE: %x\n",(&i)[-1]);
2007 printf("TRACE: %x \n",(&j)[10]);
2008 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2012 //printf("TRACE: %x\n",(&i)[-1]);
2015 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2017 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2020 void alu_assemble(int i,struct regstat *i_regs)
2022 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2024 signed char s1,s2,t;
2025 t=get_reg(i_regs->regmap,rt1[i]);
2027 s1=get_reg(i_regs->regmap,rs1[i]);
2028 s2=get_reg(i_regs->regmap,rs2[i]);
2029 if(rs1[i]&&rs2[i]) {
2032 if(opcode2[i]&2) emit_sub(s1,s2,t);
2033 else emit_add(s1,s2,t);
2036 if(s1>=0) emit_mov(s1,t);
2037 else emit_loadreg(rs1[i],t);
2041 if(opcode2[i]&2) emit_neg(s2,t);
2042 else emit_mov(s2,t);
2045 emit_loadreg(rs2[i],t);
2046 if(opcode2[i]&2) emit_neg(t,t);
2049 else emit_zeroreg(t);
2053 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2055 signed char s1l,s2l,s1h,s2h,tl,th;
2056 tl=get_reg(i_regs->regmap,rt1[i]);
2057 th=get_reg(i_regs->regmap,rt1[i]|64);
2059 s1l=get_reg(i_regs->regmap,rs1[i]);
2060 s2l=get_reg(i_regs->regmap,rs2[i]);
2061 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2062 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2063 if(rs1[i]&&rs2[i]) {
2066 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2067 else emit_adds(s1l,s2l,tl);
2069 #ifdef INVERTED_CARRY
2070 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2072 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2074 else emit_add(s1h,s2h,th);
2078 if(s1l>=0) emit_mov(s1l,tl);
2079 else emit_loadreg(rs1[i],tl);
2081 if(s1h>=0) emit_mov(s1h,th);
2082 else emit_loadreg(rs1[i]|64,th);
2087 if(opcode2[i]&2) emit_negs(s2l,tl);
2088 else emit_mov(s2l,tl);
2091 emit_loadreg(rs2[i],tl);
2092 if(opcode2[i]&2) emit_negs(tl,tl);
2095 #ifdef INVERTED_CARRY
2096 if(s2h>=0) emit_mov(s2h,th);
2097 else emit_loadreg(rs2[i]|64,th);
2099 emit_adcimm(-1,th); // x86 has inverted carry flag
2104 if(s2h>=0) emit_rscimm(s2h,0,th);
2106 emit_loadreg(rs2[i]|64,th);
2107 emit_rscimm(th,0,th);
2110 if(s2h>=0) emit_mov(s2h,th);
2111 else emit_loadreg(rs2[i]|64,th);
2118 if(th>=0) emit_zeroreg(th);
2123 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2125 signed char s1l,s1h,s2l,s2h,t;
2126 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2128 t=get_reg(i_regs->regmap,rt1[i]);
2131 s1l=get_reg(i_regs->regmap,rs1[i]);
2132 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2133 s2l=get_reg(i_regs->regmap,rs2[i]);
2134 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2135 if(rs2[i]==0) // rx<r0
2138 if(opcode2[i]==0x2a) // SLT
2139 emit_shrimm(s1h,31,t);
2140 else // SLTU (unsigned can not be less than zero)
2143 else if(rs1[i]==0) // r0<rx
2146 if(opcode2[i]==0x2a) // SLT
2147 emit_set_gz64_32(s2h,s2l,t);
2148 else // SLTU (set if not zero)
2149 emit_set_nz64_32(s2h,s2l,t);
2152 assert(s1l>=0);assert(s1h>=0);
2153 assert(s2l>=0);assert(s2h>=0);
2154 if(opcode2[i]==0x2a) // SLT
2155 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2157 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2161 t=get_reg(i_regs->regmap,rt1[i]);
2164 s1l=get_reg(i_regs->regmap,rs1[i]);
2165 s2l=get_reg(i_regs->regmap,rs2[i]);
2166 if(rs2[i]==0) // rx<r0
2169 if(opcode2[i]==0x2a) // SLT
2170 emit_shrimm(s1l,31,t);
2171 else // SLTU (unsigned can not be less than zero)
2174 else if(rs1[i]==0) // r0<rx
2177 if(opcode2[i]==0x2a) // SLT
2178 emit_set_gz32(s2l,t);
2179 else // SLTU (set if not zero)
2180 emit_set_nz32(s2l,t);
2183 assert(s1l>=0);assert(s2l>=0);
2184 if(opcode2[i]==0x2a) // SLT
2185 emit_set_if_less32(s1l,s2l,t);
2187 emit_set_if_carry32(s1l,s2l,t);
2193 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2195 signed char s1l,s1h,s2l,s2h,th,tl;
2196 tl=get_reg(i_regs->regmap,rt1[i]);
2197 th=get_reg(i_regs->regmap,rt1[i]|64);
2198 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2202 s1l=get_reg(i_regs->regmap,rs1[i]);
2203 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2204 s2l=get_reg(i_regs->regmap,rs2[i]);
2205 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2206 if(rs1[i]&&rs2[i]) {
2207 assert(s1l>=0);assert(s1h>=0);
2208 assert(s2l>=0);assert(s2h>=0);
2209 if(opcode2[i]==0x24) { // AND
2210 emit_and(s1l,s2l,tl);
2211 emit_and(s1h,s2h,th);
2213 if(opcode2[i]==0x25) { // OR
2214 emit_or(s1l,s2l,tl);
2215 emit_or(s1h,s2h,th);
2217 if(opcode2[i]==0x26) { // XOR
2218 emit_xor(s1l,s2l,tl);
2219 emit_xor(s1h,s2h,th);
2221 if(opcode2[i]==0x27) { // NOR
2222 emit_or(s1l,s2l,tl);
2223 emit_or(s1h,s2h,th);
2230 if(opcode2[i]==0x24) { // AND
2234 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2236 if(s1l>=0) emit_mov(s1l,tl);
2237 else emit_loadreg(rs1[i],tl);
2238 if(s1h>=0) emit_mov(s1h,th);
2239 else emit_loadreg(rs1[i]|64,th);
2243 if(s2l>=0) emit_mov(s2l,tl);
2244 else emit_loadreg(rs2[i],tl);
2245 if(s2h>=0) emit_mov(s2h,th);
2246 else emit_loadreg(rs2[i]|64,th);
2253 if(opcode2[i]==0x27) { // NOR
2255 if(s1l>=0) emit_not(s1l,tl);
2257 emit_loadreg(rs1[i],tl);
2260 if(s1h>=0) emit_not(s1h,th);
2262 emit_loadreg(rs1[i]|64,th);
2268 if(s2l>=0) emit_not(s2l,tl);
2270 emit_loadreg(rs2[i],tl);
2273 if(s2h>=0) emit_not(s2h,th);
2275 emit_loadreg(rs2[i]|64,th);
2291 s1l=get_reg(i_regs->regmap,rs1[i]);
2292 s2l=get_reg(i_regs->regmap,rs2[i]);
2293 if(rs1[i]&&rs2[i]) {
2296 if(opcode2[i]==0x24) { // AND
2297 emit_and(s1l,s2l,tl);
2299 if(opcode2[i]==0x25) { // OR
2300 emit_or(s1l,s2l,tl);
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2305 if(opcode2[i]==0x27) { // NOR
2306 emit_or(s1l,s2l,tl);
2312 if(opcode2[i]==0x24) { // AND
2315 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2317 if(s1l>=0) emit_mov(s1l,tl);
2318 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2322 if(s2l>=0) emit_mov(s2l,tl);
2323 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2325 else emit_zeroreg(tl);
2327 if(opcode2[i]==0x27) { // NOR
2329 if(s1l>=0) emit_not(s1l,tl);
2331 emit_loadreg(rs1[i],tl);
2337 if(s2l>=0) emit_not(s2l,tl);
2339 emit_loadreg(rs2[i],tl);
2343 else emit_movimm(-1,tl);
2352 void imm16_assemble(int i,struct regstat *i_regs)
2354 if (opcode[i]==0x0f) { // LUI
2357 t=get_reg(i_regs->regmap,rt1[i]);
2360 if(!((i_regs->isconst>>t)&1))
2361 emit_movimm(imm[i]<<16,t);
2365 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2368 t=get_reg(i_regs->regmap,rt1[i]);
2369 s=get_reg(i_regs->regmap,rs1[i]);
2374 if(!((i_regs->isconst>>t)&1)) {
2376 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2377 emit_addimm(t,imm[i],t);
2379 if(!((i_regs->wasconst>>s)&1))
2380 emit_addimm(s,imm[i],t);
2382 emit_movimm(constmap[i][s]+imm[i],t);
2388 if(!((i_regs->isconst>>t)&1))
2389 emit_movimm(imm[i],t);
2394 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2396 signed char sh,sl,th,tl;
2397 th=get_reg(i_regs->regmap,rt1[i]|64);
2398 tl=get_reg(i_regs->regmap,rt1[i]);
2399 sh=get_reg(i_regs->regmap,rs1[i]|64);
2400 sl=get_reg(i_regs->regmap,rs1[i]);
2406 emit_addimm64_32(sh,sl,imm[i],th,tl);
2409 emit_addimm(sl,imm[i],tl);
2412 emit_movimm(imm[i],tl);
2413 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2418 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2420 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2421 signed char sh,sl,t;
2422 t=get_reg(i_regs->regmap,rt1[i]);
2423 sh=get_reg(i_regs->regmap,rs1[i]|64);
2424 sl=get_reg(i_regs->regmap,rs1[i]);
2428 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2429 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2430 if(opcode[i]==0x0a) { // SLTI
2432 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2433 emit_slti32(t,imm[i],t);
2435 emit_slti32(sl,imm[i],t);
2440 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2441 emit_sltiu32(t,imm[i],t);
2443 emit_sltiu32(sl,imm[i],t);
2448 if(opcode[i]==0x0a) // SLTI
2449 emit_slti64_32(sh,sl,imm[i],t);
2451 emit_sltiu64_32(sh,sl,imm[i],t);
2454 // SLTI(U) with r0 is just stupid,
2455 // nonetheless examples can be found
2456 if(opcode[i]==0x0a) // SLTI
2457 if(0<imm[i]) emit_movimm(1,t);
2458 else emit_zeroreg(t);
2461 if(imm[i]) emit_movimm(1,t);
2462 else emit_zeroreg(t);
2468 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2470 signed char sh,sl,th,tl;
2471 th=get_reg(i_regs->regmap,rt1[i]|64);
2472 tl=get_reg(i_regs->regmap,rt1[i]);
2473 sh=get_reg(i_regs->regmap,rs1[i]|64);
2474 sl=get_reg(i_regs->regmap,rs1[i]);
2475 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2476 if(opcode[i]==0x0c) //ANDI
2480 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2481 emit_andimm(tl,imm[i],tl);
2483 if(!((i_regs->wasconst>>sl)&1))
2484 emit_andimm(sl,imm[i],tl);
2486 emit_movimm(constmap[i][sl]&imm[i],tl);
2491 if(th>=0) emit_zeroreg(th);
2497 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2501 emit_loadreg(rs1[i]|64,th);
2506 if(opcode[i]==0x0d) //ORI
2508 emit_orimm(tl,imm[i],tl);
2510 if(!((i_regs->wasconst>>sl)&1))
2511 emit_orimm(sl,imm[i],tl);
2513 emit_movimm(constmap[i][sl]|imm[i],tl);
2515 if(opcode[i]==0x0e) //XORI
2517 emit_xorimm(tl,imm[i],tl);
2519 if(!((i_regs->wasconst>>sl)&1))
2520 emit_xorimm(sl,imm[i],tl);
2522 emit_movimm(constmap[i][sl]^imm[i],tl);
2526 emit_movimm(imm[i],tl);
2527 if(th>=0) emit_zeroreg(th);
2535 void shiftimm_assemble(int i,struct regstat *i_regs)
2537 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2541 t=get_reg(i_regs->regmap,rt1[i]);
2542 s=get_reg(i_regs->regmap,rs1[i]);
2551 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2553 if(opcode2[i]==0) // SLL
2555 emit_shlimm(s<0?t:s,imm[i],t);
2557 if(opcode2[i]==2) // SRL
2559 emit_shrimm(s<0?t:s,imm[i],t);
2561 if(opcode2[i]==3) // SRA
2563 emit_sarimm(s<0?t:s,imm[i],t);
2567 if(s>=0 && s!=t) emit_mov(s,t);
2571 //emit_storereg(rt1[i],t); //DEBUG
2574 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2577 signed char sh,sl,th,tl;
2578 th=get_reg(i_regs->regmap,rt1[i]|64);
2579 tl=get_reg(i_regs->regmap,rt1[i]);
2580 sh=get_reg(i_regs->regmap,rs1[i]|64);
2581 sl=get_reg(i_regs->regmap,rs1[i]);
2586 if(th>=0) emit_zeroreg(th);
2593 if(opcode2[i]==0x38) // DSLL
2595 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2596 emit_shlimm(sl,imm[i],tl);
2598 if(opcode2[i]==0x3a) // DSRL
2600 emit_shrdimm(sl,sh,imm[i],tl);
2601 if(th>=0) emit_shrimm(sh,imm[i],th);
2603 if(opcode2[i]==0x3b) // DSRA
2605 emit_shrdimm(sl,sh,imm[i],tl);
2606 if(th>=0) emit_sarimm(sh,imm[i],th);
2610 if(sl!=tl) emit_mov(sl,tl);
2611 if(th>=0&&sh!=th) emit_mov(sh,th);
2617 if(opcode2[i]==0x3c) // DSLL32
2620 signed char sl,tl,th;
2621 tl=get_reg(i_regs->regmap,rt1[i]);
2622 th=get_reg(i_regs->regmap,rt1[i]|64);
2623 sl=get_reg(i_regs->regmap,rs1[i]);
2632 emit_shlimm(th,imm[i]&31,th);
2637 if(opcode2[i]==0x3e) // DSRL32
2640 signed char sh,tl,th;
2641 tl=get_reg(i_regs->regmap,rt1[i]);
2642 th=get_reg(i_regs->regmap,rt1[i]|64);
2643 sh=get_reg(i_regs->regmap,rs1[i]|64);
2647 if(th>=0) emit_zeroreg(th);
2650 emit_shrimm(tl,imm[i]&31,tl);
2655 if(opcode2[i]==0x3f) // DSRA32
2659 tl=get_reg(i_regs->regmap,rt1[i]);
2660 sh=get_reg(i_regs->regmap,rs1[i]|64);
2666 emit_sarimm(tl,imm[i]&31,tl);
2673 #ifndef shift_assemble
2674 void shift_assemble(int i,struct regstat *i_regs)
2676 printf("Need shift_assemble for this architecture.\n");
2681 void load_assemble(int i,struct regstat *i_regs)
2683 int s,th,tl,addr,map=-1;
2688 th=get_reg(i_regs->regmap,rt1[i]|64);
2689 tl=get_reg(i_regs->regmap,rt1[i]);
2690 s=get_reg(i_regs->regmap,rs1[i]);
2692 for(hr=0;hr<HOST_REGS;hr++) {
2693 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2695 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2697 c=(i_regs->wasconst>>s)&1;
2698 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2699 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2701 if(offset||s<0||c) addr=tl;
2703 //printf("load_assemble: c=%d\n",c);
2704 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2705 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2710 if(th>=0) reglist&=~(1<<th);
2713 //#define R29_HACK 1
2715 // Strmnnrmn's speed hack
2716 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2719 emit_cmpimm(addr,0x800000);
2721 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2722 // Hint to branch predictor that the branch is unlikely to be taken
2724 emit_jno_unlikely(0);
2732 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2733 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2734 map=get_reg(i_regs->regmap,TLREG);
2736 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2737 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2739 if (opcode[i]==0x20) { // LB
2741 #ifdef HOST_IMM_ADDR32
2743 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2747 //emit_xorimm(addr,3,tl);
2748 //gen_tlb_addr_r(tl,map);
2749 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2751 #ifdef BIG_ENDIAN_MIPS
2752 if(!c) emit_xorimm(addr,3,tl);
2753 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2755 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2756 else if (tl!=addr) emit_mov(addr,tl);
2758 emit_movsbl_indexed_tlb(x,tl,map,tl);
2761 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2764 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2766 if (opcode[i]==0x21) { // LH
2768 #ifdef HOST_IMM_ADDR32
2770 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2775 #ifdef BIG_ENDIAN_MIPS
2776 if(!c) emit_xorimm(addr,2,tl);
2777 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2779 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2780 else if (tl!=addr) emit_mov(addr,tl);
2783 //emit_movswl_indexed_tlb(x,tl,map,tl);
2786 gen_tlb_addr_r(tl,map);
2787 emit_movswl_indexed(x,tl,tl);
2789 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2792 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2795 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2797 if (opcode[i]==0x23) { // LW
2799 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2800 #ifdef HOST_IMM_ADDR32
2802 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2805 emit_readword_indexed_tlb(0,addr,map,tl);
2807 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2810 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2812 if (opcode[i]==0x24) { // LBU
2814 #ifdef HOST_IMM_ADDR32
2816 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2820 //emit_xorimm(addr,3,tl);
2821 //gen_tlb_addr_r(tl,map);
2822 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2824 #ifdef BIG_ENDIAN_MIPS
2825 if(!c) emit_xorimm(addr,3,tl);
2826 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2828 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2829 else if (tl!=addr) emit_mov(addr,tl);
2831 emit_movzbl_indexed_tlb(x,tl,map,tl);
2834 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2837 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2839 if (opcode[i]==0x25) { // LHU
2841 #ifdef HOST_IMM_ADDR32
2843 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2848 #ifdef BIG_ENDIAN_MIPS
2849 if(!c) emit_xorimm(addr,2,tl);
2850 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2852 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2853 else if (tl!=addr) emit_mov(addr,tl);
2856 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2859 gen_tlb_addr_r(tl,map);
2860 emit_movzwl_indexed(x,tl,tl);
2862 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2864 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2868 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2870 if (opcode[i]==0x27) { // LWU
2873 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2874 #ifdef HOST_IMM_ADDR32
2876 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2879 emit_readword_indexed_tlb(0,addr,map,tl);
2881 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2884 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2888 if (opcode[i]==0x37) { // LD
2890 //gen_tlb_addr_r(tl,map);
2891 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2892 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2893 #ifdef HOST_IMM_ADDR32
2895 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2898 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2900 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2903 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2905 //emit_storereg(rt1[i],tl); // DEBUG
2907 //if(opcode[i]==0x23)
2908 //if(opcode[i]==0x24)
2909 //if(opcode[i]==0x23||opcode[i]==0x24)
2910 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2914 emit_readword((int)&last_count,ECX);
2916 if(get_reg(i_regs->regmap,CCREG)<0)
2917 emit_loadreg(CCREG,HOST_CCREG);
2918 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2919 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2920 emit_writeword(HOST_CCREG,(int)&Count);
2923 if(get_reg(i_regs->regmap,CCREG)<0)
2924 emit_loadreg(CCREG,0);
2926 emit_mov(HOST_CCREG,0);
2928 emit_addimm(0,2*ccadj[i],0);
2929 emit_writeword(0,(int)&Count);
2931 emit_call((int)memdebug);
2933 restore_regs(0x100f);
2937 #ifndef loadlr_assemble
2938 void loadlr_assemble(int i,struct regstat *i_regs)
2940 printf("Need loadlr_assemble for this architecture.\n");
2945 void store_assemble(int i,struct regstat *i_regs)
2950 int jaddr=0,jaddr2,type;
2952 int agr=AGEN1+(i&1);
2954 th=get_reg(i_regs->regmap,rs2[i]|64);
2955 tl=get_reg(i_regs->regmap,rs2[i]);
2956 s=get_reg(i_regs->regmap,rs1[i]);
2957 temp=get_reg(i_regs->regmap,agr);
2958 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2961 c=(i_regs->wasconst>>s)&1;
2962 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2963 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2967 for(hr=0;hr<HOST_REGS;hr++) {
2968 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2970 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2971 if(offset||s<0||c) addr=temp;
2976 // Strmnnrmn's speed hack
2978 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2980 emit_cmpimm(addr,0x800000);
2981 #ifdef DESTRUCTIVE_SHIFT
2982 if(s==addr) emit_mov(s,temp);
2985 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2989 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2990 // Hint to branch predictor that the branch is unlikely to be taken
2992 emit_jno_unlikely(0);
3000 if (opcode[i]==0x28) x=3; // SB
3001 if (opcode[i]==0x29) x=2; // SH
3002 map=get_reg(i_regs->regmap,TLREG);
3004 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3005 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3008 if (opcode[i]==0x28) { // SB
3011 #ifdef BIG_ENDIAN_MIPS
3012 if(!c) emit_xorimm(addr,3,temp);
3013 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3015 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3016 else if (addr!=temp) emit_mov(addr,temp);
3018 //gen_tlb_addr_w(temp,map);
3019 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3020 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3024 if (opcode[i]==0x29) { // SH
3027 #ifdef BIG_ENDIAN_MIPS
3028 if(!c) emit_xorimm(addr,2,temp);
3029 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3031 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3032 else if (addr!=temp) emit_mov(addr,temp);
3035 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3038 gen_tlb_addr_w(temp,map);
3039 emit_writehword_indexed(tl,x,temp);
3041 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3045 if (opcode[i]==0x2B) { // SW
3047 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3048 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3051 if (opcode[i]==0x3F) { // SD
3055 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3056 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3057 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3060 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3061 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3062 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3068 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3069 } else if(!memtarget) {
3070 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3074 #ifdef DESTRUCTIVE_SHIFT
3075 // The x86 shift operation is 'destructive'; it overwrites the
3076 // source register, so we need to make a copy first and use that.
3079 #if defined(HOST_IMM8)
3080 int ir=get_reg(i_regs->regmap,INVCP);
3082 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3084 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3088 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3091 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3092 //if(opcode[i]==0x2B || opcode[i]==0x28)
3093 //if(opcode[i]==0x2B || opcode[i]==0x29)
3094 //if(opcode[i]==0x2B)
3095 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3099 emit_readword((int)&last_count,ECX);
3101 if(get_reg(i_regs->regmap,CCREG)<0)
3102 emit_loadreg(CCREG,HOST_CCREG);
3103 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3104 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3105 emit_writeword(HOST_CCREG,(int)&Count);
3108 if(get_reg(i_regs->regmap,CCREG)<0)
3109 emit_loadreg(CCREG,0);
3111 emit_mov(HOST_CCREG,0);
3113 emit_addimm(0,2*ccadj[i],0);
3114 emit_writeword(0,(int)&Count);
3116 emit_call((int)memdebug);
3118 restore_regs(0x100f);
3122 void storelr_assemble(int i,struct regstat *i_regs)
3129 int case1,case2,case3;
3130 int done0,done1,done2;
3133 th=get_reg(i_regs->regmap,rs2[i]|64);
3134 tl=get_reg(i_regs->regmap,rs2[i]);
3135 s=get_reg(i_regs->regmap,rs1[i]);
3136 temp=get_reg(i_regs->regmap,-1);
3139 c=(i_regs->isconst>>s)&1;
3140 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3141 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3144 for(hr=0;hr<HOST_REGS;hr++) {
3145 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3151 emit_cmpimm(s<0||offset?temp:s,0x800000);
3152 if(!offset&&s!=temp) emit_mov(s,temp);
3158 if(!memtarget||!rs1[i]) {
3163 if((u_int)rdram!=0x80000000)
3164 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3166 int map=get_reg(i_regs->regmap,TLREG);
3168 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3169 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3170 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3171 if(!jaddr&&!memtarget) {
3175 gen_tlb_addr_w(temp,map);
3178 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3179 temp2=get_reg(i_regs->regmap,FTEMP);
3180 if(!rs2[i]) temp2=th=tl;
3183 #ifndef BIG_ENDIAN_MIPS
3184 emit_xorimm(temp,3,temp);
3186 emit_testimm(temp,2);
3189 emit_testimm(temp,1);
3193 if (opcode[i]==0x2A) { // SWL
3194 emit_writeword_indexed(tl,0,temp);
3196 if (opcode[i]==0x2E) { // SWR
3197 emit_writebyte_indexed(tl,3,temp);
3199 if (opcode[i]==0x2C) { // SDL
3200 emit_writeword_indexed(th,0,temp);
3201 if(rs2[i]) emit_mov(tl,temp2);
3203 if (opcode[i]==0x2D) { // SDR
3204 emit_writebyte_indexed(tl,3,temp);
3205 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3210 set_jump_target(case1,(int)out);
3211 if (opcode[i]==0x2A) { // SWL
3212 // Write 3 msb into three least significant bytes
3213 if(rs2[i]) emit_rorimm(tl,8,tl);
3214 emit_writehword_indexed(tl,-1,temp);
3215 if(rs2[i]) emit_rorimm(tl,16,tl);
3216 emit_writebyte_indexed(tl,1,temp);
3217 if(rs2[i]) emit_rorimm(tl,8,tl);
3219 if (opcode[i]==0x2E) { // SWR
3220 // Write two lsb into two most significant bytes
3221 emit_writehword_indexed(tl,1,temp);
3223 if (opcode[i]==0x2C) { // SDL
3224 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3225 // Write 3 msb into three least significant bytes
3226 if(rs2[i]) emit_rorimm(th,8,th);
3227 emit_writehword_indexed(th,-1,temp);
3228 if(rs2[i]) emit_rorimm(th,16,th);
3229 emit_writebyte_indexed(th,1,temp);
3230 if(rs2[i]) emit_rorimm(th,8,th);
3232 if (opcode[i]==0x2D) { // SDR
3233 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3234 // Write two lsb into two most significant bytes
3235 emit_writehword_indexed(tl,1,temp);
3240 set_jump_target(case2,(int)out);
3241 emit_testimm(temp,1);
3244 if (opcode[i]==0x2A) { // SWL
3245 // Write two msb into two least significant bytes
3246 if(rs2[i]) emit_rorimm(tl,16,tl);
3247 emit_writehword_indexed(tl,-2,temp);
3248 if(rs2[i]) emit_rorimm(tl,16,tl);
3250 if (opcode[i]==0x2E) { // SWR
3251 // Write 3 lsb into three most significant bytes
3252 emit_writebyte_indexed(tl,-1,temp);
3253 if(rs2[i]) emit_rorimm(tl,8,tl);
3254 emit_writehword_indexed(tl,0,temp);
3255 if(rs2[i]) emit_rorimm(tl,24,tl);
3257 if (opcode[i]==0x2C) { // SDL
3258 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3259 // Write two msb into two least significant bytes
3260 if(rs2[i]) emit_rorimm(th,16,th);
3261 emit_writehword_indexed(th,-2,temp);
3262 if(rs2[i]) emit_rorimm(th,16,th);
3264 if (opcode[i]==0x2D) { // SDR
3265 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3266 // Write 3 lsb into three most significant bytes
3267 emit_writebyte_indexed(tl,-1,temp);
3268 if(rs2[i]) emit_rorimm(tl,8,tl);
3269 emit_writehword_indexed(tl,0,temp);
3270 if(rs2[i]) emit_rorimm(tl,24,tl);
3275 set_jump_target(case3,(int)out);
3276 if (opcode[i]==0x2A) { // SWL
3277 // Write msb into least significant byte
3278 if(rs2[i]) emit_rorimm(tl,24,tl);
3279 emit_writebyte_indexed(tl,-3,temp);
3280 if(rs2[i]) emit_rorimm(tl,8,tl);
3282 if (opcode[i]==0x2E) { // SWR
3283 // Write entire word
3284 emit_writeword_indexed(tl,-3,temp);
3286 if (opcode[i]==0x2C) { // SDL
3287 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3288 // Write msb into least significant byte
3289 if(rs2[i]) emit_rorimm(th,24,th);
3290 emit_writebyte_indexed(th,-3,temp);
3291 if(rs2[i]) emit_rorimm(th,8,th);
3293 if (opcode[i]==0x2D) { // SDR
3294 if(rs2[i]) emit_mov(th,temp2);
3295 // Write entire word
3296 emit_writeword_indexed(tl,-3,temp);
3298 set_jump_target(done0,(int)out);
3299 set_jump_target(done1,(int)out);
3300 set_jump_target(done2,(int)out);
3301 if (opcode[i]==0x2C) { // SDL
3302 emit_testimm(temp,4);
3305 emit_andimm(temp,~3,temp);
3306 emit_writeword_indexed(temp2,4,temp);
3307 set_jump_target(done0,(int)out);
3309 if (opcode[i]==0x2D) { // SDR
3310 emit_testimm(temp,4);
3313 emit_andimm(temp,~3,temp);
3314 emit_writeword_indexed(temp2,-4,temp);
3315 set_jump_target(done0,(int)out);
3318 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3321 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3322 #if defined(HOST_IMM8)
3323 int ir=get_reg(i_regs->regmap,INVCP);
3325 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3327 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3331 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3335 //save_regs(0x100f);
3336 emit_readword((int)&last_count,ECX);
3337 if(get_reg(i_regs->regmap,CCREG)<0)
3338 emit_loadreg(CCREG,HOST_CCREG);
3339 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3340 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3341 emit_writeword(HOST_CCREG,(int)&Count);
3342 emit_call((int)memdebug);
3344 //restore_regs(0x100f);
3348 void c1ls_assemble(int i,struct regstat *i_regs)
3350 #ifndef DISABLE_COP1
3356 int jaddr,jaddr2=0,jaddr3,type;
3357 int agr=AGEN1+(i&1);
3359 th=get_reg(i_regs->regmap,FTEMP|64);
3360 tl=get_reg(i_regs->regmap,FTEMP);
3361 s=get_reg(i_regs->regmap,rs1[i]);
3362 temp=get_reg(i_regs->regmap,agr);
3363 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3368 for(hr=0;hr<HOST_REGS;hr++) {
3369 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3371 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3372 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3374 // Loads use a temporary register which we need to save
3377 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3381 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3382 //else c=(i_regs->wasconst>>s)&1;
3383 if(s>=0) c=(i_regs->wasconst>>s)&1;
3384 // Check cop1 unusable
3386 signed char rs=get_reg(i_regs->regmap,CSREG);
3388 emit_testimm(rs,0x20000000);
3391 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3394 if (opcode[i]==0x39) { // SWC1 (get float address)
3395 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3397 if (opcode[i]==0x3D) { // SDC1 (get double address)
3398 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3400 // Generate address + offset
3403 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3407 map=get_reg(i_regs->regmap,TLREG);
3409 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3410 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3412 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3413 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3416 if (opcode[i]==0x39) { // SWC1 (read float)
3417 emit_readword_indexed(0,tl,tl);
3419 if (opcode[i]==0x3D) { // SDC1 (read double)
3420 emit_readword_indexed(4,tl,th);
3421 emit_readword_indexed(0,tl,tl);
3423 if (opcode[i]==0x31) { // LWC1 (get target address)
3424 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3426 if (opcode[i]==0x35) { // LDC1 (get target address)
3427 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3434 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3436 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3438 #ifdef DESTRUCTIVE_SHIFT
3439 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3440 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3444 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3445 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3447 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3448 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3451 if (opcode[i]==0x31) { // LWC1
3452 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3453 //gen_tlb_addr_r(ar,map);
3454 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3455 #ifdef HOST_IMM_ADDR32
3456 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3459 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3462 if (opcode[i]==0x35) { // LDC1
3464 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3465 //gen_tlb_addr_r(ar,map);
3466 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3467 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3468 #ifdef HOST_IMM_ADDR32
3469 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3472 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3475 if (opcode[i]==0x39) { // SWC1
3476 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3477 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3480 if (opcode[i]==0x3D) { // SDC1
3482 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3483 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3484 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3488 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3489 #ifndef DESTRUCTIVE_SHIFT
3490 temp=offset||c||s<0?ar:s;
3492 #if defined(HOST_IMM8)
3493 int ir=get_reg(i_regs->regmap,INVCP);
3495 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3497 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3501 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3504 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3505 if (opcode[i]==0x31) { // LWC1 (write float)
3506 emit_writeword_indexed(tl,0,temp);
3508 if (opcode[i]==0x35) { // LDC1 (write double)
3509 emit_writeword_indexed(th,4,temp);
3510 emit_writeword_indexed(tl,0,temp);
3512 //if(opcode[i]==0x39)
3513 /*if(opcode[i]==0x39||opcode[i]==0x31)
3516 emit_readword((int)&last_count,ECX);
3517 if(get_reg(i_regs->regmap,CCREG)<0)
3518 emit_loadreg(CCREG,HOST_CCREG);
3519 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3520 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3521 emit_writeword(HOST_CCREG,(int)&Count);
3522 emit_call((int)memdebug);
3526 cop1_unusable(i, i_regs);
3530 #ifndef multdiv_assemble
3531 void multdiv_assemble(int i,struct regstat *i_regs)
3533 printf("Need multdiv_assemble for this architecture.\n");
3538 void mov_assemble(int i,struct regstat *i_regs)
3540 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3541 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3544 signed char sh,sl,th,tl;
3545 th=get_reg(i_regs->regmap,rt1[i]|64);
3546 tl=get_reg(i_regs->regmap,rt1[i]);
3549 sh=get_reg(i_regs->regmap,rs1[i]|64);
3550 sl=get_reg(i_regs->regmap,rs1[i]);
3551 if(sl>=0) emit_mov(sl,tl);
3552 else emit_loadreg(rs1[i],tl);
3554 if(sh>=0) emit_mov(sh,th);
3555 else emit_loadreg(rs1[i]|64,th);
3561 #ifndef fconv_assemble
3562 void fconv_assemble(int i,struct regstat *i_regs)
3564 printf("Need fconv_assemble for this architecture.\n");
3570 void float_assemble(int i,struct regstat *i_regs)
3572 printf("Need float_assemble for this architecture.\n");
3577 void syscall_assemble(int i,struct regstat *i_regs)
3579 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3580 assert(ccreg==HOST_CCREG);
3581 assert(!is_delayslot);
3582 emit_movimm(start+i*4,EAX); // Get PC
3583 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3584 emit_jmp((int)jump_syscall);
3587 void ds_assemble(int i,struct regstat *i_regs)
3592 alu_assemble(i,i_regs);break;
3594 imm16_assemble(i,i_regs);break;
3596 shift_assemble(i,i_regs);break;
3598 shiftimm_assemble(i,i_regs);break;
3600 load_assemble(i,i_regs);break;
3602 loadlr_assemble(i,i_regs);break;
3604 store_assemble(i,i_regs);break;
3606 storelr_assemble(i,i_regs);break;
3608 cop0_assemble(i,i_regs);break;
3610 cop1_assemble(i,i_regs);break;
3612 c1ls_assemble(i,i_regs);break;
3614 fconv_assemble(i,i_regs);break;
3616 float_assemble(i,i_regs);break;
3618 fcomp_assemble(i,i_regs);break;
3620 multdiv_assemble(i,i_regs);break;
3622 mov_assemble(i,i_regs);break;
3630 printf("Jump in the delay slot. This is probably a bug.\n");
3635 // Is the branch target a valid internal jump?
3636 int internal_branch(uint64_t i_is32,int addr)
3638 if(addr&1) return 0; // Indirect (register) jump
3639 if(addr>=start && addr<start+slen*4-4)
3641 int t=(addr-start)>>2;
3642 // Delay slots are not valid branch targets
3643 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3644 // 64 -> 32 bit transition requires a recompile
3645 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3647 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3648 else printf("optimizable: yes\n");
3650 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3651 if(requires_32bit[t]&~i_is32) return 0;
3657 #ifndef wb_invalidate
3658 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3659 uint64_t u,uint64_t uu)
3662 for(hr=0;hr<HOST_REGS;hr++) {
3663 if(hr!=EXCLUDE_REG) {
3664 if(pre[hr]!=entry[hr]) {
3667 if(get_reg(entry,pre[hr])<0) {
3669 if(!((u>>pre[hr])&1)) {
3670 emit_storereg(pre[hr],hr);
3671 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3672 emit_sarimm(hr,31,hr);
3673 emit_storereg(pre[hr]|64,hr);
3677 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3678 emit_storereg(pre[hr],hr);
3687 // Move from one register to another (no writeback)
3688 for(hr=0;hr<HOST_REGS;hr++) {
3689 if(hr!=EXCLUDE_REG) {
3690 if(pre[hr]!=entry[hr]) {
3691 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3693 if((nr=get_reg(entry,pre[hr]))>=0) {
3703 // Load the specified registers
3704 // This only loads the registers given as arguments because
3705 // we don't want to load things that will be overwritten
3706 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3710 for(hr=0;hr<HOST_REGS;hr++) {
3711 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3712 if(entry[hr]!=regmap[hr]) {
3713 if(regmap[hr]==rs1||regmap[hr]==rs2)
3720 emit_loadreg(regmap[hr],hr);
3727 for(hr=0;hr<HOST_REGS;hr++) {
3728 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3729 if(entry[hr]!=regmap[hr]) {
3730 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3732 assert(regmap[hr]!=64);
3733 if((is32>>(regmap[hr]&63))&1) {
3734 int lr=get_reg(regmap,regmap[hr]-64);
3736 emit_sarimm(lr,31,hr);
3738 emit_loadreg(regmap[hr],hr);
3742 emit_loadreg(regmap[hr],hr);
3750 // Load registers prior to the start of a loop
3751 // so that they are not loaded within the loop
3752 static void loop_preload(signed char pre[],signed char entry[])
3755 for(hr=0;hr<HOST_REGS;hr++) {
3756 if(hr!=EXCLUDE_REG) {
3757 if(pre[hr]!=entry[hr]) {
3759 if(get_reg(pre,entry[hr])<0) {
3760 assem_debug("loop preload:\n");
3761 //printf("loop preload: %d\n",hr);
3765 else if(entry[hr]<TEMPREG)
3767 emit_loadreg(entry[hr],hr);
3769 else if(entry[hr]-64<TEMPREG)
3771 emit_loadreg(entry[hr],hr);
3780 // Generate address for load/store instruction
3781 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3783 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3785 int agr=AGEN1+(i&1);
3786 int mgr=MGEN1+(i&1);
3787 if(itype[i]==LOAD) {
3788 ra=get_reg(i_regs->regmap,rt1[i]);
3789 //if(rt1[i]) assert(ra>=0);
3791 if(itype[i]==LOADLR) {
3792 ra=get_reg(i_regs->regmap,FTEMP);
3794 if(itype[i]==STORE||itype[i]==STORELR) {
3795 ra=get_reg(i_regs->regmap,agr);
3796 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3798 if(itype[i]==C1LS) {
3799 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3800 ra=get_reg(i_regs->regmap,FTEMP);
3802 ra=get_reg(i_regs->regmap,agr);
3803 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3806 int rs=get_reg(i_regs->regmap,rs1[i]);
3807 int rm=get_reg(i_regs->regmap,TLREG);
3810 int c=(i_regs->wasconst>>rs)&1;
3812 // Using r0 as a base address
3814 if(!entry||entry[rm]!=mgr) {
3815 generate_map_const(offset,rm);
3816 } // else did it in the previous cycle
3818 if(!entry||entry[ra]!=agr) {
3819 if (opcode[i]==0x22||opcode[i]==0x26) {
3820 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3821 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3822 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3824 emit_movimm(offset,ra);
3826 } // else did it in the previous cycle
3829 if(!entry||entry[ra]!=rs1[i])
3830 emit_loadreg(rs1[i],ra);
3831 //if(!entry||entry[ra]!=rs1[i])
3832 // printf("poor load scheduling!\n");
3836 if(!entry||entry[rm]!=mgr) {
3837 if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3838 // Stores to memory go thru the mapper to detect self-modifying
3839 // code, loads don't.
3840 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3841 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3842 generate_map_const(constmap[i][rs]+offset,rm);
3844 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3845 generate_map_const(constmap[i][rs]+offset,rm);
3849 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3850 if(!entry||entry[ra]!=agr) {
3851 if (opcode[i]==0x22||opcode[i]==0x26) {
3852 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3853 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3854 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3856 #ifdef HOST_IMM_ADDR32
3857 if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3858 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3860 emit_movimm(constmap[i][rs]+offset,ra);
3862 } // else did it in the previous cycle
3863 } // else load_consts already did it
3865 if(offset&&!c&&rs1[i]) {
3867 emit_addimm(rs,offset,ra);
3869 emit_addimm(ra,offset,ra);
3874 // Preload constants for next instruction
3875 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3877 #ifndef HOST_IMM_ADDR32
3879 agr=MGEN1+((i+1)&1);
3880 ra=get_reg(i_regs->regmap,agr);
3882 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3883 int offset=imm[i+1];
3884 int c=(regs[i+1].wasconst>>rs)&1;
3886 if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3887 // Stores to memory go thru the mapper to detect self-modifying
3888 // code, loads don't.
3889 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3890 (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3891 generate_map_const(constmap[i+1][rs]+offset,ra);
3893 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3894 generate_map_const(constmap[i+1][rs]+offset,ra);
3897 /*else if(rs1[i]==0) {
3898 generate_map_const(offset,ra);
3903 agr=AGEN1+((i+1)&1);
3904 ra=get_reg(i_regs->regmap,agr);
3906 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3907 int offset=imm[i+1];
3908 int c=(regs[i+1].wasconst>>rs)&1;
3909 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3910 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3911 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3912 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3913 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR