drc: attempt to support little endian
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
138#define FTEMP 38 // FPU temporary register
139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
178
179 /* stubs */
180#define CC_STUB 1
181#define FP_STUB 2
182#define LOADB_STUB 3
183#define LOADH_STUB 4
184#define LOADW_STUB 5
185#define LOADD_STUB 6
186#define LOADBU_STUB 7
187#define LOADHU_STUB 8
188#define STOREB_STUB 9
189#define STOREH_STUB 10
190#define STOREW_STUB 11
191#define STORED_STUB 12
192#define STORELR_STUB 13
193#define INVCODE_STUB 14
194
195 /* branch codes */
196#define TAKEN 1
197#define NOTTAKEN 2
198#define NULLDS 3
199
200// asm linkage
201int new_recompile_block(int addr);
202void *get_addr_ht(u_int vaddr);
203void invalidate_block(u_int block);
204void invalidate_addr(u_int addr);
205void remove_hash(int vaddr);
206void jump_vaddr();
207void dyna_linker();
208void dyna_linker_ds();
209void verify_code();
210void verify_code_vm();
211void verify_code_ds();
212void cc_interrupt();
213void fp_exception();
214void fp_exception_ds();
215void jump_syscall();
216void jump_eret();
217
218// TLB
219void TLBWI_new();
220void TLBWR_new();
221void read_nomem_new();
222void read_nomemb_new();
223void read_nomemh_new();
224void read_nomemd_new();
225void write_nomem_new();
226void write_nomemb_new();
227void write_nomemh_new();
228void write_nomemd_new();
229void write_rdram_new();
230void write_rdramb_new();
231void write_rdramh_new();
232void write_rdramd_new();
233extern u_int memory_map[1048576];
234
235// Needed by assembler
236void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
237void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
238void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
239void load_all_regs(signed char i_regmap[]);
240void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
241void load_regs_entry(int t);
242void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
243
244int tracedebug=0;
245
246//#define DEBUG_CYCLE_COUNT 1
247
248void nullf() {}
249//#define assem_debug printf
250//#define inv_debug printf
251#define assem_debug nullf
252#define inv_debug nullf
253
94d23bb9 254static void tlb_hacks()
57871462 255{
94d23bb9 256#ifndef DISABLE_TLB
57871462 257 // Goldeneye hack
258 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
259 {
260 u_int addr;
261 int n;
262 switch (ROM_HEADER->Country_code&0xFF)
263 {
264 case 0x45: // U
265 addr=0x34b30;
266 break;
267 case 0x4A: // J
268 addr=0x34b70;
269 break;
270 case 0x50: // E
271 addr=0x329f0;
272 break;
273 default:
274 // Unknown country code
275 addr=0;
276 break;
277 }
278 u_int rom_addr=(u_int)rom;
279 #ifdef ROM_COPY
280 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
281 // in the lower 4G of memory to use this hack. Copy it if necessary.
282 if((void *)rom>(void *)0xffffffff) {
283 munmap(ROM_COPY, 67108864);
284 if(mmap(ROM_COPY, 12582912,
285 PROT_READ | PROT_WRITE,
286 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
287 -1, 0) <= 0) {printf("mmap() failed\n");}
288 memcpy(ROM_COPY,rom,12582912);
289 rom_addr=(u_int)ROM_COPY;
290 }
291 #endif
292 if(addr) {
293 for(n=0x7F000;n<0x80000;n++) {
294 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
295 }
296 }
297 }
94d23bb9 298#endif
57871462 299}
300
94d23bb9 301static u_int get_page(u_int vaddr)
57871462 302{
303 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 304#ifndef DISABLE_TLB
57871462 305 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 306#endif
57871462 307 if(page>2048) page=2048+(page&2047);
94d23bb9 308 return page;
309}
310
311static u_int get_vpage(u_int vaddr)
312{
313 u_int vpage=(vaddr^0x80000000)>>12;
314#ifndef DISABLE_TLB
57871462 315 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 316#endif
57871462 317 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 318 return vpage;
319}
320
321// Get address from virtual address
322// This is called from the recompiled JR/JALR instructions
323void *get_addr(u_int vaddr)
324{
325 u_int page=get_page(vaddr);
326 u_int vpage=get_vpage(vaddr);
57871462 327 struct ll_entry *head;
328 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
329 head=jump_in[page];
330 while(head!=NULL) {
331 if(head->vaddr==vaddr&&head->reg32==0) {
332 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
333 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
334 ht_bin[3]=ht_bin[1];
335 ht_bin[2]=ht_bin[0];
336 ht_bin[1]=(int)head->addr;
337 ht_bin[0]=vaddr;
338 return head->addr;
339 }
340 head=head->next;
341 }
342 head=jump_dirty[vpage];
343 while(head!=NULL) {
344 if(head->vaddr==vaddr&&head->reg32==0) {
345 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
346 // Don't restore blocks which are about to expire from the cache
347 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
348 if(verify_dirty(head->addr)) {
349 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
350 invalid_code[vaddr>>12]=0;
351 memory_map[vaddr>>12]|=0x40000000;
352 if(vpage<2048) {
94d23bb9 353#ifndef DISABLE_TLB
57871462 354 if(tlb_LUT_r[vaddr>>12]) {
355 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
356 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
357 }
94d23bb9 358#endif
57871462 359 restore_candidate[vpage>>3]|=1<<(vpage&7);
360 }
361 else restore_candidate[page>>3]|=1<<(page&7);
362 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 if(ht_bin[0]==vaddr) {
364 ht_bin[1]=(int)head->addr; // Replace existing entry
365 }
366 else
367 {
368 ht_bin[3]=ht_bin[1];
369 ht_bin[2]=ht_bin[0];
370 ht_bin[1]=(int)head->addr;
371 ht_bin[0]=vaddr;
372 }
373 return head->addr;
374 }
375 }
376 head=head->next;
377 }
378 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
379 int r=new_recompile_block(vaddr);
380 if(r==0) return get_addr(vaddr);
381 // Execute in unmapped page, generate pagefault execption
382 Status|=2;
383 Cause=(vaddr<<31)|0x8;
384 EPC=(vaddr&1)?vaddr-5:vaddr;
385 BadVAddr=(vaddr&~1);
386 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
387 EntryHi=BadVAddr&0xFFFFE000;
388 return get_addr_ht(0x80000000);
389}
390// Look up address in hash table first
391void *get_addr_ht(u_int vaddr)
392{
393 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
394 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
396 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
397 return get_addr(vaddr);
398}
399
400void *get_addr_32(u_int vaddr,u_int flags)
401{
402 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 406 u_int page=get_page(vaddr);
407 u_int vpage=get_vpage(vaddr);
57871462 408 struct ll_entry *head;
409 head=jump_in[page];
410 while(head!=NULL) {
411 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
412 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
413 if(head->reg32==0) {
414 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
415 if(ht_bin[0]==-1) {
416 ht_bin[1]=(int)head->addr;
417 ht_bin[0]=vaddr;
418 }else if(ht_bin[2]==-1) {
419 ht_bin[3]=(int)head->addr;
420 ht_bin[2]=vaddr;
421 }
422 //ht_bin[3]=ht_bin[1];
423 //ht_bin[2]=ht_bin[0];
424 //ht_bin[1]=(int)head->addr;
425 //ht_bin[0]=vaddr;
426 }
427 return head->addr;
428 }
429 head=head->next;
430 }
431 head=jump_dirty[vpage];
432 while(head!=NULL) {
433 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
434 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435 // Don't restore blocks which are about to expire from the cache
436 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
437 if(verify_dirty(head->addr)) {
438 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
439 invalid_code[vaddr>>12]=0;
440 memory_map[vaddr>>12]|=0x40000000;
441 if(vpage<2048) {
94d23bb9 442#ifndef DISABLE_TLB
57871462 443 if(tlb_LUT_r[vaddr>>12]) {
444 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
445 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
446 }
94d23bb9 447#endif
57871462 448 restore_candidate[vpage>>3]|=1<<(vpage&7);
449 }
450 else restore_candidate[page>>3]|=1<<(page&7);
451 if(head->reg32==0) {
452 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
453 if(ht_bin[0]==-1) {
454 ht_bin[1]=(int)head->addr;
455 ht_bin[0]=vaddr;
456 }else if(ht_bin[2]==-1) {
457 ht_bin[3]=(int)head->addr;
458 ht_bin[2]=vaddr;
459 }
460 //ht_bin[3]=ht_bin[1];
461 //ht_bin[2]=ht_bin[0];
462 //ht_bin[1]=(int)head->addr;
463 //ht_bin[0]=vaddr;
464 }
465 return head->addr;
466 }
467 }
468 head=head->next;
469 }
470 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
471 int r=new_recompile_block(vaddr);
472 if(r==0) return get_addr(vaddr);
473 // Execute in unmapped page, generate pagefault execption
474 Status|=2;
475 Cause=(vaddr<<31)|0x8;
476 EPC=(vaddr&1)?vaddr-5:vaddr;
477 BadVAddr=(vaddr&~1);
478 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
479 EntryHi=BadVAddr&0xFFFFE000;
480 return get_addr_ht(0x80000000);
481}
482
483void clear_all_regs(signed char regmap[])
484{
485 int hr;
486 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
487}
488
489signed char get_reg(signed char regmap[],int r)
490{
491 int hr;
492 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
493 return -1;
494}
495
496// Find a register that is available for two consecutive cycles
497signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
498{
499 int hr;
500 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
501 return -1;
502}
503
504int count_free_regs(signed char regmap[])
505{
506 int count=0;
507 int hr;
508 for(hr=0;hr<HOST_REGS;hr++)
509 {
510 if(hr!=EXCLUDE_REG) {
511 if(regmap[hr]<0) count++;
512 }
513 }
514 return count;
515}
516
517void dirty_reg(struct regstat *cur,signed char reg)
518{
519 int hr;
520 if(!reg) return;
521 for (hr=0;hr<HOST_REGS;hr++) {
522 if((cur->regmap[hr]&63)==reg) {
523 cur->dirty|=1<<hr;
524 }
525 }
526}
527
528// If we dirty the lower half of a 64 bit register which is now being
529// sign-extended, we need to dump the upper half.
530// Note: Do this only after completion of the instruction, because
531// some instructions may need to read the full 64-bit value even if
532// overwriting it (eg SLTI, DSRA32).
533static void flush_dirty_uppers(struct regstat *cur)
534{
535 int hr,reg;
536 for (hr=0;hr<HOST_REGS;hr++) {
537 if((cur->dirty>>hr)&1) {
538 reg=cur->regmap[hr];
539 if(reg>=64)
540 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
541 }
542 }
543}
544
545void set_const(struct regstat *cur,signed char reg,uint64_t value)
546{
547 int hr;
548 if(!reg) return;
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if(cur->regmap[hr]==reg) {
551 cur->isconst|=1<<hr;
552 cur->constmap[hr]=value;
553 }
554 else if((cur->regmap[hr]^64)==reg) {
555 cur->isconst|=1<<hr;
556 cur->constmap[hr]=value>>32;
557 }
558 }
559}
560
561void clear_const(struct regstat *cur,signed char reg)
562{
563 int hr;
564 if(!reg) return;
565 for (hr=0;hr<HOST_REGS;hr++) {
566 if((cur->regmap[hr]&63)==reg) {
567 cur->isconst&=~(1<<hr);
568 }
569 }
570}
571
572int is_const(struct regstat *cur,signed char reg)
573{
574 int hr;
575 if(!reg) return 1;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if((cur->regmap[hr]&63)==reg) {
578 return (cur->isconst>>hr)&1;
579 }
580 }
581 return 0;
582}
583uint64_t get_const(struct regstat *cur,signed char reg)
584{
585 int hr;
586 if(!reg) return 0;
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if(cur->regmap[hr]==reg) {
589 return cur->constmap[hr];
590 }
591 }
592 printf("Unknown constant in r%d\n",reg);
593 exit(1);
594}
595
596// Least soon needed registers
597// Look at the next ten instructions and see which registers
598// will be used. Try not to reallocate these.
599void lsn(u_char hsn[], int i, int *preferred_reg)
600{
601 int j;
602 int b=-1;
603 for(j=0;j<9;j++)
604 {
605 if(i+j>=slen) {
606 j=slen-i-1;
607 break;
608 }
609 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
610 {
611 // Don't go past an unconditonal jump
612 j++;
613 break;
614 }
615 }
616 for(;j>=0;j--)
617 {
618 if(rs1[i+j]) hsn[rs1[i+j]]=j;
619 if(rs2[i+j]) hsn[rs2[i+j]]=j;
620 if(rt1[i+j]) hsn[rt1[i+j]]=j;
621 if(rt2[i+j]) hsn[rt2[i+j]]=j;
622 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
623 // Stores can allocate zero
624 hsn[rs1[i+j]]=j;
625 hsn[rs2[i+j]]=j;
626 }
627 // On some architectures stores need invc_ptr
628 #if defined(HOST_IMM8)
629 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
630 hsn[INVCP]=j;
631 }
632 #endif
633 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
634 {
635 hsn[CCREG]=j;
636 b=j;
637 }
638 }
639 if(b>=0)
640 {
641 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
642 {
643 // Follow first branch
644 int t=(ba[i+b]-start)>>2;
645 j=7-b;if(t+j>=slen) j=slen-t-1;
646 for(;j>=0;j--)
647 {
648 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
649 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
650 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
651 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
652 }
653 }
654 // TODO: preferred register based on backward branch
655 }
656 // Delay slot should preferably not overwrite branch conditions or cycle count
657 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
658 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
659 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
660 hsn[CCREG]=1;
661 // ...or hash tables
662 hsn[RHASH]=1;
663 hsn[RHTBL]=1;
664 }
665 // Coprocessor load/store needs FTEMP, even if not declared
666 if(itype[i]==C1LS) {
667 hsn[FTEMP]=0;
668 }
669 // Load L/R also uses FTEMP as a temporary register
670 if(itype[i]==LOADLR) {
671 hsn[FTEMP]=0;
672 }
673 // Also 64-bit SDL/SDR
674 if(opcode[i]==0x2c||opcode[i]==0x2d) {
675 hsn[FTEMP]=0;
676 }
677 // Don't remove the TLB registers either
678 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
679 hsn[TLREG]=0;
680 }
681 // Don't remove the miniht registers
682 if(itype[i]==UJUMP||itype[i]==RJUMP)
683 {
684 hsn[RHASH]=0;
685 hsn[RHTBL]=0;
686 }
687}
688
689// We only want to allocate registers if we're going to use them again soon
690int needed_again(int r, int i)
691{
692 int j;
693 int b=-1;
694 int rn=10;
695 int hr;
696 u_char hsn[MAXREG+1];
697 int preferred_reg;
698
699 memset(hsn,10,sizeof(hsn));
700 lsn(hsn,i,&preferred_reg);
701
702 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
703 {
704 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
705 return 0; // Don't need any registers if exiting the block
706 }
707 for(j=0;j<9;j++)
708 {
709 if(i+j>=slen) {
710 j=slen-i-1;
711 break;
712 }
713 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
714 {
715 // Don't go past an unconditonal jump
716 j++;
717 break;
718 }
719 if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
720 {
721 break;
722 }
723 }
724 for(;j>=1;j--)
725 {
726 if(rs1[i+j]==r) rn=j;
727 if(rs2[i+j]==r) rn=j;
728 if((unneeded_reg[i+j]>>r)&1) rn=10;
729 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
730 {
731 b=j;
732 }
733 }
734 /*
735 if(b>=0)
736 {
737 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
738 {
739 // Follow first branch
740 int o=rn;
741 int t=(ba[i+b]-start)>>2;
742 j=7-b;if(t+j>=slen) j=slen-t-1;
743 for(;j>=0;j--)
744 {
745 if(!((unneeded_reg[t+j]>>r)&1)) {
746 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
747 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
748 }
749 else rn=o;
750 }
751 }
752 }*/
753 for(hr=0;hr<HOST_REGS;hr++) {
754 if(hr!=EXCLUDE_REG) {
755 if(rn<hsn[hr]) return 1;
756 }
757 }
758 return 0;
759}
760
761// Try to match register allocations at the end of a loop with those
762// at the beginning
763int loop_reg(int i, int r, int hr)
764{
765 int j,k;
766 for(j=0;j<9;j++)
767 {
768 if(i+j>=slen) {
769 j=slen-i-1;
770 break;
771 }
772 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
773 {
774 // Don't go past an unconditonal jump
775 j++;
776 break;
777 }
778 }
779 k=0;
780 if(i>0){
781 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
782 k--;
783 }
784 for(;k<j;k++)
785 {
786 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
787 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
788 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
789 {
790 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
791 {
792 int t=(ba[i+k]-start)>>2;
793 int reg=get_reg(regs[t].regmap_entry,r);
794 if(reg>=0) return reg;
795 //reg=get_reg(regs[t+1].regmap_entry,r);
796 //if(reg>=0) return reg;
797 }
798 }
799 }
800 return hr;
801}
802
803
804// Allocate every register, preserving source/target regs
805void alloc_all(struct regstat *cur,int i)
806{
807 int hr;
808
809 for(hr=0;hr<HOST_REGS;hr++) {
810 if(hr!=EXCLUDE_REG) {
811 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
812 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
813 {
814 cur->regmap[hr]=-1;
815 cur->dirty&=~(1<<hr);
816 }
817 // Don't need zeros
818 if((cur->regmap[hr]&63)==0)
819 {
820 cur->regmap[hr]=-1;
821 cur->dirty&=~(1<<hr);
822 }
823 }
824 }
825}
826
827
828void div64(int64_t dividend,int64_t divisor)
829{
830 lo=dividend/divisor;
831 hi=dividend%divisor;
832 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
833 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
834}
835void divu64(uint64_t dividend,uint64_t divisor)
836{
837 lo=dividend/divisor;
838 hi=dividend%divisor;
839 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
840 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
841}
842
843void mult64(uint64_t m1,uint64_t m2)
844{
845 unsigned long long int op1, op2, op3, op4;
846 unsigned long long int result1, result2, result3, result4;
847 unsigned long long int temp1, temp2, temp3, temp4;
848 int sign = 0;
849
850 if (m1 < 0)
851 {
852 op2 = -m1;
853 sign = 1 - sign;
854 }
855 else op2 = m1;
856 if (m2 < 0)
857 {
858 op4 = -m2;
859 sign = 1 - sign;
860 }
861 else op4 = m2;
862
863 op1 = op2 & 0xFFFFFFFF;
864 op2 = (op2 >> 32) & 0xFFFFFFFF;
865 op3 = op4 & 0xFFFFFFFF;
866 op4 = (op4 >> 32) & 0xFFFFFFFF;
867
868 temp1 = op1 * op3;
869 temp2 = (temp1 >> 32) + op1 * op4;
870 temp3 = op2 * op3;
871 temp4 = (temp3 >> 32) + op2 * op4;
872
873 result1 = temp1 & 0xFFFFFFFF;
874 result2 = temp2 + (temp3 & 0xFFFFFFFF);
875 result3 = (result2 >> 32) + temp4;
876 result4 = (result3 >> 32);
877
878 lo = result1 | (result2 << 32);
879 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
880 if (sign)
881 {
882 hi = ~hi;
883 if (!lo) hi++;
884 else lo = ~lo + 1;
885 }
886}
887
888void multu64(uint64_t m1,uint64_t m2)
889{
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
893
894 op1 = m1 & 0xFFFFFFFF;
895 op2 = (m1 >> 32) & 0xFFFFFFFF;
896 op3 = m2 & 0xFFFFFFFF;
897 op4 = (m2 >> 32) & 0xFFFFFFFF;
898
899 temp1 = op1 * op3;
900 temp2 = (temp1 >> 32) + op1 * op4;
901 temp3 = op2 * op3;
902 temp4 = (temp3 >> 32) + op2 * op4;
903
904 result1 = temp1 & 0xFFFFFFFF;
905 result2 = temp2 + (temp3 & 0xFFFFFFFF);
906 result3 = (result2 >> 32) + temp4;
907 result4 = (result3 >> 32);
908
909 lo = result1 | (result2 << 32);
910 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
911
912 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
913 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
914}
915
916uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
917{
918 if(bits) {
919 original<<=64-bits;
920 original>>=64-bits;
921 loaded<<=bits;
922 original|=loaded;
923 }
924 else original=loaded;
925 return original;
926}
927uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
928{
929 if(bits^56) {
930 original>>=64-(bits^56);
931 original<<=64-(bits^56);
932 loaded>>=bits^56;
933 original|=loaded;
934 }
935 else original=loaded;
936 return original;
937}
938
939#ifdef __i386__
940#include "assem_x86.c"
941#endif
942#ifdef __x86_64__
943#include "assem_x64.c"
944#endif
945#ifdef __arm__
946#include "assem_arm.c"
947#endif
948
949// Add virtual address mapping to linked list
950void ll_add(struct ll_entry **head,int vaddr,void *addr)
951{
952 struct ll_entry *new_entry;
953 new_entry=malloc(sizeof(struct ll_entry));
954 assert(new_entry!=NULL);
955 new_entry->vaddr=vaddr;
956 new_entry->reg32=0;
957 new_entry->addr=addr;
958 new_entry->next=*head;
959 *head=new_entry;
960}
961
962// Add virtual address mapping for 32-bit compiled block
963void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
964{
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
969 new_entry->reg32=reg32;
970 new_entry->addr=addr;
971 new_entry->next=*head;
972 *head=new_entry;
973}
974
975// Check if an address is already compiled
976// but don't return addresses which are about to expire from the cache
977void *check_addr(u_int vaddr)
978{
979 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
980 if(ht_bin[0]==vaddr) {
981 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
982 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
983 }
984 if(ht_bin[2]==vaddr) {
985 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
986 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
987 }
94d23bb9 988 u_int page=get_page(vaddr);
57871462 989 struct ll_entry *head;
990 head=jump_in[page];
991 while(head!=NULL) {
992 if(head->vaddr==vaddr&&head->reg32==0) {
993 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
994 // Update existing entry with current address
995 if(ht_bin[0]==vaddr) {
996 ht_bin[1]=(int)head->addr;
997 return head->addr;
998 }
999 if(ht_bin[2]==vaddr) {
1000 ht_bin[3]=(int)head->addr;
1001 return head->addr;
1002 }
1003 // Insert into hash table with low priority.
1004 // Don't evict existing entries, as they are probably
1005 // addresses that are being accessed frequently.
1006 if(ht_bin[0]==-1) {
1007 ht_bin[1]=(int)head->addr;
1008 ht_bin[0]=vaddr;
1009 }else if(ht_bin[2]==-1) {
1010 ht_bin[3]=(int)head->addr;
1011 ht_bin[2]=vaddr;
1012 }
1013 return head->addr;
1014 }
1015 }
1016 head=head->next;
1017 }
1018 return 0;
1019}
1020
1021void remove_hash(int vaddr)
1022{
1023 //printf("remove hash: %x\n",vaddr);
1024 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025 if(ht_bin[2]==vaddr) {
1026 ht_bin[2]=ht_bin[3]=-1;
1027 }
1028 if(ht_bin[0]==vaddr) {
1029 ht_bin[0]=ht_bin[2];
1030 ht_bin[1]=ht_bin[3];
1031 ht_bin[2]=ht_bin[3]=-1;
1032 }
1033}
1034
1035void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1036{
1037 struct ll_entry *next;
1038 while(*head) {
1039 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1040 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1041 {
1042 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043 remove_hash((*head)->vaddr);
1044 next=(*head)->next;
1045 free(*head);
1046 *head=next;
1047 }
1048 else
1049 {
1050 head=&((*head)->next);
1051 }
1052 }
1053}
1054
1055// Remove all entries from linked list
1056void ll_clear(struct ll_entry **head)
1057{
1058 struct ll_entry *cur;
1059 struct ll_entry *next;
1060 if(cur=*head) {
1061 *head=0;
1062 while(cur) {
1063 next=cur->next;
1064 free(cur);
1065 cur=next;
1066 }
1067 }
1068}
1069
1070// Dereference the pointers and remove if it matches
1071void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1072{
1073 while(head) {
1074 int ptr=get_pointer(head->addr);
1075 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076 if(((ptr>>shift)==(addr>>shift)) ||
1077 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1078 {
1079 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080 kill_pointer(head->addr);
1081 }
1082 head=head->next;
1083 }
1084}
1085
1086// This is called when we write to a compiled block (see do_invstub)
1087int invalidate_page(u_int page)
1088{
1089 int modified=0;
1090 struct ll_entry *head;
1091 struct ll_entry *next;
1092 head=jump_in[page];
1093 jump_in[page]=0;
1094 while(head!=NULL) {
1095 inv_debug("INVALIDATE: %x\n",head->vaddr);
1096 remove_hash(head->vaddr);
1097 next=head->next;
1098 free(head);
1099 head=next;
1100 }
1101 head=jump_out[page];
1102 jump_out[page]=0;
1103 while(head!=NULL) {
1104 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105 kill_pointer(head->addr);
1106 modified=1;
1107 next=head->next;
1108 free(head);
1109 head=next;
1110 }
1111 return modified;
1112}
1113void invalidate_block(u_int block)
1114{
1115 int modified;
94d23bb9 1116 u_int page=get_page(block<<12);
1117 u_int vpage=get_vpage(block<<12);
57871462 1118 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1120 u_int first,last;
1121 first=last=page;
1122 struct ll_entry *head;
1123 head=jump_dirty[vpage];
1124 //printf("page=%d vpage=%d\n",page,vpage);
1125 while(head!=NULL) {
1126 u_int start,end;
1127 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128 get_bounds((int)head->addr,&start,&end);
1129 //printf("start: %x end: %x\n",start,end);
1130 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1134 }
1135 }
90ae6d4e 1136#ifndef DISABLE_TLB
57871462 1137 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1138 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1139 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1140 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1141 }
1142 }
90ae6d4e 1143#endif
57871462 1144 }
1145 head=head->next;
1146 }
1147 //printf("first=%d last=%d\n",first,last);
1148 modified=invalidate_page(page);
1149 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1150 assert(last<page+5);
1151 // Invalidate the adjacent pages if a block crosses a 4K boundary
1152 while(first<page) {
1153 invalidate_page(first);
1154 first++;
1155 }
1156 for(first=page+1;first<last;first++) {
1157 invalidate_page(first);
1158 }
1159
1160 // Don't trap writes
1161 invalid_code[block]=1;
94d23bb9 1162#ifndef DISABLE_TLB
57871462 1163 // If there is a valid TLB entry for this page, remove write protect
1164 if(tlb_LUT_w[block]) {
1165 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1166 // CHECK: Is this right?
1167 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1168 u_int real_block=tlb_LUT_w[block]>>12;
1169 invalid_code[real_block]=1;
1170 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1171 }
1172 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1173#endif
57871462 1174 #ifdef __arm__
1175 if(modified)
1176 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1177 #endif
1178 #ifdef USE_MINI_HT
1179 memset(mini_ht,-1,sizeof(mini_ht));
1180 #endif
1181}
1182void invalidate_addr(u_int addr)
1183{
1184 invalidate_block(addr>>12);
1185}
1186void invalidate_all_pages()
1187{
1188 u_int page,n;
1189 for(page=0;page<4096;page++)
1190 invalidate_page(page);
1191 for(page=0;page<1048576;page++)
1192 if(!invalid_code[page]) {
1193 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1194 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1195 }
1196 #ifdef __arm__
1197 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1198 #endif
1199 #ifdef USE_MINI_HT
1200 memset(mini_ht,-1,sizeof(mini_ht));
1201 #endif
94d23bb9 1202 #ifndef DISABLE_TLB
57871462 1203 // TLB
1204 for(page=0;page<0x100000;page++) {
1205 if(tlb_LUT_r[page]) {
1206 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1207 if(!tlb_LUT_w[page]||!invalid_code[page])
1208 memory_map[page]|=0x40000000; // Write protect
1209 }
1210 else memory_map[page]=-1;
1211 if(page==0x80000) page=0xC0000;
1212 }
1213 tlb_hacks();
94d23bb9 1214 #endif
57871462 1215}
1216
1217// Add an entry to jump_out after making a link
1218void add_link(u_int vaddr,void *src)
1219{
94d23bb9 1220 u_int page=get_page(vaddr);
57871462 1221 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1222 ll_add(jump_out+page,vaddr,src);
1223 //int ptr=get_pointer(src);
1224 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1225}
1226
1227// If a code block was found to be unmodified (bit was set in
1228// restore_candidate) and it remains unmodified (bit is clear
1229// in invalid_code) then move the entries for that 4K page from
1230// the dirty list to the clean list.
1231void clean_blocks(u_int page)
1232{
1233 struct ll_entry *head;
1234 inv_debug("INV: clean_blocks page=%d\n",page);
1235 head=jump_dirty[page];
1236 while(head!=NULL) {
1237 if(!invalid_code[head->vaddr>>12]) {
1238 // Don't restore blocks which are about to expire from the cache
1239 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1240 u_int start,end;
1241 if(verify_dirty((int)head->addr)) {
1242 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1243 u_int i;
1244 u_int inv=0;
1245 get_bounds((int)head->addr,&start,&end);
1246 if(start-(u_int)rdram<0x800000) {
1247 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1248 inv|=invalid_code[i];
1249 }
1250 }
1251 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1252 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1253 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1254 if(addr<start||addr>=end) inv=1;
1255 }
1256 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1257 inv=1;
1258 }
1259 if(!inv) {
1260 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1261 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262 u_int ppage=page;
94d23bb9 1263#ifndef DISABLE_TLB
57871462 1264 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1265#endif
57871462 1266 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1267 //printf("page=%x, addr=%x\n",page,head->vaddr);
1268 //assert(head->vaddr>>12==(page|0x80000));
1269 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1270 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1271 if(!head->reg32) {
1272 if(ht_bin[0]==head->vaddr) {
1273 ht_bin[1]=(int)clean_addr; // Replace existing entry
1274 }
1275 if(ht_bin[2]==head->vaddr) {
1276 ht_bin[3]=(int)clean_addr; // Replace existing entry
1277 }
1278 }
1279 }
1280 }
1281 }
1282 }
1283 }
1284 head=head->next;
1285 }
1286}
1287
1288
1289void mov_alloc(struct regstat *current,int i)
1290{
1291 // Note: Don't need to actually alloc the source registers
1292 if((~current->is32>>rs1[i])&1) {
1293 //alloc_reg64(current,i,rs1[i]);
1294 alloc_reg64(current,i,rt1[i]);
1295 current->is32&=~(1LL<<rt1[i]);
1296 } else {
1297 //alloc_reg(current,i,rs1[i]);
1298 alloc_reg(current,i,rt1[i]);
1299 current->is32|=(1LL<<rt1[i]);
1300 }
1301 clear_const(current,rs1[i]);
1302 clear_const(current,rt1[i]);
1303 dirty_reg(current,rt1[i]);
1304}
1305
1306void shiftimm_alloc(struct regstat *current,int i)
1307{
1308 clear_const(current,rs1[i]);
1309 clear_const(current,rt1[i]);
1310 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1311 {
1312 if(rt1[i]) {
1313 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1314 else lt1[i]=rs1[i];
1315 alloc_reg(current,i,rt1[i]);
1316 current->is32|=1LL<<rt1[i];
1317 dirty_reg(current,rt1[i]);
1318 }
1319 }
1320 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1321 {
1322 if(rt1[i]) {
1323 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1324 alloc_reg64(current,i,rt1[i]);
1325 current->is32&=~(1LL<<rt1[i]);
1326 dirty_reg(current,rt1[i]);
1327 }
1328 }
1329 if(opcode2[i]==0x3c) // DSLL32
1330 {
1331 if(rt1[i]) {
1332 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1333 alloc_reg64(current,i,rt1[i]);
1334 current->is32&=~(1LL<<rt1[i]);
1335 dirty_reg(current,rt1[i]);
1336 }
1337 }
1338 if(opcode2[i]==0x3e) // DSRL32
1339 {
1340 if(rt1[i]) {
1341 alloc_reg64(current,i,rs1[i]);
1342 if(imm[i]==32) {
1343 alloc_reg64(current,i,rt1[i]);
1344 current->is32&=~(1LL<<rt1[i]);
1345 } else {
1346 alloc_reg(current,i,rt1[i]);
1347 current->is32|=1LL<<rt1[i];
1348 }
1349 dirty_reg(current,rt1[i]);
1350 }
1351 }
1352 if(opcode2[i]==0x3f) // DSRA32
1353 {
1354 if(rt1[i]) {
1355 alloc_reg64(current,i,rs1[i]);
1356 alloc_reg(current,i,rt1[i]);
1357 current->is32|=1LL<<rt1[i];
1358 dirty_reg(current,rt1[i]);
1359 }
1360 }
1361}
1362
1363void shift_alloc(struct regstat *current,int i)
1364{
1365 if(rt1[i]) {
1366 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1367 {
1368 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1369 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1370 alloc_reg(current,i,rt1[i]);
1371 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1372 current->is32|=1LL<<rt1[i];
1373 } else { // DSLLV/DSRLV/DSRAV
1374 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg64(current,i,rt1[i]);
1377 current->is32&=~(1LL<<rt1[i]);
1378 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1379 alloc_reg_temp(current,i,-1);
1380 }
1381 clear_const(current,rs1[i]);
1382 clear_const(current,rs2[i]);
1383 clear_const(current,rt1[i]);
1384 dirty_reg(current,rt1[i]);
1385 }
1386}
1387
1388void alu_alloc(struct regstat *current,int i)
1389{
1390 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1391 if(rt1[i]) {
1392 if(rs1[i]&&rs2[i]) {
1393 alloc_reg(current,i,rs1[i]);
1394 alloc_reg(current,i,rs2[i]);
1395 }
1396 else {
1397 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1398 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1399 }
1400 alloc_reg(current,i,rt1[i]);
1401 }
1402 current->is32|=1LL<<rt1[i];
1403 }
1404 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1405 if(rt1[i]) {
1406 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1407 {
1408 alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rs2[i]);
1410 alloc_reg(current,i,rt1[i]);
1411 } else {
1412 alloc_reg(current,i,rs1[i]);
1413 alloc_reg(current,i,rs2[i]);
1414 alloc_reg(current,i,rt1[i]);
1415 }
1416 }
1417 current->is32|=1LL<<rt1[i];
1418 }
1419 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1420 if(rt1[i]) {
1421 if(rs1[i]&&rs2[i]) {
1422 alloc_reg(current,i,rs1[i]);
1423 alloc_reg(current,i,rs2[i]);
1424 }
1425 else
1426 {
1427 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1428 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1429 }
1430 alloc_reg(current,i,rt1[i]);
1431 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1432 {
1433 if(!((current->uu>>rt1[i])&1)) {
1434 alloc_reg64(current,i,rt1[i]);
1435 }
1436 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1437 if(rs1[i]&&rs2[i]) {
1438 alloc_reg64(current,i,rs1[i]);
1439 alloc_reg64(current,i,rs2[i]);
1440 }
1441 else
1442 {
1443 // Is is really worth it to keep 64-bit values in registers?
1444 #ifdef NATIVE_64BIT
1445 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1446 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1447 #endif
1448 }
1449 }
1450 current->is32&=~(1LL<<rt1[i]);
1451 } else {
1452 current->is32|=1LL<<rt1[i];
1453 }
1454 }
1455 }
1456 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1457 if(rt1[i]) {
1458 if(rs1[i]&&rs2[i]) {
1459 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1460 alloc_reg64(current,i,rs1[i]);
1461 alloc_reg64(current,i,rs2[i]);
1462 alloc_reg64(current,i,rt1[i]);
1463 } else {
1464 alloc_reg(current,i,rs1[i]);
1465 alloc_reg(current,i,rs2[i]);
1466 alloc_reg(current,i,rt1[i]);
1467 }
1468 }
1469 else {
1470 alloc_reg(current,i,rt1[i]);
1471 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1472 // DADD used as move, or zeroing
1473 // If we have a 64-bit source, then make the target 64 bits too
1474 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1475 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1476 alloc_reg64(current,i,rt1[i]);
1477 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1478 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1479 alloc_reg64(current,i,rt1[i]);
1480 }
1481 if(opcode2[i]>=0x2e&&rs2[i]) {
1482 // DSUB used as negation - 64-bit result
1483 // If we have a 32-bit register, extend it to 64 bits
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1486 }
1487 }
1488 }
1489 if(rs1[i]&&rs2[i]) {
1490 current->is32&=~(1LL<<rt1[i]);
1491 } else if(rs1[i]) {
1492 current->is32&=~(1LL<<rt1[i]);
1493 if((current->is32>>rs1[i])&1)
1494 current->is32|=1LL<<rt1[i];
1495 } else if(rs2[i]) {
1496 current->is32&=~(1LL<<rt1[i]);
1497 if((current->is32>>rs2[i])&1)
1498 current->is32|=1LL<<rt1[i];
1499 } else {
1500 current->is32|=1LL<<rt1[i];
1501 }
1502 }
1503 }
1504 clear_const(current,rs1[i]);
1505 clear_const(current,rs2[i]);
1506 clear_const(current,rt1[i]);
1507 dirty_reg(current,rt1[i]);
1508}
1509
1510void imm16_alloc(struct regstat *current,int i)
1511{
1512 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513 else lt1[i]=rs1[i];
1514 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1515 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1516 current->is32&=~(1LL<<rt1[i]);
1517 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1518 // TODO: Could preserve the 32-bit flag if the immediate is zero
1519 alloc_reg64(current,i,rt1[i]);
1520 alloc_reg64(current,i,rs1[i]);
1521 }
1522 clear_const(current,rs1[i]);
1523 clear_const(current,rt1[i]);
1524 }
1525 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1526 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1527 current->is32|=1LL<<rt1[i];
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1530 }
1531 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1532 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1533 if(rs1[i]!=rt1[i]) {
1534 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1535 alloc_reg64(current,i,rt1[i]);
1536 current->is32&=~(1LL<<rt1[i]);
1537 }
1538 }
1539 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1540 if(is_const(current,rs1[i])) {
1541 int v=get_const(current,rs1[i]);
1542 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1543 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1544 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1545 }
1546 else clear_const(current,rt1[i]);
1547 }
1548 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1549 if(is_const(current,rs1[i])) {
1550 int v=get_const(current,rs1[i]);
1551 set_const(current,rt1[i],v+imm[i]);
1552 }
1553 else clear_const(current,rt1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 }
1556 else {
1557 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1558 current->is32|=1LL<<rt1[i];
1559 }
1560 dirty_reg(current,rt1[i]);
1561}
1562
1563void load_alloc(struct regstat *current,int i)
1564{
1565 clear_const(current,rt1[i]);
1566 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1567 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1568 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1569 if(rt1[i]) {
1570 alloc_reg(current,i,rt1[i]);
1571 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1572 {
1573 current->is32&=~(1LL<<rt1[i]);
1574 alloc_reg64(current,i,rt1[i]);
1575 }
1576 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1577 {
1578 current->is32&=~(1LL<<rt1[i]);
1579 alloc_reg64(current,i,rt1[i]);
1580 alloc_all(current,i);
1581 alloc_reg64(current,i,FTEMP);
1582 }
1583 else current->is32|=1LL<<rt1[i];
1584 dirty_reg(current,rt1[i]);
1585 // If using TLB, need a register for pointer to the mapping table
1586 if(using_tlb) alloc_reg(current,i,TLREG);
1587 // LWL/LWR need a temporary register for the old value
1588 if(opcode[i]==0x22||opcode[i]==0x26)
1589 {
1590 alloc_reg(current,i,FTEMP);
1591 alloc_reg_temp(current,i,-1);
1592 }
1593 }
1594 else
1595 {
1596 // Load to r0 (dummy load)
1597 // but we still need a register to calculate the address
1598 alloc_reg_temp(current,i,-1);
1599 }
1600}
1601
1602void store_alloc(struct regstat *current,int i)
1603{
1604 clear_const(current,rs2[i]);
1605 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1606 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1607 alloc_reg(current,i,rs2[i]);
1608 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1609 alloc_reg64(current,i,rs2[i]);
1610 if(rs2[i]) alloc_reg(current,i,FTEMP);
1611 }
1612 // If using TLB, need a register for pointer to the mapping table
1613 if(using_tlb) alloc_reg(current,i,TLREG);
1614 #if defined(HOST_IMM8)
1615 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1616 else alloc_reg(current,i,INVCP);
1617 #endif
1618 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1619 alloc_reg(current,i,FTEMP);
1620 }
1621 // We need a temporary register for address generation
1622 alloc_reg_temp(current,i,-1);
1623}
1624
1625void c1ls_alloc(struct regstat *current,int i)
1626{
1627 //clear_const(current,rs1[i]); // FIXME
1628 clear_const(current,rt1[i]);
1629 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1630 alloc_reg(current,i,CSREG); // Status
1631 alloc_reg(current,i,FTEMP);
1632 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1633 alloc_reg64(current,i,FTEMP);
1634 }
1635 // If using TLB, need a register for pointer to the mapping table
1636 if(using_tlb) alloc_reg(current,i,TLREG);
1637 #if defined(HOST_IMM8)
1638 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1639 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1640 alloc_reg(current,i,INVCP);
1641 #endif
1642 // We need a temporary register for address generation
1643 alloc_reg_temp(current,i,-1);
1644}
1645
1646#ifndef multdiv_alloc
1647void multdiv_alloc(struct regstat *current,int i)
1648{
1649 // case 0x18: MULT
1650 // case 0x19: MULTU
1651 // case 0x1A: DIV
1652 // case 0x1B: DIVU
1653 // case 0x1C: DMULT
1654 // case 0x1D: DMULTU
1655 // case 0x1E: DDIV
1656 // case 0x1F: DDIVU
1657 clear_const(current,rs1[i]);
1658 clear_const(current,rs2[i]);
1659 if(rs1[i]&&rs2[i])
1660 {
1661 if((opcode2[i]&4)==0) // 32-bit
1662 {
1663 current->u&=~(1LL<<HIREG);
1664 current->u&=~(1LL<<LOREG);
1665 alloc_reg(current,i,HIREG);
1666 alloc_reg(current,i,LOREG);
1667 alloc_reg(current,i,rs1[i]);
1668 alloc_reg(current,i,rs2[i]);
1669 current->is32|=1LL<<HIREG;
1670 current->is32|=1LL<<LOREG;
1671 dirty_reg(current,HIREG);
1672 dirty_reg(current,LOREG);
1673 }
1674 else // 64-bit
1675 {
1676 current->u&=~(1LL<<HIREG);
1677 current->u&=~(1LL<<LOREG);
1678 current->uu&=~(1LL<<HIREG);
1679 current->uu&=~(1LL<<LOREG);
1680 alloc_reg64(current,i,HIREG);
1681 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1682 alloc_reg64(current,i,rs1[i]);
1683 alloc_reg64(current,i,rs2[i]);
1684 alloc_all(current,i);
1685 current->is32&=~(1LL<<HIREG);
1686 current->is32&=~(1LL<<LOREG);
1687 dirty_reg(current,HIREG);
1688 dirty_reg(current,LOREG);
1689 }
1690 }
1691 else
1692 {
1693 // Multiply by zero is zero.
1694 // MIPS does not have a divide by zero exception.
1695 // The result is undefined, we return zero.
1696 alloc_reg(current,i,HIREG);
1697 alloc_reg(current,i,LOREG);
1698 current->is32|=1LL<<HIREG;
1699 current->is32|=1LL<<LOREG;
1700 dirty_reg(current,HIREG);
1701 dirty_reg(current,LOREG);
1702 }
1703}
1704#endif
1705
1706void cop0_alloc(struct regstat *current,int i)
1707{
1708 if(opcode2[i]==0) // MFC0
1709 {
1710 if(rt1[i]) {
1711 clear_const(current,rt1[i]);
1712 alloc_all(current,i);
1713 alloc_reg(current,i,rt1[i]);
1714 current->is32|=1LL<<rt1[i];
1715 dirty_reg(current,rt1[i]);
1716 }
1717 }
1718 else if(opcode2[i]==4) // MTC0
1719 {
1720 if(rs1[i]){
1721 clear_const(current,rs1[i]);
1722 alloc_reg(current,i,rs1[i]);
1723 alloc_all(current,i);
1724 }
1725 else {
1726 alloc_all(current,i); // FIXME: Keep r0
1727 current->u&=~1LL;
1728 alloc_reg(current,i,0);
1729 }
1730 }
1731 else
1732 {
1733 // TLBR/TLBWI/TLBWR/TLBP/ERET
1734 assert(opcode2[i]==0x10);
1735 alloc_all(current,i);
1736 }
1737}
1738
1739void cop1_alloc(struct regstat *current,int i)
1740{
1741 alloc_reg(current,i,CSREG); // Load status
1742 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1743 {
1744 assert(rt1[i]);
1745 clear_const(current,rt1[i]);
1746 if(opcode2[i]==1) {
1747 alloc_reg64(current,i,rt1[i]); // DMFC1
1748 current->is32&=~(1LL<<rt1[i]);
1749 }else{
1750 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1751 current->is32|=1LL<<rt1[i];
1752 }
1753 dirty_reg(current,rt1[i]);
1754 alloc_reg_temp(current,i,-1);
1755 }
1756 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1757 {
1758 if(rs1[i]){
1759 clear_const(current,rs1[i]);
1760 if(opcode2[i]==5)
1761 alloc_reg64(current,i,rs1[i]); // DMTC1
1762 else
1763 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1764 alloc_reg_temp(current,i,-1);
1765 }
1766 else {
1767 current->u&=~1LL;
1768 alloc_reg(current,i,0);
1769 alloc_reg_temp(current,i,-1);
1770 }
1771 }
1772}
1773void fconv_alloc(struct regstat *current,int i)
1774{
1775 alloc_reg(current,i,CSREG); // Load status
1776 alloc_reg_temp(current,i,-1);
1777}
1778void float_alloc(struct regstat *current,int i)
1779{
1780 alloc_reg(current,i,CSREG); // Load status
1781 alloc_reg_temp(current,i,-1);
1782}
1783void fcomp_alloc(struct regstat *current,int i)
1784{
1785 alloc_reg(current,i,CSREG); // Load status
1786 alloc_reg(current,i,FSREG); // Load flags
1787 dirty_reg(current,FSREG); // Flag will be modified
1788 alloc_reg_temp(current,i,-1);
1789}
1790
1791void syscall_alloc(struct regstat *current,int i)
1792{
1793 alloc_cc(current,i);
1794 dirty_reg(current,CCREG);
1795 alloc_all(current,i);
1796 current->isconst=0;
1797}
1798
1799void delayslot_alloc(struct regstat *current,int i)
1800{
1801 switch(itype[i]) {
1802 case UJUMP:
1803 case CJUMP:
1804 case SJUMP:
1805 case RJUMP:
1806 case FJUMP:
1807 case SYSCALL:
1808 case SPAN:
1809 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1810 printf("Disabled speculative precompilation\n");
1811 stop_after_jal=1;
1812 break;
1813 case IMM16:
1814 imm16_alloc(current,i);
1815 break;
1816 case LOAD:
1817 case LOADLR:
1818 load_alloc(current,i);
1819 break;
1820 case STORE:
1821 case STORELR:
1822 store_alloc(current,i);
1823 break;
1824 case ALU:
1825 alu_alloc(current,i);
1826 break;
1827 case SHIFT:
1828 shift_alloc(current,i);
1829 break;
1830 case MULTDIV:
1831 multdiv_alloc(current,i);
1832 break;
1833 case SHIFTIMM:
1834 shiftimm_alloc(current,i);
1835 break;
1836 case MOV:
1837 mov_alloc(current,i);
1838 break;
1839 case COP0:
1840 cop0_alloc(current,i);
1841 break;
1842 case COP1:
1843 cop1_alloc(current,i);
1844 break;
1845 case C1LS:
1846 c1ls_alloc(current,i);
1847 break;
1848 case FCONV:
1849 fconv_alloc(current,i);
1850 break;
1851 case FLOAT:
1852 float_alloc(current,i);
1853 break;
1854 case FCOMP:
1855 fcomp_alloc(current,i);
1856 break;
1857 }
1858}
1859
1860// Special case where a branch and delay slot span two pages in virtual memory
1861static void pagespan_alloc(struct regstat *current,int i)
1862{
1863 current->isconst=0;
1864 current->wasconst=0;
1865 regs[i].wasconst=0;
1866 alloc_all(current,i);
1867 alloc_cc(current,i);
1868 dirty_reg(current,CCREG);
1869 if(opcode[i]==3) // JAL
1870 {
1871 alloc_reg(current,i,31);
1872 dirty_reg(current,31);
1873 }
1874 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1875 {
1876 alloc_reg(current,i,rs1[i]);
1877 if (rt1[i]==31) {
1878 alloc_reg(current,i,31);
1879 dirty_reg(current,31);
1880 }
1881 }
1882 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1883 {
1884 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1885 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1886 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1887 {
1888 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1889 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1890 }
1891 }
1892 else
1893 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1894 {
1895 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1896 if(!((current->is32>>rs1[i])&1))
1897 {
1898 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1899 }
1900 }
1901 else
1902 if(opcode[i]==0x11) // BC1
1903 {
1904 alloc_reg(current,i,FSREG);
1905 alloc_reg(current,i,CSREG);
1906 }
1907 //else ...
1908}
1909
1910add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1911{
1912 stubs[stubcount][0]=type;
1913 stubs[stubcount][1]=addr;
1914 stubs[stubcount][2]=retaddr;
1915 stubs[stubcount][3]=a;
1916 stubs[stubcount][4]=b;
1917 stubs[stubcount][5]=c;
1918 stubs[stubcount][6]=d;
1919 stubs[stubcount][7]=e;
1920 stubcount++;
1921}
1922
1923// Write out a single register
1924void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1925{
1926 int hr;
1927 for(hr=0;hr<HOST_REGS;hr++) {
1928 if(hr!=EXCLUDE_REG) {
1929 if((regmap[hr]&63)==r) {
1930 if((dirty>>hr)&1) {
1931 if(regmap[hr]<64) {
1932 emit_storereg(r,hr);
24385cae 1933#ifndef FORCE32
57871462 1934 if((is32>>regmap[hr])&1) {
1935 emit_sarimm(hr,31,hr);
1936 emit_storereg(r|64,hr);
1937 }
24385cae 1938#endif
57871462 1939 }else{
1940 emit_storereg(r|64,hr);
1941 }
1942 }
1943 }
1944 }
1945 }
1946}
1947
1948int mchecksum()
1949{
1950 //if(!tracedebug) return 0;
1951 int i;
1952 int sum=0;
1953 for(i=0;i<2097152;i++) {
1954 unsigned int temp=sum;
1955 sum<<=1;
1956 sum|=(~temp)>>31;
1957 sum^=((u_int *)rdram)[i];
1958 }
1959 return sum;
1960}
1961int rchecksum()
1962{
1963 int i;
1964 int sum=0;
1965 for(i=0;i<64;i++)
1966 sum^=((u_int *)reg)[i];
1967 return sum;
1968}
57871462 1969void rlist()
1970{
1971 int i;
1972 printf("TRACE: ");
1973 for(i=0;i<32;i++)
1974 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1975 printf("\n");
3d624f89 1976#ifndef DISABLE_COP1
57871462 1977 printf("TRACE: ");
1978 for(i=0;i<32;i++)
1979 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1980 printf("\n");
3d624f89 1981#endif
57871462 1982}
1983
1984void enabletrace()
1985{
1986 tracedebug=1;
1987}
1988
1989void memdebug(int i)
1990{
1991 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1992 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1993 //rlist();
1994 //if(tracedebug) {
1995 //if(Count>=-2084597794) {
1996 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1997 //if(0) {
1998 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1999 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2000 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2001 rlist();
2002 #ifdef __i386__
2003 printf("TRACE: %x\n",(&i)[-1]);
2004 #endif
2005 #ifdef __arm__
2006 int j;
2007 printf("TRACE: %x \n",(&j)[10]);
2008 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2009 #endif
2010 //fflush(stdout);
2011 }
2012 //printf("TRACE: %x\n",(&i)[-1]);
2013}
2014
2015void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2016{
2017 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2018}
2019
2020void alu_assemble(int i,struct regstat *i_regs)
2021{
2022 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2023 if(rt1[i]) {
2024 signed char s1,s2,t;
2025 t=get_reg(i_regs->regmap,rt1[i]);
2026 if(t>=0) {
2027 s1=get_reg(i_regs->regmap,rs1[i]);
2028 s2=get_reg(i_regs->regmap,rs2[i]);
2029 if(rs1[i]&&rs2[i]) {
2030 assert(s1>=0);
2031 assert(s2>=0);
2032 if(opcode2[i]&2) emit_sub(s1,s2,t);
2033 else emit_add(s1,s2,t);
2034 }
2035 else if(rs1[i]) {
2036 if(s1>=0) emit_mov(s1,t);
2037 else emit_loadreg(rs1[i],t);
2038 }
2039 else if(rs2[i]) {
2040 if(s2>=0) {
2041 if(opcode2[i]&2) emit_neg(s2,t);
2042 else emit_mov(s2,t);
2043 }
2044 else {
2045 emit_loadreg(rs2[i],t);
2046 if(opcode2[i]&2) emit_neg(t,t);
2047 }
2048 }
2049 else emit_zeroreg(t);
2050 }
2051 }
2052 }
2053 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2054 if(rt1[i]) {
2055 signed char s1l,s2l,s1h,s2h,tl,th;
2056 tl=get_reg(i_regs->regmap,rt1[i]);
2057 th=get_reg(i_regs->regmap,rt1[i]|64);
2058 if(tl>=0) {
2059 s1l=get_reg(i_regs->regmap,rs1[i]);
2060 s2l=get_reg(i_regs->regmap,rs2[i]);
2061 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2062 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2063 if(rs1[i]&&rs2[i]) {
2064 assert(s1l>=0);
2065 assert(s2l>=0);
2066 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2067 else emit_adds(s1l,s2l,tl);
2068 if(th>=0) {
2069 #ifdef INVERTED_CARRY
2070 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2071 #else
2072 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2073 #endif
2074 else emit_add(s1h,s2h,th);
2075 }
2076 }
2077 else if(rs1[i]) {
2078 if(s1l>=0) emit_mov(s1l,tl);
2079 else emit_loadreg(rs1[i],tl);
2080 if(th>=0) {
2081 if(s1h>=0) emit_mov(s1h,th);
2082 else emit_loadreg(rs1[i]|64,th);
2083 }
2084 }
2085 else if(rs2[i]) {
2086 if(s2l>=0) {
2087 if(opcode2[i]&2) emit_negs(s2l,tl);
2088 else emit_mov(s2l,tl);
2089 }
2090 else {
2091 emit_loadreg(rs2[i],tl);
2092 if(opcode2[i]&2) emit_negs(tl,tl);
2093 }
2094 if(th>=0) {
2095 #ifdef INVERTED_CARRY
2096 if(s2h>=0) emit_mov(s2h,th);
2097 else emit_loadreg(rs2[i]|64,th);
2098 if(opcode2[i]&2) {
2099 emit_adcimm(-1,th); // x86 has inverted carry flag
2100 emit_not(th,th);
2101 }
2102 #else
2103 if(opcode2[i]&2) {
2104 if(s2h>=0) emit_rscimm(s2h,0,th);
2105 else {
2106 emit_loadreg(rs2[i]|64,th);
2107 emit_rscimm(th,0,th);
2108 }
2109 }else{
2110 if(s2h>=0) emit_mov(s2h,th);
2111 else emit_loadreg(rs2[i]|64,th);
2112 }
2113 #endif
2114 }
2115 }
2116 else {
2117 emit_zeroreg(tl);
2118 if(th>=0) emit_zeroreg(th);
2119 }
2120 }
2121 }
2122 }
2123 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2124 if(rt1[i]) {
2125 signed char s1l,s1h,s2l,s2h,t;
2126 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2127 {
2128 t=get_reg(i_regs->regmap,rt1[i]);
2129 //assert(t>=0);
2130 if(t>=0) {
2131 s1l=get_reg(i_regs->regmap,rs1[i]);
2132 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2133 s2l=get_reg(i_regs->regmap,rs2[i]);
2134 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2135 if(rs2[i]==0) // rx<r0
2136 {
2137 assert(s1h>=0);
2138 if(opcode2[i]==0x2a) // SLT
2139 emit_shrimm(s1h,31,t);
2140 else // SLTU (unsigned can not be less than zero)
2141 emit_zeroreg(t);
2142 }
2143 else if(rs1[i]==0) // r0<rx
2144 {
2145 assert(s2h>=0);
2146 if(opcode2[i]==0x2a) // SLT
2147 emit_set_gz64_32(s2h,s2l,t);
2148 else // SLTU (set if not zero)
2149 emit_set_nz64_32(s2h,s2l,t);
2150 }
2151 else {
2152 assert(s1l>=0);assert(s1h>=0);
2153 assert(s2l>=0);assert(s2h>=0);
2154 if(opcode2[i]==0x2a) // SLT
2155 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2156 else // SLTU
2157 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2158 }
2159 }
2160 } else {
2161 t=get_reg(i_regs->regmap,rt1[i]);
2162 //assert(t>=0);
2163 if(t>=0) {
2164 s1l=get_reg(i_regs->regmap,rs1[i]);
2165 s2l=get_reg(i_regs->regmap,rs2[i]);
2166 if(rs2[i]==0) // rx<r0
2167 {
2168 assert(s1l>=0);
2169 if(opcode2[i]==0x2a) // SLT
2170 emit_shrimm(s1l,31,t);
2171 else // SLTU (unsigned can not be less than zero)
2172 emit_zeroreg(t);
2173 }
2174 else if(rs1[i]==0) // r0<rx
2175 {
2176 assert(s2l>=0);
2177 if(opcode2[i]==0x2a) // SLT
2178 emit_set_gz32(s2l,t);
2179 else // SLTU (set if not zero)
2180 emit_set_nz32(s2l,t);
2181 }
2182 else{
2183 assert(s1l>=0);assert(s2l>=0);
2184 if(opcode2[i]==0x2a) // SLT
2185 emit_set_if_less32(s1l,s2l,t);
2186 else // SLTU
2187 emit_set_if_carry32(s1l,s2l,t);
2188 }
2189 }
2190 }
2191 }
2192 }
2193 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2194 if(rt1[i]) {
2195 signed char s1l,s1h,s2l,s2h,th,tl;
2196 tl=get_reg(i_regs->regmap,rt1[i]);
2197 th=get_reg(i_regs->regmap,rt1[i]|64);
2198 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2199 {
2200 assert(tl>=0);
2201 if(tl>=0) {
2202 s1l=get_reg(i_regs->regmap,rs1[i]);
2203 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2204 s2l=get_reg(i_regs->regmap,rs2[i]);
2205 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2206 if(rs1[i]&&rs2[i]) {
2207 assert(s1l>=0);assert(s1h>=0);
2208 assert(s2l>=0);assert(s2h>=0);
2209 if(opcode2[i]==0x24) { // AND
2210 emit_and(s1l,s2l,tl);
2211 emit_and(s1h,s2h,th);
2212 } else
2213 if(opcode2[i]==0x25) { // OR
2214 emit_or(s1l,s2l,tl);
2215 emit_or(s1h,s2h,th);
2216 } else
2217 if(opcode2[i]==0x26) { // XOR
2218 emit_xor(s1l,s2l,tl);
2219 emit_xor(s1h,s2h,th);
2220 } else
2221 if(opcode2[i]==0x27) { // NOR
2222 emit_or(s1l,s2l,tl);
2223 emit_or(s1h,s2h,th);
2224 emit_not(tl,tl);
2225 emit_not(th,th);
2226 }
2227 }
2228 else
2229 {
2230 if(opcode2[i]==0x24) { // AND
2231 emit_zeroreg(tl);
2232 emit_zeroreg(th);
2233 } else
2234 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2235 if(rs1[i]){
2236 if(s1l>=0) emit_mov(s1l,tl);
2237 else emit_loadreg(rs1[i],tl);
2238 if(s1h>=0) emit_mov(s1h,th);
2239 else emit_loadreg(rs1[i]|64,th);
2240 }
2241 else
2242 if(rs2[i]){
2243 if(s2l>=0) emit_mov(s2l,tl);
2244 else emit_loadreg(rs2[i],tl);
2245 if(s2h>=0) emit_mov(s2h,th);
2246 else emit_loadreg(rs2[i]|64,th);
2247 }
2248 else{
2249 emit_zeroreg(tl);
2250 emit_zeroreg(th);
2251 }
2252 } else
2253 if(opcode2[i]==0x27) { // NOR
2254 if(rs1[i]){
2255 if(s1l>=0) emit_not(s1l,tl);
2256 else{
2257 emit_loadreg(rs1[i],tl);
2258 emit_not(tl,tl);
2259 }
2260 if(s1h>=0) emit_not(s1h,th);
2261 else{
2262 emit_loadreg(rs1[i]|64,th);
2263 emit_not(th,th);
2264 }
2265 }
2266 else
2267 if(rs2[i]){
2268 if(s2l>=0) emit_not(s2l,tl);
2269 else{
2270 emit_loadreg(rs2[i],tl);
2271 emit_not(tl,tl);
2272 }
2273 if(s2h>=0) emit_not(s2h,th);
2274 else{
2275 emit_loadreg(rs2[i]|64,th);
2276 emit_not(th,th);
2277 }
2278 }
2279 else {
2280 emit_movimm(-1,tl);
2281 emit_movimm(-1,th);
2282 }
2283 }
2284 }
2285 }
2286 }
2287 else
2288 {
2289 // 32 bit
2290 if(tl>=0) {
2291 s1l=get_reg(i_regs->regmap,rs1[i]);
2292 s2l=get_reg(i_regs->regmap,rs2[i]);
2293 if(rs1[i]&&rs2[i]) {
2294 assert(s1l>=0);
2295 assert(s2l>=0);
2296 if(opcode2[i]==0x24) { // AND
2297 emit_and(s1l,s2l,tl);
2298 } else
2299 if(opcode2[i]==0x25) { // OR
2300 emit_or(s1l,s2l,tl);
2301 } else
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2304 } else
2305 if(opcode2[i]==0x27) { // NOR
2306 emit_or(s1l,s2l,tl);
2307 emit_not(tl,tl);
2308 }
2309 }
2310 else
2311 {
2312 if(opcode2[i]==0x24) { // AND
2313 emit_zeroreg(tl);
2314 } else
2315 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2316 if(rs1[i]){
2317 if(s1l>=0) emit_mov(s1l,tl);
2318 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2319 }
2320 else
2321 if(rs2[i]){
2322 if(s2l>=0) emit_mov(s2l,tl);
2323 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2324 }
2325 else emit_zeroreg(tl);
2326 } else
2327 if(opcode2[i]==0x27) { // NOR
2328 if(rs1[i]){
2329 if(s1l>=0) emit_not(s1l,tl);
2330 else {
2331 emit_loadreg(rs1[i],tl);
2332 emit_not(tl,tl);
2333 }
2334 }
2335 else
2336 if(rs2[i]){
2337 if(s2l>=0) emit_not(s2l,tl);
2338 else {
2339 emit_loadreg(rs2[i],tl);
2340 emit_not(tl,tl);
2341 }
2342 }
2343 else emit_movimm(-1,tl);
2344 }
2345 }
2346 }
2347 }
2348 }
2349 }
2350}
2351
2352void imm16_assemble(int i,struct regstat *i_regs)
2353{
2354 if (opcode[i]==0x0f) { // LUI
2355 if(rt1[i]) {
2356 signed char t;
2357 t=get_reg(i_regs->regmap,rt1[i]);
2358 //assert(t>=0);
2359 if(t>=0) {
2360 if(!((i_regs->isconst>>t)&1))
2361 emit_movimm(imm[i]<<16,t);
2362 }
2363 }
2364 }
2365 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2366 if(rt1[i]) {
2367 signed char s,t;
2368 t=get_reg(i_regs->regmap,rt1[i]);
2369 s=get_reg(i_regs->regmap,rs1[i]);
2370 if(rs1[i]) {
2371 //assert(t>=0);
2372 //assert(s>=0);
2373 if(t>=0) {
2374 if(!((i_regs->isconst>>t)&1)) {
2375 if(s<0) {
2376 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2377 emit_addimm(t,imm[i],t);
2378 }else{
2379 if(!((i_regs->wasconst>>s)&1))
2380 emit_addimm(s,imm[i],t);
2381 else
2382 emit_movimm(constmap[i][s]+imm[i],t);
2383 }
2384 }
2385 }
2386 } else {
2387 if(t>=0) {
2388 if(!((i_regs->isconst>>t)&1))
2389 emit_movimm(imm[i],t);
2390 }
2391 }
2392 }
2393 }
2394 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2395 if(rt1[i]) {
2396 signed char sh,sl,th,tl;
2397 th=get_reg(i_regs->regmap,rt1[i]|64);
2398 tl=get_reg(i_regs->regmap,rt1[i]);
2399 sh=get_reg(i_regs->regmap,rs1[i]|64);
2400 sl=get_reg(i_regs->regmap,rs1[i]);
2401 if(tl>=0) {
2402 if(rs1[i]) {
2403 assert(sh>=0);
2404 assert(sl>=0);
2405 if(th>=0) {
2406 emit_addimm64_32(sh,sl,imm[i],th,tl);
2407 }
2408 else {
2409 emit_addimm(sl,imm[i],tl);
2410 }
2411 } else {
2412 emit_movimm(imm[i],tl);
2413 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2414 }
2415 }
2416 }
2417 }
2418 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2419 if(rt1[i]) {
2420 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2421 signed char sh,sl,t;
2422 t=get_reg(i_regs->regmap,rt1[i]);
2423 sh=get_reg(i_regs->regmap,rs1[i]|64);
2424 sl=get_reg(i_regs->regmap,rs1[i]);
2425 //assert(t>=0);
2426 if(t>=0) {
2427 if(rs1[i]>0) {
2428 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2429 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2430 if(opcode[i]==0x0a) { // SLTI
2431 if(sl<0) {
2432 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2433 emit_slti32(t,imm[i],t);
2434 }else{
2435 emit_slti32(sl,imm[i],t);
2436 }
2437 }
2438 else { // SLTIU
2439 if(sl<0) {
2440 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2441 emit_sltiu32(t,imm[i],t);
2442 }else{
2443 emit_sltiu32(sl,imm[i],t);
2444 }
2445 }
2446 }else{ // 64-bit
2447 assert(sl>=0);
2448 if(opcode[i]==0x0a) // SLTI
2449 emit_slti64_32(sh,sl,imm[i],t);
2450 else // SLTIU
2451 emit_sltiu64_32(sh,sl,imm[i],t);
2452 }
2453 }else{
2454 // SLTI(U) with r0 is just stupid,
2455 // nonetheless examples can be found
2456 if(opcode[i]==0x0a) // SLTI
2457 if(0<imm[i]) emit_movimm(1,t);
2458 else emit_zeroreg(t);
2459 else // SLTIU
2460 {
2461 if(imm[i]) emit_movimm(1,t);
2462 else emit_zeroreg(t);
2463 }
2464 }
2465 }
2466 }
2467 }
2468 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2469 if(rt1[i]) {
2470 signed char sh,sl,th,tl;
2471 th=get_reg(i_regs->regmap,rt1[i]|64);
2472 tl=get_reg(i_regs->regmap,rt1[i]);
2473 sh=get_reg(i_regs->regmap,rs1[i]|64);
2474 sl=get_reg(i_regs->regmap,rs1[i]);
2475 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2476 if(opcode[i]==0x0c) //ANDI
2477 {
2478 if(rs1[i]) {
2479 if(sl<0) {
2480 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2481 emit_andimm(tl,imm[i],tl);
2482 }else{
2483 if(!((i_regs->wasconst>>sl)&1))
2484 emit_andimm(sl,imm[i],tl);
2485 else
2486 emit_movimm(constmap[i][sl]&imm[i],tl);
2487 }
2488 }
2489 else
2490 emit_zeroreg(tl);
2491 if(th>=0) emit_zeroreg(th);
2492 }
2493 else
2494 {
2495 if(rs1[i]) {
2496 if(sl<0) {
2497 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2498 }
2499 if(th>=0) {
2500 if(sh<0) {
2501 emit_loadreg(rs1[i]|64,th);
2502 }else{
2503 emit_mov(sh,th);
2504 }
2505 }
2506 if(opcode[i]==0x0d) //ORI
2507 if(sl<0) {
2508 emit_orimm(tl,imm[i],tl);
2509 }else{
2510 if(!((i_regs->wasconst>>sl)&1))
2511 emit_orimm(sl,imm[i],tl);
2512 else
2513 emit_movimm(constmap[i][sl]|imm[i],tl);
2514 }
2515 if(opcode[i]==0x0e) //XORI
2516 if(sl<0) {
2517 emit_xorimm(tl,imm[i],tl);
2518 }else{
2519 if(!((i_regs->wasconst>>sl)&1))
2520 emit_xorimm(sl,imm[i],tl);
2521 else
2522 emit_movimm(constmap[i][sl]^imm[i],tl);
2523 }
2524 }
2525 else {
2526 emit_movimm(imm[i],tl);
2527 if(th>=0) emit_zeroreg(th);
2528 }
2529 }
2530 }
2531 }
2532 }
2533}
2534
2535void shiftimm_assemble(int i,struct regstat *i_regs)
2536{
2537 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2538 {
2539 if(rt1[i]) {
2540 signed char s,t;
2541 t=get_reg(i_regs->regmap,rt1[i]);
2542 s=get_reg(i_regs->regmap,rs1[i]);
2543 //assert(t>=0);
2544 if(t>=0){
2545 if(rs1[i]==0)
2546 {
2547 emit_zeroreg(t);
2548 }
2549 else
2550 {
2551 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2552 if(imm[i]) {
2553 if(opcode2[i]==0) // SLL
2554 {
2555 emit_shlimm(s<0?t:s,imm[i],t);
2556 }
2557 if(opcode2[i]==2) // SRL
2558 {
2559 emit_shrimm(s<0?t:s,imm[i],t);
2560 }
2561 if(opcode2[i]==3) // SRA
2562 {
2563 emit_sarimm(s<0?t:s,imm[i],t);
2564 }
2565 }else{
2566 // Shift by zero
2567 if(s>=0 && s!=t) emit_mov(s,t);
2568 }
2569 }
2570 }
2571 //emit_storereg(rt1[i],t); //DEBUG
2572 }
2573 }
2574 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2575 {
2576 if(rt1[i]) {
2577 signed char sh,sl,th,tl;
2578 th=get_reg(i_regs->regmap,rt1[i]|64);
2579 tl=get_reg(i_regs->regmap,rt1[i]);
2580 sh=get_reg(i_regs->regmap,rs1[i]|64);
2581 sl=get_reg(i_regs->regmap,rs1[i]);
2582 if(tl>=0) {
2583 if(rs1[i]==0)
2584 {
2585 emit_zeroreg(tl);
2586 if(th>=0) emit_zeroreg(th);
2587 }
2588 else
2589 {
2590 assert(sl>=0);
2591 assert(sh>=0);
2592 if(imm[i]) {
2593 if(opcode2[i]==0x38) // DSLL
2594 {
2595 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2596 emit_shlimm(sl,imm[i],tl);
2597 }
2598 if(opcode2[i]==0x3a) // DSRL
2599 {
2600 emit_shrdimm(sl,sh,imm[i],tl);
2601 if(th>=0) emit_shrimm(sh,imm[i],th);
2602 }
2603 if(opcode2[i]==0x3b) // DSRA
2604 {
2605 emit_shrdimm(sl,sh,imm[i],tl);
2606 if(th>=0) emit_sarimm(sh,imm[i],th);
2607 }
2608 }else{
2609 // Shift by zero
2610 if(sl!=tl) emit_mov(sl,tl);
2611 if(th>=0&&sh!=th) emit_mov(sh,th);
2612 }
2613 }
2614 }
2615 }
2616 }
2617 if(opcode2[i]==0x3c) // DSLL32
2618 {
2619 if(rt1[i]) {
2620 signed char sl,tl,th;
2621 tl=get_reg(i_regs->regmap,rt1[i]);
2622 th=get_reg(i_regs->regmap,rt1[i]|64);
2623 sl=get_reg(i_regs->regmap,rs1[i]);
2624 if(th>=0||tl>=0){
2625 assert(tl>=0);
2626 assert(th>=0);
2627 assert(sl>=0);
2628 emit_mov(sl,th);
2629 emit_zeroreg(tl);
2630 if(imm[i]>32)
2631 {
2632 emit_shlimm(th,imm[i]&31,th);
2633 }
2634 }
2635 }
2636 }
2637 if(opcode2[i]==0x3e) // DSRL32
2638 {
2639 if(rt1[i]) {
2640 signed char sh,tl,th;
2641 tl=get_reg(i_regs->regmap,rt1[i]);
2642 th=get_reg(i_regs->regmap,rt1[i]|64);
2643 sh=get_reg(i_regs->regmap,rs1[i]|64);
2644 if(tl>=0){
2645 assert(sh>=0);
2646 emit_mov(sh,tl);
2647 if(th>=0) emit_zeroreg(th);
2648 if(imm[i]>32)
2649 {
2650 emit_shrimm(tl,imm[i]&31,tl);
2651 }
2652 }
2653 }
2654 }
2655 if(opcode2[i]==0x3f) // DSRA32
2656 {
2657 if(rt1[i]) {
2658 signed char sh,tl;
2659 tl=get_reg(i_regs->regmap,rt1[i]);
2660 sh=get_reg(i_regs->regmap,rs1[i]|64);
2661 if(tl>=0){
2662 assert(sh>=0);
2663 emit_mov(sh,tl);
2664 if(imm[i]>32)
2665 {
2666 emit_sarimm(tl,imm[i]&31,tl);
2667 }
2668 }
2669 }
2670 }
2671}
2672
2673#ifndef shift_assemble
2674void shift_assemble(int i,struct regstat *i_regs)
2675{
2676 printf("Need shift_assemble for this architecture.\n");
2677 exit(1);
2678}
2679#endif
2680
2681void load_assemble(int i,struct regstat *i_regs)
2682{
2683 int s,th,tl,addr,map=-1;
2684 int offset;
2685 int jaddr=0;
2686 int memtarget,c=0;
2687 u_int hr,reglist=0;
2688 th=get_reg(i_regs->regmap,rt1[i]|64);
2689 tl=get_reg(i_regs->regmap,rt1[i]);
2690 s=get_reg(i_regs->regmap,rs1[i]);
2691 offset=imm[i];
2692 for(hr=0;hr<HOST_REGS;hr++) {
2693 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2694 }
2695 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2696 if(s>=0) {
2697 c=(i_regs->wasconst>>s)&1;
2698 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2699 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2700 }
2701 if(offset||s<0||c) addr=tl;
2702 else addr=s;
2703 //printf("load_assemble: c=%d\n",c);
2704 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2705 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2706 if(tl>=0) {
2707 //assert(tl>=0);
2708 //assert(rt1[i]);
2709 reglist&=~(1<<tl);
2710 if(th>=0) reglist&=~(1<<th);
2711 if(!using_tlb) {
2712 if(!c) {
2713//#define R29_HACK 1
2714 #ifdef R29_HACK
2715 // Strmnnrmn's speed hack
2716 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2717 #endif
2718 {
2719 emit_cmpimm(addr,0x800000);
2720 jaddr=(int)out;
2721 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2722 // Hint to branch predictor that the branch is unlikely to be taken
2723 if(rs1[i]>=28)
2724 emit_jno_unlikely(0);
2725 else
2726 #endif
2727 emit_jno(0);
2728 }
2729 }
2730 }else{ // using tlb
2731 int x=0;
2732 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2733 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2734 map=get_reg(i_regs->regmap,TLREG);
2735 assert(map>=0);
2736 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2737 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2738 }
2739 if (opcode[i]==0x20) { // LB
2740 if(!c||memtarget) {
2741 #ifdef HOST_IMM_ADDR32
2742 if(c)
2743 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2744 else
2745 #endif
2746 {
2747 //emit_xorimm(addr,3,tl);
2748 //gen_tlb_addr_r(tl,map);
2749 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2750 int x=0;
2002a1db 2751#ifdef BIG_ENDIAN_MIPS
57871462 2752 if(!c) emit_xorimm(addr,3,tl);
2753 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2754#else
2755 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2756 else if (tl!=addr) emit_mov(addr,tl);
2757#endif
57871462 2758 emit_movsbl_indexed_tlb(x,tl,map,tl);
2759 }
2760 if(jaddr)
2761 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2762 }
2763 else
2764 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2765 }
2766 if (opcode[i]==0x21) { // LH
2767 if(!c||memtarget) {
2768 #ifdef HOST_IMM_ADDR32
2769 if(c)
2770 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2771 else
2772 #endif
2773 {
2774 int x=0;
2002a1db 2775#ifdef BIG_ENDIAN_MIPS
57871462 2776 if(!c) emit_xorimm(addr,2,tl);
2777 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2778#else
2779 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2780 else if (tl!=addr) emit_mov(addr,tl);
2781#endif
57871462 2782 //#ifdef
2783 //emit_movswl_indexed_tlb(x,tl,map,tl);
2784 //else
2785 if(map>=0) {
2786 gen_tlb_addr_r(tl,map);
2787 emit_movswl_indexed(x,tl,tl);
2788 }else
2789 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2790 }
2791 if(jaddr)
2792 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2793 }
2794 else
2795 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2796 }
2797 if (opcode[i]==0x23) { // LW
2798 if(!c||memtarget) {
2799 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2800 #ifdef HOST_IMM_ADDR32
2801 if(c)
2802 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2803 else
2804 #endif
2805 emit_readword_indexed_tlb(0,addr,map,tl);
2806 if(jaddr)
2807 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2808 }
2809 else
2810 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2811 }
2812 if (opcode[i]==0x24) { // LBU
2813 if(!c||memtarget) {
2814 #ifdef HOST_IMM_ADDR32
2815 if(c)
2816 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2817 else
2818 #endif
2819 {
2820 //emit_xorimm(addr,3,tl);
2821 //gen_tlb_addr_r(tl,map);
2822 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2823 int x=0;
2002a1db 2824#ifdef BIG_ENDIAN_MIPS
57871462 2825 if(!c) emit_xorimm(addr,3,tl);
2826 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2827#else
2828 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2829 else if (tl!=addr) emit_mov(addr,tl);
2830#endif
57871462 2831 emit_movzbl_indexed_tlb(x,tl,map,tl);
2832 }
2833 if(jaddr)
2834 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2835 }
2836 else
2837 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2838 }
2839 if (opcode[i]==0x25) { // LHU
2840 if(!c||memtarget) {
2841 #ifdef HOST_IMM_ADDR32
2842 if(c)
2843 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2844 else
2845 #endif
2846 {
2847 int x=0;
2002a1db 2848#ifdef BIG_ENDIAN_MIPS
57871462 2849 if(!c) emit_xorimm(addr,2,tl);
2850 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2851#else
2852 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2853 else if (tl!=addr) emit_mov(addr,tl);
2854#endif
57871462 2855 //#ifdef
2856 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2857 //#else
2858 if(map>=0) {
2859 gen_tlb_addr_r(tl,map);
2860 emit_movzwl_indexed(x,tl,tl);
2861 }else
2862 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2863 if(jaddr)
2864 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2865 }
2866 }
2867 else
2868 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2869 }
2870 if (opcode[i]==0x27) { // LWU
2871 assert(th>=0);
2872 if(!c||memtarget) {
2873 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2874 #ifdef HOST_IMM_ADDR32
2875 if(c)
2876 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2877 else
2878 #endif
2879 emit_readword_indexed_tlb(0,addr,map,tl);
2880 if(jaddr)
2881 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2882 }
2883 else {
2884 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2885 }
2886 emit_zeroreg(th);
2887 }
2888 if (opcode[i]==0x37) { // LD
2889 if(!c||memtarget) {
2890 //gen_tlb_addr_r(tl,map);
2891 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2892 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2893 #ifdef HOST_IMM_ADDR32
2894 if(c)
2895 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2896 else
2897 #endif
2898 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2899 if(jaddr)
2900 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2901 }
2902 else
2903 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 }
2905 //emit_storereg(rt1[i],tl); // DEBUG
2906 }
2907 //if(opcode[i]==0x23)
2908 //if(opcode[i]==0x24)
2909 //if(opcode[i]==0x23||opcode[i]==0x24)
2910 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2911 {
2912 //emit_pusha();
2913 save_regs(0x100f);
2914 emit_readword((int)&last_count,ECX);
2915 #ifdef __i386__
2916 if(get_reg(i_regs->regmap,CCREG)<0)
2917 emit_loadreg(CCREG,HOST_CCREG);
2918 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2919 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2920 emit_writeword(HOST_CCREG,(int)&Count);
2921 #endif
2922 #ifdef __arm__
2923 if(get_reg(i_regs->regmap,CCREG)<0)
2924 emit_loadreg(CCREG,0);
2925 else
2926 emit_mov(HOST_CCREG,0);
2927 emit_add(0,ECX,0);
2928 emit_addimm(0,2*ccadj[i],0);
2929 emit_writeword(0,(int)&Count);
2930 #endif
2931 emit_call((int)memdebug);
2932 //emit_popa();
2933 restore_regs(0x100f);
2934 }/**/
2935}
2936
2937#ifndef loadlr_assemble
2938void loadlr_assemble(int i,struct regstat *i_regs)
2939{
2940 printf("Need loadlr_assemble for this architecture.\n");
2941 exit(1);
2942}
2943#endif
2944
2945void store_assemble(int i,struct regstat *i_regs)
2946{
2947 int s,th,tl,map=-1;
2948 int addr,temp;
2949 int offset;
2950 int jaddr=0,jaddr2,type;
2951 int memtarget,c=0;
2952 int agr=AGEN1+(i&1);
2953 u_int hr,reglist=0;
2954 th=get_reg(i_regs->regmap,rs2[i]|64);
2955 tl=get_reg(i_regs->regmap,rs2[i]);
2956 s=get_reg(i_regs->regmap,rs1[i]);
2957 temp=get_reg(i_regs->regmap,agr);
2958 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2959 offset=imm[i];
2960 if(s>=0) {
2961 c=(i_regs->wasconst>>s)&1;
2962 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2963 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2964 }
2965 assert(tl>=0);
2966 assert(temp>=0);
2967 for(hr=0;hr<HOST_REGS;hr++) {
2968 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2969 }
2970 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2971 if(offset||s<0||c) addr=temp;
2972 else addr=s;
2973 if(!using_tlb) {
2974 if(!c) {
2975 #ifdef R29_HACK
2976 // Strmnnrmn's speed hack
2977 memtarget=1;
2978 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2979 #endif
2980 emit_cmpimm(addr,0x800000);
2981 #ifdef DESTRUCTIVE_SHIFT
2982 if(s==addr) emit_mov(s,temp);
2983 #endif
2984 #ifdef R29_HACK
2985 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2986 #endif
2987 {
2988 jaddr=(int)out;
2989 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2990 // Hint to branch predictor that the branch is unlikely to be taken
2991 if(rs1[i]>=28)
2992 emit_jno_unlikely(0);
2993 else
2994 #endif
2995 emit_jno(0);
2996 }
2997 }
2998 }else{ // using tlb
2999 int x=0;
3000 if (opcode[i]==0x28) x=3; // SB
3001 if (opcode[i]==0x29) x=2; // SH
3002 map=get_reg(i_regs->regmap,TLREG);
3003 assert(map>=0);
3004 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3005 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3006 }
3007
3008 if (opcode[i]==0x28) { // SB
3009 if(!c||memtarget) {
3010 int x=0;
2002a1db 3011#ifdef BIG_ENDIAN_MIPS
57871462 3012 if(!c) emit_xorimm(addr,3,temp);
3013 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3014#else
3015 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3016 else if (addr!=temp) emit_mov(addr,temp);
3017#endif
57871462 3018 //gen_tlb_addr_w(temp,map);
3019 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3020 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3021 }
3022 type=STOREB_STUB;
3023 }
3024 if (opcode[i]==0x29) { // SH
3025 if(!c||memtarget) {
3026 int x=0;
2002a1db 3027#ifdef BIG_ENDIAN_MIPS
57871462 3028 if(!c) emit_xorimm(addr,2,temp);
3029 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3030#else
3031 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3032 else if (addr!=temp) emit_mov(addr,temp);
3033#endif
57871462 3034 //#ifdef
3035 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3036 //#else
3037 if(map>=0) {
3038 gen_tlb_addr_w(temp,map);
3039 emit_writehword_indexed(tl,x,temp);
3040 }else
3041 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3042 }
3043 type=STOREH_STUB;
3044 }
3045 if (opcode[i]==0x2B) { // SW
3046 if(!c||memtarget)
3047 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3048 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3049 type=STOREW_STUB;
3050 }
3051 if (opcode[i]==0x3F) { // SD
3052 if(!c||memtarget) {
3053 if(rs2[i]) {
3054 assert(th>=0);
3055 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3056 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3057 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3058 }else{
3059 // Store zero
3060 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3061 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3062 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3063 }
3064 }
3065 type=STORED_STUB;
3066 }
3067 if(jaddr) {
3068 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3069 } else if(!memtarget) {
3070 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3071 }
3072 if(!using_tlb) {
3073 if(!c||memtarget) {
3074 #ifdef DESTRUCTIVE_SHIFT
3075 // The x86 shift operation is 'destructive'; it overwrites the
3076 // source register, so we need to make a copy first and use that.
3077 addr=temp;
3078 #endif
3079 #if defined(HOST_IMM8)
3080 int ir=get_reg(i_regs->regmap,INVCP);
3081 assert(ir>=0);
3082 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3083 #else
3084 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3085 #endif
3086 jaddr2=(int)out;
3087 emit_jne(0);
3088 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3089 }
3090 }
3091 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3092 //if(opcode[i]==0x2B || opcode[i]==0x28)
3093 //if(opcode[i]==0x2B || opcode[i]==0x29)
3094 //if(opcode[i]==0x2B)
3095 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3096 {
3097 //emit_pusha();
3098 save_regs(0x100f);
3099 emit_readword((int)&last_count,ECX);
3100 #ifdef __i386__
3101 if(get_reg(i_regs->regmap,CCREG)<0)
3102 emit_loadreg(CCREG,HOST_CCREG);
3103 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3104 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3105 emit_writeword(HOST_CCREG,(int)&Count);
3106 #endif
3107 #ifdef __arm__
3108 if(get_reg(i_regs->regmap,CCREG)<0)
3109 emit_loadreg(CCREG,0);
3110 else
3111 emit_mov(HOST_CCREG,0);
3112 emit_add(0,ECX,0);
3113 emit_addimm(0,2*ccadj[i],0);
3114 emit_writeword(0,(int)&Count);
3115 #endif
3116 emit_call((int)memdebug);
3117 //emit_popa();
3118 restore_regs(0x100f);
3119 }/**/
3120}
3121
3122void storelr_assemble(int i,struct regstat *i_regs)
3123{
3124 int s,th,tl;
3125 int temp;
3126 int temp2;
3127 int offset;
3128 int jaddr=0,jaddr2;
3129 int case1,case2,case3;
3130 int done0,done1,done2;
3131 int memtarget,c=0;
3132 u_int hr,reglist=0;
3133 th=get_reg(i_regs->regmap,rs2[i]|64);
3134 tl=get_reg(i_regs->regmap,rs2[i]);
3135 s=get_reg(i_regs->regmap,rs1[i]);
3136 temp=get_reg(i_regs->regmap,-1);
3137 offset=imm[i];
3138 if(s>=0) {
3139 c=(i_regs->isconst>>s)&1;
3140 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3141 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3142 }
3143 assert(tl>=0);
3144 for(hr=0;hr<HOST_REGS;hr++) {
3145 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3146 }
3147 if(tl>=0) {
3148 assert(temp>=0);
3149 if(!using_tlb) {
3150 if(!c) {
3151 emit_cmpimm(s<0||offset?temp:s,0x800000);
3152 if(!offset&&s!=temp) emit_mov(s,temp);
3153 jaddr=(int)out;
3154 emit_jno(0);
3155 }
3156 else
3157 {
3158 if(!memtarget||!rs1[i]) {
3159 jaddr=(int)out;
3160 emit_jmp(0);
3161 }
3162 }
3163 if((u_int)rdram!=0x80000000)
3164 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3165 }else{ // using tlb
3166 int map=get_reg(i_regs->regmap,TLREG);
3167 assert(map>=0);
3168 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3169 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3170 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3171 if(!jaddr&&!memtarget) {
3172 jaddr=(int)out;
3173 emit_jmp(0);
3174 }
3175 gen_tlb_addr_w(temp,map);
3176 }
3177
3178 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3179 temp2=get_reg(i_regs->regmap,FTEMP);
3180 if(!rs2[i]) temp2=th=tl;
3181 }
3182
2002a1db 3183#ifndef BIG_ENDIAN_MIPS
3184 emit_xorimm(temp,3,temp);
3185#endif
57871462 3186 emit_testimm(temp,2);
3187 case2=(int)out;
3188 emit_jne(0);
3189 emit_testimm(temp,1);
3190 case1=(int)out;
3191 emit_jne(0);
3192 // 0
3193 if (opcode[i]==0x2A) { // SWL
3194 emit_writeword_indexed(tl,0,temp);
3195 }
3196 if (opcode[i]==0x2E) { // SWR
3197 emit_writebyte_indexed(tl,3,temp);
3198 }
3199 if (opcode[i]==0x2C) { // SDL
3200 emit_writeword_indexed(th,0,temp);
3201 if(rs2[i]) emit_mov(tl,temp2);
3202 }
3203 if (opcode[i]==0x2D) { // SDR
3204 emit_writebyte_indexed(tl,3,temp);
3205 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3206 }
3207 done0=(int)out;
3208 emit_jmp(0);
3209 // 1
3210 set_jump_target(case1,(int)out);
3211 if (opcode[i]==0x2A) { // SWL
3212 // Write 3 msb into three least significant bytes
3213 if(rs2[i]) emit_rorimm(tl,8,tl);
3214 emit_writehword_indexed(tl,-1,temp);
3215 if(rs2[i]) emit_rorimm(tl,16,tl);
3216 emit_writebyte_indexed(tl,1,temp);
3217 if(rs2[i]) emit_rorimm(tl,8,tl);
3218 }
3219 if (opcode[i]==0x2E) { // SWR
3220 // Write two lsb into two most significant bytes
3221 emit_writehword_indexed(tl,1,temp);
3222 }
3223 if (opcode[i]==0x2C) { // SDL
3224 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3225 // Write 3 msb into three least significant bytes
3226 if(rs2[i]) emit_rorimm(th,8,th);
3227 emit_writehword_indexed(th,-1,temp);
3228 if(rs2[i]) emit_rorimm(th,16,th);
3229 emit_writebyte_indexed(th,1,temp);
3230 if(rs2[i]) emit_rorimm(th,8,th);
3231 }
3232 if (opcode[i]==0x2D) { // SDR
3233 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3234 // Write two lsb into two most significant bytes
3235 emit_writehword_indexed(tl,1,temp);
3236 }
3237 done1=(int)out;
3238 emit_jmp(0);
3239 // 2
3240 set_jump_target(case2,(int)out);
3241 emit_testimm(temp,1);
3242 case3=(int)out;
3243 emit_jne(0);
3244 if (opcode[i]==0x2A) { // SWL
3245 // Write two msb into two least significant bytes
3246 if(rs2[i]) emit_rorimm(tl,16,tl);
3247 emit_writehword_indexed(tl,-2,temp);
3248 if(rs2[i]) emit_rorimm(tl,16,tl);
3249 }
3250 if (opcode[i]==0x2E) { // SWR
3251 // Write 3 lsb into three most significant bytes
3252 emit_writebyte_indexed(tl,-1,temp);
3253 if(rs2[i]) emit_rorimm(tl,8,tl);
3254 emit_writehword_indexed(tl,0,temp);
3255 if(rs2[i]) emit_rorimm(tl,24,tl);
3256 }
3257 if (opcode[i]==0x2C) { // SDL
3258 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3259 // Write two msb into two least significant bytes
3260 if(rs2[i]) emit_rorimm(th,16,th);
3261 emit_writehword_indexed(th,-2,temp);
3262 if(rs2[i]) emit_rorimm(th,16,th);
3263 }
3264 if (opcode[i]==0x2D) { // SDR
3265 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3266 // Write 3 lsb into three most significant bytes
3267 emit_writebyte_indexed(tl,-1,temp);
3268 if(rs2[i]) emit_rorimm(tl,8,tl);
3269 emit_writehword_indexed(tl,0,temp);
3270 if(rs2[i]) emit_rorimm(tl,24,tl);
3271 }
3272 done2=(int)out;
3273 emit_jmp(0);
3274 // 3
3275 set_jump_target(case3,(int)out);
3276 if (opcode[i]==0x2A) { // SWL
3277 // Write msb into least significant byte
3278 if(rs2[i]) emit_rorimm(tl,24,tl);
3279 emit_writebyte_indexed(tl,-3,temp);
3280 if(rs2[i]) emit_rorimm(tl,8,tl);
3281 }
3282 if (opcode[i]==0x2E) { // SWR
3283 // Write entire word
3284 emit_writeword_indexed(tl,-3,temp);
3285 }
3286 if (opcode[i]==0x2C) { // SDL
3287 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3288 // Write msb into least significant byte
3289 if(rs2[i]) emit_rorimm(th,24,th);
3290 emit_writebyte_indexed(th,-3,temp);
3291 if(rs2[i]) emit_rorimm(th,8,th);
3292 }
3293 if (opcode[i]==0x2D) { // SDR
3294 if(rs2[i]) emit_mov(th,temp2);
3295 // Write entire word
3296 emit_writeword_indexed(tl,-3,temp);
3297 }
3298 set_jump_target(done0,(int)out);
3299 set_jump_target(done1,(int)out);
3300 set_jump_target(done2,(int)out);
3301 if (opcode[i]==0x2C) { // SDL
3302 emit_testimm(temp,4);
3303 done0=(int)out;
3304 emit_jne(0);
3305 emit_andimm(temp,~3,temp);
3306 emit_writeword_indexed(temp2,4,temp);
3307 set_jump_target(done0,(int)out);
3308 }
3309 if (opcode[i]==0x2D) { // SDR
3310 emit_testimm(temp,4);
3311 done0=(int)out;
3312 emit_jeq(0);
3313 emit_andimm(temp,~3,temp);
3314 emit_writeword_indexed(temp2,-4,temp);
3315 set_jump_target(done0,(int)out);
3316 }
3317 if(!c||!memtarget)
3318 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3319 }
3320 if(!using_tlb) {
3321 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3322 #if defined(HOST_IMM8)
3323 int ir=get_reg(i_regs->regmap,INVCP);
3324 assert(ir>=0);
3325 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3326 #else
3327 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3328 #endif
3329 jaddr2=(int)out;
3330 emit_jne(0);
3331 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3332 }
3333 /*
3334 emit_pusha();
3335 //save_regs(0x100f);
3336 emit_readword((int)&last_count,ECX);
3337 if(get_reg(i_regs->regmap,CCREG)<0)
3338 emit_loadreg(CCREG,HOST_CCREG);
3339 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3340 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3341 emit_writeword(HOST_CCREG,(int)&Count);
3342 emit_call((int)memdebug);
3343 emit_popa();
3344 //restore_regs(0x100f);
3345 /**/
3346}
3347
3348void c1ls_assemble(int i,struct regstat *i_regs)
3349{
3d624f89 3350#ifndef DISABLE_COP1
57871462 3351 int s,th,tl;
3352 int temp,ar;
3353 int map=-1;
3354 int offset;
3355 int c=0;
3356 int jaddr,jaddr2=0,jaddr3,type;
3357 int agr=AGEN1+(i&1);
3358 u_int hr,reglist=0;
3359 th=get_reg(i_regs->regmap,FTEMP|64);
3360 tl=get_reg(i_regs->regmap,FTEMP);
3361 s=get_reg(i_regs->regmap,rs1[i]);
3362 temp=get_reg(i_regs->regmap,agr);
3363 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3364 offset=imm[i];
3365 assert(tl>=0);
3366 assert(rs1[i]>0);
3367 assert(temp>=0);
3368 for(hr=0;hr<HOST_REGS;hr++) {
3369 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3370 }
3371 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3372 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3373 {
3374 // Loads use a temporary register which we need to save
3375 reglist|=1<<temp;
3376 }
3377 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3378 ar=temp;
3379 else // LWC1/LDC1
3380 ar=tl;
3381 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3382 //else c=(i_regs->wasconst>>s)&1;
3383 if(s>=0) c=(i_regs->wasconst>>s)&1;
3384 // Check cop1 unusable
3385 if(!cop1_usable) {
3386 signed char rs=get_reg(i_regs->regmap,CSREG);
3387 assert(rs>=0);
3388 emit_testimm(rs,0x20000000);
3389 jaddr=(int)out;
3390 emit_jeq(0);
3391 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3392 cop1_usable=1;
3393 }
3394 if (opcode[i]==0x39) { // SWC1 (get float address)
3395 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3396 }
3397 if (opcode[i]==0x3D) { // SDC1 (get double address)
3398 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3399 }
3400 // Generate address + offset
3401 if(!using_tlb) {
3402 if(!c)
3403 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3404 }
3405 else
3406 {
3407 map=get_reg(i_regs->regmap,TLREG);
3408 assert(map>=0);
3409 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3410 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3411 }
3412 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3413 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3414 }
3415 }
3416 if (opcode[i]==0x39) { // SWC1 (read float)
3417 emit_readword_indexed(0,tl,tl);
3418 }
3419 if (opcode[i]==0x3D) { // SDC1 (read double)
3420 emit_readword_indexed(4,tl,th);
3421 emit_readword_indexed(0,tl,tl);
3422 }
3423 if (opcode[i]==0x31) { // LWC1 (get target address)
3424 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3425 }
3426 if (opcode[i]==0x35) { // LDC1 (get target address)
3427 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3428 }
3429 if(!using_tlb) {
3430 if(!c) {
3431 jaddr2=(int)out;
3432 emit_jno(0);
3433 }
3434 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3435 jaddr2=(int)out;
3436 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3437 }
3438 #ifdef DESTRUCTIVE_SHIFT
3439 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3440 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3441 }
3442 #endif
3443 }else{
3444 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3445 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3446 }
3447 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3448 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3449 }
3450 }
3451 if (opcode[i]==0x31) { // LWC1
3452 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3453 //gen_tlb_addr_r(ar,map);
3454 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3455 #ifdef HOST_IMM_ADDR32
3456 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3457 else
3458 #endif
3459 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3460 type=LOADW_STUB;
3461 }
3462 if (opcode[i]==0x35) { // LDC1
3463 assert(th>=0);
3464 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3465 //gen_tlb_addr_r(ar,map);
3466 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3467 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3468 #ifdef HOST_IMM_ADDR32
3469 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3470 else
3471 #endif
3472 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3473 type=LOADD_STUB;
3474 }
3475 if (opcode[i]==0x39) { // SWC1
3476 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3477 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3478 type=STOREW_STUB;
3479 }
3480 if (opcode[i]==0x3D) { // SDC1
3481 assert(th>=0);
3482 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3483 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3484 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3485 type=STORED_STUB;
3486 }
3487 if(!using_tlb) {
3488 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3489 #ifndef DESTRUCTIVE_SHIFT
3490 temp=offset||c||s<0?ar:s;
3491 #endif
3492 #if defined(HOST_IMM8)
3493 int ir=get_reg(i_regs->regmap,INVCP);
3494 assert(ir>=0);
3495 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3496 #else
3497 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3498 #endif
3499 jaddr3=(int)out;
3500 emit_jne(0);
3501 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3502 }
3503 }