1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
41 #include "emu_if.h" // emulator interface
42 #include "linkage_offsets.h"
43 #include "compiler_features.h"
44 #include "arm_features.h"
47 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
50 #define min(a, b) ((b) < (a) ? (b) : (a))
53 #define max(a, b) ((b) > (a) ? (b) : (a))
58 //#define REGMAP_PRINT // with DISASM only
63 #define assem_debug printf
65 #define assem_debug(...)
67 //#define inv_debug printf
68 #define inv_debug(...)
71 #include "assem_x86.h"
74 #include "assem_x64.h"
77 #include "assem_arm.h"
80 #include "assem_arm64.h"
83 #define RAM_SIZE 0x200000
85 #define MAX_OUTPUT_BLOCK_SIZE 262144
86 #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
87 #define PAGE_COUNT 1024
89 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
90 #define INVALIDATE_USE_COND_CALL
94 // apparently Vita has a 16MB limit, so either we cut tc in half,
95 // or use this hack (it's a hack because tc size was designed to be power-of-2)
96 #define TC_REDUCE_BYTES 4096
98 #define TC_REDUCE_BYTES 0
103 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
104 const void *f[2048 / sizeof(void *)];
109 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
110 struct ndrc_tramp tramp;
113 #ifdef BASE_ADDR_DYNAMIC
114 static struct ndrc_mem *ndrc;
116 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
117 static struct ndrc_mem *ndrc = &ndrc_;
119 #ifdef TC_WRITE_OFFSET
121 # include <sys/types.h>
122 # include <sys/stat.h>
126 static long ndrc_write_ofs;
127 #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
129 #define NDRC_WRITE_OFFSET(x) (x)
152 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
153 // don't match .regmap will be written back
154 // [i].regmap_entry - regs that must be set up if someone jumps here
155 // [i].regmap - regs [i] insn will read/(over)write
156 // branch_regs[i].* - same as above but for branches, takes delay slot into account
159 signed char regmap_entry[HOST_REGS];
160 signed char regmap[HOST_REGS];
164 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
165 u_int isconst; // ... but isconst is false when r2 is known (hr)
166 u_int loadedconst; // host regs that have constants loaded
167 u_int noevict; // can't evict this hr (alloced by current op)
168 //u_int waswritten; // MIPS regs that were used as store base before
198 struct block_info *next;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
207 u_char inv_near_misses;
225 static struct decoded_insn
228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
247 static struct compile_info
252 signed char min_free_regs;
254 signed char reserved[2];
258 static char invalid_code[0x100000];
259 static struct ht_entry hash_table[65536];
260 static struct block_info *blocks[PAGE_COUNT];
261 static struct jump_info *jumps[PAGE_COUNT];
263 static u_int *source;
264 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
265 static uint64_t gte_rt[MAXBLOCK];
266 static uint64_t gte_unneeded[MAXBLOCK];
267 static u_int smrv[32]; // speculated MIPS register values
268 static u_int smrv_strong; // mask or regs that are likely to have correct values
269 static u_int smrv_weak; // same, but somewhat less likely
270 static u_int smrv_strong_next; // same, but after current insn executes
271 static u_int smrv_weak_next;
272 static uint64_t unneeded_reg[MAXBLOCK];
273 static uint64_t branch_unneeded_reg[MAXBLOCK];
274 // see 'struct regstat' for a description
275 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
276 // contains 'real' consts at [i] insn, but may differ from what's actually
277 // loaded in host reg as 'final' value is always loaded, see get_final_value()
278 static uint32_t current_constmap[HOST_REGS];
279 static uint32_t constmap[MAXBLOCK][HOST_REGS];
280 static struct regstat regs[MAXBLOCK];
281 static struct regstat branch_regs[MAXBLOCK];
283 static void *instr_addr[MAXBLOCK];
284 static struct link_entry link_addr[MAXBLOCK];
285 static int linkcount;
286 static struct code_stub stubs[MAXBLOCK*3];
287 static int stubcount;
288 static u_int literals[1024][2];
289 static int literalcount;
290 static int is_delayslot;
291 static char shadow[1048576] __attribute__((aligned(16)));
293 static u_int expirep;
294 static u_int stop_after_jal;
295 static u_int f1_hack;
297 static int stat_bc_direct;
298 static int stat_bc_pre;
299 static int stat_bc_restore;
300 static int stat_ht_lookups;
301 static int stat_jump_in_lookups;
302 static int stat_restore_tries;
303 static int stat_restore_compares;
304 static int stat_inv_addr_calls;
305 static int stat_inv_hits;
306 static int stat_blocks;
307 static int stat_links;
308 #define stat_inc(s) s++
309 #define stat_dec(s) s--
310 #define stat_clear(s) s = 0
314 #define stat_clear(s)
317 int new_dynarec_hacks;
318 int new_dynarec_hacks_pergame;
319 int new_dynarec_hacks_old;
320 int new_dynarec_did_compile;
322 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
324 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
325 extern int last_count; // last absolute target, often = next_interupt
327 extern int pending_exception;
328 extern int branch_target;
329 extern uintptr_t ram_offset;
330 extern uintptr_t mini_ht[32][2];
332 /* registers that may be allocated */
334 #define LOREG 32 // lo
335 #define HIREG 33 // hi
336 //#define FSREG 34 // FPU status (FCSR)
337 //#define CSREG 35 // Coprocessor status
338 #define CCREG 36 // Cycle count
339 #define INVCP 37 // Pointer to invalid_code
340 //#define MMREG 38 // Pointer to memory_map
341 #define ROREG 39 // ram offset (if rdram!=0x80000000)
343 #define FTEMP 40 // FPU temporary register
344 #define PTEMP 41 // Prefetch temporary register
345 //#define TLREG 42 // TLB mapping offset
346 #define RHASH 43 // Return address hash
347 #define RHTBL 44 // Return address hash table address
348 #define RTEMP 45 // JR/JALR address register
350 #define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
351 //#define AGEN2 47 // Address generation temporary register
352 #define BTREG 50 // Branch target temporary register
354 /* instruction types */
355 #define NOP 0 // No operation
356 #define LOAD 1 // Load
357 #define STORE 2 // Store
358 #define LOADLR 3 // Unaligned load
359 #define STORELR 4 // Unaligned store
360 #define MOV 5 // Move (hi/lo only)
361 #define ALU 6 // Arithmetic/logic
362 #define MULTDIV 7 // Multiply/divide
363 #define SHIFT 8 // Shift by register
364 #define SHIFTIMM 9// Shift by immediate
365 #define IMM16 10 // 16-bit immediate
366 #define RJUMP 11 // Unconditional jump to register
367 #define UJUMP 12 // Unconditional jump
368 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
369 #define SJUMP 14 // Conditional branch (regimm format)
370 #define COP0 15 // Coprocessor 0
372 #define SYSCALL 22// SYSCALL,BREAK
373 #define OTHER 23 // Other/unknown - do nothing
374 #define HLECALL 26// PCSX fake opcodes for HLE
375 #define COP2 27 // Coprocessor 2 move
376 #define C2LS 28 // Coprocessor 2 load/store
377 #define C2OP 29 // Coprocessor 2 operation
378 #define INTCALL 30// Call interpreter to handle rare corner cases
385 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
386 #define DJT_2 (void *)2l
391 void jump_syscall (u_int u0, u_int u1, u_int pc);
392 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
393 void jump_break (u_int u0, u_int u1, u_int pc);
394 void jump_break_ds(u_int u0, u_int u1, u_int pc);
395 void jump_overflow (u_int u0, u_int u1, u_int pc);
396 void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
397 void jump_addrerror (u_int cause, u_int addr, u_int pc);
398 void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
399 void jump_to_new_pc();
400 void call_gteStall();
401 void new_dyna_leave();
403 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
404 void *ndrc_get_addr_ht(u_int vaddr);
405 void ndrc_add_jump_out(u_int vaddr, void *src);
406 void ndrc_write_invalidate_one(u_int addr);
407 static void ndrc_write_invalidate_many(u_int addr, u_int end);
409 static int new_recompile_block(u_int addr);
410 static void invalidate_block(struct block_info *block);
411 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
413 // Needed by assembler
414 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
415 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
416 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
417 static void load_all_regs(const signed char i_regmap[]);
418 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
419 static void load_regs_entry(int t);
420 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
421 static u_int get_host_reglist(const signed char *regmap);
423 static int get_final_value(int hr, int i, u_int *value);
424 static void add_stub(enum stub_type type, void *addr, void *retaddr,
425 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
426 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
427 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
428 static void add_to_linker(void *addr, u_int target, int ext);
429 static void *get_direct_memhandler(void *table, u_int addr,
430 enum stub_type type, uintptr_t *addr_host);
431 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
432 static void pass_args(int a0, int a1);
433 static void emit_far_jump(const void *f);
434 static void emit_far_call(const void *f);
437 #include <psp2/kernel/sysmem.h>
439 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
440 extern int getVMBlock();
441 int _newlib_vm_size_user = sizeof(*ndrc);
444 static void mprotect_w_x(void *start, void *end, int is_x)
448 // *Open* enables write on all memory that was
449 // allocated by sceKernelAllocMemBlockForVM()?
451 sceKernelCloseVMDomain();
453 sceKernelOpenVMDomain();
454 #elif defined(HAVE_LIBNX)
456 // check to avoid the full flush in jitTransitionToExecutable()
457 if (g_jit.type != JitType_CodeMemory) {
459 rc = jitTransitionToExecutable(&g_jit);
461 rc = jitTransitionToWritable(&g_jit);
463 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
465 #elif defined(TC_WRITE_OFFSET)
466 // separated rx and rw areas are always available
468 u_long mstart = (u_long)start & ~4095ul;
469 u_long mend = (u_long)end;
470 if (mprotect((void *)mstart, mend - mstart,
471 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
472 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
477 static void start_tcache_write(void *start, void *end)
479 mprotect_w_x(start, end, 0);
482 static void end_tcache_write(void *start, void *end)
484 #if defined(__arm__) || defined(__aarch64__)
485 size_t len = (char *)end - (char *)start;
486 #if defined(__BLACKBERRY_QNX__)
487 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
488 #elif defined(__MACH__)
489 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
491 sceKernelSyncVMDomain(sceBlock, start, len);
493 ctr_flush_invalidate_cache();
494 #elif defined(HAVE_LIBNX)
495 if (g_jit.type == JitType_CodeMemory) {
496 armDCacheClean(start, len);
497 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
498 // as of v4.2.1 libnx lacks isb
499 __asm__ volatile("isb" ::: "memory");
501 #elif defined(__aarch64__)
502 // as of 2021, __clear_cache() is still broken on arm64
503 // so here is a custom one :(
504 clear_cache_arm64(start, end);
506 __clear_cache(start, end);
511 mprotect_w_x(start, end, 1);
514 static void *start_block(void)
516 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
517 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
518 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
519 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
523 static void end_block(void *start)
525 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
528 #ifdef NDRC_CACHE_FLUSH_ALL
530 static int needs_clear_cache;
532 static void mark_clear_cache(void *target)
534 if (!needs_clear_cache) {
535 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
536 needs_clear_cache = 1;
540 static void do_clear_cache(void)
542 if (needs_clear_cache) {
543 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
544 needs_clear_cache = 0;
550 // also takes care of w^x mappings when patching code
551 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
553 static void mark_clear_cache(void *target)
555 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
556 u_int mask = 1u << ((offset >> 12) & 31);
557 if (!(needs_clear_cache[offset >> 17] & mask)) {
558 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
559 start_tcache_write(start, start + 4095);
560 needs_clear_cache[offset >> 17] |= mask;
564 // Clearing the cache is rather slow on ARM Linux, so mark the areas
565 // that need to be cleared, and then only clear these areas once.
566 static void do_clear_cache(void)
569 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
571 u_int bitmap = needs_clear_cache[i];
574 for (j = 0; j < 32; j++)
577 if (!(bitmap & (1u << j)))
580 start = ndrc->translation_cache + i*131072 + j*4096;
582 for (j++; j < 32; j++) {
583 if (!(bitmap & (1u << j)))
587 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
589 needs_clear_cache[i] = 0;
593 #endif // NDRC_CACHE_FLUSH_ALL
595 #define NO_CYCLE_PENALTY_THR 12
597 int cycle_multiplier_old;
598 static int cycle_multiplier_active;
600 static int CLOCK_ADJUST(int x)
602 int m = cycle_multiplier_active;
603 int s = (x >> 31) | 1;
604 return (x * m + s * 50) / 100;
607 static int ds_writes_rjump_rs(int i)
609 return dops[i].rs1 != 0
610 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
611 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
614 // psx addr mirror masking (for invalidation)
615 static u_int pmmask(u_int vaddr)
617 vaddr &= ~0xe0000000;
618 if (vaddr < 0x01000000)
619 vaddr &= ~0x00e00000; // RAM mirrors
623 static u_int get_page(u_int vaddr)
625 u_int page = pmmask(vaddr) >> 12;
626 if (page >= PAGE_COUNT / 2)
627 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
631 // get a page for looking for a block that has vaddr
632 // (needed because the block may start in previous page)
633 static u_int get_page_prev(u_int vaddr)
635 assert(MAXBLOCK <= (1 << 12));
636 u_int page = get_page(vaddr);
642 static struct ht_entry *hash_table_get(u_int vaddr)
644 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
647 static void hash_table_add(u_int vaddr, void *tcaddr)
649 struct ht_entry *ht_bin = hash_table_get(vaddr);
651 ht_bin->vaddr[1] = ht_bin->vaddr[0];
652 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
653 ht_bin->vaddr[0] = vaddr;
654 ht_bin->tcaddr[0] = tcaddr;
657 static void hash_table_remove(int vaddr)
659 //printf("remove hash: %x\n",vaddr);
660 struct ht_entry *ht_bin = hash_table_get(vaddr);
661 if (ht_bin->vaddr[1] == vaddr) {
662 ht_bin->vaddr[1] = -1;
663 ht_bin->tcaddr[1] = NULL;
665 if (ht_bin->vaddr[0] == vaddr) {
666 ht_bin->vaddr[0] = ht_bin->vaddr[1];
667 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
668 ht_bin->vaddr[1] = -1;
669 ht_bin->tcaddr[1] = NULL;
673 static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
675 u_int vaddr_m = vaddr & 0x1fffffff;
677 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
678 // ram mirrors, but should not hurt bios
679 for (j = 0; j < 0x800000; j += 0x200000) {
680 invalid_code[(i|j) >> 12] =
681 invalid_code[(i|j|0x80000000u) >> 12] =
682 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
685 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
686 inv_code_start = inv_code_end = ~0;
689 static int doesnt_expire_soon(u_char *tcaddr)
691 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
692 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
695 static unused void check_for_block_changes(u_int start, u_int end)
697 u_int start_page = get_page_prev(start);
698 u_int end_page = get_page(end - 1);
701 for (page = start_page; page <= end_page; page++) {
702 struct block_info *block;
703 for (block = blocks[page]; block != NULL; block = block->next) {
706 if (memcmp(block->source, block->copy, block->len)) {
707 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
708 block->start, block->start + block->len,
709 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
717 static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
719 void *found_clean = NULL;
722 stat_inc(stat_restore_tries);
723 for (page = start_page; page <= end_page; page++) {
724 struct block_info *block;
725 for (block = blocks[page]; block != NULL; block = block->next) {
726 if (vaddr < block->start)
728 if (!block->is_dirty || vaddr >= block->start + block->len)
730 for (i = 0; i < block->jump_in_cnt; i++)
731 if (block->jump_in[i].vaddr == vaddr)
733 if (i == block->jump_in_cnt)
735 assert(block->source && block->copy);
736 stat_inc(stat_restore_compares);
737 if (memcmp(block->source, block->copy, block->len))
740 block->is_dirty = block->inv_near_misses = 0;
741 found_clean = block->jump_in[i].addr;
742 hash_table_add(vaddr, found_clean);
743 mark_invalid_code(block->start, block->len, 0);
744 stat_inc(stat_bc_restore);
745 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
752 // this doesn't normally happen
753 static noinline u_int generate_exception(u_int pc)
755 //if (execBreakCheck(&psxRegs, pc))
756 // return psxRegs.pc;
758 // generate an address or bus error
759 psxRegs.CP0.n.Cause &= 0x300;
760 psxRegs.CP0.n.EPC = pc;
762 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
763 psxRegs.CP0.n.BadVAddr = pc;
768 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
769 return (psxRegs.pc = 0x80000080);
772 // Get address from virtual address
773 // This is called from the recompiled JR/JALR instructions
774 static void noinline *get_addr(u_int vaddr, int can_compile)
776 u_int start_page = get_page_prev(vaddr);
777 u_int i, page, end_page = get_page(vaddr);
778 void *found_clean = NULL;
780 stat_inc(stat_jump_in_lookups);
781 for (page = start_page; page <= end_page; page++) {
782 const struct block_info *block;
783 for (block = blocks[page]; block != NULL; block = block->next) {
784 if (vaddr < block->start)
786 if (block->is_dirty || vaddr >= block->start + block->len)
788 for (i = 0; i < block->jump_in_cnt; i++)
789 if (block->jump_in[i].vaddr == vaddr)
791 if (i == block->jump_in_cnt)
793 found_clean = block->jump_in[i].addr;
794 hash_table_add(vaddr, found_clean);
798 found_clean = try_restore_block(vaddr, start_page, end_page);
805 int r = new_recompile_block(vaddr);
807 return ndrc_get_addr_ht(vaddr);
809 return ndrc_get_addr_ht(generate_exception(vaddr));
812 // Look up address in hash table first
813 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
815 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
816 const struct ht_entry *ht_bin = hash_table_get(vaddr);
817 u_int vaddr_a = vaddr & ~3;
818 stat_inc(stat_ht_lookups);
819 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
820 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
821 return get_addr(vaddr, can_compile);
824 void *ndrc_get_addr_ht(u_int vaddr)
826 return ndrc_get_addr_ht_param(vaddr, 1);
829 static void clear_all_regs(signed char regmap[])
831 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
834 // get_reg: get allocated host reg from mips reg
835 // returns -1 if no such mips reg was allocated
836 #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
838 extern signed char get_reg(const signed char regmap[], signed char r);
842 static signed char get_reg(const signed char regmap[], signed char r)
845 for (hr = 0; hr < HOST_REGS; hr++) {
846 if (hr == EXCLUDE_REG)
856 // get reg suitable for writing
857 static signed char get_reg_w(const signed char regmap[], signed char r)
859 return r == 0 ? -1 : get_reg(regmap, r);
862 // get reg as mask bit (1 << hr)
863 static u_int get_regm(const signed char regmap[], signed char r)
865 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
868 static signed char get_reg_temp(const signed char regmap[])
871 for (hr = 0; hr < HOST_REGS; hr++) {
872 if (hr == EXCLUDE_REG)
874 if (regmap[hr] == (signed char)-1)
880 // Find a register that is available for two consecutive cycles
881 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
884 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
888 // reverse reg map: mips -> host
889 #define RRMAP_SIZE 64
890 static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
891 u_int *regs_can_change)
893 u_int r, hr, hr_can_change = 0;
894 memset(rrmap, -1, RRMAP_SIZE);
895 for (hr = 0; hr < HOST_REGS; )
898 rrmap[r & (RRMAP_SIZE - 1)] = hr;
899 // only add mips $1-$31+$lo, others shifted out
900 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
902 if (hr == EXCLUDE_REG)
905 hr_can_change |= 1u << (rrmap[33] & 31);
906 hr_can_change |= 1u << (rrmap[CCREG] & 31);
907 hr_can_change &= ~(1u << 31);
908 *regs_can_change = hr_can_change;
911 // same as get_reg, but takes rrmap
912 static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
914 assert(0 <= r && r < RRMAP_SIZE);
918 static int count_free_regs(const signed char regmap[])
922 for(hr=0;hr<HOST_REGS;hr++)
924 if(hr!=EXCLUDE_REG) {
925 if(regmap[hr]<0) count++;
931 static void dirty_reg(struct regstat *cur, signed char reg)
935 hr = get_reg(cur->regmap, reg);
940 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
944 hr = get_reg(cur->regmap, reg);
946 cur->isconst |= 1<<hr;
947 current_constmap[hr] = value;
951 static void clear_const(struct regstat *cur, signed char reg)
955 hr = get_reg(cur->regmap, reg);
957 cur->isconst &= ~(1<<hr);
960 static int is_const(const struct regstat *cur, signed char reg)
963 if (reg < 0) return 0;
965 hr = get_reg(cur->regmap, reg);
967 return (cur->isconst>>hr)&1;
971 static uint32_t get_const(const struct regstat *cur, signed char reg)
975 hr = get_reg(cur->regmap, reg);
977 return current_constmap[hr];
979 SysPrintf("Unknown constant in r%d\n", reg);
983 // Least soon needed registers
984 // Look at the next ten instructions and see which registers
985 // will be used. Try not to reallocate these.
986 static void lsn(u_char hsn[], int i)
996 if (dops[i+j].is_ujump)
998 // Don't go past an unconditonal jump
1005 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1006 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1007 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1008 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1009 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
1010 // Stores can allocate zero
1011 hsn[dops[i+j].rs1]=j;
1012 hsn[dops[i+j].rs2]=j;
1014 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1016 // On some architectures stores need invc_ptr
1017 #if defined(HOST_IMM8)
1018 if (dops[i+j].is_store)
1021 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1029 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
1031 // Follow first branch
1032 int t=(cinfo[i+b].ba-start)>>2;
1033 j=7-b;if(t+j>=slen) j=slen-t-1;
1036 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1037 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1038 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1039 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
1042 // TODO: preferred register based on backward branch
1044 // Delay slot should preferably not overwrite branch conditions or cycle count
1045 if (i > 0 && dops[i-1].is_jump) {
1046 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1047 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1049 // ...or hash tables
1053 // Coprocessor load/store needs FTEMP, even if not declared
1054 if(dops[i].itype==C2LS) {
1057 // Load L/R also uses FTEMP as a temporary register
1058 if(dops[i].itype==LOADLR) {
1061 // Also SWL/SWR/SDL/SDR
1062 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
1065 // Don't remove the miniht registers
1066 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1073 // We only want to allocate registers if we're going to use them again soon
1074 static int needed_again(int r, int i)
1080 if (i > 0 && dops[i-1].is_ujump)
1082 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
1083 return 0; // Don't need any registers if exiting the block
1091 if (dops[i+j].is_ujump)
1093 // Don't go past an unconditonal jump
1097 if (dops[i+j].is_exception)
1104 if(dops[i+j].rs1==r) rn=j;
1105 if(dops[i+j].rs2==r) rn=j;
1106 if((unneeded_reg[i+j]>>r)&1) rn=10;
1107 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1117 // Try to match register allocations at the end of a loop with those
1119 static int loop_reg(int i, int r, int hr)
1128 if (dops[i+j].is_ujump)
1130 // Don't go past an unconditonal jump
1137 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1143 if((unneeded_reg[i+k]>>r)&1) return hr;
1144 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1146 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
1148 int t=(cinfo[i+k].ba-start)>>2;
1149 int reg=get_reg(regs[t].regmap_entry,r);
1150 if(reg>=0) return reg;
1151 //reg=get_reg(regs[t+1].regmap_entry,r);
1152 //if(reg>=0) return reg;
1160 // Allocate every register, preserving source/target regs
1161 static void alloc_all(struct regstat *cur,int i)
1165 for(hr=0;hr<HOST_REGS;hr++) {
1166 if(hr!=EXCLUDE_REG) {
1167 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1168 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1171 cur->dirty&=~(1<<hr);
1174 if(cur->regmap[hr]==0)
1177 cur->dirty&=~(1<<hr);
1184 static int host_tempreg_in_use;
1186 static void host_tempreg_acquire(void)
1188 assert(!host_tempreg_in_use);
1189 host_tempreg_in_use = 1;
1192 static void host_tempreg_release(void)
1194 host_tempreg_in_use = 0;
1197 static void host_tempreg_acquire(void) {}
1198 static void host_tempreg_release(void) {}
1202 extern void gen_interupt();
1203 extern void do_insn_cmp();
1204 #define FUNCNAME(f) { f, " " #f }
1205 static const struct {
1208 } function_names[] = {
1209 FUNCNAME(cc_interrupt),
1210 FUNCNAME(gen_interupt),
1211 FUNCNAME(ndrc_get_addr_ht),
1212 FUNCNAME(jump_handler_read8),
1213 FUNCNAME(jump_handler_read16),
1214 FUNCNAME(jump_handler_read32),
1215 FUNCNAME(jump_handler_write8),
1216 FUNCNAME(jump_handler_write16),
1217 FUNCNAME(jump_handler_write32),
1218 FUNCNAME(ndrc_write_invalidate_one),
1219 FUNCNAME(ndrc_write_invalidate_many),
1220 FUNCNAME(jump_to_new_pc),
1221 FUNCNAME(jump_break),
1222 FUNCNAME(jump_break_ds),
1223 FUNCNAME(jump_syscall),
1224 FUNCNAME(jump_syscall_ds),
1225 FUNCNAME(jump_overflow),
1226 FUNCNAME(jump_overflow_ds),
1227 FUNCNAME(jump_addrerror),
1228 FUNCNAME(jump_addrerror_ds),
1229 FUNCNAME(call_gteStall),
1230 FUNCNAME(new_dyna_leave),
1231 FUNCNAME(pcsx_mtc0),
1232 FUNCNAME(pcsx_mtc0_ds),
1235 FUNCNAME(do_memhandler_pre),
1236 FUNCNAME(do_memhandler_post),
1239 FUNCNAME(do_insn_cmp),
1243 static const char *func_name(const void *a)
1246 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1247 if (function_names[i].addr == a)
1248 return function_names[i].name;
1252 static const char *fpofs_name(u_int ofs)
1254 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1255 static char buf[64];
1257 #define ofscase(x) case LO_##x: return " ; " #x
1258 ofscase(next_interupt);
1259 ofscase(cycle_count);
1260 ofscase(last_count);
1261 ofscase(pending_exception);
1272 ofscase(ram_offset);
1276 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1277 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1278 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1279 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1280 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1281 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1282 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1283 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1287 #define func_name(x) ""
1288 #define fpofs_name(x) ""
1292 #include "assem_x86.c"
1295 #include "assem_x64.c"
1298 #include "assem_arm.c"
1301 #include "assem_arm64.c"
1304 static void *get_trampoline(const void *f)
1306 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1309 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1310 if (tramp->f[i] == f || tramp->f[i] == NULL)
1313 if (i == ARRAY_SIZE(tramp->f)) {
1314 SysPrintf("trampoline table is full, last func %p\n", f);
1317 if (tramp->f[i] == NULL) {
1318 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1320 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1322 // invalidate the RX mirror (unsure if necessary, but just in case...)
1323 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1326 return &ndrc->tramp.ops[i];
1329 static void emit_far_jump(const void *f)
1331 if (can_jump_or_call(f)) {
1336 f = get_trampoline(f);
1340 static void emit_far_call(const void *f)
1342 if (can_jump_or_call(f)) {
1347 f = get_trampoline(f);
1351 // Check if an address is already compiled
1352 // but don't return addresses which are about to expire from the cache
1353 static void *check_addr(u_int vaddr)
1355 struct ht_entry *ht_bin = hash_table_get(vaddr);
1357 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1358 if (ht_bin->vaddr[i] == vaddr)
1359 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1360 return ht_bin->tcaddr[i];
1363 // refactor to get_addr_nocompile?
1364 u_int start_page = get_page_prev(vaddr);
1365 u_int page, end_page = get_page(vaddr);
1367 stat_inc(stat_jump_in_lookups);
1368 for (page = start_page; page <= end_page; page++) {
1369 const struct block_info *block;
1370 for (block = blocks[page]; block != NULL; block = block->next) {
1371 if (vaddr < block->start)
1373 if (block->is_dirty || vaddr >= block->start + block->len)
1375 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1377 for (i = 0; i < block->jump_in_cnt; i++)
1378 if (block->jump_in[i].vaddr == vaddr)
1380 if (i == block->jump_in_cnt)
1383 // Update existing entry with current address
1384 void *addr = block->jump_in[i].addr;
1385 if (ht_bin->vaddr[0] == vaddr) {
1386 ht_bin->tcaddr[0] = addr;
1389 if (ht_bin->vaddr[1] == vaddr) {
1390 ht_bin->tcaddr[1] = addr;
1393 // Insert into hash table with low priority.
1394 // Don't evict existing entries, as they are probably
1395 // addresses that are being accessed frequently.
1396 if (ht_bin->vaddr[0] == -1) {
1397 ht_bin->vaddr[0] = vaddr;
1398 ht_bin->tcaddr[0] = addr;
1400 else if (ht_bin->vaddr[1] == -1) {
1401 ht_bin->vaddr[1] = vaddr;
1402 ht_bin->tcaddr[1] = addr;
1410 static void blocks_clear(struct block_info **head)
1412 struct block_info *cur, *next;
1414 if ((cur = *head)) {
1424 static int blocks_remove_matching_addrs(struct block_info **head,
1425 u_int base_offs, int shift)
1427 struct block_info *next;
1430 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1431 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
1432 invalidate_block(*head);
1433 next = (*head)->next;
1436 stat_dec(stat_blocks);
1441 head = &((*head)->next);
1447 // This is called when we write to a compiled block (see do_invstub)
1448 static void unlink_jumps_vaddr_range(u_int start, u_int end)
1450 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1453 for (page = start_page; page <= end_page; page++) {
1454 struct jump_info *ji = jumps[page];
1457 for (i = 0; i < ji->count; ) {
1458 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1463 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1464 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1465 void *host_addr = find_extjump_insn(ji->e[i].stub);
1466 mark_clear_cache(host_addr);
1467 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1469 stat_dec(stat_links);
1471 if (i < ji->count) {
1472 ji->e[i] = ji->e[ji->count];
1480 static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1485 for (i = 0; i < ji->count; ) {
1486 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1487 if (((tc_offs ^ base_offs) >> shift) != 0) {
1492 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
1493 stat_dec(stat_links);
1495 if (i < ji->count) {
1496 ji->e[i] = ji->e[ji->count];
1503 static void invalidate_block(struct block_info *block)
1507 block->is_dirty = 1;
1508 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1509 for (i = 0; i < block->jump_in_cnt; i++)
1510 hash_table_remove(block->jump_in[i].vaddr);
1513 static int invalidate_range(u_int start, u_int end,
1514 u32 *inv_start_ret, u32 *inv_end_ret)
1516 struct block_info *last_block = NULL;
1517 u_int start_page = get_page_prev(start);
1518 u_int end_page = get_page(end - 1);
1519 u_int start_m = pmmask(start);
1520 u_int end_m = pmmask(end - 1);
1521 u_int inv_start, inv_end;
1522 u_int blk_start_m, blk_end_m;
1526 // additional area without code (to supplement invalid_code[]), [start, end)
1527 // avoids excessive ndrc_write_invalidate*() calls
1528 inv_start = start_m & ~0xfff;
1529 inv_end = end_m | 0xfff;
1531 for (page = start_page; page <= end_page; page++) {
1532 struct block_info *block;
1533 for (block = blocks[page]; block != NULL; block = block->next) {
1534 if (block->is_dirty)
1537 blk_end_m = pmmask(block->start + block->len);
1538 if (blk_end_m <= start_m) {
1539 inv_start = max(inv_start, blk_end_m);
1542 blk_start_m = pmmask(block->start);
1543 if (end_m <= blk_start_m) {
1544 inv_end = min(inv_end, blk_start_m - 1);
1547 if (!block->source) // "hack" block - leave it alone
1551 invalidate_block(block);
1552 stat_inc(stat_inv_hits);
1556 if (!hit && last_block && last_block->source) {
1557 // could be some leftover unused block, uselessly trapping writes
1558 last_block->inv_near_misses++;
1559 if (last_block->inv_near_misses > 128) {
1560 invalidate_block(last_block);
1561 stat_inc(stat_inv_hits);
1568 memset(mini_ht, -1, sizeof(mini_ht));
1572 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1573 // the whole page is empty now
1574 mark_invalid_code(start, 1, 1);
1576 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1577 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1581 void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1583 invalidate_range(start, end, NULL, NULL);
1586 static void ndrc_write_invalidate_many(u_int start, u_int end)
1588 // this check is done by the caller
1589 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1590 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1592 int invc = invalid_code[start >> 12];
1593 u_int len = end - start;
1595 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
1597 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1598 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1599 check_for_block_changes(start, end);
1601 stat_inc(stat_inv_addr_calls);
1605 void ndrc_write_invalidate_one(u_int addr)
1607 ndrc_write_invalidate_many(addr, addr + 4);
1610 // This is called when loading a save state.
1611 // Anything could have changed, so invalidate everything.
1612 void new_dynarec_invalidate_all_pages(void)
1614 struct block_info *block;
1616 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1617 for (block = blocks[page]; block != NULL; block = block->next) {
1618 if (block->is_dirty)
1620 if (!block->source) // hack block?
1622 invalidate_block(block);
1627 memset(mini_ht, -1, sizeof(mini_ht));
1632 // Add an entry to jump_out after making a link
1633 // src should point to code by emit_extjump()
1634 void ndrc_add_jump_out(u_int vaddr, void *src)
1636 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1637 u_int page = get_page(vaddr);
1638 struct jump_info *ji;
1640 stat_inc(stat_links);
1641 check_extjump2(src);
1644 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1648 else if (ji->count >= ji->alloc) {
1650 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1653 ji->e[ji->count].target_vaddr = vaddr;
1654 ji->e[ji->count].stub = src;
1658 /* Register allocation */
1660 static void alloc_set(struct regstat *cur, int reg, int hr)
1662 cur->regmap[hr] = reg;
1663 cur->dirty &= ~(1u << hr);
1664 cur->isconst &= ~(1u << hr);
1665 cur->noevict |= 1u << hr;
1668 static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1670 u_char hsn[MAXREG+1];
1672 memset(hsn, 10, sizeof(hsn));
1674 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1676 // Don't evict the cycle count at entry points, otherwise the entry
1677 // stub will have to write it.
1678 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1679 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1682 // Alloc preferred register if available
1683 if (!((cur->noevict >> preferred_hr) & 1)
1684 && hsn[cur->regmap[preferred_hr]] == j)
1686 alloc_set(cur, reg, preferred_hr);
1689 for(r=1;r<=MAXREG;r++)
1691 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1692 for(hr=0;hr<HOST_REGS;hr++) {
1693 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1695 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1696 if(cur->regmap[hr]==r) {
1697 alloc_set(cur, reg, hr);
1708 for(r=1;r<=MAXREG;r++)
1711 for(hr=0;hr<HOST_REGS;hr++) {
1712 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1714 if(cur->regmap[hr]==r) {
1715 alloc_set(cur, reg, hr);
1722 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1726 // Note: registers are allocated clean (unmodified state)
1727 // if you intend to modify the register, you must call dirty_reg().
1728 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1731 int preferred_reg = PREFERRED_REG_FIRST
1732 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1733 if (reg == CCREG) preferred_reg = HOST_CCREG;
1734 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1735 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1738 // Don't allocate unused registers
1739 if((cur->u>>reg)&1) return;
1741 // see if it's already allocated
1742 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1743 cur->noevict |= 1u << hr;
1747 // Keep the same mapping if the register was already allocated in a loop
1748 preferred_reg = loop_reg(i,reg,preferred_reg);
1750 // Try to allocate the preferred register
1751 if (cur->regmap[preferred_reg] == -1) {
1752 alloc_set(cur, reg, preferred_reg);
1755 r=cur->regmap[preferred_reg];
1758 alloc_set(cur, reg, preferred_reg);
1762 // Clear any unneeded registers
1763 // We try to keep the mapping consistent, if possible, because it
1764 // makes branches easier (especially loops). So we try to allocate
1765 // first (see above) before removing old mappings. If this is not
1766 // possible then go ahead and clear out the registers that are no
1768 for(hr=0;hr<HOST_REGS;hr++)
1773 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1777 // Try to allocate any available register, but prefer
1778 // registers that have not been used recently.
1780 for (hr = PREFERRED_REG_FIRST; ; ) {
1781 if (cur->regmap[hr] < 0) {
1782 int oldreg = regs[i-1].regmap[hr];
1783 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1784 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1786 alloc_set(cur, reg, hr);
1791 if (hr == EXCLUDE_REG)
1793 if (hr == HOST_REGS)
1795 if (hr == PREFERRED_REG_FIRST)
1800 // Try to allocate any available register
1801 for (hr = PREFERRED_REG_FIRST; ; ) {
1802 if (cur->regmap[hr] < 0) {
1803 alloc_set(cur, reg, hr);
1807 if (hr == EXCLUDE_REG)
1809 if (hr == HOST_REGS)
1811 if (hr == PREFERRED_REG_FIRST)
1815 // Ok, now we have to evict someone
1816 // Pick a register we hopefully won't need soon
1817 evict_alloc_reg(cur, i, reg, preferred_reg);
1820 // Allocate a temporary register. This is done without regard to
1821 // dirty status or whether the register we request is on the unneeded list
1822 // Note: This will only allocate one register, even if called multiple times
1823 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1827 // see if it's already allocated
1828 for (hr = 0; hr < HOST_REGS; hr++)
1830 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1831 cur->noevict |= 1u << hr;
1836 // Try to allocate any available register
1837 for(hr=HOST_REGS-1;hr>=0;hr--) {
1838 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1839 alloc_set(cur, reg, hr);
1844 // Find an unneeded register
1845 for(hr=HOST_REGS-1;hr>=0;hr--)
1851 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1852 alloc_set(cur, reg, hr);
1859 // Ok, now we have to evict someone
1860 // Pick a register we hopefully won't need soon
1861 evict_alloc_reg(cur, i, reg, 0);
1864 static void mov_alloc(struct regstat *current,int i)
1866 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1867 alloc_cc(current,i); // for stalls
1868 dirty_reg(current,CCREG);
1871 // Note: Don't need to actually alloc the source registers
1872 //alloc_reg(current,i,dops[i].rs1);
1873 alloc_reg(current,i,dops[i].rt1);
1875 clear_const(current,dops[i].rs1);
1876 clear_const(current,dops[i].rt1);
1877 dirty_reg(current,dops[i].rt1);
1880 static void shiftimm_alloc(struct regstat *current,int i)
1882 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1885 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1886 else dops[i].use_lt1=!!dops[i].rs1;
1887 alloc_reg(current,i,dops[i].rt1);
1888 dirty_reg(current,dops[i].rt1);
1889 if(is_const(current,dops[i].rs1)) {
1890 int v=get_const(current,dops[i].rs1);
1891 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1892 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1893 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
1895 else clear_const(current,dops[i].rt1);
1900 clear_const(current,dops[i].rs1);
1901 clear_const(current,dops[i].rt1);
1904 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1908 if(dops[i].opcode2==0x3c) // DSLL32
1912 if(dops[i].opcode2==0x3e) // DSRL32
1916 if(dops[i].opcode2==0x3f) // DSRA32
1922 static void shift_alloc(struct regstat *current,int i)
1925 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1926 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1927 alloc_reg(current,i,dops[i].rt1);
1928 if(dops[i].rt1==dops[i].rs2) {
1929 alloc_reg_temp(current,i,-1);
1930 cinfo[i].min_free_regs=1;
1932 clear_const(current,dops[i].rs1);
1933 clear_const(current,dops[i].rs2);
1934 clear_const(current,dops[i].rt1);
1935 dirty_reg(current,dops[i].rt1);
1939 static void alu_alloc(struct regstat *current,int i)
1941 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1943 if(dops[i].rs1&&dops[i].rs2) {
1944 alloc_reg(current,i,dops[i].rs1);
1945 alloc_reg(current,i,dops[i].rs2);
1948 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1949 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1951 alloc_reg(current,i,dops[i].rt1);
1953 if (dops[i].may_except) {
1954 alloc_cc_optional(current, i); // for exceptions
1955 alloc_reg_temp(current, i, -1);
1956 cinfo[i].min_free_regs = 1;
1959 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1961 alloc_reg(current,i,dops[i].rs1);
1962 alloc_reg(current,i,dops[i].rs2);
1963 alloc_reg(current,i,dops[i].rt1);
1966 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1968 if(dops[i].rs1&&dops[i].rs2) {
1969 alloc_reg(current,i,dops[i].rs1);
1970 alloc_reg(current,i,dops[i].rs2);
1974 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1975 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1977 alloc_reg(current,i,dops[i].rt1);
1980 clear_const(current,dops[i].rs1);
1981 clear_const(current,dops[i].rs2);
1982 clear_const(current,dops[i].rt1);
1983 dirty_reg(current,dops[i].rt1);
1986 static void imm16_alloc(struct regstat *current,int i)
1988 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1989 else dops[i].use_lt1=!!dops[i].rs1;
1990 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1991 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1992 clear_const(current,dops[i].rs1);
1993 clear_const(current,dops[i].rt1);
1995 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1996 if(is_const(current,dops[i].rs1)) {
1997 int v=get_const(current,dops[i].rs1);
1998 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
1999 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2000 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
2002 else clear_const(current,dops[i].rt1);
2004 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2005 if(is_const(current,dops[i].rs1)) {
2006 int v=get_const(current,dops[i].rs1);
2007 set_const(current,dops[i].rt1,v+cinfo[i].imm);
2009 else clear_const(current,dops[i].rt1);
2010 if (dops[i].may_except) {
2011 alloc_cc_optional(current, i); // for exceptions
2012 alloc_reg_temp(current, i, -1);
2013 cinfo[i].min_free_regs = 1;
2017 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
2019 dirty_reg(current,dops[i].rt1);
2022 static void load_alloc(struct regstat *current,int i)
2025 clear_const(current,dops[i].rt1);
2026 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2027 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
2028 if (needed_again(dops[i].rs1, i))
2029 alloc_reg(current, i, dops[i].rs1);
2031 alloc_reg(current, i, ROREG);
2032 if (dops[i].may_except) {
2033 alloc_cc_optional(current, i); // for exceptions
2036 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2037 alloc_reg(current,i,dops[i].rt1);
2038 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
2039 dirty_reg(current,dops[i].rt1);
2040 // LWL/LWR need a temporary register for the old value
2041 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2043 alloc_reg(current,i,FTEMP);
2049 // Load to r0 or unneeded register (dummy load)
2050 // but we still need a register to calculate the address
2051 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2052 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2056 alloc_reg_temp(current, i, -1);
2057 cinfo[i].min_free_regs = 1;
2061 // this may eat up to 7 registers
2062 static void store_alloc(struct regstat *current, int i)
2064 clear_const(current,dops[i].rs2);
2065 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2066 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2067 alloc_reg(current,i,dops[i].rs2);
2069 alloc_reg(current, i, ROREG);
2070 #if defined(HOST_IMM8)
2071 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2072 alloc_reg(current, i, INVCP);
2074 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
2075 alloc_reg(current,i,FTEMP);
2077 if (dops[i].may_except)
2078 alloc_cc_optional(current, i); // for exceptions
2079 // We need a temporary register for address generation
2080 alloc_reg_temp(current,i,-1);
2081 cinfo[i].min_free_regs=1;
2084 static void c2ls_alloc(struct regstat *current, int i)
2086 clear_const(current,dops[i].rt1);
2087 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2088 alloc_reg(current,i,FTEMP);
2090 alloc_reg(current, i, ROREG);
2091 #if defined(HOST_IMM8)
2092 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2093 if (dops[i].opcode == 0x3a) // SWC2
2094 alloc_reg(current,i,INVCP);
2096 if (dops[i].may_except)
2097 alloc_cc_optional(current, i); // for exceptions
2098 // We need a temporary register for address generation
2099 alloc_reg_temp(current,i,-1);
2100 cinfo[i].min_free_regs=1;
2103 #ifndef multdiv_alloc
2104 static void multdiv_alloc(struct regstat *current,int i)
2110 clear_const(current,dops[i].rs1);
2111 clear_const(current,dops[i].rs2);
2112 alloc_cc(current,i); // for stalls
2113 dirty_reg(current,CCREG);
2114 if(dops[i].rs1&&dops[i].rs2)
2116 current->u&=~(1LL<<HIREG);
2117 current->u&=~(1LL<<LOREG);
2118 alloc_reg(current,i,HIREG);
2119 alloc_reg(current,i,LOREG);
2120 alloc_reg(current,i,dops[i].rs1);
2121 alloc_reg(current,i,dops[i].rs2);
2122 dirty_reg(current,HIREG);
2123 dirty_reg(current,LOREG);
2127 // Multiply by zero is zero.
2128 // MIPS does not have a divide by zero exception.
2129 alloc_reg(current,i,HIREG);
2130 alloc_reg(current,i,LOREG);
2131 dirty_reg(current,HIREG);
2132 dirty_reg(current,LOREG);
2133 if (dops[i].rs1 && ((dops[i].opcode2 & 0x3e) == 0x1a)) // div(u) 0
2134 alloc_reg(current, i, dops[i].rs1);
2139 static void cop0_alloc(struct regstat *current,int i)
2141 if(dops[i].opcode2==0) // MFC0
2144 clear_const(current,dops[i].rt1);
2145 alloc_reg(current,i,dops[i].rt1);
2146 dirty_reg(current,dops[i].rt1);
2149 else if(dops[i].opcode2==4) // MTC0
2151 if (((source[i]>>11)&0x1e) == 12) {
2152 alloc_cc(current, i);
2153 dirty_reg(current, CCREG);
2156 clear_const(current,dops[i].rs1);
2157 alloc_reg(current,i,dops[i].rs1);
2158 alloc_all(current,i);
2161 alloc_all(current,i); // FIXME: Keep r0
2163 alloc_reg(current,i,0);
2165 cinfo[i].min_free_regs = HOST_REGS;
2169 static void rfe_alloc(struct regstat *current, int i)
2171 alloc_all(current, i);
2172 cinfo[i].min_free_regs = HOST_REGS;
2175 static void cop2_alloc(struct regstat *current,int i)
2177 if (dops[i].opcode2 < 3) // MFC2/CFC2
2179 alloc_cc(current,i); // for stalls
2180 dirty_reg(current,CCREG);
2182 clear_const(current,dops[i].rt1);
2183 alloc_reg(current,i,dops[i].rt1);
2184 dirty_reg(current,dops[i].rt1);
2187 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2190 clear_const(current,dops[i].rs1);
2191 alloc_reg(current,i,dops[i].rs1);
2195 alloc_reg(current,i,0);
2198 alloc_reg_temp(current,i,-1);
2199 cinfo[i].min_free_regs=1;
2202 static void c2op_alloc(struct regstat *current,int i)
2204 alloc_cc(current,i); // for stalls
2205 dirty_reg(current,CCREG);
2206 alloc_reg_temp(current,i,-1);
2209 static void syscall_alloc(struct regstat *current,int i)
2211 alloc_cc(current,i);
2212 dirty_reg(current,CCREG);
2213 alloc_all(current,i);
2214 cinfo[i].min_free_regs=HOST_REGS;
2218 static void delayslot_alloc(struct regstat *current,int i)
2220 switch(dops[i].itype) {
2228 imm16_alloc(current,i);
2232 load_alloc(current,i);
2236 store_alloc(current,i);
2239 alu_alloc(current,i);
2242 shift_alloc(current,i);
2245 multdiv_alloc(current,i);
2248 shiftimm_alloc(current,i);
2251 mov_alloc(current,i);
2254 cop0_alloc(current,i);
2257 rfe_alloc(current,i);
2260 cop2_alloc(current,i);
2263 c2ls_alloc(current,i);
2266 c2op_alloc(current,i);
2271 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2272 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2274 assert(stubcount < ARRAY_SIZE(stubs));
2275 stubs[stubcount].type = type;
2276 stubs[stubcount].addr = addr;
2277 stubs[stubcount].retaddr = retaddr;
2278 stubs[stubcount].a = a;
2279 stubs[stubcount].b = b;
2280 stubs[stubcount].c = c;
2281 stubs[stubcount].d = d;
2282 stubs[stubcount].e = e;
2286 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2287 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2289 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2292 // Write out a single register
2293 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2296 for(hr=0;hr<HOST_REGS;hr++) {
2297 if(hr!=EXCLUDE_REG) {
2300 assert(regmap[hr]<64);
2301 emit_storereg(r,hr);
2308 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2310 //if(dirty_pre==dirty) return;
2312 for (hr = 0; hr < HOST_REGS; hr++) {
2314 if (r < 1 || r > 33 || ((u >> r) & 1))
2316 if (((dirty_pre & ~dirty) >> hr) & 1)
2317 emit_storereg(r, hr);
2322 static void pass_args(int a0, int a1)
2326 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2328 else if(a0!=0&&a1==0) {
2330 if (a0>=0) emit_mov(a0,0);
2333 if(a0>=0&&a0!=0) emit_mov(a0,0);
2334 if(a1>=0&&a1!=1) emit_mov(a1,1);
2338 static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
2340 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2341 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2342 if (dops[i].rt1 || do_oflow) {
2343 int do_exception_check = 0;
2344 signed char s1, s2, t, tmp;
2345 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2346 tmp = get_reg_temp(i_regs->regmap);
2349 if (t < 0 && do_oflow)
2352 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2353 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2354 if (dops[i].rs1 && dops[i].rs2) {
2357 if (dops[i].opcode2 & 2) {
2359 emit_subs(s1, s2, tmp);
2360 do_exception_check = 1;
2367 emit_adds(s1, s2, tmp);
2368 do_exception_check = 1;
2374 else if(dops[i].rs1) {
2375 if(s1>=0) emit_mov(s1,t);
2376 else emit_loadreg(dops[i].rs1,t);
2378 else if(dops[i].rs2) {
2380 emit_loadreg(dops[i].rs2, t);
2383 if (dops[i].opcode2 & 2) {
2386 do_exception_check = 1;
2397 if (do_exception_check) {
2400 if (t >= 0 && tmp != t)
2402 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2406 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2408 signed char s1l,s2l,t;
2410 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2413 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2414 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2415 if(dops[i].rs2==0) // rx<r0
2417 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2419 emit_shrimm(s1l,31,t);
2421 else // SLTU (unsigned can not be less than zero, 0<0)
2424 else if(dops[i].rs1==0) // r0<rx
2427 if(dops[i].opcode2==0x2a) // SLT
2428 emit_set_gz32(s2l,t);
2429 else // SLTU (set if not zero)
2430 emit_set_nz32(s2l,t);
2433 assert(s1l>=0);assert(s2l>=0);
2434 if(dops[i].opcode2==0x2a) // SLT
2435 emit_set_if_less32(s1l,s2l,t);
2437 emit_set_if_carry32(s1l,s2l,t);
2443 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2445 signed char s1l,s2l,tl;
2446 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2449 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2450 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2451 if(dops[i].rs1&&dops[i].rs2) {
2454 if(dops[i].opcode2==0x24) { // AND
2455 emit_and(s1l,s2l,tl);
2457 if(dops[i].opcode2==0x25) { // OR
2458 emit_or(s1l,s2l,tl);
2460 if(dops[i].opcode2==0x26) { // XOR
2461 emit_xor(s1l,s2l,tl);
2463 if(dops[i].opcode2==0x27) { // NOR
2464 emit_or(s1l,s2l,tl);
2470 if(dops[i].opcode2==0x24) { // AND
2473 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2475 if(s1l>=0) emit_mov(s1l,tl);
2476 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2480 if(s2l>=0) emit_mov(s2l,tl);
2481 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2483 else emit_zeroreg(tl);
2485 if(dops[i].opcode2==0x27) { // NOR
2487 if(s1l>=0) emit_not(s1l,tl);
2489 emit_loadreg(dops[i].rs1,tl);
2495 if(s2l>=0) emit_not(s2l,tl);
2497 emit_loadreg(dops[i].rs2,tl);
2501 else emit_movimm(-1,tl);
2510 static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
2512 if (dops[i].opcode==0x0f) { // LUI
2515 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2518 if(!((i_regs->isconst>>t)&1))
2519 emit_movimm(cinfo[i].imm<<16,t);
2523 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2524 int is_addi = dops[i].may_except;
2525 if (dops[i].rt1 || is_addi) {
2526 signed char s, t, tmp;
2527 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2528 s=get_reg(i_regs->regmap,dops[i].rs1);
2530 tmp = get_reg_temp(i_regs->regmap);
2536 if(!((i_regs->isconst>>t)&1)) {
2537 int sum, do_exception_check = 0;
2539 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2541 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
2542 do_exception_check = 1;
2545 emit_addimm(t, cinfo[i].imm, t);
2547 if (!((i_regs->wasconst >> s) & 1)) {
2549 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
2550 do_exception_check = 1;
2553 emit_addimm(s, cinfo[i].imm, t);
2556 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
2557 if (is_addi && oflow)
2558 do_exception_check = 2;
2560 emit_movimm(sum, t);
2563 if (do_exception_check) {
2565 if (do_exception_check == 2)
2572 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2578 if(!((i_regs->isconst>>t)&1))
2579 emit_movimm(cinfo[i].imm,t);
2584 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2586 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2588 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2589 sl=get_reg(i_regs->regmap,dops[i].rs1);
2593 if(dops[i].opcode==0x0a) { // SLTI
2595 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2596 emit_slti32(t,cinfo[i].imm,t);
2598 emit_slti32(sl,cinfo[i].imm,t);
2603 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2604 emit_sltiu32(t,cinfo[i].imm,t);
2606 emit_sltiu32(sl,cinfo[i].imm,t);
2610 // SLTI(U) with r0 is just stupid,
2611 // nonetheless examples can be found
2612 if(dops[i].opcode==0x0a) // SLTI
2613 if(0<cinfo[i].imm) emit_movimm(1,t);
2614 else emit_zeroreg(t);
2617 if(cinfo[i].imm) emit_movimm(1,t);
2618 else emit_zeroreg(t);
2624 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2627 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2628 sl=get_reg(i_regs->regmap,dops[i].rs1);
2629 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2630 if(dops[i].opcode==0x0c) //ANDI
2634 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2635 emit_andimm(tl,cinfo[i].imm,tl);
2637 if(!((i_regs->wasconst>>sl)&1))
2638 emit_andimm(sl,cinfo[i].imm,tl);
2640 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
2650 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2652 if(dops[i].opcode==0x0d) { // ORI
2654 emit_orimm(tl,cinfo[i].imm,tl);
2656 if(!((i_regs->wasconst>>sl)&1))
2657 emit_orimm(sl,cinfo[i].imm,tl);
2659 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
2662 if(dops[i].opcode==0x0e) { // XORI
2664 emit_xorimm(tl,cinfo[i].imm,tl);
2666 if(!((i_regs->wasconst>>sl)&1))
2667 emit_xorimm(sl,cinfo[i].imm,tl);
2669 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
2674 emit_movimm(cinfo[i].imm,tl);
2682 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2684 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2688 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2689 s=get_reg(i_regs->regmap,dops[i].rs1);
2691 if(t>=0&&!((i_regs->isconst>>t)&1)){
2698 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2700 if(dops[i].opcode2==0) // SLL
2702 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
2704 if(dops[i].opcode2==2) // SRL
2706 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
2708 if(dops[i].opcode2==3) // SRA
2710 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
2714 if(s>=0 && s!=t) emit_mov(s,t);
2718 //emit_storereg(dops[i].rt1,t); //DEBUG
2721 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2725 if(dops[i].opcode2==0x3c) // DSLL32
2729 if(dops[i].opcode2==0x3e) // DSRL32
2733 if(dops[i].opcode2==0x3f) // DSRA32
2739 #ifndef shift_assemble
2740 static void shift_assemble(int i, const struct regstat *i_regs)
2742 signed char s,t,shift;
2743 if (dops[i].rt1 == 0)
2745 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2746 t = get_reg(i_regs->regmap, dops[i].rt1);
2747 s = get_reg(i_regs->regmap, dops[i].rs1);
2748 shift = get_reg(i_regs->regmap, dops[i].rs2);
2754 else if(dops[i].rs2==0) {
2756 if(s!=t) emit_mov(s,t);
2759 host_tempreg_acquire();
2760 emit_andimm(shift,31,HOST_TEMPREG);
2761 switch(dops[i].opcode2) {
2763 emit_shl(s,HOST_TEMPREG,t);
2766 emit_shr(s,HOST_TEMPREG,t);
2769 emit_sar(s,HOST_TEMPREG,t);
2774 host_tempreg_release();
2788 static int get_ptr_mem_type(u_int a)
2790 if(a < 0x00200000) {
2791 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2792 // return wrong, must use memhandler for BIOS self-test to pass
2793 // 007 does similar stuff from a00 mirror, weird stuff
2797 if(0x1f800000 <= a && a < 0x1f801000)
2799 if(0x80200000 <= a && a < 0x80800000)
2801 if(0xa0000000 <= a && a < 0xa0200000)
2806 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2808 int r = get_reg(i_regs->regmap, ROREG);
2809 if (r < 0 && host_tempreg_free) {
2810 host_tempreg_acquire();
2811 emit_loadreg(ROREG, r = HOST_TEMPREG);
2818 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2819 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
2823 int mr = dops[i].rs1;
2826 if(((smrv_strong|smrv_weak)>>mr)&1) {
2827 type=get_ptr_mem_type(smrv[mr]);
2828 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2831 // use the mirror we are running on
2832 type=get_ptr_mem_type(start);
2833 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2836 if (dops[i].may_except) {
2838 u_int op = dops[i].opcode;
2839 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
2841 emit_testimm(addr, mask);
2844 add_stub_r(ALIGNMENT_STUB, jaddr, out, i, addr, i_regs, ccadj_, 0);
2847 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2848 host_tempreg_acquire();
2849 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2850 addr=*addr_reg_override=HOST_TEMPREG;
2853 else if(type==MTYPE_0000) { // RAM 0 mirror
2854 host_tempreg_acquire();
2855 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2856 addr=*addr_reg_override=HOST_TEMPREG;
2859 else if(type==MTYPE_A000) { // RAM A mirror
2860 host_tempreg_acquire();
2861 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2862 addr=*addr_reg_override=HOST_TEMPREG;
2865 else if(type==MTYPE_1F80) { // scratchpad
2866 if (psxH == (void *)0x1f800000) {
2867 host_tempreg_acquire();
2868 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2869 emit_cmpimm(HOST_TEMPREG,0x1000);
2870 host_tempreg_release();
2875 // do the usual RAM check, jump will go to the right handler
2880 if (type == 0) // need ram check
2882 emit_cmpimm(addr,RAM_SIZE);
2884 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2885 // Hint to branch predictor that the branch is unlikely to be taken
2886 if (dops[i].rs1 >= 28)
2887 emit_jno_unlikely(0);
2891 if (ram_offset != 0)
2892 *offset_reg = get_ro_reg(i_regs, 0);
2898 // return memhandler, or get directly accessable address and return 0
2899 static void *get_direct_memhandler(void *table, u_int addr,
2900 enum stub_type type, uintptr_t *addr_host)
2902 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2903 uintptr_t l1, l2 = 0;
2904 l1 = ((uintptr_t *)table)[addr>>12];
2906 uintptr_t v = l1 << 1;
2907 *addr_host = v + addr;
2912 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2913 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2914 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2915 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2917 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2919 uintptr_t v = l2 << 1;
2920 *addr_host = v + (addr&0xfff);
2923 return (void *)(l2 << 1);
2927 static u_int get_host_reglist(const signed char *regmap)
2929 u_int reglist = 0, hr;
2930 for (hr = 0; hr < HOST_REGS; hr++) {
2931 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2937 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2940 reglist &= ~(1u << r1);
2942 reglist &= ~(1u << r2);
2946 // find a temp caller-saved register not in reglist (so assumed to be free)
2947 static int reglist_find_free(u_int reglist)
2949 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2952 return __builtin_ctz(free_regs);
2955 static void do_load_word(int a, int rt, int offset_reg)
2957 if (offset_reg >= 0)
2958 emit_ldr_dualindexed(offset_reg, a, rt);
2960 emit_readword_indexed(0, a, rt);
2963 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2965 if (offset_reg < 0) {
2966 emit_writeword_indexed(rt, ofs, a);
2970 emit_addimm(a, ofs, a);
2971 emit_str_dualindexed(offset_reg, a, rt);
2972 if (ofs != 0 && preseve_a)
2973 emit_addimm(a, -ofs, a);
2976 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2978 if (offset_reg < 0) {
2979 emit_writehword_indexed(rt, ofs, a);
2983 emit_addimm(a, ofs, a);
2984 emit_strh_dualindexed(offset_reg, a, rt);
2985 if (ofs != 0 && preseve_a)
2986 emit_addimm(a, -ofs, a);
2989 static void do_store_byte(int a, int rt, int offset_reg)
2991 if (offset_reg >= 0)
2992 emit_strb_dualindexed(offset_reg, a, rt);
2994 emit_writebyte_indexed(rt, 0, a);
2997 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2999 int addr = cinfo[i].addr;
3003 int memtarget=0,c=0;
3004 int offset_reg = -1;
3005 int fastio_reg_override = -1;
3006 u_int reglist=get_host_reglist(i_regs->regmap);
3007 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3008 s=get_reg(i_regs->regmap,dops[i].rs1);
3009 offset=cinfo[i].imm;
3010 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3012 c=(i_regs->wasconst>>s)&1;
3014 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3017 //printf("load_assemble: c=%d\n",c);
3018 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3019 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
3020 // could be FIFO, must perform the read
3022 assem_debug("(forced read)\n");
3023 tl = get_reg_temp(i_regs->regmap); // may be == addr
3028 //printf("load_assemble: c=%d\n",c);
3029 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3033 // Strmnnrmn's speed hack
3034 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3037 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3038 &offset_reg, &fastio_reg_override, ccadj_);
3041 else if (ram_offset && memtarget) {
3042 offset_reg = get_ro_reg(i_regs, 0);
3044 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
3045 switch (dops[i].opcode) {
3050 if (fastio_reg_override >= 0)
3051 a = fastio_reg_override;
3053 if (offset_reg >= 0)
3054 emit_ldrsb_dualindexed(offset_reg, a, tl);
3056 emit_movsbl_indexed(0, a, tl);
3059 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3062 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3068 if (fastio_reg_override >= 0)
3069 a = fastio_reg_override;
3070 if (offset_reg >= 0)
3071 emit_ldrsh_dualindexed(offset_reg, a, tl);
3073 emit_movswl_indexed(0, a, tl);
3076 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3079 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3085 if (fastio_reg_override >= 0)
3086 a = fastio_reg_override;
3087 do_load_word(a, tl, offset_reg);
3090 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3093 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3099 if (fastio_reg_override >= 0)
3100 a = fastio_reg_override;
3102 if (offset_reg >= 0)
3103 emit_ldrb_dualindexed(offset_reg, a, tl);
3105 emit_movzbl_indexed(0, a, tl);
3108 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3111 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3117 if (fastio_reg_override >= 0)
3118 a = fastio_reg_override;
3119 if (offset_reg >= 0)
3120 emit_ldrh_dualindexed(offset_reg, a, tl);
3122 emit_movzwl_indexed(0, a, tl);
3125 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3128 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3134 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3135 host_tempreg_release();
3138 #ifndef loadlr_assemble
3139 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3141 int addr = cinfo[i].addr;
3142 int s,tl,temp,temp2;
3145 int memtarget=0,c=0;
3146 int offset_reg = -1;
3147 int fastio_reg_override = -1;
3148 u_int reglist=get_host_reglist(i_regs->regmap);
3149 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3150 s=get_reg(i_regs->regmap,dops[i].rs1);
3151 temp=get_reg_temp(i_regs->regmap);
3152 temp2=get_reg(i_regs->regmap,FTEMP);
3153 offset=cinfo[i].imm;
3157 c=(i_regs->wasconst>>s)&1;
3159 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3163 emit_shlimm(addr,3,temp);
3164 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3165 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3167 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3169 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3170 &offset_reg, &fastio_reg_override, ccadj_);
3173 if (ram_offset && memtarget) {
3174 offset_reg = get_ro_reg(i_regs, 0);
3176 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3177 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3179 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3182 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3185 if (fastio_reg_override >= 0)
3186 a = fastio_reg_override;
3187 do_load_word(a, temp2, offset_reg);
3188 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3189 host_tempreg_release();
3190 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3193 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3196 emit_andimm(temp,24,temp);
3197 if (dops[i].opcode==0x22) // LWL
3198 emit_xorimm(temp,24,temp);
3199 host_tempreg_acquire();
3200 emit_movimm(-1,HOST_TEMPREG);
3201 if (dops[i].opcode==0x26) {
3202 emit_shr(temp2,temp,temp2);
3203 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3205 emit_shl(temp2,temp,temp2);
3206 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3208 host_tempreg_release();
3209 emit_or(temp2,tl,tl);
3211 //emit_storereg(dops[i].rt1,tl); // DEBUG
3213 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3219 static void do_invstub(int n)
3222 assem_debug("do_invstub\n");
3223 u_int reglist = stubs[n].a;
3224 u_int addrr = stubs[n].b;
3225 int ofs_start = stubs[n].c;
3226 int ofs_end = stubs[n].d;
3227 int len = ofs_end - ofs_start;
3230 set_jump_target(stubs[n].addr, out);
3232 if (addrr != 0 || ofs_start != 0)
3233 emit_addimm(addrr, ofs_start, 0);
3234 emit_readword(&inv_code_start, 2);
3235 emit_readword(&inv_code_end, 3);
3237 emit_addimm(0, len + 4, (rightr = 1));
3239 emit_cmpcs(3, rightr);
3242 void *func = (len != 0)
3243 ? (void *)ndrc_write_invalidate_many
3244 : (void *)ndrc_write_invalidate_one;
3245 emit_far_call(func);
3246 set_jump_target(jaddr, out);
3247 restore_regs(reglist);
3248 emit_jmp(stubs[n].retaddr);
3251 static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3253 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3255 // this can't be used any more since we started to check exact
3256 // block boundaries in invalidate_range()
3257 //if (i_regs->waswritten & (1<<dops[i].rs1))
3259 // (naively) assume nobody will run code from stack
3260 if (dops[i].rs1 == 29)
3263 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
3264 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
3265 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
3267 for (j = i - 1; j >= 0; j--) {
3268 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
3269 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
3272 if (imm_min > cinfo[j].imm)
3273 imm_min = cinfo[j].imm;
3274 if (imm_max < cinfo[j].imm)
3275 imm_max = cinfo[j].imm;
3277 #if defined(HOST_IMM8)
3278 int ir = get_reg(i_regs->regmap, INVCP);
3280 host_tempreg_acquire();
3281 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3283 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3286 #ifdef INVALIDATE_USE_COND_CALL
3288 emit_cmpimm(HOST_TEMPREG, 1);
3289 emit_callne(invalidate_addr_reg[addr]);
3290 host_tempreg_release();
3294 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3295 host_tempreg_release();
3296 imm_min -= cinfo[i].imm;
3297 imm_max -= cinfo[i].imm;
3298 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
3299 addr, imm_min, imm_max, 0);
3302 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3305 int addr = cinfo[i].addr;
3308 enum stub_type type=0;
3309 int memtarget=0,c=0;
3310 int offset_reg = -1;
3311 int fastio_reg_override = -1;
3312 u_int reglist=get_host_reglist(i_regs->regmap);
3313 tl=get_reg(i_regs->regmap,dops[i].rs2);
3314 s=get_reg(i_regs->regmap,dops[i].rs1);
3315 offset=cinfo[i].imm;
3317 c=(i_regs->wasconst>>s)&1;
3319 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3324 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3326 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3327 &offset_reg, &fastio_reg_override, ccadj_);
3329 else if (ram_offset && memtarget) {
3330 offset_reg = get_ro_reg(i_regs, 0);
3333 switch (dops[i].opcode) {
3337 if (fastio_reg_override >= 0)
3338 a = fastio_reg_override;
3339 do_store_byte(a, tl, offset_reg);
3346 if (fastio_reg_override >= 0)
3347 a = fastio_reg_override;
3348 do_store_hword(a, 0, tl, offset_reg, 1);
3355 if (fastio_reg_override >= 0)
3356 a = fastio_reg_override;
3357 do_store_word(a, 0, tl, offset_reg, 1);
3364 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3365 host_tempreg_release();
3367 // PCSX store handlers don't check invcode again
3369 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3374 do_store_smc_check(i, i_regs, reglist, addr);
3377 u_int addr_val=constmap[i][s]+offset;
3379 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3380 } else if(c&&!memtarget) {
3381 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3383 // basic current block modification detection..
3384 // not looking back as that should be in mips cache already
3385 // (see Spyro2 title->attract mode)
3386 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3387 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3388 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3389 if(i_regs->regmap==regs[i].regmap) {
3390 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3391 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3392 emit_movimm(start+i*4+4,0);
3393 emit_writeword(0,&pcaddr);
3394 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3395 emit_far_call(ndrc_get_addr_ht);
3401 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3403 int addr = cinfo[i].addr;
3407 void *case1, *case23, *case3;
3408 void *done0, *done1, *done2;
3409 int memtarget=0,c=0;
3410 int offset_reg = -1;
3411 u_int reglist=get_host_reglist(i_regs->regmap);
3412 tl=get_reg(i_regs->regmap,dops[i].rs2);
3413 s=get_reg(i_regs->regmap,dops[i].rs1);
3414 offset=cinfo[i].imm;
3416 c=(i_regs->isconst>>s)&1;
3418 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3424 emit_cmpimm(addr, RAM_SIZE);
3430 if(!memtarget||!dops[i].rs1) {
3436 offset_reg = get_ro_reg(i_regs, 0);
3438 emit_testimm(addr,2);
3441 emit_testimm(addr,1);
3445 if (dops[i].opcode == 0x2A) { // SWL
3446 // Write msb into least significant byte
3447 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3448 do_store_byte(addr, tl, offset_reg);
3449 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3451 else if (dops[i].opcode == 0x2E) { // SWR
3452 // Write entire word
3453 do_store_word(addr, 0, tl, offset_reg, 1);
3458 set_jump_target(case1, out);
3459 if (dops[i].opcode == 0x2A) { // SWL
3460 // Write two msb into two least significant bytes
3461 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3462 do_store_hword(addr, -1, tl, offset_reg, 0);
3463 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3465 else if (dops[i].opcode == 0x2E) { // SWR
3466 // Write 3 lsb into three most significant bytes
3467 do_store_byte(addr, tl, offset_reg);
3468 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3469 do_store_hword(addr, 1, tl, offset_reg, 0);
3470 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3475 set_jump_target(case23, out);
3476 emit_testimm(addr,1);
3480 if (dops[i].opcode==0x2A) { // SWL
3481 // Write 3 msb into three least significant bytes
3482 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3483 do_store_hword(addr, -2, tl, offset_reg, 1);
3484 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3485 do_store_byte(addr, tl, offset_reg);
3486 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3488 else if (dops[i].opcode == 0x2E) { // SWR
3489 // Write two lsb into two most significant bytes
3490 do_store_hword(addr, 0, tl, offset_reg, 1);
3495 set_jump_target(case3, out);
3496 if (dops[i].opcode == 0x2A) { // SWL
3497 do_store_word(addr, -3, tl, offset_reg, 0);
3499 else if (dops[i].opcode == 0x2E) { // SWR
3500 do_store_byte(addr, tl, offset_reg);
3502 set_jump_target(done0, out);
3503 set_jump_target(done1, out);
3504 set_jump_target(done2, out);
3505 if (offset_reg == HOST_TEMPREG)
3506 host_tempreg_release();
3508 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3509 do_store_smc_check(i, i_regs, reglist, addr);
3512 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3514 if(dops[i].opcode2==0) // MFC0
3516 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
3517 u_int copr=(source[i]>>11)&0x1f;
3518 if(t>=0&&dops[i].rt1!=0) {
3519 emit_readword(®_cop0[copr],t);
3522 else if(dops[i].opcode2==4) // MTC0
3524 int s = get_reg(i_regs->regmap, dops[i].rs1);
3525 int cc = get_reg(i_regs->regmap, CCREG);
3526 char copr=(source[i]>>11)&0x1f;
3528 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3529 if (copr == 12 || copr == 13) {
3530 emit_readword(&last_count,HOST_TEMPREG);
3531 if (cc != HOST_CCREG)
3532 emit_loadreg(CCREG, HOST_CCREG);
3533 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3534 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3535 emit_writeword(HOST_CCREG, &psxRegs.cycle);
3537 // burn cycles to cause cc_interrupt, which will
3538 // reschedule next_interupt. Relies on CCREG from above.
3539 assem_debug("MTC0 DS %d\n", copr);
3540 emit_writeword(HOST_CCREG,&last_count);
3541 emit_movimm(0,HOST_CCREG);
3542 emit_storereg(CCREG,HOST_CCREG);
3543 emit_loadreg(dops[i].rs1,1);
3544 emit_movimm(copr,0);
3545 emit_far_call(pcsx_mtc0_ds);
3546 emit_loadreg(dops[i].rs1,s);
3549 emit_movimm(start+i*4+4,HOST_TEMPREG);
3550 emit_writeword(HOST_TEMPREG,&pcaddr);
3551 emit_movimm(0,HOST_TEMPREG);
3552 emit_writeword(HOST_TEMPREG,&pending_exception);
3556 emit_movimm(copr, 0);
3557 emit_far_call(pcsx_mtc0);
3558 if (copr == 12 || copr == 13) {
3559 emit_readword(&psxRegs.cycle,HOST_CCREG);
3560 emit_readword(&last_count,HOST_TEMPREG);
3561 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3562 //emit_writeword(HOST_TEMPREG,&last_count);
3563 assert(!is_delayslot);
3564 emit_readword(&pending_exception,HOST_TEMPREG);
3565 emit_test(HOST_TEMPREG,HOST_TEMPREG);
3568 emit_readword(&pcaddr, 0);
3569 emit_far_call(ndrc_get_addr_ht);
3571 set_jump_target(jaddr, out);
3572 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3573 if (cc != HOST_CCREG)
3574 emit_storereg(CCREG, HOST_CCREG);
3576 emit_loadreg(dops[i].rs1,s);
3580 static void rfe_assemble(int i, const struct regstat *i_regs)
3582 emit_readword(&psxRegs.CP0.n.SR, 0);
3583 emit_andimm(0, 0x3c, 1);
3584 emit_andimm(0, ~0xf, 0);
3585 emit_orrshr_imm(1, 2, 0);
3586 emit_writeword(0, &psxRegs.CP0.n.SR);
3589 static int cop2_is_stalling_op(int i, int *cycles)
3591 if (dops[i].opcode == 0x3a) { // SWC2
3595 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3599 if (dops[i].itype == C2OP) {
3600 *cycles = gte_cycletab[source[i] & 0x3f];
3603 // ... what about MTC2/CTC2/LWC2?
3608 static void log_gte_stall(int stall, u_int cycle)
3610 if ((u_int)stall <= 44)
3611 printf("x stall %2d %u\n", stall, cycle + last_count);
3614 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3618 emit_movimm(stall, 0);
3620 emit_mov(HOST_TEMPREG, 0);
3621 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3622 emit_far_call(log_gte_stall);
3623 restore_regs(reglist);
3627 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3629 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3630 int rtmp = reglist_find_free(reglist);
3632 if (HACK_ENABLED(NDHACK_NO_STALLS))
3634 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3635 // happens occasionally... cc evicted? Don't bother then
3636 //printf("no cc %08x\n", start + i*4);
3640 for (j = i - 1; j >= 0; j--) {
3641 //if (dops[j].is_ds) break;
3642 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3644 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
3649 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
3650 if (other_gte_op_cycles >= 0)
3651 stall = other_gte_op_cycles - cycles_passed;
3652 else if (cycles_passed >= 44)
3653 stall = 0; // can't stall
3654 if (stall == -MAXBLOCK && rtmp >= 0) {
3655 // unknown stall, do the expensive runtime check
3656 assem_debug("; cop2_do_stall_check\n");
3659 emit_movimm(gte_cycletab[op], 0);
3660 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3661 emit_far_call(call_gteStall);
3662 restore_regs(reglist);
3664 host_tempreg_acquire();
3665 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3666 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3667 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3668 emit_cmpimm(HOST_TEMPREG, 44);
3669 emit_cmovb_reg(rtmp, HOST_CCREG);
3670 //emit_log_gte_stall(i, 0, reglist);
3671 host_tempreg_release();
3674 else if (stall > 0) {
3675 //emit_log_gte_stall(i, stall, reglist);
3676 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3679 // save gteBusyCycle, if needed
3680 if (gte_cycletab[op] == 0)
3682 other_gte_op_cycles = -1;
3683 for (j = i + 1; j < slen; j++) {
3684 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3686 if (dops[j].is_jump) {
3688 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3693 if (other_gte_op_cycles >= 0)
3694 // will handle stall when assembling that op
3696 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
3697 if (cycles_passed >= 44)
3699 assem_debug("; save gteBusyCycle\n");
3700 host_tempreg_acquire();
3702 emit_readword(&last_count, HOST_TEMPREG);
3703 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3704 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
3705 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3706 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3708 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
3709 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3711 host_tempreg_release();
3714 static int is_mflohi(int i)
3716 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3719 static int check_multdiv(int i, int *cycles)
3721 if (dops[i].itype != MULTDIV)
3723 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3724 *cycles = 11; // approx from 7 11 14
3730 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3732 int j, found = 0, c = 0;
3733 if (HACK_ENABLED(NDHACK_NO_STALLS))
3735 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3736 // happens occasionally... cc evicted? Don't bother then
3739 for (j = i + 1; j < slen; j++) {
3742 if ((found = is_mflohi(j)))
3744 if (dops[j].is_jump) {
3746 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3752 // handle all in multdiv_do_stall()
3754 check_multdiv(i, &c);
3756 assem_debug("; muldiv prepare stall %d\n", c);
3757 host_tempreg_acquire();
3758 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3759 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3760 host_tempreg_release();
3763 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3765 int j, known_cycles = 0;
3766 u_int reglist = get_host_reglist(i_regs->regmap);
3767 int rtmp = get_reg_temp(i_regs->regmap);
3769 rtmp = reglist_find_free(reglist);
3770 if (HACK_ENABLED(NDHACK_NO_STALLS))
3772 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3773 // happens occasionally... cc evicted? Don't bother then
3774 //printf("no cc/rtmp %08x\n", start + i*4);
3778 for (j = i - 1; j >= 0; j--) {
3779 if (dops[j].is_ds) break;
3780 if (check_multdiv(j, &known_cycles))
3783 // already handled by this op
3785 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
3790 if (known_cycles > 0) {
3791 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
3792 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3793 if (known_cycles > 0)
3794 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3797 assem_debug("; muldiv stall unresolved\n");
3798 host_tempreg_acquire();
3799 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3800 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3801 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3802 emit_cmpimm(HOST_TEMPREG, 37);
3803 emit_cmovb_reg(rtmp, HOST_CCREG);
3804 //emit_log_gte_stall(i, 0, reglist);
3805 host_tempreg_release();
3808 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3818 emit_readword(®_cop2d[copr],tl);
3819 emit_signextend16(tl,tl);
3820 emit_writeword(tl,®_cop2d[copr]); // hmh
3827 emit_readword(®_cop2d[copr],tl);
3828 emit_andimm(tl,0xffff,tl);
3829 emit_writeword(tl,®_cop2d[copr]);
3832 emit_readword(®_cop2d[14],tl); // SXY2
3833 emit_writeword(tl,®_cop2d[copr]);
3837 c2op_mfc2_29_assemble(tl,temp);
3840 emit_readword(®_cop2d[copr],tl);
3845 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3849 emit_readword(®_cop2d[13],temp); // SXY1
3850 emit_writeword(sl,®_cop2d[copr]);
3851 emit_writeword(temp,®_cop2d[12]); // SXY0
3852 emit_readword(®_cop2d[14],temp); // SXY2
3853 emit_writeword(sl,®_cop2d[14]);
3854 emit_writeword(temp,®_cop2d[13]); // SXY1
3857 emit_andimm(sl,0x001f,temp);
3858 emit_shlimm(temp,7,temp);
3859 emit_writeword(temp,®_cop2d[9]);
3860 emit_andimm(sl,0x03e0,temp);
3861 emit_shlimm(temp,2,temp);
3862 emit_writeword(temp,®_cop2d[10]);
3863 emit_andimm(sl,0x7c00,temp);
3864 emit_shrimm(temp,3,temp);
3865 emit_writeword(temp,®_cop2d[11]);
3866 emit_writeword(sl,®_cop2d[28]);
3869 emit_xorsar_imm(sl,sl,31,temp);
3870 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3871 emit_clz(temp,temp);
3873 emit_movs(temp,HOST_TEMPREG);
3874 emit_movimm(0,temp);
3875 emit_jeq((int)out+4*4);
3876 emit_addpl_imm(temp,1,temp);
3877 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3878 emit_jns((int)out-2*4);
3880 emit_writeword(sl,®_cop2d[30]);
3881 emit_writeword(temp,®_cop2d[31]);
3886 emit_writeword(sl,®_cop2d[copr]);
3891 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3896 int memtarget=0,c=0;
3898 enum stub_type type;
3899 int offset_reg = -1;
3900 int fastio_reg_override = -1;
3901 u_int reglist=get_host_reglist(i_regs->regmap);
3902 u_int copr=(source[i]>>16)&0x1f;
3903 s=get_reg(i_regs->regmap,dops[i].rs1);
3904 tl=get_reg(i_regs->regmap,FTEMP);
3905 offset=cinfo[i].imm;
3908 if(i_regs->regmap[HOST_CCREG]==CCREG)
3909 reglist&=~(1<<HOST_CCREG);
3914 if (dops[i].opcode==0x3a) { // SWC2
3917 if(s>=0) c=(i_regs->wasconst>>s)&1;
3918 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3920 cop2_do_stall_check(0, i, i_regs, reglist);
3922 if (dops[i].opcode==0x3a) { // SWC2
3923 cop2_get_dreg(copr,tl,-1);
3931 emit_jmp(0); // inline_readstub/inline_writestub?
3935 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3936 &offset_reg, &fastio_reg_override, ccadj_);
3938 else if (ram_offset && memtarget) {
3939 offset_reg = get_ro_reg(i_regs, 0);
3941 switch (dops[i].opcode) {
3942 case 0x32: { // LWC2
3944 if (fastio_reg_override >= 0)
3945 a = fastio_reg_override;
3946 do_load_word(a, tl, offset_reg);
3949 case 0x3a: { // SWC2
3950 #ifdef DESTRUCTIVE_SHIFT
3951 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3954 if (fastio_reg_override >= 0)
3955 a = fastio_reg_override;
3956 do_store_word(a, 0, tl, offset_reg, 1);
3963 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3964 host_tempreg_release();
3966 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3967 if(dops[i].opcode==0x3a) // SWC2
3968 do_store_smc_check(i, i_regs, reglist, ar);
3969 if (dops[i].opcode==0x32) { // LWC2
3970 host_tempreg_acquire();
3971 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3972 host_tempreg_release();
3976 static void cop2_assemble(int i, const struct regstat *i_regs)
3978 u_int copr = (source[i]>>11) & 0x1f;
3979 signed char temp = get_reg_temp(i_regs->regmap);
3981 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3982 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3983 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3984 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3985 reglist = reglist_exclude(reglist, tl, -1);
3987 cop2_do_stall_check(0, i, i_regs, reglist);
3989 if (dops[i].opcode2==0) { // MFC2
3990 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3991 if(tl>=0&&dops[i].rt1!=0)
3992 cop2_get_dreg(copr,tl,temp);
3994 else if (dops[i].opcode2==4) { // MTC2
3995 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3996 cop2_put_dreg(copr,sl,temp);
3998 else if (dops[i].opcode2==2) // CFC2
4000 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4001 if(tl>=0&&dops[i].rt1!=0)
4002 emit_readword(®_cop2c[copr],tl);
4004 else if (dops[i].opcode2==6) // CTC2
4006 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4015 emit_signextend16(sl,temp);
4018 c2op_ctc2_31_assemble(sl,temp);
4024 emit_writeword(temp,®_cop2c[copr]);
4029 static void do_unalignedwritestub(int n)
4031 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4033 set_jump_target(stubs[n].addr, out);
4036 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4037 int addr=stubs[n].b;
4038 u_int reglist=stubs[n].e;
4039 signed char *i_regmap=i_regs->regmap;
4040 int temp2=get_reg(i_regmap,FTEMP);
4042 rt=get_reg(i_regmap,dops[i].rs2);
4045 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4047 reglist&=~(1<<temp2);
4049 // don't bother with it and call write handler
4052 int cc=get_reg(i_regmap,CCREG);
4054 emit_loadreg(CCREG,2);
4055 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4056 emit_movimm(start + i*4,3);
4057 emit_writeword(3,&psxRegs.pc);
4058 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4059 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4061 emit_storereg(CCREG,2);
4062 restore_regs(reglist);
4063 emit_jmp(stubs[n].retaddr); // return address
4066 static void do_overflowstub(int n)
4068 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4071 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4072 int ccadj = stubs[n].d;
4073 set_jump_target(stubs[n].addr, out);
4074 wb_dirtys(regs[i].regmap, regs[i].dirty);
4075 exception_assemble(i, i_regs, ccadj);
4078 static void do_alignmentstub(int n)
4080 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4083 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4084 int ccadj = stubs[n].d;
4085 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4086 int cause = (dops[i].opcode & 3) << 28;
4087 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4088 set_jump_target(stubs[n].addr, out);
4089 wb_dirtys(regs[i].regmap, regs[i].dirty);
4090 if (stubs[n].b != 1)
4091 emit_mov(stubs[n].b, 1); // faulting address
4092 emit_movimm(cause, 0);
4093 exception_assemble(i, i_regs, ccadj);
4096 #ifndef multdiv_assemble
4097 void multdiv_assemble(int i,struct regstat *i_regs)
4099 printf("Need multdiv_assemble for this architecture.\n");
4104 static void mov_assemble(int i, const struct regstat *i_regs)
4106 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4107 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4110 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4113 sl=get_reg(i_regs->regmap,dops[i].rs1);
4114 if(sl>=0) emit_mov(sl,tl);
4115 else emit_loadreg(dops[i].rs1,tl);
4118 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4119 multdiv_do_stall(i, i_regs);
4122 // call interpreter, exception handler, things that change pc/regs/cycles ...
4123 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4125 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4126 assert(ccreg==HOST_CCREG);
4127 assert(!is_delayslot);
4130 emit_movimm(pc,3); // Get PC
4131 emit_readword(&last_count,2);
4132 emit_writeword(3,&psxRegs.pc);
4133 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4134 emit_add(2,HOST_CCREG,2);
4135 emit_writeword(2,&psxRegs.cycle);
4136 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
4137 emit_far_call(func);
4138 emit_far_jump(jump_to_new_pc);
4141 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
4143 // 'break' tends to be littered around to catch things like
4144 // division by 0 and is almost never executed, so don't emit much code here
4146 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4147 func = is_delayslot ? jump_overflow_ds : jump_overflow;
4148 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4149 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
4150 else if (dops[i].opcode2 == 0x0C)
4151 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4153 func = is_delayslot ? jump_break_ds : jump_break;
4154 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4155 emit_loadreg(CCREG, HOST_CCREG);
4156 emit_movimm(start + i*4, 2); // pc
4157 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4158 emit_far_jump(func);
4161 static void hlecall_bad()
4166 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4168 void *hlefunc = hlecall_bad;
4169 uint32_t hleCode = source[i] & 0x03ffffff;
4170 if (hleCode < ARRAY_SIZE(psxHLEt))
4171 hlefunc = psxHLEt[hleCode];
4173 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4176 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4178 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4181 static void speculate_mov(int rs,int rt)
4184 smrv_strong_next|=1<<rt;
4189 static void speculate_mov_weak(int rs,int rt)
4192 smrv_weak_next|=1<<rt;
4197 static void speculate_register_values(int i)
4200 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4201 // gp,sp are likely to stay the same throughout the block
4202 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4203 smrv_weak_next=~smrv_strong_next;
4204 //printf(" llr %08x\n", smrv[4]);
4206 smrv_strong=smrv_strong_next;
4207 smrv_weak=smrv_weak_next;
4208 switch(dops[i].itype) {
4210 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4211 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4212 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4213 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4215 smrv_strong_next&=~(1<<dops[i].rt1);
4216 smrv_weak_next&=~(1<<dops[i].rt1);
4220 smrv_strong_next&=~(1<<dops[i].rt1);
4221 smrv_weak_next&=~(1<<dops[i].rt1);
4224 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4225 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4228 if(get_final_value(hr,i,&value))
4229 smrv[dops[i].rt1]=value;
4230 else smrv[dops[i].rt1]=constmap[i][hr];
4231 smrv_strong_next|=1<<dops[i].rt1;
4235 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4236 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4240 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4241 // special case for BIOS
4242 smrv[dops[i].rt1]=0xa0000000;
4243 smrv_strong_next|=1<<dops[i].rt1;
4250 smrv_strong_next&=~(1<<dops[i].rt1);
4251 smrv_weak_next&=~(1<<dops[i].rt1);
4255 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4256 smrv_strong_next&=~(1<<dops[i].rt1);
4257 smrv_weak_next&=~(1<<dops[i].rt1);
4261 if (dops[i].opcode==0x32) { // LWC2
4262 smrv_strong_next&=~(1<<dops[i].rt1);
4263 smrv_weak_next&=~(1<<dops[i].rt1);
4269 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4270 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4274 static void ujump_assemble(int i, const struct regstat *i_regs);
4275 static void rjump_assemble(int i, const struct regstat *i_regs);
4276 static void cjump_assemble(int i, const struct regstat *i_regs);
4277 static void sjump_assemble(int i, const struct regstat *i_regs);
4279 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4282 switch (dops[i].itype) {
4284 alu_assemble(i, i_regs, ccadj_);
4287 imm16_assemble(i, i_regs, ccadj_);
4290 shift_assemble(i, i_regs);
4293 shiftimm_assemble(i, i_regs);
4296 load_assemble(i, i_regs, ccadj_);
4299 loadlr_assemble(i, i_regs, ccadj_);
4302 store_assemble(i, i_regs, ccadj_);
4305 storelr_assemble(i, i_regs, ccadj_);
4308 cop0_assemble(i, i_regs, ccadj_);
4311 rfe_assemble(i, i_regs);
4314 cop2_assemble(i, i_regs);
4317 c2ls_assemble(i, i_regs, ccadj_);
4320 c2op_assemble(i, i_regs);
4323 multdiv_assemble(i, i_regs);
4324 multdiv_prepare_stall(i, i_regs, ccadj_);
4327 mov_assemble(i, i_regs);
4330 exception_assemble(i, i_regs, ccadj_);
4333 hlecall_assemble(i, i_regs, ccadj_);
4336 intcall_assemble(i, i_regs, ccadj_);
4339 ujump_assemble(i, i_regs);
4343 rjump_assemble(i, i_regs);
4347 cjump_assemble(i, i_regs);
4351 sjump_assemble(i, i_regs);
4356 // not handled, just skip
4364 static void ds_assemble(int i, const struct regstat *i_regs)
4366 speculate_register_values(i);
4368 switch (dops[i].itype) {
4376 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4379 assemble(i, i_regs, cinfo[i].ccadj);
4384 // Is the branch target a valid internal jump?
4385 static int internal_branch(int addr)
4387 if(addr&1) return 0; // Indirect (register) jump
4388 if(addr>=start && addr<start+slen*4-4)
4395 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4398 for(hr=0;hr<HOST_REGS;hr++) {
4399 if(hr!=EXCLUDE_REG) {
4400 if(pre[hr]!=entry[hr]) {
4403 if(get_reg(entry,pre[hr])<0) {
4405 if(!((u>>pre[hr])&1))
4406 emit_storereg(pre[hr],hr);
4413 // Move from one register to another (no writeback)
4414 for(hr=0;hr<HOST_REGS;hr++) {
4415 if(hr!=EXCLUDE_REG) {
4416 if(pre[hr]!=entry[hr]) {
4417 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4419 if((nr=get_reg(entry,pre[hr]))>=0) {
4428 // Load the specified registers
4429 // This only loads the registers given as arguments because
4430 // we don't want to load things that will be overwritten
4431 static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4433 int hr = get_reg(regmap, rs);
4434 if (hr >= 0 && entry[hr] != regmap[hr])
4435 emit_loadreg(regmap[hr], hr);
4438 static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4440 load_reg(entry, regmap, rs1);
4442 load_reg(entry, regmap, rs2);
4445 // Load registers prior to the start of a loop
4446 // so that they are not loaded within the loop
4447 static void loop_preload(signed char pre[],signed char entry[])
4450 for (hr = 0; hr < HOST_REGS; hr++) {
4452 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4453 assem_debug("loop preload:\n");
4455 emit_loadreg(r, hr);
4460 // Generate address for load/store instruction
4461 // goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4462 // AGEN is assigned by pass5b_preallocate2
4463 static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4465 if (dops[i].is_load || dops[i].is_store) {
4467 int agr = AGEN1 + (i&1);
4468 if(dops[i].itype==LOAD) {
4469 if (!dops[i].may_except)
4470 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4472 ra = get_reg_temp(i_regs->regmap);
4474 if(dops[i].itype==LOADLR) {
4475 ra=get_reg(i_regs->regmap,FTEMP);
4477 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4478 ra=get_reg(i_regs->regmap,agr);
4479 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4481 if(dops[i].itype==C2LS) {
4482 if (dops[i].opcode == 0x32) // LWC2
4483 ra=get_reg(i_regs->regmap,FTEMP);
4485 ra=get_reg(i_regs->regmap,agr);
4486 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4489 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4492 int offset = cinfo[i].imm;
4493 int add_offset = offset != 0;
4494 int c=(i_regs->wasconst>>rs)&1;
4495 if(dops[i].rs1==0) {
4496 // Using r0 as a base address
4498 if(!entry||entry[ra]!=agr) {
4499 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4500 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4502 emit_movimm(offset,ra);
4504 } // else did it in the previous cycle
4510 if (!entry || entry[ra] != dops[i].rs1)
4511 emit_loadreg(dops[i].rs1, ra);
4513 //if(!entry||entry[ra]!=dops[i].rs1)
4514 // printf("poor load scheduling!\n");
4517 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4519 if(!entry||entry[ra]!=agr) {
4520 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4521 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4523 emit_movimm(constmap[i][rs]+offset,ra);
4524 regs[i].loadedconst|=1<<ra;
4526 } // else did it in the previous cycle
4529 else // else load_consts already did it
4533 else if (dops[i].itype == STORELR) { // overwrites addr
4544 emit_addimm(rs,offset,ra);
4546 emit_addimm(ra,offset,ra);
4551 assert(cinfo[i].addr >= 0);
4553 // Preload constants for next instruction
4554 if (dops[i+1].is_load || dops[i+1].is_store) {
4557 agr=AGEN1+((i+1)&1);
4558 ra=get_reg(i_regs->regmap,agr);
4560 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4561 int offset=cinfo[i+1].imm;
4562 int c=(regs[i+1].wasconst>>rs)&1;
4563 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4564 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4565 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4566 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4567 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4569 emit_movimm(constmap[i+1][rs]+offset,ra);
4570 regs[i+1].loadedconst|=1<<ra;
4573 else if(dops[i+1].rs1==0) {
4574 // Using r0 as a base address
4575 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4576 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4577 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4578 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4580 emit_movimm(offset,ra);
4587 static int get_final_value(int hr, int i, u_int *value)
4589 int reg=regs[i].regmap[hr];
4591 if(regs[i+1].regmap[hr]!=reg) break;
4592 if(!((regs[i+1].isconst>>hr)&1)) break;
4593 if(dops[i+1].bt) break;
4597 if (dops[i].is_jump) {
4598 *value=constmap[i][hr];
4602 if (dops[i+1].is_jump) {
4603 // Load in delay slot, out-of-order execution
4604 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4606 // Precompute load address
4607 *value=constmap[i][hr]+cinfo[i+2].imm;
4611 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4613 // Precompute load address
4614 *value=constmap[i][hr]+cinfo[i+1].imm;
4615 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
4620 *value=constmap[i][hr];
4621 //printf("c=%lx\n",(long)constmap[i][hr]);
4622 if(i==slen-1) return 1;
4624 return !((unneeded_reg[i+1]>>reg)&1);
4627 // Load registers with known constants
4628 static void load_consts(signed char pre[],signed char regmap[],int i)
4631 // propagate loaded constant flags
4632 if(i==0||dops[i].bt)
4633 regs[i].loadedconst=0;
4635 for(hr=0;hr<HOST_REGS;hr++) {
4636 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4637 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4639 regs[i].loadedconst|=1<<hr;
4644 for(hr=0;hr<HOST_REGS;hr++) {
4645 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4646 //if(entry[hr]!=regmap[hr]) {
4647 if(!((regs[i].loadedconst>>hr)&1)) {
4648 assert(regmap[hr]<64);
4649 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4650 u_int value, similar=0;
4651 if(get_final_value(hr,i,&value)) {
4652 // see if some other register has similar value
4653 for(hr2=0;hr2<HOST_REGS;hr2++) {
4654 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4655 if(is_similar_value(value,constmap[i][hr2])) {
4663 if(get_final_value(hr2,i,&value2)) // is this needed?
4664 emit_movimm_from(value2,hr2,value,hr);
4666 emit_movimm(value,hr);
4672 emit_movimm(value,hr);
4675 regs[i].loadedconst|=1<<hr;
4682 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4686 for(hr=0;hr<HOST_REGS;hr++) {
4687 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4688 assert(regmap[hr] < 64);
4689 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4690 int value=constmap[i][hr];
4695 emit_movimm(value,hr);
4702 // Write out all dirty registers (except cycle count)
4703 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4706 for(hr=0;hr<HOST_REGS;hr++) {
4707 if(hr!=EXCLUDE_REG) {
4708 if(i_regmap[hr]>0) {
4709 if(i_regmap[hr]!=CCREG) {
4710 if((i_dirty>>hr)&1) {
4711 assert(i_regmap[hr]<64);
4712 emit_storereg(i_regmap[hr],hr);
4720 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4721 // This writes the registers not written by store_regs_bt
4722 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4725 int t=(addr-start)>>2;
4726 for(hr=0;hr<HOST_REGS;hr++) {
4727 if(hr!=EXCLUDE_REG) {
4728 if(i_regmap[hr]>0) {
4729 if(i_regmap[hr]!=CCREG) {
4730 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4731 if((i_dirty>>hr)&1) {
4732 assert(i_regmap[hr]<64);
4733 emit_storereg(i_regmap[hr],hr);
4742 // Load all registers (except cycle count)
4743 static void load_all_regs(const signed char i_regmap[])
4746 for(hr=0;hr<HOST_REGS;hr++) {
4747 if(hr!=EXCLUDE_REG) {
4748 if(i_regmap[hr]==0) {
4752 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4754 emit_loadreg(i_regmap[hr],hr);
4760 // Load all current registers also needed by next instruction
4761 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4764 for(hr=0;hr<HOST_REGS;hr++) {
4765 if(hr!=EXCLUDE_REG) {
4766 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4767 if(i_regmap[hr]==0) {
4771 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4773 emit_loadreg(i_regmap[hr],hr);
4780 // Load all regs, storing cycle count if necessary
4781 static void load_regs_entry(int t)
4784 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4785 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
4786 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4787 emit_storereg(CCREG,HOST_CCREG);
4790 for(hr=0;hr<HOST_REGS;hr++) {
4791 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4792 if(regs[t].regmap_entry[hr]==0) {
4795 else if(regs[t].regmap_entry[hr]!=CCREG)
4797 emit_loadreg(regs[t].regmap_entry[hr],hr);
4803 // Store dirty registers prior to branch
4804 static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4806 if(internal_branch(addr))
4808 int t=(addr-start)>>2;
4810 for(hr=0;hr<HOST_REGS;hr++) {
4811 if(hr!=EXCLUDE_REG) {
4812 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4813 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4814 if((i_dirty>>hr)&1) {
4815 assert(i_regmap[hr]<64);
4816 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4817 emit_storereg(i_regmap[hr],hr);
4826 // Branch out of this block, write out all dirty regs
4827 wb_dirtys(i_regmap,i_dirty);
4831 // Load all needed registers for branch target
4832 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4834 //if(addr>=start && addr<(start+slen*4))
4835 if(internal_branch(addr))
4837 int t=(addr-start)>>2;
4839 // Store the cycle count before loading something else
4840 if(i_regmap[HOST_CCREG]!=CCREG) {
4841 assert(i_regmap[HOST_CCREG]==-1);
4843 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4844 emit_storereg(CCREG,HOST_CCREG);
4847 for(hr=0;hr<HOST_REGS;hr++) {
4848 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4849 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4850 if(regs[t].regmap_entry[hr]==0) {
4853 else if(regs[t].regmap_entry[hr]!=CCREG)
4855 emit_loadreg(regs[t].regmap_entry[hr],hr);
4863 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4865 if(addr>=start && addr<start+slen*4-4)
4867 int t=(addr-start)>>2;
4869 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4870 for(hr=0;hr<HOST_REGS;hr++)
4874 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4876 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4883 if(i_regmap[hr]<TEMPREG)
4885 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4888 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4894 else // Same register but is it 32-bit or dirty?
4897 if(!((regs[t].dirty>>hr)&1))
4901 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4903 //printf("%x: dirty no match\n",addr);
4911 // Delay slots are not valid branch targets
4912 //if(t>0&&(dops[t-1].is_jump) return 0;
4913 // Delay slots require additional processing, so do not match
4914 if(dops[t].is_ds) return 0;
4919 for(hr=0;hr<HOST_REGS;hr++)
4925 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4940 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4942 extern void do_insn_cmp();
4944 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4946 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4948 // write out changed consts to match the interpreter
4949 if (i > 0 && !dops[i].bt) {
4950 for (hr = 0; hr < HOST_REGS; hr++) {
4951 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4952 if (hr == EXCLUDE_REG || reg <= 0)
4954 if (!((regs[i-1].isconst >> hr) & 1))
4956 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4958 emit_movimm(constmap[i-1][hr],0);
4959 emit_storereg(reg, 0);
4962 emit_movimm(start+i*4,0);
4963 emit_writeword(0,&pcaddr);
4964 int cc = get_reg(regs[i].regmap_entry, CCREG);
4966 emit_loadreg(CCREG, cc = 0);
4967 emit_addimm(cc, ccadj_, 0);
4968 emit_writeword(0, &psxRegs.cycle);
4969 emit_far_call(do_insn_cmp);
4970 //emit_readword(&cycle,0);
4971 //emit_addimm(0,2,0);
4972 //emit_writeword(0,&cycle);
4974 restore_regs(reglist);
4975 assem_debug("\\\\do_insn_cmp\n");
4978 #define drc_dbg_emit_do_cmp(x,y)
4981 // Used when a branch jumps into the delay slot of another branch
4982 static void ds_assemble_entry(int i)
4984 int t = (cinfo[i].ba - start) >> 2;
4985 int ccadj_ = -CLOCK_ADJUST(1);
4987 instr_addr[t] = out;
4988 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
4989 assem_debug("<->\n");
4990 drc_dbg_emit_do_cmp(t, ccadj_);
4991 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4992 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4993 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4994 address_generation(t,®s[t],regs[t].regmap_entry);
4995 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4996 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4997 if (dops[t].is_store)
4998 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
5000 switch (dops[t].itype) {
5008 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5011 assemble(t, ®s[t], ccadj_);
5013 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5014 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5015 if(internal_branch(cinfo[i].ba+4))
5016 assem_debug("branch: internal\n");
5018 assem_debug("branch: external\n");
5019 assert(internal_branch(cinfo[i].ba+4));
5020 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
5024 // Load 2 immediates optimizing for small code size
5025 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5027 emit_movimm(imm1,rt1);
5028 emit_movimm_from(imm1,rt1,imm2,rt2);
5031 static void do_cc(int i, const signed char i_regmap[], int *adj,
5032 int addr, int taken, int invert)
5034 int count, count_plus2;
5038 if(dops[i].itype==RJUMP)
5042 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5043 if(internal_branch(cinfo[i].ba))
5045 t=(cinfo[i].ba-start)>>2;
5046 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
5047 else *adj=cinfo[t].ccadj;
5053 count = cinfo[i].ccadj;
5054 count_plus2 = count + CLOCK_ADJUST(2);
5055 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
5057 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5059 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5060 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5064 else if(*adj==0||invert) {
5065 int cycles = count_plus2;
5070 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5071 cycles=*adj+count+2-*adj;
5074 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5080 emit_cmpimm(HOST_CCREG, -count_plus2);
5084 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
5087 static void do_ccstub(int n)
5090 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
5091 set_jump_target(stubs[n].addr, out);
5093 if(stubs[n].d==NULLDS) {
5094 // Delay slot instruction is nullified ("likely" branch)
5095 wb_dirtys(regs[i].regmap,regs[i].dirty);
5097 else if(stubs[n].d!=TAKEN) {
5098 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5101 if(internal_branch(cinfo[i].ba))
5102 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5106 // Save PC as return address
5107 emit_movimm(stubs[n].c,0);
5108 emit_writeword(0,&pcaddr);
5112 // Return address depends on which way the branch goes
5113 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5115 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5116 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5122 else if(dops[i].rs2==0)
5127 #ifdef DESTRUCTIVE_WRITEBACK
5129 if((branch_regs[i].dirty>>s1l)&&1)
5130 emit_loadreg(dops[i].rs1,s1l);
5133 if((branch_regs[i].dirty>>s1l)&1)
5134 emit_loadreg(dops[i].rs2,s1l);
5137 if((branch_regs[i].dirty>>s2l)&1)
5138 emit_loadreg(dops[i].rs2,s2l);
5141 int addr=-1,alt=-1,ntaddr=-1;
5144 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5145 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5146 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5154 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5155 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5156 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5162 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
5166 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5167 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5168 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5174 assert(hr<HOST_REGS);
5176 if (dops[i].opcode == 4) // BEQ
5178 #ifdef HAVE_CMOV_IMM
5179 if(s2l>=0) emit_cmp(s1l,s2l);
5180 else emit_test(s1l,s1l);
5181 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
5183 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
5184 if(s2l>=0) emit_cmp(s1l,s2l);
5185 else emit_test(s1l,s1l);
5186 emit_cmovne_reg(alt,addr);
5189 else if (dops[i].opcode == 5) // BNE
5191 #ifdef HAVE_CMOV_IMM
5192 if(s2l>=0) emit_cmp(s1l,s2l);
5193 else emit_test(s1l,s1l);
5194 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
5196 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
5197 if(s2l>=0) emit_cmp(s1l,s2l);
5198 else emit_test(s1l,s1l);
5199 emit_cmovne_reg(alt,addr);
5202 else if (dops[i].opcode == 6) // BLEZ
5204 //emit_movimm(cinfo[i].ba,alt);
5205 //emit_movimm(start+i*4+8,addr);
5206 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
5208 emit_cmovl_reg(alt,addr);
5210 else if (dops[i].opcode == 7) // BGTZ
5212 //emit_movimm(cinfo[i].ba,addr);
5213 //emit_movimm(start+i*4+8,ntaddr);
5214 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
5216 emit_cmovl_reg(ntaddr,addr);
5218 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
5220 //emit_movimm(cinfo[i].ba,alt);
5221 //emit_movimm(start+i*4+8,addr);
5223 emit_mov2imm_compact(cinfo[i].ba,
5224 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5225 (dops[i].opcode2 & 1) ? alt : addr);
5227 emit_cmovs_reg(alt,addr);
5230 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
5232 emit_writeword(addr, &pcaddr);
5235 if(dops[i].itype==RJUMP)
5237 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5238 if (ds_writes_rjump_rs(i)) {
5239 r=get_reg(branch_regs[i].regmap,RTEMP);
5241 emit_writeword(r,&pcaddr);
5243 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5245 // Update cycle count
5246 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5247 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5248 emit_far_call(cc_interrupt);
5249 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5250 if(stubs[n].d==TAKEN) {
5251 if(internal_branch(cinfo[i].ba))
5252 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
5253 else if(dops[i].itype==RJUMP) {
5254 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5255 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5257 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5259 }else if(stubs[n].d==NOTTAKEN) {
5260 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5261 else load_all_regs(branch_regs[i].regmap);
5262 }else if(stubs[n].d==NULLDS) {
5263 // Delay slot instruction is nullified ("likely" branch)
5264 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5265 else load_all_regs(regs[i].regmap);
5267 load_all_regs(branch_regs[i].regmap);
5269 if (stubs[n].retaddr)
5270 emit_jmp(stubs[n].retaddr);
5272 do_jump_vaddr(stubs[n].e);
5275 static void add_to_linker(void *addr, u_int target, int is_internal)
5277 assert(linkcount < ARRAY_SIZE(link_addr));
5278 link_addr[linkcount].addr = addr;
5279 link_addr[linkcount].target = target;
5280 link_addr[linkcount].internal = is_internal;
5284 static void ujump_assemble_write_ra(int i)
5287 unsigned int return_address;
5288 rt=get_reg(branch_regs[i].regmap,31);
5289 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5291 return_address=start+i*4+8;
5294 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5295 int temp=-1; // note: must be ds-safe
5299 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5300 else emit_movimm(return_address,rt);
5308 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5311 if (!((regs[i].loadedconst >> rt) & 1))
5312 emit_movimm(return_address, rt); // PC into link register
5314 emit_prefetch(hash_table_get(return_address));
5320 static void ujump_assemble(int i, const struct regstat *i_regs)
5322 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5323 address_generation(i+1,i_regs,regs[i].regmap_entry);
5325 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5326 if(dops[i].rt1==31&&temp>=0)
5328 signed char *i_regmap=i_regs->regmap;
5329 int return_address=start+i*4+8;
5330 if(get_reg(branch_regs[i].regmap,31)>0)
5331 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5334 if (dops[i].rt1 == 31)
5335 ujump_assemble_write_ra(i); // writeback ra for DS
5336 ds_assemble(i+1,i_regs);
5337 uint64_t bc_unneeded=branch_regs[i].u;
5338 bc_unneeded|=1|(1LL<<dops[i].rt1);
5339 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5340 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5342 cc=get_reg(branch_regs[i].regmap,CCREG);
5343 assert(cc==HOST_CCREG);
5344 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5346 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5348 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5349 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5350 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5351 if(internal_branch(cinfo[i].ba))
5352 assem_debug("branch: internal\n");
5354 assem_debug("branch: external\n");
5355 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
5356 ds_assemble_entry(i);
5359 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
5364 static void rjump_assemble_write_ra(int i)
5366 int rt,return_address;
5367 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
5368 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5370 return_address=start+i*4+8;
5374 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5377 if (!((regs[i].loadedconst >> rt) & 1))
5378 emit_movimm(return_address, rt); // PC into link register
5380 emit_prefetch(hash_table_get(return_address));
5384 static void rjump_assemble(int i, const struct regstat *i_regs)
5388 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5390 if (ds_writes_rjump_rs(i)) {
5391 // Delay slot abuse, make a copy of the branch address register
5392 temp=get_reg(branch_regs[i].regmap,RTEMP);
5394 assert(regs[i].regmap[temp]==RTEMP);
5398 address_generation(i+1,i_regs,regs[i].regmap_entry);
5402 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5403 signed char *i_regmap=i_regs->regmap;
5404 int return_address=start+i*4+8;
5405 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5410 if(dops[i].rs1==31) {
5411 int rh=get_reg(regs[i].regmap,RHASH);
5412 if(rh>=0) do_preload_rhash(rh);
5415 if (dops[i].rt1 != 0)
5416 rjump_assemble_write_ra(i);
5417 ds_assemble(i+1,i_regs);
5418 uint64_t bc_unneeded=branch_regs[i].u;
5419 bc_unneeded|=1|(1LL<<dops[i].rt1);
5420 bc_unneeded&=~(1LL<<dops[i].rs1);
5421 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5422 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5423 cc=get_reg(branch_regs[i].regmap,CCREG);
5424 assert(cc==HOST_CCREG);
5427 int rh=get_reg(branch_regs[i].regmap,RHASH);
5428 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5429 if(dops[i].rs1==31) {
5430 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5431 do_preload_rhtbl(ht);
5435 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5436 #ifdef DESTRUCTIVE_WRITEBACK
5437 if((branch_regs[i].dirty>>rs)&1) {
5438 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5439 emit_loadreg(dops[i].rs1,rs);
5444 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5447 if(dops[i].rs1==31) {
5448 do_miniht_load(ht,rh);
5451 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5452 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
5454 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5455 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5456 if (dops[i+1].itype == RFE)
5457 // special case for RFE
5461 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5463 if(dops[i].rs1==31) {
5464 do_miniht_jump(rs,rh,ht);
5471 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5472 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5476 static void cjump_assemble(int i, const struct regstat *i_regs)
5478 const signed char *i_regmap = i_regs->regmap;
5481 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5482 assem_debug("match=%d\n",match);
5484 int unconditional=0,nop=0;
5486 int internal=internal_branch(cinfo[i].ba);
5487 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5488 if(!match) invert=1;
5489 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5490 if(i>(cinfo[i].ba-start)>>2) invert=1;
5493 invert=1; // because of near cond. branches
5497 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5498 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5501 s1l=get_reg(i_regmap,dops[i].rs1);
5502 s2l=get_reg(i_regmap,dops[i].rs2);
5504 if(dops[i].rs1==0&&dops[i].rs2==0)
5506 if(dops[i].opcode&1) nop=1;
5507 else unconditional=1;
5508 //assert(dops[i].opcode!=5);
5509 //assert(dops[i].opcode!=7);
5510 //assert(dops[i].opcode!=0x15);
5511 //assert(dops[i].opcode!=0x17);
5513 else if(dops[i].rs1==0)
5518 else if(dops[i].rs2==0)
5524 // Out of order execution (delay slot first)
5526 address_generation(i+1,i_regs,regs[i].regmap_entry);
5527 ds_assemble(i+1,i_regs);
5529 uint64_t bc_unneeded=branch_regs[i].u;
5530 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5532 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5533 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5534 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5535 cc=get_reg(branch_regs[i].regmap,CCREG);
5536 assert(cc==HOST_CCREG);
5538 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5539 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5540 //assem_debug("cycle count (adj)\n");
5542 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5543 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5544 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5545 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5547 assem_debug("branch: internal\n");
5549 assem_debug("branch: external\n");
5550 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
5551 ds_assemble_entry(i);
5554 add_to_linker(out,cinfo[i].ba,internal);
5557 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5558 if(((u_int)out)&7) emit_addnop(0);
5563 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5566 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5569 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5570 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5571 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5573 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5575 if(dops[i].opcode==4) // BEQ
5577 if(s2l>=0) emit_cmp(s1l,s2l);
5578 else emit_test(s1l,s1l);
5583 add_to_linker(out,cinfo[i].ba,internal);
5587 if(dops[i].opcode==5) // BNE
5589 if(s2l>=0) emit_cmp(s1l,s2l);
5590 else emit_test(s1l,s1l);
5595 add_to_linker(out,cinfo[i].ba,internal);
5599 if(dops[i].opcode==6) // BLEZ
5606 add_to_linker(out,cinfo[i].ba,internal);
5610 if(dops[i].opcode==7) // BGTZ
5617 add_to_linker(out,cinfo[i].ba,internal);
5622 if(taken) set_jump_target(taken, out);
5623 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5624 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
5626 emit_addimm(cc,-adj,cc);
5627 add_to_linker(out,cinfo[i].ba,internal);
5630 add_to_linker(out,cinfo[i].ba,internal*2);
5636 if(adj) emit_addimm(cc,-adj,cc);
5637 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5638 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5640 assem_debug("branch: internal\n");
5642 assem_debug("branch: external\n");
5643 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5644 ds_assemble_entry(i);
5647 add_to_linker(out,cinfo[i].ba,internal);
5651 set_jump_target(nottaken, out);
5654 if(nottaken1) set_jump_target(nottaken1, out);
5656 if(!invert) emit_addimm(cc,adj,cc);
5658 } // (!unconditional)
5662 // In-order execution (branch first)
5663 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5664 if(!unconditional&&!nop) {
5665 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5667 if((dops[i].opcode&0x2f)==4) // BEQ
5669 if(s2l>=0) emit_cmp(s1l,s2l);
5670 else emit_test(s1l,s1l);
5674 if((dops[i].opcode&0x2f)==5) // BNE
5676 if(s2l>=0) emit_cmp(s1l,s2l);
5677 else emit_test(s1l,s1l);
5681 if((dops[i].opcode&0x2f)==6) // BLEZ
5687 if((dops[i].opcode&0x2f)==7) // BGTZ
5693 } // if(!unconditional)
5695 uint64_t ds_unneeded=branch_regs[i].u;
5696 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5700 if(taken) set_jump_target(taken, out);
5701 assem_debug("1:\n");
5702 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5704 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5705 address_generation(i+1,&branch_regs[i],0);
5707 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5708 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5709 ds_assemble(i+1,&branch_regs[i]);
5710 cc=get_reg(branch_regs[i].regmap,CCREG);
5712 emit_loadreg(CCREG,cc=HOST_CCREG);
5713 // CHECK: Is the following instruction (fall thru) allocated ok?
5715 assert(cc==HOST_CCREG);
5716 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5717 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5718 assem_debug("cycle count (adj)\n");
5719 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5720 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5722 assem_debug("branch: internal\n");
5724 assem_debug("branch: external\n");
5725 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5726 ds_assemble_entry(i);
5729 add_to_linker(out,cinfo[i].ba,internal);
5734 if(!unconditional) {
5735 if(nottaken1) set_jump_target(nottaken1, out);
5736 set_jump_target(nottaken, out);
5737 assem_debug("2:\n");
5738 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5740 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5741 address_generation(i+1,&branch_regs[i],0);
5743 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5744 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5745 ds_assemble(i+1,&branch_regs[i]);
5746 cc=get_reg(branch_regs[i].regmap,CCREG);
5748 // Cycle count isn't in a register, temporarily load it then write it out
5749 emit_loadreg(CCREG,HOST_CCREG);
5750 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5753 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5754 emit_storereg(CCREG,HOST_CCREG);
5757 cc=get_reg(i_regmap,CCREG);
5758 assert(cc==HOST_CCREG);
5759 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5762 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5768 static void sjump_assemble(int i, const struct regstat *i_regs)
5770 const signed char *i_regmap = i_regs->regmap;
5773 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5774 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5776 int unconditional=0,nevertaken=0;
5778 int internal=internal_branch(cinfo[i].ba);
5779 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5780 if(!match) invert=1;
5781 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5782 if(i>(cinfo[i].ba-start)>>2) invert=1;
5785 invert=1; // because of near cond. branches
5788 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5789 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5792 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5795 s1l=get_reg(i_regmap,dops[i].rs1);
5799 if(dops[i].opcode2&1) unconditional=1;
5801 // These are never taken (r0 is never less than zero)
5802 //assert(dops[i].opcode2!=0);
5803 //assert(dops[i].opcode2!=2);
5804 //assert(dops[i].opcode2!=0x10);
5805 //assert(dops[i].opcode2!=0x12);
5809 // Out of order execution (delay slot first)
5811 address_generation(i+1,i_regs,regs[i].regmap_entry);
5812 ds_assemble(i+1,i_regs);
5814 uint64_t bc_unneeded=branch_regs[i].u;
5815 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5817 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5818 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5819 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5820 if(dops[i].rt1==31) {
5821 int rt,return_address;
5822 rt=get_reg(branch_regs[i].regmap,31);
5823 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5825 // Save the PC even if the branch is not taken
5826 return_address=start+i*4+8;
5827 emit_movimm(return_address,rt); // PC into link register
5829 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5833 cc=get_reg(branch_regs[i].regmap,CCREG);
5834 assert(cc==HOST_CCREG);
5836 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5837 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5838 assem_debug("cycle count (adj)\n");
5840 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5841 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5842 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5843 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5845 assem_debug("branch: internal\n");
5847 assem_debug("branch: external\n");
5848 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5849 ds_assemble_entry(i);
5852 add_to_linker(out,cinfo[i].ba,internal);
5855 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5856 if(((u_int)out)&7) emit_addnop(0);
5860 else if(nevertaken) {
5861 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5864 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5867 void *nottaken = NULL;
5868 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5869 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5872 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
5879 add_to_linker(out,cinfo[i].ba,internal);
5890 add_to_linker(out,cinfo[i].ba,internal);
5897 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5898 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
5900 emit_addimm(cc,-adj,cc);
5901 add_to_linker(out,cinfo[i].ba,internal);
5904 add_to_linker(out,cinfo[i].ba,internal*2);
5910 if(adj) emit_addimm(cc,-adj,cc);
5911 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5912 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5914 assem_debug("branch: internal\n");
5916 assem_debug("branch: external\n");
5917 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5918 ds_assemble_entry(i);
5921 add_to_linker(out,cinfo[i].ba,internal);
5925 set_jump_target(nottaken, out);
5929 if(!invert) emit_addimm(cc,adj,cc);
5931 } // (!unconditional)
5935 // In-order execution (branch first)
5937 void *nottaken = NULL;
5938 if (!unconditional && !nevertaken) {
5940 emit_test(s1l, s1l);
5942 if (dops[i].rt1 == 31) {
5943 int rt, return_address;
5944 rt = get_reg(branch_regs[i].regmap,31);
5946 // Save the PC even if the branch is not taken
5947 return_address = start + i*4+8;
5948 emit_movimm(return_address, rt); // PC into link register
5950 emit_prefetch(hash_table_get(return_address));
5954 if (!unconditional && !nevertaken) {
5956 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5962 uint64_t ds_unneeded=branch_regs[i].u;
5963 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5967 //assem_debug("1:\n");
5968 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5970 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5971 address_generation(i+1,&branch_regs[i],0);
5973 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5974 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5975 ds_assemble(i+1,&branch_regs[i]);
5976 cc=get_reg(branch_regs[i].regmap,CCREG);
5978 emit_loadreg(CCREG,cc=HOST_CCREG);
5979 // CHECK: Is the following instruction (fall thru) allocated ok?
5981 assert(cc==HOST_CCREG);
5982 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5983 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5984 assem_debug("cycle count (adj)\n");
5985 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5986 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5988 assem_debug("branch: internal\n");
5990 assem_debug("branch: external\n");
5991 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5992 ds_assemble_entry(i);
5995 add_to_linker(out,cinfo[i].ba,internal);
6000 if(!unconditional) {
6003 set_jump_target(nottaken, out);
6005 assem_debug("1:\n");
6006 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6007 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6008 address_generation(i+1,&branch_regs[i],0);
6010 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6011 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6012 ds_assemble(i+1,&branch_regs[i]);
6013 cc=get_reg(branch_regs[i].regmap,CCREG);
6015 // Cycle count isn't in a register, temporarily load it then write it out
6016 emit_loadreg(CCREG,HOST_CCREG);
6017 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
6020 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6021 emit_storereg(CCREG,HOST_CCREG);
6024 cc=get_reg(i_regmap,CCREG);
6025 assert(cc==HOST_CCREG);
6026 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
6029 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6035 static void check_regmap(signed char *regmap)
6039 for (i = 0; i < HOST_REGS; i++) {
6042 for (j = i + 1; j < HOST_REGS; j++)
6043 assert(regmap[i] != regmap[j]);
6049 #include <inttypes.h>
6050 static char insn[MAXBLOCK][10];
6052 #define set_mnemonic(i_, n_) \
6053 strcpy(insn[i_], n_)
6055 void print_regmap(const char *name, const signed char *regmap)
6059 fputs(name, stdout);
6060 for (i = 0; i < HOST_REGS; i++) {
6063 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6067 printf(" r%d=%s", i, buf);
6069 fputs("\n", stdout);
6073 void disassemble_inst(int i)
6075 if (dops[i].bt) printf("*"); else printf(" ");
6076 switch(dops[i].itype) {
6078 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
6080 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
6082 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6084 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
6085 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6087 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6090 if(dops[i].opcode==0xf) //LUI
6091 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
6093 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6097 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6101 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
6105 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6108 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6111 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6114 if((dops[i].opcode2&0x1d)==0x10)
6115 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6116 else if((dops[i].opcode2&0x1d)==0x11)
6117 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6119 printf (" %x: %s\n",start+i*4,insn[i]);
6122 if(dops[i].opcode2==0)
6123 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6124 else if(dops[i].opcode2==4)
6125 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6126 else printf (" %x: %s\n",start+i*4,insn[i]);
6129 if(dops[i].opcode2<3)
6130 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6131 else if(dops[i].opcode2>3)
6132 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6133 else printf (" %x: %s\n",start+i*4,insn[i]);
6136 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
6139 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6142 //printf (" %s %8x\n",insn[i],source[i]);
6143 printf (" %x: %s\n",start+i*4,insn[i]);
6145 #ifndef REGMAP_PRINT
6148 printf("D: %"PRIx64" WD: %"PRIx64" U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
6149 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6150 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
6151 print_regmap("pre: ", regmap_pre[i]);
6152 print_regmap("entry: ", regs[i].regmap_entry);
6153 print_regmap("map: ", regs[i].regmap);
6154 if (dops[i].is_jump) {
6155 print_regmap("bentry:", branch_regs[i].regmap_entry);
6156 print_regmap("bmap: ", branch_regs[i].regmap);
6160 #define set_mnemonic(i_, n_)
6161 static void disassemble_inst(int i) {}
6164 #define DRC_TEST_VAL 0x74657374
6166 static noinline void new_dynarec_test(void)
6168 int (*testfunc)(void);
6173 // check structure linkage
6174 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6176 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6179 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6180 new_dynarec_test, out);
6181 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6183 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6184 out = ndrc->translation_cache;
6185 beginning = start_block();
6186 emit_movimm(DRC_TEST_VAL + i, 0); // test
6189 end_block(beginning);
6190 testfunc = beginning;
6191 ret[i] = testfunc();
6194 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6195 SysPrintf("test passed.\n");
6197 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6198 out = ndrc->translation_cache;
6201 // clear the state completely, instead of just marking
6202 // things invalid like invalidate_all_pages() does
6203 void new_dynarec_clear_full(void)
6206 out = ndrc->translation_cache;
6207 memset(invalid_code,1,sizeof(invalid_code));
6208 memset(hash_table,0xff,sizeof(hash_table));
6209 memset(mini_ht,-1,sizeof(mini_ht));
6210 memset(shadow,0,sizeof(shadow));
6212 expirep = EXPIRITY_OFFSET;
6213 pending_exception=0;
6216 inv_code_start=inv_code_end=~0;
6219 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6220 blocks_clear(&blocks[n]);
6221 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6225 stat_clear(stat_blocks);
6226 stat_clear(stat_links);
6228 cycle_multiplier_old = Config.cycle_multiplier;
6229 new_dynarec_hacks_old = new_dynarec_hacks;
6232 void new_dynarec_init(void)
6234 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6239 #ifdef BASE_ADDR_DYNAMIC
6241 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6243 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6244 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6246 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6247 sceKernelOpenVMDomain();
6248 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6249 #elif defined(_MSC_VER)
6250 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6251 PAGE_EXECUTE_READWRITE);
6252 #elif defined(HAVE_LIBNX)
6253 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6255 SysPrintf("jitCreate failed: %08x\n", rc);
6256 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6257 jitTransitionToWritable(&g_jit);
6258 ndrc = g_jit.rx_addr;
6259 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6260 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6262 uintptr_t desired_addr = 0;
6263 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6264 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6268 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6270 #ifdef TC_WRITE_OFFSET
6271 // mostly for testing
6272 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6273 ftruncate(fd, sizeof(*ndrc));
6274 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6275 (flags = MAP_SHARED), fd, 0);
6276 assert(mw != MAP_FAILED);
6277 prot = PROT_READ | PROT_EXEC;
6279 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6280 if (ndrc == MAP_FAILED) {
6281 SysPrintf("mmap() failed: %s\n", strerror(errno));
6284 #ifdef TC_WRITE_OFFSET
6285 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6289 #ifndef NO_WRITE_EXEC
6290 // not all systems allow execute in data segment by default
6291 // size must be 4K aligned for 3DS?
6292 if (mprotect(ndrc, sizeof(*ndrc),
6293 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6294 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6297 out = ndrc->translation_cache;
6298 new_dynarec_clear_full();
6300 // Copy this into local area so we don't have to put it in every literal pool
6301 invc_ptr=invalid_code;
6305 ram_offset=(uintptr_t)rdram-0x80000000;
6307 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6308 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6309 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6312 void new_dynarec_cleanup(void)
6315 #ifdef BASE_ADDR_DYNAMIC
6317 // sceBlock is managed by retroarch's bootstrap code
6318 //sceKernelFreeMemBlock(sceBlock);
6320 #elif defined(HAVE_LIBNX)
6324 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6325 SysPrintf("munmap() failed\n");
6329 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6330 blocks_clear(&blocks[n]);
6331 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6335 stat_clear(stat_blocks);
6336 stat_clear(stat_links);
6337 new_dynarec_print_stats();
6340 static u_int *get_source_start(u_int addr, u_int *limit)
6342 if (addr < 0x00200000 ||
6343 (0xa0000000 <= addr && addr < 0xa0200000))
6345 // used for BIOS calls mostly?
6346 *limit = (addr&0xa0000000)|0x00200000;
6347 return (u_int *)(rdram + (addr&0x1fffff));
6349 else if (!Config.HLE && (
6350 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6351 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6353 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6354 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
6355 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6356 cycle_multiplier_active = 200;
6358 *limit = (addr & 0xfff00000) | 0x80000;
6359 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6361 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6362 *limit = (addr & 0x80600000) + 0x00200000;
6363 return (u_int *)(rdram + (addr&0x1fffff));
6368 static u_int scan_for_ret(u_int addr)
6373 mem = get_source_start(addr, &limit);
6377 if (limit > addr + 0x1000)
6378 limit = addr + 0x1000;
6379 for (; addr < limit; addr += 4, mem++) {
6380 if (*mem == 0x03e00008) // jr $ra
6386 struct savestate_block {
6391 static int addr_cmp(const void *p1_, const void *p2_)
6393 const struct savestate_block *p1 = p1_, *p2 = p2_;
6394 return p1->addr - p2->addr;
6397 int new_dynarec_save_blocks(void *save, int size)
6399 struct savestate_block *sblocks = save;
6400 int maxcount = size / sizeof(sblocks[0]);
6401 struct savestate_block tmp_blocks[1024];
6402 struct block_info *block;
6403 int p, s, d, o, bcnt;
6407 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6409 for (block = blocks[p]; block != NULL; block = block->next) {
6410 if (block->is_dirty)
6412 tmp_blocks[bcnt].addr = block->start;
6413 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6418 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6420 addr = tmp_blocks[0].addr;
6421 for (s = d = 0; s < bcnt; s++) {
6422 if (tmp_blocks[s].addr < addr)
6424 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6425 tmp_blocks[d++] = tmp_blocks[s];
6426 addr = scan_for_ret(tmp_blocks[s].addr);
6429 if (o + d > maxcount)
6431 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6435 return o * sizeof(sblocks[0]);
6438 void new_dynarec_load_blocks(const void *save, int size)
6440 const struct savestate_block *sblocks = save;
6441 int count = size / sizeof(sblocks[0]);
6442 struct block_info *block;
6443 u_int regs_save[32];
6448 // restore clean blocks, if any
6449 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6450 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6451 if (!block->is_dirty)
6453 assert(block->source && block->copy);
6454 if (memcmp(block->source, block->copy, block->len))
6457 // see try_restore_block
6458 block->is_dirty = 0;
6459 mark_invalid_code(block->start, block->len, 0);
6463 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6465 // change GPRs for speculation to at least partially work..
6466 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6467 for (i = 1; i < 32; i++)
6468 psxRegs.GPR.r[i] = 0x80000000;
6470 for (b = 0; b < count; b++) {
6471 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6473 psxRegs.GPR.r[i] = 0x1f800000;
6476 ndrc_get_addr_ht(sblocks[b].addr);
6478 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6480 psxRegs.GPR.r[i] = 0x80000000;
6484 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6487 void new_dynarec_print_stats(void)
6490 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6491 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6492 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6493 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6494 out - ndrc->translation_cache, stat_blocks, stat_links);
6495 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6496 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6497 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6501 static int apply_hacks(void)
6504 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6506 /* special hack(s) */
6507 for (i = 0; i < slen - 4; i++)
6509 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6510 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6511 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6512 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
6514 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6515 dops[i + 3].itype = NOP;
6519 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6520 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6521 && dops[i-7].itype == STORE)
6524 if (dops[i].itype == IMM16)
6526 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6527 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6528 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6530 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6538 static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op)
6540 return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2)
6541 && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP;
6544 static void force_intcall(int i)
6546 memset(&dops[i], 0, sizeof(dops[i]));
6547 dops[i].itype = INTCALL;
6548 dops[i].rs1 = CCREG;
6549 dops[i].is_exception = 1;
6553 static void disassemble_one(int i, u_int src)
6555 unsigned int type, op, op2, op3;
6556 memset(&dops[i], 0, sizeof(dops[i]));
6557 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6560 dops[i].opcode = op = src >> 26;
6563 set_mnemonic(i, "???");
6566 case 0x00: set_mnemonic(i, "special");
6570 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6571 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6572 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6573 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6574 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6575 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6576 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6577 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6578 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6579 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6580 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6581 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6582 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6583 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6584 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6585 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6586 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6587 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6588 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6589 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6590 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6591 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6592 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6593 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6594 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6595 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6596 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6597 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6600 case 0x01: set_mnemonic(i, "regimm");
6602 op2 = (src >> 16) & 0x1f;
6605 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6606 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6609 set_mnemonic(i, "BGEZ");
6611 set_mnemonic(i, "BLTZ");
6614 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6615 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6616 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6617 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6618 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6619 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6620 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6621 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6622 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6623 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6624 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6625 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6626 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6627 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6628 case 0x10: set_mnemonic(i, "COP0");
6629 op2 = (src >> 21) & 0x1f;
6634 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6635 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6636 default: type = OTHER; break;
6644 set_mnemonic(i, "MFC0");
6645 rd = (src >> 11) & 0x1F;
6646 if (!(0x00000417u & (1u << rd)))
6649 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6651 case 0x06: type = INTCALL; break;
6652 default: type = OTHER; break;
6655 case 0x11: set_mnemonic(i, "COP1");
6656 op2 = (src >> 21) & 0x1f;
6658 case 0x12: set_mnemonic(i, "COP2");
6659 op2 = (src >> 21) & 0x1f;
6662 if (gte_handlers[src & 0x3f] != NULL) {
6664 if (gte_regnames[src & 0x3f] != NULL)
6665 strcpy(insn[i], gte_regnames[src & 0x3f]);
6667 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
6674 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6675 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6676 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6677 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6680 case 0x13: set_mnemonic(i, "COP3");
6681 op2 = (src >> 21) & 0x1f;
6683 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6684 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6685 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6686 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6687 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6688 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6689 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
6690 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6691 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6692 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6693 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
6694 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6695 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6696 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6698 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
6699 set_mnemonic(i, "HLECALL");
6706 if (type == INTCALL)
6707 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
6709 dops[i].opcode2=op2;
6710 /* Get registers/immediates */
6712 gte_rs[i]=gte_rt[i]=0;
6719 dops[i].rs1 = (src >> 21) & 0x1f;
6720 dops[i].rt1 = (src >> 16) & 0x1f;
6721 cinfo[i].imm = (short)src;
6725 dops[i].rs1 = (src >> 21) & 0x1f;
6726 dops[i].rs2 = (src >> 16) & 0x1f;
6727 cinfo[i].imm = (short)src;
6730 // LWL/LWR only load part of the register,
6731 // therefore the target register must be treated as a source too
6732 dops[i].rs1 = (src >> 21) & 0x1f;
6733 dops[i].rs2 = (src >> 16) & 0x1f;
6734 dops[i].rt1 = (src >> 16) & 0x1f;
6735 cinfo[i].imm = (short)src;
6738 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6739 else dops[i].rs1 = (src >> 21) & 0x1f;
6741 dops[i].rt1 = (src >> 16) & 0x1f;
6742 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6743 cinfo[i].imm = (unsigned short)src;
6745 cinfo[i].imm = (short)src;
6749 // The JAL instruction writes to r31.
6756 dops[i].rs1 = (src >> 21) & 0x1f;
6757 // The JALR instruction writes to rd.
6759 dops[i].rt1 = (src >> 11) & 0x1f;
6764 dops[i].rs1 = (src >> 21) & 0x1f;
6765 dops[i].rs2 = (src >> 16) & 0x1f;
6766 if(op&2) { // BGTZ/BLEZ
6771 dops[i].rs1 = (src >> 21) & 0x1f;
6772 dops[i].rs2 = CCREG;
6773 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6775 // NOTE: If the branch is not taken, r31 is still overwritten
6779 dops[i].rs1=(src>>21)&0x1f; // source
6780 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6781 dops[i].rt1=(src>>11)&0x1f; // destination
6784 dops[i].rs1=(src>>21)&0x1f; // source
6785 dops[i].rs2=(src>>16)&0x1f; // divisor
6790 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6791 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6792 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6793 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6794 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6795 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
6798 dops[i].rs1=(src>>16)&0x1f; // target of shift
6799 dops[i].rs2=(src>>21)&0x1f; // shift amount
6800 dops[i].rt1=(src>>11)&0x1f; // destination
6803 dops[i].rs1=(src>>16)&0x1f;
6805 dops[i].rt1=(src>>11)&0x1f;
6806 cinfo[i].imm=(src>>6)&0x1f;
6809 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6810 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6811 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
6814 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6815 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6816 int gr=(src>>11)&0x1F;
6819 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6820 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6821 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6822 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6826 dops[i].rs1=(src>>21)&0x1F;
6827 cinfo[i].imm=(short)src;
6828 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6829 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
6832 gte_rs[i]=gte_reg_reads[src&0x3f];
6833 gte_rt[i]=gte_reg_writes[src&0x3f];
6834 gte_rt[i]|=1ll<<63; // every op changes flags
6835 if((src&0x3f)==GTE_MVMVA) {
6836 int v = (src >> 15) & 3;
6837 gte_rs[i]&=~0xe3fll;
6838 if(v==3) gte_rs[i]|=0xe00ll;
6839 else gte_rs[i]|=3ll<<(v*2);
6852 static noinline void pass1_disassemble(u_int pagelimit)
6854 int i, j, done = 0, ni_count = 0;
6856 for (i = 0; !done; i++)
6858 int force_j_to_interpreter = 0;
6859 unsigned int type, op, op2;
6861 disassemble_one(i, source[i]);
6862 type = dops[i].itype;
6863 op = dops[i].opcode;
6864 op2 = dops[i].opcode2;
6866 /* Calculate branch target addresses */
6868 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6869 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6870 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6871 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6872 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6873 else if(type==CJUMP||type==SJUMP)
6874 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6876 /* simplify always (not)taken branches */
6877 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6878 dops[i].rs1 = dops[i].rs2 = 0;
6880 dops[i].itype = type = UJUMP;
6881 dops[i].rs2 = CCREG;
6884 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6885 dops[i].itype = type = UJUMP;
6887 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6888 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6889 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
6890 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
6891 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6892 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6893 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
6895 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6896 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6897 dops[i].may_except = 1;
6898 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6899 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6900 dops[i].may_except = 1;
6902 /* rare messy cases to just pass over to the interpreter */
6903 if (i > 0 && dops[i-1].is_jump) {
6905 // branch in delay slot?
6906 if (dops[i].is_jump) {
6907 // don't handle first branch and call interpreter if it's hit
6908 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
6909 force_j_to_interpreter = 1;
6911 // load delay detection through a branch
6912 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
6913 const struct decoded_insn *dop = NULL;
6915 if (cinfo[i-1].ba != -1) {
6916 t = (cinfo[i-1].ba - start) / 4;
6917 if (t < 0 || t > i) {
6919 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6921 disassemble_one(MAXBLOCK - 1, mem[0]);
6922 dop = &dops[MAXBLOCK - 1];
6928 if ((dop && is_ld_use_hazard(dops[i].rt1, dop))
6929 || (!dop && Config.PreciseExceptions)) {
6930 // jump target wants DS result - potential load delay effect
6931 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
6932 force_j_to_interpreter = 1;
6933 if (0 <= t && t < i)
6934 dops[t + 1].bt = 1; // expected return from interpreter
6936 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6937 !(i>=3&&dops[i-3].is_jump)) {
6938 // v0 overwrite like this is a sign of trouble, bail out
6939 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6940 force_j_to_interpreter = 1;
6944 else if (i > 0 && dops[i-1].is_delay_load
6945 && is_ld_use_hazard(dops[i-1].rt1, &dops[i])
6946 && (i < 2 || !dops[i-2].is_ujump)) {
6947 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6948 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6949 if (dops[j-1].rt1 != dops[i-1].rt1)
6951 force_j_to_interpreter = 1;
6953 if (force_j_to_interpreter) {
6956 i = j; // don't compile the problematic branch/load/etc
6958 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
6959 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
6964 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
6966 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
6969 /* Is this the end of the block? */
6970 if (i > 0 && dops[i-1].is_ujump) {
6971 if (dops[i-1].rt1 == 0) { // not jal
6972 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
6973 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6974 // scan for a branch back to i+1
6975 for (j = t; j < t + 64; j++) {
6976 int tmpop = source[j] >> 26;
6977 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6978 int t2 = j + 1 + (int)(signed short)source[j];
6980 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6991 if(stop_after_jal) done=1;
6993 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6995 // Don't recompile stuff that's already compiled
6996 if(check_addr(start+i*4+4)) done=1;
6997 // Don't get too close to the limit
6998 if(i>MAXBLOCK/2) done=1;
7000 if (dops[i].itype == HLECALL)
7002 else if (dops[i].itype == INTCALL)
7004 else if (dops[i].is_exception)
7005 done = stop_after_jal ? 1 : 2;
7007 // Does the block continue due to a branch?
7010 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7011 if(cinfo[j].ba==start+i*4+4) done=j=0;
7012 if(cinfo[j].ba==start+i*4+8) done=j=0;
7015 //assert(i<MAXBLOCK-1);
7016 if(start+i*4==pagelimit-4) done=1;
7017 assert(start+i*4<pagelimit);
7018 if (i==MAXBLOCK-1) done=1;
7019 // Stop if we're compiling junk
7020 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7021 done=stop_after_jal=1;
7022 SysPrintf("Disabled speculative precompilation\n");
7025 while (i > 0 && dops[i-1].is_jump)
7028 assert(!dops[i-1].is_jump);
7032 // Basic liveness analysis for MIPS registers
7033 static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7036 uint64_t u,gte_u,b,gte_b;
7037 uint64_t temp_u,temp_gte_u=0;
7038 uint64_t gte_u_unknown=0;
7039 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7043 gte_u=gte_u_unknown;
7045 //u=unneeded_reg[iend+1];
7047 gte_u=gte_unneeded[iend+1];
7050 for (i=iend;i>=istart;i--)
7052 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7055 // If subroutine call, flag return address as a possible branch target
7056 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7058 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7060 // Branch out of this block, flush all regs
7062 gte_u=gte_u_unknown;
7063 branch_unneeded_reg[i]=u;
7064 // Merge in delay slot
7065 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7066 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7069 gte_u&=~gte_rs[i+1];
7073 // Internal branch, flag target
7074 dops[(cinfo[i].ba-start)>>2].bt=1;
7075 if(cinfo[i].ba<=start+i*4) {
7077 if(dops[i].is_ujump)
7079 // Unconditional branch
7083 // Conditional branch (not taken case)
7084 temp_u=unneeded_reg[i+2];
7085 temp_gte_u&=gte_unneeded[i+2];
7087 // Merge in delay slot
7088 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7089 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7091 temp_gte_u|=gte_rt[i+1];
7092 temp_gte_u&=~gte_rs[i+1];
7093 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7094 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7096 temp_gte_u|=gte_rt[i];
7097 temp_gte_u&=~gte_rs[i];
7098 unneeded_reg[i]=temp_u;
7099 gte_unneeded[i]=temp_gte_u;
7100 // Only go three levels deep. This recursion can take an
7101 // excessive amount of time if there are a lot of nested loops.
7103 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
7105 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7106 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
7109 if (dops[i].is_ujump)
7111 // Unconditional branch
7112 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7113 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
7114 branch_unneeded_reg[i]=u;
7115 // Merge in delay slot
7116 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7117 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7120 gte_u&=~gte_rs[i+1];
7122 // Conditional branch
7123 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7124 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
7125 branch_unneeded_reg[i]=b;
7126 // Branch delay slot
7127 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7128 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7131 gte_b&=~gte_rs[i+1];
7135 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7137 branch_unneeded_reg[i]=1;
7144 // Written registers are unneeded
7145 u|=1LL<<dops[i].rt1;
7146 u|=1LL<<dops[i].rt2;
7148 // Accessed registers are needed
7149 u&=~(1LL<<dops[i].rs1);
7150 u&=~(1LL<<dops[i].rs2);
7152 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7153 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7154 if (dops[i].may_except || dops[i].itype == RFE)
7156 // SYSCALL instruction, etc or conditional exception
7159 // Source-target dependencies
7160 // R0 is always unneeded
7164 gte_unneeded[i]=gte_u;
7166 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7169 for(r=1;r<=CCREG;r++) {
7170 if((unneeded_reg[i]>>r)&1) {
7171 if(r==HIREG) printf(" HI");
7172 else if(r==LOREG) printf(" LO");
7173 else printf(" r%d",r);
7181 static noinline void pass3_register_alloc(u_int addr)
7183 struct regstat current; // Current register allocations/status
7184 clear_all_regs(current.regmap_entry);
7185 clear_all_regs(current.regmap);
7186 current.wasdirty = current.dirty = 0;
7187 current.u = unneeded_reg[0];
7188 alloc_reg(¤t, 0, CCREG);
7189 dirty_reg(¤t, CCREG);
7190 current.wasconst = 0;
7191 current.isconst = 0;
7192 current.loadedconst = 0;
7193 current.noevict = 0;
7194 //current.waswritten = 0;
7201 // First instruction is delay slot
7206 current.regmap[HOST_BTREG]=BTREG;
7213 for(hr=0;hr<HOST_REGS;hr++)
7215 // Is this really necessary?
7216 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7219 //current.waswritten=0;
7222 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7223 regs[i].wasconst=current.isconst;
7224 regs[i].wasdirty=current.dirty;
7228 regs[i].loadedconst=0;
7229 if (!dops[i].is_jump) {
7231 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7238 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7239 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7242 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7248 ds=0; // Skip delay slot, already allocated as part of branch
7249 // ...but we need to alloc it in case something jumps here
7251 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7253 current.u=branch_unneeded_reg[i-1];
7255 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7257 struct regstat temp;
7258 memcpy(&temp,¤t,sizeof(current));
7259 temp.wasdirty=temp.dirty;
7260 // TODO: Take into account unconditional branches, as below
7261 delayslot_alloc(&temp,i);
7262 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7263 regs[i].wasdirty=temp.wasdirty;
7264 regs[i].dirty=temp.dirty;
7268 // Create entry (branch target) regmap
7269 for(hr=0;hr<HOST_REGS;hr++)
7271 int r=temp.regmap[hr];
7273 if(r!=regmap_pre[i][hr]) {
7274 regs[i].regmap_entry[hr]=-1;
7279 if((current.u>>r)&1) {
7280 regs[i].regmap_entry[hr]=-1;
7281 regs[i].regmap[hr]=-1;
7282 //Don't clear regs in the delay slot as the branch might need them
7283 //current.regmap[hr]=-1;
7285 regs[i].regmap_entry[hr]=r;
7288 // First instruction expects CCREG to be allocated
7289 if(i==0&&hr==HOST_CCREG)
7290 regs[i].regmap_entry[hr]=CCREG;
7292 regs[i].regmap_entry[hr]=-1;
7296 else { // Not delay slot
7297 current.noevict = 0;
7298 switch(dops[i].itype) {
7300 //current.isconst=0; // DEBUG
7301 //current.wasconst=0; // DEBUG
7302 //regs[i].wasconst=0; // DEBUG
7303 clear_const(¤t,dops[i].rt1);
7304 alloc_cc(¤t,i);
7305 dirty_reg(¤t,CCREG);
7306 if (dops[i].rt1==31) {
7307 alloc_reg(¤t,i,31);
7308 dirty_reg(¤t,31);
7309 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7310 //assert(dops[i+1].rt1!=dops[i].rt1);
7312 alloc_reg(¤t,i,PTEMP);
7316 delayslot_alloc(¤t,i+1);
7317 //current.isconst=0; // DEBUG
7321 //current.isconst=0;
7322 //current.wasconst=0;
7323 //regs[i].wasconst=0;
7324 clear_const(¤t,dops[i].rs1);
7325 clear_const(¤t,dops[i].rt1);
7326 alloc_cc(¤t,i);
7327 dirty_reg(¤t,CCREG);
7328 if (!ds_writes_rjump_rs(i)) {
7329 alloc_reg(¤t,i,dops[i].rs1);
7330 if (dops[i].rt1!=0) {
7331 alloc_reg(¤t,i,dops[i].rt1);
7332 dirty_reg(¤t,dops[i].rt1);
7334 alloc_reg(¤t,i,PTEMP);
7338 if(dops[i].rs1==31) { // JALR
7339 alloc_reg(¤t,i,RHASH);
7340 alloc_reg(¤t,i,RHTBL);
7343 delayslot_alloc(¤t,i+1);
7345 // The delay slot overwrites our source register,
7346 // allocate a temporary register to hold the old value.
7350 delayslot_alloc(¤t,i+1);
7352 alloc_reg(¤t,i,RTEMP);
7354 //current.isconst=0; // DEBUG
7359 //current.isconst=0;
7360 //current.wasconst=0;
7361 //regs[i].wasconst=0;
7362 clear_const(¤t,dops[i].rs1);
7363 clear_const(¤t,dops[i].rs2);
7364 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7366 alloc_cc(¤t,i);
7367 dirty_reg(¤t,CCREG);
7368 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7369 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7370 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7371 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7372 // The delay slot overwrites one of our conditions.
7373 // Allocate the branch condition registers instead.
7377 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7378 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7383 delayslot_alloc(¤t,i+1);
7387 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7389 alloc_cc(¤t,i);
7390 dirty_reg(¤t,CCREG);
7391 alloc_reg(¤t,i,dops[i].rs1);
7392 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7393 // The delay slot overwrites one of our conditions.
7394 // Allocate the branch condition registers instead.
7398 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7403 delayslot_alloc(¤t,i+1);
7407 // Don't alloc the delay slot yet because we might not execute it
7408 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7413 alloc_cc(¤t,i);
7414 dirty_reg(¤t,CCREG);
7415 alloc_reg(¤t,i,dops[i].rs1);
7416 alloc_reg(¤t,i,dops[i].rs2);
7419 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7424 alloc_cc(¤t,i);
7425 dirty_reg(¤t,CCREG);
7426 alloc_reg(¤t,i,dops[i].rs1);
7429 //current.isconst=0;
7432 clear_const(¤t,dops[i].rs1);
7433 clear_const(¤t,dops[i].rt1);
7435 alloc_cc(¤t,i);
7436 dirty_reg(¤t,CCREG);
7437 alloc_reg(¤t,i,dops[i].rs1);
7438 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
7439 alloc_reg(¤t,i,31);
7440 dirty_reg(¤t,31);
7443 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7444 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
7445 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7446 // Allocate the branch condition registers instead.
7450 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7455 delayslot_alloc(¤t,i+1);
7459 //current.isconst=0;
7462 imm16_alloc(¤t,i);
7466 load_alloc(¤t,i);
7470 store_alloc(¤t,i);
7473 alu_alloc(¤t,i);
7476 shift_alloc(¤t,i);
7479 multdiv_alloc(¤t,i);
7482 shiftimm_alloc(¤t,i);
7485 mov_alloc(¤t,i);
7488 cop0_alloc(¤t,i);
7491 rfe_alloc(¤t,i);
7494 cop2_alloc(¤t,i);
7497 c2ls_alloc(¤t,i);
7500 c2op_alloc(¤t,i);
7505 syscall_alloc(¤t,i);
7509 // Create entry (branch target) regmap
7510 for(hr=0;hr<HOST_REGS;hr++)
7513 r=current.regmap[hr];
7515 if(r!=regmap_pre[i][hr]) {
7516 // TODO: delay slot (?)
7517 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7518 if(or<0||r>=TEMPREG){
7519 regs[i].regmap_entry[hr]=-1;
7523 // Just move it to a different register
7524 regs[i].regmap_entry[hr]=r;
7525 // If it was dirty before, it's still dirty
7526 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
7533 regs[i].regmap_entry[hr]=0;
7538 if((current.u>>r)&1) {
7539 regs[i].regmap_entry[hr]=-1;
7540 //regs[i].regmap[hr]=-1;
7541 current.regmap[hr]=-1;
7543 regs[i].regmap_entry[hr]=r;
7547 // Branches expect CCREG to be allocated at the target
7548 if(regmap_pre[i][hr]==CCREG)
7549 regs[i].regmap_entry[hr]=CCREG;
7551 regs[i].regmap_entry[hr]=-1;
7554 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7557 #if 0 // see do_store_smc_check()
7558 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
7559 current.waswritten|=1<<dops[i-1].rs1;
7560 current.waswritten&=~(1<<dops[i].rt1);
7561 current.waswritten&=~(1<<dops[i].rt2);
7562 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
7563 current.waswritten&=~(1<<dops[i].rs1);
7566 /* Branch post-alloc */
7569 current.wasdirty=current.dirty;
7570 switch(dops[i-1].itype) {
7572 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7573 branch_regs[i-1].isconst=0;
7574 branch_regs[i-1].wasconst=0;
7575 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7576 alloc_cc(&branch_regs[i-1],i-1);
7577 dirty_reg(&branch_regs[i-1],CCREG);
7578 if(dops[i-1].rt1==31) { // JAL
7579 alloc_reg(&branch_regs[i-1],i-1,31);
7580 dirty_reg(&branch_regs[i-1],31);
7582 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7583 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7586 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7587 branch_regs[i-1].isconst=0;
7588 branch_regs[i-1].wasconst=0;
7589 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7590 alloc_cc(&branch_regs[i-1],i-1);
7591 dirty_reg(&branch_regs[i-1],CCREG);
7592 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7593 if(dops[i-1].rt1!=0) { // JALR
7594 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7595 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7598 if(dops[i-1].rs1==31) { // JALR
7599 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7600 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7603 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7604 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7607 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7609 alloc_cc(¤t,i-1);
7610 dirty_reg(¤t,CCREG);
7611 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7612 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7613 // The delay slot overwrote one of our conditions
7614 // Delay slot goes after the test (in order)
7615 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7617 delayslot_alloc(¤t,i);
7622 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7623 // Alloc the branch condition registers
7624 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
7625 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
7627 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7628 branch_regs[i-1].isconst=0;
7629 branch_regs[i-1].wasconst=0;
7630 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7631 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7634 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7636 alloc_cc(¤t,i-1);
7637 dirty_reg(¤t,CCREG);
7638 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7639 // The delay slot overwrote the branch condition
7640 // Delay slot goes after the test (in order)
7641 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7643 delayslot_alloc(¤t,i);
7648 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7649 // Alloc the branch condition register
7650 alloc_reg(¤t,i-1,dops[i-1].rs1);
7652 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7653 branch_regs[i-1].isconst=0;
7654 branch_regs[i-1].wasconst=0;
7655 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7656 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7661 alloc_cc(¤t,i-1);
7662 dirty_reg(¤t,CCREG);
7663 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7664 // The delay slot overwrote the branch condition
7665 // Delay slot goes after the test (in order)
7666 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7668 delayslot_alloc(¤t,i);
7673 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7674 // Alloc the branch condition register
7675 alloc_reg(¤t,i-1,dops[i-1].rs1);
7677 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7678 branch_regs[i-1].isconst=0;
7679 branch_regs[i-1].wasconst=0;
7680 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7681 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7686 if (dops[i-1].is_ujump)
7688 if(dops[i-1].rt1==31) // JAL/JALR
7690 // Subroutine call will return here, don't alloc any registers
7692 clear_all_regs(current.regmap);
7693 alloc_reg(¤t,i,CCREG);
7694 dirty_reg(¤t,CCREG);
7698 // Internal branch will jump here, match registers to caller
7700 clear_all_regs(current.regmap);
7701 alloc_reg(¤t,i,CCREG);
7702 dirty_reg(¤t,CCREG);
7705 if(cinfo[j].ba==start+i*4+4) {
7706 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7707 current.dirty=branch_regs[j].dirty;
7712 if(cinfo[j].ba==start+i*4+4) {
7713 for(hr=0;hr<HOST_REGS;hr++) {
7714 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7715 current.regmap[hr]=-1;
7717 current.dirty&=branch_regs[j].dirty;
7726 // Count cycles in between branches
7727 cinfo[i].ccadj = CLOCK_ADJUST(cc);
7728 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
7732 #if !defined(DRC_DBG)
7733 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
7735 // this should really be removed since the real stalls have been implemented,
7736 // but doing so causes sizeable perf regression against the older version
7737 u_int gtec = gte_cycletab[source[i] & 0x3f];
7738 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7740 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7744 else if(dops[i].itype==C2LS)
7746 // same as with C2OP
7747 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7755 if(!dops[i].is_ds) {
7756 regs[i].dirty=current.dirty;
7757 regs[i].isconst=current.isconst;
7758 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7760 for(hr=0;hr<HOST_REGS;hr++) {
7761 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7762 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7763 regs[i].wasconst&=~(1<<hr);
7767 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7768 //regs[i].waswritten=current.waswritten;
7772 static noinline void pass4_cull_unused_regs(void)
7774 u_int last_needed_regs[4] = {0,0,0,0};
7778 for (i=slen-1;i>=0;i--)
7781 __builtin_prefetch(regs[i-2].regmap);
7784 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7786 // Branch out of this block, don't need anything
7792 // Need whatever matches the target
7794 int t=(cinfo[i].ba-start)>>2;
7795 for(hr=0;hr<HOST_REGS;hr++)
7797 if(regs[i].regmap_entry[hr]>=0) {
7798 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7802 // Conditional branch may need registers for following instructions
7803 if (!dops[i].is_ujump)
7806 nr |= last_needed_regs[(i+2) & 3];
7807 for(hr=0;hr<HOST_REGS;hr++)
7809 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7810 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7814 // Don't need stuff which is overwritten
7815 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7816 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7817 // Merge in delay slot
7818 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7819 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7820 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7821 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7822 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7823 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7824 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7825 nr |= get_regm(regmap_pre[i], ROREG);
7826 nr |= get_regm(regs[i].regmap_entry, ROREG);
7828 if (dops[i+1].is_store) {
7829 nr |= get_regm(regmap_pre[i], INVCP);
7830 nr |= get_regm(regs[i].regmap_entry, INVCP);
7833 else if (dops[i].is_exception)
7835 // SYSCALL instruction, etc
7841 for(hr=0;hr<HOST_REGS;hr++) {
7842 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7843 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7844 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7845 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7849 // Overwritten registers are not needed
7850 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7851 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7852 nr &= ~get_regm(regs[i].regmap, FTEMP);
7853 // Source registers are needed
7854 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7855 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7856 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7857 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7858 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7859 nr |= get_regm(regmap_pre[i], ROREG);
7860 nr |= get_regm(regs[i].regmap_entry, ROREG);
7862 if (dops[i].is_store) {
7863 nr |= get_regm(regmap_pre[i], INVCP);
7864 nr |= get_regm(regs[i].regmap_entry, INVCP);
7867 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7868 for(hr=0;hr<HOST_REGS;hr++)
7870 // Don't store a register immediately after writing it,
7871 // may prevent dual-issue.
7872 // But do so if this is a branch target, otherwise we
7873 // might have to load the register before the branch.
7874 if((regs[i].wasdirty>>hr)&1) {
7875 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7876 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7877 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7879 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7880 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7881 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7885 // Cycle count is needed at branches. Assume it is needed at the target too.
7886 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
7887 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7888 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7891 last_needed_regs[i & 3] = nr;
7893 // Deallocate unneeded registers
7894 for(hr=0;hr<HOST_REGS;hr++)
7897 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7900 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7901 if (dops[i+1].is_load || dops[i+1].is_store)
7903 if (dops[i+1].is_store)
7905 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7907 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7908 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7909 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7910 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7911 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7912 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7913 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7914 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7916 regs[i].regmap[hr]=-1;
7917 regs[i].isconst&=~(1<<hr);
7918 regs[i].dirty&=~(1<<hr);
7919 regs[i+1].wasdirty&=~(1<<hr);
7920 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7921 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7922 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7923 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7924 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7925 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7926 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7927 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7929 branch_regs[i].regmap[hr]=-1;
7930 branch_regs[i].regmap_entry[hr]=-1;
7931 if (!dops[i].is_ujump)
7934 regmap_pre[i+2][hr]=-1;
7935 regs[i+2].wasconst&=~(1<<hr);
7946 int map1 = -1, map2 = -1, temp=-1;
7947 if (dops[i].is_load || dops[i].is_store)
7949 if (dops[i].is_store)
7951 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7953 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7954 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7955 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
7956 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7957 regs[i].regmap[hr] != CCREG)
7959 if(i<slen-1&&!dops[i].is_ds) {
7960 assert(regs[i].regmap[hr]<64);
7961 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
7962 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
7964 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
7965 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7967 regmap_pre[i+1][hr]=-1;
7968 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
7969 regs[i+1].wasconst&=~(1<<hr);
7971 regs[i].regmap[hr]=-1;
7972 regs[i].isconst&=~(1<<hr);
7973 regs[i].dirty&=~(1<<hr);
7974 regs[i+1].wasdirty&=~(1<<hr);
7983 // If a register is allocated during a loop, try to allocate it for the
7984 // entire loop, if possible. This avoids loading/storing registers
7985 // inside of the loop.
7986 static noinline void pass5a_preallocate1(void)
7989 signed char f_regmap[HOST_REGS];
7990 clear_all_regs(f_regmap);
7991 for(i=0;i<slen-1;i++)
7993 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
7995 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
7996 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
7997 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
7998 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
7999 ||dops[i+1].itype==SHIFT
8000 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8002 int t=(cinfo[i].ba-start)>>2;
8003 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8004 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8005 for(hr=0;hr<HOST_REGS;hr++)
8007 if(regs[i].regmap[hr]>=0) {
8008 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8009 // dealloc old register
8011 for(n=0;n<HOST_REGS;n++)
8013 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8015 // and alloc new one
8016 f_regmap[hr]=regs[i].regmap[hr];
8019 if(branch_regs[i].regmap[hr]>=0) {
8020 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8021 // dealloc old register
8023 for(n=0;n<HOST_REGS;n++)
8025 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8027 // and alloc new one
8028 f_regmap[hr]=branch_regs[i].regmap[hr];
8032 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
8033 f_regmap[hr]=branch_regs[i].regmap[hr];
8035 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
8036 f_regmap[hr]=branch_regs[i].regmap[hr];
8038 // Avoid dirty->clean transition
8039 #ifdef DESTRUCTIVE_WRITEBACK
8040 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8042 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8043 // case above, however it's always a good idea. We can't hoist the
8044 // load if the register was already allocated, so there's no point
8045 // wasting time analyzing most of these cases. It only "succeeds"
8046 // when the mapping was different and the load can be replaced with
8047 // a mov, which is of negligible benefit. So such cases are
8049 if(f_regmap[hr]>0) {
8050 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8054 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8055 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8057 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8058 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8060 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8061 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8062 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8064 while(k>1&®s[k-1].regmap[hr]==-1) {
8065 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8066 //printf("no free regs for store %x\n",start+(k-1)*4);
8069 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8070 //printf("no-match due to different register\n");
8073 if (dops[k-2].is_jump) {
8074 //printf("no-match due to branch\n");
8077 // call/ret fast path assumes no registers allocated
8078 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8083 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8084 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8086 regs[k].regmap_entry[hr]=f_regmap[hr];
8087 regs[k].regmap[hr]=f_regmap[hr];
8088 regmap_pre[k+1][hr]=f_regmap[hr];
8089 regs[k].wasdirty&=~(1<<hr);
8090 regs[k].dirty&=~(1<<hr);
8091 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8092 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8093 regs[k].wasconst&=~(1<<hr);
8094 regs[k].isconst&=~(1<<hr);
8099 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8102 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8103 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8104 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8105 regs[i].regmap_entry[hr]=f_regmap[hr];
8106 regs[i].regmap[hr]=f_regmap[hr];
8107 regs[i].wasdirty&=~(1<<hr);
8108 regs[i].dirty&=~(1<<hr);
8109 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8110 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8111 regs[i].wasconst&=~(1<<hr);
8112 regs[i].isconst&=~(1<<hr);
8113 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8114 branch_regs[i].wasdirty&=~(1<<hr);
8115 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8116 branch_regs[i].regmap[hr]=f_regmap[hr];
8117 branch_regs[i].dirty&=~(1<<hr);
8118 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8119 branch_regs[i].wasconst&=~(1<<hr);
8120 branch_regs[i].isconst&=~(1<<hr);
8121 if (!dops[i].is_ujump) {
8122 regmap_pre[i+2][hr]=f_regmap[hr];
8123 regs[i+2].wasdirty&=~(1<<hr);
8124 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8129 // Alloc register clean at beginning of loop,
8130 // but may dirty it in pass 6
8131 regs[k].regmap_entry[hr]=f_regmap[hr];
8132 regs[k].regmap[hr]=f_regmap[hr];
8133 regs[k].dirty&=~(1<<hr);
8134 regs[k].wasconst&=~(1<<hr);
8135 regs[k].isconst&=~(1<<hr);
8136 if (dops[k].is_jump) {
8137 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8138 branch_regs[k].regmap[hr]=f_regmap[hr];
8139 branch_regs[k].dirty&=~(1<<hr);
8140 branch_regs[k].wasconst&=~(1<<hr);
8141 branch_regs[k].isconst&=~(1<<hr);
8142 if (!dops[k].is_ujump) {
8143 regmap_pre[k+2][hr]=f_regmap[hr];
8144 regs[k+2].wasdirty&=~(1<<hr);
8149 regmap_pre[k+1][hr]=f_regmap[hr];
8150 regs[k+1].wasdirty&=~(1<<hr);
8153 if(regs[j].regmap[hr]==f_regmap[hr])
8154 regs[j].regmap_entry[hr]=f_regmap[hr];
8158 if(regs[j].regmap[hr]>=0)
8160 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8161 //printf("no-match due to different register\n");
8164 if (dops[j].is_ujump)
8166 // Stop on unconditional branch
8169 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8172 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
8175 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
8178 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8179 //printf("no-match due to different register (branch)\n");
8183 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8184 //printf("No free regs for store %x\n",start+j*4);
8187 assert(f_regmap[hr]<64);
8194 // Non branch or undetermined branch target
8195 for(hr=0;hr<HOST_REGS;hr++)
8197 if(hr!=EXCLUDE_REG) {
8198 if(regs[i].regmap[hr]>=0) {
8199 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8200 // dealloc old register
8202 for(n=0;n<HOST_REGS;n++)
8204 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8206 // and alloc new one
8207 f_regmap[hr]=regs[i].regmap[hr];
8212 // Try to restore cycle count at branch targets
8214 for(j=i;j<slen-1;j++) {
8215 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8216 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8217 //printf("no free regs for store %x\n",start+j*4);
8221 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8223 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8225 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8226 regs[k].regmap[HOST_CCREG]=CCREG;
8227 regmap_pre[k+1][HOST_CCREG]=CCREG;
8228 regs[k+1].wasdirty|=1<<HOST_CCREG;
8229 regs[k].dirty|=1<<HOST_CCREG;
8230 regs[k].wasconst&=~(1<<HOST_CCREG);
8231 regs[k].isconst&=~(1<<HOST_CCREG);
8234 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8236 // Work backwards from the branch target
8237 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8239 //printf("Extend backwards\n");
8242 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8243 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8244 //printf("no free regs for store %x\n",start+(k-1)*4);
8249 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8250 //printf("Extend CC, %x ->\n",start+k*4);
8252 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8253 regs[k].regmap[HOST_CCREG]=CCREG;
8254 regmap_pre[k+1][HOST_CCREG]=CCREG;
8255 regs[k+1].wasdirty|=1<<HOST_CCREG;
8256 regs[k].dirty|=1<<HOST_CCREG;
8257 regs[k].wasconst&=~(1<<HOST_CCREG);
8258 regs[k].isconst&=~(1<<HOST_CCREG);
8263 //printf("Fail Extend CC, %x ->\n",start+k*4);
8267 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
8268 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8269 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
8271 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8277 // This allocates registers (if possible) one instruction prior
8278 // to use, which can avoid a load-use penalty on certain CPUs.
8279 static noinline void pass5b_preallocate2(void)
8282 for(i=0;i<slen-1;i++)
8284 if (!i || !dops[i-1].is_jump)
8288 int j, can_steal = 1;
8289 for (j = i; j < i + 2; j++) {
8291 if (cinfo[j].min_free_regs == 0)
8293 for (hr = 0; hr < HOST_REGS; hr++)
8294 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8296 if (free_regs <= cinfo[j].min_free_regs) {
8303 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8304 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
8307 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8309 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8311 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8312 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8313 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8314 regs[i].isconst&=~(1<<hr);
8315 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8316 constmap[i][hr]=constmap[i+1][hr];
8317 regs[i+1].wasdirty&=~(1<<hr);
8318 regs[i].dirty&=~(1<<hr);
8323 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8325 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8327 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8328 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8329 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8330 regs[i].isconst&=~(1<<hr);
8331 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8332 constmap[i][hr]=constmap[i+1][hr];
8333 regs[i+1].wasdirty&=~(1<<hr);
8334 regs[i].dirty&=~(1<<hr);
8338 // Preload target address for load instruction (non-constant)
8339 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8340 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8342 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8344 regs[i].regmap[hr]=dops[i+1].rs1;
8345 regmap_pre[i+1][hr]=dops[i+1].rs1;
8346 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8347 regs[i].isconst&=~(1<<hr);
8348 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8349 constmap[i][hr]=constmap[i+1][hr];
8350 regs[i+1].wasdirty&=~(1<<hr);
8351 regs[i].dirty&=~(1<<hr);
8355 // Load source into target register
8356 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8357 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8359 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8361 regs[i].regmap[hr]=dops[i+1].rs1;
8362 regmap_pre[i+1][hr]=dops[i+1].rs1;
8363 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8364 regs[i].isconst&=~(1<<hr);
8365 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8366 constmap[i][hr]=constmap[i+1][hr];
8367 regs[i+1].wasdirty&=~(1<<hr);
8368 regs[i].dirty&=~(1<<hr);
8372 // Address for store instruction (non-constant)
8373 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
8374 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8375 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8376 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8378 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8379 regs[i+1].isconst&=~(1<<hr);
8380 regs[i+1].dirty&=~(1<<hr);
8381 regs[i+2].wasdirty&=~(1<<hr);
8384 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8386 regs[i].regmap[hr]=dops[i+1].rs1;
8387 regmap_pre[i+1][hr]=dops[i+1].rs1;
8388 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8389 regs[i].isconst&=~(1<<hr);
8390 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8391 constmap[i][hr]=constmap[i+1][hr];
8392 regs[i+1].wasdirty&=~(1<<hr);
8393 regs[i].dirty&=~(1<<hr);
8397 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
8398 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8400 hr=get_reg(regs[i+1].regmap,FTEMP);
8402 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8404 regs[i].regmap[hr]=dops[i+1].rs1;
8405 regmap_pre[i+1][hr]=dops[i+1].rs1;
8406 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8407 regs[i].isconst&=~(1<<hr);
8408 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8409 constmap[i][hr]=constmap[i+1][hr];
8410 regs[i+1].wasdirty&=~(1<<hr);
8411 regs[i].dirty&=~(1<<hr);
8413 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8415 // move it to another register
8416 regs[i+1].regmap[hr]=-1;
8417 regmap_pre[i+2][hr]=-1;
8418 regs[i+1].regmap[nr]=FTEMP;
8419 regmap_pre[i+2][nr]=FTEMP;
8420 regs[i].regmap[nr]=dops[i+1].rs1;
8421 regmap_pre[i+1][nr]=dops[i+1].rs1;
8422 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8423 regs[i].isconst&=~(1<<nr);
8424 regs[i+1].isconst&=~(1<<nr);
8425 regs[i].dirty&=~(1<<nr);
8426 regs[i+1].wasdirty&=~(1<<nr);
8427 regs[i+1].dirty&=~(1<<nr);
8428 regs[i+2].wasdirty&=~(1<<nr);
8432 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
8434 if(dops[i+1].itype==LOAD)
8435 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
8436 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
8437 hr=get_reg(regs[i+1].regmap,FTEMP);
8438 if (dops[i+1].is_store) {
8439 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8440 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8442 if(hr>=0&®s[i].regmap[hr]<0) {
8443 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8444 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8445 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8446 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8447 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8448 regs[i].isconst&=~(1<<hr);
8449 regs[i+1].wasdirty&=~(1<<hr);
8450 regs[i].dirty&=~(1<<hr);
8460 // Write back dirty registers as soon as we will no longer modify them,
8461 // so that we don't end up with lots of writes at the branches.
8462 static noinline void pass6_clean_registers(int istart, int iend, int wr)
8464 static u_int wont_dirty[MAXBLOCK];
8465 static u_int will_dirty[MAXBLOCK];
8468 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8469 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8471 will_dirty_i=will_dirty_next=0;
8472 wont_dirty_i=wont_dirty_next=0;
8474 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8475 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8477 for (i=iend;i>=istart;i--)
8479 signed char rregmap_i[RRMAP_SIZE];
8480 u_int hr_candirty = 0;
8481 assert(HOST_REGS < 32);
8482 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8483 __builtin_prefetch(regs[i-1].regmap);
8486 signed char branch_rregmap_i[RRMAP_SIZE];
8487 u_int branch_hr_candirty = 0;
8488 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8489 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
8491 // Branch out of this block, flush all regs
8493 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8494 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8495 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8496 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8497 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8498 will_dirty_i &= branch_hr_candirty;
8499 if (dops[i].is_ujump)
8501 // Unconditional branch
8503 // Merge in delay slot (will dirty)
8504 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8505 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8506 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8507 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8508 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8509 will_dirty_i &= hr_candirty;
8513 // Conditional branch
8514 wont_dirty_i = wont_dirty_next;
8515 // Merge in delay slot (will dirty)
8516 // (the original code had no explanation why these 2 are commented out)
8517 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8518 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8519 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8520 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8521 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8522 will_dirty_i &= hr_candirty;
8524 // Merge in delay slot (wont dirty)
8525 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8526 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8527 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8528 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8529 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8530 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8531 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8532 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8533 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8534 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8535 wont_dirty_i &= ~(1u << 31);
8537 #ifndef DESTRUCTIVE_WRITEBACK
8538 branch_regs[i].dirty&=wont_dirty_i;
8540 branch_regs[i].dirty|=will_dirty_i;
8546 if(cinfo[i].ba<=start+i*4) {
8548 if (dops[i].is_ujump)
8550 // Unconditional branch
8553 // Merge in delay slot (will dirty)
8554 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8555 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8556 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8557 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8558 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8559 temp_will_dirty &= branch_hr_candirty;
8560 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8561 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8562 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8563 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8564 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8565 temp_will_dirty &= hr_candirty;
8567 // Conditional branch (not taken case)
8568 temp_will_dirty=will_dirty_next;
8569 temp_wont_dirty=wont_dirty_next;
8570 // Merge in delay slot (will dirty)
8571 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8572 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8573 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8574 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8575 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8576 temp_will_dirty &= branch_hr_candirty;
8577 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8578 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8579 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8580 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8581 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8582 temp_will_dirty &= hr_candirty;
8584 // Merge in delay slot (wont dirty)
8585 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8586 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8587 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8588 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8589 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8590 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8591 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8592 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8593 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8594 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8595 temp_wont_dirty &= ~(1u << 31);
8596 // Deal with changed mappings
8598 for(r=0;r<HOST_REGS;r++) {
8599 if(r!=EXCLUDE_REG) {
8600 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8601 temp_will_dirty&=~(1<<r);
8602 temp_wont_dirty&=~(1<<r);
8603 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8604 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8605 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8607 temp_will_dirty|=1<<r;
8608 temp_wont_dirty|=1<<r;
8615 will_dirty[i]=temp_will_dirty;
8616 wont_dirty[i]=temp_wont_dirty;
8617 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
8619 // Limit recursion. It can take an excessive amount
8620 // of time if there are a lot of nested loops.
8621 will_dirty[(cinfo[i].ba-start)>>2]=0;
8622 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
8627 if (dops[i].is_ujump)
8629 // Unconditional branch
8632 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
8633 for(r=0;r<HOST_REGS;r++) {
8634 if(r!=EXCLUDE_REG) {
8635 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8636 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8637 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8639 if(branch_regs[i].regmap[r]>=0) {
8640 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8641 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8646 // Merge in delay slot
8647 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8648 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8649 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8650 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8651 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8652 will_dirty_i &= branch_hr_candirty;
8653 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8654 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8655 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8656 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8657 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8658 will_dirty_i &= hr_candirty;
8660 // Conditional branch
8661 will_dirty_i=will_dirty_next;
8662 wont_dirty_i=wont_dirty_next;
8663 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
8664 for(r=0;r<HOST_REGS;r++) {
8665 if(r!=EXCLUDE_REG) {
8666 signed char target_reg=branch_regs[i].regmap[r];
8667 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8668 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8669 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8671 else if(target_reg>=0) {
8672 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8673 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8677 // Merge in delay slot
8678 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8679 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8680 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8681 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8682 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8683 will_dirty_i &= branch_hr_candirty;
8684 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8685 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8686 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8687 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8688 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8689 will_dirty_i &= hr_candirty;
8691 // Merge in delay slot (won't dirty)
8692 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8693 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8694 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8695 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8696 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8697 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8698 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8699 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8700 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8701 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8702 wont_dirty_i &= ~(1u << 31);
8704 #ifndef DESTRUCTIVE_WRITEBACK
8705 branch_regs[i].dirty&=wont_dirty_i;
8707 branch_regs[i].dirty|=will_dirty_i;
8712 else if (dops[i].is_exception)
8714 // SYSCALL instruction, etc
8718 will_dirty_next=will_dirty_i;
8719 wont_dirty_next=wont_dirty_i;
8720 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8721 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8722 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8723 will_dirty_i &= hr_candirty;
8724 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8725 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8726 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8727 wont_dirty_i &= ~(1u << 31);
8728 if (i > istart && !dops[i].is_jump) {
8729 // Don't store a register immediately after writing it,
8730 // may prevent dual-issue.
8731 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8732 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8735 will_dirty[i]=will_dirty_i;
8736 wont_dirty[i]=wont_dirty_i;
8737 // Mark registers that won't be dirtied as not dirty
8739 regs[i].dirty|=will_dirty_i;
8740 #ifndef DESTRUCTIVE_WRITEBACK
8741 regs[i].dirty&=wont_dirty_i;
8744 if (i < iend-1 && !dops[i].is_ujump) {
8745 for(r=0;r<HOST_REGS;r++) {
8746 if(r!=EXCLUDE_REG) {
8747 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8748 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8749 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8757 for(r=0;r<HOST_REGS;r++) {
8758 if(r!=EXCLUDE_REG) {
8759 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8760 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8761 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8768 // Deal with changed mappings
8769 temp_will_dirty=will_dirty_i;
8770 temp_wont_dirty=wont_dirty_i;
8771 for(r=0;r<HOST_REGS;r++) {
8772 if(r!=EXCLUDE_REG) {
8774 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8776 #ifndef DESTRUCTIVE_WRITEBACK
8777 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8779 regs[i].wasdirty|=will_dirty_i&(1<<r);
8782 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8783 // Register moved to a different register
8784 will_dirty_i&=~(1<<r);
8785 wont_dirty_i&=~(1<<r);
8786 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8787 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8789 #ifndef DESTRUCTIVE_WRITEBACK
8790 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8792 regs[i].wasdirty|=will_dirty_i&(1<<r);
8796 will_dirty_i&=~(1<<r);
8797 wont_dirty_i&=~(1<<r);
8798 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8799 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8800 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8803 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8811 static noinline void pass10_expire_blocks(void)
8813 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8814 // not sizeof(ndrc->translation_cache) due to vita hack
8815 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8816 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8817 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8820 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8822 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8823 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8824 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8825 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8826 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8827 (long)(out - ndrc->translation_cache), phase);
8831 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8835 memset(mini_ht, -1, sizeof(mini_ht));
8840 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8844 static struct block_info *new_block_info(u_int start, u_int len,
8845 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8847 struct block_info **b_pptr;
8848 struct block_info *block;
8849 u_int page = get_page(start);
8851 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8853 assert(jump_in_count > 0);
8854 block->source = source;
8856 block->start = start;
8858 block->reg_sv_flags = 0;
8859 block->tc_offs = beginning - ndrc->translation_cache;
8860 //block->tc_len = out - beginning;
8861 block->is_dirty = 0;
8862 block->inv_near_misses = 0;
8863 block->jump_in_cnt = jump_in_count;
8865 // insert sorted by start mirror-unmasked vaddr
8866 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8867 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8868 block->next = *b_pptr;
8873 stat_inc(stat_blocks);
8877 static int new_recompile_block(u_int addr)
8879 u_int pagelimit = 0;
8880 u_int state_rflags = 0;
8883 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8886 if (addr != hack_addr) {
8887 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8893 // this is just for speculation
8894 for (i = 1; i < 32; i++) {
8895 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8896 state_rflags |= 1 << i;
8900 new_dynarec_did_compile=1;
8901 if (Config.HLE && start == 0x80001000) // hlecall
8903 // XXX: is this enough? Maybe check hleSoftCall?
8904 void *beginning = start_block();
8906 emit_movimm(start,0);
8907 emit_writeword(0,&pcaddr);
8908 emit_far_jump(new_dyna_leave);
8910 end_block(beginning);
8911 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8912 block->jump_in[0].vaddr = start;
8913 block->jump_in[0].addr = beginning;
8916 else if (f1_hack && hack_addr == 0) {
8917 void *beginning = start_block();
8918 emit_movimm(start, 0);
8919 emit_writeword(0, &hack_addr);
8920 emit_readword(&psxRegs.GPR.n.sp, 0);
8921 emit_readptr(&mem_rtab, 1);
8922 emit_shrimm(0, 12, 2);
8923 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8924 emit_addimm(0, 0x18, 0);
8925 emit_adds_ptr(1, 1, 1);
8926 emit_ldr_dualindexed(1, 0, 0);
8927 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8928 emit_far_call(ndrc_get_addr_ht);
8929 emit_jmpreg(0); // jr k0
8931 end_block(beginning);
8933 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8934 block->jump_in[0].vaddr = start;
8935 block->jump_in[0].addr = beginning;
8936 SysPrintf("F1 hack to %08x\n", start);
8940 cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
8941 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
8943 source = get_source_start(start, &pagelimit);
8944 if (source == NULL) {
8945 if (addr != hack_addr) {
8946 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8953 /* Pass 1: disassemble */
8954 /* Pass 2: register dependencies, branch targets */
8955 /* Pass 3: register allocation */
8956 /* Pass 4: branch dependencies */
8957 /* Pass 5: pre-alloc */
8958 /* Pass 6: optimize clean/dirty state */
8959 /* Pass 7: flag 32-bit registers */
8960 /* Pass 8: assembly */
8961 /* Pass 9: linker */
8962 /* Pass 10: garbage collection / free memory */
8964 /* Pass 1 disassembly */
8966 pass1_disassemble(pagelimit);
8968 int clear_hack_addr = apply_hacks();
8970 /* Pass 2 - Register dependencies and branch targets */
8972 pass2_unneeded_regs(0,slen-1,0);
8974 /* Pass 3 - Register allocation */
8976 pass3_register_alloc(addr);
8978 /* Pass 4 - Cull unused host registers */
8980 pass4_cull_unused_regs();
8982 /* Pass 5 - Pre-allocate registers */
8984 pass5a_preallocate1();
8985 pass5b_preallocate2();
8987 /* Pass 6 - Optimize clean/dirty state */
8988 pass6_clean_registers(0, slen-1, 1);
8990 /* Pass 7 - Identify 32-bit registers */
8991 for (i=slen-1;i>=0;i--)
8993 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8995 // Conditional branch
8996 if((source[i]>>16)!=0x1000&&i<slen-2) {
8997 // Mark this address as a branch target since it may be called
8998 // upon return from interrupt
9004 /* Pass 8 - Assembly */
9005 linkcount=0;stubcount=0;
9008 void *beginning=start_block();
9009 void *instr_addr0_override = NULL;
9012 if (start == 0x80030000) {
9013 // nasty hack for the fastbios thing
9014 // override block entry to this code
9015 instr_addr0_override = out;
9016 emit_movimm(start,0);
9017 // abuse io address var as a flag that we
9018 // have already returned here once
9019 emit_readword(&address,1);
9020 emit_writeword(0,&pcaddr);
9021 emit_writeword(0,&address);
9024 emit_jeq(out + 4*2);
9025 emit_far_jump(new_dyna_leave);
9027 emit_jne(new_dyna_leave);
9032 __builtin_prefetch(regs[i+1].regmap);
9033 check_regmap(regmap_pre[i]);
9034 check_regmap(regs[i].regmap_entry);
9035 check_regmap(regs[i].regmap);
9036 //if(ds) printf("ds: ");
9037 disassemble_inst(i);
9039 ds=0; // Skip delay slot
9040 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9041 instr_addr[i] = NULL;
9043 speculate_register_values(i);
9044 #ifndef DESTRUCTIVE_WRITEBACK
9045 if (i < 2 || !dops[i-2].is_ujump)
9047 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9049 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9050 dirty_pre=branch_regs[i].dirty;
9052 dirty_pre=regs[i].dirty;
9056 if (i < 2 || !dops[i-2].is_ujump)
9058 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9059 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9061 // branch target entry point
9062 instr_addr[i] = out;
9063 assem_debug("<->\n");
9064 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
9065 if (clear_hack_addr) {
9067 emit_writeword(0, &hack_addr);
9068 clear_hack_addr = 0;
9072 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9073 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9074 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9075 address_generation(i,®s[i],regs[i].regmap_entry);
9076 load_consts(regmap_pre[i],regs[i].regmap,i);
9079 // Load the delay slot registers if necessary
9080 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9081 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9082 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9083 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9084 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9085 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9086 if (dops[i+1].is_store)
9087 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9091 // Preload registers for following instruction
9092 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9093 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9094 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9095 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9096 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9097 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9099 // TODO: if(is_ooo(i)) address_generation(i+1);
9100 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9101 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9102 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9103 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9104 if (dops[i].is_store)
9105 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9107 ds = assemble(i, ®s[i], cinfo[i].ccadj);
9109 if (dops[i].is_ujump)
9112 literal_pool_jumpover(256);
9117 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9118 // no ending needed for this block since INTCALL never returns
9120 // If the block did not end with an unconditional branch,
9121 // add a jump to the next instruction.
9123 if (!dops[i-2].is_ujump) {
9124 assert(!dops[i-1].is_jump);
9126 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9127 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9128 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9129 emit_loadreg(CCREG,HOST_CCREG);
9130 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9134 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9135 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9137 add_to_linker(out,start+i*4,0);
9144 assert(!dops[i-1].is_jump);
9145 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9146 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9147 emit_loadreg(CCREG,HOST_CCREG);
9148 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9149 add_to_linker(out,start+i*4,0);
9154 for(i = 0; i < stubcount; i++)
9156 switch(stubs[i].type)
9163 do_readstub(i);break;
9167 do_writestub(i);break;
9171 do_invstub(i);break;
9173 do_unalignedwritestub(i);break;
9175 do_overflowstub(i); break;
9176 case ALIGNMENT_STUB:
9177 do_alignmentstub(i); break;
9183 if (instr_addr0_override)
9184 instr_addr[0] = instr_addr0_override;
9187 /* check for improper expiration */
9188 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9192 for (j = 0; j < jumps[i]->count; j++)
9193 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9197 /* Pass 9 - Linker */
9198 for(i=0;i<linkcount;i++)
9200 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9202 if (!link_addr[i].internal)
9205 void *addr = check_addr(link_addr[i].target);
9206 emit_extjump(link_addr[i].addr, link_addr[i].target);
9208 set_jump_target(link_addr[i].addr, addr);
9209 ndrc_add_jump_out(link_addr[i].target,stub);
9212 set_jump_target(link_addr[i].addr, stub);
9217 int target=(link_addr[i].target-start)>>2;
9218 assert(target>=0&&target<slen);
9219 assert(instr_addr[target]);
9220 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9221 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9223 set_jump_target(link_addr[i].addr, instr_addr[target]);
9228 u_int source_len = slen*4;
9229 if (dops[slen-1].itype == INTCALL && source_len > 4)
9230 // no need to treat the last instruction as compiled
9231 // as interpreter fully handles it
9234 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9237 // External Branch Targets (jump_in)
9238 int jump_in_count = 1;
9239 assert(instr_addr[0]);
9240 for (i = 1; i < slen; i++)
9242 if (dops[i].bt && instr_addr[i])
9246 struct block_info *block =
9247 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9248 block->reg_sv_flags = state_rflags;
9251 for (i = 0; i < slen; i++)
9253 if ((i == 0 || dops[i].bt) && instr_addr[i])
9255 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9256 u_int vaddr = start + i*4;
9262 entry = instr_addr[i];
9264 emit_jmp(instr_addr[i]);
9266 block->jump_in[jump_in_i].vaddr = vaddr;
9267 block->jump_in[jump_in_i].addr = entry;
9271 assert(jump_in_i == jump_in_count);
9272 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9273 // Write out the literal pool if necessary
9275 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9277 if(((u_int)out)&7) emit_addnop(13);
9279 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9280 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9281 memcpy(copy, source, source_len);
9284 end_block(beginning);
9286 // If we're within 256K of the end of the buffer,
9287 // start over from the beginning. (Is 256K enough?)
9288 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9289 out = ndrc->translation_cache;
9291 // Trap writes to any of the pages we compiled
9292 mark_invalid_code(start, slen*4, 0);
9294 /* Pass 10 - Free memory by expiring oldest blocks */
9296 pass10_expire_blocks();
9301 stat_inc(stat_bc_direct);
9305 // vim:shiftwidth=2:expandtab