57871462 |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * |
20d507ba |
3 | * Copyright (C) 2009-2011 Ari64 * |
57871462 |
4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * |
6 | * it under the terms of the GNU General Public License as published by * |
7 | * the Free Software Foundation; either version 2 of the License, or * |
8 | * (at your option) any later version. * |
9 | * * |
10 | * This program is distributed in the hope that it will be useful, * |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
13 | * GNU General Public License for more details. * |
14 | * * |
15 | * You should have received a copy of the GNU General Public License * |
16 | * along with this program; if not, write to the * |
17 | * Free Software Foundation, Inc., * |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
20 | |
21 | #include <stdlib.h> |
22 | #include <stdint.h> //include for uint64_t |
23 | #include <assert.h> |
d848b60a |
24 | #include <errno.h> |
4600ba03 |
25 | #include <sys/mman.h> |
d148d265 |
26 | #ifdef __MACH__ |
27 | #include <libkern/OSCacheControl.h> |
28 | #endif |
1e212a25 |
29 | #ifdef _3DS |
30 | #include <3ds_utils.h> |
31 | #endif |
3039c914 |
32 | #ifdef HAVE_LIBNX |
33 | #include <switch.h> |
34 | static Jit g_jit; |
35 | #endif |
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36 | |
d148d265 |
37 | #include "new_dynarec_config.h" |
3968e69e |
38 | #include "../psxhle.h" |
39 | #include "../psxinterpreter.h" |
81dbbf4c |
40 | #include "../gte.h" |
41 | #include "emu_if.h" // emulator interface |
a5cd72d0 |
42 | #include "linkage_offsets.h" |
43 | #include "compiler_features.h" |
cdc2da64 |
44 | #include "arm_features.h" |
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45 | |
b14b6a8f |
46 | #ifndef ARRAY_SIZE |
47 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) |
48 | #endif |
e3c6bdb5 |
49 | #ifndef min |
50 | #define min(a, b) ((b) < (a) ? (b) : (a)) |
51 | #endif |
32631e6a |
52 | #ifndef max |
53 | #define max(a, b) ((b) > (a) ? (b) : (a)) |
54 | #endif |
b14b6a8f |
55 | |
4600ba03 |
56 | //#define DISASM |
32631e6a |
57 | //#define ASSEM_PRINT |
a5cd72d0 |
58 | //#define REGMAP_PRINT // with DISASM only |
9b495f6e |
59 | //#define INV_DEBUG_W |
ece032e6 |
60 | //#define STAT_PRINT |
32631e6a |
61 | |
62 | #ifdef ASSEM_PRINT |
63 | #define assem_debug printf |
64 | #else |
4600ba03 |
65 | #define assem_debug(...) |
32631e6a |
66 | #endif |
67 | //#define inv_debug printf |
4600ba03 |
68 | #define inv_debug(...) |
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69 | |
70 | #ifdef __i386__ |
71 | #include "assem_x86.h" |
72 | #endif |
73 | #ifdef __x86_64__ |
74 | #include "assem_x64.h" |
75 | #endif |
76 | #ifdef __arm__ |
77 | #include "assem_arm.h" |
78 | #endif |
be516ebe |
79 | #ifdef __aarch64__ |
80 | #include "assem_arm64.h" |
81 | #endif |
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82 | |
81dbbf4c |
83 | #define RAM_SIZE 0x200000 |
57871462 |
84 | #define MAXBLOCK 4096 |
85 | #define MAX_OUTPUT_BLOCK_SIZE 262144 |
93c0345b |
86 | #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2) |
87 | #define PAGE_COUNT 1024 |
2573466a |
88 | |
882a08fc |
89 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
90 | #define INVALIDATE_USE_COND_CALL |
91 | #endif |
92 | |
66ea165f |
93 | #ifdef VITA |
94 | // apparently Vita has a 16MB limit, so either we cut tc in half, |
95 | // or use this hack (it's a hack because tc size was designed to be power-of-2) |
96 | #define TC_REDUCE_BYTES 4096 |
97 | #else |
98 | #define TC_REDUCE_BYTES 0 |
99 | #endif |
100 | |
d9e2b173 |
101 | struct ndrc_tramp |
102 | { |
103 | struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; |
104 | const void *f[2048 / sizeof(void *)]; |
105 | }; |
106 | |
2a014d73 |
107 | struct ndrc_mem |
108 | { |
66ea165f |
109 | u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES]; |
d9e2b173 |
110 | struct ndrc_tramp tramp; |
2a014d73 |
111 | }; |
112 | |
113 | #ifdef BASE_ADDR_DYNAMIC |
114 | static struct ndrc_mem *ndrc; |
115 | #else |
116 | static struct ndrc_mem ndrc_ __attribute__((aligned(4096))); |
117 | static struct ndrc_mem *ndrc = &ndrc_; |
118 | #endif |
d9e2b173 |
119 | #ifdef TC_WRITE_OFFSET |
3039c914 |
120 | # ifdef __GLIBC__ |
121 | # include <sys/types.h> |
122 | # include <sys/stat.h> |
123 | # include <fcntl.h> |
124 | # include <unistd.h> |
125 | # endif |
126 | static long ndrc_write_ofs; |
d9e2b173 |
127 | #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs) |
3039c914 |
128 | #else |
d9e2b173 |
129 | #define NDRC_WRITE_OFFSET(x) (x) |
3039c914 |
130 | #endif |
2a014d73 |
131 | |
b14b6a8f |
132 | // stubs |
133 | enum stub_type { |
134 | CC_STUB = 1, |
a5cd72d0 |
135 | //FP_STUB = 2, |
b14b6a8f |
136 | LOADB_STUB = 3, |
137 | LOADH_STUB = 4, |
138 | LOADW_STUB = 5, |
a5cd72d0 |
139 | //LOADD_STUB = 6, |
b14b6a8f |
140 | LOADBU_STUB = 7, |
141 | LOADHU_STUB = 8, |
142 | STOREB_STUB = 9, |
143 | STOREH_STUB = 10, |
144 | STOREW_STUB = 11, |
a5cd72d0 |
145 | //STORED_STUB = 12, |
b14b6a8f |
146 | STORELR_STUB = 13, |
147 | INVCODE_STUB = 14, |
a5cd72d0 |
148 | OVERFLOW_STUB = 15, |
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149 | ALIGNMENT_STUB = 16, |
b14b6a8f |
150 | }; |
151 | |
6cc8d23c |
152 | // regmap_pre[i] - regs before [i] insn starts; dirty things here that |
153 | // don't match .regmap will be written back |
154 | // [i].regmap_entry - regs that must be set up if someone jumps here |
155 | // [i].regmap - regs [i] insn will read/(over)write |
2acc46cd |
156 | // branch_regs[i].* - same as above but for branches, takes delay slot into account |
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157 | struct regstat |
158 | { |
6cc8d23c |
159 | signed char regmap_entry[HOST_REGS]; |
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160 | signed char regmap[HOST_REGS]; |
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161 | uint64_t wasdirty; |
162 | uint64_t dirty; |
163 | uint64_t u; |
24058131 |
164 | u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true |
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165 | u_int isconst; // ... but isconst is false when r2 is known (hr) |
8575a877 |
166 | u_int loadedconst; // host regs that have constants loaded |
90f98e7c |
167 | u_int noevict; // can't evict this hr (alloced by current op) |
9b495f6e |
168 | //u_int waswritten; // MIPS regs that were used as store base before |
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169 | }; |
170 | |
df4dc2b1 |
171 | struct ht_entry |
172 | { |
173 | u_int vaddr[2]; |
174 | void *tcaddr[2]; |
175 | }; |
176 | |
b14b6a8f |
177 | struct code_stub |
178 | { |
179 | enum stub_type type; |
180 | void *addr; |
181 | void *retaddr; |
182 | u_int a; |
183 | uintptr_t b; |
184 | uintptr_t c; |
185 | u_int d; |
186 | u_int e; |
187 | }; |
188 | |
643aeae3 |
189 | struct link_entry |
190 | { |
191 | void *addr; |
192 | u_int target; |
104df9d3 |
193 | u_int internal; |
194 | }; |
195 | |
196 | struct block_info |
197 | { |
198 | struct block_info *next; |
199 | const void *source; |
200 | const void *copy; |
201 | u_int start; // vaddr of the block start |
202 | u_int len; // of the whole block source |
203 | u_int tc_offs; |
204 | //u_int tc_len; |
205 | u_int reg_sv_flags; |
3280e616 |
206 | u_char is_dirty; |
207 | u_char inv_near_misses; |
104df9d3 |
208 | u_short jump_in_cnt; |
209 | struct { |
210 | u_int vaddr; |
211 | void *addr; |
212 | } jump_in[0]; |
643aeae3 |
213 | }; |
214 | |
b7ad2f2c |
215 | struct jump_info |
216 | { |
217 | int alloc; |
218 | int count; |
219 | struct { |
220 | u_int target_vaddr; |
221 | void *stub; |
222 | } e[0]; |
223 | }; |
224 | |
cf95b4f0 |
225 | static struct decoded_insn |
226 | { |
227 | u_char itype; |
a5cd72d0 |
228 | u_char opcode; // bits 31-26 |
229 | u_char opcode2; // (depends on opcode) |
cf95b4f0 |
230 | u_char rs1; |
231 | u_char rs2; |
232 | u_char rt1; |
233 | u_char rt2; |
53dc27f6 |
234 | u_char use_lt1:1; |
cf95b4f0 |
235 | u_char bt:1; |
cf95b4f0 |
236 | u_char ooo:1; |
237 | u_char is_ds:1; |
fe807a8a |
238 | u_char is_jump:1; |
239 | u_char is_ujump:1; |
37387d8b |
240 | u_char is_load:1; |
241 | u_char is_store:1; |
a5cd72d0 |
242 | u_char is_delay_load:1; // is_load + MFC/CFC |
243 | u_char is_exception:1; // unconditional, also interp. fallback |
244 | u_char may_except:1; // might generate an exception |
cf95b4f0 |
245 | } dops[MAXBLOCK]; |
246 | |
277718fa |
247 | static struct compile_info |
248 | { |
249 | int imm; |
250 | u_int ba; |
251 | int ccadj; |
252 | signed char min_free_regs; |
253 | signed char addr; |
254 | signed char reserved[2]; |
255 | } cinfo[MAXBLOCK]; |
256 | |
398d6924 |
257 | static u_char *out; |
6d75addf |
258 | static char invalid_code[0x100000]; |
104df9d3 |
259 | static struct ht_entry hash_table[65536]; |
93c0345b |
260 | static struct block_info *blocks[PAGE_COUNT]; |
b7ad2f2c |
261 | static struct jump_info *jumps[PAGE_COUNT]; |
e2b5e7aa |
262 | static u_int start; |
263 | static u_int *source; |
bedfea38 |
264 | static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs |
265 | static uint64_t gte_rt[MAXBLOCK]; |
266 | static uint64_t gte_unneeded[MAXBLOCK]; |
ffb0b9e0 |
267 | static u_int smrv[32]; // speculated MIPS register values |
268 | static u_int smrv_strong; // mask or regs that are likely to have correct values |
269 | static u_int smrv_weak; // same, but somewhat less likely |
270 | static u_int smrv_strong_next; // same, but after current insn executes |
271 | static u_int smrv_weak_next; |
e2b5e7aa |
272 | static uint64_t unneeded_reg[MAXBLOCK]; |
e2b5e7aa |
273 | static uint64_t branch_unneeded_reg[MAXBLOCK]; |
6cc8d23c |
274 | // see 'struct regstat' for a description |
2330734f |
275 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
40fca85b |
276 | // contains 'real' consts at [i] insn, but may differ from what's actually |
277 | // loaded in host reg as 'final' value is always loaded, see get_final_value() |
278 | static uint32_t current_constmap[HOST_REGS]; |
279 | static uint32_t constmap[MAXBLOCK][HOST_REGS]; |
956f3129 |
280 | static struct regstat regs[MAXBLOCK]; |
281 | static struct regstat branch_regs[MAXBLOCK]; |
e2b5e7aa |
282 | static int slen; |
df4dc2b1 |
283 | static void *instr_addr[MAXBLOCK]; |
643aeae3 |
284 | static struct link_entry link_addr[MAXBLOCK]; |
e2b5e7aa |
285 | static int linkcount; |
b14b6a8f |
286 | static struct code_stub stubs[MAXBLOCK*3]; |
e2b5e7aa |
287 | static int stubcount; |
288 | static u_int literals[1024][2]; |
289 | static int literalcount; |
290 | static int is_delayslot; |
e2b5e7aa |
291 | static char shadow[1048576] __attribute__((aligned(16))); |
292 | static void *copy; |
93c0345b |
293 | static u_int expirep; |
e2b5e7aa |
294 | static u_int stop_after_jal; |
7f94b097 |
295 | static u_int f1_hack; |
ece032e6 |
296 | #ifdef STAT_PRINT |
297 | static int stat_bc_direct; |
298 | static int stat_bc_pre; |
299 | static int stat_bc_restore; |
104df9d3 |
300 | static int stat_ht_lookups; |
ece032e6 |
301 | static int stat_jump_in_lookups; |
302 | static int stat_restore_tries; |
303 | static int stat_restore_compares; |
304 | static int stat_inv_addr_calls; |
305 | static int stat_inv_hits; |
104df9d3 |
306 | static int stat_blocks; |
307 | static int stat_links; |
ece032e6 |
308 | #define stat_inc(s) s++ |
104df9d3 |
309 | #define stat_dec(s) s-- |
310 | #define stat_clear(s) s = 0 |
ece032e6 |
311 | #else |
312 | #define stat_inc(s) |
104df9d3 |
313 | #define stat_dec(s) |
314 | #define stat_clear(s) |
ece032e6 |
315 | #endif |
e2b5e7aa |
316 | |
317 | int new_dynarec_hacks; |
d62c125a |
318 | int new_dynarec_hacks_pergame; |
32631e6a |
319 | int new_dynarec_hacks_old; |
e2b5e7aa |
320 | int new_dynarec_did_compile; |
687b4580 |
321 | |
d62c125a |
322 | #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) |
323 | |
de6dbc52 |
324 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG) |
687b4580 |
325 | extern int last_count; // last absolute target, often = next_interupt |
326 | extern int pcaddr; |
327 | extern int pending_exception; |
328 | extern int branch_target; |
37387d8b |
329 | extern uintptr_t ram_offset; |
d1e4ebd9 |
330 | extern uintptr_t mini_ht[32][2]; |
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331 | |
332 | /* registers that may be allocated */ |
333 | /* 1-31 gpr */ |
7c3a5182 |
334 | #define LOREG 32 // lo |
335 | #define HIREG 33 // hi |
00fa9369 |
336 | //#define FSREG 34 // FPU status (FCSR) |
de6dbc52 |
337 | //#define CSREG 35 // Coprocessor status |
57871462 |
338 | #define CCREG 36 // Cycle count |
339 | #define INVCP 37 // Pointer to invalid_code |
1edfcc68 |
340 | //#define MMREG 38 // Pointer to memory_map |
37387d8b |
341 | #define ROREG 39 // ram offset (if rdram!=0x80000000) |
619e5ded |
342 | #define TEMPREG 40 |
343 | #define FTEMP 40 // FPU temporary register |
344 | #define PTEMP 41 // Prefetch temporary register |
1edfcc68 |
345 | //#define TLREG 42 // TLB mapping offset |
619e5ded |
346 | #define RHASH 43 // Return address hash |
347 | #define RHTBL 44 // Return address hash table address |
348 | #define RTEMP 45 // JR/JALR address register |
349 | #define MAXREG 45 |
277718fa |
350 | #define AGEN1 46 // Address generation temporary register (pass5b_preallocate2) |
1edfcc68 |
351 | //#define AGEN2 47 // Address generation temporary register |
619e5ded |
352 | #define BTREG 50 // Branch target temporary register |
57871462 |
353 | |
354 | /* instruction types */ |
355 | #define NOP 0 // No operation |
356 | #define LOAD 1 // Load |
357 | #define STORE 2 // Store |
358 | #define LOADLR 3 // Unaligned load |
359 | #define STORELR 4 // Unaligned store |
a5cd72d0 |
360 | #define MOV 5 // Move (hi/lo only) |
57871462 |
361 | #define ALU 6 // Arithmetic/logic |
362 | #define MULTDIV 7 // Multiply/divide |
363 | #define SHIFT 8 // Shift by register |
364 | #define SHIFTIMM 9// Shift by immediate |
365 | #define IMM16 10 // 16-bit immediate |
366 | #define RJUMP 11 // Unconditional jump to register |
367 | #define UJUMP 12 // Unconditional jump |
368 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) |
369 | #define SJUMP 14 // Conditional branch (regimm format) |
370 | #define COP0 15 // Coprocessor 0 |
a5cd72d0 |
371 | #define RFE 16 |
d1150cd6 |
372 | #define SYSCALL 22// SYSCALL,BREAK |
a5cd72d0 |
373 | #define OTHER 23 // Other/unknown - do nothing |
7139f3c8 |
374 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 |
375 | #define COP2 27 // Coprocessor 2 move |
376 | #define C2LS 28 // Coprocessor 2 load/store |
377 | #define C2OP 29 // Coprocessor 2 operation |
1e973cb0 |
378 | #define INTCALL 30// Call interpreter to handle rare corner cases |
57871462 |
379 | |
57871462 |
380 | /* branch codes */ |
381 | #define TAKEN 1 |
382 | #define NOTTAKEN 2 |
383 | #define NULLDS 3 |
384 | |
7c3a5182 |
385 | #define DJT_1 (void *)1l // no function, just a label in assem_debug log |
386 | #define DJT_2 (void *)2l |
387 | |
57871462 |
388 | // asm linkage |
57871462 |
389 | void dyna_linker(); |
57871462 |
390 | void cc_interrupt(); |
d1150cd6 |
391 | void jump_syscall (u_int u0, u_int u1, u_int pc); |
392 | void jump_syscall_ds(u_int u0, u_int u1, u_int pc); |
393 | void jump_break (u_int u0, u_int u1, u_int pc); |
394 | void jump_break_ds(u_int u0, u_int u1, u_int pc); |
a5cd72d0 |
395 | void jump_overflow (u_int u0, u_int u1, u_int pc); |
396 | void jump_overflow_ds(u_int u0, u_int u1, u_int pc); |
277718fa |
397 | void jump_addrerror (u_int cause, u_int addr, u_int pc); |
398 | void jump_addrerror_ds(u_int cause, u_int addr, u_int pc); |
3968e69e |
399 | void jump_to_new_pc(); |
81dbbf4c |
400 | void call_gteStall(); |
7139f3c8 |
401 | void new_dyna_leave(); |
57871462 |
402 | |
104df9d3 |
403 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile); |
404 | void *ndrc_get_addr_ht(u_int vaddr); |
104df9d3 |
405 | void ndrc_add_jump_out(u_int vaddr, void *src); |
9b495f6e |
406 | void ndrc_write_invalidate_one(u_int addr); |
407 | static void ndrc_write_invalidate_many(u_int addr, u_int end); |
104df9d3 |
408 | |
409 | static int new_recompile_block(u_int addr); |
410 | static void invalidate_block(struct block_info *block); |
a5cd72d0 |
411 | static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_); |
398d6924 |
412 | |
57871462 |
413 | // Needed by assembler |
2330734f |
414 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); |
415 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); |
416 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); |
417 | static void load_all_regs(const signed char i_regmap[]); |
418 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); |
e2b5e7aa |
419 | static void load_regs_entry(int t); |
2330734f |
420 | static void load_all_consts(const signed char regmap[], u_int dirty, int i); |
81dbbf4c |
421 | static u_int get_host_reglist(const signed char *regmap); |
e2b5e7aa |
422 | |
de6dbc52 |
423 | static int get_final_value(int hr, int i, u_int *value); |
b14b6a8f |
424 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
425 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); |
426 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, |
81dbbf4c |
427 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); |
643aeae3 |
428 | static void add_to_linker(void *addr, u_int target, int ext); |
687b4580 |
429 | static void *get_direct_memhandler(void *table, u_int addr, |
430 | enum stub_type type, uintptr_t *addr_host); |
32631e6a |
431 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); |
687b4580 |
432 | static void pass_args(int a0, int a1); |
2a014d73 |
433 | static void emit_far_jump(const void *f); |
434 | static void emit_far_call(const void *f); |
57871462 |
435 | |
9c67c98f |
436 | #ifdef VITA |
437 | #include <psp2/kernel/sysmem.h> |
438 | static int sceBlock; |
439 | // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c |
440 | extern int getVMBlock(); |
441 | int _newlib_vm_size_user = sizeof(*ndrc); |
442 | #endif |
443 | |
d148d265 |
444 | static void mprotect_w_x(void *start, void *end, int is_x) |
445 | { |
446 | #ifdef NO_WRITE_EXEC |
1e212a25 |
447 | #if defined(VITA) |
448 | // *Open* enables write on all memory that was |
449 | // allocated by sceKernelAllocMemBlockForVM()? |
450 | if (is_x) |
451 | sceKernelCloseVMDomain(); |
452 | else |
453 | sceKernelOpenVMDomain(); |
3039c914 |
454 | #elif defined(HAVE_LIBNX) |
455 | Result rc; |
d9e2b173 |
456 | // check to avoid the full flush in jitTransitionToExecutable() |
457 | if (g_jit.type != JitType_CodeMemory) { |
458 | if (is_x) |
459 | rc = jitTransitionToExecutable(&g_jit); |
460 | else |
461 | rc = jitTransitionToWritable(&g_jit); |
462 | if (R_FAILED(rc)) |
463 | ;//SysPrintf("jitTransition %d %08x\n", is_x, rc); |
464 | } |
465 | #elif defined(TC_WRITE_OFFSET) |
3039c914 |
466 | // separated rx and rw areas are always available |
1e212a25 |
467 | #else |
d148d265 |
468 | u_long mstart = (u_long)start & ~4095ul; |
469 | u_long mend = (u_long)end; |
470 | if (mprotect((void *)mstart, mend - mstart, |
471 | PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0) |
472 | SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno)); |
1e212a25 |
473 | #endif |
d148d265 |
474 | #endif |
475 | } |
476 | |
d9e2b173 |
477 | static void start_tcache_write(void *start, void *end) |
d148d265 |
478 | { |
479 | mprotect_w_x(start, end, 0); |
480 | } |
481 | |
482 | static void end_tcache_write(void *start, void *end) |
483 | { |
919981d0 |
484 | #if defined(__arm__) || defined(__aarch64__) |
d148d265 |
485 | size_t len = (char *)end - (char *)start; |
486 | #if defined(__BLACKBERRY_QNX__) |
487 | msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); |
488 | #elif defined(__MACH__) |
489 | sys_cache_control(kCacheFunctionPrepareForExecution, start, len); |
490 | #elif defined(VITA) |
1e212a25 |
491 | sceKernelSyncVMDomain(sceBlock, start, len); |
492 | #elif defined(_3DS) |
493 | ctr_flush_invalidate_cache(); |
3039c914 |
494 | #elif defined(HAVE_LIBNX) |
d9e2b173 |
495 | if (g_jit.type == JitType_CodeMemory) { |
496 | armDCacheClean(start, len); |
497 | armICacheInvalidate((char *)start - ndrc_write_ofs, len); |
aaece508 |
498 | // as of v4.2.1 libnx lacks isb |
499 | __asm__ volatile("isb" ::: "memory"); |
d9e2b173 |
500 | } |
919981d0 |
501 | #elif defined(__aarch64__) |
502 | // as of 2021, __clear_cache() is still broken on arm64 |
503 | // so here is a custom one :( |
504 | clear_cache_arm64(start, end); |
d148d265 |
505 | #else |
506 | __clear_cache(start, end); |
507 | #endif |
508 | (void)len; |
509 | #endif |
510 | |
511 | mprotect_w_x(start, end, 1); |
512 | } |
513 | |
514 | static void *start_block(void) |
515 | { |
516 | u_char *end = out + MAX_OUTPUT_BLOCK_SIZE; |
2a014d73 |
517 | if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache)) |
518 | end = ndrc->translation_cache + sizeof(ndrc->translation_cache); |
d9e2b173 |
519 | start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end)); |
d148d265 |
520 | return out; |
521 | } |
522 | |
523 | static void end_block(void *start) |
524 | { |
d9e2b173 |
525 | end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out)); |
d148d265 |
526 | } |
527 | |
af700b41 |
528 | #ifdef NDRC_CACHE_FLUSH_ALL |
529 | |
530 | static int needs_clear_cache; |
531 | |
532 | static void mark_clear_cache(void *target) |
533 | { |
534 | if (!needs_clear_cache) { |
d9e2b173 |
535 | start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1)); |
af700b41 |
536 | needs_clear_cache = 1; |
537 | } |
538 | } |
539 | |
540 | static void do_clear_cache(void) |
541 | { |
542 | if (needs_clear_cache) { |
d9e2b173 |
543 | end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1)); |
af700b41 |
544 | needs_clear_cache = 0; |
545 | } |
546 | } |
547 | |
548 | #else |
549 | |
919981d0 |
550 | // also takes care of w^x mappings when patching code |
551 | static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; |
552 | |
553 | static void mark_clear_cache(void *target) |
554 | { |
555 | uintptr_t offset = (u_char *)target - ndrc->translation_cache; |
556 | u_int mask = 1u << ((offset >> 12) & 31); |
557 | if (!(needs_clear_cache[offset >> 17] & mask)) { |
d9e2b173 |
558 | char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l); |
919981d0 |
559 | start_tcache_write(start, start + 4095); |
560 | needs_clear_cache[offset >> 17] |= mask; |
561 | } |
562 | } |
563 | |
564 | // Clearing the cache is rather slow on ARM Linux, so mark the areas |
565 | // that need to be cleared, and then only clear these areas once. |
566 | static void do_clear_cache(void) |
567 | { |
568 | int i, j; |
569 | for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++) |
570 | { |
571 | u_int bitmap = needs_clear_cache[i]; |
572 | if (!bitmap) |
573 | continue; |
574 | for (j = 0; j < 32; j++) |
575 | { |
576 | u_char *start, *end; |
93c0345b |
577 | if (!(bitmap & (1u << j))) |
919981d0 |
578 | continue; |
579 | |
580 | start = ndrc->translation_cache + i*131072 + j*4096; |
581 | end = start + 4095; |
582 | for (j++; j < 32; j++) { |
93c0345b |
583 | if (!(bitmap & (1u << j))) |
919981d0 |
584 | break; |
585 | end += 4096; |
586 | } |
d9e2b173 |
587 | end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end)); |
919981d0 |
588 | } |
589 | needs_clear_cache[i] = 0; |
590 | } |
591 | } |
592 | |
af700b41 |
593 | #endif // NDRC_CACHE_FLUSH_ALL |
57871462 |
594 | |
b6e87b2b |
595 | #define NO_CYCLE_PENALTY_THR 12 |
596 | |
32631e6a |
597 | int cycle_multiplier_old; |
24058131 |
598 | static int cycle_multiplier_active; |
4e9dcd7f |
599 | |
600 | static int CLOCK_ADJUST(int x) |
601 | { |
24058131 |
602 | int m = cycle_multiplier_active; |
603 | int s = (x >> 31) | 1; |
a3203cf4 |
604 | return (x * m + s * 50) / 100; |
4e9dcd7f |
605 | } |
606 | |
4919de1e |
607 | static int ds_writes_rjump_rs(int i) |
608 | { |
ecca05e3 |
609 | return dops[i].rs1 != 0 |
610 | && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2 |
611 | || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect |
4919de1e |
612 | } |
613 | |
104df9d3 |
614 | // psx addr mirror masking (for invalidation) |
615 | static u_int pmmask(u_int vaddr) |
616 | { |
617 | vaddr &= ~0xe0000000; |
618 | if (vaddr < 0x01000000) |
619 | vaddr &= ~0x00e00000; // RAM mirrors |
620 | return vaddr; |
621 | } |
622 | |
94d23bb9 |
623 | static u_int get_page(u_int vaddr) |
57871462 |
624 | { |
104df9d3 |
625 | u_int page = pmmask(vaddr) >> 12; |
93c0345b |
626 | if (page >= PAGE_COUNT / 2) |
627 | page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1)); |
94d23bb9 |
628 | return page; |
629 | } |
630 | |
104df9d3 |
631 | // get a page for looking for a block that has vaddr |
632 | // (needed because the block may start in previous page) |
633 | static u_int get_page_prev(u_int vaddr) |
d25604ca |
634 | { |
104df9d3 |
635 | assert(MAXBLOCK <= (1 << 12)); |
636 | u_int page = get_page(vaddr); |
637 | if (page & 511) |
638 | page--; |
639 | return page; |
d25604ca |
640 | } |
94d23bb9 |
641 | |
df4dc2b1 |
642 | static struct ht_entry *hash_table_get(u_int vaddr) |
643 | { |
644 | return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
645 | } |
646 | |
104df9d3 |
647 | static void hash_table_add(u_int vaddr, void *tcaddr) |
df4dc2b1 |
648 | { |
104df9d3 |
649 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
650 | assert(tcaddr); |
df4dc2b1 |
651 | ht_bin->vaddr[1] = ht_bin->vaddr[0]; |
652 | ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; |
653 | ht_bin->vaddr[0] = vaddr; |
654 | ht_bin->tcaddr[0] = tcaddr; |
655 | } |
656 | |
104df9d3 |
657 | static void hash_table_remove(int vaddr) |
658 | { |
659 | //printf("remove hash: %x\n",vaddr); |
660 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
661 | if (ht_bin->vaddr[1] == vaddr) { |
662 | ht_bin->vaddr[1] = -1; |
663 | ht_bin->tcaddr[1] = NULL; |
664 | } |
665 | if (ht_bin->vaddr[0] == vaddr) { |
666 | ht_bin->vaddr[0] = ht_bin->vaddr[1]; |
667 | ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; |
668 | ht_bin->vaddr[1] = -1; |
669 | ht_bin->tcaddr[1] = NULL; |
670 | } |
671 | } |
672 | |
673 | static void mark_invalid_code(u_int vaddr, u_int len, char invalid) |
398d6924 |
674 | { |
ab4377be |
675 | u_int vaddr_m = vaddr & 0x1fffffff; |
398d6924 |
676 | u_int i, j; |
ab4377be |
677 | for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) { |
398d6924 |
678 | // ram mirrors, but should not hurt bios |
679 | for (j = 0; j < 0x800000; j += 0x200000) { |
680 | invalid_code[(i|j) >> 12] = |
681 | invalid_code[(i|j|0x80000000u) >> 12] = |
104df9d3 |
682 | invalid_code[(i|j|0xa0000000u) >> 12] = invalid; |
398d6924 |
683 | } |
684 | } |
882a08fc |
685 | if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end) |
104df9d3 |
686 | inv_code_start = inv_code_end = ~0; |
398d6924 |
687 | } |
688 | |
93c0345b |
689 | static int doesnt_expire_soon(u_char *tcaddr) |
df4dc2b1 |
690 | { |
93c0345b |
691 | u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u); |
692 | return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE; |
df4dc2b1 |
693 | } |
694 | |
9b495f6e |
695 | static unused void check_for_block_changes(u_int start, u_int end) |
696 | { |
697 | u_int start_page = get_page_prev(start); |
698 | u_int end_page = get_page(end - 1); |
699 | u_int page; |
700 | |
701 | for (page = start_page; page <= end_page; page++) { |
702 | struct block_info *block; |
703 | for (block = blocks[page]; block != NULL; block = block->next) { |
704 | if (block->is_dirty) |
705 | continue; |
706 | if (memcmp(block->source, block->copy, block->len)) { |
707 | printf("bad block %08x-%08x %016llx %016llx @%08x\n", |
708 | block->start, block->start + block->len, |
709 | *(long long *)block->source, *(long long *)block->copy, psxRegs.pc); |
710 | fflush(stdout); |
711 | abort(); |
712 | } |
713 | } |
714 | } |
715 | } |
716 | |
104df9d3 |
717 | static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) |
398d6924 |
718 | { |
104df9d3 |
719 | void *found_clean = NULL; |
720 | u_int i, page; |
398d6924 |
721 | |
ece032e6 |
722 | stat_inc(stat_restore_tries); |
104df9d3 |
723 | for (page = start_page; page <= end_page; page++) { |
724 | struct block_info *block; |
725 | for (block = blocks[page]; block != NULL; block = block->next) { |
726 | if (vaddr < block->start) |
727 | break; |
728 | if (!block->is_dirty || vaddr >= block->start + block->len) |
729 | continue; |
730 | for (i = 0; i < block->jump_in_cnt; i++) |
731 | if (block->jump_in[i].vaddr == vaddr) |
732 | break; |
733 | if (i == block->jump_in_cnt) |
734 | continue; |
735 | assert(block->source && block->copy); |
736 | stat_inc(stat_restore_compares); |
737 | if (memcmp(block->source, block->copy, block->len)) |
738 | continue; |
398d6924 |
739 | |
3280e616 |
740 | block->is_dirty = block->inv_near_misses = 0; |
104df9d3 |
741 | found_clean = block->jump_in[i].addr; |
742 | hash_table_add(vaddr, found_clean); |
743 | mark_invalid_code(block->start, block->len, 0); |
744 | stat_inc(stat_bc_restore); |
745 | inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt); |
746 | return found_clean; |
398d6924 |
747 | } |
398d6924 |
748 | } |
104df9d3 |
749 | return NULL; |
398d6924 |
750 | } |
751 | |
de6dbc52 |
752 | // this doesn't normally happen |
753 | static noinline u_int generate_exception(u_int pc) |
754 | { |
755 | //if (execBreakCheck(&psxRegs, pc)) |
756 | // return psxRegs.pc; |
757 | |
758 | // generate an address or bus error |
759 | psxRegs.CP0.n.Cause &= 0x300; |
760 | psxRegs.CP0.n.EPC = pc; |
761 | if (pc & 3) { |
762 | psxRegs.CP0.n.Cause |= R3000E_AdEL << 2; |
763 | psxRegs.CP0.n.BadVAddr = pc; |
764 | #ifdef DRC_DBG |
765 | last_count -= 2; |
766 | #endif |
767 | } else |
768 | psxRegs.CP0.n.Cause |= R3000E_IBE << 2; |
769 | return (psxRegs.pc = 0x80000080); |
770 | } |
771 | |
94d23bb9 |
772 | // Get address from virtual address |
773 | // This is called from the recompiled JR/JALR instructions |
104df9d3 |
774 | static void noinline *get_addr(u_int vaddr, int can_compile) |
94d23bb9 |
775 | { |
104df9d3 |
776 | u_int start_page = get_page_prev(vaddr); |
777 | u_int i, page, end_page = get_page(vaddr); |
778 | void *found_clean = NULL; |
398d6924 |
779 | |
ece032e6 |
780 | stat_inc(stat_jump_in_lookups); |
104df9d3 |
781 | for (page = start_page; page <= end_page; page++) { |
782 | const struct block_info *block; |
783 | for (block = blocks[page]; block != NULL; block = block->next) { |
784 | if (vaddr < block->start) |
785 | break; |
786 | if (block->is_dirty || vaddr >= block->start + block->len) |
787 | continue; |
788 | for (i = 0; i < block->jump_in_cnt; i++) |
789 | if (block->jump_in[i].vaddr == vaddr) |
790 | break; |
791 | if (i == block->jump_in_cnt) |
792 | continue; |
793 | found_clean = block->jump_in[i].addr; |
794 | hash_table_add(vaddr, found_clean); |
795 | return found_clean; |
57871462 |
796 | } |
57871462 |
797 | } |
104df9d3 |
798 | found_clean = try_restore_block(vaddr, start_page, end_page); |
799 | if (found_clean) |
800 | return found_clean; |
801 | |
802 | if (!can_compile) |
803 | return NULL; |
398d6924 |
804 | |
805 | int r = new_recompile_block(vaddr); |
de6dbc52 |
806 | if (likely(r == 0)) |
104df9d3 |
807 | return ndrc_get_addr_ht(vaddr); |
df4dc2b1 |
808 | |
de6dbc52 |
809 | return ndrc_get_addr_ht(generate_exception(vaddr)); |
57871462 |
810 | } |
104df9d3 |
811 | |
57871462 |
812 | // Look up address in hash table first |
104df9d3 |
813 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile) |
57871462 |
814 | { |
9b495f6e |
815 | //check_for_block_changes(vaddr, vaddr + MAXBLOCK); |
df4dc2b1 |
816 | const struct ht_entry *ht_bin = hash_table_get(vaddr); |
277718fa |
817 | u_int vaddr_a = vaddr & ~3; |
104df9d3 |
818 | stat_inc(stat_ht_lookups); |
277718fa |
819 | if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0]; |
820 | if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1]; |
104df9d3 |
821 | return get_addr(vaddr, can_compile); |
822 | } |
823 | |
824 | void *ndrc_get_addr_ht(u_int vaddr) |
825 | { |
826 | return ndrc_get_addr_ht_param(vaddr, 1); |
57871462 |
827 | } |
828 | |
6cc8d23c |
829 | static void clear_all_regs(signed char regmap[]) |
57871462 |
830 | { |
6cc8d23c |
831 | memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); |
57871462 |
832 | } |
833 | |
53358c1d |
834 | // get_reg: get allocated host reg from mips reg |
835 | // returns -1 if no such mips reg was allocated |
cdc2da64 |
836 | #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11 |
837 | |
838 | extern signed char get_reg(const signed char regmap[], signed char r); |
839 | |
840 | #else |
841 | |
9de8a0c3 |
842 | static signed char get_reg(const signed char regmap[], signed char r) |
57871462 |
843 | { |
844 | int hr; |
9de8a0c3 |
845 | for (hr = 0; hr < HOST_REGS; hr++) { |
846 | if (hr == EXCLUDE_REG) |
847 | continue; |
848 | if (regmap[hr] == r) |
849 | return hr; |
850 | } |
851 | return -1; |
852 | } |
853 | |
cdc2da64 |
854 | #endif |
855 | |
a5cd72d0 |
856 | // get reg suitable for writing |
857 | static signed char get_reg_w(const signed char regmap[], signed char r) |
858 | { |
859 | return r == 0 ? -1 : get_reg(regmap, r); |
860 | } |
861 | |
53358c1d |
862 | // get reg as mask bit (1 << hr) |
863 | static u_int get_regm(const signed char regmap[], signed char r) |
864 | { |
865 | return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31); |
866 | } |
867 | |
9de8a0c3 |
868 | static signed char get_reg_temp(const signed char regmap[]) |
869 | { |
870 | int hr; |
871 | for (hr = 0; hr < HOST_REGS; hr++) { |
872 | if (hr == EXCLUDE_REG) |
873 | continue; |
874 | if (regmap[hr] == (signed char)-1) |
875 | return hr; |
876 | } |
57871462 |
877 | return -1; |
878 | } |
879 | |
880 | // Find a register that is available for two consecutive cycles |
d1e4ebd9 |
881 | static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r) |
57871462 |
882 | { |
883 | int hr; |
884 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; |
885 | return -1; |
886 | } |
887 | |
53dc27f6 |
888 | // reverse reg map: mips -> host |
889 | #define RRMAP_SIZE 64 |
890 | static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE], |
891 | u_int *regs_can_change) |
892 | { |
893 | u_int r, hr, hr_can_change = 0; |
894 | memset(rrmap, -1, RRMAP_SIZE); |
895 | for (hr = 0; hr < HOST_REGS; ) |
896 | { |
897 | r = regmap[hr]; |
898 | rrmap[r & (RRMAP_SIZE - 1)] = hr; |
899 | // only add mips $1-$31+$lo, others shifted out |
900 | hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32)); |
901 | hr++; |
902 | if (hr == EXCLUDE_REG) |
903 | hr++; |
904 | } |
905 | hr_can_change |= 1u << (rrmap[33] & 31); |
906 | hr_can_change |= 1u << (rrmap[CCREG] & 31); |
907 | hr_can_change &= ~(1u << 31); |
908 | *regs_can_change = hr_can_change; |
909 | } |
910 | |
911 | // same as get_reg, but takes rrmap |
912 | static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r) |
913 | { |
914 | assert(0 <= r && r < RRMAP_SIZE); |
915 | return rrmap[r]; |
916 | } |
917 | |
9de8a0c3 |
918 | static int count_free_regs(const signed char regmap[]) |
57871462 |
919 | { |
920 | int count=0; |
921 | int hr; |
922 | for(hr=0;hr<HOST_REGS;hr++) |
923 | { |
924 | if(hr!=EXCLUDE_REG) { |
925 | if(regmap[hr]<0) count++; |
926 | } |
927 | } |
928 | return count; |
929 | } |
930 | |
9de8a0c3 |
931 | static void dirty_reg(struct regstat *cur, signed char reg) |
57871462 |
932 | { |
933 | int hr; |
9de8a0c3 |
934 | if (!reg) return; |
935 | hr = get_reg(cur->regmap, reg); |
936 | if (hr >= 0) |
937 | cur->dirty |= 1<<hr; |
57871462 |
938 | } |
939 | |
40fca85b |
940 | static void set_const(struct regstat *cur, signed char reg, uint32_t value) |
57871462 |
941 | { |
942 | int hr; |
9de8a0c3 |
943 | if (!reg) return; |
944 | hr = get_reg(cur->regmap, reg); |
945 | if (hr >= 0) { |
946 | cur->isconst |= 1<<hr; |
947 | current_constmap[hr] = value; |
57871462 |
948 | } |
949 | } |
950 | |
40fca85b |
951 | static void clear_const(struct regstat *cur, signed char reg) |
57871462 |
952 | { |
953 | int hr; |
9de8a0c3 |
954 | if (!reg) return; |
955 | hr = get_reg(cur->regmap, reg); |
956 | if (hr >= 0) |
957 | cur->isconst &= ~(1<<hr); |
57871462 |
958 | } |
959 | |
9de8a0c3 |
960 | static int is_const(const struct regstat *cur, signed char reg) |
57871462 |
961 | { |
962 | int hr; |
9de8a0c3 |
963 | if (reg < 0) return 0; |
964 | if (!reg) return 1; |
965 | hr = get_reg(cur->regmap, reg); |
966 | if (hr >= 0) |
967 | return (cur->isconst>>hr)&1; |
57871462 |
968 | return 0; |
969 | } |
40fca85b |
970 | |
9de8a0c3 |
971 | static uint32_t get_const(const struct regstat *cur, signed char reg) |
57871462 |
972 | { |
973 | int hr; |
9de8a0c3 |
974 | if (!reg) return 0; |
975 | hr = get_reg(cur->regmap, reg); |
976 | if (hr >= 0) |
977 | return current_constmap[hr]; |
978 | |
979 | SysPrintf("Unknown constant in r%d\n", reg); |
7c3a5182 |
980 | abort(); |
57871462 |
981 | } |
982 | |
983 | // Least soon needed registers |
984 | // Look at the next ten instructions and see which registers |
985 | // will be used. Try not to reallocate these. |
90f98e7c |
986 | static void lsn(u_char hsn[], int i) |
57871462 |
987 | { |
988 | int j; |
989 | int b=-1; |
990 | for(j=0;j<9;j++) |
991 | { |
992 | if(i+j>=slen) { |
993 | j=slen-i-1; |
994 | break; |
995 | } |
fe807a8a |
996 | if (dops[i+j].is_ujump) |
57871462 |
997 | { |
998 | // Don't go past an unconditonal jump |
999 | j++; |
1000 | break; |
1001 | } |
1002 | } |
1003 | for(;j>=0;j--) |
1004 | { |
cf95b4f0 |
1005 | if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j; |
1006 | if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j; |
1007 | if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j; |
1008 | if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j; |
1009 | if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) { |
57871462 |
1010 | // Stores can allocate zero |
cf95b4f0 |
1011 | hsn[dops[i+j].rs1]=j; |
1012 | hsn[dops[i+j].rs2]=j; |
57871462 |
1013 | } |
37387d8b |
1014 | if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) |
1015 | hsn[ROREG] = j; |
57871462 |
1016 | // On some architectures stores need invc_ptr |
1017 | #if defined(HOST_IMM8) |
37387d8b |
1018 | if (dops[i+j].is_store) |
1019 | hsn[INVCP] = j; |
57871462 |
1020 | #endif |
cf95b4f0 |
1021 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 |
1022 | { |
1023 | hsn[CCREG]=j; |
1024 | b=j; |
1025 | } |
1026 | } |
1027 | if(b>=0) |
1028 | { |
277718fa |
1029 | if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4)) |
57871462 |
1030 | { |
1031 | // Follow first branch |
277718fa |
1032 | int t=(cinfo[i+b].ba-start)>>2; |
57871462 |
1033 | j=7-b;if(t+j>=slen) j=slen-t-1; |
1034 | for(;j>=0;j--) |
1035 | { |
cf95b4f0 |
1036 | if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2; |
1037 | if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2; |
1038 | //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2; |
1039 | //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2; |
57871462 |
1040 | } |
1041 | } |
1042 | // TODO: preferred register based on backward branch |
1043 | } |
1044 | // Delay slot should preferably not overwrite branch conditions or cycle count |
fe807a8a |
1045 | if (i > 0 && dops[i-1].is_jump) { |
cf95b4f0 |
1046 | if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; |
1047 | if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; |
57871462 |
1048 | hsn[CCREG]=1; |
1049 | // ...or hash tables |
1050 | hsn[RHASH]=1; |
1051 | hsn[RHTBL]=1; |
1052 | } |
1053 | // Coprocessor load/store needs FTEMP, even if not declared |
37387d8b |
1054 | if(dops[i].itype==C2LS) { |
57871462 |
1055 | hsn[FTEMP]=0; |
1056 | } |
1057 | // Load L/R also uses FTEMP as a temporary register |
cf95b4f0 |
1058 | if(dops[i].itype==LOADLR) { |
57871462 |
1059 | hsn[FTEMP]=0; |
1060 | } |
b7918751 |
1061 | // Also SWL/SWR/SDL/SDR |
cf95b4f0 |
1062 | if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { |
57871462 |
1063 | hsn[FTEMP]=0; |
1064 | } |
57871462 |
1065 | // Don't remove the miniht registers |
cf95b4f0 |
1066 | if(dops[i].itype==UJUMP||dops[i].itype==RJUMP) |
57871462 |
1067 | { |
1068 | hsn[RHASH]=0; |
1069 | hsn[RHTBL]=0; |
1070 | } |
1071 | } |
1072 | |
1073 | // We only want to allocate registers if we're going to use them again soon |
4149788d |
1074 | static int needed_again(int r, int i) |
57871462 |
1075 | { |
1076 | int j; |
1077 | int b=-1; |
1078 | int rn=10; |
9f51b4b9 |
1079 | |
fe807a8a |
1080 | if (i > 0 && dops[i-1].is_ujump) |
57871462 |
1081 | { |
277718fa |
1082 | if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4) |
57871462 |
1083 | return 0; // Don't need any registers if exiting the block |
1084 | } |
1085 | for(j=0;j<9;j++) |
1086 | { |
1087 | if(i+j>=slen) { |
1088 | j=slen-i-1; |
1089 | break; |
1090 | } |
fe807a8a |
1091 | if (dops[i+j].is_ujump) |
57871462 |
1092 | { |
1093 | // Don't go past an unconditonal jump |
1094 | j++; |
1095 | break; |
1096 | } |
a5cd72d0 |
1097 | if (dops[i+j].is_exception) |
57871462 |
1098 | { |
1099 | break; |
1100 | } |
1101 | } |
1102 | for(;j>=1;j--) |
1103 | { |
cf95b4f0 |
1104 | if(dops[i+j].rs1==r) rn=j; |
1105 | if(dops[i+j].rs2==r) rn=j; |
57871462 |
1106 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
cf95b4f0 |
1107 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 |
1108 | { |
1109 | b=j; |
1110 | } |
1111 | } |
b7217e13 |
1112 | if(rn<10) return 1; |
581335b0 |
1113 | (void)b; |
57871462 |
1114 | return 0; |
1115 | } |
1116 | |
1117 | // Try to match register allocations at the end of a loop with those |
1118 | // at the beginning |
4149788d |
1119 | static int loop_reg(int i, int r, int hr) |
57871462 |
1120 | { |
1121 | int j,k; |
1122 | for(j=0;j<9;j++) |
1123 | { |
1124 | if(i+j>=slen) { |
1125 | j=slen-i-1; |
1126 | break; |
1127 | } |
fe807a8a |
1128 | if (dops[i+j].is_ujump) |
57871462 |
1129 | { |
1130 | // Don't go past an unconditonal jump |
1131 | j++; |
1132 | break; |
1133 | } |
1134 | } |
1135 | k=0; |
1136 | if(i>0){ |
cf95b4f0 |
1137 | if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP) |
57871462 |
1138 | k--; |
1139 | } |
1140 | for(;k<j;k++) |
1141 | { |
00fa9369 |
1142 | assert(r < 64); |
1143 | if((unneeded_reg[i+k]>>r)&1) return hr; |
cf95b4f0 |
1144 | if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP)) |
57871462 |
1145 | { |
277718fa |
1146 | if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4)) |
57871462 |
1147 | { |
277718fa |
1148 | int t=(cinfo[i+k].ba-start)>>2; |
57871462 |
1149 | int reg=get_reg(regs[t].regmap_entry,r); |
1150 | if(reg>=0) return reg; |
1151 | //reg=get_reg(regs[t+1].regmap_entry,r); |
1152 | //if(reg>=0) return reg; |
1153 | } |
1154 | } |
1155 | } |
1156 | return hr; |
1157 | } |
1158 | |
1159 | |
1160 | // Allocate every register, preserving source/target regs |
4149788d |
1161 | static void alloc_all(struct regstat *cur,int i) |
57871462 |
1162 | { |
1163 | int hr; |
9f51b4b9 |
1164 | |
57871462 |
1165 | for(hr=0;hr<HOST_REGS;hr++) { |
1166 | if(hr!=EXCLUDE_REG) { |
9de8a0c3 |
1167 | if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& |
1168 | (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) |
57871462 |
1169 | { |
1170 | cur->regmap[hr]=-1; |
1171 | cur->dirty&=~(1<<hr); |
1172 | } |
1173 | // Don't need zeros |
9de8a0c3 |
1174 | if(cur->regmap[hr]==0) |
57871462 |
1175 | { |
1176 | cur->regmap[hr]=-1; |
1177 | cur->dirty&=~(1<<hr); |
1178 | } |
1179 | } |
1180 | } |
1181 | } |
1182 | |
d1e4ebd9 |
1183 | #ifndef NDEBUG |
1184 | static int host_tempreg_in_use; |
1185 | |
1186 | static void host_tempreg_acquire(void) |
1187 | { |
1188 | assert(!host_tempreg_in_use); |
1189 | host_tempreg_in_use = 1; |
1190 | } |
1191 | |
1192 | static void host_tempreg_release(void) |
1193 | { |
1194 | host_tempreg_in_use = 0; |
1195 | } |
1196 | #else |
1197 | static void host_tempreg_acquire(void) {} |
1198 | static void host_tempreg_release(void) {} |
1199 | #endif |
1200 | |
32631e6a |
1201 | #ifdef ASSEM_PRINT |
8062d65a |
1202 | extern void gen_interupt(); |
1203 | extern void do_insn_cmp(); |
d1e4ebd9 |
1204 | #define FUNCNAME(f) { f, " " #f } |
8062d65a |
1205 | static const struct { |
d1e4ebd9 |
1206 | void *addr; |
8062d65a |
1207 | const char *name; |
1208 | } function_names[] = { |
1209 | FUNCNAME(cc_interrupt), |
1210 | FUNCNAME(gen_interupt), |
104df9d3 |
1211 | FUNCNAME(ndrc_get_addr_ht), |
8062d65a |
1212 | FUNCNAME(jump_handler_read8), |
1213 | FUNCNAME(jump_handler_read16), |
1214 | FUNCNAME(jump_handler_read32), |
1215 | FUNCNAME(jump_handler_write8), |
1216 | FUNCNAME(jump_handler_write16), |
1217 | FUNCNAME(jump_handler_write32), |
9b495f6e |
1218 | FUNCNAME(ndrc_write_invalidate_one), |
1219 | FUNCNAME(ndrc_write_invalidate_many), |
3968e69e |
1220 | FUNCNAME(jump_to_new_pc), |
d1150cd6 |
1221 | FUNCNAME(jump_break), |
1222 | FUNCNAME(jump_break_ds), |
1223 | FUNCNAME(jump_syscall), |
1224 | FUNCNAME(jump_syscall_ds), |
a5cd72d0 |
1225 | FUNCNAME(jump_overflow), |
1226 | FUNCNAME(jump_overflow_ds), |
277718fa |
1227 | FUNCNAME(jump_addrerror), |
1228 | FUNCNAME(jump_addrerror_ds), |
81dbbf4c |
1229 | FUNCNAME(call_gteStall), |
8062d65a |
1230 | FUNCNAME(new_dyna_leave), |
1231 | FUNCNAME(pcsx_mtc0), |
1232 | FUNCNAME(pcsx_mtc0_ds), |
277718fa |
1233 | FUNCNAME(execI), |
1234 | #ifdef __aarch64__ |
1235 | FUNCNAME(do_memhandler_pre), |
1236 | FUNCNAME(do_memhandler_post), |
1237 | #endif |
32631e6a |
1238 | #ifdef DRC_DBG |
8062d65a |
1239 | FUNCNAME(do_insn_cmp), |
32631e6a |
1240 | #endif |
8062d65a |
1241 | }; |
1242 | |
d1e4ebd9 |
1243 | static const char *func_name(const void *a) |
8062d65a |
1244 | { |
1245 | int i; |
1246 | for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++) |
1247 | if (function_names[i].addr == a) |
1248 | return function_names[i].name; |
1249 | return ""; |
1250 | } |
a5cd72d0 |
1251 | |
1252 | static const char *fpofs_name(u_int ofs) |
1253 | { |
1254 | u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int); |
1255 | static char buf[64]; |
1256 | switch (ofs) { |
1257 | #define ofscase(x) case LO_##x: return " ; " #x |
1258 | ofscase(next_interupt); |
de6dbc52 |
1259 | ofscase(cycle_count); |
a5cd72d0 |
1260 | ofscase(last_count); |
1261 | ofscase(pending_exception); |
1262 | ofscase(stop); |
1263 | ofscase(address); |
1264 | ofscase(lo); |
1265 | ofscase(hi); |
1266 | ofscase(PC); |
1267 | ofscase(cycle); |
1268 | ofscase(mem_rtab); |
1269 | ofscase(mem_wtab); |
1270 | ofscase(psxH_ptr); |
1271 | ofscase(invc_ptr); |
1272 | ofscase(ram_offset); |
1273 | #undef ofscase |
1274 | } |
1275 | buf[0] = 0; |
1276 | if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32]) |
1277 | snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r)); |
1278 | else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32]) |
1279 | snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r)); |
1280 | else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32]) |
1281 | snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r)); |
1282 | else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32]) |
1283 | snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r)); |
1284 | return buf; |
1285 | } |
8062d65a |
1286 | #else |
1287 | #define func_name(x) "" |
a5cd72d0 |
1288 | #define fpofs_name(x) "" |
8062d65a |
1289 | #endif |
1290 | |
57871462 |
1291 | #ifdef __i386__ |
1292 | #include "assem_x86.c" |
1293 | #endif |
1294 | #ifdef __x86_64__ |
1295 | #include "assem_x64.c" |
1296 | #endif |
1297 | #ifdef __arm__ |
1298 | #include "assem_arm.c" |
1299 | #endif |
be516ebe |
1300 | #ifdef __aarch64__ |
1301 | #include "assem_arm64.c" |
1302 | #endif |
57871462 |
1303 | |
2a014d73 |
1304 | static void *get_trampoline(const void *f) |
1305 | { |
d9e2b173 |
1306 | struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp); |
2a014d73 |
1307 | size_t i; |
1308 | |
d9e2b173 |
1309 | for (i = 0; i < ARRAY_SIZE(tramp->f); i++) { |
1310 | if (tramp->f[i] == f || tramp->f[i] == NULL) |
2a014d73 |
1311 | break; |
1312 | } |
d9e2b173 |
1313 | if (i == ARRAY_SIZE(tramp->f)) { |
2a014d73 |
1314 | SysPrintf("trampoline table is full, last func %p\n", f); |
1315 | abort(); |
1316 | } |
d9e2b173 |
1317 | if (tramp->f[i] == NULL) { |
1318 | start_tcache_write(&tramp->f[i], &tramp->f[i + 1]); |
1319 | tramp->f[i] = f; |
1320 | end_tcache_write(&tramp->f[i], &tramp->f[i + 1]); |
1321 | #ifdef HAVE_LIBNX |
1322 | // invalidate the RX mirror (unsure if necessary, but just in case...) |
1323 | armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i])); |
1324 | #endif |
2a014d73 |
1325 | } |
1326 | return &ndrc->tramp.ops[i]; |
1327 | } |
1328 | |
1329 | static void emit_far_jump(const void *f) |
1330 | { |
1331 | if (can_jump_or_call(f)) { |
1332 | emit_jmp(f); |
1333 | return; |
1334 | } |
1335 | |
1336 | f = get_trampoline(f); |
1337 | emit_jmp(f); |
1338 | } |
1339 | |
1340 | static void emit_far_call(const void *f) |
1341 | { |
1342 | if (can_jump_or_call(f)) { |
1343 | emit_call(f); |
1344 | return; |
1345 | } |
1346 | |
1347 | f = get_trampoline(f); |
1348 | emit_call(f); |
1349 | } |
1350 | |
57871462 |
1351 | // Check if an address is already compiled |
1352 | // but don't return addresses which are about to expire from the cache |
4149788d |
1353 | static void *check_addr(u_int vaddr) |
57871462 |
1354 | { |
df4dc2b1 |
1355 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
1356 | size_t i; |
b14b6a8f |
1357 | for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { |
df4dc2b1 |
1358 | if (ht_bin->vaddr[i] == vaddr) |
93c0345b |
1359 | if (doesnt_expire_soon(ht_bin->tcaddr[i])) |
104df9d3 |
1360 | return ht_bin->tcaddr[i]; |
57871462 |
1361 | } |
104df9d3 |
1362 | |
1363 | // refactor to get_addr_nocompile? |
1364 | u_int start_page = get_page_prev(vaddr); |
1365 | u_int page, end_page = get_page(vaddr); |
1366 | |
1367 | stat_inc(stat_jump_in_lookups); |
1368 | for (page = start_page; page <= end_page; page++) { |
1369 | const struct block_info *block; |
1370 | for (block = blocks[page]; block != NULL; block = block->next) { |
1371 | if (vaddr < block->start) |
1372 | break; |
1373 | if (block->is_dirty || vaddr >= block->start + block->len) |
1374 | continue; |
1375 | if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs)) |
1376 | continue; |
1377 | for (i = 0; i < block->jump_in_cnt; i++) |
1378 | if (block->jump_in[i].vaddr == vaddr) |
1379 | break; |
1380 | if (i == block->jump_in_cnt) |
1381 | continue; |
1382 | |
1383 | // Update existing entry with current address |
1384 | void *addr = block->jump_in[i].addr; |
1385 | if (ht_bin->vaddr[0] == vaddr) { |
1386 | ht_bin->tcaddr[0] = addr; |
1387 | return addr; |
1388 | } |
1389 | if (ht_bin->vaddr[1] == vaddr) { |
1390 | ht_bin->tcaddr[1] = addr; |
1391 | return addr; |
1392 | } |
1393 | // Insert into hash table with low priority. |
1394 | // Don't evict existing entries, as they are probably |
1395 | // addresses that are being accessed frequently. |
1396 | if (ht_bin->vaddr[0] == -1) { |
1397 | ht_bin->vaddr[0] = vaddr; |
1398 | ht_bin->tcaddr[0] = addr; |
57871462 |
1399 | } |
104df9d3 |
1400 | else if (ht_bin->vaddr[1] == -1) { |
1401 | ht_bin->vaddr[1] = vaddr; |
1402 | ht_bin->tcaddr[1] = addr; |
1403 | } |
1404 | return addr; |
57871462 |
1405 | } |
57871462 |
1406 | } |
104df9d3 |
1407 | return NULL; |
57871462 |
1408 | } |
1409 | |
104df9d3 |
1410 | static void blocks_clear(struct block_info **head) |
1411 | { |
1412 | struct block_info *cur, *next; |
1413 | |
1414 | if ((cur = *head)) { |
1415 | *head = NULL; |
1416 | while (cur) { |
1417 | next = cur->next; |
1418 | free(cur); |
1419 | cur = next; |
1420 | } |
1421 | } |
1422 | } |
1423 | |
93c0345b |
1424 | static int blocks_remove_matching_addrs(struct block_info **head, |
1425 | u_int base_offs, int shift) |
104df9d3 |
1426 | { |
1427 | struct block_info *next; |
93c0345b |
1428 | int hit = 0; |
104df9d3 |
1429 | while (*head) { |
93c0345b |
1430 | if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) { |
9b495f6e |
1431 | inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs); |
104df9d3 |
1432 | invalidate_block(*head); |
1433 | next = (*head)->next; |
1434 | free(*head); |
1435 | *head = next; |
1436 | stat_dec(stat_blocks); |
93c0345b |
1437 | hit = 1; |
104df9d3 |
1438 | } |
1439 | else |
1440 | { |
1441 | head = &((*head)->next); |
1442 | } |
1443 | } |
93c0345b |
1444 | return hit; |
104df9d3 |
1445 | } |
57871462 |
1446 | |
1447 | // This is called when we write to a compiled block (see do_invstub) |
b7ad2f2c |
1448 | static void unlink_jumps_vaddr_range(u_int start, u_int end) |
57871462 |
1449 | { |
104df9d3 |
1450 | u_int page, start_page = get_page(start), end_page = get_page(end - 1); |
b7ad2f2c |
1451 | int i; |
104df9d3 |
1452 | |
1453 | for (page = start_page; page <= end_page; page++) { |
b7ad2f2c |
1454 | struct jump_info *ji = jumps[page]; |
1455 | if (ji == NULL) |
1456 | continue; |
1457 | for (i = 0; i < ji->count; ) { |
1458 | if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) { |
1459 | i++; |
104df9d3 |
1460 | continue; |
1461 | } |
b7ad2f2c |
1462 | |
1463 | inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, |
1464 | (u_char *)ji->e[i].stub - ndrc->translation_cache); |
1465 | void *host_addr = find_extjump_insn(ji->e[i].stub); |
104df9d3 |
1466 | mark_clear_cache(host_addr); |
b7ad2f2c |
1467 | set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub |
104df9d3 |
1468 | |
104df9d3 |
1469 | stat_dec(stat_links); |
b7ad2f2c |
1470 | ji->count--; |
1471 | if (i < ji->count) { |
1472 | ji->e[i] = ji->e[ji->count]; |
1473 | continue; |
1474 | } |
1475 | i++; |
1476 | } |
1477 | } |
1478 | } |
1479 | |
1480 | static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift) |
1481 | { |
1482 | int i; |
1483 | if (ji == NULL) |
1484 | return; |
1485 | for (i = 0; i < ji->count; ) { |
1486 | u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache; |
1487 | if (((tc_offs ^ base_offs) >> shift) != 0) { |
1488 | i++; |
1489 | continue; |
1490 | } |
1491 | |
9b495f6e |
1492 | inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs); |
b7ad2f2c |
1493 | stat_dec(stat_links); |
1494 | ji->count--; |
1495 | if (i < ji->count) { |
1496 | ji->e[i] = ji->e[ji->count]; |
1497 | continue; |
104df9d3 |
1498 | } |
b7ad2f2c |
1499 | i++; |
57871462 |
1500 | } |
104df9d3 |
1501 | } |
9f51b4b9 |
1502 | |
104df9d3 |
1503 | static void invalidate_block(struct block_info *block) |
1504 | { |
1505 | u_int i; |
f76eeef9 |
1506 | |
104df9d3 |
1507 | block->is_dirty = 1; |
b7ad2f2c |
1508 | unlink_jumps_vaddr_range(block->start, block->start + block->len); |
104df9d3 |
1509 | for (i = 0; i < block->jump_in_cnt; i++) |
1510 | hash_table_remove(block->jump_in[i].vaddr); |
57871462 |
1511 | } |
9be4ba64 |
1512 | |
104df9d3 |
1513 | static int invalidate_range(u_int start, u_int end, |
1514 | u32 *inv_start_ret, u32 *inv_end_ret) |
9be4ba64 |
1515 | { |
3280e616 |
1516 | struct block_info *last_block = NULL; |
104df9d3 |
1517 | u_int start_page = get_page_prev(start); |
1518 | u_int end_page = get_page(end - 1); |
1519 | u_int start_m = pmmask(start); |
ab4377be |
1520 | u_int end_m = pmmask(end - 1); |
104df9d3 |
1521 | u_int inv_start, inv_end; |
1522 | u_int blk_start_m, blk_end_m; |
1523 | u_int page; |
1524 | int hit = 0; |
1525 | |
1526 | // additional area without code (to supplement invalid_code[]), [start, end) |
9b495f6e |
1527 | // avoids excessive ndrc_write_invalidate*() calls |
104df9d3 |
1528 | inv_start = start_m & ~0xfff; |
1529 | inv_end = end_m | 0xfff; |
1530 | |
1531 | for (page = start_page; page <= end_page; page++) { |
1532 | struct block_info *block; |
1533 | for (block = blocks[page]; block != NULL; block = block->next) { |
1534 | if (block->is_dirty) |
1535 | continue; |
3280e616 |
1536 | last_block = block; |
104df9d3 |
1537 | blk_end_m = pmmask(block->start + block->len); |
1538 | if (blk_end_m <= start_m) { |
1539 | inv_start = max(inv_start, blk_end_m); |
1540 | continue; |
1541 | } |
1542 | blk_start_m = pmmask(block->start); |
1543 | if (end_m <= blk_start_m) { |
1544 | inv_end = min(inv_end, blk_start_m - 1); |
1545 | continue; |
9be4ba64 |
1546 | } |
104df9d3 |
1547 | if (!block->source) // "hack" block - leave it alone |
1548 | continue; |
1549 | |
1550 | hit++; |
1551 | invalidate_block(block); |
1552 | stat_inc(stat_inv_hits); |
9be4ba64 |
1553 | } |
9be4ba64 |
1554 | } |
104df9d3 |
1555 | |
3280e616 |
1556 | if (!hit && last_block && last_block->source) { |
1557 | // could be some leftover unused block, uselessly trapping writes |
1558 | last_block->inv_near_misses++; |
1559 | if (last_block->inv_near_misses > 128) { |
1560 | invalidate_block(last_block); |
1561 | stat_inc(stat_inv_hits); |
1562 | hit++; |
1563 | } |
1564 | } |
104df9d3 |
1565 | if (hit) { |
1566 | do_clear_cache(); |
1567 | #ifdef USE_MINI_HT |
1568 | memset(mini_ht, -1, sizeof(mini_ht)); |
1569 | #endif |
1570 | } |
3280e616 |
1571 | |
104df9d3 |
1572 | if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff)) |
1573 | // the whole page is empty now |
1574 | mark_invalid_code(start, 1, 1); |
1575 | |
1576 | if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000); |
1577 | if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000); |
1578 | return hit; |
9be4ba64 |
1579 | } |
1580 | |
104df9d3 |
1581 | void new_dynarec_invalidate_range(unsigned int start, unsigned int end) |
1582 | { |
1583 | invalidate_range(start, end, NULL, NULL); |
1584 | } |
1585 | |
9b495f6e |
1586 | static void ndrc_write_invalidate_many(u_int start, u_int end) |
57871462 |
1587 | { |
9be4ba64 |
1588 | // this check is done by the caller |
1589 | //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } |
9b495f6e |
1590 | int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end); |
1591 | #ifdef INV_DEBUG_W |
1592 | int invc = invalid_code[start >> 12]; |
1593 | u_int len = end - start; |
104df9d3 |
1594 | if (ret) |
9b495f6e |
1595 | printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret); |
104df9d3 |
1596 | else |
9b495f6e |
1597 | printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len, |
1598 | inv_code_start, inv_code_end, invc, invalid_code[start >> 12]); |
1599 | check_for_block_changes(start, end); |
1600 | #endif |
ece032e6 |
1601 | stat_inc(stat_inv_addr_calls); |
9b495f6e |
1602 | (void)ret; |
1603 | } |
1604 | |
1605 | void ndrc_write_invalidate_one(u_int addr) |
1606 | { |
1607 | ndrc_write_invalidate_many(addr, addr + 4); |
57871462 |
1608 | } |
9be4ba64 |
1609 | |
dd3a91a1 |
1610 | // This is called when loading a save state. |
1611 | // Anything could have changed, so invalidate everything. |
104df9d3 |
1612 | void new_dynarec_invalidate_all_pages(void) |
57871462 |
1613 | { |
104df9d3 |
1614 | struct block_info *block; |
581335b0 |
1615 | u_int page; |
104df9d3 |
1616 | for (page = 0; page < ARRAY_SIZE(blocks); page++) { |
1617 | for (block = blocks[page]; block != NULL; block = block->next) { |
1618 | if (block->is_dirty) |
1619 | continue; |
1620 | if (!block->source) // hack block? |
1621 | continue; |
1622 | invalidate_block(block); |
1623 | } |
1624 | } |
1625 | |
57871462 |
1626 | #ifdef USE_MINI_HT |
93c0345b |
1627 | memset(mini_ht, -1, sizeof(mini_ht)); |
57871462 |
1628 | #endif |
919981d0 |
1629 | do_clear_cache(); |
57871462 |
1630 | } |
1631 | |
1632 | // Add an entry to jump_out after making a link |
104df9d3 |
1633 | // src should point to code by emit_extjump() |
b7ad2f2c |
1634 | void ndrc_add_jump_out(u_int vaddr, void *src) |
57871462 |
1635 | { |
b7ad2f2c |
1636 | inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr); |
1637 | u_int page = get_page(vaddr); |
1638 | struct jump_info *ji; |
1639 | |
104df9d3 |
1640 | stat_inc(stat_links); |
b7ad2f2c |
1641 | check_extjump2(src); |
1642 | ji = jumps[page]; |
1643 | if (ji == NULL) { |
1644 | ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16); |
1645 | ji->alloc = 16; |
1646 | ji->count = 0; |
1647 | } |
1648 | else if (ji->count >= ji->alloc) { |
1649 | ji->alloc += 16; |
1650 | ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc); |
1651 | } |
1652 | jumps[page] = ji; |
1653 | ji->e[ji->count].target_vaddr = vaddr; |
1654 | ji->e[ji->count].stub = src; |
1655 | ji->count++; |
57871462 |
1656 | } |
1657 | |
8062d65a |
1658 | /* Register allocation */ |
1659 | |
90f98e7c |
1660 | static void alloc_set(struct regstat *cur, int reg, int hr) |
1661 | { |
1662 | cur->regmap[hr] = reg; |
1663 | cur->dirty &= ~(1u << hr); |
1664 | cur->isconst &= ~(1u << hr); |
1665 | cur->noevict |= 1u << hr; |
1666 | } |
1667 | |
1668 | static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr) |
1669 | { |
1670 | u_char hsn[MAXREG+1]; |
1671 | int j, r, hr; |
1672 | memset(hsn, 10, sizeof(hsn)); |
1673 | lsn(hsn, i); |
1674 | //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); |
1675 | if(i>0) { |
1676 | // Don't evict the cycle count at entry points, otherwise the entry |
1677 | // stub will have to write it. |
1678 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; |
1679 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; |
1680 | for(j=10;j>=3;j--) |
1681 | { |
1682 | // Alloc preferred register if available |
1683 | if (!((cur->noevict >> preferred_hr) & 1) |
1684 | && hsn[cur->regmap[preferred_hr]] == j) |
1685 | { |
1686 | alloc_set(cur, reg, preferred_hr); |
1687 | return; |
1688 | } |
1689 | for(r=1;r<=MAXREG;r++) |
1690 | { |
1691 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { |
1692 | for(hr=0;hr<HOST_REGS;hr++) { |
1693 | if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1)) |
1694 | continue; |
1695 | if(hr!=HOST_CCREG||j<hsn[CCREG]) { |
1696 | if(cur->regmap[hr]==r) { |
1697 | alloc_set(cur, reg, hr); |
1698 | return; |
1699 | } |
1700 | } |
1701 | } |
1702 | } |
1703 | } |
1704 | } |
1705 | } |
1706 | for(j=10;j>=0;j--) |
1707 | { |
1708 | for(r=1;r<=MAXREG;r++) |
1709 | { |
1710 | if(hsn[r]==j) { |
1711 | for(hr=0;hr<HOST_REGS;hr++) { |
1712 | if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1)) |
1713 | continue; |
1714 | if(cur->regmap[hr]==r) { |
1715 | alloc_set(cur, reg, hr); |
1716 | return; |
1717 | } |
1718 | } |
1719 | } |
1720 | } |
1721 | } |
1722 | SysPrintf("This shouldn't happen (evict_alloc_reg)\n"); |
1723 | abort(); |
1724 | } |
1725 | |
8062d65a |
1726 | // Note: registers are allocated clean (unmodified state) |
1727 | // if you intend to modify the register, you must call dirty_reg(). |
1728 | static void alloc_reg(struct regstat *cur,int i,signed char reg) |
1729 | { |
1730 | int r,hr; |
b7ec323c |
1731 | int preferred_reg = PREFERRED_REG_FIRST |
1732 | + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); |
1733 | if (reg == CCREG) preferred_reg = HOST_CCREG; |
1734 | if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; |
1735 | assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); |
53358c1d |
1736 | assert(reg >= 0); |
8062d65a |
1737 | |
1738 | // Don't allocate unused registers |
1739 | if((cur->u>>reg)&1) return; |
1740 | |
1741 | // see if it's already allocated |
90f98e7c |
1742 | if ((hr = get_reg(cur->regmap, reg)) >= 0) { |
1743 | cur->noevict |= 1u << hr; |
53358c1d |
1744 | return; |
90f98e7c |
1745 | } |
8062d65a |
1746 | |
1747 | // Keep the same mapping if the register was already allocated in a loop |
1748 | preferred_reg = loop_reg(i,reg,preferred_reg); |
1749 | |
1750 | // Try to allocate the preferred register |
90f98e7c |
1751 | if (cur->regmap[preferred_reg] == -1) { |
1752 | alloc_set(cur, reg, preferred_reg); |
8062d65a |
1753 | return; |
1754 | } |
1755 | r=cur->regmap[preferred_reg]; |
1756 | assert(r < 64); |
1757 | if((cur->u>>r)&1) { |
90f98e7c |
1758 | alloc_set(cur, reg, preferred_reg); |
8062d65a |
1759 | return; |
1760 | } |
1761 | |
1762 | // Clear any unneeded registers |
1763 | // We try to keep the mapping consistent, if possible, because it |
1764 | // makes branches easier (especially loops). So we try to allocate |
1765 | // first (see above) before removing old mappings. If this is not |
1766 | // possible then go ahead and clear out the registers that are no |
1767 | // longer needed. |
1768 | for(hr=0;hr<HOST_REGS;hr++) |
1769 | { |
1770 | r=cur->regmap[hr]; |
1771 | if(r>=0) { |
1772 | assert(r < 64); |
1773 | if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} |
1774 | } |
1775 | } |
b7ec323c |
1776 | |
8062d65a |
1777 | // Try to allocate any available register, but prefer |
1778 | // registers that have not been used recently. |
b7ec323c |
1779 | if (i > 0) { |
1780 | for (hr = PREFERRED_REG_FIRST; ; ) { |
1781 | if (cur->regmap[hr] < 0) { |
1782 | int oldreg = regs[i-1].regmap[hr]; |
1783 | if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 |
1784 | && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) |
1785 | { |
90f98e7c |
1786 | alloc_set(cur, reg, hr); |
8062d65a |
1787 | return; |
1788 | } |
1789 | } |
b7ec323c |
1790 | hr++; |
1791 | if (hr == EXCLUDE_REG) |
1792 | hr++; |
1793 | if (hr == HOST_REGS) |
1794 | hr = 0; |
1795 | if (hr == PREFERRED_REG_FIRST) |
1796 | break; |
8062d65a |
1797 | } |
1798 | } |
b7ec323c |
1799 | |
8062d65a |
1800 | // Try to allocate any available register |
b7ec323c |
1801 | for (hr = PREFERRED_REG_FIRST; ; ) { |
1802 | if (cur->regmap[hr] < 0) { |
90f98e7c |
1803 | alloc_set(cur, reg, hr); |
8062d65a |
1804 | return; |
1805 | } |
b7ec323c |
1806 | hr++; |
1807 | if (hr == EXCLUDE_REG) |
1808 | hr++; |
1809 | if (hr == HOST_REGS) |
1810 | hr = 0; |
1811 | if (hr == PREFERRED_REG_FIRST) |
1812 | break; |
8062d65a |
1813 | } |
1814 | |
1815 | // Ok, now we have to evict someone |
1816 | // Pick a register we hopefully won't need soon |
90f98e7c |
1817 | evict_alloc_reg(cur, i, reg, preferred_reg); |
8062d65a |
1818 | } |
1819 | |
1820 | // Allocate a temporary register. This is done without regard to |
1821 | // dirty status or whether the register we request is on the unneeded list |
1822 | // Note: This will only allocate one register, even if called multiple times |
1823 | static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) |
1824 | { |
1825 | int r,hr; |
8062d65a |
1826 | |
1827 | // see if it's already allocated |
90f98e7c |
1828 | for (hr = 0; hr < HOST_REGS; hr++) |
8062d65a |
1829 | { |
90f98e7c |
1830 | if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) { |
1831 | cur->noevict |= 1u << hr; |
1832 | return; |
1833 | } |
8062d65a |
1834 | } |
1835 | |
1836 | // Try to allocate any available register |
1837 | for(hr=HOST_REGS-1;hr>=0;hr--) { |
1838 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) { |
90f98e7c |
1839 | alloc_set(cur, reg, hr); |
8062d65a |
1840 | return; |
1841 | } |
1842 | } |
1843 | |
1844 | // Find an unneeded register |
1845 | for(hr=HOST_REGS-1;hr>=0;hr--) |
1846 | { |
1847 | r=cur->regmap[hr]; |
1848 | if(r>=0) { |
1849 | assert(r < 64); |
1850 | if((cur->u>>r)&1) { |
1851 | if(i==0||((unneeded_reg[i-1]>>r)&1)) { |
90f98e7c |
1852 | alloc_set(cur, reg, hr); |
8062d65a |
1853 | return; |
1854 | } |
1855 | } |
1856 | } |
1857 | } |
1858 | |
1859 | // Ok, now we have to evict someone |
1860 | // Pick a register we hopefully won't need soon |
90f98e7c |
1861 | evict_alloc_reg(cur, i, reg, 0); |
8062d65a |
1862 | } |
1863 | |
ad49de89 |
1864 | static void mov_alloc(struct regstat *current,int i) |
57871462 |
1865 | { |
cf95b4f0 |
1866 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { |
9a3ccfeb |
1867 | alloc_cc(current,i); // for stalls |
1868 | dirty_reg(current,CCREG); |
32631e6a |
1869 | } |
1870 | |
57871462 |
1871 | // Note: Don't need to actually alloc the source registers |
cf95b4f0 |
1872 | //alloc_reg(current,i,dops[i].rs1); |
1873 | alloc_reg(current,i,dops[i].rt1); |
ad49de89 |
1874 | |
cf95b4f0 |
1875 | clear_const(current,dops[i].rs1); |
1876 | clear_const(current,dops[i].rt1); |
1877 | dirty_reg(current,dops[i].rt1); |
57871462 |
1878 | } |
1879 | |
ad49de89 |
1880 | static void shiftimm_alloc(struct regstat *current,int i) |
57871462 |
1881 | { |
cf95b4f0 |
1882 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA |
57871462 |
1883 | { |
cf95b4f0 |
1884 | if(dops[i].rt1) { |
1885 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
53dc27f6 |
1886 | else dops[i].use_lt1=!!dops[i].rs1; |
cf95b4f0 |
1887 | alloc_reg(current,i,dops[i].rt1); |
1888 | dirty_reg(current,dops[i].rt1); |
1889 | if(is_const(current,dops[i].rs1)) { |
1890 | int v=get_const(current,dops[i].rs1); |
277718fa |
1891 | if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm); |
1892 | if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm); |
1893 | if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm); |
dc49e339 |
1894 | } |
cf95b4f0 |
1895 | else clear_const(current,dops[i].rt1); |
57871462 |
1896 | } |
1897 | } |
dc49e339 |
1898 | else |
1899 | { |
cf95b4f0 |
1900 | clear_const(current,dops[i].rs1); |
1901 | clear_const(current,dops[i].rt1); |
dc49e339 |
1902 | } |
1903 | |
cf95b4f0 |
1904 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA |
57871462 |
1905 | { |
9c45ca93 |
1906 | assert(0); |
57871462 |
1907 | } |
cf95b4f0 |
1908 | if(dops[i].opcode2==0x3c) // DSLL32 |
57871462 |
1909 | { |
9c45ca93 |
1910 | assert(0); |
57871462 |
1911 | } |
cf95b4f0 |
1912 | if(dops[i].opcode2==0x3e) // DSRL32 |
57871462 |
1913 | { |
9c45ca93 |
1914 | assert(0); |
57871462 |
1915 | } |
cf95b4f0 |
1916 | if(dops[i].opcode2==0x3f) // DSRA32 |
57871462 |
1917 | { |
9c45ca93 |
1918 | assert(0); |
57871462 |
1919 | } |
1920 | } |
1921 | |
ad49de89 |
1922 | static void shift_alloc(struct regstat *current,int i) |
57871462 |
1923 | { |
cf95b4f0 |
1924 | if(dops[i].rt1) { |
cf95b4f0 |
1925 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
1926 | if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); |
1927 | alloc_reg(current,i,dops[i].rt1); |
1928 | if(dops[i].rt1==dops[i].rs2) { |
e1190b87 |
1929 | alloc_reg_temp(current,i,-1); |
277718fa |
1930 | cinfo[i].min_free_regs=1; |
e1190b87 |
1931 | } |
cf95b4f0 |
1932 | clear_const(current,dops[i].rs1); |
1933 | clear_const(current,dops[i].rs2); |
1934 | clear_const(current,dops[i].rt1); |
1935 | dirty_reg(current,dops[i].rt1); |
57871462 |
1936 | } |
1937 | } |
1938 | |
ad49de89 |
1939 | static void alu_alloc(struct regstat *current,int i) |
57871462 |
1940 | { |
cf95b4f0 |
1941 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
1942 | if(dops[i].rt1) { |
1943 | if(dops[i].rs1&&dops[i].rs2) { |
1944 | alloc_reg(current,i,dops[i].rs1); |
1945 | alloc_reg(current,i,dops[i].rs2); |
57871462 |
1946 | } |
1947 | else { |
cf95b4f0 |
1948 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1949 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); |
57871462 |
1950 | } |
cf95b4f0 |
1951 | alloc_reg(current,i,dops[i].rt1); |
57871462 |
1952 | } |
277718fa |
1953 | if (dops[i].may_except) { |
90f98e7c |
1954 | alloc_cc_optional(current, i); // for exceptions |
277718fa |
1955 | alloc_reg_temp(current, i, -1); |
1956 | cinfo[i].min_free_regs = 1; |
a5cd72d0 |
1957 | } |
57871462 |
1958 | } |
277718fa |
1959 | else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
cf95b4f0 |
1960 | if(dops[i].rt1) { |
1961 | alloc_reg(current,i,dops[i].rs1); |
1962 | alloc_reg(current,i,dops[i].rs2); |
1963 | alloc_reg(current,i,dops[i].rt1); |
57871462 |
1964 | } |
57871462 |
1965 | } |
277718fa |
1966 | else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
cf95b4f0 |
1967 | if(dops[i].rt1) { |
1968 | if(dops[i].rs1&&dops[i].rs2) { |
1969 | alloc_reg(current,i,dops[i].rs1); |
1970 | alloc_reg(current,i,dops[i].rs2); |
57871462 |
1971 | } |
1972 | else |
1973 | { |
cf95b4f0 |
1974 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1975 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); |
57871462 |
1976 | } |
cf95b4f0 |
1977 | alloc_reg(current,i,dops[i].rt1); |
57871462 |
1978 | } |
1979 | } |
cf95b4f0 |
1980 | clear_const(current,dops[i].rs1); |
1981 | clear_const(current,dops[i].rs2); |
1982 | clear_const(current,dops[i].rt1); |
1983 | dirty_reg(current,dops[i].rt1); |
57871462 |
1984 | } |
1985 | |
ad49de89 |
1986 | static void imm16_alloc(struct regstat *current,int i) |
57871462 |
1987 | { |
cf95b4f0 |
1988 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
53dc27f6 |
1989 | else dops[i].use_lt1=!!dops[i].rs1; |
cf95b4f0 |
1990 | if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); |
a5cd72d0 |
1991 | if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
cf95b4f0 |
1992 | clear_const(current,dops[i].rs1); |
1993 | clear_const(current,dops[i].rt1); |
57871462 |
1994 | } |
cf95b4f0 |
1995 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
1996 | if(is_const(current,dops[i].rs1)) { |
1997 | int v=get_const(current,dops[i].rs1); |
277718fa |
1998 | if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm); |
1999 | if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm); |
2000 | if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm); |
57871462 |
2001 | } |
cf95b4f0 |
2002 | else clear_const(current,dops[i].rt1); |
57871462 |
2003 | } |
cf95b4f0 |
2004 | else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
2005 | if(is_const(current,dops[i].rs1)) { |
2006 | int v=get_const(current,dops[i].rs1); |
277718fa |
2007 | set_const(current,dops[i].rt1,v+cinfo[i].imm); |
57871462 |
2008 | } |
cf95b4f0 |
2009 | else clear_const(current,dops[i].rt1); |
277718fa |
2010 | if (dops[i].may_except) { |
90f98e7c |
2011 | alloc_cc_optional(current, i); // for exceptions |
277718fa |
2012 | alloc_reg_temp(current, i, -1); |
2013 | cinfo[i].min_free_regs = 1; |
a5cd72d0 |
2014 | } |
57871462 |
2015 | } |
2016 | else { |
277718fa |
2017 | set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI |
57871462 |
2018 | } |
cf95b4f0 |
2019 | dirty_reg(current,dops[i].rt1); |
57871462 |
2020 | } |
2021 | |
ad49de89 |
2022 | static void load_alloc(struct regstat *current,int i) |
57871462 |
2023 | { |
277718fa |
2024 | int need_temp = 0; |
cf95b4f0 |
2025 | clear_const(current,dops[i].rt1); |
2026 | //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? |
2027 | if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register |
37387d8b |
2028 | if (needed_again(dops[i].rs1, i)) |
2029 | alloc_reg(current, i, dops[i].rs1); |
2030 | if (ram_offset) |
2031 | alloc_reg(current, i, ROREG); |
277718fa |
2032 | if (dops[i].may_except) { |
90f98e7c |
2033 | alloc_cc_optional(current, i); // for exceptions |
277718fa |
2034 | need_temp = 1; |
2035 | } |
cf95b4f0 |
2036 | if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { |
2037 | alloc_reg(current,i,dops[i].rt1); |
a5cd72d0 |
2038 | assert(get_reg_w(current->regmap, dops[i].rt1)>=0); |
cf95b4f0 |
2039 | dirty_reg(current,dops[i].rt1); |
57871462 |
2040 | // LWL/LWR need a temporary register for the old value |
cf95b4f0 |
2041 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
57871462 |
2042 | { |
2043 | alloc_reg(current,i,FTEMP); |
277718fa |
2044 | need_temp = 1; |
57871462 |
2045 | } |
2046 | } |
2047 | else |
2048 | { |
373d1d07 |
2049 | // Load to r0 or unneeded register (dummy load) |
57871462 |
2050 | // but we still need a register to calculate the address |
cf95b4f0 |
2051 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
535d208a |
2052 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary |
277718fa |
2053 | need_temp = 1; |
2054 | } |
2055 | if (need_temp) { |
2056 | alloc_reg_temp(current, i, -1); |
2057 | cinfo[i].min_free_regs = 1; |
57871462 |
2058 | } |
2059 | } |
2060 | |
90f98e7c |
2061 | // this may eat up to 7 registers |
2062 | static void store_alloc(struct regstat *current, int i) |
57871462 |
2063 | { |
cf95b4f0 |
2064 | clear_const(current,dops[i].rs2); |
2065 | if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary |
2066 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
2067 | alloc_reg(current,i,dops[i].rs2); |
37387d8b |
2068 | if (ram_offset) |
2069 | alloc_reg(current, i, ROREG); |
57871462 |
2070 | #if defined(HOST_IMM8) |
2071 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
37387d8b |
2072 | alloc_reg(current, i, INVCP); |
57871462 |
2073 | #endif |
277718fa |
2074 | if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL |
57871462 |
2075 | alloc_reg(current,i,FTEMP); |
2076 | } |
90f98e7c |
2077 | if (dops[i].may_except) |
2078 | alloc_cc_optional(current, i); // for exceptions |
57871462 |
2079 | // We need a temporary register for address generation |
2080 | alloc_reg_temp(current,i,-1); |
277718fa |
2081 | cinfo[i].min_free_regs=1; |
57871462 |
2082 | } |
2083 | |
90f98e7c |
2084 | static void c2ls_alloc(struct regstat *current, int i) |
b9b61529 |
2085 | { |
cf95b4f0 |
2086 | clear_const(current,dops[i].rt1); |
2087 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
b9b61529 |
2088 | alloc_reg(current,i,FTEMP); |
37387d8b |
2089 | if (ram_offset) |
2090 | alloc_reg(current, i, ROREG); |
b9b61529 |
2091 | #if defined(HOST_IMM8) |
2092 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
37387d8b |
2093 | if (dops[i].opcode == 0x3a) // SWC2 |
b9b61529 |
2094 | alloc_reg(current,i,INVCP); |
2095 | #endif |
90f98e7c |
2096 | if (dops[i].may_except) |
2097 | alloc_cc_optional(current, i); // for exceptions |
b9b61529 |
2098 | // We need a temporary register for address generation |
2099 | alloc_reg_temp(current,i,-1); |
277718fa |
2100 | cinfo[i].min_free_regs=1; |
b9b61529 |
2101 | } |
2102 | |
57871462 |
2103 | #ifndef multdiv_alloc |
4149788d |
2104 | static void multdiv_alloc(struct regstat *current,int i) |
57871462 |
2105 | { |
2106 | // case 0x18: MULT |
2107 | // case 0x19: MULTU |
2108 | // case 0x1A: DIV |
2109 | // case 0x1B: DIVU |
cf95b4f0 |
2110 | clear_const(current,dops[i].rs1); |
2111 | clear_const(current,dops[i].rs2); |
32631e6a |
2112 | alloc_cc(current,i); // for stalls |
90f98e7c |
2113 | dirty_reg(current,CCREG); |
cf95b4f0 |
2114 | if(dops[i].rs1&&dops[i].rs2) |
57871462 |
2115 | { |
57871462 |
2116 | current->u&=~(1LL<<HIREG); |
2117 | current->u&=~(1LL<<LOREG); |
2118 | alloc_reg(current,i,HIREG); |
2119 | alloc_reg(current,i,LOREG); |
cf95b4f0 |
2120 | alloc_reg(current,i,dops[i].rs1); |
2121 | alloc_reg(current,i,dops[i].rs2); |
57871462 |
2122 | dirty_reg(current,HIREG); |
2123 | dirty_reg(current,LOREG); |
57871462 |
2124 | } |
2125 | else |
2126 | { |
2127 | // Multiply by zero is zero. |
2128 | // MIPS does not have a divide by zero exception. |
57871462 |
2129 | alloc_reg(current,i,HIREG); |
2130 | alloc_reg(current,i,LOREG); |
57871462 |
2131 | dirty_reg(current,HIREG); |
2132 | dirty_reg(current,LOREG); |
de6dbc52 |
2133 | if (dops[i].rs1 && ((dops[i].opcode2 & 0x3e) == 0x1a)) // div(u) 0 |
2134 | alloc_reg(current, i, dops[i].rs1); |
57871462 |
2135 | } |
2136 | } |
2137 | #endif |
2138 | |
4149788d |
2139 | static void cop0_alloc(struct regstat *current,int i) |
57871462 |
2140 | { |
cf95b4f0 |
2141 | if(dops[i].opcode2==0) // MFC0 |
57871462 |
2142 | { |
cf95b4f0 |
2143 | if(dops[i].rt1) { |
2144 | clear_const(current,dops[i].rt1); |
cf95b4f0 |
2145 | alloc_reg(current,i,dops[i].rt1); |
2146 | dirty_reg(current,dops[i].rt1); |
57871462 |
2147 | } |
2148 | } |
cf95b4f0 |
2149 | else if(dops[i].opcode2==4) // MTC0 |
57871462 |
2150 | { |
de6dbc52 |
2151 | if (((source[i]>>11)&0x1e) == 12) { |
2152 | alloc_cc(current, i); |
2153 | dirty_reg(current, CCREG); |
2154 | } |
cf95b4f0 |
2155 | if(dops[i].rs1){ |
2156 | clear_const(current,dops[i].rs1); |
2157 | alloc_reg(current,i,dops[i].rs1); |
57871462 |
2158 | alloc_all(current,i); |
2159 | } |
2160 | else { |
2161 | alloc_all(current,i); // FIXME: Keep r0 |
2162 | current->u&=~1LL; |
2163 | alloc_reg(current,i,0); |
2164 | } |
277718fa |
2165 | cinfo[i].min_free_regs = HOST_REGS; |
57871462 |
2166 | } |
a5cd72d0 |
2167 | } |
2168 | |
2169 | static void rfe_alloc(struct regstat *current, int i) |
2170 | { |
2171 | alloc_all(current, i); |
277718fa |
2172 | cinfo[i].min_free_regs = HOST_REGS; |
57871462 |
2173 | } |
2174 | |
81dbbf4c |
2175 | static void cop2_alloc(struct regstat *current,int i) |
57871462 |
2176 | { |
cf95b4f0 |
2177 | if (dops[i].opcode2 < 3) // MFC2/CFC2 |
57871462 |
2178 | { |
81dbbf4c |
2179 | alloc_cc(current,i); // for stalls |
2180 | dirty_reg(current,CCREG); |
cf95b4f0 |
2181 | if(dops[i].rt1){ |
2182 | clear_const(current,dops[i].rt1); |
2183 | alloc_reg(current,i,dops[i].rt1); |
2184 | dirty_reg(current,dops[i].rt1); |
57871462 |
2185 | } |
57871462 |
2186 | } |
cf95b4f0 |
2187 | else if (dops[i].opcode2 > 3) // MTC2/CTC2 |
57871462 |
2188 | { |
cf95b4f0 |
2189 | if(dops[i].rs1){ |
2190 | clear_const(current,dops[i].rs1); |
2191 | alloc_reg(current,i,dops[i].rs1); |
57871462 |
2192 | } |
2193 | else { |
2194 | current->u&=~1LL; |
2195 | alloc_reg(current,i,0); |
57871462 |
2196 | } |
2197 | } |
81dbbf4c |
2198 | alloc_reg_temp(current,i,-1); |
277718fa |
2199 | cinfo[i].min_free_regs=1; |
57871462 |
2200 | } |
00fa9369 |
2201 | |
4149788d |
2202 | static void c2op_alloc(struct regstat *current,int i) |
b9b61529 |
2203 | { |
81dbbf4c |
2204 | alloc_cc(current,i); // for stalls |
2205 | dirty_reg(current,CCREG); |
b9b61529 |
2206 | alloc_reg_temp(current,i,-1); |
2207 | } |
57871462 |
2208 | |
4149788d |
2209 | static void syscall_alloc(struct regstat *current,int i) |
57871462 |
2210 | { |
2211 | alloc_cc(current,i); |
2212 | dirty_reg(current,CCREG); |
2213 | alloc_all(current,i); |
277718fa |
2214 | cinfo[i].min_free_regs=HOST_REGS; |
57871462 |
2215 | current->isconst=0; |
2216 | } |
2217 | |
4149788d |
2218 | static void delayslot_alloc(struct regstat *current,int i) |
57871462 |
2219 | { |
cf95b4f0 |
2220 | switch(dops[i].itype) { |
57871462 |
2221 | case UJUMP: |
2222 | case CJUMP: |
2223 | case SJUMP: |
2224 | case RJUMP: |
57871462 |
2225 | case SYSCALL: |
7139f3c8 |
2226 | case HLECALL: |
57871462 |
2227 | case IMM16: |
2228 | imm16_alloc(current,i); |
2229 | break; |
2230 | case LOAD: |
2231 | case LOADLR: |
2232 | load_alloc(current,i); |
2233 | break; |
2234 | case STORE: |
2235 | case STORELR: |
2236 | store_alloc(current,i); |
2237 | break; |
2238 | case ALU: |
2239 | alu_alloc(current,i); |
2240 | break; |
2241 | case SHIFT: |
2242 | shift_alloc(current,i); |
2243 | break; |
2244 | case MULTDIV: |
2245 | multdiv_alloc(current,i); |
2246 | break; |
2247 | case SHIFTIMM: |
2248 | shiftimm_alloc(current,i); |
2249 | break; |
2250 | case MOV: |
2251 | mov_alloc(current,i); |
2252 | break; |
2253 | case COP0: |
2254 | cop0_alloc(current,i); |
2255 | break; |
a5cd72d0 |
2256 | case RFE: |
2257 | rfe_alloc(current,i); |
81dbbf4c |
2258 | break; |
b9b61529 |
2259 | case COP2: |
81dbbf4c |
2260 | cop2_alloc(current,i); |
57871462 |
2261 | break; |
b9b61529 |
2262 | case C2LS: |
2263 | c2ls_alloc(current,i); |
2264 | break; |
b9b61529 |
2265 | case C2OP: |
2266 | c2op_alloc(current,i); |
2267 | break; |
57871462 |
2268 | } |
2269 | } |
2270 | |
b14b6a8f |
2271 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
2272 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) |
2273 | { |
d1e4ebd9 |
2274 | assert(stubcount < ARRAY_SIZE(stubs)); |
b14b6a8f |
2275 | stubs[stubcount].type = type; |
2276 | stubs[stubcount].addr = addr; |
2277 | stubs[stubcount].retaddr = retaddr; |
2278 | stubs[stubcount].a = a; |
2279 | stubs[stubcount].b = b; |
2280 | stubs[stubcount].c = c; |
2281 | stubs[stubcount].d = d; |
2282 | stubs[stubcount].e = e; |
57871462 |
2283 | stubcount++; |
2284 | } |
2285 | |
b14b6a8f |
2286 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, |
81dbbf4c |
2287 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist) |
b14b6a8f |
2288 | { |
2289 | add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist); |
2290 | } |
2291 | |
57871462 |
2292 | // Write out a single register |
2330734f |
2293 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) |
57871462 |
2294 | { |
2295 | int hr; |
2296 | for(hr=0;hr<HOST_REGS;hr++) { |
2297 | if(hr!=EXCLUDE_REG) { |
9de8a0c3 |
2298 | if(regmap[hr]==r) { |
57871462 |
2299 | if((dirty>>hr)&1) { |
ad49de89 |
2300 | assert(regmap[hr]<64); |
2301 | emit_storereg(r,hr); |
57871462 |
2302 | } |
2303 | } |
2304 | } |
2305 | } |
2306 | } |
2307 | |
8062d65a |
2308 | static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) |
2309 | { |
2310 | //if(dirty_pre==dirty) return; |
53358c1d |
2311 | int hr, r; |
2312 | for (hr = 0; hr < HOST_REGS; hr++) { |
2313 | r = pre[hr]; |
2314 | if (r < 1 || r > 33 || ((u >> r) & 1)) |
2315 | continue; |
2316 | if (((dirty_pre & ~dirty) >> hr) & 1) |
2317 | emit_storereg(r, hr); |
8062d65a |
2318 | } |
2319 | } |
2320 | |
687b4580 |
2321 | // trashes r2 |
2322 | static void pass_args(int a0, int a1) |
2323 | { |
2324 | if(a0==1&&a1==0) { |
2325 | // must swap |
2326 | emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0); |
2327 | } |
2328 | else if(a0!=0&&a1==0) { |
2329 | emit_mov(a1,1); |
2330 | if (a0>=0) emit_mov(a0,0); |
2331 | } |
2332 | else { |
2333 | if(a0>=0&&a0!=0) emit_mov(a0,0); |
2334 | if(a1>=0&&a1!=1) emit_mov(a1,1); |
2335 | } |
2336 | } |
2337 | |
a5cd72d0 |
2338 | static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
2339 | { |
cf95b4f0 |
2340 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
a5cd72d0 |
2341 | int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled |
2342 | if (dops[i].rt1 || do_oflow) { |
2343 | int do_exception_check = 0; |
2344 | signed char s1, s2, t, tmp; |
2345 | t = get_reg_w(i_regs->regmap, dops[i].rt1); |
2346 | tmp = get_reg_temp(i_regs->regmap); |
277718fa |
2347 | if (do_oflow) |
2348 | assert(tmp >= 0); |
90f98e7c |
2349 | if (t < 0 && do_oflow) |
2350 | t = tmp; |
a5cd72d0 |
2351 | if (t >= 0) { |
2352 | s1 = get_reg(i_regs->regmap, dops[i].rs1); |
2353 | s2 = get_reg(i_regs->regmap, dops[i].rs2); |
2354 | if (dops[i].rs1 && dops[i].rs2) { |
57871462 |
2355 | assert(s1>=0); |
2356 | assert(s2>=0); |
a5cd72d0 |
2357 | if (dops[i].opcode2 & 2) { |
2358 | if (do_oflow) { |
2359 | emit_subs(s1, s2, tmp); |
2360 | do_exception_check = 1; |
2361 | } |
2362 | else |
2363 | emit_sub(s1,s2,t); |
2364 | } |
2365 | else { |
2366 | if (do_oflow) { |
2367 | emit_adds(s1, s2, tmp); |
2368 | do_exception_check = 1; |
2369 | } |
2370 | else |
2371 | emit_add(s1,s2,t); |
2372 | } |
57871462 |
2373 | } |
cf95b4f0 |
2374 | else if(dops[i].rs1) { |
57871462 |
2375 | if(s1>=0) emit_mov(s1,t); |
cf95b4f0 |
2376 | else emit_loadreg(dops[i].rs1,t); |
57871462 |
2377 | } |
cf95b4f0 |
2378 | else if(dops[i].rs2) { |
a5cd72d0 |
2379 | if (s2 < 0) { |
2380 | emit_loadreg(dops[i].rs2, t); |
2381 | s2 = t; |
57871462 |
2382 | } |
a5cd72d0 |
2383 | if (dops[i].opcode2 & 2) { |
2384 | if (do_oflow) { |
2385 | emit_negs(s2, tmp); |
2386 | do_exception_check = 1; |
2387 | } |
2388 | else |
2389 | emit_neg(s2, t); |
57871462 |
2390 | } |
a5cd72d0 |
2391 | else if (s2 != t) |
2392 | emit_mov(s2, t); |
57871462 |
2393 | } |
a5cd72d0 |
2394 | else |
2395 | emit_zeroreg(t); |
2396 | } |
2397 | if (do_exception_check) { |
2398 | void *jaddr = out; |
2399 | emit_jo(0); |
2400 | if (t >= 0 && tmp != t) |
2401 | emit_mov(tmp, t); |
2402 | add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0); |
57871462 |
2403 | } |
2404 | } |
2405 | } |
a5cd72d0 |
2406 | else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
cf95b4f0 |
2407 | if(dops[i].rt1) { |
ad49de89 |
2408 | signed char s1l,s2l,t; |
57871462 |
2409 | { |
a5cd72d0 |
2410 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 |
2411 | //assert(t>=0); |
2412 | if(t>=0) { |
cf95b4f0 |
2413 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2414 | s2l=get_reg(i_regs->regmap,dops[i].rs2); |
2415 | if(dops[i].rs2==0) // rx<r0 |
57871462 |
2416 | { |
cf95b4f0 |
2417 | if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT |
06e425d7 |
2418 | assert(s1l>=0); |
57871462 |
2419 | emit_shrimm(s1l,31,t); |
06e425d7 |
2420 | } |
2421 | else // SLTU (unsigned can not be less than zero, 0<0) |
57871462 |
2422 | emit_zeroreg(t); |
2423 | } |
cf95b4f0 |
2424 | else if(dops[i].rs1==0) // r0<rx |
57871462 |
2425 | { |
2426 | assert(s2l>=0); |
cf95b4f0 |
2427 | if(dops[i].opcode2==0x2a) // SLT |
57871462 |
2428 | emit_set_gz32(s2l,t); |
2429 | else // SLTU (set if not zero) |
2430 | emit_set_nz32(s2l,t); |
2431 | } |
2432 | else{ |
2433 | assert(s1l>=0);assert(s2l>=0); |
cf95b4f0 |
2434 | if(dops[i].opcode2==0x2a) // SLT |
57871462 |
2435 | emit_set_if_less32(s1l,s2l,t); |
2436 | else // SLTU |
2437 | emit_set_if_carry32(s1l,s2l,t); |
2438 | } |
2439 | } |
2440 | } |
2441 | } |
2442 | } |
a5cd72d0 |
2443 | else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
cf95b4f0 |
2444 | if(dops[i].rt1) { |
ad49de89 |
2445 | signed char s1l,s2l,tl; |
a5cd72d0 |
2446 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 |
2447 | { |
57871462 |
2448 | if(tl>=0) { |
cf95b4f0 |
2449 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2450 | s2l=get_reg(i_regs->regmap,dops[i].rs2); |
2451 | if(dops[i].rs1&&dops[i].rs2) { |
57871462 |
2452 | assert(s1l>=0); |
2453 | assert(s2l>=0); |
cf95b4f0 |
2454 | if(dops[i].opcode2==0x24) { // AND |
57871462 |
2455 | emit_and(s1l,s2l,tl); |
2456 | } else |
cf95b4f0 |
2457 | if(dops[i].opcode2==0x25) { // OR |
57871462 |
2458 | emit_or(s1l,s2l,tl); |
2459 | } else |
cf95b4f0 |
2460 | if(dops[i].opcode2==0x26) { // XOR |
57871462 |
2461 | emit_xor(s1l,s2l,tl); |
2462 | } else |
cf95b4f0 |
2463 | if(dops[i].opcode2==0x27) { // NOR |
57871462 |
2464 | emit_or(s1l,s2l,tl); |
2465 | emit_not(tl,tl); |
2466 | } |
2467 | } |
2468 | else |
2469 | { |
cf95b4f0 |
2470 | if(dops[i].opcode2==0x24) { // AND |
57871462 |
2471 | emit_zeroreg(tl); |
2472 | } else |
cf95b4f0 |
2473 | if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR |
2474 | if(dops[i].rs1){ |
57871462 |
2475 | if(s1l>=0) emit_mov(s1l,tl); |
cf95b4f0 |
2476 | else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry? |
57871462 |
2477 | } |
2478 | else |
cf95b4f0 |
2479 | if(dops[i].rs2){ |
57871462 |
2480 | if(s2l>=0) emit_mov(s2l,tl); |
cf95b4f0 |
2481 | else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry? |
57871462 |
2482 | } |
2483 | else emit_zeroreg(tl); |
2484 | } else |
cf95b4f0 |
2485 | if(dops[i].opcode2==0x27) { // NOR |
2486 | if(dops[i].rs1){ |
57871462 |
2487 | if(s1l>=0) emit_not(s1l,tl); |
2488 | else { |
cf95b4f0 |
2489 | emit_loadreg(dops[i].rs1,tl); |
57871462 |
2490 | emit_not(tl,tl); |
2491 | } |
2492 | } |
2493 | else |
cf95b4f0 |
2494 | if(dops[i].rs2){ |
57871462 |
2495 | if(s2l>=0) emit_not(s2l,tl); |
2496 | else { |
cf95b4f0 |
2497 | emit_loadreg(dops[i].rs2,tl); |
57871462 |
2498 | emit_not(tl,tl); |
2499 | } |
2500 | } |
2501 | else emit_movimm(-1,tl); |
2502 | } |
2503 | } |
2504 | } |
2505 | } |
2506 | } |
2507 | } |
2508 | } |
2509 | |
a5cd72d0 |
2510 | static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
2511 | { |
cf95b4f0 |
2512 | if (dops[i].opcode==0x0f) { // LUI |
2513 | if(dops[i].rt1) { |
57871462 |
2514 | signed char t; |
a5cd72d0 |
2515 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 |
2516 | //assert(t>=0); |
2517 | if(t>=0) { |
2518 | if(!((i_regs->isconst>>t)&1)) |
277718fa |
2519 | emit_movimm(cinfo[i].imm<<16,t); |
57871462 |
2520 | } |
2521 | } |
2522 | } |
cf95b4f0 |
2523 | if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
277718fa |
2524 | int is_addi = dops[i].may_except; |
a5cd72d0 |
2525 | if (dops[i].rt1 || is_addi) { |
2526 | signed char s, t, tmp; |
2527 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
2528 | s=get_reg(i_regs->regmap,dops[i].rs1); |
2529 | if(dops[i].rs1) { |
a5cd72d0 |
2530 | tmp = get_reg_temp(i_regs->regmap); |
2531 | if (is_addi) { |
2532 | assert(tmp >= 0); |
2533 | if (t < 0) t = tmp; |
2534 | } |
57871462 |
2535 | if(t>=0) { |
2536 | if(!((i_regs->isconst>>t)&1)) { |
a5cd72d0 |
2537 | int sum, do_exception_check = 0; |
2538 | if (s < 0) { |
cf95b4f0 |
2539 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
a5cd72d0 |
2540 | if (is_addi) { |
277718fa |
2541 | emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp); |
a5cd72d0 |
2542 | do_exception_check = 1; |
2543 | } |
57871462 |
2544 | else |
277718fa |
2545 | emit_addimm(t, cinfo[i].imm, t); |
a5cd72d0 |
2546 | } else { |
2547 | if (!((i_regs->wasconst >> s) & 1)) { |
2548 | if (is_addi) { |
277718fa |
2549 | emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp); |
a5cd72d0 |
2550 | do_exception_check = 1; |
2551 | } |
2552 | else |
277718fa |
2553 | emit_addimm(s, cinfo[i].imm, t); |
a5cd72d0 |
2554 | } |
2555 | else { |
277718fa |
2556 | int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum); |
a5cd72d0 |
2557 | if (is_addi && oflow) |
2558 | do_exception_check = 2; |
2559 | else |
2560 | emit_movimm(sum, t); |
2561 | } |
2562 | } |
2563 | if (do_exception_check) { |
2564 | void *jaddr = out; |
2565 | if (do_exception_check == 2) |
2566 | emit_jmp(0); |
2567 | else { |
2568 | emit_jo(0); |
2569 | if (tmp != t) |
2570 | emit_mov(tmp, t); |
2571 | } |
2572 | add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0); |
57871462 |
2573 | } |
2574 | } |
2575 | } |
2576 | } else { |
2577 | if(t>=0) { |
2578 | if(!((i_regs->isconst>>t)&1)) |
277718fa |
2579 | emit_movimm(cinfo[i].imm,t); |
57871462 |
2580 | } |
2581 | } |
2582 | } |
2583 | } |
cf95b4f0 |
2584 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
2585 | if(dops[i].rt1) { |
2586 | //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug |
ad49de89 |
2587 | signed char sl,t; |
a5cd72d0 |
2588 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
2589 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 |
2590 | //assert(t>=0); |
2591 | if(t>=0) { |
cf95b4f0 |
2592 | if(dops[i].rs1>0) { |
2593 | if(dops[i].opcode==0x0a) { // SLTI |
57871462 |
2594 | if(sl<0) { |
cf95b4f0 |
2595 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
277718fa |
2596 | emit_slti32(t,cinfo[i].imm,t); |
57871462 |
2597 | }else{ |
277718fa |
2598 | emit_slti32(sl,cinfo[i].imm,t); |
57871462 |
2599 | } |
2600 | } |
2601 | else { // SLTIU |
2602 | if(sl<0) { |
cf95b4f0 |
2603 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
277718fa |
2604 | emit_sltiu32(t,cinfo[i].imm,t); |
57871462 |
2605 | }else{ |
277718fa |
2606 | emit_sltiu32(sl,cinfo[i].imm,t); |
57871462 |
2607 | } |
2608 | } |
57871462 |
2609 | }else{ |
2610 | // SLTI(U) with r0 is just stupid, |
2611 | // nonetheless examples can be found |
cf95b4f0 |
2612 | if(dops[i].opcode==0x0a) // SLTI |
277718fa |
2613 | if(0<cinfo[i].imm) emit_movimm(1,t); |
57871462 |
2614 | else emit_zeroreg(t); |
2615 | else // SLTIU |
2616 | { |
277718fa |
2617 | if(cinfo[i].imm) emit_movimm(1,t); |
57871462 |
2618 | else emit_zeroreg(t); |
2619 | } |
2620 | } |
2621 | } |
2622 | } |
2623 | } |
cf95b4f0 |
2624 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
2625 | if(dops[i].rt1) { |
7c3a5182 |
2626 | signed char sl,tl; |
a5cd72d0 |
2627 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
2628 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 |
2629 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
cf95b4f0 |
2630 | if(dops[i].opcode==0x0c) //ANDI |
57871462 |
2631 | { |
cf95b4f0 |
2632 | if(dops[i].rs1) { |
57871462 |
2633 | if(sl<0) { |
cf95b4f0 |
2634 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
277718fa |
2635 | emit_andimm(tl,cinfo[i].imm,tl); |
57871462 |
2636 | }else{ |
2637 | if(!((i_regs->wasconst>>sl)&1)) |
277718fa |
2638 | emit_andimm(sl,cinfo[i].imm,tl); |
57871462 |
2639 | else |
277718fa |
2640 | emit_movimm(constmap[i][sl]&cinfo[i].imm,tl); |
57871462 |
2641 | } |
2642 | } |
2643 | else |
2644 | emit_zeroreg(tl); |
57871462 |
2645 | } |
2646 | else |
2647 | { |
cf95b4f0 |
2648 | if(dops[i].rs1) { |
57871462 |
2649 | if(sl<0) { |
cf95b4f0 |
2650 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 |
2651 | } |
cf95b4f0 |
2652 | if(dops[i].opcode==0x0d) { // ORI |
581335b0 |
2653 | if(sl<0) { |
277718fa |
2654 | emit_orimm(tl,cinfo[i].imm,tl); |
581335b0 |
2655 | }else{ |
2656 | if(!((i_regs->wasconst>>sl)&1)) |
277718fa |
2657 | emit_orimm(sl,cinfo[i].imm,tl); |
581335b0 |
2658 | else |
277718fa |
2659 | emit_movimm(constmap[i][sl]|cinfo[i].imm,tl); |
581335b0 |
2660 | } |
57871462 |
2661 | } |
cf95b4f0 |
2662 | if(dops[i].opcode==0x0e) { // XORI |
581335b0 |
2663 | if(sl<0) { |
277718fa |
2664 | emit_xorimm(tl,cinfo[i].imm,tl); |
581335b0 |
2665 | }else{ |
2666 | if(!((i_regs->wasconst>>sl)&1)) |
277718fa |
2667 | emit_xorimm(sl,cinfo[i].imm,tl); |
581335b0 |
2668 | else |
277718fa |
2669 | emit_movimm(constmap[i][sl]^cinfo[i].imm,tl); |
581335b0 |
2670 | } |
57871462 |
2671 | } |
2672 | } |
2673 | else { |
277718fa |
2674 | emit_movimm(cinfo[i].imm,tl); |
57871462 |
2675 | } |
2676 | } |
2677 | } |
2678 | } |
2679 | } |
2680 | } |
2681 | |
2330734f |
2682 | static void shiftimm_assemble(int i, const struct regstat *i_regs) |
57871462 |
2683 | { |
cf95b4f0 |
2684 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA |
57871462 |
2685 | { |
cf95b4f0 |
2686 | if(dops[i].rt1) { |
57871462 |
2687 | signed char s,t; |
a5cd72d0 |
2688 | t=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
2689 | s=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 |
2690 | //assert(t>=0); |
dc49e339 |
2691 | if(t>=0&&!((i_regs->isconst>>t)&1)){ |
cf95b4f0 |
2692 | if(dops[i].rs1==0) |
57871462 |
2693 | { |
2694 | emit_zeroreg(t); |
2695 | } |
2696 | else |
2697 | { |
cf95b4f0 |
2698 | if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
277718fa |
2699 | if(cinfo[i].imm) { |
cf95b4f0 |
2700 | if(dops[i].opcode2==0) // SLL |
57871462 |
2701 | { |
277718fa |
2702 | emit_shlimm(s<0?t:s,cinfo[i].imm,t); |
57871462 |
2703 | } |
cf95b4f0 |
2704 | if(dops[i].opcode2==2) // SRL |
57871462 |
2705 | { |
277718fa |
2706 | emit_shrimm(s<0?t:s,cinfo[i].imm,t); |
57871462 |
2707 | } |
cf95b4f0 |
2708 | if(dops[i].opcode2==3) // SRA |
57871462 |
2709 | { |
277718fa |
2710 | emit_sarimm(s<0?t:s,cinfo[i].imm,t); |
57871462 |
2711 | } |
2712 | }else{ |
2713 | // Shift by zero |
2714 | if(s>=0 && s!=t) emit_mov(s,t); |
2715 | } |
2716 | } |
2717 | } |
cf95b4f0 |
2718 | //emit_storereg(dops[i].rt1,t); //DEBUG |
57871462 |
2719 | } |
2720 | } |
cf95b4f0 |
2721 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA |
57871462 |
2722 | { |
9c45ca93 |
2723 | assert(0); |
57871462 |
2724 | } |
cf95b4f0 |
2725 | if(dops[i].opcode2==0x3c) // DSLL32 |
57871462 |
2726 | { |
9c45ca93 |
2727 | assert(0); |
57871462 |
2728 | } |
cf95b4f0 |
2729 | if(dops[i].opcode2==0x3e) // DSRL32 |
57871462 |
2730 | { |
9c45ca93 |
2731 | assert(0); |
57871462 |
2732 | } |
cf95b4f0 |
2733 | if(dops[i].opcode2==0x3f) // DSRA32 |
57871462 |
2734 | { |
9c45ca93 |
2735 | assert(0); |
57871462 |
2736 | } |
2737 | } |
2738 | |
2739 | #ifndef shift_assemble |
2330734f |
2740 | static void shift_assemble(int i, const struct regstat *i_regs) |
57871462 |
2741 | { |
3968e69e |
2742 | signed char s,t,shift; |
cf95b4f0 |
2743 | if (dops[i].rt1 == 0) |
3968e69e |
2744 | return; |
cf95b4f0 |
2745 | assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV |
2746 | t = get_reg(i_regs->regmap, dops[i].rt1); |
2747 | s = get_reg(i_regs->regmap, dops[i].rs1); |
2748 | shift = get_reg(i_regs->regmap, dops[i].rs2); |
3968e69e |
2749 | if (t < 0) |
2750 | return; |
2751 | |
cf95b4f0 |
2752 | if(dops[i].rs1==0) |
3968e69e |
2753 | emit_zeroreg(t); |
cf95b4f0 |
2754 | else if(dops[i].rs2==0) { |
3968e69e |
2755 | assert(s>=0); |
2756 | if(s!=t) emit_mov(s,t); |
2757 | } |
2758 | else { |
2759 | host_tempreg_acquire(); |
2760 | emit_andimm(shift,31,HOST_TEMPREG); |
cf95b4f0 |
2761 | switch(dops[i].opcode2) { |
3968e69e |
2762 | case 4: // SLLV |
2763 | emit_shl(s,HOST_TEMPREG,t); |
2764 | break; |
2765 | case 6: // SRLV |
2766 | emit_shr(s,HOST_TEMPREG,t); |
2767 | break; |
2768 | case 7: // SRAV |
2769 | emit_sar(s,HOST_TEMPREG,t); |
2770 | break; |
2771 | default: |
2772 | assert(0); |
2773 | } |
2774 | host_tempreg_release(); |
2775 | } |
57871462 |
2776 | } |
3968e69e |
2777 | |
57871462 |
2778 | #endif |
2779 | |
8062d65a |
2780 | enum { |
2781 | MTYPE_8000 = 0, |
2782 | MTYPE_8020, |
2783 | MTYPE_0000, |
2784 | MTYPE_A000, |
2785 | MTYPE_1F80, |
2786 | }; |
2787 | |
2788 | static int get_ptr_mem_type(u_int a) |
2789 | { |
2790 | if(a < 0x00200000) { |
2791 | if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0)) |
2792 | // return wrong, must use memhandler for BIOS self-test to pass |
2793 | // 007 does similar stuff from a00 mirror, weird stuff |
2794 | return MTYPE_8000; |
2795 | return MTYPE_0000; |
2796 | } |
2797 | if(0x1f800000 <= a && a < 0x1f801000) |
2798 | return MTYPE_1F80; |
2799 | if(0x80200000 <= a && a < 0x80800000) |
2800 | return MTYPE_8020; |
2801 | if(0xa0000000 <= a && a < 0xa0200000) |
2802 | return MTYPE_A000; |
2803 | return MTYPE_8000; |
2804 | } |
2805 | |
37387d8b |
2806 | static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) |
2807 | { |
2808 | int r = get_reg(i_regs->regmap, ROREG); |
2809 | if (r < 0 && host_tempreg_free) { |
2810 | host_tempreg_acquire(); |
2811 | emit_loadreg(ROREG, r = HOST_TEMPREG); |
2812 | } |
2813 | if (r < 0) |
2814 | abort(); |
2815 | return r; |
2816 | } |
2817 | |
2818 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, |
277718fa |
2819 | int addr, int *offset_reg, int *addr_reg_override, int ccadj_) |
8062d65a |
2820 | { |
2821 | void *jaddr = NULL; |
37387d8b |
2822 | int type = 0; |
2823 | int mr = dops[i].rs1; |
277718fa |
2824 | assert(addr >= 0); |
37387d8b |
2825 | *offset_reg = -1; |
8062d65a |
2826 | if(((smrv_strong|smrv_weak)>>mr)&1) { |
2827 | type=get_ptr_mem_type(smrv[mr]); |
2828 | //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); |
2829 | } |
2830 | else { |
2831 | // use the mirror we are running on |
2832 | type=get_ptr_mem_type(start); |
2833 | //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type); |
2834 | } |
2835 | |
277718fa |
2836 | if (dops[i].may_except) { |
2837 | // alignment check |
2838 | u_int op = dops[i].opcode; |
2839 | int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU |
2840 | void *jaddr; |
2841 | emit_testimm(addr, mask); |
2842 | jaddr = out; |
2843 | emit_jne(0); |
2844 | add_stub_r(ALIGNMENT_STUB, jaddr, out, i, addr, i_regs, ccadj_, 0); |
2845 | } |
2846 | |
8062d65a |
2847 | if(type==MTYPE_8020) { // RAM 80200000+ mirror |
d1e4ebd9 |
2848 | host_tempreg_acquire(); |
8062d65a |
2849 | emit_andimm(addr,~0x00e00000,HOST_TEMPREG); |
2850 | addr=*addr_reg_override=HOST_TEMPREG; |
2851 | type=0; |
2852 | } |
2853 | else if(type==MTYPE_0000) { // RAM 0 mirror |
d1e4ebd9 |
2854 | host_tempreg_acquire(); |
8062d65a |
2855 | emit_orimm(addr,0x80000000,HOST_TEMPREG); |
2856 | addr=*addr_reg_override=HOST_TEMPREG; |
2857 | type=0; |
2858 | } |
2859 | else if(type==MTYPE_A000) { // RAM A mirror |
d1e4ebd9 |
2860 | host_tempreg_acquire(); |
8062d65a |
2861 | emit_andimm(addr,~0x20000000,HOST_TEMPREG); |
2862 | addr=*addr_reg_override=HOST_TEMPREG; |
2863 | type=0; |
2864 | } |
2865 | else if(type==MTYPE_1F80) { // scratchpad |
2866 | if (psxH == (void *)0x1f800000) { |
d1e4ebd9 |
2867 | host_tempreg_acquire(); |
3968e69e |
2868 | emit_xorimm(addr,0x1f800000,HOST_TEMPREG); |
8062d65a |
2869 | emit_cmpimm(HOST_TEMPREG,0x1000); |
d1e4ebd9 |
2870 | host_tempreg_release(); |
8062d65a |
2871 | jaddr=out; |
2872 | emit_jc(0); |
2873 | } |
2874 | else { |
2875 | // do the usual RAM check, jump will go to the right handler |
2876 | type=0; |
2877 | } |
2878 | } |
2879 | |
37387d8b |
2880 | if (type == 0) // need ram check |
8062d65a |
2881 | { |
2882 | emit_cmpimm(addr,RAM_SIZE); |
37387d8b |
2883 | jaddr = out; |
8062d65a |
2884 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
2885 | // Hint to branch predictor that the branch is unlikely to be taken |
37387d8b |
2886 | if (dops[i].rs1 >= 28) |
8062d65a |
2887 | emit_jno_unlikely(0); |
2888 | else |
2889 | #endif |
2890 | emit_jno(0); |
37387d8b |
2891 | if (ram_offset != 0) |
2892 | *offset_reg = get_ro_reg(i_regs, 0); |
8062d65a |
2893 | } |
2894 | |
2895 | return jaddr; |
2896 | } |
2897 | |
687b4580 |
2898 | // return memhandler, or get directly accessable address and return 0 |
2899 | static void *get_direct_memhandler(void *table, u_int addr, |
2900 | enum stub_type type, uintptr_t *addr_host) |
2901 | { |
c979e8c2 |
2902 | uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); |
687b4580 |
2903 | uintptr_t l1, l2 = 0; |
2904 | l1 = ((uintptr_t *)table)[addr>>12]; |
c979e8c2 |
2905 | if (!(l1 & msb)) { |
687b4580 |
2906 | uintptr_t v = l1 << 1; |
2907 | *addr_host = v + addr; |
2908 | return NULL; |
2909 | } |
2910 | else { |
2911 | l1 <<= 1; |
2912 | if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) |
2913 | l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; |
2914 | else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) |
c979e8c2 |
2915 | l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; |
687b4580 |
2916 | else |
c979e8c2 |
2917 | l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; |
2918 | if (!(l2 & msb)) { |
687b4580 |
2919 | uintptr_t v = l2 << 1; |
2920 | *addr_host = v + (addr&0xfff); |
2921 | return NULL; |
2922 | } |
2923 | return (void *)(l2 << 1); |
2924 | } |
2925 | } |
2926 | |
81dbbf4c |
2927 | static u_int get_host_reglist(const signed char *regmap) |
2928 | { |
2929 | u_int reglist = 0, hr; |
2930 | for (hr = 0; hr < HOST_REGS; hr++) { |
2931 | if (hr != EXCLUDE_REG && regmap[hr] >= 0) |
2932 | reglist |= 1 << hr; |
2933 | } |
2934 | return reglist; |
2935 | } |
2936 | |
2937 | static u_int reglist_exclude(u_int reglist, int r1, int r2) |
2938 | { |
2939 | if (r1 >= 0) |
2940 | reglist &= ~(1u << r1); |
2941 | if (r2 >= 0) |
2942 | reglist &= ~(1u << r2); |
2943 | return reglist; |
2944 | } |
2945 | |
e3c6bdb5 |
2946 | // find a temp caller-saved register not in reglist (so assumed to be free) |
2947 | static int reglist_find_free(u_int reglist) |
2948 | { |
2949 | u_int free_regs = ~reglist & CALLER_SAVE_REGS; |
2950 | if (free_regs == 0) |
2951 | return -1; |
2952 | return __builtin_ctz(free_regs); |
2953 | } |
2954 | |
37387d8b |
2955 | static void do_load_word(int a, int rt, int offset_reg) |
2956 | { |
2957 | if (offset_reg >= 0) |
2958 | emit_ldr_dualindexed(offset_reg, a, rt); |
2959 | else |
2960 | emit_readword_indexed(0, a, rt); |
2961 | } |
2962 | |
2963 | static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) |
2964 | { |
2965 | if (offset_reg < 0) { |
2966 | emit_writeword_indexed(rt, ofs, a); |
2967 | return; |
2968 | } |
2969 | if (ofs != 0) |
2970 | emit_addimm(a, ofs, a); |
2971 | emit_str_dualindexed(offset_reg, a, rt); |
2972 | if (ofs != 0 && preseve_a) |
2973 | emit_addimm(a, -ofs, a); |
2974 | } |
2975 | |
2976 | static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) |
2977 | { |
2978 | if (offset_reg < 0) { |
2979 | emit_writehword_indexed(rt, ofs, a); |
2980 | return; |
2981 | } |
2982 | if (ofs != 0) |
2983 | emit_addimm(a, ofs, a); |
2984 | emit_strh_dualindexed(offset_reg, a, rt); |
2985 | if (ofs != 0 && preseve_a) |
2986 | emit_addimm(a, -ofs, a); |
2987 | } |
2988 | |
2989 | static void do_store_byte(int a, int rt, int offset_reg) |
2990 | { |
2991 | if (offset_reg >= 0) |
2992 | emit_strb_dualindexed(offset_reg, a, rt); |
2993 | else |
2994 | emit_writebyte_indexed(rt, 0, a); |
2995 | } |
2996 | |
2330734f |
2997 | static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
2998 | { |
277718fa |
2999 | int addr = cinfo[i].addr; |
3000 | int s,tl; |
57871462 |
3001 | int offset; |
b14b6a8f |
3002 | void *jaddr=0; |
5bf843dc |
3003 | int memtarget=0,c=0; |
37387d8b |
3004 | int offset_reg = -1; |
3005 | int fastio_reg_override = -1; |
81dbbf4c |
3006 | u_int reglist=get_host_reglist(i_regs->regmap); |
a5cd72d0 |
3007 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
3008 | s=get_reg(i_regs->regmap,dops[i].rs1); |
277718fa |
3009 | offset=cinfo[i].imm; |
57871462 |
3010 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3011 | if(s>=0) { |
3012 | c=(i_regs->wasconst>>s)&1; |
af4ee1fe |
3013 | if (c) { |
3014 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
af4ee1fe |
3015 | } |
57871462 |
3016 | } |
57871462 |
3017 | //printf("load_assemble: c=%d\n",c); |
643aeae3 |
3018 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
a5cd72d0 |
3019 | if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) { |
5bf843dc |
3020 | // could be FIFO, must perform the read |
f18c0f46 |
3021 | // ||dummy read |
5bf843dc |
3022 | assem_debug("(forced read)\n"); |
277718fa |
3023 | tl = get_reg_temp(i_regs->regmap); // may be == addr |
5bf843dc |
3024 | assert(tl>=0); |
5bf843dc |
3025 | } |
277718fa |
3026 | assert(addr >= 0); |
535d208a |
3027 | if(tl>=0) { |
3028 | //printf("load_assemble: c=%d\n",c); |
643aeae3 |
3029 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
535d208a |
3030 | reglist&=~(1<<tl); |
1edfcc68 |
3031 | if(!c) { |
1edfcc68 |
3032 | #ifdef R29_HACK |
3033 | // Strmnnrmn's speed hack |
cf95b4f0 |
3034 | if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
1edfcc68 |
3035 | #endif |
3036 | { |
37387d8b |
3037 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, |
277718fa |
3038 | &offset_reg, &fastio_reg_override, ccadj_); |
535d208a |
3039 | } |
1edfcc68 |
3040 | } |
37387d8b |
3041 | else if (ram_offset && memtarget) { |
3042 | offset_reg = get_ro_reg(i_regs, 0); |
535d208a |
3043 | } |
a5cd72d0 |
3044 | int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg |
37387d8b |
3045 | switch (dops[i].opcode) { |
3046 | case 0x20: // LB |
535d208a |
3047 | if(!c||memtarget) { |
3048 | if(!dummy) { |
277718fa |
3049 | int a = addr; |
37387d8b |
3050 | if (fastio_reg_override >= 0) |
3051 | a = fastio_reg_override; |
b1570849 |
3052 | |
37387d8b |
3053 | if (offset_reg >= 0) |
3054 | emit_ldrsb_dualindexed(offset_reg, a, tl); |
3055 | else |
3056 | emit_movsbl_indexed(0, a, tl); |
57871462 |
3057 | } |
535d208a |
3058 | if(jaddr) |
2330734f |
3059 | add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 |
3060 | } |
535d208a |
3061 | else |
2330734f |
3062 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
37387d8b |
3063 | break; |
3064 | case 0x21: // LH |
535d208a |
3065 | if(!c||memtarget) { |
3066 | if(!dummy) { |
277718fa |
3067 | int a = addr; |
37387d8b |
3068 | if (fastio_reg_override >= 0) |
3069 | a = fastio_reg_override; |
3070 | if (offset_reg >= 0) |
3071 | emit_ldrsh_dualindexed(offset_reg, a, tl); |
3072 | else |
3073 | emit_movswl_indexed(0, a, tl); |
57871462 |
3074 | } |
535d208a |
3075 | if(jaddr) |
2330734f |
3076 | add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 |
3077 | } |
535d208a |
3078 | else |
2330734f |
3079 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
37387d8b |
3080 | break; |
3081 | case 0x23: // LW |
535d208a |
3082 | if(!c||memtarget) { |
3083 | if(!dummy) { |
37387d8b |
3084 | int a = addr; |
3085 | if (fastio_reg_override >= 0) |
3086 | a = fastio_reg_override; |
3087 | do_load_word(a, tl, offset_reg); |
57871462 |
3088 | } |
535d208a |
3089 | if(jaddr) |
2330734f |
3090 | add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 |
3091 | } |
535d208a |
3092 | else |
2330734f |
3093 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
37387d8b |
3094 | break; |
3095 | case 0x24: // LBU |
535d208a |
3096 | if(!c||memtarget) { |
3097 | if(!dummy) { |
277718fa |
3098 | int a = addr; |
37387d8b |
3099 | if (fastio_reg_override >= 0) |
3100 | a = fastio_reg_override; |
b1570849 |
3101 | |
37387d8b |
3102 | if (offset_reg >= 0) |
3103 | emit_ldrb_dualindexed(offset_reg, a, tl); |
3104 | else |
3105 | emit_movzbl_indexed(0, a, tl); |
57871462 |
3106 | } |
535d208a |
3107 | if(jaddr) |
2330734f |
3108 | add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 |
3109 | } |
535d208a |
3110 | else |
2330734f |
3111 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
37387d8b |
3112 | break; |
3113 | case 0x25: // LHU |
535d208a |
3114 | if(!c||memtarget) { |
3115 | if(!dummy) { |
277718fa |
3116 | int a = addr; |
37387d8b |
3117 | if (fastio_reg_override >= 0) |
3118 | a = fastio_reg_override; |
3119 | if (offset_reg >= 0) |
3120 | emit_ldrh_dualindexed(offset_reg, a, tl); |
3121 | else |
3122 | emit_movzwl_indexed(0, a, tl); |
57871462 |
3123 | } |
535d208a |
3124 | if(jaddr) |
2330734f |
3125 | add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 |
3126 | } |
535d208a |
3127 | else |
2330734f |
3128 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
37387d8b |
3129 | break; |
37387d8b |
3130 | default: |
9c45ca93 |
3131 | assert(0); |
57871462 |
3132 | } |
a5cd72d0 |
3133 | } // tl >= 0 |
37387d8b |
3134 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
d1e4ebd9 |
3135 | host_tempreg_release(); |
57871462 |
3136 | } |
3137 | |
3138 | #ifndef loadlr_assemble |
2330734f |
3139 | static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
3140 | { |
277718fa |
3141 | int addr = cinfo[i].addr; |
3142 | int s,tl,temp,temp2; |
3968e69e |
3143 | int offset; |
3144 | void *jaddr=0; |
3145 | int memtarget=0,c=0; |
37387d8b |
3146 | int offset_reg = -1; |
3147 | int fastio_reg_override = -1; |
81dbbf4c |
3148 | u_int reglist=get_host_reglist(i_regs->regmap); |
a5cd72d0 |
3149 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
3150 | s=get_reg(i_regs->regmap,dops[i].rs1); |
9de8a0c3 |
3151 | temp=get_reg_temp(i_regs->regmap); |
3968e69e |
3152 | temp2=get_reg(i_regs->regmap,FTEMP); |
277718fa |
3153 | offset=cinfo[i].imm; |
3968e69e |
3154 | reglist|=1<<temp; |
277718fa |
3155 | assert(addr >= 0); |
3968e69e |
3156 | if(s>=0) { |
3157 | c=(i_regs->wasconst>>s)&1; |
3158 | if(c) { |
3159 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
3160 | } |
3161 | } |
3162 | if(!c) { |
3163 | emit_shlimm(addr,3,temp); |
cf95b4f0 |
3164 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
3968e69e |
3165 | emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR |
3166 | }else{ |
3167 | emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR |
3168 | } |
37387d8b |
3169 | jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, |
277718fa |
3170 | &offset_reg, &fastio_reg_override, ccadj_); |
3968e69e |
3171 | } |
3172 | else { |
37387d8b |
3173 | if (ram_offset && memtarget) { |
3174 | offset_reg = get_ro_reg(i_regs, 0); |
3968e69e |
3175 | } |
cf95b4f0 |
3176 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
3968e69e |
3177 | emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR |
3178 | }else{ |
3179 | emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR |
3180 | } |
3181 | } |
cf95b4f0 |
3182 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR |
3968e69e |
3183 | if(!c||memtarget) { |
37387d8b |
3184 | int a = temp2; |
3185 | if (fastio_reg_override >= 0) |
3186 | a = fastio_reg_override; |
3187 | do_load_word(a, temp2, offset_reg); |
3188 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
3189 | host_tempreg_release(); |
2330734f |
3190 | if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); |
3968e69e |
3191 | } |
3192 | else |
2330734f |
3193 | inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); |
cf95b4f0 |
3194 | if(dops[i].rt1) { |
3968e69e |
3195 | assert(tl>=0); |
3196 | emit_andimm(temp,24,temp); |
cf95b4f0 |
3197 | if (dops[i].opcode==0x22) // LWL |
3968e69e |
3198 | emit_xorimm(temp,24,temp); |
3199 | host_tempreg_acquire(); |
3200 | emit_movimm(-1,HOST_TEMPREG); |
cf95b4f0 |
3201 | if (dops[i].opcode==0x26) { |
3968e69e |
3202 | emit_shr(temp2,temp,temp2); |
3203 | emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); |
3204 | }else{ |
3205 | emit_shl(temp2,temp,temp2); |
3206 | emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); |
3207 | } |
3208 | host_tempreg_release(); |
3209 | emit_or(temp2,tl,tl); |
3210 | } |
cf95b4f0 |
3211 | //emit_storereg(dops[i].rt1,tl); // DEBUG |
3968e69e |
3212 | } |
cf95b4f0 |
3213 | if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR |
3968e69e |
3214 | assert(0); |
3215 | } |
57871462 |
3216 | } |
3217 | #endif |
3218 | |
9b495f6e |
3219 | static void do_invstub(int n) |
3220 | { |
3221 | literal_pool(20); |
3222 | assem_debug("do_invstub\n"); |
3223 | u_int reglist = stubs[n].a; |
3224 | u_int addrr = stubs[n].b; |
3225 | int ofs_start = stubs[n].c; |
3226 | int ofs_end = stubs[n].d; |
3227 | int len = ofs_end - ofs_start; |
3228 | u_int rightr = 0; |
3229 | |
3230 | set_jump_target(stubs[n].addr, out); |
3231 | save_regs(reglist); |
9b495f6e |
3232 | if (addrr != 0 || ofs_start != 0) |
3233 | emit_addimm(addrr, ofs_start, 0); |
3033d898 |
3234 | emit_readword(&inv_code_start, 2); |
3235 | emit_readword(&inv_code_end, 3); |
9b495f6e |
3236 | if (len != 0) |
3237 | emit_addimm(0, len + 4, (rightr = 1)); |
3238 | emit_cmp(0, 2); |
3239 | emit_cmpcs(3, rightr); |
3240 | void *jaddr = out; |
3241 | emit_jc(0); |
3242 | void *func = (len != 0) |
3243 | ? (void *)ndrc_write_invalidate_many |
3244 | : (void *)ndrc_write_invalidate_one; |
3245 | emit_far_call(func); |
3246 | set_jump_target(jaddr, out); |
3247 | restore_regs(reglist); |
3248 | emit_jmp(stubs[n].retaddr); |
3249 | } |
3250 | |
3251 | static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr) |
3252 | { |
3253 | if (HACK_ENABLED(NDHACK_NO_SMC_CHECK)) |
3254 | return; |
3255 | // this can't be used any more since we started to check exact |
3256 | // block boundaries in invalidate_range() |
3257 | //if (i_regs->waswritten & (1<<dops[i].rs1)) |
3258 | // return; |
3259 | // (naively) assume nobody will run code from stack |
3260 | if (dops[i].rs1 == 29) |
3261 | return; |
3262 | |
277718fa |
3263 | int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1; |
9b495f6e |
3264 | if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1 |
277718fa |
3265 | && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff) |
9b495f6e |
3266 | return; |
3267 | for (j = i - 1; j >= 0; j--) { |
3268 | if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1 |
277718fa |
3269 | || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff) |
9b495f6e |
3270 | break; |
3271 | count++; |
277718fa |
3272 | if (imm_min > cinfo[j].imm) |
3273 | imm_min = cinfo[j].imm; |
3274 | if (imm_max < cinfo[j].imm) |
3275 | imm_max = cinfo[j].imm; |
9b495f6e |
3276 | } |
3277 | #if defined(HOST_IMM8) |
3278 | int ir = get_reg(i_regs->regmap, INVCP); |
3279 | assert(ir >= 0); |
3280 | host_tempreg_acquire(); |
3281 | emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG); |
3282 | #else |
3283 | emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1); |
3284 | #error not handled |
3285 | #endif |
3286 | #ifdef INVALIDATE_USE_COND_CALL |
3287 | if (count == 1) { |
3288 | emit_cmpimm(HOST_TEMPREG, 1); |
3289 | emit_callne(invalidate_addr_reg[addr]); |
3290 | host_tempreg_release(); |
3291 | return; |
3292 | } |
3293 | #endif |
3294 | void *jaddr = emit_cbz(HOST_TEMPREG, 0); |
3295 | host_tempreg_release(); |
277718fa |
3296 | imm_min -= cinfo[i].imm; |
3297 | imm_max -= cinfo[i].imm; |
9b495f6e |
3298 | add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG), |
3299 | addr, imm_min, imm_max, 0); |
3300 | } |
3301 | |
2330734f |
3302 | static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
3303 | { |
9c45ca93 |
3304 | int s,tl; |
277718fa |
3305 | int addr = cinfo[i].addr; |
57871462 |
3306 | int offset; |
b14b6a8f |
3307 | void *jaddr=0; |
37387d8b |
3308 | enum stub_type type=0; |
666a299d |
3309 | int memtarget=0,c=0; |
37387d8b |
3310 | int offset_reg = -1; |
3311 | int fastio_reg_override = -1; |
81dbbf4c |
3312 | u_int reglist=get_host_reglist(i_regs->regmap); |
cf95b4f0 |
3313 | tl=get_reg(i_regs->regmap,dops[i].rs2); |
3314 | s=get_reg(i_regs->regmap,dops[i].rs1); |
277718fa |
3315 | offset=cinfo[i].imm; |
57871462 |
3316 | if(s>=0) { |
3317 | c=(i_regs->wasconst>>s)&1; |
af4ee1fe |
3318 | if(c) { |
3319 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
af4ee1fe |
3320 | } |
57871462 |
3321 | } |
3322 | assert(tl>=0); |
277718fa |
3323 | assert(addr >= 0); |
57871462 |
3324 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
37387d8b |
3325 | if (!c) { |
3326 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, |
277718fa |
3327 | &offset_reg, &fastio_reg_override, ccadj_); |
1edfcc68 |
3328 | } |
37387d8b |
3329 | else if (ram_offset && memtarget) { |
3330 | offset_reg = get_ro_reg(i_regs, 0); |
57871462 |
3331 | } |
3332 | |
37387d8b |
3333 | switch (dops[i].opcode) { |
3334 | case 0x28: // SB |
57871462 |
3335 | if(!c||memtarget) { |
277718fa |
3336 | int a = addr; |
37387d8b |
3337 | if (fastio_reg_override >= 0) |
3338 | a = fastio_reg_override; |
3339 | do_store_byte(a, tl, offset_reg); |
3340 | } |
3341 | type = STOREB_STUB; |
3342 | break; |
3343 | case 0x29: // SH |
57871462 |
3344 | if(!c||memtarget) { |
277718fa |
3345 | int a = addr; |
37387d8b |
3346 | if (fastio_reg_override >= 0) |
3347 | a = fastio_reg_override; |
3348 | do_store_hword(a, 0, tl, offset_reg, 1); |
3349 | } |
3350 | type = STOREH_STUB; |
3351 | break; |
3352 | case 0x2B: // SW |
dadf55f2 |
3353 | if(!c||memtarget) { |
37387d8b |
3354 | int a = addr; |
3355 | if (fastio_reg_override >= 0) |
3356 | a = fastio_reg_override; |
3357 | do_store_word(a, 0, tl, offset_reg, 1); |
3358 | } |
3359 | type = STOREW_STUB; |
3360 | break; |
37387d8b |
3361 | default: |
9c45ca93 |
3362 | assert(0); |
57871462 |
3363 | } |
37387d8b |
3364 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
d1e4ebd9 |
3365 | host_tempreg_release(); |
b96d3df7 |
3366 | if(jaddr) { |
3367 | // PCSX store handlers don't check invcode again |
3368 | reglist|=1<<addr; |
2330734f |
3369 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
b96d3df7 |
3370 | jaddr=0; |
3371 | } |
9b495f6e |
3372 | { |
57871462 |
3373 | if(!c||memtarget) { |
9b495f6e |
3374 | do_store_smc_check(i, i_regs, reglist, addr); |
57871462 |
3375 | } |
3376 | } |
7a518516 |
3377 | u_int addr_val=constmap[i][s]+offset; |
3eaa7048 |
3378 | if(jaddr) { |
2330734f |
3379 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
3eaa7048 |
3380 | } else if(c&&!memtarget) { |
2330734f |
3381 | inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); |
7a518516 |
3382 | } |
3383 | // basic current block modification detection.. |
3384 | // not looking back as that should be in mips cache already |
3968e69e |
3385 | // (see Spyro2 title->attract mode) |
7a518516 |
3386 | if(c&&start+i*4<addr_val&&addr_val<start+slen*4) { |
c43b5311 |
3387 | SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4); |
7a518516 |
3388 | assert(i_regs->regmap==regs[i].regmap); // not delay slot |
3389 | if(i_regs->regmap==regs[i].regmap) { |
ad49de89 |
3390 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); |
3391 | wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty); |
7a518516 |
3392 | emit_movimm(start+i*4+4,0); |
643aeae3 |
3393 | emit_writeword(0,&pcaddr); |
d1e4ebd9 |
3394 | emit_addimm(HOST_CCREG,2,HOST_CCREG); |
104df9d3 |
3395 | emit_far_call(ndrc_get_addr_ht); |
d1e4ebd9 |
3396 | emit_jmpreg(0); |
7a518516 |
3397 | } |
3eaa7048 |
3398 | } |
57871462 |
3399 | } |
3400 | |
2330734f |
3401 | static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
3402 | { |
277718fa |
3403 | int addr = cinfo[i].addr; |
9c45ca93 |
3404 | int s,tl; |
57871462 |
3405 | int offset; |
b14b6a8f |
3406 | void *jaddr=0; |
37387d8b |
3407 | void *case1, *case23, *case3; |
df4dc2b1 |
3408 | void *done0, *done1, *done2; |
af4ee1fe |
3409 | int memtarget=0,c=0; |
37387d8b |
3410 | int offset_reg = -1; |
81dbbf4c |
3411 | u_int reglist=get_host_reglist(i_regs->regmap); |
cf95b4f0 |
3412 | tl=get_reg(i_regs->regmap,dops[i].rs2); |
3413 | s=get_reg(i_regs->regmap,dops[i].rs1); |
277718fa |
3414 | offset=cinfo[i].imm; |
57871462 |
3415 | if(s>=0) { |
3416 | c=(i_regs->isconst>>s)&1; |
af4ee1fe |
3417 | if(c) { |
3418 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
af4ee1fe |
3419 | } |
57871462 |
3420 | } |
3421 | assert(tl>=0); |
277718fa |
3422 | assert(addr >= 0); |
1edfcc68 |
3423 | if(!c) { |
277718fa |
3424 | emit_cmpimm(addr, RAM_SIZE); |
b14b6a8f |
3425 | jaddr=out; |
1edfcc68 |
3426 | emit_jno(0); |
3427 | } |
3428 | else |
3429 | { |
cf95b4f0 |
3430 | if(!memtarget||!dops[i].rs1) { |
b14b6a8f |
3431 | jaddr=out; |
535d208a |
3432 | emit_jmp(0); |
57871462 |
3433 | } |
535d208a |
3434 | } |
37387d8b |
3435 | if (ram_offset) |
3436 | offset_reg = get_ro_reg(i_regs, 0); |
535d208a |
3437 | |
277718fa |
3438 | emit_testimm(addr,2); |
37387d8b |
3439 | case23=out; |
535d208a |
3440 | emit_jne(0); |
277718fa |
3441 | emit_testimm(addr,1); |
df4dc2b1 |
3442 | case1=out; |
535d208a |
3443 | emit_jne(0); |
3444 | // 0 |
37387d8b |
3445 | if (dops[i].opcode == 0x2A) { // SWL |
3446 | // Write msb into least significant byte |
3447 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); |
277718fa |
3448 | do_store_byte(addr, tl, offset_reg); |
37387d8b |
3449 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
535d208a |
3450 | } |
37387d8b |
3451 | else if (dops[i].opcode == 0x2E) { // SWR |
3452 | // Write entire word |
277718fa |
3453 | do_store_word(addr, 0, tl, offset_reg, 1); |
535d208a |
3454 | } |
37387d8b |
3455 | done0 = out; |
535d208a |
3456 | emit_jmp(0); |
3457 | // 1 |
df4dc2b1 |
3458 | set_jump_target(case1, out); |
37387d8b |
3459 | if (dops[i].opcode == 0x2A) { // SWL |
3460 | // Write two msb into two least significant bytes |
3461 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); |
277718fa |
3462 | do_store_hword(addr, -1, tl, offset_reg, 0); |
37387d8b |
3463 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); |
535d208a |
3464 | } |
37387d8b |
3465 | else if (dops[i].opcode == 0x2E) { // SWR |
3466 | // Write 3 lsb into three most significant bytes |
277718fa |
3467 | do_store_byte(addr, tl, offset_reg); |
37387d8b |
3468 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
277718fa |
3469 | do_store_hword(addr, 1, tl, offset_reg, 0); |
37387d8b |
3470 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); |
535d208a |
3471 | } |
df4dc2b1 |
3472 | done1=out; |
535d208a |
3473 | emit_jmp(0); |
37387d8b |
3474 | // 2,3 |
3475 | set_jump_target(case23, out); |
277718fa |
3476 | emit_testimm(addr,1); |
37387d8b |
3477 | case3 = out; |
535d208a |
3478 | emit_jne(0); |
37387d8b |
3479 | // 2 |
cf95b4f0 |
3480 | if (dops[i].opcode==0x2A) { // SWL |
37387d8b |
3481 | // Write 3 msb into three least significant bytes |
3482 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
277718fa |
3483 | do_store_hword(addr, -2, tl, offset_reg, 1); |
37387d8b |
3484 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); |
277718fa |
3485 | do_store_byte(addr, tl, offset_reg); |
37387d8b |
3486 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); |
535d208a |
3487 | } |
37387d8b |
3488 | else if (dops[i].opcode == 0x2E) { // SWR |
3489 | // Write two lsb into two most significant bytes |
277718fa |
3490 | do_store_hword(addr, 0, tl, offset_reg, 1); |
535d208a |
3491 | } |
37387d8b |
3492 | done2 = out; |
535d208a |
3493 | emit_jmp(0); |
3494 | // 3 |
df4dc2b1 |
3495 | set_jump_target(case3, out); |
37387d8b |
3496 | if (dops[i].opcode == 0x2A) { // SWL |
277718fa |
3497 | do_store_word(addr, -3, tl, offset_reg, 0); |
535d208a |
3498 | } |
37387d8b |
3499 | else if (dops[i].opcode == 0x2E) { // SWR |
277718fa |
3500 | do_store_byte(addr, tl, offset_reg); |
535d208a |
3501 | } |
df4dc2b1 |
3502 | set_jump_target(done0, out); |
3503 | set_jump_target(done1, out); |
3504 | set_jump_target(done2, out); |
37387d8b |
3505 | if (offset_reg == HOST_TEMPREG) |
3506 | host_tempreg_release(); |
535d208a |
3507 | if(!c||!memtarget) |
277718fa |
3508 | add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
3509 | do_store_smc_check(i, i_regs, reglist, addr); |
57871462 |
3510 | } |
3511 | |
2330734f |
3512 | static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) |
8062d65a |
3513 | { |
cf95b4f0 |
3514 | if(dops[i].opcode2==0) // MFC0 |
8062d65a |
3515 | { |
a5cd72d0 |
3516 | signed char t=get_reg_w(i_regs->regmap, dops[i].rt1); |
8062d65a |
3517 | u_int copr=(source[i]>>11)&0x1f; |
cf95b4f0 |
3518 | if(t>=0&&dops[i].rt1!=0) { |
8062d65a |
3519 | emit_readword(®_cop0[copr],t); |
3520 | } |
3521 | } |
cf95b4f0 |
3522 | else if(dops[i].opcode2==4) // MTC0 |
8062d65a |
3523 | { |
de6dbc52 |
3524 | int s = get_reg(i_regs->regmap, dops[i].rs1); |
3525 | int cc = get_reg(i_regs->regmap, CCREG); |
8062d65a |
3526 | char copr=(source[i]>>11)&0x1f; |
3527 | assert(s>=0); |
cf95b4f0 |
3528 | wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); |
de6dbc52 |
3529 | if (copr == 12 || copr == 13) { |
8062d65a |
3530 | emit_readword(&last_count,HOST_TEMPREG); |
de6dbc52 |
3531 | if (cc != HOST_CCREG) |
3532 | emit_loadreg(CCREG, HOST_CCREG); |
3533 | emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG); |
3534 | emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG); |
3535 | emit_writeword(HOST_CCREG, &psxRegs.cycle); |
8062d65a |
3536 | if (is_delayslot) { |
3537 | // burn cycles to cause cc_interrupt, which will |
3538 | // reschedule next_interupt. Relies on CCREG from above. |
3539 | assem_debug("MTC0 DS %d\n", copr); |
3540 | emit_writeword(HOST_CCREG,&last_count); |
3541 | emit_movimm(0,HOST_CCREG); |
3542 | emit_storereg(CCREG,HOST_CCREG); |
cf95b4f0 |
3543 | emit_loadreg(dops[i].rs1,1); |
8062d65a |
3544 | emit_movimm(copr,0); |
2a014d73 |
3545 | emit_far_call(pcsx_mtc0_ds); |
cf95b4f0 |
3546 | emit_loadreg(dops[i].rs1,s); |
8062d65a |
3547 | return; |
3548 | } |
3549 | emit_movimm(start+i*4+4,HOST_TEMPREG); |
3550 | emit_writeword(HOST_TEMPREG,&pcaddr); |
3551 | emit_movimm(0,HOST_TEMPREG); |
3552 | emit_writeword(HOST_TEMPREG,&pending_exception); |
3553 | } |
de6dbc52 |
3554 | if( s != 1) |
3555 | emit_mov(s, 1); |
3556 | emit_movimm(copr, 0); |
2a014d73 |
3557 | emit_far_call(pcsx_mtc0); |
de6dbc52 |
3558 | if (copr == 12 || copr == 13) { |
d7546062 |
3559 | emit_readword(&psxRegs.cycle,HOST_CCREG); |
de6dbc52 |
3560 | emit_readword(&last_count,HOST_TEMPREG); |
8062d65a |
3561 | emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); |
de6dbc52 |
3562 | //emit_writeword(HOST_TEMPREG,&last_count); |
8062d65a |
3563 | assert(!is_delayslot); |
9b495f6e |
3564 | emit_readword(&pending_exception,HOST_TEMPREG); |
3565 | emit_test(HOST_TEMPREG,HOST_TEMPREG); |
d1e4ebd9 |
3566 | void *jaddr = out; |
3567 | emit_jeq(0); |
3568 | emit_readword(&pcaddr, 0); |
104df9d3 |
3569 | emit_far_call(ndrc_get_addr_ht); |
d1e4ebd9 |
3570 | emit_jmpreg(0); |
3571 | set_jump_target(jaddr, out); |
de6dbc52 |
3572 | emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG); |
3573 | if (cc != HOST_CCREG) |
3574 | emit_storereg(CCREG, HOST_CCREG); |
8062d65a |
3575 | } |
cf95b4f0 |
3576 | emit_loadreg(dops[i].rs1,s); |
8062d65a |
3577 | } |
8062d65a |
3578 | } |
3579 | |
277718fa |
3580 | static void rfe_assemble(int i, const struct regstat *i_regs) |
8062d65a |
3581 | { |
a5cd72d0 |
3582 | emit_readword(&psxRegs.CP0.n.SR, 0); |
3583 | emit_andimm(0, 0x3c, 1); |
3584 | emit_andimm(0, ~0xf, 0); |
3585 | emit_orrshr_imm(1, 2, 0); |
3586 | emit_writeword(0, &psxRegs.CP0.n.SR); |
8062d65a |
3587 | } |
3588 | |
e3c6bdb5 |
3589 | static int cop2_is_stalling_op(int i, int *cycles) |
3590 | { |
cf95b4f0 |
3591 | if (dops[i].opcode == 0x3a) { // SWC2 |
e3c6bdb5 |
3592 | *cycles = 0; |
3593 | return 1; |
3594 | } |
cf95b4f0 |
3595 | if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2 |
e3c6bdb5 |
3596 | *cycles = 0; |
3597 | return 1; |
3598 | } |
cf95b4f0 |
3599 | if (dops[i].itype == C2OP) { |
e3c6bdb5 |
3600 | *cycles = gte_cycletab[source[i] & 0x3f]; |
3601 | return 1; |
3602 | } |
3603 | // ... what about MTC2/CTC2/LWC2? |
3604 | return 0; |
3605 | } |
3606 | |
3607 | #if 0 |
3608 | static void log_gte_stall(int stall, u_int cycle) |
3609 | { |
3610 | if ((u_int)stall <= 44) |
3611 | printf("x stall %2d %u\n", stall, cycle + last_count); |
e3c6bdb5 |
3612 | } |
3613 | |
3614 | static void emit_log_gte_stall(int i, int stall, u_int reglist) |
3615 | { |
3616 | save_regs(reglist); |
3617 | if (stall > 0) |
3618 | emit_movimm(stall, 0); |
3619 | else |
3620 | emit_mov(HOST_TEMPREG, 0); |
277718fa |
3621 | emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1); |
e3c6bdb5 |
3622 | emit_far_call(log_gte_stall); |
3623 | restore_regs(reglist); |
3624 | } |
3625 | #endif |
3626 | |
32631e6a |
3627 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist) |
81dbbf4c |
3628 | { |
e3c6bdb5 |
3629 | int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed; |
3630 | int rtmp = reglist_find_free(reglist); |
3631 | |
32631e6a |
3632 | if (HACK_ENABLED(NDHACK_NO_STALLS)) |
81dbbf4c |
3633 | return; |
81dbbf4c |
3634 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { |
3635 | // happens occasionally... cc evicted? Don't bother then |
3636 | //printf("no cc %08x\n", start + i*4); |
3637 | return; |
3638 | } |
cf95b4f0 |
3639 | if (!dops[i].bt) { |
e3c6bdb5 |
3640 | for (j = i - 1; j >= 0; j--) { |
cf95b4f0 |
3641 | //if (dops[j].is_ds) break; |
3642 | if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) |
e3c6bdb5 |
3643 | break; |
277718fa |
3644 | if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj) |
2330734f |
3645 | break; |
e3c6bdb5 |
3646 | } |
32631e6a |
3647 | j = max(j, 0); |
e3c6bdb5 |
3648 | } |
277718fa |
3649 | cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj; |
e3c6bdb5 |
3650 | if (other_gte_op_cycles >= 0) |
3651 | stall = other_gte_op_cycles - cycles_passed; |
3652 | else if (cycles_passed >= 44) |
3653 | stall = 0; // can't stall |
3654 | if (stall == -MAXBLOCK && rtmp >= 0) { |
3655 | // unknown stall, do the expensive runtime check |
32631e6a |
3656 | assem_debug("; cop2_do_stall_check\n"); |
e3c6bdb5 |
3657 | #if 0 // too slow |
3658 | save_regs(reglist); |
3659 | emit_movimm(gte_cycletab[op], 0); |
277718fa |
3660 | emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1); |
e3c6bdb5 |
3661 | emit_far_call(call_gteStall); |
3662 | restore_regs(reglist); |
3663 | #else |
3664 | host_tempreg_acquire(); |
3665 | emit_readword(&psxRegs.gteBusyCycle, rtmp); |
277718fa |
3666 | emit_addimm(rtmp, -cinfo[i].ccadj, rtmp); |
e3c6bdb5 |
3667 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); |
3668 | emit_cmpimm(HOST_TEMPREG, 44); |
3669 | emit_cmovb_reg(rtmp, HOST_CCREG); |
3670 | //emit_log_gte_stall(i, 0, reglist); |
3671 | host_tempreg_release(); |
3672 | #endif |
3673 | } |
3674 | else if (stall > 0) { |
3675 | //emit_log_gte_stall(i, stall, reglist); |
3676 | emit_addimm(HOST_CCREG, stall, HOST_CCREG); |
3677 | } |
3678 | |
3679 | // save gteBusyCycle, if needed |
3680 | if (gte_cycletab[op] == 0) |
3681 | return; |
3682 | other_gte_op_cycles = -1; |
3683 | for (j = i + 1; j < slen; j++) { |
3684 | if (cop2_is_stalling_op(j, &other_gte_op_cycles)) |
3685 | break; |
fe807a8a |
3686 | if (dops[j].is_jump) { |
e3c6bdb5 |
3687 | // check ds |
3688 | if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) |
3689 | j++; |
3690 | break; |
3691 | } |
3692 | } |
3693 | if (other_gte_op_cycles >= 0) |
3694 | // will handle stall when assembling that op |
3695 | return; |
277718fa |
3696 | cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj; |
e3c6bdb5 |
3697 | if (cycles_passed >= 44) |
3698 | return; |
3699 | assem_debug("; save gteBusyCycle\n"); |
3700 | host_tempreg_acquire(); |
3701 | #if 0 |
3702 | emit_readword(&last_count, HOST_TEMPREG); |
3703 | emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); |
277718fa |
3704 | emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG); |
e3c6bdb5 |
3705 | emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); |
3706 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); |
3707 | #else |
277718fa |
3708 | emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG); |
e3c6bdb5 |
3709 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); |
3710 | #endif |
3711 | host_tempreg_release(); |
81dbbf4c |
3712 | } |
3713 | |
32631e6a |
3714 | static int is_mflohi(int i) |
3715 | { |
cf95b4f0 |
3716 | return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG)); |
32631e6a |
3717 | } |
3718 | |
3719 | static int check_multdiv(int i, int *cycles) |
3720 | { |
cf95b4f0 |
3721 | if (dops[i].itype != MULTDIV) |
32631e6a |
3722 | return 0; |
cf95b4f0 |
3723 | if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U) |
32631e6a |
3724 | *cycles = 11; // approx from 7 11 14 |
3725 | else |
3726 | *cycles = 37; |
3727 | return 1; |
3728 | } |
3729 | |
2330734f |
3730 | static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) |
32631e6a |
3731 | { |
3732 | int j, found = 0, c = 0; |
3733 | if (HACK_ENABLED(NDHACK_NO_STALLS)) |
3734 | return; |
3735 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { |
3736 | // happens occasionally... cc evicted? Don't bother then |
3737 | return; |
3738 | } |
3739 | for (j = i + 1; j < slen; j++) { |
cf95b4f0 |
3740 | if (dops[j].bt) |
32631e6a |
3741 | break; |
3742 | if ((found = is_mflohi(j))) |
3743 | break; |
fe807a8a |
3744 | if (dops[j].is_jump) { |
32631e6a |
3745 | // check ds |
3746 | if (j + 1 < slen && (found = is_mflohi(j + 1))) |
3747 | j++; |
3748 | break; |
3749 | } |
3750 | } |
3751 | if (found) |
3752 | // handle all in multdiv_do_stall() |
3753 | return; |
3754 | check_multdiv(i, &c); |
3755 | assert(c > 0); |
3756 | assem_debug("; muldiv prepare stall %d\n", c); |
3757 | host_tempreg_acquire(); |
2330734f |
3758 | emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); |
32631e6a |
3759 | emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); |
3760 | host_tempreg_release(); |
3761 | } |
3762 | |
3763 | static void multdiv_do_stall(int i, const struct regstat *i_regs) |
3764 | { |
3765 | int j, known_cycles = 0; |
3766 | u_int reglist = get_host_reglist(i_regs->regmap); |
9de8a0c3 |
3767 | int rtmp = get_reg_temp(i_regs->regmap); |
32631e6a |
3768 | if (rtmp < 0) |
3769 | rtmp = reglist_find_free(reglist); |
3770 | if (HACK_ENABLED(NDHACK_NO_STALLS)) |
3771 | return; |
3772 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) { |
3773 | // happens occasionally... cc evicted? Don't bother then |
3774 | //printf("no cc/rtmp %08x\n", start + i*4); |
3775 | return; |
3776 | } |
cf95b4f0 |
3777 | if (!dops[i].bt) { |
32631e6a |
3778 | for (j = i - 1; j >= 0; j--) { |
cf95b4f0 |
3779 | if (dops[j].is_ds) break; |
2330734f |
3780 | if (check_multdiv(j, &known_cycles)) |
32631e6a |
3781 | break; |
3782 | if (is_mflohi(j)) |
3783 | // already handled by this op |
3784 | return; |
277718fa |
3785 | if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)) |
2330734f |
3786 | break; |
32631e6a |
3787 | } |
3788 | j = max(j, 0); |
3789 | } |
3790 | if (known_cycles > 0) { |
277718fa |
3791 | known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj; |
32631e6a |
3792 | assem_debug("; muldiv stall resolved %d\n", known_cycles); |
3793 | if (known_cycles > 0) |
3794 | emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); |
3795 | return; |
3796 | } |
3797 | assem_debug("; muldiv stall unresolved\n"); |
3798 | host_tempreg_acquire(); |
3799 | emit_readword(&psxRegs.muldivBusyCycle, rtmp); |
277718fa |
3800 | emit_addimm(rtmp, -cinfo[i].ccadj, rtmp); |
32631e6a |
3801 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); |
3802 | emit_cmpimm(HOST_TEMPREG, 37); |
3803 | emit_cmovb_reg(rtmp, HOST_CCREG); |
3804 | //emit_log_gte_stall(i, 0, reglist); |
3805 | host_tempreg_release(); |
3806 | } |
3807 | |
8062d65a |
3808 | static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) |
3809 | { |
3810 | switch (copr) { |
3811 | case 1: |
3812 | case 3: |
3813 | case 5: |
3814 | case 8: |
3815 | case 9: |
3816 | case 10: |
3817 | case 11: |
3818 | emit_readword(®_cop2d[copr],tl); |
3819 | emit_signextend16(tl,tl); |
3820 | emit_writeword(tl,®_cop2d[copr]); // hmh |
3821 | break; |
3822 | case 7: |
3823 | case 16: |
3824 | case 17: |
3825 | case 18: |
3826 | case 19: |
3827 | emit_readword(®_cop2d[copr],tl); |
3828 | emit_andimm(tl,0xffff,tl); |
3829 | emit_writeword(tl,®_cop2d[copr]); |
3830 | break; |
3831 | case 15: |
3832 | emit_readword(®_cop2d[14],tl); // SXY2 |
3833 | emit_writeword(tl,®_cop2d[copr]); |
3834 | break; |
3835 | case 28: |
3836 | case 29: |
3968e69e |
3837 | c2op_mfc2_29_assemble(tl,temp); |
8062d65a |
3838 | break; |
3839 | default: |
3840 | emit_readword(®_cop2d[copr],tl); |
3841 | break; |
3842 | } |
3843 | } |
3844 | |
3845 | static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) |
3846 | { |
3847 | switch (copr) { |
3848 | case 15: |
3849 | emit_readword(®_cop2d[13],temp); // SXY1 |
3850 | emit_writeword(sl,®_cop2d[copr]); |
3851 | emit_writeword(temp,®_cop2d[12]); // SXY0 |
3852 | emit_readword(®_cop2d[14],temp); // SXY2 |
3853 | emit_writeword(sl,®_cop2d[14]); |
3854 | emit_writeword(temp,®_cop2d[13]); // SXY1 |
3855 | break; |
3856 | case 28: |
3857 | emit_andimm(sl,0x001f,temp); |
3858 | emit_shlimm(temp,7,temp); |
3859 | emit_writeword(temp,®_cop2d[9]); |
3860 | emit_andimm(sl,0x03e0,temp); |
3861 | emit_shlimm(temp,2,temp); |
3862 | emit_writeword(temp,®_cop2d[10]); |
3863 | emit_andimm(sl,0x7c00,temp); |
3864 | emit_shrimm(temp,3,temp); |
3865 | emit_writeword(temp,®_cop2d[11]); |
3866 | emit_writeword(sl,®_cop2d[28]); |
3867 | break; |
3868 | case 30: |
3968e69e |
3869 | emit_xorsar_imm(sl,sl,31,temp); |
be516ebe |
3870 | #if defined(HAVE_ARMV5) || defined(__aarch64__) |
8062d65a |
3871 | emit_clz(temp,temp); |
3872 | #else |
3873 | emit_movs(temp,HOST_TEMPREG); |
3874 | emit_movimm(0,temp); |
3875 | emit_jeq((int)out+4*4); |
3876 | emit_addpl_imm(temp,1,temp); |
3877 | emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG); |
3878 | emit_jns((int)out-2*4); |
3879 | #endif |
3880 | emit_writeword(sl,®_cop2d[30]); |
3881 | emit_writeword(temp,®_cop2d[31]); |
3882 | break; |
3883 | case 31: |
3884 | break; |
3885 | default: |
3886 | emit_writeword(sl,®_cop2d[copr]); |
3887 | break; |
3888 | } |
3889 | } |
3890 | |
2330734f |
3891 | static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) |
b9b61529 |
3892 | { |
3893 | int s,tl; |
3894 | int ar; |
3895 | int offset; |
1fd1aceb |
3896 | int memtarget=0,c=0; |
b14b6a8f |
3897 | void *jaddr2=NULL; |
3898 | enum stub_type type; |
37387d8b |
3899 | int offset_reg = -1; |
3900 | int fastio_reg_override = -1; |
81dbbf4c |
3901 | u_int reglist=get_host_reglist(i_regs->regmap); |
b9b61529 |
3902 | u_int copr=(source[i]>>16)&0x1f; |
cf95b4f0 |
3903 | s=get_reg(i_regs->regmap,dops[i].rs1); |
b9b61529 |
3904 | tl=get_reg(i_regs->regmap,FTEMP); |
277718fa |
3905 | offset=cinfo[i].imm; |
b9b61529 |
3906 | assert(tl>=0); |
b9b61529 |
3907 | |
b9b61529 |
3908 | if(i_regs->regmap[HOST_CCREG]==CCREG) |
3909 | reglist&=~(1<<HOST_CCREG); |
3910 | |
3911 | // get the address |
277718fa |
3912 | ar = cinfo[i].addr; |
3913 | assert(ar >= 0); |
cf95b4f0 |
3914 | if (dops[i].opcode==0x3a) { // SWC2 |
277718fa |
3915 | reglist |= 1<<ar; |
b9b61529 |
3916 | } |
1fd1aceb |
3917 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3918 | memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE); |
b9b61529 |
3919 | |
32631e6a |
3920 | cop2_do_stall_check(0, i, i_regs, reglist); |
3921 | |
cf95b4f0 |
3922 | if (dops[i].opcode==0x3a) { // SWC2 |
3968e69e |
3923 | cop2_get_dreg(copr,tl,-1); |
1fd1aceb |
3924 | type=STOREW_STUB; |
b9b61529 |
3925 | } |
1fd1aceb |
3926 | else |
b9b61529 |
3927 | type=LOADW_STUB; |
1fd1aceb |
3928 | |
3929 | if(c&&!memtarget) { |
b14b6a8f |
3930 | jaddr2=out; |
1fd1aceb |
3931 | emit_jmp(0); // inline_readstub/inline_writestub? |
b9b61529 |
3932 | } |
1fd1aceb |
3933 | else { |
3934 | if(!c) { |
37387d8b |
3935 | jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, |
277718fa |
3936 | &offset_reg, &fastio_reg_override, ccadj_); |
37387d8b |
3937 | } |
3938 | else if (ram_offset && memtarget) { |
3939 | offset_reg = get_ro_reg(i_regs, 0); |
3940 | } |
3941 | switch (dops[i].opcode) { |
3942 | case 0x32: { // LWC2 |
3943 | int a = ar; |
3944 | if (fastio_reg_override >= 0) |
3945 | a = fastio_reg_override; |
3946 | do_load_word(a, tl, offset_reg); |
3947 | break; |
1fd1aceb |
3948 | } |
37387d8b |
3949 | case 0x3a: { // SWC2 |
1fd1aceb |
3950 | #ifdef DESTRUCTIVE_SHIFT |
3951 | if(!offset&&!c&&s>=0) emit_mov(s,ar); |
3952 | #endif |
37387d8b |
3953 | int a = ar; |
3954 | if (fastio_reg_override >= 0) |
3955 | a = fastio_reg_override; |
3956 | do_store_word(a, 0, tl, offset_reg, 1); |
3957 | break; |
3958 | } |
3959 | default: |
3960 | assert(0); |
1fd1aceb |
3961 | } |
b9b61529 |
3962 | } |
37387d8b |
3963 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
d1e4ebd9 |
3964 | host_tempreg_release(); |
b9b61529 |
3965 | if(jaddr2) |
2330734f |
3966 | add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); |
cf95b4f0 |
3967 | if(dops[i].opcode==0x3a) // SWC2 |
9b495f6e |
3968 | do_store_smc_check(i, i_regs, reglist, ar); |
cf95b4f0 |
3969 | if (dops[i].opcode==0x32) { // LWC2 |
d1e4ebd9 |
3970 | host_tempreg_acquire(); |
b9b61529 |
3971 | cop2_put_dreg(copr,tl,HOST_TEMPREG); |
d1e4ebd9 |
3972 | host_tempreg_release(); |
b9b61529 |
3973 | } |
3974 | } |
3975 | |
81dbbf4c |
3976 | static void cop2_assemble(int i, const struct regstat *i_regs) |
8062d65a |
3977 | { |
81dbbf4c |
3978 | u_int copr = (source[i]>>11) & 0x1f; |
9de8a0c3 |
3979 | signed char temp = get_reg_temp(i_regs->regmap); |
81dbbf4c |
3980 | |
32631e6a |
3981 | if (!HACK_ENABLED(NDHACK_NO_STALLS)) { |
3982 | u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); |
cf95b4f0 |
3983 | if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2 |
3984 | signed char tl = get_reg(i_regs->regmap, dops[i].rt1); |
32631e6a |
3985 | reglist = reglist_exclude(reglist, tl, -1); |
81dbbf4c |
3986 | } |
32631e6a |
3987 | cop2_do_stall_check(0, i, i_regs, reglist); |
81dbbf4c |
3988 | } |
cf95b4f0 |
3989 | if (dops[i].opcode2==0) { // MFC2 |
a5cd72d0 |
3990 | signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
3991 | if(tl>=0&&dops[i].rt1!=0) |
8062d65a |
3992 | cop2_get_dreg(copr,tl,temp); |
3993 | } |
cf95b4f0 |
3994 | else if (dops[i].opcode2==4) { // MTC2 |
3995 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); |
8062d65a |
3996 | cop2_put_dreg(copr,sl,temp); |
3997 | } |
cf95b4f0 |
3998 | else if (dops[i].opcode2==2) // CFC2 |
8062d65a |
3999 | { |
a5cd72d0 |
4000 | signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
cf95b4f0 |
4001 | if(tl>=0&&dops[i].rt1!=0) |
8062d65a |
4002 | emit_readword(®_cop2c[copr],tl); |
4003 | } |
cf95b4f0 |
4004 | else if (dops[i].opcode2==6) // CTC2 |
8062d65a |
4005 | { |
cf95b4f0 |
4006 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); |
8062d65a |
4007 | switch(copr) { |
4008 | case 4: |
4009 | case 12: |
4010 | case 20: |
4011 | case 26: |
4012 | case 27: |
4013 | case 29: |
4014 | case 30: |
4015 | emit_signextend16(sl,temp); |
4016 | break; |
4017 | case 31: |
3968e69e |
4018 | c2op_ctc2_31_assemble(sl,temp); |
8062d65a |
4019 | break; |
4020 | default: |
4021 | temp=sl; |
4022 | break; |
4023 | } |
4024 | emit_writeword(temp,®_cop2c[copr]); |
4025 | assert(sl>=0); |
4026 | } |
4027 | } |
4028 | |
3968e69e |
4029 | static void do_unalignedwritestub(int n) |
4030 | { |
4031 | assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4); |
4032 | literal_pool(256); |
4033 | set_jump_target(stubs[n].addr, out); |
4034 | |
4035 | int i=stubs[n].a; |
4036 | struct regstat *i_regs=(struct regstat *)stubs[n].c; |
4037 | int addr=stubs[n].b; |
4038 | u_int reglist=stubs[n].e; |
4039 | signed char *i_regmap=i_regs->regmap; |
4040 | int temp2=get_reg(i_regmap,FTEMP); |
4041 | int rt; |
cf95b4f0 |
4042 | rt=get_reg(i_regmap,dops[i].rs2); |
3968e69e |
4043 | assert(rt>=0); |
4044 | assert(addr>=0); |
cf95b4f0 |
4045 | assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented |
3968e69e |
4046 | reglist|=(1<<addr); |
4047 | reglist&=~(1<<temp2); |
4048 | |
3968e69e |
4049 | // don't bother with it and call write handler |
4050 | save_regs(reglist); |
4051 | pass_args(addr,rt); |
4052 | int cc=get_reg(i_regmap,CCREG); |
4053 | if(cc<0) |
4054 | emit_loadreg(CCREG,2); |
2330734f |
4055 | emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); |
de6dbc52 |
4056 | emit_movimm(start + i*4,3); |
4057 | emit_writeword(3,&psxRegs.pc); |
cf95b4f0 |
4058 | emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); |
2330734f |
4059 | emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); |
3968e69e |
4060 | if(cc<0) |
4061 | emit_storereg(CCREG,2); |
4062 | restore_regs(reglist); |
4063 | emit_jmp(stubs[n].retaddr); // return address |
3968e69e |
4064 | } |
4065 | |
a5cd72d0 |
4066 | static void do_overflowstub(int n) |
4067 | { |
4068 | assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4); |
4069 | literal_pool(24); |
4070 | int i = stubs[n].a; |
4071 | struct regstat *i_regs = (struct regstat *)stubs[n].c; |
4072 | int ccadj = stubs[n].d; |
4073 | set_jump_target(stubs[n].addr, out); |
4074 | wb_dirtys(regs[i].regmap, regs[i].dirty); |
4075 | exception_assemble(i, i_regs, ccadj); |
4076 | } |
4077 | |
277718fa |
4078 | static void do_alignmentstub(int n) |
4079 | { |
4080 | assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4); |
4081 | literal_pool(24); |
4082 | int i = stubs[n].a; |
4083 | struct regstat *i_regs = (struct regstat *)stubs[n].c; |
4084 | int ccadj = stubs[n].d; |
4085 | int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2 |
4086 | int cause = (dops[i].opcode & 3) << 28; |
4087 | cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2); |
4088 | set_jump_target(stubs[n].addr, out); |
4089 | wb_dirtys(regs[i].regmap, regs[i].dirty); |
4090 | if (stubs[n].b != 1) |
4091 | emit_mov(stubs[n].b, 1); // faulting address |
4092 | emit_movimm(cause, 0); |
4093 | exception_assemble(i, i_regs, ccadj); |
4094 | } |
4095 | |
57871462 |
4096 | #ifndef multdiv_assemble |
4097 | void multdiv_assemble(int i,struct regstat *i_regs) |
4098 | { |
4099 | printf("Need multdiv_assemble for this architecture.\n"); |
7c3a5182 |
4100 | abort(); |
57871462 |
4101 | } |
4102 | #endif |
4103 | |
2330734f |
4104 | static void mov_assemble(int i, const struct regstat *i_regs) |
57871462 |
4105 | { |
cf95b4f0 |
4106 | //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO |
4107 | //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO |
4108 | if(dops[i].rt1) { |
7c3a5182 |
4109 | signed char sl,tl; |
a5cd72d0 |
4110 | tl=get_reg_w(i_regs->regmap, dops[i].rt1); |
57871462 |
4111 | //assert(tl>=0); |
4112 | if(tl>=0) { |
cf95b4f0 |
4113 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 |
4114 | if(sl>=0) emit_mov(sl,tl); |
cf95b4f0 |
4115 | else emit_loadreg(dops[i].rs1,tl); |
57871462 |
4116 | } |
4117 | } |
cf95b4f0 |
4118 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO |
32631e6a |
4119 | multdiv_do_stall(i, i_regs); |
57871462 |
4120 | } |
4121 | |
3968e69e |
4122 | // call interpreter, exception handler, things that change pc/regs/cycles ... |
2330734f |
4123 | static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) |
57871462 |
4124 | { |
4125 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
4126 | assert(ccreg==HOST_CCREG); |
4127 | assert(!is_delayslot); |
581335b0 |
4128 | (void)ccreg; |
3968e69e |
4129 | |
4130 | emit_movimm(pc,3); // Get PC |
4131 | emit_readword(&last_count,2); |
4132 | emit_writeword(3,&psxRegs.pc); |
2330734f |
4133 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); |
3968e69e |
4134 | emit_add(2,HOST_CCREG,2); |
4135 | emit_writeword(2,&psxRegs.cycle); |
bc7c5acb |
4136 | emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0); |
2a014d73 |
4137 | emit_far_call(func); |
4138 | emit_far_jump(jump_to_new_pc); |
3968e69e |
4139 | } |
4140 | |
a5cd72d0 |
4141 | static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_) |
3968e69e |
4142 | { |
d1150cd6 |
4143 | // 'break' tends to be littered around to catch things like |
4144 | // division by 0 and is almost never executed, so don't emit much code here |
a5cd72d0 |
4145 | void *func; |
4146 | if (dops[i].itype == ALU || dops[i].itype == IMM16) |
4147 | func = is_delayslot ? jump_overflow_ds : jump_overflow; |
277718fa |
4148 | else if (dops[i].itype == LOAD || dops[i].itype == STORE) |
4149 | func = is_delayslot ? jump_addrerror_ds : jump_addrerror; |
a5cd72d0 |
4150 | else if (dops[i].opcode2 == 0x0C) |
4151 | func = is_delayslot ? jump_syscall_ds : jump_syscall; |
4152 | else |
4153 | func = is_delayslot ? jump_break_ds : jump_break; |
277718fa |
4154 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted |
4155 | emit_loadreg(CCREG, HOST_CCREG); |
d1150cd6 |
4156 | emit_movimm(start + i*4, 2); // pc |
4157 | emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG); |
4158 | emit_far_jump(func); |
7139f3c8 |
4159 | } |
4160 | |
bc7c5acb |
4161 | static void hlecall_bad() |
4162 | { |
a5cd72d0 |
4163 | assert(0); |
bc7c5acb |
4164 | } |
4165 | |
2330734f |
4166 | static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
7139f3c8 |
4167 | { |
bc7c5acb |
4168 | void *hlefunc = hlecall_bad; |
dd79da89 |
4169 | uint32_t hleCode = source[i] & 0x03ffffff; |
3968e69e |
4170 | if (hleCode < ARRAY_SIZE(psxHLEt)) |
4171 | hlefunc = psxHLEt[hleCode]; |
4172 | |
2330734f |
4173 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); |
57871462 |
4174 | } |
4175 | |
2330734f |
4176 | static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
1e973cb0 |
4177 | { |
2330734f |
4178 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); |
1e973cb0 |
4179 | } |
4180 | |
8062d65a |
4181 | static void speculate_mov(int rs,int rt) |
4182 | { |
4183 | if(rt!=0) { |
4184 | smrv_strong_next|=1<<rt; |
4185 | smrv[rt]=smrv[rs]; |
4186 | } |
4187 | } |
4188 | |
4189 | static void speculate_mov_weak(int rs,int rt) |
4190 | { |
4191 | if(rt!=0) { |
4192 | smrv_weak_next|=1<<rt; |
4193 | smrv[rt]=smrv[rs]; |
4194 | } |
4195 | } |
4196 | |
4197 | static void speculate_register_values(int i) |
4198 | { |
4199 | if(i==0) { |
4200 | memcpy(smrv,psxRegs.GPR.r,sizeof(smrv)); |
4201 | // gp,sp are likely to stay the same throughout the block |
4202 | smrv_strong_next=(1<<28)|(1<<29)|(1<<30); |
4203 | smrv_weak_next=~smrv_strong_next; |
4204 | //printf(" llr %08x\n", smrv[4]); |
4205 | } |
4206 | smrv_strong=smrv_strong_next; |
4207 | smrv_weak=smrv_weak_next; |
cf95b4f0 |
4208 | switch(dops[i].itype) { |
8062d65a |
4209 | case ALU: |
cf95b4f0 |
4210 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); |
4211 | else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1); |
4212 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); |
4213 | else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1); |
8062d65a |
4214 | else { |
cf95b4f0 |
4215 | smrv_strong_next&=~(1<<dops[i].rt1); |
4216 | smrv_weak_next&=~(1<<dops[i].rt1); |
8062d65a |
4217 | } |
4218 | break; |
4219 | case SHIFTIMM: |
cf95b4f0 |
4220 | smrv_strong_next&=~(1<<dops[i].rt1); |
4221 | smrv_weak_next&=~(1<<dops[i].rt1); |
8062d65a |
4222 | // fallthrough |
4223 | case IMM16: |
cf95b4f0 |
4224 | if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) { |
de6dbc52 |
4225 | int hr = get_reg_w(regs[i].regmap, dops[i].rt1); |
4226 | u_int value; |
8062d65a |
4227 | if(hr>=0) { |
4228 | if(get_final_value(hr,i,&value)) |
cf95b4f0 |
4229 | smrv[dops[i].rt1]=value; |
4230 | else smrv[dops[i].rt1]=constmap[i][hr]; |
4231 | smrv_strong_next|=1<<dops[i].rt1; |
8062d65a |
4232 | } |
4233 | } |
4234 | else { |
cf95b4f0 |
4235 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); |
4236 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); |
8062d65a |
4237 | } |
4238 | break; |
4239 | case LOAD: |
cf95b4f0 |
4240 | if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) { |
8062d65a |
4241 | // special case for BIOS |
cf95b4f0 |
4242 | smrv[dops[i].rt1]=0xa0000000; |
4243 | smrv_strong_next|=1<<dops[i].rt1; |
8062d65a |
4244 | break; |
4245 | } |
4246 | // fallthrough |
4247 | case SHIFT: |
4248 | case LOADLR: |
4249 | case MOV: |
cf95b4f0 |
4250 | smrv_strong_next&=~(1<<dops[i].rt1); |
4251 | smrv_weak_next&=~(1<<dops[i].rt1); |
8062d65a |
4252 | break; |
4253 | case COP0: |
4254 | case COP2: |
cf95b4f0 |
4255 | if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC |
4256 | smrv_strong_next&=~(1<<dops[i].rt1); |
4257 | smrv_weak_next&=~(1<<dops[i].rt1); |
8062d65a |
4258 | } |
4259 | break; |
4260 | case C2LS: |
cf95b4f0 |
4261 | if (dops[i].opcode==0x32) { // LWC2 |
4262 | smrv_strong_next&=~(1<<dops[i].rt1); |
4263 | smrv_weak_next&=~(1<<dops[i].rt1); |
8062d65a |
4264 | } |
4265 | break; |
4266 | } |
4267 | #if 0 |
4268 | int r=4; |
4269 | printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4, |
4270 | ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst); |
4271 | #endif |
4272 | } |
4273 | |
2330734f |
4274 | static void ujump_assemble(int i, const struct regstat *i_regs); |
4275 | static void rjump_assemble(int i, const struct regstat *i_regs); |
4276 | static void cjump_assemble(int i, const struct regstat *i_regs); |
4277 | static void sjump_assemble(int i, const struct regstat *i_regs); |
2330734f |
4278 | |
4279 | static int assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 |
4280 | { |
2330734f |
4281 | int ds = 0; |
4282 | switch (dops[i].itype) { |
57871462 |
4283 | case ALU: |
a5cd72d0 |
4284 | alu_assemble(i, i_regs, ccadj_); |
2330734f |
4285 | break; |
57871462 |
4286 | case IMM16: |
a5cd72d0 |
4287 | imm16_assemble(i, i_regs, ccadj_); |
2330734f |
4288 | break; |
57871462 |
4289 | case SHIFT: |
2330734f |
4290 | shift_assemble(i, i_regs); |
4291 | break; |
57871462 |
4292 | case SHIFTIMM: |
2330734f |
4293 | shiftimm_assemble(i, i_regs); |
4294 | break; |
57871462 |
4295 | case LOAD: |
2330734f |
4296 | load_assemble(i, i_regs, ccadj_); |
4297 | break; |
57871462 |
4298 | case LOADLR: |
2330734f |
4299 | loadlr_assemble(i, i_regs, ccadj_); |
4300 | break; |
57871462 |
4301 | case STORE: |
2330734f |
4302 | store_assemble(i, i_regs, ccadj_); |
4303 | break; |
57871462 |
4304 | case STORELR: |
2330734f |
4305 | storelr_assemble(i, i_regs, ccadj_); |
4306 | break; |
57871462 |
4307 | case COP0: |
2330734f |
4308 | cop0_assemble(i, i_regs, ccadj_); |
4309 | break; |
a5cd72d0 |
4310 | case RFE: |
277718fa |
4311 | rfe_assemble(i, i_regs); |
2330734f |
4312 | break; |
b9b61529 |
4313 | case COP2: |
2330734f |
4314 | cop2_assemble(i, i_regs); |
4315 | break; |
b9b61529 |
4316 | case C2LS: |
2330734f |
4317 | c2ls_assemble(i, i_regs, ccadj_); |
4318 | break; |
b9b61529 |
4319 | case C2OP: |
2330734f |
4320 | c2op_assemble(i, i_regs); |
4321 | break; |
57871462 |
4322 | case MULTDIV: |
2330734f |
4323 | multdiv_assemble(i, i_regs); |
4324 | multdiv_prepare_stall(i, i_regs, ccadj_); |
32631e6a |
4325 | break; |
57871462 |
4326 | case MOV: |
2330734f |
4327 | mov_assemble(i, i_regs); |
4328 | break; |
4329 | case SYSCALL: |
a5cd72d0 |
4330 | exception_assemble(i, i_regs, ccadj_); |
2330734f |
4331 | break; |
4332 | case HLECALL: |
4333 | hlecall_assemble(i, i_regs, ccadj_); |
4334 | break; |
4335 | case INTCALL: |
4336 | intcall_assemble(i, i_regs, ccadj_); |
4337 | break; |
4338 | case UJUMP: |
4339 | ujump_assemble(i, i_regs); |
4340 | ds = 1; |
4341 | break; |
4342 | case RJUMP: |
4343 | rjump_assemble(i, i_regs); |
4344 | ds = 1; |
4345 | break; |
4346 | case CJUMP: |
4347 | cjump_assemble(i, i_regs); |
4348 | ds = 1; |
4349 | break; |
4350 | case SJUMP: |
4351 | sjump_assemble(i, i_regs); |
4352 | ds = 1; |
4353 | break; |
24058131 |
4354 | case NOP: |
2330734f |
4355 | case OTHER: |
2330734f |
4356 | // not handled, just skip |
4357 | break; |
4358 | default: |
4359 | assert(0); |
4360 | } |
4361 | return ds; |
4362 | } |
4363 | |
4364 | static void ds_assemble(int i, const struct regstat *i_regs) |
4365 | { |
4366 | speculate_register_values(i); |
4367 | is_delayslot = 1; |
4368 | switch (dops[i].itype) { |
57871462 |
4369 | case SYSCALL: |
7139f3c8 |
4370 | case HLECALL: |
1e973cb0 |
4371 | case INTCALL: |
57871462 |
4372 | case UJUMP: |
4373 | case RJUMP: |
4374 | case CJUMP: |
4375 | case SJUMP: |
c43b5311 |
4376 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
2330734f |
4377 | break; |
4378 | default: |
277718fa |
4379 | assemble(i, i_regs, cinfo[i].ccadj); |
57871462 |
4380 | } |
2330734f |
4381 | is_delayslot = 0; |
57871462 |
4382 | } |
4383 | |
4384 | // Is the branch target a valid internal jump? |
ad49de89 |
4385 | static int internal_branch(int addr) |
57871462 |
4386 | { |
4387 | if(addr&1) return 0; // Indirect (register) jump |
4388 | if(addr>=start && addr<start+slen*4-4) |
4389 | { |
71e490c5 |
4390 | return 1; |
57871462 |
4391 | } |
4392 | return 0; |
4393 | } |
4394 | |
ad49de89 |
4395 | static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u) |
57871462 |
4396 | { |
4397 | int hr; |
4398 | for(hr=0;hr<HOST_REGS;hr++) { |
4399 | if(hr!=EXCLUDE_REG) { |
4400 | if(pre[hr]!=entry[hr]) { |
4401 | if(pre[hr]>=0) { |
4402 | if((dirty>>hr)&1) { |
4403 | if(get_reg(entry,pre[hr])<0) { |
00fa9369 |
4404 | assert(pre[hr]<64); |
4405 | if(!((u>>pre[hr])&1)) |
4406 | emit_storereg(pre[hr],hr); |
57871462 |
4407 | } |
4408 | } |
4409 | } |
4410 | } |
4411 | } |
4412 | } |
4413 | // Move from one register to another (no writeback) |
4414 | for(hr=0;hr<HOST_REGS;hr++) { |
4415 | if(hr!=EXCLUDE_REG) { |
4416 | if(pre[hr]!=entry[hr]) { |
9de8a0c3 |
4417 | if(pre[hr]>=0&&pre[hr]<TEMPREG) { |
57871462 |
4418 | int nr; |
4419 | if((nr=get_reg(entry,pre[hr]))>=0) { |
4420 | emit_mov(hr,nr); |
4421 | } |
4422 | } |
4423 | } |
4424 | } |
4425 | } |
4426 | } |
57871462 |
4427 | |
4428 | // Load the specified registers |
4429 | // This only loads the registers given as arguments because |
4430 | // we don't want to load things that will be overwritten |
53358c1d |
4431 | static inline void load_reg(signed char entry[], signed char regmap[], int rs) |
57871462 |
4432 | { |
53358c1d |
4433 | int hr = get_reg(regmap, rs); |
4434 | if (hr >= 0 && entry[hr] != regmap[hr]) |
4435 | emit_loadreg(regmap[hr], hr); |
4436 | } |
4437 | |
4438 | static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2) |
4439 | { |
4440 | load_reg(entry, regmap, rs1); |
4441 | if (rs1 != rs2) |
4442 | load_reg(entry, regmap, rs2); |
57871462 |
4443 | } |
4444 | |
4445 | // Load registers prior to the start of a loop |
4446 | // so that they are not loaded within the loop |
4447 | static void loop_preload(signed char pre[],signed char entry[]) |
4448 | { |
4449 | int hr; |
53358c1d |
4450 | for (hr = 0; hr < HOST_REGS; hr++) { |
4451 | int r = entry[hr]; |
4452 | if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) { |
4453 | assem_debug("loop preload:\n"); |
4454 | if (r < TEMPREG) |
4455 | emit_loadreg(r, hr); |
57871462 |
4456 | } |
4457 | } |
4458 | } |
4459 | |
4460 | // Generate address for load/store instruction |
277718fa |
4461 | // goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads |
4462 | // AGEN is assigned by pass5b_preallocate2 |
4149788d |
4463 | static void address_generation(int i, const struct regstat *i_regs, signed char entry[]) |
57871462 |
4464 | { |
37387d8b |
4465 | if (dops[i].is_load || dops[i].is_store) { |
277718fa |
4466 | int ra = -1; |
4467 | int agr = AGEN1 + (i&1); |
cf95b4f0 |
4468 | if(dops[i].itype==LOAD) { |
277718fa |
4469 | if (!dops[i].may_except) |
4470 | ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen |
4471 | if (ra < 0) |
4472 | ra = get_reg_temp(i_regs->regmap); |
57871462 |
4473 | } |
cf95b4f0 |
4474 | if(dops[i].itype==LOADLR) { |
57871462 |
4475 | ra=get_reg(i_regs->regmap,FTEMP); |
4476 | } |
cf95b4f0 |
4477 | if(dops[i].itype==STORE||dops[i].itype==STORELR) { |
57871462 |
4478 | ra=get_reg(i_regs->regmap,agr); |
9de8a0c3 |
4479 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 |
4480 | } |
37387d8b |
4481 | if(dops[i].itype==C2LS) { |
277718fa |
4482 | if (dops[i].opcode == 0x32) // LWC2 |
57871462 |
4483 | ra=get_reg(i_regs->regmap,FTEMP); |
277718fa |
4484 | else { // SWC2 |
57871462 |
4485 | ra=get_reg(i_regs->regmap,agr); |
9de8a0c3 |
4486 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 |
4487 | } |
4488 | } |
277718fa |
4489 | int rs = get_reg(i_regs->regmap, dops[i].rs1); |
4490 | //if(ra>=0) |
4491 | { |
4492 | int offset = cinfo[i].imm; |
4493 | int add_offset = offset != 0; |
57871462 |
4494 | int c=(i_regs->wasconst>>rs)&1; |
cf95b4f0 |
4495 | if(dops[i].rs1==0) { |
57871462 |
4496 | // Using r0 as a base address |
277718fa |
4497 | assert(ra >= 0); |
57871462 |
4498 | if(!entry||entry[ra]!=agr) { |
cf95b4f0 |
4499 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 |
4500 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
57871462 |
4501 | }else{ |
4502 | emit_movimm(offset,ra); |
4503 | } |
4504 | } // else did it in the previous cycle |
277718fa |
4505 | cinfo[i].addr = ra; |
4506 | add_offset = 0; |
4507 | } |
4508 | else if (rs < 0) { |
4509 | assert(ra >= 0); |
4510 | if (!entry || entry[ra] != dops[i].rs1) |
4511 | emit_loadreg(dops[i].rs1, ra); |
4512 | cinfo[i].addr = ra; |
cf95b4f0 |
4513 | //if(!entry||entry[ra]!=dops[i].rs1) |
57871462 |
4514 | // printf("poor load scheduling!\n"); |
4515 | } |
4516 | else if(c) { |
cf95b4f0 |
4517 | if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) { |
277718fa |
4518 | assert(ra >= 0); |
57871462 |
4519 | if(!entry||entry[ra]!=agr) { |
cf95b4f0 |
4520 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 |
4521 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
57871462 |
4522 | }else{ |
57871462 |
4523 | emit_movimm(constmap[i][rs]+offset,ra); |
8575a877 |
4524 | regs[i].loadedconst|=1<<ra; |
57871462 |
4525 | } |
4526 | } // else did it in the previous cycle |
277718fa |
4527 | cinfo[i].addr = ra; |
4528 | } |
4529 | else // else load_consts already did it |
4530 | cinfo[i].addr = rs; |
4531 | add_offset = 0; |
57871462 |
4532 | } |
277718fa |
4533 | else if (dops[i].itype == STORELR) { // overwrites addr |
4534 | assert(ra >= 0); |
4535 | assert(rs != ra); |
4536 | emit_mov(rs, ra); |
4537 | cinfo[i].addr = ra; |
4538 | } |
4539 | else |
4540 | cinfo[i].addr = rs; |
4541 | if (add_offset) { |
4542 | assert(ra >= 0); |
57871462 |
4543 | if(rs>=0) { |
4544 | emit_addimm(rs,offset,ra); |
4545 | }else{ |
4546 | emit_addimm(ra,offset,ra); |
4547 | } |
277718fa |
4548 | cinfo[i].addr = ra; |
57871462 |
4549 | } |
4550 | } |
277718fa |
4551 | assert(cinfo[i].addr >= 0); |
57871462 |
4552 | } |
4553 | // Preload constants for next instruction |
37387d8b |
4554 | if (dops[i+1].is_load || dops[i+1].is_store) { |
57871462 |
4555 | int agr,ra; |
57871462 |
4556 | // Actual address |
4557 | agr=AGEN1+((i+1)&1); |
4558 | ra=get_reg(i_regs->regmap,agr); |
4559 | if(ra>=0) { |
cf95b4f0 |
4560 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
277718fa |
4561 | int offset=cinfo[i+1].imm; |
57871462 |
4562 | int c=(regs[i+1].wasconst>>rs)&1; |
cf95b4f0 |
4563 | if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) { |
4564 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { |
57871462 |
4565 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
cf95b4f0 |
4566 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 |
4567 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4568 | }else{ |
57871462 |
4569 | emit_movimm(constmap[i+1][rs]+offset,ra); |
8575a877 |
4570 | regs[i+1].loadedconst|=1<<ra; |
57871462 |
4571 | } |
4572 | } |
cf95b4f0 |
4573 | else if(dops[i+1].rs1==0) { |
57871462 |
4574 | // Using r0 as a base address |
cf95b4f0 |
4575 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { |
57871462 |
4576 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
cf95b4f0 |
4577 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 |
4578 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4579 | }else{ |
4580 | emit_movimm(offset,ra); |
4581 | } |
4582 | } |
4583 | } |
4584 | } |
4585 | } |
4586 | |
de6dbc52 |
4587 | static int get_final_value(int hr, int i, u_int *value) |
57871462 |
4588 | { |
4589 | int reg=regs[i].regmap[hr]; |
4590 | while(i<slen-1) { |
4591 | if(regs[i+1].regmap[hr]!=reg) break; |
4592 | if(!((regs[i+1].isconst>>hr)&1)) break; |
cf95b4f0 |
4593 | if(dops[i+1].bt) break; |
57871462 |
4594 | i++; |
4595 | } |
4596 | if(i<slen-1) { |
fe807a8a |
4597 | if (dops[i].is_jump) { |
57871462 |
4598 | *value=constmap[i][hr]; |
4599 | return 1; |
4600 | } |
cf95b4f0 |
4601 | if(!dops[i+1].bt) { |
fe807a8a |
4602 | if (dops[i+1].is_jump) { |
57871462 |
4603 | // Load in delay slot, out-of-order execution |
cf95b4f0 |
4604 | if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1)) |
57871462 |
4605 | { |
57871462 |
4606 | // Precompute load address |
277718fa |
4607 | *value=constmap[i][hr]+cinfo[i+2].imm; |
57871462 |
4608 | return 1; |
4609 | } |
4610 | } |
cf95b4f0 |
4611 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg) |
57871462 |
4612 | { |
57871462 |
4613 | // Precompute load address |
277718fa |
4614 | *value=constmap[i][hr]+cinfo[i+1].imm; |
4615 | //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm); |
57871462 |
4616 | return 1; |
4617 | } |
4618 | } |
4619 | } |
4620 | *value=constmap[i][hr]; |
643aeae3 |
4621 | //printf("c=%lx\n",(long)constmap[i][hr]); |
57871462 |
4622 | if(i==slen-1) return 1; |
00fa9369 |
4623 | assert(reg < 64); |
4624 | return !((unneeded_reg[i+1]>>reg)&1); |
57871462 |
4625 | } |
4626 | |
4627 | // Load registers with known constants |
ad49de89 |
4628 | static void load_consts(signed char pre[],signed char regmap[],int i) |
57871462 |
4629 | { |
8575a877 |
4630 | int hr,hr2; |
4631 | // propagate loaded constant flags |
cf95b4f0 |
4632 | if(i==0||dops[i].bt) |
8575a877 |
4633 | regs[i].loadedconst=0; |
4634 | else { |
4635 | for(hr=0;hr<HOST_REGS;hr++) { |
4636 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr] |
4637 | &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1)) |
4638 | { |
4639 | regs[i].loadedconst|=1<<hr; |
4640 | } |
4641 | } |
4642 | } |
57871462 |
4643 | // Load 32-bit regs |
4644 | for(hr=0;hr<HOST_REGS;hr++) { |
4645 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { |
4646 | //if(entry[hr]!=regmap[hr]) { |
8575a877 |
4647 | if(!((regs[i].loadedconst>>hr)&1)) { |
ad49de89 |
4648 | assert(regmap[hr]<64); |
4649 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { |
de6dbc52 |
4650 | u_int value, similar=0; |
57871462 |
4651 | if(get_final_value(hr,i,&value)) { |
8575a877 |
4652 | // see if some other register has similar value |
4653 | for(hr2=0;hr2<HOST_REGS;hr2++) { |
4654 | if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) { |
4655 | if(is_similar_value(value,constmap[i][hr2])) { |
4656 | similar=1; |
4657 | break; |
4658 | } |
4659 | } |
4660 | } |
4661 | if(similar) { |
de6dbc52 |
4662 | u_int value2; |
8575a877 |
4663 | if(get_final_value(hr2,i,&value2)) // is this needed? |
4664 | emit_movimm_from(value2,hr2,value,hr); |
4665 | else |
4666 | emit_movimm(value,hr); |
4667 | } |
4668 | else if(value==0) { |
57871462 |
4669 | emit_zeroreg(hr); |
4670 | } |
4671 | else { |
4672 | emit_movimm(value,hr); |
4673 | } |
4674 | } |
8575a877 |
4675 | regs[i].loadedconst|=1<<hr; |
57871462 |
4676 | } |
4677 | } |
4678 | } |
4679 | } |
57871462 |
4680 | } |
ad49de89 |
4681 | |
2330734f |
4682 | static void load_all_consts(const signed char regmap[], u_int dirty, int i) |
57871462 |
4683 | { |
4684 | int hr; |
4685 | // Load 32-bit regs |
4686 | for(hr=0;hr<HOST_REGS;hr++) { |
4687 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { |
ad49de89 |
4688 | assert(regmap[hr] < 64); |
4689 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { |
57871462 |
4690 | int value=constmap[i][hr]; |
4691 | if(value==0) { |
4692 | emit_zeroreg(hr); |
4693 | } |
4694 | else { |
4695 | emit_movimm(value,hr); |
4696 | } |
4697 | } |
4698 | } |
4699 | } |
57871462 |
4700 | } |
4701 | |
4702 | // Write out all dirty registers (except cycle count) |
2330734f |
4703 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty) |
57871462 |
4704 | { |
4705 | int hr; |
4706 | for(hr=0;hr<HOST_REGS;hr++) { |
4707 | if(hr!=EXCLUDE_REG) { |
4708 | if(i_regmap[hr]>0) { |
4709 | if(i_regmap[hr]!=CCREG) { |
4710 | if((i_dirty>>hr)&1) { |
00fa9369 |
4711 | assert(i_regmap[hr]<64); |
4712 | emit_storereg(i_regmap[hr],hr); |
57871462 |
4713 | } |
4714 | } |
4715 | } |
4716 | } |
4717 | } |
4718 | } |
ad49de89 |
4719 | |
57871462 |
4720 | // Write out dirty registers that we need to reload (pair with load_needed_regs) |
4721 | // This writes the registers not written by store_regs_bt |
2330734f |
4722 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr) |
57871462 |
4723 | { |
4724 | int hr; |
4725 | int t=(addr-start)>>2; |
4726 | for(hr=0;hr<HOST_REGS;hr++) { |
4727 | if(hr!=EXCLUDE_REG) { |
4728 | if(i_regmap[hr]>0) { |
4729 | if(i_regmap[hr]!=CCREG) { |
ad49de89 |
4730 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) { |
57871462 |
4731 | if((i_dirty>>hr)&1) { |
00fa9369 |
4732 | assert(i_regmap[hr]<64); |
4733 | emit_storereg(i_regmap[hr],hr); |
57871462 |
4734 | } |
4735 | } |
4736 | } |
4737 | } |
4738 | } |
4739 | } |
4740 | } |
4741 | |
4742 | // Load all registers (except cycle count) |
2330734f |
4743 | static void load_all_regs(const signed char i_regmap[]) |
57871462 |
4744 | { |
4745 | int hr; |
4746 | for(hr=0;hr<HOST_REGS;hr++) { |
4747 | if(hr!=EXCLUDE_REG) { |
4748 | if(i_regmap[hr]==0) { |
4749 | emit_zeroreg(hr); |
4750 | } |
4751 | else |
9de8a0c3 |
4752 | if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 |
4753 | { |
4754 | emit_loadreg(i_regmap[hr],hr); |
4755 | } |
4756 | } |
4757 | } |
4758 | } |
4759 | |
4760 | // Load all current registers also needed by next instruction |
2330734f |
4761 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]) |
57871462 |
4762 | { |
4763 | int hr; |
4764 | for(hr=0;hr<HOST_REGS;hr++) { |
4765 | if(hr!=EXCLUDE_REG) { |
4766 | if(get_reg(next_regmap,i_regmap[hr])>=0) { |
4767 | if(i_regmap[hr]==0) { |
4768 | emit_zeroreg(hr); |
4769 | } |
4770 | else |
9de8a0c3 |
4771 | if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 |
4772 | { |
4773 | emit_loadreg(i_regmap[hr],hr); |
4774 | } |
4775 | } |
4776 | } |
4777 | } |
4778 | } |
4779 | |
4780 | // Load all regs, storing cycle count if necessary |
2330734f |
4781 | static void load_regs_entry(int t) |
57871462 |
4782 | { |
4783 | int hr; |
cf95b4f0 |
4784 | if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG); |
277718fa |
4785 | else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG); |
57871462 |
4786 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4787 | emit_storereg(CCREG,HOST_CCREG); |
4788 | } |
4789 | // Load 32-bit regs |
4790 | for(hr=0;hr<HOST_REGS;hr++) { |
ea3d2e6e |
4791 | if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
57871462 |
4792 | if(regs[t].regmap_entry[hr]==0) { |
4793 | emit_zeroreg(hr); |
4794 | } |
4795 | else if(regs[t].regmap_entry[hr]!=CCREG) |
4796 | { |
4797 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4798 | } |
4799 | } |
4800 | } |
57871462 |
4801 | } |
4802 | |
4803 | // Store dirty registers prior to branch |
4149788d |
4804 | static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 |
4805 | { |
ad49de89 |
4806 | if(internal_branch(addr)) |
57871462 |
4807 | { |
4808 | int t=(addr-start)>>2; |
4809 | int hr; |
4810 | for(hr=0;hr<HOST_REGS;hr++) { |
4811 | if(hr!=EXCLUDE_REG) { |
4812 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { |
ad49de89 |
4813 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) { |
57871462 |
4814 | if((i_dirty>>hr)&1) { |
00fa9369 |
4815 | assert(i_regmap[hr]<64); |
4816 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) |
4817 | emit_storereg(i_regmap[hr],hr); |
57871462 |
4818 | } |
4819 | } |
4820 | } |
4821 | } |
4822 | } |
4823 | } |
4824 | else |
4825 | { |
4826 | // Branch out of this block, write out all dirty regs |
ad49de89 |
4827 | wb_dirtys(i_regmap,i_dirty); |
57871462 |
4828 | } |
4829 | } |
4830 | |
4831 | // Load all needed registers for branch target |
ad49de89 |
4832 | static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 |
4833 | { |
4834 | //if(addr>=start && addr<(start+slen*4)) |
ad49de89 |
4835 | if(internal_branch(addr)) |
57871462 |
4836 | { |
4837 | int t=(addr-start)>>2; |
4838 | int hr; |
4839 | // Store the cycle count before loading something else |
4840 | if(i_regmap[HOST_CCREG]!=CCREG) { |
4841 | assert(i_regmap[HOST_CCREG]==-1); |
4842 | } |
4843 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4844 | emit_storereg(CCREG,HOST_CCREG); |
4845 | } |
4846 | // Load 32-bit regs |
4847 | for(hr=0;hr<HOST_REGS;hr++) { |
ea3d2e6e |
4848 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
00fa9369 |
4849 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
57871462 |
4850 | if(regs[t].regmap_entry[hr]==0) { |
4851 | emit_zeroreg(hr); |
4852 | } |
4853 | else if(regs[t].regmap_entry[hr]!=CCREG) |
4854 | { |
4855 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4856 | } |
4857 | } |
4858 | } |
4859 | } |
57871462 |
4860 | } |
4861 | } |
4862 | |
ad49de89 |
4863 | static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 |
4864 | { |
4865 | if(addr>=start && addr<start+slen*4-4) |
4866 | { |
4867 | int t=(addr-start)>>2; |
4868 | int hr; |
4869 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; |
4870 | for(hr=0;hr<HOST_REGS;hr++) |
4871 | { |
4872 | if(hr!=EXCLUDE_REG) |
4873 | { |
4874 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) |
4875 | { |
ea3d2e6e |
4876 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
57871462 |
4877 | { |
4878 | return 0; |
4879 | } |
9f51b4b9 |
4880 | else |
57871462 |
4881 | if((i_dirty>>hr)&1) |
4882 | { |
ea3d2e6e |
4883 | if(i_regmap[hr]<TEMPREG) |
57871462 |
4884 | { |
4885 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) |
4886 | return 0; |
4887 | } |
ea3d2e6e |
4888 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
57871462 |
4889 | { |
00fa9369 |
4890 | assert(0); |
57871462 |
4891 | } |
4892 | } |
4893 | } |
4894 | else // Same register but is it 32-bit or dirty? |
4895 | if(i_regmap[hr]>=0) |
4896 | { |
4897 | if(!((regs[t].dirty>>hr)&1)) |
4898 | { |
4899 | if((i_dirty>>hr)&1) |
4900 | { |
4901 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) |
4902 | { |
4903 | //printf("%x: dirty no match\n",addr); |
4904 | return 0; |
4905 | } |
4906 | } |
4907 | } |
57871462 |
4908 | } |
4909 | } |
4910 | } |
57871462 |
4911 | // Delay slots are not valid branch targets |
fe807a8a |
4912 | //if(t>0&&(dops[t-1].is_jump) return 0; |
57871462 |
4913 | // Delay slots require additional processing, so do not match |
cf95b4f0 |
4914 | if(dops[t].is_ds) return 0; |
57871462 |
4915 | } |
4916 | else |
4917 | { |
4918 | int hr; |
4919 | for(hr=0;hr<HOST_REGS;hr++) |
4920 | { |
4921 | if(hr!=EXCLUDE_REG) |
4922 | { |
4923 | if(i_regmap[hr]>=0) |
4924 | { |
4925 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) |
4926 | { |
4927 | if((i_dirty>>hr)&1) |
4928 | { |
4929 | return 0; |
4930 | } |
4931 | } |
4932 | } |
4933 | } |
4934 | } |
4935 | } |
4936 | return 1; |
4937 | } |
4938 | |
dd114d7d |
4939 | #ifdef DRC_DBG |
2330734f |
4940 | static void drc_dbg_emit_do_cmp(int i, int ccadj_) |
dd114d7d |
4941 | { |
4942 | extern void do_insn_cmp(); |
3968e69e |
4943 | //extern int cycle; |
81dbbf4c |
4944 | u_int hr, reglist = get_host_reglist(regs[i].regmap); |
dd114d7d |
4945 | |
40fca85b |
4946 | assem_debug("//do_insn_cmp %08x\n", start+i*4); |
dd114d7d |
4947 | save_regs(reglist); |
40fca85b |
4948 | // write out changed consts to match the interpreter |
cf95b4f0 |
4949 | if (i > 0 && !dops[i].bt) { |
40fca85b |
4950 | for (hr = 0; hr < HOST_REGS; hr++) { |
2330734f |
4951 | int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; |
277718fa |
4952 | if (hr == EXCLUDE_REG || reg <= 0) |
40fca85b |
4953 | continue; |
4954 | if (!((regs[i-1].isconst >> hr) & 1)) |
4955 | continue; |
4956 | if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr]) |
4957 | continue; |
4958 | emit_movimm(constmap[i-1][hr],0); |
4959 | emit_storereg(reg, 0); |
4960 | } |
4961 | } |
dd114d7d |
4962 | emit_movimm(start+i*4,0); |
643aeae3 |
4963 | emit_writeword(0,&pcaddr); |
2330734f |
4964 | int cc = get_reg(regs[i].regmap_entry, CCREG); |
4965 | if (cc < 0) |
4966 | emit_loadreg(CCREG, cc = 0); |
4967 | emit_addimm(cc, ccadj_, 0); |
4968 | emit_writeword(0, &psxRegs.cycle); |
2a014d73 |
4969 | emit_far_call(do_insn_cmp); |
643aeae3 |
4970 | //emit_readword(&cycle,0); |
dd114d7d |
4971 | //emit_addimm(0,2,0); |
643aeae3 |
4972 | //emit_writeword(0,&cycle); |
3968e69e |
4973 | (void)get_reg2; |
dd114d7d |
4974 | restore_regs(reglist); |
40fca85b |
4975 | assem_debug("\\\\do_insn_cmp\n"); |
dd114d7d |
4976 | } |
4977 | #else |
2330734f |
4978 | #define drc_dbg_emit_do_cmp(x,y) |
dd114d7d |
4979 | #endif |
4980 | |
57871462 |
4981 | // Used when a branch jumps into the delay slot of another branch |
7c3a5182 |
4982 | static void ds_assemble_entry(int i) |
57871462 |
4983 | { |
277718fa |
4984 | int t = (cinfo[i].ba - start) >> 2; |
2330734f |
4985 | int ccadj_ = -CLOCK_ADJUST(1); |
df4dc2b1 |
4986 | if (!instr_addr[t]) |
4987 | instr_addr[t] = out; |
277718fa |
4988 | assem_debug("Assemble delay slot at %x\n",cinfo[i].ba); |
57871462 |
4989 | assem_debug("<->\n"); |
2330734f |
4990 | drc_dbg_emit_do_cmp(t, ccadj_); |
57871462 |
4991 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) |
ad49de89 |
4992 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); |
cf95b4f0 |
4993 | load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); |
57871462 |
4994 | address_generation(t,®s[t],regs[t].regmap_entry); |
37387d8b |
4995 | if (ram_offset && (dops[t].is_load || dops[t].is_store)) |
53358c1d |
4996 | load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG); |
37387d8b |
4997 | if (dops[t].is_store) |
53358c1d |
4998 | load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP); |
57871462 |
4999 | is_delayslot=0; |
2330734f |
5000 | switch (dops[t].itype) { |
57871462 |
5001 | case SYSCALL: |
7139f3c8 |
5002 | case HLECALL: |
1e973cb0 |
5003 | case INTCALL: |
57871462 |
5004 | case UJUMP: |
5005 | case RJUMP: |
5006 | case CJUMP: |
5007 | case SJUMP: |
c43b5311 |
5008 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
2330734f |
5009 | break; |
5010 | default: |
5011 | assemble(t, ®s[t], ccadj_); |
57871462 |
5012 | } |
277718fa |
5013 | store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4); |
5014 | load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4); |
5015 | if(internal_branch(cinfo[i].ba+4)) |
57871462 |
5016 | assem_debug("branch: internal\n"); |
5017 | else |
5018 | assem_debug("branch: external\n"); |
277718fa |
5019 | assert(internal_branch(cinfo[i].ba+4)); |
5020 | add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4)); |
57871462 |
5021 | emit_jmp(0); |
5022 | } |
5023 | |
d1e4ebd9 |
5024 | // Load 2 immediates optimizing for small code size |
5025 | static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) |
5026 | { |
5027 | emit_movimm(imm1,rt1); |
5028 | emit_movimm_from(imm1,rt1,imm2,rt2); |
5029 | } |
5030 | |
2330734f |
5031 | static void do_cc(int i, const signed char i_regmap[], int *adj, |
5032 | int addr, int taken, int invert) |
57871462 |
5033 | { |
2330734f |
5034 | int count, count_plus2; |
b14b6a8f |
5035 | void *jaddr; |
5036 | void *idle=NULL; |
b6e87b2b |
5037 | int t=0; |
cf95b4f0 |
5038 | if(dops[i].itype==RJUMP) |
57871462 |
5039 | { |
5040 | *adj=0; |
5041 | } |
277718fa |
5042 | //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4)) |
5043 | if(internal_branch(cinfo[i].ba)) |
57871462 |
5044 | { |
277718fa |
5045 | t=(cinfo[i].ba-start)>>2; |
2330734f |
5046 | if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle |
277718fa |
5047 | else *adj=cinfo[t].ccadj; |
57871462 |
5048 | } |
5049 | else |
5050 | { |
5051 | *adj=0; |
5052 | } |
277718fa |
5053 | count = cinfo[i].ccadj; |
2330734f |
5054 | count_plus2 = count + CLOCK_ADJUST(2); |
277718fa |
5055 | if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) { |
57871462 |
5056 | // Idle loop |
5057 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); |
b14b6a8f |
5058 | idle=out; |
57871462 |
5059 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles |
5060 | emit_andimm(HOST_CCREG,3,HOST_CCREG); |
b14b6a8f |
5061 | jaddr=out; |
57871462 |
5062 | emit_jmp(0); |
5063 | } |
5064 | else if(*adj==0||invert) { |
2330734f |
5065 | int cycles = count_plus2; |
b6e87b2b |
5066 | // faster loop HACK |
bb4f300c |
5067 | #if 0 |
b6e87b2b |
5068 | if (t&&*adj) { |
5069 | int rel=t-i; |
5070 | if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) |
2330734f |
5071 | cycles=*adj+count+2-*adj; |
b6e87b2b |
5072 | } |
bb4f300c |
5073 | #endif |
2330734f |
5074 | emit_addimm_and_set_flags(cycles, HOST_CCREG); |
5075 | jaddr = out; |
57871462 |
5076 | emit_jns(0); |
5077 | } |
5078 | else |
5079 | { |
2330734f |
5080 | emit_cmpimm(HOST_CCREG, -count_plus2); |
5081 | jaddr = out; |
57871462 |
5082 | emit_jns(0); |
5083 | } |
2330734f |
5084 | add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0); |
57871462 |
5085 | } |
5086 | |
b14b6a8f |
5087 | static void do_ccstub(int n) |
57871462 |
5088 | { |
5089 | literal_pool(256); |
d1e4ebd9 |
5090 | assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4); |
b14b6a8f |
5091 | set_jump_target(stubs[n].addr, out); |
5092 | int i=stubs[n].b; |
5093 | if(stubs[n].d==NULLDS) { |
57871462 |
5094 | // Delay slot instruction is nullified ("likely" branch) |
ad49de89 |
5095 | wb_dirtys(regs[i].regmap,regs[i].dirty); |
57871462 |
5096 | } |
b14b6a8f |
5097 | else if(stubs[n].d!=TAKEN) { |
ad49de89 |
5098 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty); |
57871462 |
5099 | } |
5100 | else { |
277718fa |
5101 | if(internal_branch(cinfo[i].ba)) |
5102 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5103 | } |
b14b6a8f |
5104 | if(stubs[n].c!=-1) |
57871462 |
5105 | { |
5106 | // Save PC as return address |
6d75addf |
5107 | emit_movimm(stubs[n].c,0); |
5108 | emit_writeword(0,&pcaddr); |
57871462 |
5109 | } |
5110 | else |
5111 | { |
5112 | // Return address depends on which way the branch goes |
cf95b4f0 |
5113 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 |
5114 | { |
cf95b4f0 |
5115 | int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5116 | int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); |
5117 | if(dops[i].rs1==0) |
57871462 |
5118 | { |
ad49de89 |
5119 | s1l=s2l; |
5120 | s2l=-1; |
57871462 |
5121 | } |
cf95b4f0 |
5122 | else if(dops[i].rs2==0) |
57871462 |
5123 | { |
ad49de89 |
5124 | s2l=-1; |
57871462 |
5125 | } |
5126 | assert(s1l>=0); |
5127 | #ifdef DESTRUCTIVE_WRITEBACK |
cf95b4f0 |
5128 | if(dops[i].rs1) { |
ad49de89 |
5129 | if((branch_regs[i].dirty>>s1l)&&1) |
cf95b4f0 |
5130 | emit_loadreg(dops[i].rs1,s1l); |
9f51b4b9 |
5131 | } |
57871462 |
5132 | else { |
ad49de89 |
5133 | if((branch_regs[i].dirty>>s1l)&1) |
cf95b4f0 |
5134 | emit_loadreg(dops[i].rs2,s1l); |
57871462 |
5135 | } |
5136 | if(s2l>=0) |
ad49de89 |
5137 | if((branch_regs[i].dirty>>s2l)&1) |
cf95b4f0 |
5138 | emit_loadreg(dops[i].rs2,s2l); |
57871462 |
5139 | #endif |
5140 | int hr=0; |
5194fb95 |
5141 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 |
5142 | while(hr<HOST_REGS) |
5143 | { |
5144 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
9de8a0c3 |
5145 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5146 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) |
57871462 |
5147 | { |
5148 | addr=hr++;break; |
5149 | } |
5150 | hr++; |
5151 | } |
5152 | while(hr<HOST_REGS) |
5153 | { |
5154 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
9de8a0c3 |
5155 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5156 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) |
57871462 |
5157 | { |
5158 | alt=hr++;break; |
5159 | } |
5160 | hr++; |
5161 | } |
ecca05e3 |
5162 | if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register |
57871462 |
5163 | { |
5164 | while(hr<HOST_REGS) |
5165 | { |
5166 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
9de8a0c3 |
5167 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
5168 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) |
57871462 |
5169 | { |
5170 | ntaddr=hr;break; |
5171 | } |
5172 | hr++; |
5173 | } |
5174 | assert(hr<HOST_REGS); |
5175 | } |
ecca05e3 |
5176 | if (dops[i].opcode == 4) // BEQ |
57871462 |
5177 | { |
5178 | #ifdef HAVE_CMOV_IMM |
ad49de89 |
5179 | if(s2l>=0) emit_cmp(s1l,s2l); |
5180 | else emit_test(s1l,s1l); |
277718fa |
5181 | emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr); |
ad49de89 |
5182 | #else |
277718fa |
5183 | emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt); |
ad49de89 |
5184 | if(s2l>=0) emit_cmp(s1l,s2l); |
5185 | else emit_test(s1l,s1l); |
5186 | emit_cmovne_reg(alt,addr); |
57871462 |
5187 | #endif |
57871462 |
5188 | } |
ecca05e3 |
5189 | else if (dops[i].opcode == 5) // BNE |
57871462 |
5190 | { |
5191 | #ifdef HAVE_CMOV_IMM |
ad49de89 |
5192 | if(s2l>=0) emit_cmp(s1l,s2l); |
5193 | else emit_test(s1l,s1l); |
277718fa |
5194 | emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr); |
ad49de89 |
5195 | #else |
277718fa |
5196 | emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt); |
ad49de89 |
5197 | if(s2l>=0) emit_cmp(s1l,s2l); |
5198 | else emit_test(s1l,s1l); |
5199 | emit_cmovne_reg(alt,addr); |
57871462 |
5200 | #endif |
57871462 |
5201 | } |
ecca05e3 |
5202 | else if (dops[i].opcode == 6) // BLEZ |
57871462 |
5203 | { |
277718fa |
5204 | //emit_movimm(cinfo[i].ba,alt); |
57871462 |
5205 | //emit_movimm(start+i*4+8,addr); |
277718fa |
5206 | emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr); |
57871462 |
5207 | emit_cmpimm(s1l,1); |
57871462 |
5208 | emit_cmovl_reg(alt,addr); |
57871462 |
5209 | } |
ecca05e3 |
5210 | else if (dops[i].opcode == 7) // BGTZ |
57871462 |
5211 | { |
277718fa |
5212 | //emit_movimm(cinfo[i].ba,addr); |
57871462 |
5213 | //emit_movimm(start+i*4+8,ntaddr); |
277718fa |
5214 | emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr); |
57871462 |
5215 | emit_cmpimm(s1l,1); |
57871462 |
5216 | emit_cmovl_reg(ntaddr,addr); |
57871462 |
5217 | } |
ecca05e3 |
5218 | else if (dops[i].itype == SJUMP) // BLTZ/BGEZ |
57871462 |
5219 | { |
277718fa |
5220 | //emit_movimm(cinfo[i].ba,alt); |
57871462 |
5221 | //emit_movimm(start+i*4+8,addr); |
de6dbc52 |
5222 | if (dops[i].rs1) { |
5223 | emit_mov2imm_compact(cinfo[i].ba, |
5224 | (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8, |
5225 | (dops[i].opcode2 & 1) ? alt : addr); |
5226 | emit_test(s1l,s1l); |
5227 | emit_cmovs_reg(alt,addr); |
5228 | } |
5229 | else |
5230 | emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr); |
57871462 |
5231 | } |
ecca05e3 |
5232 | emit_writeword(addr, &pcaddr); |
57871462 |
5233 | } |
5234 | else |
cf95b4f0 |
5235 | if(dops[i].itype==RJUMP) |
57871462 |
5236 | { |
cf95b4f0 |
5237 | int r=get_reg(branch_regs[i].regmap,dops[i].rs1); |
4919de1e |
5238 | if (ds_writes_rjump_rs(i)) { |
57871462 |
5239 | r=get_reg(branch_regs[i].regmap,RTEMP); |
5240 | } |
643aeae3 |
5241 | emit_writeword(r,&pcaddr); |
57871462 |
5242 | } |
7c3a5182 |
5243 | else {SysPrintf("Unknown branch type in do_ccstub\n");abort();} |
57871462 |
5244 | } |
5245 | // Update cycle count |
5246 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); |
2330734f |
5247 | if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG); |
2a014d73 |
5248 | emit_far_call(cc_interrupt); |
2330734f |
5249 | if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG); |
b14b6a8f |
5250 | if(stubs[n].d==TAKEN) { |
277718fa |
5251 | if(internal_branch(cinfo[i].ba)) |
5252 | load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry); |
cf95b4f0 |
5253 | else if(dops[i].itype==RJUMP) { |
57871462 |
5254 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) |
643aeae3 |
5255 | emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); |
57871462 |
5256 | else |
cf95b4f0 |
5257 | emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1)); |
57871462 |
5258 | } |
b14b6a8f |
5259 | }else if(stubs[n].d==NOTTAKEN) { |
57871462 |
5260 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); |
5261 | else load_all_regs(branch_regs[i].regmap); |
b14b6a8f |
5262 | }else if(stubs[n].d==NULLDS) { |
57871462 |
5263 | // Delay slot instruction is nullified ("likely" branch) |
5264 | if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]); |
5265 | else load_all_regs(regs[i].regmap); |
5266 | }else{ |
5267 | load_all_regs(branch_regs[i].regmap); |
5268 | } |
d1e4ebd9 |
5269 | if (stubs[n].retaddr) |
5270 | emit_jmp(stubs[n].retaddr); |
5271 | else |
5272 | do_jump_vaddr(stubs[n].e); |
57871462 |
5273 | } |
5274 | |
104df9d3 |
5275 | static void add_to_linker(void *addr, u_int target, int is_internal) |
57871462 |
5276 | { |
643aeae3 |
5277 | assert(linkcount < ARRAY_SIZE(link_addr)); |
5278 | link_addr[linkcount].addr = addr; |
5279 | link_addr[linkcount].target = target; |
104df9d3 |
5280 | link_addr[linkcount].internal = is_internal; |
57871462 |
5281 | linkcount++; |
5282 | } |
5283 | |
eba830cd |
5284 | static void ujump_assemble_write_ra(int i) |
5285 | { |
5286 | int rt; |
5287 | unsigned int return_address; |
5288 | rt=get_reg(branch_regs[i].regmap,31); |
de6dbc52 |
5289 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
eba830cd |
5290 | //assert(rt>=0); |
5291 | return_address=start+i*4+8; |
5292 | if(rt>=0) { |
5293 | #ifdef USE_MINI_HT |
cf95b4f0 |
5294 | if(internal_branch(return_address)&&dops[i+1].rt1!=31) { |
eba830cd |
5295 | int temp=-1; // note: must be ds-safe |
5296 | #ifdef HOST_TEMPREG |
5297 | temp=HOST_TEMPREG; |
5298 | #endif |
5299 | if(temp>=0) do_miniht_insert(return_address,rt,temp); |
5300 | else emit_movimm(return_address,rt); |
5301 | } |
5302 | else |
5303 | #endif |
5304 | { |
5305 | #ifdef REG_PREFETCH |
9f51b4b9 |
5306 | if(temp>=0) |
eba830cd |
5307 | { |
643aeae3 |
5308 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd |
5309 | } |
5310 | #endif |
de6dbc52 |
5311 | if (!((regs[i].loadedconst >> rt) & 1)) |
5312 | emit_movimm(return_address, rt); // PC into link register |
eba830cd |
5313 | #ifdef IMM_PREFETCH |
df4dc2b1 |
5314 | emit_prefetch(hash_table_get(return_address)); |
eba830cd |
5315 | #endif |
5316 | } |
5317 | } |
5318 | } |
5319 | |
2330734f |
5320 | static void ujump_assemble(int i, const struct regstat *i_regs) |
57871462 |
5321 | { |
277718fa |
5322 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); |
57871462 |
5323 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5324 | #ifdef REG_PREFETCH |
5325 | int temp=get_reg(branch_regs[i].regmap,PTEMP); |
cf95b4f0 |
5326 | if(dops[i].rt1==31&&temp>=0) |
57871462 |
5327 | { |
581335b0 |
5328 | signed char *i_regmap=i_regs->regmap; |
57871462 |
5329 | int return_address=start+i*4+8; |
9f51b4b9 |
5330 | if(get_reg(branch_regs[i].regmap,31)>0) |
643aeae3 |
5331 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 |
5332 | } |
5333 | #endif |
de6dbc52 |
5334 | if (dops[i].rt1 == 31) |
eba830cd |
5335 | ujump_assemble_write_ra(i); // writeback ra for DS |
4ef8f67d |
5336 | ds_assemble(i+1,i_regs); |
5337 | uint64_t bc_unneeded=branch_regs[i].u; |
cf95b4f0 |
5338 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
ad49de89 |
5339 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
53358c1d |
5340 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
57871462 |
5341 | int cc,adj; |
5342 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5343 | assert(cc==HOST_CCREG); |
277718fa |
5344 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5345 | #ifdef REG_PREFETCH |
cf95b4f0 |
5346 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 |
5347 | #endif |
277718fa |
5348 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5349 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5350 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5351 | if(internal_branch(cinfo[i].ba)) |
57871462 |
5352 | assem_debug("branch: internal\n"); |
5353 | else |
5354 | assem_debug("branch: external\n"); |
277718fa |
5355 | if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) { |
57871462 |
5356 | ds_assemble_entry(i); |
5357 | } |
5358 | else { |
277718fa |
5359 | add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba)); |
57871462 |
5360 | emit_jmp(0); |
5361 | } |
5362 | } |
5363 | |
eba830cd |
5364 | static void rjump_assemble_write_ra(int i) |
5365 | { |
5366 | int rt,return_address; |
a5cd72d0 |
5367 | rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1); |
de6dbc52 |
5368 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
eba830cd |
5369 | assert(rt>=0); |
5370 | return_address=start+i*4+8; |
5371 | #ifdef REG_PREFETCH |
9f51b4b9 |
5372 | if(temp>=0) |
eba830cd |
5373 | { |
643aeae3 |
5374 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd |
5375 | } |
5376 | #endif |
de6dbc52 |
5377 | if (!((regs[i].loadedconst >> rt) & 1)) |
5378 | emit_movimm(return_address, rt); // PC into link register |
eba830cd |
5379 | #ifdef IMM_PREFETCH |
df4dc2b1 |
5380 | emit_prefetch(hash_table_get(return_address)); |
eba830cd |
5381 | #endif |
5382 | } |
5383 | |
2330734f |
5384 | static void rjump_assemble(int i, const struct regstat *i_regs) |
57871462 |
5385 | { |
57871462 |
5386 | int temp; |
581335b0 |
5387 | int rs,cc; |
cf95b4f0 |
5388 | rs=get_reg(branch_regs[i].regmap,dops[i].rs1); |
57871462 |
5389 | assert(rs>=0); |
4919de1e |
5390 | if (ds_writes_rjump_rs(i)) { |
57871462 |
5391 | // Delay slot abuse, make a copy of the branch address register |
5392 | temp=get_reg(branch_regs[i].regmap,RTEMP); |
5393 | assert(temp>=0); |
5394 | assert(regs[i].regmap[temp]==RTEMP); |
5395 | emit_mov(rs,temp); |
5396 | rs=temp; |
5397 | } |
5398 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5399 | #ifdef REG_PREFETCH |
cf95b4f0 |
5400 | if(dops[i].rt1==31) |
57871462 |
5401 | { |
5402 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { |
581335b0 |
5403 | signed char *i_regmap=i_regs->regmap; |
57871462 |
5404 | int return_address=start+i*4+8; |
643aeae3 |
5405 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 |
5406 | } |
5407 | } |
5408 | #endif |
5409 | #ifdef USE_MINI_HT |
cf95b4f0 |
5410 | if(dops[i].rs1==31) { |
57871462 |
5411 | int rh=get_reg(regs[i].regmap,RHASH); |
5412 | if(rh>=0) do_preload_rhash(rh); |
5413 | } |
5414 | #endif |
de6dbc52 |
5415 | if (dops[i].rt1 != 0) |
eba830cd |
5416 | rjump_assemble_write_ra(i); |
d5910d5d |
5417 | ds_assemble(i+1,i_regs); |
5418 | uint64_t bc_unneeded=branch_regs[i].u; |
cf95b4f0 |
5419 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5420 | bc_unneeded&=~(1LL<<dops[i].rs1); |
ad49de89 |
5421 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
cf95b4f0 |
5422 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG); |
57871462 |
5423 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5424 | assert(cc==HOST_CCREG); |
581335b0 |
5425 | (void)cc; |
57871462 |
5426 | #ifdef USE_MINI_HT |
5427 | int rh=get_reg(branch_regs[i].regmap,RHASH); |
5428 | int ht=get_reg(branch_regs[i].regmap,RHTBL); |
cf95b4f0 |
5429 | if(dops[i].rs1==31) { |
57871462 |
5430 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); |
5431 | do_preload_rhtbl(ht); |
5432 | do_rhash(rs,rh); |
5433 | } |
5434 | #endif |
ad49de89 |
5435 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 |
5436 | #ifdef DESTRUCTIVE_WRITEBACK |
ad49de89 |
5437 | if((branch_regs[i].dirty>>rs)&1) { |
cf95b4f0 |
5438 | if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) { |
5439 | emit_loadreg(dops[i].rs1,rs); |
57871462 |
5440 | } |
5441 | } |
5442 | #endif |
5443 | #ifdef REG_PREFETCH |
cf95b4f0 |
5444 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 |
5445 | #endif |
5446 | #ifdef USE_MINI_HT |
cf95b4f0 |
5447 | if(dops[i].rs1==31) { |
57871462 |
5448 | do_miniht_load(ht,rh); |
5449 | } |
5450 | #endif |
5451 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); |
277718fa |
5452 | //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen |
57871462 |
5453 | //assert(adj==0); |
277718fa |
5454 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
d1e4ebd9 |
5455 | add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); |
a5cd72d0 |
5456 | if (dops[i+1].itype == RFE) |
911f2d55 |
5457 | // special case for RFE |
5458 | emit_jmp(0); |
5459 | else |
71e490c5 |
5460 | emit_jns(0); |
ad49de89 |
5461 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 |
5462 | #ifdef USE_MINI_HT |
cf95b4f0 |
5463 | if(dops[i].rs1==31) { |
57871462 |
5464 | do_miniht_jump(rs,rh,ht); |
5465 | } |
5466 | else |
5467 | #endif |
5468 | { |
d1e4ebd9 |
5469 | do_jump_vaddr(rs); |
57871462 |
5470 | } |
57871462 |
5471 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
cf95b4f0 |
5472 | if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); |
57871462 |
5473 | #endif |
5474 | } |
5475 | |
2330734f |
5476 | static void cjump_assemble(int i, const struct regstat *i_regs) |
57871462 |
5477 | { |
2330734f |
5478 | const signed char *i_regmap = i_regs->regmap; |
57871462 |
5479 | int cc; |
5480 | int match; |
277718fa |
5481 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5482 | assem_debug("match=%d\n",match); |
ad49de89 |
5483 | int s1l,s2l; |
57871462 |
5484 | int unconditional=0,nop=0; |
57871462 |
5485 | int invert=0; |
277718fa |
5486 | int internal=internal_branch(cinfo[i].ba); |
5487 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); |
57871462 |
5488 | if(!match) invert=1; |
5489 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
277718fa |
5490 | if(i>(cinfo[i].ba-start)>>2) invert=1; |
57871462 |
5491 | #endif |
3968e69e |
5492 | #ifdef __aarch64__ |
5493 | invert=1; // because of near cond. branches |
5494 | #endif |
9f51b4b9 |
5495 | |
cf95b4f0 |
5496 | if(dops[i].ooo) { |
5497 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5498 | s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); |
57871462 |
5499 | } |
5500 | else { |
cf95b4f0 |
5501 | s1l=get_reg(i_regmap,dops[i].rs1); |
5502 | s2l=get_reg(i_regmap,dops[i].rs2); |
57871462 |
5503 | } |
cf95b4f0 |
5504 | if(dops[i].rs1==0&&dops[i].rs2==0) |
57871462 |
5505 | { |
cf95b4f0 |
5506 | if(dops[i].opcode&1) nop=1; |
57871462 |
5507 | else unconditional=1; |
cf95b4f0 |
5508 | //assert(dops[i].opcode!=5); |
5509 | //assert(dops[i].opcode!=7); |
5510 | //assert(dops[i].opcode!=0x15); |
5511 | //assert(dops[i].opcode!=0x17); |
57871462 |
5512 | } |
cf95b4f0 |
5513 | else if(dops[i].rs1==0) |
57871462 |
5514 | { |
ad49de89 |
5515 | s1l=s2l; |
5516 | s2l=-1; |
57871462 |
5517 | } |
cf95b4f0 |
5518 | else if(dops[i].rs2==0) |
57871462 |
5519 | { |
ad49de89 |
5520 | s2l=-1; |
57871462 |
5521 | } |
5522 | |
cf95b4f0 |
5523 | if(dops[i].ooo) { |
57871462 |
5524 | // Out of order execution (delay slot first) |
5525 | //printf("OOOE\n"); |
5526 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5527 | ds_assemble(i+1,i_regs); |
5528 | int adj; |
5529 | uint64_t bc_unneeded=branch_regs[i].u; |
cf95b4f0 |
5530 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
5531 | bc_unneeded|=1; |
ad49de89 |
5532 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
cf95b4f0 |
5533 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2); |
53358c1d |
5534 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
57871462 |
5535 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5536 | assert(cc==HOST_CCREG); |
9f51b4b9 |
5537 | if(unconditional) |
277718fa |
5538 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5539 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional); |
57871462 |
5540 | //assem_debug("cycle count (adj)\n"); |
5541 | if(unconditional) { |
277718fa |
5542 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5543 | if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) { |
5544 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5545 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5546 | if(internal) |
5547 | assem_debug("branch: internal\n"); |
5548 | else |
5549 | assem_debug("branch: external\n"); |
277718fa |
5550 | if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) { |
57871462 |
5551 | ds_assemble_entry(i); |
5552 | } |
5553 | else { |
277718fa |
5554 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5555 | emit_jmp(0); |
5556 | } |
5557 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5558 | if(((u_int)out)&7) emit_addnop(0); |
5559 | #endif |
5560 | } |
5561 | } |
5562 | else if(nop) { |
277718fa |
5563 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
b14b6a8f |
5564 | void *jaddr=out; |
57871462 |
5565 | emit_jns(0); |
b14b6a8f |
5566 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
5567 | } |
5568 | else { |
df4dc2b1 |
5569 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 |
5570 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
277718fa |
5571 | if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
9f51b4b9 |
5572 | |
57871462 |
5573 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5574 | assert(s1l>=0); |
cf95b4f0 |
5575 | if(dops[i].opcode==4) // BEQ |
57871462 |
5576 | { |
5577 | if(s2l>=0) emit_cmp(s1l,s2l); |
5578 | else emit_test(s1l,s1l); |
5579 | if(invert){ |
df4dc2b1 |
5580 | nottaken=out; |
7c3a5182 |
5581 | emit_jne(DJT_1); |
57871462 |
5582 | }else{ |
277718fa |
5583 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5584 | emit_jeq(0); |
5585 | } |
5586 | } |
cf95b4f0 |
5587 | if(dops[i].opcode==5) // BNE |
57871462 |
5588 | { |
5589 | if(s2l>=0) emit_cmp(s1l,s2l); |
5590 | else emit_test(s1l,s1l); |
5591 | if(invert){ |
df4dc2b1 |
5592 | nottaken=out; |
7c3a5182 |
5593 | emit_jeq(DJT_1); |
57871462 |
5594 | }else{ |
277718fa |
5595 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5596 | emit_jne(0); |
5597 | } |
5598 | } |
cf95b4f0 |
5599 | if(dops[i].opcode==6) // BLEZ |
57871462 |
5600 | { |
5601 | emit_cmpimm(s1l,1); |
5602 | if(invert){ |
df4dc2b1 |
5603 | nottaken=out; |
7c3a5182 |
5604 | emit_jge(DJT_1); |
57871462 |
5605 | }else{ |
277718fa |
5606 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5607 | emit_jl(0); |
5608 | } |
5609 | } |
cf95b4f0 |
5610 | if(dops[i].opcode==7) // BGTZ |
57871462 |
5611 | { |
5612 | emit_cmpimm(s1l,1); |
5613 | if(invert){ |
df4dc2b1 |
5614 | nottaken=out; |
7c3a5182 |
5615 | emit_jl(DJT_1); |
57871462 |
5616 | }else{ |
277718fa |
5617 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5618 | emit_jge(0); |
5619 | } |
5620 | } |
5621 | if(invert) { |
df4dc2b1 |
5622 | if(taken) set_jump_target(taken, out); |
57871462 |
5623 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
277718fa |
5624 | if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) { |
57871462 |
5625 | if(adj) { |
2330734f |
5626 | emit_addimm(cc,-adj,cc); |
277718fa |
5627 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5628 | }else{ |
5629 | emit_addnop(13); |
277718fa |
5630 | add_to_linker(out,cinfo[i].ba,internal*2); |
57871462 |
5631 | } |
5632 | emit_jmp(0); |
5633 | }else |
5634 | #endif |
5635 | { |
2330734f |
5636 | if(adj) emit_addimm(cc,-adj,cc); |
277718fa |
5637 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5638 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5639 | if(internal) |
5640 | assem_debug("branch: internal\n"); |
5641 | else |
5642 | assem_debug("branch: external\n"); |
277718fa |
5643 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 |
5644 | ds_assemble_entry(i); |
5645 | } |
5646 | else { |
277718fa |
5647 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5648 | emit_jmp(0); |
5649 | } |
5650 | } |
df4dc2b1 |
5651 | set_jump_target(nottaken, out); |
57871462 |
5652 | } |
5653 | |
df4dc2b1 |
5654 | if(nottaken1) set_jump_target(nottaken1, out); |
57871462 |
5655 | if(adj) { |
2330734f |
5656 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 |
5657 | } |
5658 | } // (!unconditional) |
5659 | } // if(ooo) |
5660 | else |
5661 | { |
5662 | // In-order execution (branch first) |
df4dc2b1 |
5663 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 |
5664 | if(!unconditional&&!nop) { |
57871462 |
5665 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5666 | assert(s1l>=0); |
cf95b4f0 |
5667 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 |
5668 | { |
5669 | if(s2l>=0) emit_cmp(s1l,s2l); |
5670 | else emit_test(s1l,s1l); |
df4dc2b1 |
5671 | nottaken=out; |
7c3a5182 |
5672 | emit_jne(DJT_2); |
57871462 |
5673 | } |
cf95b4f0 |
5674 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 |
5675 | { |
5676 | if(s2l>=0) emit_cmp(s1l,s2l); |
5677 | else emit_test(s1l,s1l); |
df4dc2b1 |
5678 | nottaken=out; |
7c3a5182 |
5679 | emit_jeq(DJT_2); |
57871462 |
5680 | } |
cf95b4f0 |
5681 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 |
5682 | { |
5683 | emit_cmpimm(s1l,1); |
df4dc2b1 |
5684 | nottaken=out; |
7c3a5182 |
5685 | emit_jge(DJT_2); |
57871462 |
5686 | } |
cf95b4f0 |
5687 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 |
5688 | { |
5689 | emit_cmpimm(s1l,1); |
df4dc2b1 |
5690 | nottaken=out; |
7c3a5182 |
5691 | emit_jl(DJT_2); |
57871462 |
5692 | } |
5693 | } // if(!unconditional) |
5694 | int adj; |
5695 | uint64_t ds_unneeded=branch_regs[i].u; |
cf95b4f0 |
5696 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 |
5697 | ds_unneeded|=1; |
57871462 |
5698 | // branch taken |
5699 | if(!nop) { |
df4dc2b1 |
5700 | if(taken) set_jump_target(taken, out); |
57871462 |
5701 | assem_debug("1:\n"); |
ad49de89 |
5702 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
57871462 |
5703 | // load regs |
cf95b4f0 |
5704 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
57871462 |
5705 | address_generation(i+1,&branch_regs[i],0); |
37387d8b |
5706 | if (ram_offset) |
53358c1d |
5707 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
ad49de89 |
5708 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
57871462 |
5709 | ds_assemble(i+1,&branch_regs[i]); |
5710 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5711 | if(cc==-1) { |
5712 | emit_loadreg(CCREG,cc=HOST_CCREG); |
5713 | // CHECK: Is the following instruction (fall thru) allocated ok? |
5714 | } |
5715 | assert(cc==HOST_CCREG); |
277718fa |
5716 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5717 | do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0); |
57871462 |
5718 | assem_debug("cycle count (adj)\n"); |
277718fa |
5719 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5720 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5721 | if(internal) |
5722 | assem_debug("branch: internal\n"); |
5723 | else |
5724 | assem_debug("branch: external\n"); |
277718fa |
5725 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 |
5726 | ds_assemble_entry(i); |
5727 | } |
5728 | else { |
277718fa |
5729 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5730 | emit_jmp(0); |
5731 | } |
5732 | } |
5733 | // branch not taken |
57871462 |
5734 | if(!unconditional) { |
df4dc2b1 |
5735 | if(nottaken1) set_jump_target(nottaken1, out); |
5736 | set_jump_target(nottaken, out); |
57871462 |
5737 | assem_debug("2:\n"); |
fe807a8a |
5738 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
37387d8b |
5739 | // load regs |
fe807a8a |
5740 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
5741 | address_generation(i+1,&branch_regs[i],0); |
37387d8b |
5742 | if (ram_offset) |
53358c1d |
5743 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
37387d8b |
5744 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
fe807a8a |
5745 | ds_assemble(i+1,&branch_regs[i]); |
57871462 |
5746 | cc=get_reg(branch_regs[i].regmap,CCREG); |
fe807a8a |
5747 | if (cc == -1) { |
57871462 |
5748 | // Cycle count isn't in a register, temporarily load it then write it out |
5749 | emit_loadreg(CCREG,HOST_CCREG); |
277718fa |
5750 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
b14b6a8f |
5751 | void *jaddr=out; |
57871462 |
5752 | emit_jns(0); |
b14b6a8f |
5753 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
5754 | emit_storereg(CCREG,HOST_CCREG); |
5755 | } |
5756 | else{ |
5757 | cc=get_reg(i_regmap,CCREG); |
5758 | assert(cc==HOST_CCREG); |
277718fa |
5759 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
b14b6a8f |
5760 | void *jaddr=out; |
57871462 |
5761 | emit_jns(0); |
fe807a8a |
5762 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
5763 | } |
5764 | } |
5765 | } |
5766 | } |
5767 | |
2330734f |
5768 | static void sjump_assemble(int i, const struct regstat *i_regs) |
57871462 |
5769 | { |
2330734f |
5770 | const signed char *i_regmap = i_regs->regmap; |
57871462 |
5771 | int cc; |
5772 | int match; |
277718fa |
5773 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
2acc46cd |
5774 | assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo); |
ad49de89 |
5775 | int s1l; |
57871462 |
5776 | int unconditional=0,nevertaken=0; |
57871462 |
5777 | int invert=0; |
277718fa |
5778 | int internal=internal_branch(cinfo[i].ba); |
5779 | if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); |
57871462 |
5780 | if(!match) invert=1; |
5781 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
277718fa |
5782 | if(i>(cinfo[i].ba-start)>>2) invert=1; |
57871462 |
5783 | #endif |
3968e69e |
5784 | #ifdef __aarch64__ |
5785 | invert=1; // because of near cond. branches |
5786 | #endif |
57871462 |
5787 | |
cf95b4f0 |
5788 | //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL) |
5789 | //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL) |
57871462 |
5790 | |
cf95b4f0 |
5791 | if(dops[i].ooo) { |
5792 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
57871462 |
5793 | } |
5794 | else { |
cf95b4f0 |
5795 | s1l=get_reg(i_regmap,dops[i].rs1); |
57871462 |
5796 | } |
cf95b4f0 |
5797 | if(dops[i].rs1==0) |
57871462 |
5798 | { |
cf95b4f0 |
5799 | if(dops[i].opcode2&1) unconditional=1; |
57871462 |
5800 | else nevertaken=1; |
5801 | // These are never taken (r0 is never less than zero) |
cf95b4f0 |
5802 | //assert(dops[i].opcode2!=0); |
5803 | //assert(dops[i].opcode2!=2); |
5804 | //assert(dops[i].opcode2!=0x10); |
5805 | //assert(dops[i].opcode2!=0x12); |
57871462 |
5806 | } |
57871462 |
5807 | |
cf95b4f0 |
5808 | if(dops[i].ooo) { |
57871462 |
5809 | // Out of order execution (delay slot first) |
5810 | //printf("OOOE\n"); |
5811 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5812 | ds_assemble(i+1,i_regs); |
5813 | int adj; |
5814 | uint64_t bc_unneeded=branch_regs[i].u; |
cf95b4f0 |
5815 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
5816 | bc_unneeded|=1; |
ad49de89 |
5817 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
cf95b4f0 |
5818 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1); |
53358c1d |
5819 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
cf95b4f0 |
5820 | if(dops[i].rt1==31) { |
57871462 |
5821 | int rt,return_address; |
57871462 |
5822 | rt=get_reg(branch_regs[i].regmap,31); |
de6dbc52 |
5823 | //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
57871462 |
5824 | if(rt>=0) { |
5825 | // Save the PC even if the branch is not taken |
5826 | return_address=start+i*4+8; |
5827 | emit_movimm(return_address,rt); // PC into link register |
5828 | #ifdef IMM_PREFETCH |
df4dc2b1 |
5829 | if(!nevertaken) emit_prefetch(hash_table_get(return_address)); |
57871462 |
5830 | #endif |
5831 | } |
5832 | } |
5833 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5834 | assert(cc==HOST_CCREG); |
9f51b4b9 |
5835 | if(unconditional) |
277718fa |
5836 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5837 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional); |
57871462 |
5838 | assem_debug("cycle count (adj)\n"); |
5839 | if(unconditional) { |
277718fa |
5840 | do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0); |
5841 | if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) { |
5842 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5843 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5844 | if(internal) |
5845 | assem_debug("branch: internal\n"); |
5846 | else |
5847 | assem_debug("branch: external\n"); |
277718fa |
5848 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 |
5849 | ds_assemble_entry(i); |
5850 | } |
5851 | else { |
277718fa |
5852 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5853 | emit_jmp(0); |
5854 | } |
5855 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5856 | if(((u_int)out)&7) emit_addnop(0); |
5857 | #endif |
5858 | } |
5859 | } |
5860 | else if(nevertaken) { |
277718fa |
5861 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
b14b6a8f |
5862 | void *jaddr=out; |
57871462 |
5863 | emit_jns(0); |
b14b6a8f |
5864 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
5865 | } |
5866 | else { |
df4dc2b1 |
5867 | void *nottaken = NULL; |
57871462 |
5868 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
277718fa |
5869 | if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
57871462 |
5870 | { |
5871 | assert(s1l>=0); |
ecca05e3 |
5872 | if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL |
57871462 |
5873 | { |
5874 | emit_test(s1l,s1l); |
5875 | if(invert){ |
df4dc2b1 |
5876 | nottaken=out; |
7c3a5182 |
5877 | emit_jns(DJT_1); |
57871462 |
5878 | }else{ |
277718fa |
5879 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5880 | emit_js(0); |
5881 | } |
5882 | } |
ecca05e3 |
5883 | else // BGEZ/BGEZAL |
57871462 |
5884 | { |
5885 | emit_test(s1l,s1l); |
5886 | if(invert){ |
df4dc2b1 |
5887 | nottaken=out; |
7c3a5182 |
5888 | emit_js(DJT_1); |
57871462 |
5889 | }else{ |
277718fa |
5890 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5891 | emit_jns(0); |
5892 | } |
5893 | } |
ad49de89 |
5894 | } |
9f51b4b9 |
5895 | |
57871462 |
5896 | if(invert) { |
5897 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
277718fa |
5898 | if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) { |
57871462 |
5899 | if(adj) { |
2330734f |
5900 | emit_addimm(cc,-adj,cc); |
277718fa |
5901 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5902 | }else{ |
5903 | emit_addnop(13); |
277718fa |
5904 | add_to_linker(out,cinfo[i].ba,internal*2); |
57871462 |
5905 | } |
5906 | emit_jmp(0); |
5907 | }else |
5908 | #endif |
5909 | { |
2330734f |
5910 | if(adj) emit_addimm(cc,-adj,cc); |
277718fa |
5911 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5912 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5913 | if(internal) |
5914 | assem_debug("branch: internal\n"); |
5915 | else |
5916 | assem_debug("branch: external\n"); |
277718fa |
5917 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 |
5918 | ds_assemble_entry(i); |
5919 | } |
5920 | else { |
277718fa |
5921 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5922 | emit_jmp(0); |
5923 | } |
5924 | } |
df4dc2b1 |
5925 | set_jump_target(nottaken, out); |
57871462 |
5926 | } |
5927 | |
5928 | if(adj) { |
2330734f |
5929 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 |
5930 | } |
5931 | } // (!unconditional) |
5932 | } // if(ooo) |
5933 | else |
5934 | { |
5935 | // In-order execution (branch first) |
5936 | //printf("IOE\n"); |
df4dc2b1 |
5937 | void *nottaken = NULL; |
de6dbc52 |
5938 | if (!unconditional && !nevertaken) { |
ecca05e3 |
5939 | assert(s1l >= 0); |
5940 | emit_test(s1l, s1l); |
5941 | } |
5942 | if (dops[i].rt1 == 31) { |
5943 | int rt, return_address; |
5944 | rt = get_reg(branch_regs[i].regmap,31); |
5945 | if(rt >= 0) { |
a6491170 |
5946 | // Save the PC even if the branch is not taken |
ecca05e3 |
5947 | return_address = start + i*4+8; |
5948 | emit_movimm(return_address, rt); // PC into link register |
a6491170 |
5949 | #ifdef IMM_PREFETCH |
df4dc2b1 |
5950 | emit_prefetch(hash_table_get(return_address)); |
a6491170 |
5951 | #endif |
5952 | } |
5953 | } |
de6dbc52 |
5954 | if (!unconditional && !nevertaken) { |
ecca05e3 |
5955 | nottaken = out; |
5956 | if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL |
5957 | emit_jns(DJT_1); |
5958 | else // BGEZ/BGEZAL |
5959 | emit_js(DJT_1); |
5960 | } |
57871462 |
5961 | int adj; |
5962 | uint64_t ds_unneeded=branch_regs[i].u; |
cf95b4f0 |
5963 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 |
5964 | ds_unneeded|=1; |
57871462 |
5965 | // branch taken |
5966 | if(!nevertaken) { |
5967 | //assem_debug("1:\n"); |
ad49de89 |
5968 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
57871462 |
5969 | // load regs |
cf95b4f0 |
5970 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
57871462 |
5971 | address_generation(i+1,&branch_regs[i],0); |
37387d8b |
5972 | if (ram_offset) |
53358c1d |
5973 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
ad49de89 |
5974 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
57871462 |
5975 | ds_assemble(i+1,&branch_regs[i]); |
5976 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5977 | if(cc==-1) { |
5978 | emit_loadreg(CCREG,cc=HOST_CCREG); |
5979 | // CHECK: Is the following instruction (fall thru) allocated ok? |
5980 | } |
5981 | assert(cc==HOST_CCREG); |
277718fa |
5982 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
5983 | do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0); |
57871462 |
5984 | assem_debug("cycle count (adj)\n"); |
277718fa |
5985 | if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc); |
5986 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba); |
57871462 |
5987 | if(internal) |
5988 | assem_debug("branch: internal\n"); |
5989 | else |
5990 | assem_debug("branch: external\n"); |
277718fa |
5991 | if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) { |
57871462 |
5992 | ds_assemble_entry(i); |
5993 | } |
5994 | else { |
277718fa |
5995 | add_to_linker(out,cinfo[i].ba,internal); |
57871462 |
5996 | emit_jmp(0); |
5997 | } |
5998 | } |
5999 | // branch not taken |
57871462 |
6000 | if(!unconditional) { |
de6dbc52 |
6001 | if (!nevertaken) { |
6002 | assert(nottaken); |
6003 | set_jump_target(nottaken, out); |
6004 | } |
57871462 |
6005 | assem_debug("1:\n"); |
fe807a8a |
6006 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
6007 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
6008 | address_generation(i+1,&branch_regs[i],0); |
5a18ce2e |
6009 | if (ram_offset) |
53358c1d |
6010 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
5a18ce2e |
6011 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
fe807a8a |
6012 | ds_assemble(i+1,&branch_regs[i]); |
57871462 |
6013 | cc=get_reg(branch_regs[i].regmap,CCREG); |
fe807a8a |
6014 | if (cc == -1) { |
57871462 |
6015 | // Cycle count isn't in a register, temporarily load it then write it out |
6016 | emit_loadreg(CCREG,HOST_CCREG); |
277718fa |
6017 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG); |
b14b6a8f |
6018 | void *jaddr=out; |
57871462 |
6019 | emit_jns(0); |
b14b6a8f |
6020 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
6021 | emit_storereg(CCREG,HOST_CCREG); |
6022 | } |
6023 | else{ |
6024 | cc=get_reg(i_regmap,CCREG); |
6025 | assert(cc==HOST_CCREG); |
277718fa |
6026 | emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc); |
b14b6a8f |
6027 | void *jaddr=out; |
57871462 |
6028 | emit_jns(0); |
fe807a8a |
6029 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 |
6030 | } |
6031 | } |
6032 | } |
6033 | } |
6034 | |
670c0f22 |
6035 | static void check_regmap(signed char *regmap) |
6036 | { |
6037 | #ifndef NDEBUG |
6038 | int i,j; |
6039 | for (i = 0; i < HOST_REGS; i++) { |
6040 | if (regmap[i] < 0) |
6041 | continue; |
6042 | for (j = i + 1; j < HOST_REGS; j++) |
6043 | assert(regmap[i] != regmap[j]); |
6044 | } |
6045 | #endif |
6046 | } |
6047 | |
4600ba03 |
6048 | #ifdef DISASM |
2acc46cd |
6049 | #include <inttypes.h> |
53dc27f6 |
6050 | static char insn[MAXBLOCK][10]; |
6051 | |
6052 | #define set_mnemonic(i_, n_) \ |
6053 | strcpy(insn[i_], n_) |
6054 | |
2acc46cd |
6055 | void print_regmap(const char *name, const signed char *regmap) |
6056 | { |
6057 | char buf[5]; |
6058 | int i, l; |
6059 | fputs(name, stdout); |
6060 | for (i = 0; i < HOST_REGS; i++) { |
6061 | l = 0; |
6062 | if (regmap[i] >= 0) |
6063 | l = snprintf(buf, sizeof(buf), "$%d", regmap[i]); |
6064 | for (; l < 3; l++) |
6065 | buf[l] = ' '; |
6066 | buf[l] = 0; |
6067 | printf(" r%d=%s", i, buf); |
6068 | } |
6069 | fputs("\n", stdout); |
6070 | } |
6071 | |
57871462 |
6072 | /* disassembly */ |
6073 | void disassemble_inst(int i) |
6074 | { |
cf95b4f0 |
6075 | if (dops[i].bt) printf("*"); else printf(" "); |
6076 | switch(dops[i].itype) { |
57871462 |
6077 | case UJUMP: |
277718fa |
6078 | printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break; |
57871462 |
6079 | case CJUMP: |
277718fa |
6080 | printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break; |
57871462 |
6081 | case SJUMP: |
cf95b4f0 |
6082 | printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; |
57871462 |
6083 | case RJUMP: |
ecca05e3 |
6084 | if (dops[i].opcode2 == 9 && dops[i].rt1 != 31) |
cf95b4f0 |
6085 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1); |
5067f341 |
6086 | else |
cf95b4f0 |
6087 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); |
5067f341 |
6088 | break; |
57871462 |
6089 | case IMM16: |
cf95b4f0 |
6090 | if(dops[i].opcode==0xf) //LUI |
277718fa |
6091 | printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff); |
57871462 |
6092 | else |
277718fa |
6093 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 |
6094 | break; |
6095 | case LOAD: |
6096 | case LOADLR: |
277718fa |
6097 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 |
6098 | break; |
6099 | case STORE: |
6100 | case STORELR: |
277718fa |
6101 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm); |
57871462 |
6102 | break; |
6103 | case ALU: |
6104 | case SHIFT: |
cf95b4f0 |
6105 | printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2); |
57871462 |
6106 | break; |
6107 | case MULTDIV: |
cf95b4f0 |
6108 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2); |
57871462 |
6109 | break; |
6110 | case SHIFTIMM: |
277718fa |
6111 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm); |
57871462 |
6112 | break; |
6113 | case MOV: |
cf95b4f0 |
6114 | if((dops[i].opcode2&0x1d)==0x10) |
6115 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1); |
6116 | else if((dops[i].opcode2&0x1d)==0x11) |
6117 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); |
57871462 |
6118 | else |
6119 | printf (" %x: %s\n",start+i*4,insn[i]); |
6120 | break; |
6121 | case COP0: |
cf95b4f0 |
6122 | if(dops[i].opcode2==0) |
6123 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0 |
6124 | else if(dops[i].opcode2==4) |
6125 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0 |
57871462 |
6126 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6127 | break; |
b9b61529 |
6128 | case COP2: |
cf95b4f0 |
6129 | if(dops[i].opcode2<3) |
6130 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2 |
6131 | else if(dops[i].opcode2>3) |
6132 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2 |
b9b61529 |
6133 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6134 | break; |
b9b61529 |
6135 | case C2LS: |
277718fa |
6136 | printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm); |
b9b61529 |
6137 | break; |
1e973cb0 |
6138 | case INTCALL: |
6139 | printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); |
6140 | break; |
57871462 |
6141 | default: |
6142 | //printf (" %s %8x\n",insn[i],source[i]); |
6143 | printf (" %x: %s\n",start+i*4,insn[i]); |
6144 | } |
a5cd72d0 |
6145 | #ifndef REGMAP_PRINT |
2acc46cd |
6146 | return; |
a5cd72d0 |
6147 | #endif |
6148 | printf("D: %"PRIx64" WD: %"PRIx64" U: %"PRIx64" hC: %x hWC: %x hLC: %x\n", |
6149 | regs[i].dirty, regs[i].wasdirty, unneeded_reg[i], |
6150 | regs[i].isconst, regs[i].wasconst, regs[i].loadedconst); |
2acc46cd |
6151 | print_regmap("pre: ", regmap_pre[i]); |
6152 | print_regmap("entry: ", regs[i].regmap_entry); |
6153 | print_regmap("map: ", regs[i].regmap); |
6154 | if (dops[i].is_jump) { |
6155 | print_regmap("bentry:", branch_regs[i].regmap_entry); |
6156 | print_regmap("bmap: ", branch_regs[i].regmap); |
6157 | } |
57871462 |
6158 | } |
4600ba03 |
6159 | #else |
53dc27f6 |
6160 | #define set_mnemonic(i_, n_) |
4600ba03 |
6161 | static void disassemble_inst(int i) {} |
6162 | #endif // DISASM |
57871462 |
6163 | |
d848b60a |
6164 | #define DRC_TEST_VAL 0x74657374 |
6165 | |
d9e2b173 |
6166 | static noinline void new_dynarec_test(void) |
d848b60a |
6167 | { |
be516ebe |
6168 | int (*testfunc)(void); |
d148d265 |
6169 | void *beginning; |
be516ebe |
6170 | int ret[2]; |
6171 | size_t i; |
d148d265 |
6172 | |
687b4580 |
6173 | // check structure linkage |
7c3a5182 |
6174 | if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs)) |
687b4580 |
6175 | { |
7c3a5182 |
6176 | SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); |
687b4580 |
6177 | } |
6178 | |
d9e2b173 |
6179 | SysPrintf("(%p) testing if we can run recompiled code @%p...\n", |
6180 | new_dynarec_test, out); |
6181 | ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty |
be516ebe |
6182 | |
6183 | for (i = 0; i < ARRAY_SIZE(ret); i++) { |
2a014d73 |
6184 | out = ndrc->translation_cache; |
be516ebe |
6185 | beginning = start_block(); |
6186 | emit_movimm(DRC_TEST_VAL + i, 0); // test |
6187 | emit_ret(); |
6188 | literal_pool(0); |
6189 | end_block(beginning); |
6190 | testfunc = beginning; |
6191 | ret[i] = testfunc(); |
6192 | } |
6193 | |
6194 | if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1) |
d848b60a |
6195 | SysPrintf("test passed.\n"); |
6196 | else |
be516ebe |
6197 | SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]); |
2a014d73 |
6198 | out = ndrc->translation_cache; |
d848b60a |
6199 | } |
6200 | |
dc990066 |
6201 | // clear the state completely, instead of just marking |
6202 | // things invalid like invalidate_all_pages() does |
919981d0 |
6203 | void new_dynarec_clear_full(void) |
57871462 |
6204 | { |
57871462 |
6205 | int n; |
2a014d73 |
6206 | out = ndrc->translation_cache; |
35775df7 |
6207 | memset(invalid_code,1,sizeof(invalid_code)); |
6208 | memset(hash_table,0xff,sizeof(hash_table)); |
57871462 |
6209 | memset(mini_ht,-1,sizeof(mini_ht)); |
dc990066 |
6210 | memset(shadow,0,sizeof(shadow)); |
57871462 |
6211 | copy=shadow; |
93c0345b |
6212 | expirep = EXPIRITY_OFFSET; |
57871462 |
6213 | pending_exception=0; |
6214 | literalcount=0; |
57871462 |
6215 | stop_after_jal=0; |
9be4ba64 |
6216 | inv_code_start=inv_code_end=~0; |
7f94b097 |
6217 | hack_addr=0; |
39b71d9a |
6218 | f1_hack=0; |
93c0345b |
6219 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6220 | blocks_clear(&blocks[n]); |
b7ad2f2c |
6221 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6222 | free(jumps[n]); |
6223 | jumps[n] = NULL; |
6224 | } |
104df9d3 |
6225 | stat_clear(stat_blocks); |
6226 | stat_clear(stat_links); |
32631e6a |
6227 | |
d5aeda23 |
6228 | cycle_multiplier_old = Config.cycle_multiplier; |
32631e6a |
6229 | new_dynarec_hacks_old = new_dynarec_hacks; |
dc990066 |
6230 | } |
6231 | |
919981d0 |
6232 | void new_dynarec_init(void) |
dc990066 |
6233 | { |
66ea165f |
6234 | SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc)); |
1e212a25 |
6235 | |
0aeb0cb9 |
6236 | #ifdef _3DS |
6237 | check_rosalina(); |
6238 | #endif |
2a014d73 |
6239 | #ifdef BASE_ADDR_DYNAMIC |
1e212a25 |
6240 | #ifdef VITA |
0aeb0cb9 |
6241 | sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); |
66ea165f |
6242 | if (sceBlock <= 0) |
6243 | SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock); |
2a014d73 |
6244 | int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); |
1e212a25 |
6245 | if (ret < 0) |
66ea165f |
6246 | SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret); |
0aeb0cb9 |
6247 | sceKernelOpenVMDomain(); |
6248 | sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); |
6249 | #elif defined(_MSC_VER) |
6250 | ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, |
6251 | PAGE_EXECUTE_READWRITE); |
3039c914 |
6252 | #elif defined(HAVE_LIBNX) |
6253 | Result rc = jitCreate(&g_jit, sizeof(*ndrc)); |
6254 | if (R_FAILED(rc)) |
6255 | SysPrintf("jitCreate failed: %08x\n", rc); |
6256 | SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type); |
d9e2b173 |
6257 | jitTransitionToWritable(&g_jit); |
3039c914 |
6258 | ndrc = g_jit.rx_addr; |
6259 | ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc; |
d9e2b173 |
6260 | memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp)); |
1e212a25 |
6261 | #else |
2a014d73 |
6262 | uintptr_t desired_addr = 0; |
3039c914 |
6263 | int prot = PROT_READ | PROT_WRITE | PROT_EXEC; |
6264 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6265 | int fd = -1; |
2a014d73 |
6266 | #ifdef __ELF__ |
6267 | extern char _end; |
6268 | desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl; |
6269 | #endif |
d9e2b173 |
6270 | #ifdef TC_WRITE_OFFSET |
3039c914 |
6271 | // mostly for testing |
6272 | fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600); |
6273 | ftruncate(fd, sizeof(*ndrc)); |
6274 | void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE, |
6275 | (flags = MAP_SHARED), fd, 0); |
6276 | assert(mw != MAP_FAILED); |
6277 | prot = PROT_READ | PROT_EXEC; |
6278 | #endif |
6279 | ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0); |
2a014d73 |
6280 | if (ndrc == MAP_FAILED) { |
d848b60a |
6281 | SysPrintf("mmap() failed: %s\n", strerror(errno)); |
1e212a25 |
6282 | abort(); |
d848b60a |
6283 | } |
d9e2b173 |
6284 | #ifdef TC_WRITE_OFFSET |
3039c914 |
6285 | ndrc_write_ofs = (char *)mw - (char *)ndrc; |
6286 | #endif |
1e212a25 |
6287 | #endif |
6288 | #else |
6289 | #ifndef NO_WRITE_EXEC |
bdeade46 |
6290 | // not all systems allow execute in data segment by default |
761fdd0a |
6291 | // size must be 4K aligned for 3DS? |
6292 | if (mprotect(ndrc, sizeof(*ndrc), |
2a014d73 |
6293 | PROT_READ | PROT_WRITE | PROT_EXEC) != 0) |
d848b60a |
6294 | SysPrintf("mprotect() failed: %s\n", strerror(errno)); |
1e212a25 |
6295 | #endif |
dc990066 |
6296 | #endif |
2a014d73 |
6297 | out = ndrc->translation_cache; |
dc990066 |
6298 | new_dynarec_clear_full(); |
6299 | #ifdef HOST_IMM8 |
6300 | // Copy this into local area so we don't have to put it in every literal pool |
6301 | invc_ptr=invalid_code; |
6302 | #endif |
57871462 |
6303 | arch_init(); |
d848b60a |
6304 | new_dynarec_test(); |
01d26796 |
6305 | ram_offset=(uintptr_t)rdram-0x80000000; |
b105cf4f |
6306 | if (ram_offset!=0) |
c43b5311 |
6307 | SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); |
398d6924 |
6308 | SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n"); |
6309 | SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out); |
57871462 |
6310 | } |
6311 | |
919981d0 |
6312 | void new_dynarec_cleanup(void) |
57871462 |
6313 | { |
6314 | int n; |
2a014d73 |
6315 | #ifdef BASE_ADDR_DYNAMIC |
1e212a25 |
6316 | #ifdef VITA |
66ea165f |
6317 | // sceBlock is managed by retroarch's bootstrap code |
9c67c98f |
6318 | //sceKernelFreeMemBlock(sceBlock); |
6319 | //sceBlock = -1; |
3039c914 |
6320 | #elif defined(HAVE_LIBNX) |
6321 | jitClose(&g_jit); |
6322 | ndrc = NULL; |
1e212a25 |
6323 | #else |
2a014d73 |
6324 | if (munmap(ndrc, sizeof(*ndrc)) < 0) |
1e212a25 |
6325 | SysPrintf("munmap() failed\n"); |
3039c914 |
6326 | ndrc = NULL; |
bdeade46 |
6327 | #endif |
1e212a25 |
6328 | #endif |
93c0345b |
6329 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6330 | blocks_clear(&blocks[n]); |
b7ad2f2c |
6331 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6332 | free(jumps[n]); |
6333 | jumps[n] = NULL; |
6334 | } |
104df9d3 |
6335 | stat_clear(stat_blocks); |
6336 | stat_clear(stat_links); |
ece032e6 |
6337 | new_dynarec_print_stats(); |
57871462 |
6338 | } |
6339 | |
03f55e6b |
6340 | static u_int *get_source_start(u_int addr, u_int *limit) |
57871462 |
6341 | { |
03f55e6b |
6342 | if (addr < 0x00200000 || |
a3203cf4 |
6343 | (0xa0000000 <= addr && addr < 0xa0200000)) |
6344 | { |
03f55e6b |
6345 | // used for BIOS calls mostly? |
6346 | *limit = (addr&0xa0000000)|0x00200000; |
01d26796 |
6347 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b |
6348 | } |
6349 | else if (!Config.HLE && ( |
6350 | /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ |
a3203cf4 |
6351 | (0xbfc00000 <= addr && addr < 0xbfc80000))) |
6352 | { |
6353 | // BIOS. The multiplier should be much higher as it's uncached 8bit mem, |
d5aeda23 |
6354 | // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption |
d62c125a |
6355 | if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) |
24058131 |
6356 | cycle_multiplier_active = 200; |
a3203cf4 |
6357 | |
03f55e6b |
6358 | *limit = (addr & 0xfff00000) | 0x80000; |
01d26796 |
6359 | return (u_int *)((u_char *)psxR + (addr&0x7ffff)); |
03f55e6b |
6360 | } |
6361 | else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) { |
6362 | *limit = (addr & 0x80600000) + 0x00200000; |
01d26796 |
6363 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b |
6364 | } |
581335b0 |
6365 | return NULL; |
03f55e6b |
6366 | } |
6367 | |
6368 | static u_int scan_for_ret(u_int addr) |
6369 | { |
6370 | u_int limit = 0; |
6371 | u_int *mem; |
6372 | |
6373 | mem = get_source_start(addr, &limit); |
6374 | if (mem == NULL) |
6375 | return addr; |
6376 | |
6377 | if (limit > addr + 0x1000) |
6378 | limit = addr + 0x1000; |
6379 | for (; addr < limit; addr += 4, mem++) { |
6380 | if (*mem == 0x03e00008) // jr $ra |
6381 | return addr + 8; |
57871462 |
6382 | } |
581335b0 |
6383 | return addr; |
03f55e6b |
6384 | } |
6385 | |
6386 | struct savestate_block { |
6387 | uint32_t addr; |
6388 | uint32_t regflags; |
6389 | }; |
6390 | |
6391 | static int addr_cmp(const void *p1_, const void *p2_) |
6392 | { |
6393 | const struct savestate_block *p1 = p1_, *p2 = p2_; |
6394 | return p1->addr - p2->addr; |
6395 | } |
6396 | |
6397 | int new_dynarec_save_blocks(void *save, int size) |
6398 | { |
104df9d3 |
6399 | struct savestate_block *sblocks = save; |
6400 | int maxcount = size / sizeof(sblocks[0]); |
03f55e6b |
6401 | struct savestate_block tmp_blocks[1024]; |
104df9d3 |
6402 | struct block_info *block; |
03f55e6b |
6403 | int p, s, d, o, bcnt; |
6404 | u_int addr; |
6405 | |
6406 | o = 0; |
104df9d3 |
6407 | for (p = 0; p < ARRAY_SIZE(blocks); p++) { |
03f55e6b |
6408 | bcnt = 0; |
104df9d3 |
6409 | for (block = blocks[p]; block != NULL; block = block->next) { |
6410 | if (block->is_dirty) |
6411 | continue; |
6412 | tmp_blocks[bcnt].addr = block->start; |
6413 | tmp_blocks[bcnt].regflags = block->reg_sv_flags; |
03f55e6b |
6414 | bcnt++; |
6415 | } |
6416 | if (bcnt < 1) |
6417 | continue; |
6418 | qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); |
6419 | |
6420 | addr = tmp_blocks[0].addr; |
6421 | for (s = d = 0; s < bcnt; s++) { |
6422 | if (tmp_blocks[s].addr < addr) |
6423 | continue; |
6424 | if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) |
6425 | tmp_blocks[d++] = tmp_blocks[s]; |
6426 | addr = scan_for_ret(tmp_blocks[s].addr); |
6427 | } |
6428 | |
6429 | if (o + d > maxcount) |
6430 | d = maxcount - o; |
104df9d3 |
6431 | memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0])); |
03f55e6b |
6432 | o += d; |
6433 | } |
6434 | |
104df9d3 |
6435 | return o * sizeof(sblocks[0]); |
03f55e6b |
6436 | } |
6437 | |
6438 | void new_dynarec_load_blocks(const void *save, int size) |
6439 | { |
104df9d3 |
6440 | const struct savestate_block *sblocks = save; |
6441 | int count = size / sizeof(sblocks[0]); |
6442 | struct block_info *block; |
03f55e6b |
6443 | u_int regs_save[32]; |
104df9d3 |
6444 | u_int page; |
03f55e6b |
6445 | uint32_t f; |
6446 | int i, b; |
6447 | |
104df9d3 |
6448 | // restore clean blocks, if any |
6449 | for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) { |
6450 | for (block = blocks[page]; block != NULL; block = block->next, b++) { |
6451 | if (!block->is_dirty) |
6452 | continue; |
6453 | assert(block->source && block->copy); |
6454 | if (memcmp(block->source, block->copy, block->len)) |
6455 | continue; |
6456 | |
6457 | // see try_restore_block |
6458 | block->is_dirty = 0; |
6459 | mark_invalid_code(block->start, block->len, 0); |
6460 | i++; |
6461 | } |
6462 | } |
6463 | inv_debug("load_blocks: %d/%d clean blocks\n", i, b); |
03f55e6b |
6464 | |
6465 | // change GPRs for speculation to at least partially work.. |
6466 | memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); |
6467 | for (i = 1; i < 32; i++) |
6468 | psxRegs.GPR.r[i] = 0x80000000; |
6469 | |
6470 | for (b = 0; b < count; b++) { |
104df9d3 |
6471 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b |
6472 | if (f & 1) |
6473 | psxRegs.GPR.r[i] = 0x1f800000; |
6474 | } |
6475 | |
104df9d3 |
6476 | ndrc_get_addr_ht(sblocks[b].addr); |
03f55e6b |
6477 | |
104df9d3 |
6478 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b |
6479 | if (f & 1) |
6480 | psxRegs.GPR.r[i] = 0x80000000; |
6481 | } |
6482 | } |
6483 | |
6484 | memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); |
6485 | } |
6486 | |
ece032e6 |
6487 | void new_dynarec_print_stats(void) |
6488 | { |
6489 | #ifdef STAT_PRINT |
104df9d3 |
6490 | printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n", |
ece032e6 |
6491 | stat_bc_pre, stat_bc_direct, stat_bc_restore, |
104df9d3 |
6492 | stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries, |
6493 | stat_restore_compares, stat_inv_addr_calls, stat_inv_hits, |
6494 | out - ndrc->translation_cache, stat_blocks, stat_links); |
ece032e6 |
6495 | stat_bc_direct = stat_bc_pre = stat_bc_restore = |
104df9d3 |
6496 | stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries = |
6497 | stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0; |
ece032e6 |
6498 | #endif |
6499 | } |
6500 | |
7f94b097 |
6501 | static int apply_hacks(void) |
24058131 |
6502 | { |
6503 | int i; |
6504 | if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) |
7f94b097 |
6505 | return 0; |
24058131 |
6506 | /* special hack(s) */ |
6507 | for (i = 0; i < slen - 4; i++) |
6508 | { |
6509 | // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224 |
6510 | if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP |
6511 | && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a |
277718fa |
6512 | && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2) |
24058131 |
6513 | { |
6514 | SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); |
6515 | dops[i + 3].itype = NOP; |
6516 | } |
6517 | } |
6518 | i = slen; |
6519 | if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 |
6520 | && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 |
6521 | && dops[i-7].itype == STORE) |
6522 | { |
6523 | i = i-8; |
6524 | if (dops[i].itype == IMM16) |
6525 | i--; |
6526 | // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 |
6527 | if (dops[i].itype == STORELR && dops[i].rs1 == 6 |
6528 | && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) |
6529 | { |
7f94b097 |
6530 | SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr); |
6531 | f1_hack = 1; |
6532 | return 1; |
24058131 |
6533 | } |
6534 | } |
7f94b097 |
6535 | return 0; |
24058131 |
6536 | } |
6537 | |
de6dbc52 |
6538 | static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op) |
03f55e6b |
6539 | { |
de6dbc52 |
6540 | return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2) |
6541 | && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP; |
6542 | } |
57871462 |
6543 | |
de6dbc52 |
6544 | static void force_intcall(int i) |
6545 | { |
6546 | memset(&dops[i], 0, sizeof(dops[i])); |
6547 | dops[i].itype = INTCALL; |
6548 | dops[i].rs1 = CCREG; |
6549 | dops[i].is_exception = 1; |
6550 | cinfo[i].ba = -1; |
6551 | } |
6552 | |
6553 | static void disassemble_one(int i, u_int src) |
6554 | { |
6555 | unsigned int type, op, op2, op3; |
7ebfcedf |
6556 | memset(&dops[i], 0, sizeof(dops[i])); |
277718fa |
6557 | memset(&cinfo[i], 0, sizeof(cinfo[i])); |
6558 | cinfo[i].ba = -1; |
6559 | cinfo[i].addr = -1; |
de6dbc52 |
6560 | dops[i].opcode = op = src >> 26; |
277718fa |
6561 | op2 = 0; |
a5cd72d0 |
6562 | type = INTCALL; |
6563 | set_mnemonic(i, "???"); |
57871462 |
6564 | switch(op) |
6565 | { |
a5cd72d0 |
6566 | case 0x00: set_mnemonic(i, "special"); |
de6dbc52 |
6567 | op2 = src & 0x3f; |
57871462 |
6568 | switch(op2) |
6569 | { |
53dc27f6 |
6570 | case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; |
6571 | case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break; |
6572 | case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break; |
6573 | case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break; |
6574 | case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break; |
6575 | case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break; |
6576 | case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break; |
6577 | case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; |
6578 | case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; |
6579 | case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; |
53dc27f6 |
6580 | case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; |
6581 | case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; |
6582 | case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; |
6583 | case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break; |
6584 | case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break; |
6585 | case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break; |
6586 | case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break; |
6587 | case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break; |
6588 | case 0x20: set_mnemonic(i, "ADD"); type=ALU; break; |
6589 | case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break; |
6590 | case 0x22: set_mnemonic(i, "SUB"); type=ALU; break; |
6591 | case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break; |
6592 | case 0x24: set_mnemonic(i, "AND"); type=ALU; break; |
6593 | case 0x25: set_mnemonic(i, "OR"); type=ALU; break; |
6594 | case 0x26: set_mnemonic(i, "XOR"); type=ALU; break; |
6595 | case 0x27: set_mnemonic(i, "NOR"); type=ALU; break; |
6596 | case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break; |
6597 | case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break; |
57871462 |
6598 | } |
6599 | break; |
a5cd72d0 |
6600 | case 0x01: set_mnemonic(i, "regimm"); |
6601 | type = SJUMP; |
de6dbc52 |
6602 | op2 = (src >> 16) & 0x1f; |
57871462 |
6603 | switch(op2) |
6604 | { |
a5cd72d0 |
6605 | case 0x10: set_mnemonic(i, "BLTZAL"); break; |
6606 | case 0x11: set_mnemonic(i, "BGEZAL"); break; |
6607 | default: |
6608 | if (op2 & 1) |
6609 | set_mnemonic(i, "BGEZ"); |
6610 | else |
6611 | set_mnemonic(i, "BLTZ"); |
57871462 |
6612 | } |
6613 | break; |
53dc27f6 |
6614 | case 0x02: set_mnemonic(i, "J"); type=UJUMP; break; |
6615 | case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break; |
6616 | case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break; |
6617 | case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break; |
6618 | case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break; |
6619 | case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break; |
6620 | case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break; |
6621 | case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break; |
6622 | case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break; |
6623 | case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break; |
6624 | case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break; |
6625 | case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break; |
6626 | case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; |
6627 | case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; |
a5cd72d0 |
6628 | case 0x10: set_mnemonic(i, "COP0"); |
de6dbc52 |
6629 | op2 = (src >> 21) & 0x1f; |
a5cd72d0 |
6630 | if (op2 & 0x10) { |
de6dbc52 |
6631 | op3 = src & 0x1f; |
a5cd72d0 |
6632 | switch (op3) |
6633 | { |
6634 | case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break; |
6635 | case 0x10: set_mnemonic(i, "RFE"); type=RFE; break; |
6636 | default: type = OTHER; break; |
6637 | } |
6638 | break; |
6639 | } |
57871462 |
6640 | switch(op2) |
6641 | { |
a5cd72d0 |
6642 | u32 rd; |
6643 | case 0x00: |
6644 | set_mnemonic(i, "MFC0"); |
de6dbc52 |
6645 | rd = (src >> 11) & 0x1F; |
a5cd72d0 |
6646 | if (!(0x00000417u & (1u << rd))) |
6647 | type = COP0; |
6648 | break; |
53dc27f6 |
6649 | case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break; |
a5cd72d0 |
6650 | case 0x02: |
6651 | case 0x06: type = INTCALL; break; |
6652 | default: type = OTHER; break; |
57871462 |
6653 | } |
6654 | break; |
a5cd72d0 |
6655 | case 0x11: set_mnemonic(i, "COP1"); |
de6dbc52 |
6656 | op2 = (src >> 21) & 0x1f; |
57871462 |
6657 | break; |
a5cd72d0 |
6658 | case 0x12: set_mnemonic(i, "COP2"); |
de6dbc52 |
6659 | op2 = (src >> 21) & 0x1f; |
a5cd72d0 |
6660 | if (op2 & 0x10) { |
6661 | type = OTHER; |
de6dbc52 |
6662 | if (gte_handlers[src & 0x3f] != NULL) { |
53dc27f6 |
6663 | #ifdef DISASM |
de6dbc52 |
6664 | if (gte_regnames[src & 0x3f] != NULL) |
6665 | strcpy(insn[i], gte_regnames[src & 0x3f]); |
bedfea38 |
6666 | else |
de6dbc52 |
6667 | snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f); |
53dc27f6 |
6668 | #endif |
a5cd72d0 |
6669 | type = C2OP; |
c7abc864 |
6670 | } |
6671 | } |
6672 | else switch(op2) |
b9b61529 |
6673 | { |
53dc27f6 |
6674 | case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break; |
6675 | case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break; |
6676 | case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break; |
6677 | case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break; |
b9b61529 |
6678 | } |
6679 | break; |
a5cd72d0 |
6680 | case 0x13: set_mnemonic(i, "COP3"); |
de6dbc52 |
6681 | op2 = (src >> 21) & 0x1f; |
a5cd72d0 |
6682 | break; |
6683 | case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; |
6684 | case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; |
6685 | case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break; |
6686 | case 0x23: set_mnemonic(i, "LW"); type=LOAD; break; |
6687 | case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break; |
6688 | case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break; |
6689 | case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break; |
6690 | case 0x28: set_mnemonic(i, "SB"); type=STORE; break; |
6691 | case 0x29: set_mnemonic(i, "SH"); type=STORE; break; |
6692 | case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break; |
6693 | case 0x2B: set_mnemonic(i, "SW"); type=STORE; break; |
6694 | case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break; |
53dc27f6 |
6695 | case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; |
6696 | case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; |
a5cd72d0 |
6697 | case 0x3B: |
de6dbc52 |
6698 | if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) { |
a5cd72d0 |
6699 | set_mnemonic(i, "HLECALL"); |
6700 | type = HLECALL; |
6701 | } |
6702 | break; |
6703 | default: |
90ae6d4e |
6704 | break; |
57871462 |
6705 | } |
a5cd72d0 |
6706 | if (type == INTCALL) |
de6dbc52 |
6707 | SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start); |
cf95b4f0 |
6708 | dops[i].itype=type; |
6709 | dops[i].opcode2=op2; |
57871462 |
6710 | /* Get registers/immediates */ |
53dc27f6 |
6711 | dops[i].use_lt1=0; |
bedfea38 |
6712 | gte_rs[i]=gte_rt[i]=0; |
a5cd72d0 |
6713 | dops[i].rs1 = 0; |
6714 | dops[i].rs2 = 0; |
6715 | dops[i].rt1 = 0; |
6716 | dops[i].rt2 = 0; |
57871462 |
6717 | switch(type) { |
6718 | case LOAD: |
de6dbc52 |
6719 | dops[i].rs1 = (src >> 21) & 0x1f; |
6720 | dops[i].rt1 = (src >> 16) & 0x1f; |
6721 | cinfo[i].imm = (short)src; |
57871462 |
6722 | break; |
6723 | case STORE: |
6724 | case STORELR: |
de6dbc52 |
6725 | dops[i].rs1 = (src >> 21) & 0x1f; |
6726 | dops[i].rs2 = (src >> 16) & 0x1f; |
6727 | cinfo[i].imm = (short)src; |
57871462 |
6728 | break; |
6729 | case LOADLR: |
6730 | // LWL/LWR only load part of the register, |
6731 | // therefore the target register must be treated as a source too |
de6dbc52 |
6732 | dops[i].rs1 = (src >> 21) & 0x1f; |
6733 | dops[i].rs2 = (src >> 16) & 0x1f; |
6734 | dops[i].rt1 = (src >> 16) & 0x1f; |
6735 | cinfo[i].imm = (short)src; |
57871462 |
6736 | break; |
6737 | case IMM16: |
cf95b4f0 |
6738 | if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register |
de6dbc52 |
6739 | else dops[i].rs1 = (src >> 21) & 0x1f; |
6740 | dops[i].rs2 = 0; |
6741 | dops[i].rt1 = (src >> 16) & 0x1f; |
57871462 |
6742 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI |
de6dbc52 |
6743 | cinfo[i].imm = (unsigned short)src; |
57871462 |
6744 | }else{ |
de6dbc52 |
6745 | cinfo[i].imm = (short)src; |
57871462 |
6746 | } |
57871462 |
6747 | break; |
6748 | case UJUMP: |
57871462 |
6749 | // The JAL instruction writes to r31. |
6750 | if (op&1) { |
cf95b4f0 |
6751 | dops[i].rt1=31; |
57871462 |
6752 | } |
cf95b4f0 |
6753 | dops[i].rs2=CCREG; |
57871462 |
6754 | break; |
6755 | case RJUMP: |
de6dbc52 |
6756 | dops[i].rs1 = (src >> 21) & 0x1f; |
5067f341 |
6757 | // The JALR instruction writes to rd. |
57871462 |
6758 | if (op2&1) { |
de6dbc52 |
6759 | dops[i].rt1 = (src >> 11) & 0x1f; |
57871462 |
6760 | } |
cf95b4f0 |
6761 | dops[i].rs2=CCREG; |
57871462 |
6762 | break; |
6763 | case CJUMP: |
de6dbc52 |
6764 | dops[i].rs1 = (src >> 21) & 0x1f; |
6765 | dops[i].rs2 = (src >> 16) & 0x1f; |
57871462 |
6766 | if(op&2) { // BGTZ/BLEZ |
cf95b4f0 |
6767 | dops[i].rs2=0; |
57871462 |
6768 | } |
57871462 |
6769 | break; |
6770 | case SJUMP: |
de6dbc52 |
6771 | dops[i].rs1 = (src >> 21) & 0x1f; |
6772 | dops[i].rs2 = CCREG; |
a5cd72d0 |
6773 | if (op2 == 0x10 || op2 == 0x11) { // BxxAL |
6774 | dops[i].rt1 = 31; |
57871462 |
6775 | // NOTE: If the branch is not taken, r31 is still overwritten |
6776 | } |
57871462 |
6777 | break; |
57871462 |
6778 | case ALU: |
de6dbc52 |
6779 | dops[i].rs1=(src>>21)&0x1f; // source |
6780 | dops[i].rs2=(src>>16)&0x1f; // subtract amount |
6781 | dops[i].rt1=(src>>11)&0x1f; // destination |
57871462 |
6782 | break; |
6783 | case MULTDIV: |
de6dbc52 |
6784 | dops[i].rs1=(src>>21)&0x1f; // source |
6785 | dops[i].rs2=(src>>16)&0x1f; // divisor |
cf95b4f0 |
6786 | dops[i].rt1=HIREG; |
6787 | dops[i].rt2=LOREG; |
57871462 |
6788 | break; |
6789 | case MOV: |
cf95b4f0 |
6790 | if(op2==0x10) dops[i].rs1=HIREG; // MFHI |
6791 | if(op2==0x11) dops[i].rt1=HIREG; // MTHI |
6792 | if(op2==0x12) dops[i].rs1=LOREG; // MFLO |
6793 | if(op2==0x13) dops[i].rt1=LOREG; // MTLO |
de6dbc52 |
6794 | if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx |
6795 | if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx |
57871462 |
6796 | break; |
6797 | case SHIFT: |
de6dbc52 |
6798 | dops[i].rs1=(src>>16)&0x1f; // target of shift |
6799 | dops[i].rs2=(src>>21)&0x1f; // shift amount |
6800 | dops[i].rt1=(src>>11)&0x1f; // destination |
57871462 |
6801 | break; |
6802 | case SHIFTIMM: |
de6dbc52 |
6803 | dops[i].rs1=(src>>16)&0x1f; |
cf95b4f0 |
6804 | dops[i].rs2=0; |
de6dbc52 |
6805 | dops[i].rt1=(src>>11)&0x1f; |
6806 | cinfo[i].imm=(src>>6)&0x1f; |
57871462 |
6807 | break; |
6808 | case COP0: |
de6dbc52 |
6809 | if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0 |
6810 | if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0 |
6811 | if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG; |
57871462 |
6812 | break; |
bedfea38 |
6813 | case COP2: |
de6dbc52 |
6814 | if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2 |
6815 | if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2 |
6816 | int gr=(src>>11)&0x1F; |
bedfea38 |
6817 | switch(op2) |
6818 | { |
6819 | case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2 |
6820 | case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2 |
0ff8c62c |
6821 | case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2 |
bedfea38 |
6822 | case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2 |
6823 | } |
6824 | break; |
b9b61529 |
6825 | case C2LS: |
de6dbc52 |
6826 | dops[i].rs1=(src>>21)&0x1F; |
6827 | cinfo[i].imm=(short)src; |
6828 | if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2 |
6829 | else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2 |
bedfea38 |
6830 | break; |
6831 | case C2OP: |
de6dbc52 |
6832 | gte_rs[i]=gte_reg_reads[src&0x3f]; |
6833 | gte_rt[i]=gte_reg_writes[src&0x3f]; |
2167bef6 |
6834 | gte_rt[i]|=1ll<<63; // every op changes flags |
de6dbc52 |
6835 | if((src&0x3f)==GTE_MVMVA) { |
6836 | int v = (src >> 15) & 3; |
587a5b1c |
6837 | gte_rs[i]&=~0xe3fll; |
6838 | if(v==3) gte_rs[i]|=0xe00ll; |
6839 | else gte_rs[i]|=3ll<<(v*2); |
6840 | } |
b9b61529 |
6841 | break; |
57871462 |
6842 | case SYSCALL: |
7139f3c8 |
6843 | case HLECALL: |
1e973cb0 |
6844 | case INTCALL: |
cf95b4f0 |
6845 | dops[i].rs1=CCREG; |
57871462 |
6846 | break; |
6847 | default: |
a5cd72d0 |
6848 | break; |
57871462 |
6849 | } |
de6dbc52 |
6850 | } |
6851 | |
6852 | static noinline void pass1_disassemble(u_int pagelimit) |
6853 | { |
6854 | int i, j, done = 0, ni_count = 0; |
6855 | |
6856 | for (i = 0; !done; i++) |
6857 | { |
6858 | int force_j_to_interpreter = 0; |
6859 | unsigned int type, op, op2; |
6860 | |
6861 | disassemble_one(i, source[i]); |
6862 | type = dops[i].itype; |
6863 | op = dops[i].opcode; |
6864 | op2 = dops[i].opcode2; |
6865 | |
57871462 |
6866 | /* Calculate branch target addresses */ |
6867 | if(type==UJUMP) |
277718fa |
6868 | cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); |
cf95b4f0 |
6869 | else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1)) |
277718fa |
6870 | cinfo[i].ba=start+i*4+8; // Ignore never taken branch |
cf95b4f0 |
6871 | else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1)) |
277718fa |
6872 | cinfo[i].ba=start+i*4+8; // Ignore never taken branch |
ad49de89 |
6873 | else if(type==CJUMP||type==SJUMP) |
277718fa |
6874 | cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); |
4919de1e |
6875 | |
6876 | /* simplify always (not)taken branches */ |
cf95b4f0 |
6877 | if (type == CJUMP && dops[i].rs1 == dops[i].rs2) { |
6878 | dops[i].rs1 = dops[i].rs2 = 0; |
4919de1e |
6879 | if (!(op & 1)) { |
cf95b4f0 |
6880 | dops[i].itype = type = UJUMP; |
6881 | dops[i].rs2 = CCREG; |
4919de1e |
6882 | } |
6883 | } |
cf95b4f0 |
6884 | else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) |
6885 | dops[i].itype = type = UJUMP; |
4919de1e |
6886 | |
277718fa |
6887 | dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP; |
6888 | dops[i].is_ujump = type == RJUMP || type == UJUMP; |
6889 | dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2 |
a5cd72d0 |
6890 | dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC |
277718fa |
6891 | dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2 |
6892 | dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL; |
6893 | dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8; |
6894 | |
6895 | if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU |
6896 | && ((cinfo[i].imm & 1) || Config.PreciseExceptions)) |
6897 | dops[i].may_except = 1; |
6898 | if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2 |
6899 | && ((cinfo[i].imm & 3) || Config.PreciseExceptions)) |
6900 | dops[i].may_except = 1; |
fe807a8a |
6901 | |
a5cd72d0 |
6902 | /* rare messy cases to just pass over to the interpreter */ |
fe807a8a |
6903 | if (i > 0 && dops[i-1].is_jump) { |
ecca05e3 |
6904 | j = i - 1; |
3e535354 |
6905 | // branch in delay slot? |
fe807a8a |
6906 | if (dops[i].is_jump) { |
3e535354 |
6907 | // don't handle first branch and call interpreter if it's hit |
a5cd72d0 |
6908 | SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start); |
ecca05e3 |
6909 | force_j_to_interpreter = 1; |
3e535354 |
6910 | } |
de6dbc52 |
6911 | // load delay detection through a branch |
a5cd72d0 |
6912 | else if (dops[i].is_delay_load && dops[i].rt1 != 0) { |
de6dbc52 |
6913 | const struct decoded_insn *dop = NULL; |
6914 | int t = -1; |
6915 | if (cinfo[i-1].ba != -1) { |
6916 | t = (cinfo[i-1].ba - start) / 4; |
6917 | if (t < 0 || t > i) { |
6918 | u_int limit = 0; |
6919 | u_int *mem = get_source_start(cinfo[i-1].ba, &limit); |
6920 | if (mem != NULL) { |
6921 | disassemble_one(MAXBLOCK - 1, mem[0]); |
6922 | dop = &dops[MAXBLOCK - 1]; |
6923 | } |
6924 | } |
6925 | else |
6926 | dop = &dops[t]; |
6927 | } |
6928 | if ((dop && is_ld_use_hazard(dops[i].rt1, dop)) |
6929 | || (!dop && Config.PreciseExceptions)) { |
3e535354 |
6930 | // jump target wants DS result - potential load delay effect |
a5cd72d0 |
6931 | SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start); |
ecca05e3 |
6932 | force_j_to_interpreter = 1; |
de6dbc52 |
6933 | if (0 <= t && t < i) |
6934 | dops[t + 1].bt = 1; // expected return from interpreter |
3e535354 |
6935 | } |
cf95b4f0 |
6936 | else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& |
fe807a8a |
6937 | !(i>=3&&dops[i-3].is_jump)) { |
3e535354 |
6938 | // v0 overwrite like this is a sign of trouble, bail out |
4149788d |
6939 | SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start); |
ecca05e3 |
6940 | force_j_to_interpreter = 1; |
3e535354 |
6941 | } |
6942 | } |
a5cd72d0 |
6943 | } |
de6dbc52 |
6944 | else if (i > 0 && dops[i-1].is_delay_load |
6945 | && is_ld_use_hazard(dops[i-1].rt1, &dops[i]) |
6946 | && (i < 2 || !dops[i-2].is_ujump)) { |
a5cd72d0 |
6947 | SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); |
ecca05e3 |
6948 | for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--) |
6949 | if (dops[j-1].rt1 != dops[i-1].rt1) |
6950 | break; |
6951 | force_j_to_interpreter = 1; |
a5cd72d0 |
6952 | } |
ecca05e3 |
6953 | if (force_j_to_interpreter) { |
de6dbc52 |
6954 | force_intcall(j); |
a5cd72d0 |
6955 | done = 2; |
ecca05e3 |
6956 | i = j; // don't compile the problematic branch/load/etc |
3e535354 |
6957 | } |
de6dbc52 |
6958 | if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) { |
6959 | SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start); |
6960 | i--; |
6961 | force_intcall(i); |
6962 | done = 2; |
6963 | } |
6964 | if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12 |
6965 | dops[i].bt = 1; |
6966 | if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13 |
6967 | dops[i].bt = 1; |
4919de1e |
6968 | |
3e535354 |
6969 | /* Is this the end of the block? */ |
fe807a8a |
6970 | if (i > 0 && dops[i-1].is_ujump) { |
0787af86 |
6971 | if (dops[i-1].rt1 == 0) { // not jal |
277718fa |
6972 | int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4; |
0787af86 |
6973 | if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) { |
6974 | // scan for a branch back to i+1 |
6975 | for (j = t; j < t + 64; j++) { |
6976 | int tmpop = source[j] >> 26; |
6977 | if (tmpop == 1 || ((tmpop & ~3) == 4)) { |
6978 | int t2 = j + 1 + (int)(signed short)source[j]; |
6979 | if (t2 == i + 1) { |
6980 | //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4); |
6981 | found_bbranch = 1; |
6982 | break; |
6983 | } |
6984 | } |
6985 | } |
6986 | } |
6987 | if (!found_bbranch) |
6988 | done = 2; |
57871462 |
6989 | } |
6990 | else { |
6991 | if(stop_after_jal) done=1; |
6992 | // Stop on BREAK |
6993 | if((source[i+1]&0xfc00003f)==0x0d) done=1; |
6994 | } |
6995 | // Don't recompile stuff that's already compiled |
6996 | if(check_addr(start+i*4+4)) done=1; |
6997 | // Don't get too close to the limit |
6998 | if(i>MAXBLOCK/2) done=1; |
6999 | } |
a5cd72d0 |
7000 | if (dops[i].itype == HLECALL) |
7001 | stop = 1; |
7002 | else if (dops[i].itype == INTCALL) |
7003 | stop = 2; |
7004 | else if (dops[i].is_exception) |
d1150cd6 |
7005 | done = stop_after_jal ? 1 : 2; |
7006 | if (done == 2) { |
1e973cb0 |
7007 | // Does the block continue due to a branch? |
7008 | for(j=i-1;j>=0;j--) |
7009 | { |
277718fa |
7010 | if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot |
7011 | if(cinfo[j].ba==start+i*4+4) done=j=0; |
7012 | if(cinfo[j].ba==start+i*4+8) done=j=0; |
1e973cb0 |
7013 | } |
7014 | } |
75dec299 |
7015 | //assert(i<MAXBLOCK-1); |
57871462 |
7016 | if(start+i*4==pagelimit-4) done=1; |
7017 | assert(start+i*4<pagelimit); |
7018 | if (i==MAXBLOCK-1) done=1; |
7019 | // Stop if we're compiling junk |
a5cd72d0 |
7020 | if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) { |
57871462 |
7021 | done=stop_after_jal=1; |
c43b5311 |
7022 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 |
7023 | } |
7024 | } |
4bdc30ab |
7025 | while (i > 0 && dops[i-1].is_jump) |
7026 | i--; |
7027 | assert(i > 0); |
7028 | assert(!dops[i-1].is_jump); |
7029 | slen = i; |
4149788d |
7030 | } |
7031 | |
7032 | // Basic liveness analysis for MIPS registers |
7033 | static noinline void pass2_unneeded_regs(int istart,int iend,int r) |
7034 | { |
7035 | int i; |
7036 | uint64_t u,gte_u,b,gte_b; |
7037 | uint64_t temp_u,temp_gte_u=0; |
7038 | uint64_t gte_u_unknown=0; |
7039 | if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) |
7040 | gte_u_unknown=~0ll; |
7041 | if(iend==slen-1) { |
7042 | u=1; |
7043 | gte_u=gte_u_unknown; |
7044 | }else{ |
7045 | //u=unneeded_reg[iend+1]; |
7046 | u=1; |
7047 | gte_u=gte_unneeded[iend+1]; |
7048 | } |
7049 | |
7050 | for (i=iend;i>=istart;i--) |
7051 | { |
7052 | //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); |
7053 | if(dops[i].is_jump) |
7054 | { |
7055 | // If subroutine call, flag return address as a possible branch target |
7056 | if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1; |
7057 | |
277718fa |
7058 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
4149788d |
7059 | { |
7060 | // Branch out of this block, flush all regs |
7061 | u=1; |
7062 | gte_u=gte_u_unknown; |
7063 | branch_unneeded_reg[i]=u; |
7064 | // Merge in delay slot |
7065 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
7066 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7067 | u|=1; |
7068 | gte_u|=gte_rt[i+1]; |
7069 | gte_u&=~gte_rs[i+1]; |
7070 | } |
7071 | else |
7072 | { |
7073 | // Internal branch, flag target |
277718fa |
7074 | dops[(cinfo[i].ba-start)>>2].bt=1; |
7075 | if(cinfo[i].ba<=start+i*4) { |
4149788d |
7076 | // Backward branch |
7077 | if(dops[i].is_ujump) |
7078 | { |
7079 | // Unconditional branch |
7080 | temp_u=1; |
7081 | temp_gte_u=0; |
7082 | } else { |
7083 | // Conditional branch (not taken case) |
7084 | temp_u=unneeded_reg[i+2]; |
7085 | temp_gte_u&=gte_unneeded[i+2]; |
7086 | } |
7087 | // Merge in delay slot |
7088 | temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
7089 | temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7090 | temp_u|=1; |
7091 | temp_gte_u|=gte_rt[i+1]; |
7092 | temp_gte_u&=~gte_rs[i+1]; |
7093 | temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2); |
7094 | temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
7095 | temp_u|=1; |
7096 | temp_gte_u|=gte_rt[i]; |
7097 | temp_gte_u&=~gte_rs[i]; |
7098 | unneeded_reg[i]=temp_u; |
7099 | gte_unneeded[i]=temp_gte_u; |
7100 | // Only go three levels deep. This recursion can take an |
7101 | // excessive amount of time if there are a lot of nested loops. |
7102 | if(r<2) { |
277718fa |
7103 | pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1); |
4149788d |
7104 | }else{ |
277718fa |
7105 | unneeded_reg[(cinfo[i].ba-start)>>2]=1; |
7106 | gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown; |
4149788d |
7107 | } |
7108 | } /*else*/ if(1) { |
7109 | if (dops[i].is_ujump) |
7110 | { |
7111 | // Unconditional branch |
277718fa |
7112 | u=unneeded_reg[(cinfo[i].ba-start)>>2]; |
7113 | gte_u=gte_unneeded[(cinfo[i].ba-start)>>2]; |
4149788d |
7114 | branch_unneeded_reg[i]=u; |
7115 | // Merge in delay slot |
7116 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
7117 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7118 | u|=1; |
7119 | gte_u|=gte_rt[i+1]; |
7120 | gte_u&=~gte_rs[i+1]; |
7121 | } else { |
7122 | // Conditional branch |
277718fa |
7123 | b=unneeded_reg[(cinfo[i].ba-start)>>2]; |
7124 | gte_b=gte_unneeded[(cinfo[i].ba-start)>>2]; |
4149788d |
7125 | branch_unneeded_reg[i]=b; |
7126 | // Branch delay slot |
7127 | b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); |
7128 | b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7129 | b|=1; |
7130 | gte_b|=gte_rt[i+1]; |
7131 | gte_b&=~gte_rs[i+1]; |
7132 | u&=b; |
7133 | gte_u&=gte_b; |
7134 | if(i<slen-1) { |
7135 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; |
7136 | } else { |
7137 | branch_unneeded_reg[i]=1; |
7138 | } |
7139 | } |
7140 | } |
7141 | } |
7142 | } |
4149788d |
7143 | //u=1; // DEBUG |
7144 | // Written registers are unneeded |
7145 | u|=1LL<<dops[i].rt1; |
7146 | u|=1LL<<dops[i].rt2; |
7147 | gte_u|=gte_rt[i]; |
7148 | // Accessed registers are needed |
7149 | u&=~(1LL<<dops[i].rs1); |
7150 | u&=~(1LL<<dops[i].rs2); |
7151 | gte_u&=~gte_rs[i]; |
7152 | if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1))) |
7153 | gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded |
90f98e7c |
7154 | if (dops[i].may_except || dops[i].itype == RFE) |
7155 | { |
7156 | // SYSCALL instruction, etc or conditional exception |
7157 | u=1; |
7158 | } |
4149788d |
7159 | // Source-target dependencies |
7160 | // R0 is always unneeded |
7161 | u|=1; |
7162 | // Save it |
7163 | unneeded_reg[i]=u; |
7164 | gte_unneeded[i]=gte_u; |
7165 | /* |
7166 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); |
7167 | printf("U:"); |
7168 | int r; |
7169 | for(r=1;r<=CCREG;r++) { |
7170 | if((unneeded_reg[i]>>r)&1) { |
7171 | if(r==HIREG) printf(" HI"); |
7172 | else if(r==LOREG) printf(" LO"); |
7173 | else printf(" r%d",r); |
7174 | } |
7175 | } |
7176 | printf("\n"); |
7177 | */ |
7178 | } |
7179 | } |
57871462 |
7180 | |
4149788d |
7181 | static noinline void pass3_register_alloc(u_int addr) |
7182 | { |
57871462 |
7183 | struct regstat current; // Current register allocations/status |
6cc8d23c |
7184 | clear_all_regs(current.regmap_entry); |
57871462 |
7185 | clear_all_regs(current.regmap); |
6cc8d23c |
7186 | current.wasdirty = current.dirty = 0; |
7187 | current.u = unneeded_reg[0]; |
7188 | alloc_reg(¤t, 0, CCREG); |
7189 | dirty_reg(¤t, CCREG); |
7190 | current.wasconst = 0; |
7191 | current.isconst = 0; |
7192 | current.loadedconst = 0; |
90f98e7c |
7193 | current.noevict = 0; |
9b495f6e |
7194 | //current.waswritten = 0; |
57871462 |
7195 | int ds=0; |
7196 | int cc=0; |
4149788d |
7197 | int hr; |
7198 | int i, j; |
6ebf4adf |
7199 | |
4149788d |
7200 | if (addr & 1) { |
57871462 |
7201 | // First instruction is delay slot |
7202 | cc=-1; |
cf95b4f0 |
7203 | dops[1].bt=1; |
57871462 |
7204 | ds=1; |
7205 | unneeded_reg[0]=1; |
57871462 |
7206 | current.regmap[HOST_BTREG]=BTREG; |
7207 | } |
9f51b4b9 |
7208 | |
57871462 |
7209 | for(i=0;i<slen;i++) |
7210 | { |
cf95b4f0 |
7211 | if(dops[i].bt) |
57871462 |
7212 | { |
57871462 |
7213 | for(hr=0;hr<HOST_REGS;hr++) |
7214 | { |
7215 | // Is this really necessary? |
7216 | if(current.regmap[hr]==0) current.regmap[hr]=-1; |
7217 | } |
7218 | current.isconst=0; |
9b495f6e |
7219 | //current.waswritten=0; |
57871462 |
7220 | } |
24385cae |
7221 | |
57871462 |
7222 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
7223 | regs[i].wasconst=current.isconst; |
57871462 |
7224 | regs[i].wasdirty=current.dirty; |
6cc8d23c |
7225 | regs[i].dirty=0; |
7226 | regs[i].u=0; |
7227 | regs[i].isconst=0; |
8575a877 |
7228 | regs[i].loadedconst=0; |
fe807a8a |
7229 | if (!dops[i].is_jump) { |
57871462 |
7230 | if(i+1<slen) { |
cf95b4f0 |
7231 | current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7232 | current.u|=1; |
57871462 |
7233 | } else { |
7234 | current.u=1; |
57871462 |
7235 | } |
7236 | } else { |
7237 | if(i+1<slen) { |
cf95b4f0 |
7238 | current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7239 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7240 | current.u|=1; |
7ebfcedf |
7241 | } else { |
7242 | SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4); |
7243 | abort(); |
7244 | } |
57871462 |
7245 | } |
cf95b4f0 |
7246 | dops[i].is_ds=ds; |
57871462 |
7247 | if(ds) { |
7248 | ds=0; // Skip delay slot, already allocated as part of branch |
7249 | // ...but we need to alloc it in case something jumps here |
7250 | if(i+1<slen) { |
7251 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; |
57871462 |
7252 | }else{ |
7253 | current.u=branch_unneeded_reg[i-1]; |
57871462 |
7254 | } |
cf95b4f0 |
7255 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7256 | current.u|=1; |
57871462 |
7257 | struct regstat temp; |
7258 | memcpy(&temp,¤t,sizeof(current)); |
7259 | temp.wasdirty=temp.dirty; |
57871462 |
7260 | // TODO: Take into account unconditional branches, as below |
7261 | delayslot_alloc(&temp,i); |
7262 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); |
7263 | regs[i].wasdirty=temp.wasdirty; |
57871462 |
7264 | regs[i].dirty=temp.dirty; |
57871462 |
7265 | regs[i].isconst=0; |
7266 | regs[i].wasconst=0; |
7267 | current.isconst=0; |
7268 | // Create entry (branch target) regmap |
7269 | for(hr=0;hr<HOST_REGS;hr++) |
7270 | { |
7271 | int r=temp.regmap[hr]; |
7272 | if(r>=0) { |
7273 | if(r!=regmap_pre[i][hr]) { |
7274 | regs[i].regmap_entry[hr]=-1; |
7275 | } |
7276 | else |
7277 | { |
7c3a5182 |
7278 | assert(r < 64); |
57871462 |
7279 | if((current.u>>r)&1) { |
7280 | regs[i].regmap_entry[hr]=-1; |
7281 | regs[i].regmap[hr]=-1; |
7282 | //Don't clear regs in the delay slot as the branch might need them |
7283 | //current.regmap[hr]=-1; |
7284 | }else |
7285 | regs[i].regmap_entry[hr]=r; |
57871462 |
7286 | } |
7287 | } else { |
7288 | // First instruction expects CCREG to be allocated |
9f51b4b9 |
7289 | if(i==0&&hr==HOST_CCREG) |
57871462 |
7290 | regs[i].regmap_entry[hr]=CCREG; |
7291 | else |
7292 | regs[i].regmap_entry[hr]=-1; |
7293 | } |
7294 | } |
7295 | } |
7296 | else { // Not delay slot |
90f98e7c |
7297 | current.noevict = 0; |
cf95b4f0 |
7298 | switch(dops[i].itype) { |
57871462 |
7299 | case UJUMP: |
7300 | //current.isconst=0; // DEBUG |
7301 | //current.wasconst=0; // DEBUG |
7302 | //regs[i].wasconst=0; // DEBUG |
cf95b4f0 |
7303 | clear_const(¤t,dops[i].rt1); |
57871462 |
7304 | alloc_cc(¤t,i); |
7305 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7306 | if (dops[i].rt1==31) { |
57871462 |
7307 | alloc_reg(¤t,i,31); |
7308 | dirty_reg(¤t,31); |
cf95b4f0 |
7309 | //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31); |
7310 | //assert(dops[i+1].rt1!=dops[i].rt1); |
57871462 |
7311 | #ifdef REG_PREFETCH |
7312 | alloc_reg(¤t,i,PTEMP); |
7313 | #endif |
57871462 |
7314 | } |
cf95b4f0 |
7315 | dops[i].ooo=1; |
269bb29a |
7316 | delayslot_alloc(¤t,i+1); |
57871462 |
7317 | //current.isconst=0; // DEBUG |
7318 | ds=1; |
57871462 |
7319 | break; |
7320 | case RJUMP: |
7321 | //current.isconst=0; |
7322 | //current.wasconst=0; |
7323 | //regs[i].wasconst=0; |
cf95b4f0 |
7324 | clear_const(¤t,dops[i].rs1); |
7325 | clear_const(¤t,dops[i].rt1); |
57871462 |
7326 | alloc_cc(¤t,i); |
7327 | dirty_reg(¤t,CCREG); |
4919de1e |
7328 | if (!ds_writes_rjump_rs(i)) { |
cf95b4f0 |
7329 | alloc_reg(¤t,i,dops[i].rs1); |
7330 | if (dops[i].rt1!=0) { |
7331 | alloc_reg(¤t,i,dops[i].rt1); |
7332 | dirty_reg(¤t,dops[i].rt1); |
57871462 |
7333 | #ifdef REG_PREFETCH |
7334 | alloc_reg(¤t,i,PTEMP); |
7335 | #endif |
7336 | } |
7337 | #ifdef USE_MINI_HT |
cf95b4f0 |
7338 | if(dops[i].rs1==31) { // JALR |
57871462 |
7339 | alloc_reg(¤t,i,RHASH); |
57871462 |
7340 | alloc_reg(¤t,i,RHTBL); |
57871462 |
7341 | } |
7342 | #endif |
7343 | delayslot_alloc(¤t,i+1); |
7344 | } else { |
7345 | // The delay slot overwrites our source register, |
7346 | // allocate a temporary register to hold the old value. |
7347 | current.isconst=0; |
7348 | current.wasconst=0; |
7349 | regs[i].wasconst=0; |
7350 | delayslot_alloc(¤t,i+1); |
7351 | current.isconst=0; |
7352 | alloc_reg(¤t,i,RTEMP); |
7353 | } |
7354 | //current.isconst=0; // DEBUG |
cf95b4f0 |
7355 | dops[i].ooo=1; |
57871462 |
7356 | ds=1; |
7357 | break; |
7358 | case CJUMP: |
7359 | //current.isconst=0; |
7360 | //current.wasconst=0; |
7361 | //regs[i].wasconst=0; |
cf95b4f0 |
7362 | clear_const(¤t,dops[i].rs1); |
7363 | clear_const(¤t,dops[i].rs2); |
7364 | if((dops[i].opcode&0x3E)==4) // BEQ/BNE |
57871462 |
7365 | { |
7366 | alloc_cc(¤t,i); |
7367 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7368 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7369 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); |
7370 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))|| |
7371 | (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) { |
57871462 |
7372 | // The delay slot overwrites one of our conditions. |
7373 | // Allocate the branch condition registers instead. |
57871462 |
7374 | current.isconst=0; |
7375 | current.wasconst=0; |
7376 | regs[i].wasconst=0; |
cf95b4f0 |
7377 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7378 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); |
57871462 |
7379 | } |
e1190b87 |
7380 | else |
7381 | { |
cf95b4f0 |
7382 | dops[i].ooo=1; |
e1190b87 |
7383 | delayslot_alloc(¤t,i+1); |
7384 | } |
57871462 |
7385 | } |
7386 | else |
cf95b4f0 |
7387 | if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 |
7388 | { |
7389 | alloc_cc(¤t,i); |
7390 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7391 | alloc_reg(¤t,i,dops[i].rs1); |
7392 | if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) { |
57871462 |
7393 | // The delay slot overwrites one of our conditions. |
7394 | // Allocate the branch condition registers instead. |
57871462 |
7395 | current.isconst=0; |
7396 | current.wasconst=0; |
7397 | regs[i].wasconst=0; |
cf95b4f0 |
7398 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 |
7399 | } |
e1190b87 |
7400 | else |
7401 | { |
cf95b4f0 |
7402 | dops[i].ooo=1; |
e1190b87 |
7403 | delayslot_alloc(¤t,i+1); |
7404 | } |
57871462 |
7405 | } |
7406 | else |
7407 | // Don't alloc the delay slot yet because we might not execute it |
cf95b4f0 |
7408 | if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 |
7409 | { |
7410 | current.isconst=0; |
7411 | current.wasconst=0; |
7412 | regs[i].wasconst=0; |
7413 | alloc_cc(¤t,i); |
7414 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7415 | alloc_reg(¤t,i,dops[i].rs1); |
7416 | alloc_reg(¤t,i,dops[i].rs2); |
57871462 |
7417 | } |
7418 | else |
cf95b4f0 |
7419 | if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 |
7420 | { |
7421 | current.isconst=0; |
7422 | current.wasconst=0; |
7423 | regs[i].wasconst=0; |
7424 | alloc_cc(¤t,i); |
7425 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7426 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 |
7427 | } |
7428 | ds=1; |
7429 | //current.isconst=0; |
7430 | break; |
7431 | case SJUMP: |
cf95b4f0 |
7432 | clear_const(¤t,dops[i].rs1); |
7433 | clear_const(¤t,dops[i].rt1); |
57871462 |
7434 | { |
7435 | alloc_cc(¤t,i); |
7436 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7437 | alloc_reg(¤t,i,dops[i].rs1); |
ecca05e3 |
7438 | if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL |
57871462 |
7439 | alloc_reg(¤t,i,31); |
7440 | dirty_reg(¤t,31); |
57871462 |
7441 | } |
ecca05e3 |
7442 | if ((dops[i].rs1 && |
7443 | (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition. |
7444 | ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition |
cf95b4f0 |
7445 | ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra |
57871462 |
7446 | // Allocate the branch condition registers instead. |
57871462 |
7447 | current.isconst=0; |
7448 | current.wasconst=0; |
7449 | regs[i].wasconst=0; |
cf95b4f0 |
7450 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 |
7451 | } |
e1190b87 |
7452 | else |
7453 | { |
cf95b4f0 |
7454 | dops[i].ooo=1; |
e1190b87 |
7455 | delayslot_alloc(¤t,i+1); |
7456 | } |
57871462 |
7457 | } |
57871462 |
7458 | ds=1; |
7459 | //current.isconst=0; |
7460 | break; |
57871462 |
7461 | case IMM16: |
7462 | imm16_alloc(¤t,i); |
7463 | break; |
7464 | case LOAD: |
7465 | case LOADLR: |
7466 | load_alloc(¤t,i); |
7467 | break; |
7468 | case STORE: |
7469 | case STORELR: |
7470 | store_alloc(¤t,i); |
7471 | break; |
7472 | case ALU: |
7473 | alu_alloc(¤t,i); |
7474 | break; |
7475 | case SHIFT: |
7476 | shift_alloc(¤t,i); |
7477 | break; |
7478 | case MULTDIV: |
7479 | multdiv_alloc(¤t,i); |
7480 | break; |
7481 | case SHIFTIMM: |
7482 | shiftimm_alloc(¤t,i); |
7483 | break; |
7484 | case MOV: |
7485 | mov_alloc(¤t,i); |
7486 | break; |
7487 | case COP0: |
7488 | cop0_alloc(¤t,i); |
7489 | break; |
a5cd72d0 |
7490 | case RFE: |
7491 | rfe_alloc(¤t,i); |
81dbbf4c |
7492 | break; |
b9b61529 |
7493 | case COP2: |
81dbbf4c |
7494 | cop2_alloc(¤t,i); |
57871462 |
7495 | break; |
b9b61529 |
7496 | case C2LS: |
7497 | c2ls_alloc(¤t,i); |
7498 | break; |
7499 | case C2OP: |
7500 | c2op_alloc(¤t,i); |
7501 | break; |
57871462 |
7502 | case SYSCALL: |
7139f3c8 |
7503 | case HLECALL: |
1e973cb0 |
7504 | case INTCALL: |
57871462 |
7505 | syscall_alloc(¤t,i); |
7506 | break; |
57871462 |
7507 | } |
9f51b4b9 |
7508 | |
57871462 |
7509 | // Create entry (branch target) regmap |
7510 | for(hr=0;hr<HOST_REGS;hr++) |
7511 | { |
581335b0 |
7512 | int r,or; |
57871462 |
7513 | r=current.regmap[hr]; |
7514 | if(r>=0) { |
7515 | if(r!=regmap_pre[i][hr]) { |
7516 | // TODO: delay slot (?) |
7517 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register |
9de8a0c3 |
7518 | if(or<0||r>=TEMPREG){ |
57871462 |
7519 | regs[i].regmap_entry[hr]=-1; |
7520 | } |
7521 | else |
7522 | { |
7523 | // Just move it to a different register |
7524 | regs[i].regmap_entry[hr]=r; |
7525 | // If it was dirty before, it's still dirty |
9de8a0c3 |
7526 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); |
57871462 |
7527 | } |
7528 | } |
7529 | else |
7530 | { |
7531 | // Unneeded |
7532 | if(r==0){ |
7533 | regs[i].regmap_entry[hr]=0; |
7534 | } |
7535 | else |
7c3a5182 |
7536 | { |
7537 | assert(r<64); |
57871462 |
7538 | if((current.u>>r)&1) { |
7539 | regs[i].regmap_entry[hr]=-1; |
7540 | //regs[i].regmap[hr]=-1; |
7541 | current.regmap[hr]=-1; |
7542 | }else |
7543 | regs[i].regmap_entry[hr]=r; |
7544 | } |
57871462 |
7545 | } |
7546 | } else { |
7547 | // Branches expect CCREG to be allocated at the target |
9f51b4b9 |
7548 | if(regmap_pre[i][hr]==CCREG) |
57871462 |
7549 | regs[i].regmap_entry[hr]=CCREG; |
7550 | else |
7551 | regs[i].regmap_entry[hr]=-1; |
7552 | } |
7553 | } |
7554 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); |
7555 | } |
27727b63 |
7556 | |
9b495f6e |
7557 | #if 0 // see do_store_smc_check() |
277718fa |
7558 | if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800) |
cf95b4f0 |
7559 | current.waswritten|=1<<dops[i-1].rs1; |
7560 | current.waswritten&=~(1<<dops[i].rt1); |
7561 | current.waswritten&=~(1<<dops[i].rt2); |
277718fa |
7562 | if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800) |
cf95b4f0 |
7563 | current.waswritten&=~(1<<dops[i].rs1); |
9b495f6e |
7564 | #endif |
27727b63 |
7565 | |
57871462 |
7566 | /* Branch post-alloc */ |
7567 | if(i>0) |
7568 | { |
57871462 |
7569 | current.wasdirty=current.dirty; |
cf95b4f0 |
7570 | switch(dops[i-1].itype) { |
57871462 |
7571 | case UJUMP: |
7572 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
7573 | branch_regs[i-1].isconst=0; |
7574 | branch_regs[i-1].wasconst=0; |
cf95b4f0 |
7575 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 |
7576 | alloc_cc(&branch_regs[i-1],i-1); |
7577 | dirty_reg(&branch_regs[i-1],CCREG); |
cf95b4f0 |
7578 | if(dops[i-1].rt1==31) { // JAL |
57871462 |
7579 | alloc_reg(&branch_regs[i-1],i-1,31); |
7580 | dirty_reg(&branch_regs[i-1],31); |
57871462 |
7581 | } |
7582 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
40fca85b |
7583 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 |
7584 | break; |
7585 | case RJUMP: |
7586 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
7587 | branch_regs[i-1].isconst=0; |
7588 | branch_regs[i-1].wasconst=0; |
cf95b4f0 |
7589 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 |
7590 | alloc_cc(&branch_regs[i-1],i-1); |
7591 | dirty_reg(&branch_regs[i-1],CCREG); |
cf95b4f0 |
7592 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1); |
7593 | if(dops[i-1].rt1!=0) { // JALR |
7594 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1); |
7595 | dirty_reg(&branch_regs[i-1],dops[i-1].rt1); |
57871462 |
7596 | } |
7597 | #ifdef USE_MINI_HT |
cf95b4f0 |
7598 | if(dops[i-1].rs1==31) { // JALR |
57871462 |
7599 | alloc_reg(&branch_regs[i-1],i-1,RHASH); |
57871462 |
7600 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); |
57871462 |
7601 | } |
7602 | #endif |
7603 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
40fca85b |
7604 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 |
7605 | break; |
7606 | case CJUMP: |
cf95b4f0 |
7607 | if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE |
57871462 |
7608 | { |
7609 | alloc_cc(¤t,i-1); |
7610 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7611 | if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))|| |
7612 | (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) { |
57871462 |
7613 | // The delay slot overwrote one of our conditions |
7614 | // Delay slot goes after the test (in order) |
cf95b4f0 |
7615 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7616 | current.u|=1; |
57871462 |
7617 | delayslot_alloc(¤t,i); |
7618 | current.isconst=0; |
7619 | } |
7620 | else |
7621 | { |
cf95b4f0 |
7622 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 |
7623 | // Alloc the branch condition registers |
cf95b4f0 |
7624 | if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1); |
7625 | if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2); |
57871462 |
7626 | } |
7627 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
7628 | branch_regs[i-1].isconst=0; |
7629 | branch_regs[i-1].wasconst=0; |
7630 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
40fca85b |
7631 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 |
7632 | } |
7633 | else |
cf95b4f0 |
7634 | if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 |
7635 | { |
7636 | alloc_cc(¤t,i-1); |
7637 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7638 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 |
7639 | // The delay slot overwrote the branch condition |
7640 | // Delay slot goes after the test (in order) |
cf95b4f0 |
7641 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7642 | current.u|=1; |
57871462 |
7643 | delayslot_alloc(¤t,i); |
7644 | current.isconst=0; |
7645 | } |
7646 | else |
7647 | { |
cf95b4f0 |
7648 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 |
7649 | // Alloc the branch condition register |
cf95b4f0 |
7650 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 |
7651 | } |
7652 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
7653 | branch_regs[i-1].isconst=0; |
7654 | branch_regs[i-1].wasconst=0; |
7655 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
40fca85b |
7656 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 |
7657 | } |
57871462 |
7658 | break; |
7659 | case SJUMP: |
57871462 |
7660 | { |
7661 | alloc_cc(¤t,i-1); |
7662 | dirty_reg(¤t,CCREG); |
cf95b4f0 |
7663 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 |
7664 | // The delay slot overwrote the branch condition |
7665 | // Delay slot goes after the test (in order) |
cf95b4f0 |
7666 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 |
7667 | current.u|=1; |
57871462 |
7668 | delayslot_alloc(¤t,i); |
7669 | current.isconst=0; |
7670 | } |
7671 | else |
7672 | { |
cf95b4f0 |
7673 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 |
7674 | // Alloc the branch condition register |
cf95b4f0 |
7675 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 |
7676 | } |
7677 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
7678 | branch_regs[i-1].isconst=0; |
7679 | branch_regs[i-1].wasconst=0; |
7680 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
40fca85b |
7681 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 |
7682 | } |
57871462 |
7683 | break; |
57871462 |
7684 | } |
7685 | |
fe807a8a |
7686 | if (dops[i-1].is_ujump) |
57871462 |
7687 | { |
cf95b4f0 |
7688 | if(dops[i-1].rt1==31) // JAL/JALR |
57871462 |
7689 | { |
7690 | // Subroutine call will return here, don't alloc any registers |
57871462 |
7691 | current.dirty=0; |
7692 | clear_all_regs(current.regmap); |
7693 | alloc_reg(¤t,i,CCREG); |
7694 | dirty_reg(¤t,CCREG); |
7695 | } |
7696 | else if(i+1<slen) |
7697 | { |
7698 | // Internal branch will jump here, match registers to caller |
57871462 |
7699 | current.dirty=0; |
7700 | clear_all_regs(current.regmap); |
7701 | alloc_reg(¤t,i,CCREG); |
7702 | dirty_reg(¤t,CCREG); |
7703 | for(j=i-1;j>=0;j--) |
7704 | { |
277718fa |
7705 | if(cinfo[j].ba==start+i*4+4) { |
57871462 |
7706 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); |
57871462 |
7707 | current.dirty=branch_regs[j].dirty; |
7708 | break; |
7709 | } |
7710 | } |
7711 | while(j>=0) { |
277718fa |
7712 | if(cinfo[j].ba==start+i*4+4) { |
57871462 |
7713 | for(hr=0;hr<HOST_REGS;hr++) { |
7714 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { |
7715 | current.regmap[hr]=-1; |
7716 | } |
57871462 |
7717 | current.dirty&=branch_regs[j].dirty; |
7718 | } |
7719 | } |
7720 | j--; |
7721 | } |
7722 | } |
7723 | } |
7724 | } |
7725 | |
7726 | // Count cycles in between branches |
277718fa |
7727 | cinfo[i].ccadj = CLOCK_ADJUST(cc); |
a5cd72d0 |
7728 | if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception)) |
57871462 |
7729 | { |
7730 | cc=0; |
7731 | } |
71e490c5 |
7732 | #if !defined(DRC_DBG) |
cf95b4f0 |
7733 | else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2) |
054175e9 |
7734 | { |
81dbbf4c |
7735 | // this should really be removed since the real stalls have been implemented, |
7736 | // but doing so causes sizeable perf regression against the older version |
7737 | u_int gtec = gte_cycletab[source[i] & 0x3f]; |
32631e6a |
7738 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; |
fb407447 |
7739 | } |
cf95b4f0 |
7740 | else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) |
5fdcbb5a |
7741 | { |
7742 | cc+=4; |
7743 | } |
cf95b4f0 |
7744 | else if(dops[i].itype==C2LS) |
fb407447 |
7745 | { |
81dbbf4c |
7746 | // same as with C2OP |
32631e6a |
7747 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; |
fb407447 |
7748 | } |
7749 | #endif |
57871462 |
7750 | else |
7751 | { |
7752 | cc++; |
7753 | } |
7754 | |
cf95b4f0 |
7755 | if(!dops[i].is_ds) { |
57871462 |
7756 | regs[i].dirty=current.dirty; |
7757 | regs[i].isconst=current.isconst; |
40fca85b |
7758 | memcpy(constmap[i],current_constmap,sizeof(constmap[i])); |
57871462 |
7759 | } |
7760 | for(hr=0;hr<HOST_REGS;hr++) { |
7761 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { |
7762 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { |
7763 | regs[i].wasconst&=~(1<<hr); |
7764 | } |
7765 | } |
7766 | } |
7767 | if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; |
9b495f6e |
7768 | //regs[i].waswritten=current.waswritten; |
57871462 |
7769 | } |
4149788d |
7770 | } |
9f51b4b9 |
7771 | |
4149788d |
7772 | static noinline void pass4_cull_unused_regs(void) |
7773 | { |
53358c1d |
7774 | u_int last_needed_regs[4] = {0,0,0,0}; |
4149788d |
7775 | u_int nr=0; |
7776 | int i; |
9f51b4b9 |
7777 | |
57871462 |
7778 | for (i=slen-1;i>=0;i--) |
7779 | { |
7780 | int hr; |
53358c1d |
7781 | __builtin_prefetch(regs[i-2].regmap); |
fe807a8a |
7782 | if(dops[i].is_jump) |
57871462 |
7783 | { |
277718fa |
7784 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
57871462 |
7785 | { |
7786 | // Branch out of this block, don't need anything |
7787 | nr=0; |
7788 | } |
7789 | else |
7790 | { |
7791 | // Internal branch |
7792 | // Need whatever matches the target |
7793 | nr=0; |
277718fa |
7794 | int t=(cinfo[i].ba-start)>>2; |
57871462 |
7795 | for(hr=0;hr<HOST_REGS;hr++) |
7796 | { |
7797 | if(regs[i].regmap_entry[hr]>=0) { |
7798 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; |
7799 | } |
7800 | } |
7801 | } |
7802 | // Conditional branch may need registers for following instructions |
fe807a8a |
7803 | if (!dops[i].is_ujump) |
57871462 |
7804 | { |
7805 | if(i<slen-2) { |
53358c1d |
7806 | nr |= last_needed_regs[(i+2) & 3]; |
57871462 |
7807 | for(hr=0;hr<HOST_REGS;hr++) |
7808 | { |
7809 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); |
7810 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]); |
7811 | } |
7812 | } |
7813 | } |
7814 | // Don't need stuff which is overwritten |
f5955059 |
7815 | //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
7816 | //if(regs[i].regmap[hr]<0) nr&=~(1<<hr); |
57871462 |
7817 | // Merge in delay slot |
53358c1d |
7818 | if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1); |
7819 | if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2); |
7820 | nr |= get_regm(regmap_pre[i], dops[i+1].rs1); |
7821 | nr |= get_regm(regmap_pre[i], dops[i+1].rs2); |
7822 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1); |
7823 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2); |
7824 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) { |
7825 | nr |= get_regm(regmap_pre[i], ROREG); |
7826 | nr |= get_regm(regs[i].regmap_entry, ROREG); |
7827 | } |
7828 | if (dops[i+1].is_store) { |
7829 | nr |= get_regm(regmap_pre[i], INVCP); |
7830 | nr |= get_regm(regs[i].regmap_entry, INVCP); |
57871462 |
7831 | } |
7832 | } |
277718fa |
7833 | else if (dops[i].is_exception) |
57871462 |
7834 | { |
277718fa |
7835 | // SYSCALL instruction, etc |
57871462 |
7836 | nr=0; |
7837 | } |
7838 | else // Non-branch |
7839 | { |
7840 | if(i<slen-1) { |
7841 | for(hr=0;hr<HOST_REGS;hr++) { |
7842 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); |
7843 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); |
7844 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
7845 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); |
7846 | } |
7847 | } |
7848 | } |
53358c1d |
7849 | // Overwritten registers are not needed |
7850 | if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1); |
7851 | if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2); |
7852 | nr &= ~get_regm(regs[i].regmap, FTEMP); |
7853 | // Source registers are needed |
7854 | nr |= get_regm(regmap_pre[i], dops[i].rs1); |
7855 | nr |= get_regm(regmap_pre[i], dops[i].rs2); |
7856 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs1); |
7857 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs2); |
7858 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) { |
7859 | nr |= get_regm(regmap_pre[i], ROREG); |
7860 | nr |= get_regm(regs[i].regmap_entry, ROREG); |
7861 | } |
7862 | if (dops[i].is_store) { |
7863 | nr |= get_regm(regmap_pre[i], INVCP); |
7864 | nr |= get_regm(regs[i].regmap_entry, INVCP); |
7865 | } |
7866 | |
7867 | if (i > 0 && !dops[i].bt && regs[i].wasdirty) |
57871462 |
7868 | for(hr=0;hr<HOST_REGS;hr++) |
7869 | { |
57871462 |
7870 | // Don't store a register immediately after writing it, |
7871 | // may prevent dual-issue. |
7872 | // But do so if this is a branch target, otherwise we |
7873 | // might have to load the register before the branch. |
53358c1d |
7874 | if((regs[i].wasdirty>>hr)&1) { |
7c3a5182 |
7875 | if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { |
9de8a0c3 |
7876 | if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr; |
7877 | if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr; |
57871462 |
7878 | } |
7c3a5182 |
7879 | if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { |
9de8a0c3 |
7880 | if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr; |
7881 | if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr; |
57871462 |
7882 | } |
7883 | } |
7884 | } |
7885 | // Cycle count is needed at branches. Assume it is needed at the target too. |
de6dbc52 |
7886 | if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) { |
57871462 |
7887 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
7888 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
7889 | } |
7890 | // Save it |
53358c1d |
7891 | last_needed_regs[i & 3] = nr; |
9f51b4b9 |
7892 | |
57871462 |
7893 | // Deallocate unneeded registers |
7894 | for(hr=0;hr<HOST_REGS;hr++) |
7895 | { |
7896 | if(!((nr>>hr)&1)) { |
7897 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; |
fe807a8a |
7898 | if(dops[i].is_jump) |
57871462 |
7899 | { |
37387d8b |
7900 | int map1 = 0, map2 = 0, temp = 0; // or -1 ?? |
7901 | if (dops[i+1].is_load || dops[i+1].is_store) |
7902 | map1 = ROREG; |
7903 | if (dops[i+1].is_store) |
7904 | map2 = INVCP; |
7905 | if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS) |
7906 | temp = FTEMP; |
9de8a0c3 |
7907 | if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
7908 | regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && |
7909 | regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 && |
cf95b4f0 |
7910 | regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 && |
9de8a0c3 |
7911 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP && |
57871462 |
7912 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && |
7913 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && |
37387d8b |
7914 | regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2) |
57871462 |
7915 | { |
7916 | regs[i].regmap[hr]=-1; |
7917 | regs[i].isconst&=~(1<<hr); |
a550c61c |
7918 | regs[i].dirty&=~(1<<hr); |
7919 | regs[i+1].wasdirty&=~(1<<hr); |
9de8a0c3 |
7920 | if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 && |
7921 | branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 && |
7922 | branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 && |
cf95b4f0 |
7923 | branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 && |
9de8a0c3 |
7924 | branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP && |
57871462 |
7925 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && |
7926 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && |
37387d8b |
7927 | branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2) |
57871462 |
7928 | { |
7929 | branch_regs[i].regmap[hr]=-1; |
7930 | branch_regs[i].regmap_entry[hr]=-1; |
fe807a8a |
7931 | if (!dops[i].is_ujump) |
57871462 |
7932 | { |
fe807a8a |
7933 | if (i < slen-2) { |
57871462 |
7934 | regmap_pre[i+2][hr]=-1; |
79c75f1b |
7935 | regs[i+2].wasconst&=~(1<<hr); |
57871462 |
7936 | } |
7937 | } |
7938 | } |
7939 | } |
7940 | } |
7941 | else |
7942 | { |
7943 | // Non-branch |
7944 | if(i>0) |
7945 | { |
37387d8b |
7946 | int map1 = -1, map2 = -1, temp=-1; |
7947 | if (dops[i].is_load || dops[i].is_store) |
7948 | map1 = ROREG; |
7949 | if (dops[i].is_store) |
7950 | map2 = INVCP; |
7951 | if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) |
7952 | temp = FTEMP; |
9de8a0c3 |
7953 | if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && |
cf95b4f0 |
7954 | regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
9de8a0c3 |
7955 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && |
4b1c7cd1 |
7956 | //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) |
7957 | regs[i].regmap[hr] != CCREG) |
57871462 |
7958 | { |
cf95b4f0 |
7959 | if(i<slen-1&&!dops[i].is_ds) { |
ad49de89 |
7960 | assert(regs[i].regmap[hr]<64); |
afec9d44 |
7961 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0) |
57871462 |
7962 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) |
57871462 |
7963 | { |
c43b5311 |
7964 | SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
57871462 |
7965 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
7966 | } |
7967 | regmap_pre[i+1][hr]=-1; |
7968 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; |
79c75f1b |
7969 | regs[i+1].wasconst&=~(1<<hr); |
57871462 |
7970 | } |
7971 | regs[i].regmap[hr]=-1; |
7972 | regs[i].isconst&=~(1<<hr); |
a550c61c |
7973 | regs[i].dirty&=~(1<<hr); |
7974 | regs[i+1].wasdirty&=~(1<<hr); |
57871462 |
7975 | } |
7976 | } |
7977 | } |
3968e69e |
7978 | } // if needed |
7979 | } // for hr |
57871462 |
7980 | } |
4149788d |
7981 | } |
9f51b4b9 |
7982 | |
4149788d |
7983 | // If a register is allocated during a loop, try to allocate it for the |
7984 | // entire loop, if possible. This avoids loading/storing registers |
7985 | // inside of the loop. |
7986 | static noinline void pass5a_preallocate1(void) |
7987 | { |
7988 | int i, j, hr; |
57871462 |
7989 | signed char f_regmap[HOST_REGS]; |
7990 | clear_all_regs(f_regmap); |
7991 | for(i=0;i<slen-1;i++) |
7992 | { |
cf95b4f0 |
7993 | if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 |
7994 | { |
277718fa |
7995 | if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4)) |
cf95b4f0 |
7996 | if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU |
7997 | ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD |
a5cd72d0 |
7998 | ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR |
7999 | ||dops[i+1].itype==SHIFT |
cf95b4f0 |
8000 | ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP) |
57871462 |
8001 | { |
277718fa |
8002 | int t=(cinfo[i].ba-start)>>2; |
fe807a8a |
8003 | if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots |
cf95b4f0 |
8004 | if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated |
57871462 |
8005 | for(hr=0;hr<HOST_REGS;hr++) |
8006 | { |
7c3a5182 |
8007 | if(regs[i].regmap[hr]>=0) { |
b372a952 |
8008 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8009 | // dealloc old register |
8010 | int n; |
8011 | for(n=0;n<HOST_REGS;n++) |
8012 | { |
8013 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} |
8014 | } |
8015 | // and alloc new one |
8016 | f_regmap[hr]=regs[i].regmap[hr]; |
8017 | } |
8018 | } |
7c3a5182 |
8019 | if(branch_regs[i].regmap[hr]>=0) { |
b372a952 |
8020 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { |
8021 | // dealloc old register |
8022 | int n; |
8023 | for(n=0;n<HOST_REGS;n++) |
8024 | { |
8025 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} |
8026 | } |
8027 | // and alloc new one |
8028 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8029 | } |
8030 | } |
cf95b4f0 |
8031 | if(dops[i].ooo) { |
277718fa |
8032 | if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs) |
e1190b87 |
8033 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8034 | }else{ |
277718fa |
8035 | if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs) |
57871462 |
8036 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
8037 | } |
8038 | // Avoid dirty->clean transition |
e1190b87 |
8039 | #ifdef DESTRUCTIVE_WRITEBACK |
57871462 |
8040 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
e1190b87 |
8041 | #endif |
8042 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK |
8043 | // case above, however it's always a good idea. We can't hoist the |
8044 | // load if the register was already allocated, so there's no point |
8045 | // wasting time analyzing most of these cases. It only "succeeds" |
8046 | // when the mapping was different and the load can be replaced with |
8047 | // a mov, which is of negligible benefit. So such cases are |
8048 | // skipped below. |
57871462 |
8049 | if(f_regmap[hr]>0) { |
198df76f |
8050 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
57871462 |
8051 | int r=f_regmap[hr]; |
8052 | for(j=t;j<=i;j++) |
8053 | { |
277718fa |
8054 | //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r); |
57871462 |
8055 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; |
00fa9369 |
8056 | assert(r < 64); |
9de8a0c3 |
8057 | if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) { |
277718fa |
8058 | //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r); |
57871462 |
8059 | int k; |
8060 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { |
670c0f22 |
8061 | if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break; |
57871462 |
8062 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; |
57871462 |
8063 | k=i; |
8064 | while(k>1&®s[k-1].regmap[hr]==-1) { |
277718fa |
8065 | if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) { |
e1190b87 |
8066 | //printf("no free regs for store %x\n",start+(k-1)*4); |
8067 | break; |
57871462 |
8068 | } |
57871462 |
8069 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
8070 | //printf("no-match due to different register\n"); |
8071 | break; |
8072 | } |
fe807a8a |
8073 | if (dops[k-2].is_jump) { |
57871462 |
8074 | //printf("no-match due to branch\n"); |
8075 | break; |
8076 | } |
8077 | // call/ret fast path assumes no registers allocated |
cf95b4f0 |
8078 | if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { |
57871462 |
8079 | break; |
8080 | } |
57871462 |
8081 | k--; |
8082 | } |
57871462 |
8083 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { |
8084 | //printf("Extend r%d, %x ->\n",hr,start+k*4); |
8085 | while(k<i) { |
8086 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
8087 | regs[k].regmap[hr]=f_regmap[hr]; |
8088 | regmap_pre[k+1][hr]=f_regmap[hr]; |
8089 | regs[k].wasdirty&=~(1<<hr); |
8090 | regs[k].dirty&=~(1<<hr); |
8091 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; |
8092 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; |
8093 | regs[k].wasconst&=~(1<<hr); |
8094 | regs[k].isconst&=~(1<<hr); |
8095 | k++; |
8096 | } |
8097 | } |
8098 | else { |
8099 | //printf("Fail Extend r%d, %x ->\n",hr,start+k*4); |
8100 | break; |
8101 | } |
8102 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); |
8103 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { |
8104 | //printf("OK fill %x (r%d)\n",start+i*4,hr); |
8105 | regs[i].regmap_entry[hr]=f_regmap[hr]; |
8106 | regs[i].regmap[hr]=f_regmap[hr]; |
8107 | regs[i].wasdirty&=~(1<<hr); |
8108 | regs[i].dirty&=~(1<<hr); |
8109 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; |
8110 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; |
8111 | regs[i].wasconst&=~(1<<hr); |
8112 | regs[i].isconst&=~(1<<hr); |
8113 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; |
8114 | branch_regs[i].wasdirty&=~(1<<hr); |
8115 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; |
8116 | branch_regs[i].regmap[hr]=f_regmap[hr]; |
8117 | branch_regs[i].dirty&=~(1<<hr); |
8118 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; |
8119 | branch_regs[i].wasconst&=~(1<<hr); |
8120 | branch_regs[i].isconst&=~(1<<hr); |
fe807a8a |
8121 | if (!dops[i].is_ujump) { |
57871462 |
8122 | regmap_pre[i+2][hr]=f_regmap[hr]; |
8123 | regs[i+2].wasdirty&=~(1<<hr); |
8124 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; |
57871462 |
8125 | } |
8126 | } |
8127 | } |
8128 | for(k=t;k<j;k++) { |
e1190b87 |
8129 | // Alloc register clean at beginning of loop, |
8130 | // but may dirty it in pass 6 |
57871462 |
8131 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
8132 | regs[k].regmap[hr]=f_regmap[hr]; |
57871462 |
8133 | regs[k].dirty&=~(1<<hr); |
8134 | regs[k].wasconst&=~(1<<hr); |
8135 | regs[k].isconst&=~(1<<hr); |
fe807a8a |
8136 | if (dops[k].is_jump) { |
e1190b87 |
8137 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; |
8138 | branch_regs[k].regmap[hr]=f_regmap[hr]; |
8139 | branch_regs[k].dirty&=~(1<<hr); |
8140 | branch_regs[k].wasconst&=~(1<<hr); |
8141 | branch_regs[k].isconst&=~(1<<hr); |
fe807a8a |
8142 | if (!dops[k].is_ujump) { |
e1190b87 |
8143 | regmap_pre[k+2][hr]=f_regmap[hr]; |
8144 | regs[k+2].wasdirty&=~(1<<hr); |
e1190b87 |
8145 | } |
8146 | } |
8147 | else |
8148 | { |
8149 | regmap_pre[k+1][hr]=f_regmap[hr]; |
8150 | regs[k+1].wasdirty&=~(1<<hr); |
8151 | } |
57871462 |
8152 | } |
8153 | if(regs[j].regmap[hr]==f_regmap[hr]) |
8154 | regs[j].regmap_entry[hr]=f_regmap[hr]; |
8155 | break; |
8156 | } |
8157 | if(j==i) break; |
8158 | if(regs[j].regmap[hr]>=0) |
8159 | break; |
8160 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { |
8161 | //printf("no-match due to different register\n"); |
8162 | break; |
8163 | } |
fe807a8a |
8164 | if (dops[j].is_ujump) |
e1190b87 |
8165 | { |
8166 | // Stop on unconditional branch |
8167 | break; |
8168 | } |
cf95b4f0 |
8169 | if(dops[j].itype==CJUMP||dops[j].itype==SJUMP) |
e1190b87 |
8170 | { |
cf95b4f0 |
8171 | if(dops[j].ooo) { |
277718fa |
8172 | if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs) |
e1190b87 |
8173 | break; |
8174 | }else{ |
277718fa |
8175 | if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs) |
e1190b87 |
8176 | break; |
8177 | } |
8178 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { |
8179 | //printf("no-match due to different register (branch)\n"); |
57871462 |
8180 | break; |
8181 | } |
8182 | } |
277718fa |
8183 | if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) { |
e1190b87 |
8184 | //printf("No free regs for store %x\n",start+j*4); |
8185 | break; |
8186 | } |
ad49de89 |
8187 | assert(f_regmap[hr]<64); |
57871462 |
8188 | } |
8189 | } |
8190 | } |
8191 | } |
8192 | } |
8193 | }else{ |
198df76f |
8194 | // Non branch or undetermined branch target |
57871462 |
8195 | for(hr=0;hr<HOST_REGS;hr++) |
8196 | { |
8197 | if(hr!=EXCLUDE_REG) { |
7c3a5182 |
8198 | if(regs[i].regmap[hr]>=0) { |
b372a952 |
8199 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8200 | // dealloc old register |
8201 | int n; |
8202 | for(n=0;n<HOST_REGS;n++) |
8203 | { |
8204 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} |
8205 | } |
4149788d |
8206 | // and alloc new one |
8207 | f_regmap[hr]=regs[i].regmap[hr]; |
8208 | } |
8209 | } |
8210 | } |
8211 | } |
8212 | // Try to restore cycle count at branch targets |
8213 | if(dops[i].bt) { |
8214 | for(j=i;j<slen-1;j++) { |
8215 | if(regs[j].regmap[HOST_CCREG]!=-1) break; |
277718fa |
8216 | if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) { |
4149788d |
8217 | //printf("no free regs for store %x\n",start+j*4); |
8218 | break; |
8219 | } |
8220 | } |
8221 | if(regs[j].regmap[HOST_CCREG]==CCREG) { |
8222 | int k=i; |
8223 | //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4); |
8224 | while(k<j) { |
8225 | regs[k].regmap_entry[HOST_CCREG]=CCREG; |
8226 | regs[k].regmap[HOST_CCREG]=CCREG; |
8227 | regmap_pre[k+1][HOST_CCREG]=CCREG; |
8228 | regs[k+1].wasdirty|=1<<HOST_CCREG; |
8229 | regs[k].dirty|=1<<HOST_CCREG; |
8230 | regs[k].wasconst&=~(1<<HOST_CCREG); |
8231 | regs[k].isconst&=~(1<<HOST_CCREG); |
8232 | k++; |
8233 | } |
8234 | regs[j].regmap_entry[HOST_CCREG]=CCREG; |
8235 | } |
8236 | // Work backwards from the branch target |
8237 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) |
8238 | { |
8239 | //printf("Extend backwards\n"); |
8240 | int k; |
8241 | k=i; |
8242 | while(regs[k-1].regmap[HOST_CCREG]==-1) { |
277718fa |
8243 | if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) { |
4149788d |
8244 | //printf("no free regs for store %x\n",start+(k-1)*4); |
8245 | break; |
8246 | } |
8247 | k--; |
8248 | } |
8249 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { |
8250 | //printf("Extend CC, %x ->\n",start+k*4); |
8251 | while(k<=i) { |
8252 | regs[k].regmap_entry[HOST_CCREG]=CCREG; |
8253 | regs[k].regmap[HOST_CCREG]=CCREG; |
8254 | regmap_pre[k+1][HOST_CCREG]=CCREG; |
8255 | regs[k+1].wasdirty|=1<<HOST_CCREG; |
8256 | regs[k].dirty|=1<<HOST_CCREG; |
8257 | regs[k].wasconst&=~(1<<HOST_CCREG); |
8258 | regs[k].isconst&=~(1<<HOST_CCREG); |
8259 | k++; |
8260 | } |
8261 | } |
8262 | else { |
8263 | //printf("Fail Extend CC, %x ->\n",start+k*4); |
8264 | } |
8265 | } |
8266 | } |
a5cd72d0 |
8267 | if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&& |
4149788d |
8268 | dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&& |
a5cd72d0 |
8269 | dops[i].itype!=IMM16&&dops[i].itype!=LOAD) |
4149788d |
8270 | { |
8271 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); |
8272 | } |
8273 | } |
8274 | } |
8275 | } |
8276 | |
8277 | // This allocates registers (if possible) one instruction prior |
8278 | // to use, which can avoid a load-use penalty on certain CPUs. |
8279 | static noinline void pass5b_preallocate2(void) |
8280 | { |
8281 | int i, hr; |
8282 | for(i=0;i<slen-1;i++) |
8283 | { |
8284 | if (!i || !dops[i-1].is_jump) |
8285 | { |
8286 | if(!dops[i+1].bt) |
8287 | { |
277718fa |
8288 | int j, can_steal = 1; |
8289 | for (j = i; j < i + 2; j++) { |
8290 | int free_regs = 0; |
8291 | if (cinfo[j].min_free_regs == 0) |
8292 | continue; |
8293 | for (hr = 0; hr < HOST_REGS; hr++) |
8294 | if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0) |
8295 | free_regs++; |
8296 | if (free_regs <= cinfo[j].min_free_regs) { |
8297 | can_steal = 0; |
8298 | break; |
8299 | } |
8300 | } |
8301 | if (!can_steal) |
8302 | continue; |
4149788d |
8303 | if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16 |
a5cd72d0 |
8304 | ||(dops[i].itype==COP2&&dops[i].opcode2<3)) |
4149788d |
8305 | { |
8306 | if(dops[i+1].rs1) { |
8307 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0) |
8308 | { |
8309 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8310 | { |
8311 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; |
8312 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; |
8313 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; |
8314 | regs[i].isconst&=~(1<<hr); |
8315 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8316 | constmap[i][hr]=constmap[i+1][hr]; |
8317 | regs[i+1].wasdirty&=~(1<<hr); |
8318 | regs[i].dirty&=~(1<<hr); |
8319 | } |
8320 | } |
8321 | } |
8322 | if(dops[i+1].rs2) { |
8323 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0) |
8324 | { |
8325 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8326 | { |
8327 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; |
8328 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; |
8329 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; |
8330 | regs[i].isconst&=~(1<<hr); |
8331 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8332 | constmap[i][hr]=constmap[i+1][hr]; |
8333 | regs[i+1].wasdirty&=~(1<<hr); |
8334 | regs[i].dirty&=~(1<<hr); |
8335 | } |
8336 | } |
8337 | } |
8338 | // Preload target address for load instruction (non-constant) |
8339 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
a5cd72d0 |
8340 | if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0) |
4149788d |
8341 | { |
8342 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8343 | { |
8344 | regs[i].regmap[hr]=dops[i+1].rs1; |
8345 | regmap_pre[i+1][hr]=dops[i+1].rs1; |
8346 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; |
8347 | regs[i].isconst&=~(1<<hr); |
8348 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8349 | constmap[i][hr]=constmap[i+1][hr]; |
8350 | regs[i+1].wasdirty&=~(1<<hr); |
8351 | regs[i].dirty&=~(1<<hr); |
8352 | } |
8353 | } |
8354 | } |
8355 | // Load source into target register |
8356 | if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
a5cd72d0 |
8357 | if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0) |
4149788d |
8358 | { |
8359 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8360 | { |
8361 | regs[i].regmap[hr]=dops[i+1].rs1; |
8362 | regmap_pre[i+1][hr]=dops[i+1].rs1; |
8363 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; |
8364 | regs[i].isconst&=~(1<<hr); |
8365 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8366 | constmap[i][hr]=constmap[i+1][hr]; |
8367 | regs[i+1].wasdirty&=~(1<<hr); |
8368 | regs[i].dirty&=~(1<<hr); |
8369 | } |
8370 | } |
8371 | } |
8372 | // Address for store instruction (non-constant) |
277718fa |
8373 | if (dops[i+1].is_store) { // SB/SH/SW/SWC2 |
4149788d |
8374 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8375 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); |
8376 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); |
8377 | else { |
8378 | regs[i+1].regmap[hr]=AGEN1+((i+1)&1); |
8379 | regs[i+1].isconst&=~(1<<hr); |
277718fa |
8380 | regs[i+1].dirty&=~(1<<hr); |
8381 | regs[i+2].wasdirty&=~(1<<hr); |
4149788d |
8382 | } |
8383 | assert(hr>=0); |
8384 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8385 | { |
8386 | regs[i].regmap[hr]=dops[i+1].rs1; |
8387 | regmap_pre[i+1][hr]=dops[i+1].rs1; |
8388 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; |
8389 | regs[i].isconst&=~(1<<hr); |
8390 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8391 | constmap[i][hr]=constmap[i+1][hr]; |
8392 | regs[i+1].wasdirty&=~(1<<hr); |
8393 | regs[i].dirty&=~(1<<hr); |
8394 | } |
8395 | } |
8396 | } |
277718fa |
8397 | if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2 |
4149788d |
8398 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { |
8399 | int nr; |
8400 | hr=get_reg(regs[i+1].regmap,FTEMP); |
8401 | assert(hr>=0); |
8402 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
8403 | { |
8404 | regs[i].regmap[hr]=dops[i+1].rs1; |
8405 | regmap_pre[i+1][hr]=dops[i+1].rs1; |
8406 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; |
8407 | regs[i].isconst&=~(1<<hr); |
8408 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
8409 | constmap[i][hr]=constmap[i+1][hr]; |
8410 | regs[i+1].wasdirty&=~(1<<hr); |
8411 | regs[i].dirty&=~(1<<hr); |
8412 | } |
8413 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) |
8414 | { |
8415 | // move it to another register |
8416 | regs[i+1].regmap[hr]=-1; |
8417 | regmap_pre[i+2][hr]=-1; |
8418 | regs[i+1].regmap[nr]=FTEMP; |
8419 | regmap_pre[i+2][nr]=FTEMP; |
8420 | regs[i].regmap[nr]=dops[i+1].rs1; |
8421 | regmap_pre[i+1][nr]=dops[i+1].rs1; |
8422 | regs[i+1].regmap_entry[nr]=dops[i+1].rs1; |
8423 | regs[i].isconst&=~(1<<nr); |
8424 | regs[i+1].isconst&=~(1<<nr); |
8425 | regs[i].dirty&=~(1<<nr); |
8426 | regs[i+1].wasdirty&=~(1<<nr); |
8427 | regs[i+1].dirty&=~(1<<nr); |
8428 | regs[i+2].wasdirty&=~(1<<nr); |
8429 | } |
8430 | } |
8431 | } |
a5cd72d0 |
8432 | if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) { |
4149788d |
8433 | hr = -1; |
8434 | if(dops[i+1].itype==LOAD) |
a5cd72d0 |
8435 | hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1); |
277718fa |
8436 | if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2 |
4149788d |
8437 | hr=get_reg(regs[i+1].regmap,FTEMP); |
277718fa |
8438 | if (dops[i+1].is_store) { |
4149788d |
8439 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); |
8440 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); |
8441 | } |
8442 | if(hr>=0&®s[i].regmap[hr]<0) { |
8443 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
8444 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { |
8445 | regs[i].regmap[hr]=AGEN1+((i+1)&1); |
8446 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); |
8447 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); |
8448 | regs[i].isconst&=~(1<<hr); |
8449 | regs[i+1].wasdirty&=~(1<<hr); |
8450 | regs[i].dirty&=~(1<<hr); |
8451 | } |
b372a952 |
8452 | } |
8453 | } |
57871462 |
8454 | } |
8455 | } |
4149788d |
8456 | } |
8457 | } |
8458 | } |
8459 | |
8460 | // Write back dirty registers as soon as we will no longer modify them, |
8461 | // so that we don't end up with lots of writes at the branches. |
8462 | static noinline void pass6_clean_registers(int istart, int iend, int wr) |
8463 | { |
53358c1d |
8464 | static u_int wont_dirty[MAXBLOCK]; |
8465 | static u_int will_dirty[MAXBLOCK]; |
4149788d |
8466 | int i; |
8467 | int r; |
8468 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; |
8469 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; |
8470 | if(iend==slen-1) { |
8471 | will_dirty_i=will_dirty_next=0; |
8472 | wont_dirty_i=wont_dirty_next=0; |
8473 | }else{ |
8474 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; |
8475 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; |
8476 | } |
8477 | for (i=iend;i>=istart;i--) |
8478 | { |
8479 | signed char rregmap_i[RRMAP_SIZE]; |
8480 | u_int hr_candirty = 0; |
8481 | assert(HOST_REGS < 32); |
8482 | make_rregs(regs[i].regmap, rregmap_i, &hr_candirty); |
8483 | __builtin_prefetch(regs[i-1].regmap); |
8484 | if(dops[i].is_jump) |
8485 | { |
8486 | signed char branch_rregmap_i[RRMAP_SIZE]; |
8487 | u_int branch_hr_candirty = 0; |
8488 | make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty); |
277718fa |
8489 | if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4)) |
4149788d |
8490 | { |
8491 | // Branch out of this block, flush all regs |
8492 | will_dirty_i = 0; |
8493 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8494 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8495 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8496 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8497 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8498 | will_dirty_i &= branch_hr_candirty; |
8499 | if (dops[i].is_ujump) |
8500 | { |
8501 | // Unconditional branch |
8502 | wont_dirty_i = 0; |
8503 | // Merge in delay slot (will dirty) |
8504 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8505 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8506 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8507 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8508 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8509 | will_dirty_i &= hr_candirty; |
57871462 |
8510 | } |
4149788d |
8511 | else |
8512 | { |
8513 | // Conditional branch |
8514 | wont_dirty_i = wont_dirty_next; |
8515 | // Merge in delay slot (will dirty) |
8516 | // (the original code had no explanation why these 2 are commented out) |
8517 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8518 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8519 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8520 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8521 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8522 | will_dirty_i &= hr_candirty; |
8523 | } |
8524 | // Merge in delay slot (wont dirty) |
8525 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8526 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8527 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8528 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8529 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8530 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8531 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8532 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8533 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8534 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8535 | wont_dirty_i &= ~(1u << 31); |
8536 | if(wr) { |
8537 | #ifndef DESTRUCTIVE_WRITEBACK |
8538 | branch_regs[i].dirty&=wont_dirty_i; |
8539 | #endif |
8540 | branch_regs[i].dirty|=will_dirty_i; |
8541 | } |
8542 | } |
8543 | else |
8544 | { |
8545 | // Internal branch |
277718fa |
8546 | if(cinfo[i].ba<=start+i*4) { |
4149788d |
8547 | // Backward branch |
8548 | if (dops[i].is_ujump) |
8549 | { |
8550 | // Unconditional branch |
8551 | temp_will_dirty=0; |
8552 | temp_wont_dirty=0; |
8553 | // Merge in delay slot (will dirty) |
8554 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8555 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8556 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8557 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8558 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8559 | temp_will_dirty &= branch_hr_candirty; |
8560 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8561 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8562 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8563 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8564 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8565 | temp_will_dirty &= hr_candirty; |
8566 | } else { |
8567 | // Conditional branch (not taken case) |
8568 | temp_will_dirty=will_dirty_next; |
8569 | temp_wont_dirty=wont_dirty_next; |
8570 | // Merge in delay slot (will dirty) |
8571 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8572 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8573 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8574 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8575 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8576 | temp_will_dirty &= branch_hr_candirty; |
8577 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8578 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8579 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8580 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8581 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8582 | temp_will_dirty &= hr_candirty; |
8583 | } |
8584 | // Merge in delay slot (wont dirty) |
8585 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8586 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8587 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8588 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8589 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8590 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8591 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8592 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8593 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8594 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8595 | temp_wont_dirty &= ~(1u << 31); |
8596 | // Deal with changed mappings |
8597 | if(i<iend) { |
8598 | for(r=0;r<HOST_REGS;r++) { |
8599 | if(r!=EXCLUDE_REG) { |
8600 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { |
8601 | temp_will_dirty&=~(1<<r); |
8602 | temp_wont_dirty&=~(1<<r); |
8603 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { |
8604 | temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; |
8605 | temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; |
8606 | } else { |
8607 | temp_will_dirty|=1<<r; |
8608 | temp_wont_dirty|=1<<r; |
8609 | } |
8610 | } |
8611 | } |
8612 | } |
8613 | } |
8614 | if(wr) { |
8615 | will_dirty[i]=temp_will_dirty; |
8616 | wont_dirty[i]=temp_wont_dirty; |
277718fa |
8617 | pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0); |
4149788d |
8618 | }else{ |
8619 | // Limit recursion. It can take an excessive amount |
8620 | // of time if there are a lot of nested loops. |
277718fa |
8621 | will_dirty[(cinfo[i].ba-start)>>2]=0; |
8622 | wont_dirty[(cinfo[i].ba-start)>>2]=-1; |
57871462 |
8623 | } |
57871462 |
8624 | } |
4149788d |
8625 | /*else*/ if(1) |
57871462 |
8626 | { |
4149788d |
8627 | if (dops[i].is_ujump) |
8628 | { |
8629 | // Unconditional branch |
8630 | will_dirty_i=0; |
8631 | wont_dirty_i=0; |
277718fa |
8632 | //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging) |
4149788d |
8633 | for(r=0;r<HOST_REGS;r++) { |
8634 | if(r!=EXCLUDE_REG) { |
277718fa |
8635 | if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) { |
8636 | will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r); |
8637 | wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r); |
4149788d |
8638 | } |
8639 | if(branch_regs[i].regmap[r]>=0) { |
277718fa |
8640 | will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; |
8641 | wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; |
4149788d |
8642 | } |
8643 | } |
57871462 |
8644 | } |
4149788d |
8645 | //} |
8646 | // Merge in delay slot |
8647 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8648 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8649 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8650 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8651 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8652 | will_dirty_i &= branch_hr_candirty; |
8653 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8654 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8655 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8656 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8657 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8658 | will_dirty_i &= hr_candirty; |
8659 | } else { |
8660 | // Conditional branch |
8661 | will_dirty_i=will_dirty_next; |
8662 | wont_dirty_i=wont_dirty_next; |
277718fa |
8663 | //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging) |
4149788d |
8664 | for(r=0;r<HOST_REGS;r++) { |
8665 | if(r!=EXCLUDE_REG) { |
8666 | signed char target_reg=branch_regs[i].regmap[r]; |
277718fa |
8667 | if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) { |
8668 | will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r); |
8669 | wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r); |
4149788d |
8670 | } |
8671 | else if(target_reg>=0) { |
277718fa |
8672 | will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r; |
8673 | wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r; |
4149788d |
8674 | } |
8675 | } |
57871462 |
8676 | } |
4149788d |
8677 | // Merge in delay slot |
8678 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8679 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8680 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8681 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8682 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8683 | will_dirty_i &= branch_hr_candirty; |
8684 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8685 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8686 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8687 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8688 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8689 | will_dirty_i &= hr_candirty; |
57871462 |
8690 | } |
4149788d |
8691 | // Merge in delay slot (won't dirty) |
8692 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8693 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8694 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); |
8695 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); |
8696 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8697 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); |
8698 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); |
8699 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); |
8700 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); |
8701 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); |
8702 | wont_dirty_i &= ~(1u << 31); |
8703 | if(wr) { |
8704 | #ifndef DESTRUCTIVE_WRITEBACK |
8705 | branch_regs[i].dirty&=wont_dirty_i; |
8706 | #endif |
8707 | branch_regs[i].dirty|=will_dirty_i; |
57871462 |
8708 | } |
8709 | } |
8710 | } |
57871462 |
8711 | } |
277718fa |
8712 | else if (dops[i].is_exception) |
4149788d |
8713 | { |
277718fa |
8714 | // SYSCALL instruction, etc |
4149788d |
8715 | will_dirty_i=0; |
8716 | wont_dirty_i=0; |
8717 | } |
8718 | will_dirty_next=will_dirty_i; |
8719 | wont_dirty_next=wont_dirty_i; |
8720 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8721 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8722 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8723 | will_dirty_i &= hr_candirty; |
8724 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); |
8725 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); |
8726 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); |
8727 | wont_dirty_i &= ~(1u << 31); |
8728 | if (i > istart && !dops[i].is_jump) { |
8729 | // Don't store a register immediately after writing it, |
8730 | // may prevent dual-issue. |
8731 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31); |
8732 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31); |
8733 | } |
8734 | // Save it |
8735 | will_dirty[i]=will_dirty_i; |
8736 | wont_dirty[i]=wont_dirty_i; |
8737 | // Mark registers that won't be dirtied as not dirty |
8738 | if(wr) { |
8739 | regs[i].dirty|=will_dirty_i; |
8740 | #ifndef DESTRUCTIVE_WRITEBACK |
8741 | regs[i].dirty&=wont_dirty_i; |
8742 | if(dops[i].is_jump) |
57871462 |
8743 | { |
4149788d |
8744 | if (i < iend-1 && !dops[i].is_ujump) { |
8745 | for(r=0;r<HOST_REGS;r++) { |
8746 | if(r!=EXCLUDE_REG) { |
8747 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { |
8748 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); |
8749 | }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 |
8750 | } |
8751 | } |
8752 | } |
4149788d |
8753 | } |
8754 | else |
8755 | { |
8756 | if(i<iend) { |
8757 | for(r=0;r<HOST_REGS;r++) { |
8758 | if(r!=EXCLUDE_REG) { |
8759 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { |
8760 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); |
8761 | }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} |
57871462 |
8762 | } |
8763 | } |
8764 | } |
4149788d |
8765 | } |
8766 | #endif |
8767 | } |
8768 | // Deal with changed mappings |
8769 | temp_will_dirty=will_dirty_i; |
8770 | temp_wont_dirty=wont_dirty_i; |
8771 | for(r=0;r<HOST_REGS;r++) { |
8772 | if(r!=EXCLUDE_REG) { |
8773 | int nr; |
8774 | if(regs[i].regmap[r]==regmap_pre[i][r]) { |
8775 | if(wr) { |
8776 | #ifndef DESTRUCTIVE_WRITEBACK |
8777 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); |
8778 | #endif |
8779 | regs[i].wasdirty|=will_dirty_i&(1<<r); |
57871462 |
8780 | } |
4149788d |
8781 | } |
8782 | else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) { |
8783 | // Register moved to a different register |
8784 | will_dirty_i&=~(1<<r); |
8785 | wont_dirty_i&=~(1<<r); |
8786 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; |
8787 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; |
8788 | if(wr) { |
8789 | #ifndef DESTRUCTIVE_WRITEBACK |
8790 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); |
8791 | #endif |
8792 | regs[i].wasdirty|=will_dirty_i&(1<<r); |
8793 | } |
8794 | } |
8795 | else { |
8796 | will_dirty_i&=~(1<<r); |
8797 | wont_dirty_i&=~(1<<r); |
8798 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { |
8799 | will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; |
8800 | wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; |
8801 | } else { |
8802 | wont_dirty_i|=1<<r; |
8803 | /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ |
57871462 |
8804 | } |
8805 | } |
8806 | } |
8807 | } |
8808 | } |
4149788d |
8809 | } |
8810 | |
8811 | static noinline void pass10_expire_blocks(void) |
8812 | { |
93c0345b |
8813 | u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2; |
8814 | // not sizeof(ndrc->translation_cache) due to vita hack |
8815 | u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u); |
8816 | u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask; |
8817 | u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE); |
8818 | int hit; |
8819 | |
8820 | for (; expirep != end; expirep = ((expirep + step) & step_mask)) |
4149788d |
8821 | { |
93c0345b |
8822 | u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1); |
8823 | u_int block_i = expirep / step & (PAGE_COUNT - 1); |
8824 | u_int phase = (expirep >> (base_shift - 1)) & 1u; |
8825 | if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) { |
9b495f6e |
8826 | inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs, |
8827 | (long)(out - ndrc->translation_cache), phase); |
93c0345b |
8828 | } |
8829 | |
8830 | if (!phase) { |
8831 | hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift); |
8832 | if (hit) { |
8833 | do_clear_cache(); |
8834 | #ifdef USE_MINI_HT |
8835 | memset(mini_ht, -1, sizeof(mini_ht)); |
8836 | #endif |
8837 | } |
4149788d |
8838 | } |
93c0345b |
8839 | else |
b7ad2f2c |
8840 | unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift); |
4149788d |
8841 | } |
8842 | } |
8843 | |
104df9d3 |
8844 | static struct block_info *new_block_info(u_int start, u_int len, |
8845 | const void *source, const void *copy, u_char *beginning, u_short jump_in_count) |
8846 | { |
8847 | struct block_info **b_pptr; |
8848 | struct block_info *block; |
8849 | u_int page = get_page(start); |
8850 | |
8851 | block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0])); |
8852 | assert(block); |
8853 | assert(jump_in_count > 0); |
8854 | block->source = source; |
8855 | block->copy = copy; |
8856 | block->start = start; |
8857 | block->len = len; |
8858 | block->reg_sv_flags = 0; |
8859 | block->tc_offs = beginning - ndrc->translation_cache; |
8860 | //block->tc_len = out - beginning; |
8861 | block->is_dirty = 0; |
3280e616 |
8862 | block->inv_near_misses = 0; |
104df9d3 |
8863 | block->jump_in_cnt = jump_in_count; |
8864 | |
93c0345b |
8865 | // insert sorted by start mirror-unmasked vaddr |
104df9d3 |
8866 | for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) { |
8867 | if (*b_pptr == NULL || (*b_pptr)->start >= start) { |
8868 | block->next = *b_pptr; |
8869 | *b_pptr = block; |
8870 | break; |
8871 | } |
8872 | } |
8873 | stat_inc(stat_blocks); |
8874 | return block; |
8875 | } |
8876 | |
8877 | static int new_recompile_block(u_int addr) |
4149788d |
8878 | { |
8879 | u_int pagelimit = 0; |
8880 | u_int state_rflags = 0; |
8881 | int i; |
8882 | |
8883 | assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); |
8884 | |
a5cd72d0 |
8885 | if (addr & 3) { |
8886 | if (addr != hack_addr) { |
8887 | SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra); |
8888 | hack_addr = addr; |
8889 | } |
8890 | return -1; |
8891 | } |
8892 | |
4149788d |
8893 | // this is just for speculation |
8894 | for (i = 1; i < 32; i++) { |
8895 | if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) |
8896 | state_rflags |= 1 << i; |
8897 | } |
8898 | |
a5cd72d0 |
8899 | start = addr; |
4149788d |
8900 | new_dynarec_did_compile=1; |
8901 | if (Config.HLE && start == 0x80001000) // hlecall |
8902 | { |
8903 | // XXX: is this enough? Maybe check hleSoftCall? |
104df9d3 |
8904 | void *beginning = start_block(); |
4149788d |
8905 | |
4149788d |
8906 | emit_movimm(start,0); |
8907 | emit_writeword(0,&pcaddr); |
8908 | emit_far_jump(new_dyna_leave); |
8909 | literal_pool(0); |
8910 | end_block(beginning); |
104df9d3 |
8911 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
8912 | block->jump_in[0].vaddr = start; |
8913 | block->jump_in[0].addr = beginning; |
4149788d |
8914 | return 0; |
8915 | } |
8916 | else if (f1_hack && hack_addr == 0) { |
8917 | void *beginning = start_block(); |
4149788d |
8918 | emit_movimm(start, 0); |
8919 | emit_writeword(0, &hack_addr); |
8920 | emit_readword(&psxRegs.GPR.n.sp, 0); |
8921 | emit_readptr(&mem_rtab, 1); |
8922 | emit_shrimm(0, 12, 2); |
8923 | emit_readptr_dualindexedx_ptrlen(1, 2, 1); |
8924 | emit_addimm(0, 0x18, 0); |
8925 | emit_adds_ptr(1, 1, 1); |
8926 | emit_ldr_dualindexed(1, 0, 0); |
8927 | emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) |
104df9d3 |
8928 | emit_far_call(ndrc_get_addr_ht); |
4149788d |
8929 | emit_jmpreg(0); // jr k0 |
8930 | literal_pool(0); |
8931 | end_block(beginning); |
8932 | |
104df9d3 |
8933 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
8934 | block->jump_in[0].vaddr = start; |
8935 | block->jump_in[0].addr = beginning; |
4149788d |
8936 | SysPrintf("F1 hack to %08x\n", start); |
8937 | return 0; |
8938 | } |
8939 | |
d5aeda23 |
8940 | cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT |
8941 | ? Config.cycle_multiplier_override : Config.cycle_multiplier; |
4149788d |
8942 | |
8943 | source = get_source_start(start, &pagelimit); |
8944 | if (source == NULL) { |
8945 | if (addr != hack_addr) { |
8946 | SysPrintf("Compile at bogus memory address: %08x\n", addr); |
8947 | hack_addr = addr; |
8948 | } |
8949 | //abort(); |
8950 | return -1; |
8951 | } |
8952 | |
8953 | /* Pass 1: disassemble */ |
8954 | /* Pass 2: register dependencies, branch targets */ |
8955 | /* Pass 3: register allocation */ |
8956 | /* Pass 4: branch dependencies */ |
8957 | /* Pass 5: pre-alloc */ |
8958 | /* Pass 6: optimize clean/dirty state */ |
8959 | /* Pass 7: flag 32-bit registers */ |
8960 | /* Pass 8: assembly */ |
8961 | /* Pass 9: linker */ |
8962 | /* Pass 10: garbage collection / free memory */ |
8963 | |
8964 | /* Pass 1 disassembly */ |
8965 | |
8966 | pass1_disassemble(pagelimit); |
8967 | |
8968 | int clear_hack_addr = apply_hacks(); |
8969 | |
8970 | /* Pass 2 - Register dependencies and branch targets */ |
8971 | |
8972 | pass2_unneeded_regs(0,slen-1,0); |
8973 | |
8974 | /* Pass 3 - Register allocation */ |
8975 | |
8976 | pass3_register_alloc(addr); |
8977 | |
8978 | /* Pass 4 - Cull unused host registers */ |
8979 | |
8980 | pass4_cull_unused_regs(); |
8981 | |
8982 | /* Pass 5 - Pre-allocate registers */ |
8983 | |
8984 | pass5a_preallocate1(); |
8985 | pass5b_preallocate2(); |
9f51b4b9 |
8986 | |
57871462 |
8987 | /* Pass 6 - Optimize clean/dirty state */ |
4149788d |
8988 | pass6_clean_registers(0, slen-1, 1); |
9f51b4b9 |
8989 | |
57871462 |
8990 | /* Pass 7 - Identify 32-bit registers */ |
04fd948a |
8991 | for (i=slen-1;i>=0;i--) |
8992 | { |
cf95b4f0 |
8993 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
04fd948a |
8994 | { |
8995 | // Conditional branch |
8996 | if((source[i]>>16)!=0x1000&&i<slen-2) { |
8997 | // Mark this address as a branch target since it may be called |
8998 | // upon return from interrupt |
cf95b4f0 |
8999 | dops[i+2].bt=1; |
04fd948a |
9000 | } |
9001 | } |
9002 | } |
57871462 |
9003 | |
57871462 |
9004 | /* Pass 8 - Assembly */ |
9005 | linkcount=0;stubcount=0; |
4149788d |
9006 | is_delayslot=0; |
57871462 |
9007 | u_int dirty_pre=0; |
d148d265 |
9008 | void *beginning=start_block(); |
df4dc2b1 |
9009 | void *instr_addr0_override = NULL; |
4bdc30ab |
9010 | int ds = 0; |
9ad4d757 |
9011 | |
9ad4d757 |
9012 | if (start == 0x80030000) { |
3968e69e |
9013 | // nasty hack for the fastbios thing |
96186eba |
9014 | // override block entry to this code |
df4dc2b1 |
9015 | instr_addr0_override = out; |
9ad4d757 |
9016 | emit_movimm(start,0); |
96186eba |
9017 | // abuse io address var as a flag that we |
9018 | // have already returned here once |
643aeae3 |
9019 | emit_readword(&address,1); |
9020 | emit_writeword(0,&pcaddr); |
9021 | emit_writeword(0,&address); |
9ad4d757 |
9022 | emit_cmp(0,1); |
3968e69e |
9023 | #ifdef __aarch64__ |
9024 | emit_jeq(out + 4*2); |
2a014d73 |
9025 | emit_far_jump(new_dyna_leave); |
3968e69e |
9026 | #else |
643aeae3 |
9027 | emit_jne(new_dyna_leave); |
3968e69e |
9028 | #endif |
9ad4d757 |
9029 | } |
57871462 |
9030 | for(i=0;i<slen;i++) |
9031 | { |
9de8a0c3 |
9032 | __builtin_prefetch(regs[i+1].regmap); |
670c0f22 |
9033 | check_regmap(regmap_pre[i]); |
9034 | check_regmap(regs[i].regmap_entry); |
9035 | check_regmap(regs[i].regmap); |
57871462 |
9036 | //if(ds) printf("ds: "); |
4600ba03 |
9037 | disassemble_inst(i); |
57871462 |
9038 | if(ds) { |
9039 | ds=0; // Skip delay slot |
cf95b4f0 |
9040 | if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n"); |
df4dc2b1 |
9041 | instr_addr[i] = NULL; |
57871462 |
9042 | } else { |
ffb0b9e0 |
9043 | speculate_register_values(i); |
57871462 |
9044 | #ifndef DESTRUCTIVE_WRITEBACK |
fe807a8a |
9045 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 |
9046 | { |
ad49de89 |
9047 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]); |
57871462 |
9048 | } |
fe807a8a |
9049 | if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) { |
f776eb14 |
9050 | dirty_pre=branch_regs[i].dirty; |
9051 | }else{ |
f776eb14 |
9052 | dirty_pre=regs[i].dirty; |
9053 | } |
57871462 |
9054 | #endif |
9055 | // write back |
fe807a8a |
9056 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 |
9057 | { |
ad49de89 |
9058 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]); |
57871462 |
9059 | loop_preload(regmap_pre[i],regs[i].regmap_entry); |
9060 | } |
9061 | // branch target entry point |
df4dc2b1 |
9062 | instr_addr[i] = out; |
57871462 |
9063 | assem_debug("<->\n"); |
277718fa |
9064 | drc_dbg_emit_do_cmp(i, cinfo[i].ccadj); |
7f94b097 |
9065 | if (clear_hack_addr) { |
9066 | emit_movimm(0, 0); |
9067 | emit_writeword(0, &hack_addr); |
9068 | clear_hack_addr = 0; |
9069 | } |
dd114d7d |
9070 | |
57871462 |
9071 | // load regs |
9072 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) |
ad49de89 |
9073 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); |
cf95b4f0 |
9074 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); |
57871462 |
9075 | address_generation(i,®s[i],regs[i].regmap_entry); |
ad49de89 |
9076 | load_consts(regmap_pre[i],regs[i].regmap,i); |
fe807a8a |
9077 | if(dops[i].is_jump) |
57871462 |
9078 | { |
9079 | // Load the delay slot registers if necessary |
cf95b4f0 |
9080 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) |
9081 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); |
9082 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) |
9083 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); |
37387d8b |
9084 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) |
53358c1d |
9085 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
37387d8b |
9086 | if (dops[i+1].is_store) |
53358c1d |
9087 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
57871462 |
9088 | } |
9089 | else if(i+1<slen) |
9090 | { |
9091 | // Preload registers for following instruction |
cf95b4f0 |
9092 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2) |
9093 | if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2) |
9094 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); |
9095 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2) |
9096 | if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2) |
9097 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); |
57871462 |
9098 | } |
9099 | // TODO: if(is_ooo(i)) address_generation(i+1); |
9a3ccfeb |
9100 | if (!dops[i].is_jump || dops[i].itype == CJUMP) |
53358c1d |
9101 | load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG); |
37387d8b |
9102 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) |
53358c1d |
9103 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
37387d8b |
9104 | if (dops[i].is_store) |
53358c1d |
9105 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
2330734f |
9106 | |
277718fa |
9107 | ds = assemble(i, ®s[i], cinfo[i].ccadj); |
2330734f |
9108 | |
fe807a8a |
9109 | if (dops[i].is_ujump) |
57871462 |
9110 | literal_pool(1024); |
9111 | else |
9112 | literal_pool_jumpover(256); |
9113 | } |
9114 | } |
3d680478 |
9115 | |
9116 | assert(slen > 0); |
cf95b4f0 |
9117 | if (slen > 0 && dops[slen-1].itype == INTCALL) { |
3d680478 |
9118 | // no ending needed for this block since INTCALL never returns |
9119 | } |
57871462 |
9120 | // If the block did not end with an unconditional branch, |
9121 | // add a jump to the next instruction. |
3d680478 |
9122 | else if (i > 1) { |
4bdc30ab |
9123 | if (!dops[i-2].is_ujump) { |
fe807a8a |
9124 | assert(!dops[i-1].is_jump); |
57871462 |
9125 | assert(i==slen); |
cf95b4f0 |
9126 | if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { |
ad49de89 |
9127 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); |
57871462 |
9128 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9129 | emit_loadreg(CCREG,HOST_CCREG); |
277718fa |
9130 | emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG); |
57871462 |
9131 | } |
fe807a8a |
9132 | else |
57871462 |
9133 | { |
ad49de89 |
9134 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); |
57871462 |
9135 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); |
9136 | } |
643aeae3 |
9137 | add_to_linker(out,start+i*4,0); |
57871462 |
9138 | emit_jmp(0); |
9139 | } |
9140 | } |
9141 | else |
9142 | { |
9143 | assert(i>0); |
fe807a8a |
9144 | assert(!dops[i-1].is_jump); |
ad49de89 |
9145 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); |
57871462 |
9146 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9147 | emit_loadreg(CCREG,HOST_CCREG); |
277718fa |
9148 | emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG); |
643aeae3 |
9149 | add_to_linker(out,start+i*4,0); |
57871462 |
9150 | emit_jmp(0); |
9151 | } |
9152 | |
57871462 |
9153 | // Stubs |
a5cd72d0 |
9154 | for(i = 0; i < stubcount; i++) |
57871462 |
9155 | { |
b14b6a8f |
9156 | switch(stubs[i].type) |
57871462 |
9157 | { |
9158 | case LOADB_STUB: |
9159 | case LOADH_STUB: |
9160 | case LOADW_STUB: |
57871462 |
9161 | case LOADBU_STUB: |
9162 | case LOADHU_STUB: |
9163 | do_readstub(i);break; |
9164 | case STOREB_STUB: |
9165 | case STOREH_STUB: |
9166 | case STOREW_STUB: |
57871462 |
9167 | do_writestub(i);break; |
9168 | case CC_STUB: |
9169 | do_ccstub(i);break; |
9170 | case INVCODE_STUB: |
9171 | do_invstub(i);break; |
57871462 |
9172 | case STORELR_STUB: |
9173 | do_unalignedwritestub(i);break; |
a5cd72d0 |
9174 | case OVERFLOW_STUB: |
9175 | do_overflowstub(i); break; |
277718fa |
9176 | case ALIGNMENT_STUB: |
9177 | do_alignmentstub(i); break; |
a5cd72d0 |
9178 | default: |
9179 | assert(0); |
57871462 |
9180 | } |
9181 | } |
9182 | |
9ad4d757 |
9183 | if (instr_addr0_override) |
9184 | instr_addr[0] = instr_addr0_override; |
9185 | |
93c0345b |
9186 | #if 0 |
9187 | /* check for improper expiration */ |
9188 | for (i = 0; i < ARRAY_SIZE(jumps); i++) { |
9189 | int j; |
9190 | if (!jumps[i]) |
9191 | continue; |
9192 | for (j = 0; j < jumps[i]->count; j++) |
9193 | assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out); |
9194 | } |
9195 | #endif |
9196 | |
57871462 |
9197 | /* Pass 9 - Linker */ |
9198 | for(i=0;i<linkcount;i++) |
9199 | { |
643aeae3 |
9200 | assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target); |
57871462 |
9201 | literal_pool(64); |
104df9d3 |
9202 | if (!link_addr[i].internal) |
57871462 |
9203 | { |
643aeae3 |
9204 | void *stub = out; |
9205 | void *addr = check_addr(link_addr[i].target); |
9206 | emit_extjump(link_addr[i].addr, link_addr[i].target); |
9207 | if (addr) { |
9208 | set_jump_target(link_addr[i].addr, addr); |
104df9d3 |
9209 | ndrc_add_jump_out(link_addr[i].target,stub); |
57871462 |
9210 | } |
643aeae3 |
9211 | else |
9212 | set_jump_target(link_addr[i].addr, stub); |
57871462 |
9213 | } |
9214 | else |
9215 | { |
9216 | // Internal branch |
643aeae3 |
9217 | int target=(link_addr[i].target-start)>>2; |
57871462 |
9218 | assert(target>=0&&target<slen); |
9219 | assert(instr_addr[target]); |
9220 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
643aeae3 |
9221 | //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1); |
57871462 |
9222 | //#else |
643aeae3 |
9223 | set_jump_target(link_addr[i].addr, instr_addr[target]); |
57871462 |
9224 | //#endif |
9225 | } |
9226 | } |
3d680478 |
9227 | |
9228 | u_int source_len = slen*4; |
cf95b4f0 |
9229 | if (dops[slen-1].itype == INTCALL && source_len > 4) |
3d680478 |
9230 | // no need to treat the last instruction as compiled |
9231 | // as interpreter fully handles it |
9232 | source_len -= 4; |
9233 | |
9234 | if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow)) |
9235 | copy = shadow; |
9236 | |
57871462 |
9237 | // External Branch Targets (jump_in) |
104df9d3 |
9238 | int jump_in_count = 1; |
9239 | assert(instr_addr[0]); |
9240 | for (i = 1; i < slen; i++) |
9241 | { |
9242 | if (dops[i].bt && instr_addr[i]) |
9243 | jump_in_count++; |
9244 | } |
9245 | |
9246 | struct block_info *block = |
9247 | new_block_info(start, slen * 4, source, copy, beginning, jump_in_count); |
9248 | block->reg_sv_flags = state_rflags; |
9249 | |
9250 | int jump_in_i = 0; |
9251 | for (i = 0; i < slen; i++) |
57871462 |
9252 | { |
104df9d3 |
9253 | if ((i == 0 || dops[i].bt) && instr_addr[i]) |
57871462 |
9254 | { |
104df9d3 |
9255 | assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4); |
9256 | u_int vaddr = start + i*4; |
9257 | |
9258 | literal_pool(256); |
9259 | void *entry = out; |
9260 | load_regs_entry(i); |
9261 | if (entry == out) |
9262 | entry = instr_addr[i]; |
9263 | else |
9264 | emit_jmp(instr_addr[i]); |
9265 | |
9266 | block->jump_in[jump_in_i].vaddr = vaddr; |
9267 | block->jump_in[jump_in_i].addr = entry; |
9268 | jump_in_i++; |
57871462 |
9269 | } |
9270 | } |
104df9d3 |
9271 | assert(jump_in_i == jump_in_count); |
9272 | hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr); |
57871462 |
9273 | // Write out the literal pool if necessary |
9274 | literal_pool(0); |
9275 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
9276 | // Align code |
9277 | if(((u_int)out)&7) emit_addnop(13); |
9278 | #endif |
01d26796 |
9279 | assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE); |
643aeae3 |
9280 | //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4); |
3d680478 |
9281 | memcpy(copy, source, source_len); |
9282 | copy += source_len; |
9f51b4b9 |
9283 | |
d148d265 |
9284 | end_block(beginning); |
9f51b4b9 |
9285 | |
57871462 |
9286 | // If we're within 256K of the end of the buffer, |
9287 | // start over from the beginning. (Is 256K enough?) |
2a014d73 |
9288 | if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE) |
9289 | out = ndrc->translation_cache; |
9f51b4b9 |
9290 | |
57871462 |
9291 | // Trap writes to any of the pages we compiled |
104df9d3 |
9292 | mark_invalid_code(start, slen*4, 0); |
9f51b4b9 |
9293 | |
57871462 |
9294 | /* Pass 10 - Free memory by expiring oldest blocks */ |
9f51b4b9 |
9295 | |
4149788d |
9296 | pass10_expire_blocks(); |
9297 | |
37387d8b |
9298 | #ifdef ASSEM_PRINT |
9299 | fflush(stdout); |
9300 | #endif |
ece032e6 |
9301 | stat_inc(stat_bc_direct); |
57871462 |
9302 | return 0; |
9303 | } |
b9b61529 |
9304 | |
9305 | // vim:shiftwidth=2:expandtab |