1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include "new_dynarec_config.h"
34 #include "../psxhle.h"
35 #include "../psxinterpreter.h"
37 #include "emu_if.h" // emulator interface
39 #define noinline __attribute__((noinline,noclone))
41 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
44 #define min(a, b) ((b) < (a) ? (b) : (a))
47 #define max(a, b) ((b) > (a) ? (b) : (a))
52 //#define REG_ALLOC_PRINT
55 #define assem_debug printf
57 #define assem_debug(...)
59 //#define inv_debug printf
60 #define inv_debug(...)
63 #include "assem_x86.h"
66 #include "assem_x64.h"
69 #include "assem_arm.h"
72 #include "assem_arm64.h"
75 #define RAM_SIZE 0x200000
77 #define MAX_OUTPUT_BLOCK_SIZE 262144
80 // apparently Vita has a 16MB limit, so either we cut tc in half,
81 // or use this hack (it's a hack because tc size was designed to be power-of-2)
82 #define TC_REDUCE_BYTES 4096
84 #define TC_REDUCE_BYTES 0
89 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
92 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
93 const void *f[2048 / sizeof(void *)];
97 #ifdef BASE_ADDR_DYNAMIC
98 static struct ndrc_mem *ndrc;
100 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
101 static struct ndrc_mem *ndrc = &ndrc_;
122 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
123 // don't match .regmap will be written back
124 // [i].regmap_entry - regs that must be set up if someone jumps here
125 // [i].regmap - regs [i] insn will read/(over)write
126 // branch_regs[i].* - same as above but for branches, takes delay slot into account
129 signed char regmap_entry[HOST_REGS];
130 signed char regmap[HOST_REGS];
134 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
135 u_int isconst; // ... but isconst is false when r2 is known
136 u_int loadedconst; // host regs that have constants loaded
137 u_int waswritten; // MIPS regs that were used as store base before
140 // note: asm depends on this layout
146 struct ll_entry *next;
174 static struct decoded_insn
195 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
196 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
197 struct ll_entry *jump_dirty[4096];
199 static struct ll_entry *jump_out[4096];
201 static u_int *source;
202 static char insn[MAXBLOCK][10];
203 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
204 static uint64_t gte_rt[MAXBLOCK];
205 static uint64_t gte_unneeded[MAXBLOCK];
206 static u_int smrv[32]; // speculated MIPS register values
207 static u_int smrv_strong; // mask or regs that are likely to have correct values
208 static u_int smrv_weak; // same, but somewhat less likely
209 static u_int smrv_strong_next; // same, but after current insn executes
210 static u_int smrv_weak_next;
211 static int imm[MAXBLOCK];
212 static u_int ba[MAXBLOCK];
213 static uint64_t unneeded_reg[MAXBLOCK];
214 static uint64_t branch_unneeded_reg[MAXBLOCK];
215 // see 'struct regstat' for a description
216 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
217 // contains 'real' consts at [i] insn, but may differ from what's actually
218 // loaded in host reg as 'final' value is always loaded, see get_final_value()
219 static uint32_t current_constmap[HOST_REGS];
220 static uint32_t constmap[MAXBLOCK][HOST_REGS];
221 static struct regstat regs[MAXBLOCK];
222 static struct regstat branch_regs[MAXBLOCK];
223 static signed char minimum_free_regs[MAXBLOCK];
224 static u_int needed_reg[MAXBLOCK];
225 static u_int wont_dirty[MAXBLOCK];
226 static u_int will_dirty[MAXBLOCK];
227 static int ccadj[MAXBLOCK];
229 static void *instr_addr[MAXBLOCK];
230 static struct link_entry link_addr[MAXBLOCK];
231 static int linkcount;
232 static struct code_stub stubs[MAXBLOCK*3];
233 static int stubcount;
234 static u_int literals[1024][2];
235 static int literalcount;
236 static int is_delayslot;
237 static char shadow[1048576] __attribute__((aligned(16)));
240 static u_int stop_after_jal;
241 static u_int f1_hack;
243 int new_dynarec_hacks;
244 int new_dynarec_hacks_pergame;
245 int new_dynarec_hacks_old;
246 int new_dynarec_did_compile;
248 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
250 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
251 extern int last_count; // last absolute target, often = next_interupt
253 extern int pending_exception;
254 extern int branch_target;
255 extern uintptr_t ram_offset;
256 extern uintptr_t mini_ht[32][2];
257 extern u_char restore_candidate[512];
259 /* registers that may be allocated */
261 #define LOREG 32 // lo
262 #define HIREG 33 // hi
263 //#define FSREG 34 // FPU status (FCSR)
264 #define CSREG 35 // Coprocessor status
265 #define CCREG 36 // Cycle count
266 #define INVCP 37 // Pointer to invalid_code
267 //#define MMREG 38 // Pointer to memory_map
268 #define ROREG 39 // ram offset (if rdram!=0x80000000)
270 #define FTEMP 40 // FPU temporary register
271 #define PTEMP 41 // Prefetch temporary register
272 //#define TLREG 42 // TLB mapping offset
273 #define RHASH 43 // Return address hash
274 #define RHTBL 44 // Return address hash table address
275 #define RTEMP 45 // JR/JALR address register
277 #define AGEN1 46 // Address generation temporary register
278 //#define AGEN2 47 // Address generation temporary register
279 //#define MGEN1 48 // Maptable address generation temporary register
280 //#define MGEN2 49 // Maptable address generation temporary register
281 #define BTREG 50 // Branch target temporary register
283 /* instruction types */
284 #define NOP 0 // No operation
285 #define LOAD 1 // Load
286 #define STORE 2 // Store
287 #define LOADLR 3 // Unaligned load
288 #define STORELR 4 // Unaligned store
289 #define MOV 5 // Move
290 #define ALU 6 // Arithmetic/logic
291 #define MULTDIV 7 // Multiply/divide
292 #define SHIFT 8 // Shift by register
293 #define SHIFTIMM 9// Shift by immediate
294 #define IMM16 10 // 16-bit immediate
295 #define RJUMP 11 // Unconditional jump to register
296 #define UJUMP 12 // Unconditional jump
297 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
298 #define SJUMP 14 // Conditional branch (regimm format)
299 #define COP0 15 // Coprocessor 0
300 #define COP1 16 // Coprocessor 1
301 #define C1LS 17 // Coprocessor 1 load/store
302 //#define FJUMP 18 // Conditional branch (floating point)
303 //#define FLOAT 19 // Floating point unit
304 //#define FCONV 20 // Convert integer to float
305 //#define FCOMP 21 // Floating point compare (sets FSREG)
306 #define SYSCALL 22// SYSCALL,BREAK
307 #define OTHER 23 // Other
308 #define SPAN 24 // Branch/delay slot spans 2 pages
309 #define NI 25 // Not implemented
310 #define HLECALL 26// PCSX fake opcodes for HLE
311 #define COP2 27 // Coprocessor 2 move
312 #define C2LS 28 // Coprocessor 2 load/store
313 #define C2OP 29 // Coprocessor 2 operation
314 #define INTCALL 30// Call interpreter to handle rare corner cases
321 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
322 #define DJT_2 (void *)2l
325 int new_recompile_block(u_int addr);
326 void *get_addr_ht(u_int vaddr);
327 void invalidate_block(u_int block);
328 void invalidate_addr(u_int addr);
329 void remove_hash(int vaddr);
331 void dyna_linker_ds();
333 void verify_code_ds();
336 void fp_exception_ds();
337 void jump_syscall (u_int u0, u_int u1, u_int pc);
338 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
339 void jump_break (u_int u0, u_int u1, u_int pc);
340 void jump_break_ds(u_int u0, u_int u1, u_int pc);
341 void jump_to_new_pc();
342 void call_gteStall();
343 void new_dyna_leave();
345 // Needed by assembler
346 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
347 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
348 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
349 static void load_all_regs(const signed char i_regmap[]);
350 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
351 static void load_regs_entry(int t);
352 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
353 static u_int get_host_reglist(const signed char *regmap);
355 static int verify_dirty(const u_int *ptr);
356 static int get_final_value(int hr, int i, int *value);
357 static void add_stub(enum stub_type type, void *addr, void *retaddr,
358 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
359 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
360 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
361 static void add_to_linker(void *addr, u_int target, int ext);
362 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
363 int addr, int *offset_reg, int *addr_reg_override);
364 static void *get_direct_memhandler(void *table, u_int addr,
365 enum stub_type type, uintptr_t *addr_host);
366 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
367 static void pass_args(int a0, int a1);
368 static void emit_far_jump(const void *f);
369 static void emit_far_call(const void *f);
372 #include <psp2/kernel/sysmem.h>
374 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
375 extern int getVMBlock();
376 int _newlib_vm_size_user = sizeof(*ndrc);
379 static void mprotect_w_x(void *start, void *end, int is_x)
383 // *Open* enables write on all memory that was
384 // allocated by sceKernelAllocMemBlockForVM()?
386 sceKernelCloseVMDomain();
388 sceKernelOpenVMDomain();
390 u_long mstart = (u_long)start & ~4095ul;
391 u_long mend = (u_long)end;
392 if (mprotect((void *)mstart, mend - mstart,
393 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
394 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
399 static void start_tcache_write(void *start, void *end)
401 mprotect_w_x(start, end, 0);
404 static void end_tcache_write(void *start, void *end)
406 #if defined(__arm__) || defined(__aarch64__)
407 size_t len = (char *)end - (char *)start;
408 #if defined(__BLACKBERRY_QNX__)
409 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
410 #elif defined(__MACH__)
411 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
413 sceKernelSyncVMDomain(sceBlock, start, len);
415 ctr_flush_invalidate_cache();
416 #elif defined(__aarch64__)
417 // as of 2021, __clear_cache() is still broken on arm64
418 // so here is a custom one :(
419 clear_cache_arm64(start, end);
421 __clear_cache(start, end);
426 mprotect_w_x(start, end, 1);
429 static void *start_block(void)
431 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
432 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
433 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
434 start_tcache_write(out, end);
438 static void end_block(void *start)
440 end_tcache_write(start, out);
443 // also takes care of w^x mappings when patching code
444 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
446 static void mark_clear_cache(void *target)
448 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
449 u_int mask = 1u << ((offset >> 12) & 31);
450 if (!(needs_clear_cache[offset >> 17] & mask)) {
451 char *start = (char *)((uintptr_t)target & ~4095l);
452 start_tcache_write(start, start + 4095);
453 needs_clear_cache[offset >> 17] |= mask;
457 // Clearing the cache is rather slow on ARM Linux, so mark the areas
458 // that need to be cleared, and then only clear these areas once.
459 static void do_clear_cache(void)
462 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
464 u_int bitmap = needs_clear_cache[i];
467 for (j = 0; j < 32; j++)
470 if (!(bitmap & (1<<j)))
473 start = ndrc->translation_cache + i*131072 + j*4096;
475 for (j++; j < 32; j++) {
476 if (!(bitmap & (1<<j)))
480 end_tcache_write(start, end);
482 needs_clear_cache[i] = 0;
486 //#define DEBUG_CYCLE_COUNT 1
488 #define NO_CYCLE_PENALTY_THR 12
490 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
491 int cycle_multiplier_override;
492 int cycle_multiplier_old;
493 static int cycle_multiplier_active;
495 static int CLOCK_ADJUST(int x)
497 int m = cycle_multiplier_active;
498 int s = (x >> 31) | 1;
499 return (x * m + s * 50) / 100;
502 static int ds_writes_rjump_rs(int i)
504 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
507 static u_int get_page(u_int vaddr)
509 u_int page=vaddr&~0xe0000000;
510 if (page < 0x1000000)
511 page &= ~0x0e00000; // RAM mirrors
513 if(page>2048) page=2048+(page&2047);
517 // no virtual mem in PCSX
518 static u_int get_vpage(u_int vaddr)
520 return get_page(vaddr);
523 static struct ht_entry *hash_table_get(u_int vaddr)
525 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
528 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
530 ht_bin->vaddr[1] = ht_bin->vaddr[0];
531 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
532 ht_bin->vaddr[0] = vaddr;
533 ht_bin->tcaddr[0] = tcaddr;
536 // some messy ari64's code, seems to rely on unsigned 32bit overflow
537 static int doesnt_expire_soon(void *tcaddr)
539 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
540 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
543 // Get address from virtual address
544 // This is called from the recompiled JR/JALR instructions
545 void noinline *get_addr(u_int vaddr)
547 u_int page=get_page(vaddr);
548 u_int vpage=get_vpage(vaddr);
549 struct ll_entry *head;
550 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
553 if(head->vaddr==vaddr) {
554 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
555 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
560 head=jump_dirty[vpage];
562 if(head->vaddr==vaddr) {
563 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
564 // Don't restore blocks which are about to expire from the cache
565 if (doesnt_expire_soon(head->addr))
566 if (verify_dirty(head->addr)) {
567 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
568 invalid_code[vaddr>>12]=0;
569 inv_code_start=inv_code_end=~0;
571 restore_candidate[vpage>>3]|=1<<(vpage&7);
573 else restore_candidate[page>>3]|=1<<(page&7);
574 struct ht_entry *ht_bin = hash_table_get(vaddr);
575 if (ht_bin->vaddr[0] == vaddr)
576 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
578 hash_table_add(ht_bin, vaddr, head->addr);
585 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
586 int r=new_recompile_block(vaddr);
587 if(r==0) return get_addr(vaddr);
588 // generate an address error
590 Cause=(vaddr<<31)|(4<<2);
591 EPC=(vaddr&1)?vaddr-5:vaddr;
593 return get_addr_ht(0x80000080);
595 // Look up address in hash table first
596 void *get_addr_ht(u_int vaddr)
598 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
599 const struct ht_entry *ht_bin = hash_table_get(vaddr);
600 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
601 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
602 return get_addr(vaddr);
605 static void clear_all_regs(signed char regmap[])
607 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
610 static signed char get_reg(const signed char regmap[], signed char r)
613 for (hr = 0; hr < HOST_REGS; hr++) {
614 if (hr == EXCLUDE_REG)
622 static signed char get_reg_temp(const signed char regmap[])
625 for (hr = 0; hr < HOST_REGS; hr++) {
626 if (hr == EXCLUDE_REG)
628 if (regmap[hr] == (signed char)-1)
634 // Find a register that is available for two consecutive cycles
635 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
638 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
642 static int count_free_regs(const signed char regmap[])
646 for(hr=0;hr<HOST_REGS;hr++)
648 if(hr!=EXCLUDE_REG) {
649 if(regmap[hr]<0) count++;
655 static void dirty_reg(struct regstat *cur, signed char reg)
659 hr = get_reg(cur->regmap, reg);
664 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
668 hr = get_reg(cur->regmap, reg);
670 cur->isconst |= 1<<hr;
671 current_constmap[hr] = value;
675 static void clear_const(struct regstat *cur, signed char reg)
679 hr = get_reg(cur->regmap, reg);
681 cur->isconst &= ~(1<<hr);
684 static int is_const(const struct regstat *cur, signed char reg)
687 if (reg < 0) return 0;
689 hr = get_reg(cur->regmap, reg);
691 return (cur->isconst>>hr)&1;
695 static uint32_t get_const(const struct regstat *cur, signed char reg)
699 hr = get_reg(cur->regmap, reg);
701 return current_constmap[hr];
703 SysPrintf("Unknown constant in r%d\n", reg);
707 // Least soon needed registers
708 // Look at the next ten instructions and see which registers
709 // will be used. Try not to reallocate these.
710 void lsn(u_char hsn[], int i, int *preferred_reg)
720 if (dops[i+j].is_ujump)
722 // Don't go past an unconditonal jump
729 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
730 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
731 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
732 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
733 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
734 // Stores can allocate zero
735 hsn[dops[i+j].rs1]=j;
736 hsn[dops[i+j].rs2]=j;
738 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
740 // On some architectures stores need invc_ptr
741 #if defined(HOST_IMM8)
742 if (dops[i+j].is_store)
745 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
753 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
755 // Follow first branch
756 int t=(ba[i+b]-start)>>2;
757 j=7-b;if(t+j>=slen) j=slen-t-1;
760 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
761 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
762 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
763 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
766 // TODO: preferred register based on backward branch
768 // Delay slot should preferably not overwrite branch conditions or cycle count
769 if (i > 0 && dops[i-1].is_jump) {
770 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
771 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
777 // Coprocessor load/store needs FTEMP, even if not declared
778 if(dops[i].itype==C2LS) {
781 // Load L/R also uses FTEMP as a temporary register
782 if(dops[i].itype==LOADLR) {
785 // Also SWL/SWR/SDL/SDR
786 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
789 // Don't remove the miniht registers
790 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
797 // We only want to allocate registers if we're going to use them again soon
798 int needed_again(int r, int i)
804 if (i > 0 && dops[i-1].is_ujump)
806 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
807 return 0; // Don't need any registers if exiting the block
815 if (dops[i+j].is_ujump)
817 // Don't go past an unconditonal jump
821 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
828 if(dops[i+j].rs1==r) rn=j;
829 if(dops[i+j].rs2==r) rn=j;
830 if((unneeded_reg[i+j]>>r)&1) rn=10;
831 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
841 // Try to match register allocations at the end of a loop with those
843 int loop_reg(int i, int r, int hr)
852 if (dops[i+j].is_ujump)
854 // Don't go past an unconditonal jump
861 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
867 if((unneeded_reg[i+k]>>r)&1) return hr;
868 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
870 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
872 int t=(ba[i+k]-start)>>2;
873 int reg=get_reg(regs[t].regmap_entry,r);
874 if(reg>=0) return reg;
875 //reg=get_reg(regs[t+1].regmap_entry,r);
876 //if(reg>=0) return reg;
884 // Allocate every register, preserving source/target regs
885 void alloc_all(struct regstat *cur,int i)
889 for(hr=0;hr<HOST_REGS;hr++) {
890 if(hr!=EXCLUDE_REG) {
891 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
892 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
895 cur->dirty&=~(1<<hr);
898 if(cur->regmap[hr]==0)
901 cur->dirty&=~(1<<hr);
908 static int host_tempreg_in_use;
910 static void host_tempreg_acquire(void)
912 assert(!host_tempreg_in_use);
913 host_tempreg_in_use = 1;
916 static void host_tempreg_release(void)
918 host_tempreg_in_use = 0;
921 static void host_tempreg_acquire(void) {}
922 static void host_tempreg_release(void) {}
926 extern void gen_interupt();
927 extern void do_insn_cmp();
928 #define FUNCNAME(f) { f, " " #f }
929 static const struct {
932 } function_names[] = {
933 FUNCNAME(cc_interrupt),
934 FUNCNAME(gen_interupt),
935 FUNCNAME(get_addr_ht),
937 FUNCNAME(jump_handler_read8),
938 FUNCNAME(jump_handler_read16),
939 FUNCNAME(jump_handler_read32),
940 FUNCNAME(jump_handler_write8),
941 FUNCNAME(jump_handler_write16),
942 FUNCNAME(jump_handler_write32),
943 FUNCNAME(invalidate_addr),
944 FUNCNAME(jump_to_new_pc),
945 FUNCNAME(jump_break),
946 FUNCNAME(jump_break_ds),
947 FUNCNAME(jump_syscall),
948 FUNCNAME(jump_syscall_ds),
949 FUNCNAME(call_gteStall),
950 FUNCNAME(new_dyna_leave),
952 FUNCNAME(pcsx_mtc0_ds),
954 FUNCNAME(do_insn_cmp),
957 FUNCNAME(verify_code),
961 static const char *func_name(const void *a)
964 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
965 if (function_names[i].addr == a)
966 return function_names[i].name;
970 #define func_name(x) ""
974 #include "assem_x86.c"
977 #include "assem_x64.c"
980 #include "assem_arm.c"
983 #include "assem_arm64.c"
986 static void *get_trampoline(const void *f)
990 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
991 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
994 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
995 SysPrintf("trampoline table is full, last func %p\n", f);
998 if (ndrc->tramp.f[i] == NULL) {
999 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1000 ndrc->tramp.f[i] = f;
1001 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1003 return &ndrc->tramp.ops[i];
1006 static void emit_far_jump(const void *f)
1008 if (can_jump_or_call(f)) {
1013 f = get_trampoline(f);
1017 static void emit_far_call(const void *f)
1019 if (can_jump_or_call(f)) {
1024 f = get_trampoline(f);
1028 // Add virtual address mapping to linked list
1029 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1031 struct ll_entry *new_entry;
1032 new_entry=malloc(sizeof(struct ll_entry));
1033 assert(new_entry!=NULL);
1034 new_entry->vaddr=vaddr;
1035 new_entry->reg_sv_flags=0;
1036 new_entry->addr=addr;
1037 new_entry->next=*head;
1041 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1043 ll_add(head,vaddr,addr);
1044 (*head)->reg_sv_flags=reg_sv_flags;
1047 // Check if an address is already compiled
1048 // but don't return addresses which are about to expire from the cache
1049 void *check_addr(u_int vaddr)
1051 struct ht_entry *ht_bin = hash_table_get(vaddr);
1053 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1054 if (ht_bin->vaddr[i] == vaddr)
1055 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1056 if (isclean(ht_bin->tcaddr[i]))
1057 return ht_bin->tcaddr[i];
1059 u_int page=get_page(vaddr);
1060 struct ll_entry *head;
1062 while (head != NULL) {
1063 if (head->vaddr == vaddr) {
1064 if (doesnt_expire_soon(head->addr)) {
1065 // Update existing entry with current address
1066 if (ht_bin->vaddr[0] == vaddr) {
1067 ht_bin->tcaddr[0] = head->addr;
1070 if (ht_bin->vaddr[1] == vaddr) {
1071 ht_bin->tcaddr[1] = head->addr;
1074 // Insert into hash table with low priority.
1075 // Don't evict existing entries, as they are probably
1076 // addresses that are being accessed frequently.
1077 if (ht_bin->vaddr[0] == -1) {
1078 ht_bin->vaddr[0] = vaddr;
1079 ht_bin->tcaddr[0] = head->addr;
1081 else if (ht_bin->vaddr[1] == -1) {
1082 ht_bin->vaddr[1] = vaddr;
1083 ht_bin->tcaddr[1] = head->addr;
1093 void remove_hash(int vaddr)
1095 //printf("remove hash: %x\n",vaddr);
1096 struct ht_entry *ht_bin = hash_table_get(vaddr);
1097 if (ht_bin->vaddr[1] == vaddr) {
1098 ht_bin->vaddr[1] = -1;
1099 ht_bin->tcaddr[1] = NULL;
1101 if (ht_bin->vaddr[0] == vaddr) {
1102 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1103 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1104 ht_bin->vaddr[1] = -1;
1105 ht_bin->tcaddr[1] = NULL;
1109 static void ll_remove_matching_addrs(struct ll_entry **head,
1110 uintptr_t base_offs_s, int shift)
1112 struct ll_entry *next;
1114 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1115 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1116 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1118 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1119 remove_hash((*head)->vaddr);
1126 head=&((*head)->next);
1131 // Remove all entries from linked list
1132 void ll_clear(struct ll_entry **head)
1134 struct ll_entry *cur;
1135 struct ll_entry *next;
1146 // Dereference the pointers and remove if it matches
1147 static void ll_kill_pointers(struct ll_entry *head,
1148 uintptr_t base_offs_s, int shift)
1151 u_char *ptr = get_pointer(head->addr);
1152 uintptr_t o1 = ptr - ndrc->translation_cache;
1153 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1154 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1155 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1157 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1158 void *host_addr=find_extjump_insn(head->addr);
1159 mark_clear_cache(host_addr);
1160 set_jump_target(host_addr, head->addr);
1166 // This is called when we write to a compiled block (see do_invstub)
1167 static void invalidate_page(u_int page)
1169 struct ll_entry *head;
1170 struct ll_entry *next;
1174 inv_debug("INVALIDATE: %x\n",head->vaddr);
1175 remove_hash(head->vaddr);
1180 head=jump_out[page];
1183 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1184 void *host_addr=find_extjump_insn(head->addr);
1185 mark_clear_cache(host_addr);
1186 set_jump_target(host_addr, head->addr); // point back to dyna_linker
1193 static void invalidate_block_range(u_int block, u_int first, u_int last)
1195 u_int page=get_page(block<<12);
1196 //printf("first=%d last=%d\n",first,last);
1197 invalidate_page(page);
1198 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1199 assert(last<page+5);
1200 // Invalidate the adjacent pages if a block crosses a 4K boundary
1202 invalidate_page(first);
1205 for(first=page+1;first<last;first++) {
1206 invalidate_page(first);
1210 // Don't trap writes
1211 invalid_code[block]=1;
1214 memset(mini_ht,-1,sizeof(mini_ht));
1218 void invalidate_block(u_int block)
1220 u_int page=get_page(block<<12);
1221 u_int vpage=get_vpage(block<<12);
1222 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1223 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1226 struct ll_entry *head;
1227 head=jump_dirty[vpage];
1228 //printf("page=%d vpage=%d\n",page,vpage);
1230 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1231 u_char *start, *end;
1232 get_bounds(head->addr, &start, &end);
1233 //printf("start: %p end: %p\n", start, end);
1234 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1235 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1236 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1237 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1243 invalidate_block_range(block,first,last);
1246 void invalidate_addr(u_int addr)
1249 // this check is done by the caller
1250 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1251 u_int page=get_vpage(addr);
1252 if(page<2048) { // RAM
1253 struct ll_entry *head;
1254 u_int addr_min=~0, addr_max=0;
1255 u_int mask=RAM_SIZE-1;
1256 u_int addr_main=0x80000000|(addr&mask);
1258 inv_code_start=addr_main&~0xfff;
1259 inv_code_end=addr_main|0xfff;
1262 // must check previous page too because of spans..
1264 inv_code_start-=0x1000;
1266 for(;pg1<=page;pg1++) {
1267 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1268 u_char *start_h, *end_h;
1270 get_bounds(head->addr, &start_h, &end_h);
1271 start = (uintptr_t)start_h - ram_offset;
1272 end = (uintptr_t)end_h - ram_offset;
1273 if(start<=addr_main&&addr_main<end) {
1274 if(start<addr_min) addr_min=start;
1275 if(end>addr_max) addr_max=end;
1277 else if(addr_main<start) {
1278 if(start<inv_code_end)
1279 inv_code_end=start-1;
1282 if(end>inv_code_start)
1288 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1289 inv_code_start=inv_code_end=~0;
1290 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1294 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1295 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1296 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1300 invalidate_block(addr>>12);
1303 // This is called when loading a save state.
1304 // Anything could have changed, so invalidate everything.
1305 void invalidate_all_pages(void)
1308 for(page=0;page<4096;page++)
1309 invalidate_page(page);
1310 for(page=0;page<1048576;page++)
1311 if(!invalid_code[page]) {
1312 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1313 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1316 memset(mini_ht,-1,sizeof(mini_ht));
1321 static void do_invstub(int n)
1324 u_int reglist=stubs[n].a;
1325 set_jump_target(stubs[n].addr, out);
1327 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1328 emit_far_call(invalidate_addr);
1329 restore_regs(reglist);
1330 emit_jmp(stubs[n].retaddr); // return address
1333 // Add an entry to jump_out after making a link
1334 // src should point to code by emit_extjump2()
1335 void add_jump_out(u_int vaddr,void *src)
1337 u_int page=get_page(vaddr);
1338 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1339 check_extjump2(src);
1340 ll_add(jump_out+page,vaddr,src);
1341 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
1344 // If a code block was found to be unmodified (bit was set in
1345 // restore_candidate) and it remains unmodified (bit is clear
1346 // in invalid_code) then move the entries for that 4K page from
1347 // the dirty list to the clean list.
1348 void clean_blocks(u_int page)
1350 struct ll_entry *head;
1351 inv_debug("INV: clean_blocks page=%d\n",page);
1352 head=jump_dirty[page];
1354 if(!invalid_code[head->vaddr>>12]) {
1355 // Don't restore blocks which are about to expire from the cache
1356 if (doesnt_expire_soon(head->addr)) {
1357 if(verify_dirty(head->addr)) {
1358 u_char *start, *end;
1359 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1362 get_bounds(head->addr, &start, &end);
1363 if (start - rdram < RAM_SIZE) {
1364 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1365 inv|=invalid_code[i];
1368 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1372 void *clean_addr = get_clean_addr(head->addr);
1373 if (doesnt_expire_soon(clean_addr)) {
1375 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1376 //printf("page=%x, addr=%x\n",page,head->vaddr);
1377 //assert(head->vaddr>>12==(page|0x80000));
1378 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1379 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1380 if (ht_bin->vaddr[0] == head->vaddr)
1381 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1382 if (ht_bin->vaddr[1] == head->vaddr)
1383 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1393 /* Register allocation */
1395 // Note: registers are allocated clean (unmodified state)
1396 // if you intend to modify the register, you must call dirty_reg().
1397 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1400 int preferred_reg = PREFERRED_REG_FIRST
1401 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1402 if (reg == CCREG) preferred_reg = HOST_CCREG;
1403 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1404 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1406 // Don't allocate unused registers
1407 if((cur->u>>reg)&1) return;
1409 // see if it's already allocated
1410 for(hr=0;hr<HOST_REGS;hr++)
1412 if(cur->regmap[hr]==reg) return;
1415 // Keep the same mapping if the register was already allocated in a loop
1416 preferred_reg = loop_reg(i,reg,preferred_reg);
1418 // Try to allocate the preferred register
1419 if(cur->regmap[preferred_reg]==-1) {
1420 cur->regmap[preferred_reg]=reg;
1421 cur->dirty&=~(1<<preferred_reg);
1422 cur->isconst&=~(1<<preferred_reg);
1425 r=cur->regmap[preferred_reg];
1428 cur->regmap[preferred_reg]=reg;
1429 cur->dirty&=~(1<<preferred_reg);
1430 cur->isconst&=~(1<<preferred_reg);
1434 // Clear any unneeded registers
1435 // We try to keep the mapping consistent, if possible, because it
1436 // makes branches easier (especially loops). So we try to allocate
1437 // first (see above) before removing old mappings. If this is not
1438 // possible then go ahead and clear out the registers that are no
1440 for(hr=0;hr<HOST_REGS;hr++)
1445 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1449 // Try to allocate any available register, but prefer
1450 // registers that have not been used recently.
1452 for (hr = PREFERRED_REG_FIRST; ; ) {
1453 if (cur->regmap[hr] < 0) {
1454 int oldreg = regs[i-1].regmap[hr];
1455 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1456 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1458 cur->regmap[hr]=reg;
1459 cur->dirty&=~(1<<hr);
1460 cur->isconst&=~(1<<hr);
1465 if (hr == EXCLUDE_REG)
1467 if (hr == HOST_REGS)
1469 if (hr == PREFERRED_REG_FIRST)
1474 // Try to allocate any available register
1475 for (hr = PREFERRED_REG_FIRST; ; ) {
1476 if (cur->regmap[hr] < 0) {
1477 cur->regmap[hr]=reg;
1478 cur->dirty&=~(1<<hr);
1479 cur->isconst&=~(1<<hr);
1483 if (hr == EXCLUDE_REG)
1485 if (hr == HOST_REGS)
1487 if (hr == PREFERRED_REG_FIRST)
1491 // Ok, now we have to evict someone
1492 // Pick a register we hopefully won't need soon
1493 u_char hsn[MAXREG+1];
1494 memset(hsn,10,sizeof(hsn));
1496 lsn(hsn,i,&preferred_reg);
1497 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1498 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1500 // Don't evict the cycle count at entry points, otherwise the entry
1501 // stub will have to write it.
1502 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1503 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1506 // Alloc preferred register if available
1507 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1508 for(hr=0;hr<HOST_REGS;hr++) {
1509 // Evict both parts of a 64-bit register
1510 if(cur->regmap[hr]==r) {
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1516 cur->regmap[preferred_reg]=reg;
1519 for(r=1;r<=MAXREG;r++)
1521 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1522 for(hr=0;hr<HOST_REGS;hr++) {
1523 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1524 if(cur->regmap[hr]==r) {
1525 cur->regmap[hr]=reg;
1526 cur->dirty&=~(1<<hr);
1527 cur->isconst&=~(1<<hr);
1538 for(r=1;r<=MAXREG;r++)
1541 for(hr=0;hr<HOST_REGS;hr++) {
1542 if(cur->regmap[hr]==r) {
1543 cur->regmap[hr]=reg;
1544 cur->dirty&=~(1<<hr);
1545 cur->isconst&=~(1<<hr);
1552 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1555 // Allocate a temporary register. This is done without regard to
1556 // dirty status or whether the register we request is on the unneeded list
1557 // Note: This will only allocate one register, even if called multiple times
1558 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1561 int preferred_reg = -1;
1563 // see if it's already allocated
1564 for(hr=0;hr<HOST_REGS;hr++)
1566 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1569 // Try to allocate any available register
1570 for(hr=HOST_REGS-1;hr>=0;hr--) {
1571 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1572 cur->regmap[hr]=reg;
1573 cur->dirty&=~(1<<hr);
1574 cur->isconst&=~(1<<hr);
1579 // Find an unneeded register
1580 for(hr=HOST_REGS-1;hr>=0;hr--)
1586 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1587 cur->regmap[hr]=reg;
1588 cur->dirty&=~(1<<hr);
1589 cur->isconst&=~(1<<hr);
1596 // Ok, now we have to evict someone
1597 // Pick a register we hopefully won't need soon
1598 // TODO: we might want to follow unconditional jumps here
1599 // TODO: get rid of dupe code and make this into a function
1600 u_char hsn[MAXREG+1];
1601 memset(hsn,10,sizeof(hsn));
1603 lsn(hsn,i,&preferred_reg);
1604 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1606 // Don't evict the cycle count at entry points, otherwise the entry
1607 // stub will have to write it.
1608 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1609 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1612 for(r=1;r<=MAXREG;r++)
1614 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1615 for(hr=0;hr<HOST_REGS;hr++) {
1616 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1617 if(cur->regmap[hr]==r) {
1618 cur->regmap[hr]=reg;
1619 cur->dirty&=~(1<<hr);
1620 cur->isconst&=~(1<<hr);
1631 for(r=1;r<=MAXREG;r++)
1634 for(hr=0;hr<HOST_REGS;hr++) {
1635 if(cur->regmap[hr]==r) {
1636 cur->regmap[hr]=reg;
1637 cur->dirty&=~(1<<hr);
1638 cur->isconst&=~(1<<hr);
1645 SysPrintf("This shouldn't happen");abort();
1648 static void mov_alloc(struct regstat *current,int i)
1650 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1651 alloc_cc(current,i); // for stalls
1652 dirty_reg(current,CCREG);
1655 // Note: Don't need to actually alloc the source registers
1656 //alloc_reg(current,i,dops[i].rs1);
1657 alloc_reg(current,i,dops[i].rt1);
1659 clear_const(current,dops[i].rs1);
1660 clear_const(current,dops[i].rt1);
1661 dirty_reg(current,dops[i].rt1);
1664 static void shiftimm_alloc(struct regstat *current,int i)
1666 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1669 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1670 else dops[i].lt1=dops[i].rs1;
1671 alloc_reg(current,i,dops[i].rt1);
1672 dirty_reg(current,dops[i].rt1);
1673 if(is_const(current,dops[i].rs1)) {
1674 int v=get_const(current,dops[i].rs1);
1675 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1676 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1677 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1679 else clear_const(current,dops[i].rt1);
1684 clear_const(current,dops[i].rs1);
1685 clear_const(current,dops[i].rt1);
1688 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1692 if(dops[i].opcode2==0x3c) // DSLL32
1696 if(dops[i].opcode2==0x3e) // DSRL32
1700 if(dops[i].opcode2==0x3f) // DSRA32
1706 static void shift_alloc(struct regstat *current,int i)
1709 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1711 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1712 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1713 alloc_reg(current,i,dops[i].rt1);
1714 if(dops[i].rt1==dops[i].rs2) {
1715 alloc_reg_temp(current,i,-1);
1716 minimum_free_regs[i]=1;
1718 } else { // DSLLV/DSRLV/DSRAV
1721 clear_const(current,dops[i].rs1);
1722 clear_const(current,dops[i].rs2);
1723 clear_const(current,dops[i].rt1);
1724 dirty_reg(current,dops[i].rt1);
1728 static void alu_alloc(struct regstat *current,int i)
1730 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1732 if(dops[i].rs1&&dops[i].rs2) {
1733 alloc_reg(current,i,dops[i].rs1);
1734 alloc_reg(current,i,dops[i].rs2);
1737 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1738 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1740 alloc_reg(current,i,dops[i].rt1);
1743 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1745 alloc_reg(current,i,dops[i].rs1);
1746 alloc_reg(current,i,dops[i].rs2);
1747 alloc_reg(current,i,dops[i].rt1);
1750 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1752 if(dops[i].rs1&&dops[i].rs2) {
1753 alloc_reg(current,i,dops[i].rs1);
1754 alloc_reg(current,i,dops[i].rs2);
1758 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1759 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1761 alloc_reg(current,i,dops[i].rt1);
1764 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1767 clear_const(current,dops[i].rs1);
1768 clear_const(current,dops[i].rs2);
1769 clear_const(current,dops[i].rt1);
1770 dirty_reg(current,dops[i].rt1);
1773 static void imm16_alloc(struct regstat *current,int i)
1775 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1776 else dops[i].lt1=dops[i].rs1;
1777 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1778 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1781 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1782 clear_const(current,dops[i].rs1);
1783 clear_const(current,dops[i].rt1);
1785 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1786 if(is_const(current,dops[i].rs1)) {
1787 int v=get_const(current,dops[i].rs1);
1788 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1789 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1790 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1792 else clear_const(current,dops[i].rt1);
1794 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1795 if(is_const(current,dops[i].rs1)) {
1796 int v=get_const(current,dops[i].rs1);
1797 set_const(current,dops[i].rt1,v+imm[i]);
1799 else clear_const(current,dops[i].rt1);
1802 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1804 dirty_reg(current,dops[i].rt1);
1807 static void load_alloc(struct regstat *current,int i)
1809 clear_const(current,dops[i].rt1);
1810 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1811 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1812 if (needed_again(dops[i].rs1, i))
1813 alloc_reg(current, i, dops[i].rs1);
1815 alloc_reg(current, i, ROREG);
1816 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1817 alloc_reg(current,i,dops[i].rt1);
1818 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1819 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1823 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1827 dirty_reg(current,dops[i].rt1);
1828 // LWL/LWR need a temporary register for the old value
1829 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1831 alloc_reg(current,i,FTEMP);
1832 alloc_reg_temp(current,i,-1);
1833 minimum_free_regs[i]=1;
1838 // Load to r0 or unneeded register (dummy load)
1839 // but we still need a register to calculate the address
1840 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1842 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1844 alloc_reg_temp(current,i,-1);
1845 minimum_free_regs[i]=1;
1846 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1853 void store_alloc(struct regstat *current,int i)
1855 clear_const(current,dops[i].rs2);
1856 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1857 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1858 alloc_reg(current,i,dops[i].rs2);
1859 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1863 alloc_reg(current, i, ROREG);
1864 #if defined(HOST_IMM8)
1865 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1866 alloc_reg(current, i, INVCP);
1868 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1869 alloc_reg(current,i,FTEMP);
1871 // We need a temporary register for address generation
1872 alloc_reg_temp(current,i,-1);
1873 minimum_free_regs[i]=1;
1876 void c1ls_alloc(struct regstat *current,int i)
1878 clear_const(current,dops[i].rt1);
1879 alloc_reg(current,i,CSREG); // Status
1882 void c2ls_alloc(struct regstat *current,int i)
1884 clear_const(current,dops[i].rt1);
1885 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1886 alloc_reg(current,i,FTEMP);
1888 alloc_reg(current, i, ROREG);
1889 #if defined(HOST_IMM8)
1890 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1891 if (dops[i].opcode == 0x3a) // SWC2
1892 alloc_reg(current,i,INVCP);
1894 // We need a temporary register for address generation
1895 alloc_reg_temp(current,i,-1);
1896 minimum_free_regs[i]=1;
1899 #ifndef multdiv_alloc
1900 void multdiv_alloc(struct regstat *current,int i)
1907 // case 0x1D: DMULTU
1910 clear_const(current,dops[i].rs1);
1911 clear_const(current,dops[i].rs2);
1912 alloc_cc(current,i); // for stalls
1913 if(dops[i].rs1&&dops[i].rs2)
1915 if((dops[i].opcode2&4)==0) // 32-bit
1917 current->u&=~(1LL<<HIREG);
1918 current->u&=~(1LL<<LOREG);
1919 alloc_reg(current,i,HIREG);
1920 alloc_reg(current,i,LOREG);
1921 alloc_reg(current,i,dops[i].rs1);
1922 alloc_reg(current,i,dops[i].rs2);
1923 dirty_reg(current,HIREG);
1924 dirty_reg(current,LOREG);
1933 // Multiply by zero is zero.
1934 // MIPS does not have a divide by zero exception.
1935 // The result is undefined, we return zero.
1936 alloc_reg(current,i,HIREG);
1937 alloc_reg(current,i,LOREG);
1938 dirty_reg(current,HIREG);
1939 dirty_reg(current,LOREG);
1944 void cop0_alloc(struct regstat *current,int i)
1946 if(dops[i].opcode2==0) // MFC0
1949 clear_const(current,dops[i].rt1);
1950 alloc_all(current,i);
1951 alloc_reg(current,i,dops[i].rt1);
1952 dirty_reg(current,dops[i].rt1);
1955 else if(dops[i].opcode2==4) // MTC0
1958 clear_const(current,dops[i].rs1);
1959 alloc_reg(current,i,dops[i].rs1);
1960 alloc_all(current,i);
1963 alloc_all(current,i); // FIXME: Keep r0
1965 alloc_reg(current,i,0);
1970 // TLBR/TLBWI/TLBWR/TLBP/ERET
1971 assert(dops[i].opcode2==0x10);
1972 alloc_all(current,i);
1974 minimum_free_regs[i]=HOST_REGS;
1977 static void cop2_alloc(struct regstat *current,int i)
1979 if (dops[i].opcode2 < 3) // MFC2/CFC2
1981 alloc_cc(current,i); // for stalls
1982 dirty_reg(current,CCREG);
1984 clear_const(current,dops[i].rt1);
1985 alloc_reg(current,i,dops[i].rt1);
1986 dirty_reg(current,dops[i].rt1);
1989 else if (dops[i].opcode2 > 3) // MTC2/CTC2
1992 clear_const(current,dops[i].rs1);
1993 alloc_reg(current,i,dops[i].rs1);
1997 alloc_reg(current,i,0);
2000 alloc_reg_temp(current,i,-1);
2001 minimum_free_regs[i]=1;
2004 void c2op_alloc(struct regstat *current,int i)
2006 alloc_cc(current,i); // for stalls
2007 dirty_reg(current,CCREG);
2008 alloc_reg_temp(current,i,-1);
2011 void syscall_alloc(struct regstat *current,int i)
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 alloc_all(current,i);
2016 minimum_free_regs[i]=HOST_REGS;
2020 void delayslot_alloc(struct regstat *current,int i)
2022 switch(dops[i].itype) {
2030 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
2031 SysPrintf("Disabled speculative precompilation\n");
2035 imm16_alloc(current,i);
2039 load_alloc(current,i);
2043 store_alloc(current,i);
2046 alu_alloc(current,i);
2049 shift_alloc(current,i);
2052 multdiv_alloc(current,i);
2055 shiftimm_alloc(current,i);
2058 mov_alloc(current,i);
2061 cop0_alloc(current,i);
2066 cop2_alloc(current,i);
2069 c1ls_alloc(current,i);
2072 c2ls_alloc(current,i);
2075 c2op_alloc(current,i);
2080 // Special case where a branch and delay slot span two pages in virtual memory
2081 static void pagespan_alloc(struct regstat *current,int i)
2084 current->wasconst=0;
2086 minimum_free_regs[i]=HOST_REGS;
2087 alloc_all(current,i);
2088 alloc_cc(current,i);
2089 dirty_reg(current,CCREG);
2090 if(dops[i].opcode==3) // JAL
2092 alloc_reg(current,i,31);
2093 dirty_reg(current,31);
2095 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2097 alloc_reg(current,i,dops[i].rs1);
2098 if (dops[i].rt1!=0) {
2099 alloc_reg(current,i,dops[i].rt1);
2100 dirty_reg(current,dops[i].rt1);
2103 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2105 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2106 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2109 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2111 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2116 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2117 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2119 assert(stubcount < ARRAY_SIZE(stubs));
2120 stubs[stubcount].type = type;
2121 stubs[stubcount].addr = addr;
2122 stubs[stubcount].retaddr = retaddr;
2123 stubs[stubcount].a = a;
2124 stubs[stubcount].b = b;
2125 stubs[stubcount].c = c;
2126 stubs[stubcount].d = d;
2127 stubs[stubcount].e = e;
2131 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2132 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2134 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2137 // Write out a single register
2138 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2141 for(hr=0;hr<HOST_REGS;hr++) {
2142 if(hr!=EXCLUDE_REG) {
2145 assert(regmap[hr]<64);
2146 emit_storereg(r,hr);
2153 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2155 //if(dirty_pre==dirty) return;
2157 for(hr=0;hr<HOST_REGS;hr++) {
2158 if(hr!=EXCLUDE_REG) {
2162 if(((dirty_pre&~dirty)>>hr)&1) {
2164 emit_storereg(reg,hr);
2177 static void pass_args(int a0, int a1)
2181 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2183 else if(a0!=0&&a1==0) {
2185 if (a0>=0) emit_mov(a0,0);
2188 if(a0>=0&&a0!=0) emit_mov(a0,0);
2189 if(a1>=0&&a1!=1) emit_mov(a1,1);
2193 static void alu_assemble(int i, const struct regstat *i_regs)
2195 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2197 signed char s1,s2,t;
2198 t=get_reg(i_regs->regmap,dops[i].rt1);
2200 s1=get_reg(i_regs->regmap,dops[i].rs1);
2201 s2=get_reg(i_regs->regmap,dops[i].rs2);
2202 if(dops[i].rs1&&dops[i].rs2) {
2205 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2206 else emit_add(s1,s2,t);
2208 else if(dops[i].rs1) {
2209 if(s1>=0) emit_mov(s1,t);
2210 else emit_loadreg(dops[i].rs1,t);
2212 else if(dops[i].rs2) {
2214 if(dops[i].opcode2&2) emit_neg(s2,t);
2215 else emit_mov(s2,t);
2218 emit_loadreg(dops[i].rs2,t);
2219 if(dops[i].opcode2&2) emit_neg(t,t);
2222 else emit_zeroreg(t);
2226 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2229 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2231 signed char s1l,s2l,t;
2233 t=get_reg(i_regs->regmap,dops[i].rt1);
2236 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2237 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2238 if(dops[i].rs2==0) // rx<r0
2240 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2242 emit_shrimm(s1l,31,t);
2244 else // SLTU (unsigned can not be less than zero, 0<0)
2247 else if(dops[i].rs1==0) // r0<rx
2250 if(dops[i].opcode2==0x2a) // SLT
2251 emit_set_gz32(s2l,t);
2252 else // SLTU (set if not zero)
2253 emit_set_nz32(s2l,t);
2256 assert(s1l>=0);assert(s2l>=0);
2257 if(dops[i].opcode2==0x2a) // SLT
2258 emit_set_if_less32(s1l,s2l,t);
2260 emit_set_if_carry32(s1l,s2l,t);
2266 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2268 signed char s1l,s2l,tl;
2269 tl=get_reg(i_regs->regmap,dops[i].rt1);
2272 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2273 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2274 if(dops[i].rs1&&dops[i].rs2) {
2277 if(dops[i].opcode2==0x24) { // AND
2278 emit_and(s1l,s2l,tl);
2280 if(dops[i].opcode2==0x25) { // OR
2281 emit_or(s1l,s2l,tl);
2283 if(dops[i].opcode2==0x26) { // XOR
2284 emit_xor(s1l,s2l,tl);
2286 if(dops[i].opcode2==0x27) { // NOR
2287 emit_or(s1l,s2l,tl);
2293 if(dops[i].opcode2==0x24) { // AND
2296 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2298 if(s1l>=0) emit_mov(s1l,tl);
2299 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2303 if(s2l>=0) emit_mov(s2l,tl);
2304 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2306 else emit_zeroreg(tl);
2308 if(dops[i].opcode2==0x27) { // NOR
2310 if(s1l>=0) emit_not(s1l,tl);
2312 emit_loadreg(dops[i].rs1,tl);
2318 if(s2l>=0) emit_not(s2l,tl);
2320 emit_loadreg(dops[i].rs2,tl);
2324 else emit_movimm(-1,tl);
2333 static void imm16_assemble(int i, const struct regstat *i_regs)
2335 if (dops[i].opcode==0x0f) { // LUI
2338 t=get_reg(i_regs->regmap,dops[i].rt1);
2341 if(!((i_regs->isconst>>t)&1))
2342 emit_movimm(imm[i]<<16,t);
2346 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2349 t=get_reg(i_regs->regmap,dops[i].rt1);
2350 s=get_reg(i_regs->regmap,dops[i].rs1);
2355 if(!((i_regs->isconst>>t)&1)) {
2357 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2358 emit_addimm(t,imm[i],t);
2360 if(!((i_regs->wasconst>>s)&1))
2361 emit_addimm(s,imm[i],t);
2363 emit_movimm(constmap[i][s]+imm[i],t);
2369 if(!((i_regs->isconst>>t)&1))
2370 emit_movimm(imm[i],t);
2375 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2378 tl=get_reg(i_regs->regmap,dops[i].rt1);
2379 sl=get_reg(i_regs->regmap,dops[i].rs1);
2383 emit_addimm(sl,imm[i],tl);
2385 emit_movimm(imm[i],tl);
2390 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2392 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2394 t=get_reg(i_regs->regmap,dops[i].rt1);
2395 sl=get_reg(i_regs->regmap,dops[i].rs1);
2399 if(dops[i].opcode==0x0a) { // SLTI
2401 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2402 emit_slti32(t,imm[i],t);
2404 emit_slti32(sl,imm[i],t);
2409 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2410 emit_sltiu32(t,imm[i],t);
2412 emit_sltiu32(sl,imm[i],t);
2416 // SLTI(U) with r0 is just stupid,
2417 // nonetheless examples can be found
2418 if(dops[i].opcode==0x0a) // SLTI
2419 if(0<imm[i]) emit_movimm(1,t);
2420 else emit_zeroreg(t);
2423 if(imm[i]) emit_movimm(1,t);
2424 else emit_zeroreg(t);
2430 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2433 tl=get_reg(i_regs->regmap,dops[i].rt1);
2434 sl=get_reg(i_regs->regmap,dops[i].rs1);
2435 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2436 if(dops[i].opcode==0x0c) //ANDI
2440 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2441 emit_andimm(tl,imm[i],tl);
2443 if(!((i_regs->wasconst>>sl)&1))
2444 emit_andimm(sl,imm[i],tl);
2446 emit_movimm(constmap[i][sl]&imm[i],tl);
2456 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2458 if(dops[i].opcode==0x0d) { // ORI
2460 emit_orimm(tl,imm[i],tl);
2462 if(!((i_regs->wasconst>>sl)&1))
2463 emit_orimm(sl,imm[i],tl);
2465 emit_movimm(constmap[i][sl]|imm[i],tl);
2468 if(dops[i].opcode==0x0e) { // XORI
2470 emit_xorimm(tl,imm[i],tl);
2472 if(!((i_regs->wasconst>>sl)&1))
2473 emit_xorimm(sl,imm[i],tl);
2475 emit_movimm(constmap[i][sl]^imm[i],tl);
2480 emit_movimm(imm[i],tl);
2488 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2490 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2494 t=get_reg(i_regs->regmap,dops[i].rt1);
2495 s=get_reg(i_regs->regmap,dops[i].rs1);
2497 if(t>=0&&!((i_regs->isconst>>t)&1)){
2504 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2506 if(dops[i].opcode2==0) // SLL
2508 emit_shlimm(s<0?t:s,imm[i],t);
2510 if(dops[i].opcode2==2) // SRL
2512 emit_shrimm(s<0?t:s,imm[i],t);
2514 if(dops[i].opcode2==3) // SRA
2516 emit_sarimm(s<0?t:s,imm[i],t);
2520 if(s>=0 && s!=t) emit_mov(s,t);
2524 //emit_storereg(dops[i].rt1,t); //DEBUG
2527 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2531 if(dops[i].opcode2==0x3c) // DSLL32
2535 if(dops[i].opcode2==0x3e) // DSRL32
2539 if(dops[i].opcode2==0x3f) // DSRA32
2545 #ifndef shift_assemble
2546 static void shift_assemble(int i, const struct regstat *i_regs)
2548 signed char s,t,shift;
2549 if (dops[i].rt1 == 0)
2551 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2552 t = get_reg(i_regs->regmap, dops[i].rt1);
2553 s = get_reg(i_regs->regmap, dops[i].rs1);
2554 shift = get_reg(i_regs->regmap, dops[i].rs2);
2560 else if(dops[i].rs2==0) {
2562 if(s!=t) emit_mov(s,t);
2565 host_tempreg_acquire();
2566 emit_andimm(shift,31,HOST_TEMPREG);
2567 switch(dops[i].opcode2) {
2569 emit_shl(s,HOST_TEMPREG,t);
2572 emit_shr(s,HOST_TEMPREG,t);
2575 emit_sar(s,HOST_TEMPREG,t);
2580 host_tempreg_release();
2594 static int get_ptr_mem_type(u_int a)
2596 if(a < 0x00200000) {
2597 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2598 // return wrong, must use memhandler for BIOS self-test to pass
2599 // 007 does similar stuff from a00 mirror, weird stuff
2603 if(0x1f800000 <= a && a < 0x1f801000)
2605 if(0x80200000 <= a && a < 0x80800000)
2607 if(0xa0000000 <= a && a < 0xa0200000)
2612 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2614 int r = get_reg(i_regs->regmap, ROREG);
2615 if (r < 0 && host_tempreg_free) {
2616 host_tempreg_acquire();
2617 emit_loadreg(ROREG, r = HOST_TEMPREG);
2624 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2625 int addr, int *offset_reg, int *addr_reg_override)
2629 int mr = dops[i].rs1;
2631 if(((smrv_strong|smrv_weak)>>mr)&1) {
2632 type=get_ptr_mem_type(smrv[mr]);
2633 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2636 // use the mirror we are running on
2637 type=get_ptr_mem_type(start);
2638 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2641 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2642 host_tempreg_acquire();
2643 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2644 addr=*addr_reg_override=HOST_TEMPREG;
2647 else if(type==MTYPE_0000) { // RAM 0 mirror
2648 host_tempreg_acquire();
2649 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2650 addr=*addr_reg_override=HOST_TEMPREG;
2653 else if(type==MTYPE_A000) { // RAM A mirror
2654 host_tempreg_acquire();
2655 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2656 addr=*addr_reg_override=HOST_TEMPREG;
2659 else if(type==MTYPE_1F80) { // scratchpad
2660 if (psxH == (void *)0x1f800000) {
2661 host_tempreg_acquire();
2662 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2663 emit_cmpimm(HOST_TEMPREG,0x1000);
2664 host_tempreg_release();
2669 // do the usual RAM check, jump will go to the right handler
2674 if (type == 0) // need ram check
2676 emit_cmpimm(addr,RAM_SIZE);
2678 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2679 // Hint to branch predictor that the branch is unlikely to be taken
2680 if (dops[i].rs1 >= 28)
2681 emit_jno_unlikely(0);
2685 if (ram_offset != 0)
2686 *offset_reg = get_ro_reg(i_regs, 0);
2692 // return memhandler, or get directly accessable address and return 0
2693 static void *get_direct_memhandler(void *table, u_int addr,
2694 enum stub_type type, uintptr_t *addr_host)
2696 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2697 uintptr_t l1, l2 = 0;
2698 l1 = ((uintptr_t *)table)[addr>>12];
2700 uintptr_t v = l1 << 1;
2701 *addr_host = v + addr;
2706 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2707 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2708 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2709 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2711 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2713 uintptr_t v = l2 << 1;
2714 *addr_host = v + (addr&0xfff);
2717 return (void *)(l2 << 1);
2721 static u_int get_host_reglist(const signed char *regmap)
2723 u_int reglist = 0, hr;
2724 for (hr = 0; hr < HOST_REGS; hr++) {
2725 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2731 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2734 reglist &= ~(1u << r1);
2736 reglist &= ~(1u << r2);
2740 // find a temp caller-saved register not in reglist (so assumed to be free)
2741 static int reglist_find_free(u_int reglist)
2743 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2746 return __builtin_ctz(free_regs);
2749 static void do_load_word(int a, int rt, int offset_reg)
2751 if (offset_reg >= 0)
2752 emit_ldr_dualindexed(offset_reg, a, rt);
2754 emit_readword_indexed(0, a, rt);
2757 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2759 if (offset_reg < 0) {
2760 emit_writeword_indexed(rt, ofs, a);
2764 emit_addimm(a, ofs, a);
2765 emit_str_dualindexed(offset_reg, a, rt);
2766 if (ofs != 0 && preseve_a)
2767 emit_addimm(a, -ofs, a);
2770 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2772 if (offset_reg < 0) {
2773 emit_writehword_indexed(rt, ofs, a);
2777 emit_addimm(a, ofs, a);
2778 emit_strh_dualindexed(offset_reg, a, rt);
2779 if (ofs != 0 && preseve_a)
2780 emit_addimm(a, -ofs, a);
2783 static void do_store_byte(int a, int rt, int offset_reg)
2785 if (offset_reg >= 0)
2786 emit_strb_dualindexed(offset_reg, a, rt);
2788 emit_writebyte_indexed(rt, 0, a);
2791 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2796 int memtarget=0,c=0;
2797 int offset_reg = -1;
2798 int fastio_reg_override = -1;
2799 u_int reglist=get_host_reglist(i_regs->regmap);
2800 tl=get_reg(i_regs->regmap,dops[i].rt1);
2801 s=get_reg(i_regs->regmap,dops[i].rs1);
2803 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2805 c=(i_regs->wasconst>>s)&1;
2807 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2810 //printf("load_assemble: c=%d\n",c);
2811 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2812 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2813 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2815 // could be FIFO, must perform the read
2817 assem_debug("(forced read)\n");
2818 tl=get_reg_temp(i_regs->regmap);
2821 if(offset||s<0||c) addr=tl;
2823 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
2825 //printf("load_assemble: c=%d\n",c);
2826 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2827 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2831 // Strmnnrmn's speed hack
2832 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2835 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2836 &offset_reg, &fastio_reg_override);
2839 else if (ram_offset && memtarget) {
2840 offset_reg = get_ro_reg(i_regs, 0);
2842 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2843 switch (dops[i].opcode) {
2849 if (fastio_reg_override >= 0)
2850 a = fastio_reg_override;
2852 if (offset_reg >= 0)
2853 emit_ldrsb_dualindexed(offset_reg, a, tl);
2855 emit_movsbl_indexed(0, a, tl);
2858 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2861 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2868 if (fastio_reg_override >= 0)
2869 a = fastio_reg_override;
2870 if (offset_reg >= 0)
2871 emit_ldrsh_dualindexed(offset_reg, a, tl);
2873 emit_movswl_indexed(0, a, tl);
2876 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2879 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2885 if (fastio_reg_override >= 0)
2886 a = fastio_reg_override;
2887 do_load_word(a, tl, offset_reg);
2890 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2893 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2900 if (fastio_reg_override >= 0)
2901 a = fastio_reg_override;
2903 if (offset_reg >= 0)
2904 emit_ldrb_dualindexed(offset_reg, a, tl);
2906 emit_movzbl_indexed(0, a, tl);
2909 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2912 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2919 if (fastio_reg_override >= 0)
2920 a = fastio_reg_override;
2921 if (offset_reg >= 0)
2922 emit_ldrh_dualindexed(offset_reg, a, tl);
2924 emit_movzwl_indexed(0, a, tl);
2927 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2930 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2938 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2939 host_tempreg_release();
2942 #ifndef loadlr_assemble
2943 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
2945 int s,tl,temp,temp2,addr;
2948 int memtarget=0,c=0;
2949 int offset_reg = -1;
2950 int fastio_reg_override = -1;
2951 u_int reglist=get_host_reglist(i_regs->regmap);
2952 tl=get_reg(i_regs->regmap,dops[i].rt1);
2953 s=get_reg(i_regs->regmap,dops[i].rs1);
2954 temp=get_reg_temp(i_regs->regmap);
2955 temp2=get_reg(i_regs->regmap,FTEMP);
2956 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2960 if(offset||s<0||c) addr=temp2;
2963 c=(i_regs->wasconst>>s)&1;
2965 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2969 emit_shlimm(addr,3,temp);
2970 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2971 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2973 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2975 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2976 &offset_reg, &fastio_reg_override);
2979 if (ram_offset && memtarget) {
2980 offset_reg = get_ro_reg(i_regs, 0);
2982 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2983 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2985 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2988 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2991 if (fastio_reg_override >= 0)
2992 a = fastio_reg_override;
2993 do_load_word(a, temp2, offset_reg);
2994 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2995 host_tempreg_release();
2996 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
2999 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3002 emit_andimm(temp,24,temp);
3003 if (dops[i].opcode==0x22) // LWL
3004 emit_xorimm(temp,24,temp);
3005 host_tempreg_acquire();
3006 emit_movimm(-1,HOST_TEMPREG);
3007 if (dops[i].opcode==0x26) {
3008 emit_shr(temp2,temp,temp2);
3009 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3011 emit_shl(temp2,temp,temp2);
3012 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3014 host_tempreg_release();
3015 emit_or(temp2,tl,tl);
3017 //emit_storereg(dops[i].rt1,tl); // DEBUG
3019 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3025 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3031 enum stub_type type=0;
3032 int memtarget=0,c=0;
3033 int agr=AGEN1+(i&1);
3034 int offset_reg = -1;
3035 int fastio_reg_override = -1;
3036 u_int reglist=get_host_reglist(i_regs->regmap);
3037 tl=get_reg(i_regs->regmap,dops[i].rs2);
3038 s=get_reg(i_regs->regmap,dops[i].rs1);
3039 temp=get_reg(i_regs->regmap,agr);
3040 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3043 c=(i_regs->wasconst>>s)&1;
3045 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3050 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3051 if(offset||s<0||c) addr=temp;
3054 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3055 &offset_reg, &fastio_reg_override);
3057 else if (ram_offset && memtarget) {
3058 offset_reg = get_ro_reg(i_regs, 0);
3061 switch (dops[i].opcode) {
3066 if (fastio_reg_override >= 0)
3067 a = fastio_reg_override;
3068 do_store_byte(a, tl, offset_reg);
3076 if (fastio_reg_override >= 0)
3077 a = fastio_reg_override;
3078 do_store_hword(a, 0, tl, offset_reg, 1);
3085 if (fastio_reg_override >= 0)
3086 a = fastio_reg_override;
3087 do_store_word(a, 0, tl, offset_reg, 1);
3095 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3096 host_tempreg_release();
3098 // PCSX store handlers don't check invcode again
3100 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3103 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3105 #ifdef DESTRUCTIVE_SHIFT
3106 // The x86 shift operation is 'destructive'; it overwrites the
3107 // source register, so we need to make a copy first and use that.
3110 #if defined(HOST_IMM8)
3111 int ir=get_reg(i_regs->regmap,INVCP);
3113 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3115 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3117 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3118 emit_callne(invalidate_addr_reg[addr]);
3122 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3126 u_int addr_val=constmap[i][s]+offset;
3128 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3129 } else if(c&&!memtarget) {
3130 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3132 // basic current block modification detection..
3133 // not looking back as that should be in mips cache already
3134 // (see Spyro2 title->attract mode)
3135 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3136 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3137 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3138 if(i_regs->regmap==regs[i].regmap) {
3139 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3140 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3141 emit_movimm(start+i*4+4,0);
3142 emit_writeword(0,&pcaddr);
3143 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3144 emit_far_call(get_addr_ht);
3150 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3156 void *case1, *case23, *case3;
3157 void *done0, *done1, *done2;
3158 int memtarget=0,c=0;
3159 int agr=AGEN1+(i&1);
3160 int offset_reg = -1;
3161 u_int reglist=get_host_reglist(i_regs->regmap);
3162 tl=get_reg(i_regs->regmap,dops[i].rs2);
3163 s=get_reg(i_regs->regmap,dops[i].rs1);
3164 temp=get_reg(i_regs->regmap,agr);
3165 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3168 c=(i_regs->isconst>>s)&1;
3170 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3176 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3177 if(!offset&&s!=temp) emit_mov(s,temp);
3183 if(!memtarget||!dops[i].rs1) {
3189 offset_reg = get_ro_reg(i_regs, 0);
3191 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3195 emit_testimm(temp,2);
3198 emit_testimm(temp,1);
3202 if (dops[i].opcode == 0x2A) { // SWL
3203 // Write msb into least significant byte
3204 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3205 do_store_byte(temp, tl, offset_reg);
3206 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3208 else if (dops[i].opcode == 0x2E) { // SWR
3209 // Write entire word
3210 do_store_word(temp, 0, tl, offset_reg, 1);
3215 set_jump_target(case1, out);
3216 if (dops[i].opcode == 0x2A) { // SWL
3217 // Write two msb into two least significant bytes
3218 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3219 do_store_hword(temp, -1, tl, offset_reg, 0);
3220 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3222 else if (dops[i].opcode == 0x2E) { // SWR
3223 // Write 3 lsb into three most significant bytes
3224 do_store_byte(temp, tl, offset_reg);
3225 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3226 do_store_hword(temp, 1, tl, offset_reg, 0);
3227 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3232 set_jump_target(case23, out);
3233 emit_testimm(temp,1);
3237 if (dops[i].opcode==0x2A) { // SWL
3238 // Write 3 msb into three least significant bytes
3239 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3240 do_store_hword(temp, -2, tl, offset_reg, 1);
3241 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3242 do_store_byte(temp, tl, offset_reg);
3243 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3245 else if (dops[i].opcode == 0x2E) { // SWR
3246 // Write two lsb into two most significant bytes
3247 do_store_hword(temp, 0, tl, offset_reg, 1);
3252 set_jump_target(case3, out);
3253 if (dops[i].opcode == 0x2A) { // SWL
3254 do_store_word(temp, -3, tl, offset_reg, 0);
3256 else if (dops[i].opcode == 0x2E) { // SWR
3257 do_store_byte(temp, tl, offset_reg);
3259 set_jump_target(done0, out);
3260 set_jump_target(done1, out);
3261 set_jump_target(done2, out);
3262 if (offset_reg == HOST_TEMPREG)
3263 host_tempreg_release();
3265 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3266 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3267 #if defined(HOST_IMM8)
3268 int ir=get_reg(i_regs->regmap,INVCP);
3270 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3272 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3274 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3275 emit_callne(invalidate_addr_reg[temp]);
3279 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3284 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3286 if(dops[i].opcode2==0) // MFC0
3288 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3289 u_int copr=(source[i]>>11)&0x1f;
3290 //assert(t>=0); // Why does this happen? OOT is weird
3291 if(t>=0&&dops[i].rt1!=0) {
3292 emit_readword(®_cop0[copr],t);
3295 else if(dops[i].opcode2==4) // MTC0
3297 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3298 char copr=(source[i]>>11)&0x1f;
3300 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3301 if(copr==9||copr==11||copr==12||copr==13) {
3302 emit_readword(&last_count,HOST_TEMPREG);
3303 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3304 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3305 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3306 emit_writeword(HOST_CCREG,&Count);
3308 // What a mess. The status register (12) can enable interrupts,
3309 // so needs a special case to handle a pending interrupt.
3310 // The interrupt must be taken immediately, because a subsequent
3311 // instruction might disable interrupts again.
3312 if(copr==12||copr==13) {
3314 // burn cycles to cause cc_interrupt, which will
3315 // reschedule next_interupt. Relies on CCREG from above.
3316 assem_debug("MTC0 DS %d\n", copr);
3317 emit_writeword(HOST_CCREG,&last_count);
3318 emit_movimm(0,HOST_CCREG);
3319 emit_storereg(CCREG,HOST_CCREG);
3320 emit_loadreg(dops[i].rs1,1);
3321 emit_movimm(copr,0);
3322 emit_far_call(pcsx_mtc0_ds);
3323 emit_loadreg(dops[i].rs1,s);
3326 emit_movimm(start+i*4+4,HOST_TEMPREG);
3327 emit_writeword(HOST_TEMPREG,&pcaddr);
3328 emit_movimm(0,HOST_TEMPREG);
3329 emit_writeword(HOST_TEMPREG,&pending_exception);
3332 emit_loadreg(dops[i].rs1,1);
3335 emit_movimm(copr,0);
3336 emit_far_call(pcsx_mtc0);
3337 if(copr==9||copr==11||copr==12||copr==13) {
3338 emit_readword(&Count,HOST_CCREG);
3339 emit_readword(&next_interupt,HOST_TEMPREG);
3340 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3341 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3342 emit_writeword(HOST_TEMPREG,&last_count);
3343 emit_storereg(CCREG,HOST_CCREG);
3345 if(copr==12||copr==13) {
3346 assert(!is_delayslot);
3347 emit_readword(&pending_exception,14);
3351 emit_readword(&pcaddr, 0);
3352 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3353 emit_far_call(get_addr_ht);
3355 set_jump_target(jaddr, out);
3357 emit_loadreg(dops[i].rs1,s);
3361 assert(dops[i].opcode2==0x10);
3362 //if((source[i]&0x3f)==0x10) // RFE
3364 emit_readword(&Status,0);
3365 emit_andimm(0,0x3c,1);
3366 emit_andimm(0,~0xf,0);
3367 emit_orrshr_imm(1,2,0);
3368 emit_writeword(0,&Status);
3373 static void cop1_unusable(int i, const struct regstat *i_regs)
3375 // XXX: should just just do the exception instead
3380 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3384 static void cop1_assemble(int i, const struct regstat *i_regs)
3386 cop1_unusable(i, i_regs);
3389 static void c1ls_assemble(int i, const struct regstat *i_regs)
3391 cop1_unusable(i, i_regs);
3395 static void do_cop1stub(int n)
3398 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3399 set_jump_target(stubs[n].addr, out);
3401 // int rs=stubs[n].b;
3402 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3405 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3406 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3408 //else {printf("fp exception in delay slot\n");}
3409 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3410 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3411 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3412 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3413 emit_far_jump(ds?fp_exception_ds:fp_exception);
3416 static int cop2_is_stalling_op(int i, int *cycles)
3418 if (dops[i].opcode == 0x3a) { // SWC2
3422 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3426 if (dops[i].itype == C2OP) {
3427 *cycles = gte_cycletab[source[i] & 0x3f];
3430 // ... what about MTC2/CTC2/LWC2?
3435 static void log_gte_stall(int stall, u_int cycle)
3437 if ((u_int)stall <= 44)
3438 printf("x stall %2d %u\n", stall, cycle + last_count);
3441 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3445 emit_movimm(stall, 0);
3447 emit_mov(HOST_TEMPREG, 0);
3448 emit_addimm(HOST_CCREG, ccadj[i], 1);
3449 emit_far_call(log_gte_stall);
3450 restore_regs(reglist);
3454 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3456 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3457 int rtmp = reglist_find_free(reglist);
3459 if (HACK_ENABLED(NDHACK_NO_STALLS))
3461 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3462 // happens occasionally... cc evicted? Don't bother then
3463 //printf("no cc %08x\n", start + i*4);
3467 for (j = i - 1; j >= 0; j--) {
3468 //if (dops[j].is_ds) break;
3469 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3471 if (j > 0 && ccadj[j - 1] > ccadj[j])
3476 cycles_passed = ccadj[i] - ccadj[j];
3477 if (other_gte_op_cycles >= 0)
3478 stall = other_gte_op_cycles - cycles_passed;
3479 else if (cycles_passed >= 44)
3480 stall = 0; // can't stall
3481 if (stall == -MAXBLOCK && rtmp >= 0) {
3482 // unknown stall, do the expensive runtime check
3483 assem_debug("; cop2_do_stall_check\n");
3486 emit_movimm(gte_cycletab[op], 0);
3487 emit_addimm(HOST_CCREG, ccadj[i], 1);
3488 emit_far_call(call_gteStall);
3489 restore_regs(reglist);
3491 host_tempreg_acquire();
3492 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3493 emit_addimm(rtmp, -ccadj[i], rtmp);
3494 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3495 emit_cmpimm(HOST_TEMPREG, 44);
3496 emit_cmovb_reg(rtmp, HOST_CCREG);
3497 //emit_log_gte_stall(i, 0, reglist);
3498 host_tempreg_release();
3501 else if (stall > 0) {
3502 //emit_log_gte_stall(i, stall, reglist);
3503 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3506 // save gteBusyCycle, if needed
3507 if (gte_cycletab[op] == 0)
3509 other_gte_op_cycles = -1;
3510 for (j = i + 1; j < slen; j++) {
3511 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3513 if (dops[j].is_jump) {
3515 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3520 if (other_gte_op_cycles >= 0)
3521 // will handle stall when assembling that op
3523 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3524 if (cycles_passed >= 44)
3526 assem_debug("; save gteBusyCycle\n");
3527 host_tempreg_acquire();
3529 emit_readword(&last_count, HOST_TEMPREG);
3530 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3531 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3532 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3533 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3535 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3536 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3538 host_tempreg_release();
3541 static int is_mflohi(int i)
3543 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3546 static int check_multdiv(int i, int *cycles)
3548 if (dops[i].itype != MULTDIV)
3550 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3551 *cycles = 11; // approx from 7 11 14
3557 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3559 int j, found = 0, c = 0;
3560 if (HACK_ENABLED(NDHACK_NO_STALLS))
3562 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3563 // happens occasionally... cc evicted? Don't bother then
3566 for (j = i + 1; j < slen; j++) {
3569 if ((found = is_mflohi(j)))
3571 if (dops[j].is_jump) {
3573 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3579 // handle all in multdiv_do_stall()
3581 check_multdiv(i, &c);
3583 assem_debug("; muldiv prepare stall %d\n", c);
3584 host_tempreg_acquire();
3585 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3586 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3587 host_tempreg_release();
3590 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3592 int j, known_cycles = 0;
3593 u_int reglist = get_host_reglist(i_regs->regmap);
3594 int rtmp = get_reg_temp(i_regs->regmap);
3596 rtmp = reglist_find_free(reglist);
3597 if (HACK_ENABLED(NDHACK_NO_STALLS))
3599 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3600 // happens occasionally... cc evicted? Don't bother then
3601 //printf("no cc/rtmp %08x\n", start + i*4);
3605 for (j = i - 1; j >= 0; j--) {
3606 if (dops[j].is_ds) break;
3607 if (check_multdiv(j, &known_cycles))
3610 // already handled by this op
3612 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3617 if (known_cycles > 0) {
3618 known_cycles -= ccadj[i] - ccadj[j];
3619 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3620 if (known_cycles > 0)
3621 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3624 assem_debug("; muldiv stall unresolved\n");
3625 host_tempreg_acquire();
3626 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3627 emit_addimm(rtmp, -ccadj[i], rtmp);
3628 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3629 emit_cmpimm(HOST_TEMPREG, 37);
3630 emit_cmovb_reg(rtmp, HOST_CCREG);
3631 //emit_log_gte_stall(i, 0, reglist);
3632 host_tempreg_release();
3635 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3645 emit_readword(®_cop2d[copr],tl);
3646 emit_signextend16(tl,tl);
3647 emit_writeword(tl,®_cop2d[copr]); // hmh
3654 emit_readword(®_cop2d[copr],tl);
3655 emit_andimm(tl,0xffff,tl);
3656 emit_writeword(tl,®_cop2d[copr]);
3659 emit_readword(®_cop2d[14],tl); // SXY2
3660 emit_writeword(tl,®_cop2d[copr]);
3664 c2op_mfc2_29_assemble(tl,temp);
3667 emit_readword(®_cop2d[copr],tl);
3672 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3676 emit_readword(®_cop2d[13],temp); // SXY1
3677 emit_writeword(sl,®_cop2d[copr]);
3678 emit_writeword(temp,®_cop2d[12]); // SXY0
3679 emit_readword(®_cop2d[14],temp); // SXY2
3680 emit_writeword(sl,®_cop2d[14]);
3681 emit_writeword(temp,®_cop2d[13]); // SXY1
3684 emit_andimm(sl,0x001f,temp);
3685 emit_shlimm(temp,7,temp);
3686 emit_writeword(temp,®_cop2d[9]);
3687 emit_andimm(sl,0x03e0,temp);
3688 emit_shlimm(temp,2,temp);
3689 emit_writeword(temp,®_cop2d[10]);
3690 emit_andimm(sl,0x7c00,temp);
3691 emit_shrimm(temp,3,temp);
3692 emit_writeword(temp,®_cop2d[11]);
3693 emit_writeword(sl,®_cop2d[28]);
3696 emit_xorsar_imm(sl,sl,31,temp);
3697 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3698 emit_clz(temp,temp);
3700 emit_movs(temp,HOST_TEMPREG);
3701 emit_movimm(0,temp);
3702 emit_jeq((int)out+4*4);
3703 emit_addpl_imm(temp,1,temp);
3704 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3705 emit_jns((int)out-2*4);
3707 emit_writeword(sl,®_cop2d[30]);
3708 emit_writeword(temp,®_cop2d[31]);
3713 emit_writeword(sl,®_cop2d[copr]);
3718 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3723 int memtarget=0,c=0;
3725 enum stub_type type;
3726 int agr=AGEN1+(i&1);
3727 int offset_reg = -1;
3728 int fastio_reg_override = -1;
3729 u_int reglist=get_host_reglist(i_regs->regmap);
3730 u_int copr=(source[i]>>16)&0x1f;
3731 s=get_reg(i_regs->regmap,dops[i].rs1);
3732 tl=get_reg(i_regs->regmap,FTEMP);
3734 assert(dops[i].rs1>0);
3737 if(i_regs->regmap[HOST_CCREG]==CCREG)
3738 reglist&=~(1<<HOST_CCREG);
3741 if (dops[i].opcode==0x3a) { // SWC2
3742 ar=get_reg(i_regs->regmap,agr);
3743 if(ar<0) ar=get_reg_temp(i_regs->regmap);
3748 if(s>=0) c=(i_regs->wasconst>>s)&1;
3749 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3750 if (!offset&&!c&&s>=0) ar=s;
3753 cop2_do_stall_check(0, i, i_regs, reglist);
3755 if (dops[i].opcode==0x3a) { // SWC2
3756 cop2_get_dreg(copr,tl,-1);
3764 emit_jmp(0); // inline_readstub/inline_writestub?
3768 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3769 &offset_reg, &fastio_reg_override);
3771 else if (ram_offset && memtarget) {
3772 offset_reg = get_ro_reg(i_regs, 0);
3774 switch (dops[i].opcode) {
3775 case 0x32: { // LWC2
3777 if (fastio_reg_override >= 0)
3778 a = fastio_reg_override;
3779 do_load_word(a, tl, offset_reg);
3782 case 0x3a: { // SWC2
3783 #ifdef DESTRUCTIVE_SHIFT
3784 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3787 if (fastio_reg_override >= 0)
3788 a = fastio_reg_override;
3789 do_store_word(a, 0, tl, offset_reg, 1);
3796 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3797 host_tempreg_release();
3799 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3800 if(dops[i].opcode==0x3a) // SWC2
3801 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3802 #if defined(HOST_IMM8)
3803 int ir=get_reg(i_regs->regmap,INVCP);
3805 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3807 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3809 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3810 emit_callne(invalidate_addr_reg[ar]);
3814 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3817 if (dops[i].opcode==0x32) { // LWC2
3818 host_tempreg_acquire();
3819 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3820 host_tempreg_release();
3824 static void cop2_assemble(int i, const struct regstat *i_regs)
3826 u_int copr = (source[i]>>11) & 0x1f;
3827 signed char temp = get_reg_temp(i_regs->regmap);
3829 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3830 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3831 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3832 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3833 reglist = reglist_exclude(reglist, tl, -1);
3835 cop2_do_stall_check(0, i, i_regs, reglist);
3837 if (dops[i].opcode2==0) { // MFC2
3838 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3839 if(tl>=0&&dops[i].rt1!=0)
3840 cop2_get_dreg(copr,tl,temp);
3842 else if (dops[i].opcode2==4) { // MTC2
3843 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3844 cop2_put_dreg(copr,sl,temp);
3846 else if (dops[i].opcode2==2) // CFC2
3848 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3849 if(tl>=0&&dops[i].rt1!=0)
3850 emit_readword(®_cop2c[copr],tl);
3852 else if (dops[i].opcode2==6) // CTC2
3854 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3863 emit_signextend16(sl,temp);
3866 c2op_ctc2_31_assemble(sl,temp);
3872 emit_writeword(temp,®_cop2c[copr]);
3877 static void do_unalignedwritestub(int n)
3879 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3881 set_jump_target(stubs[n].addr, out);
3884 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3885 int addr=stubs[n].b;
3886 u_int reglist=stubs[n].e;
3887 signed char *i_regmap=i_regs->regmap;
3888 int temp2=get_reg(i_regmap,FTEMP);
3890 rt=get_reg(i_regmap,dops[i].rs2);
3893 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3895 reglist&=~(1<<temp2);
3897 // don't bother with it and call write handler
3900 int cc=get_reg(i_regmap,CCREG);
3902 emit_loadreg(CCREG,2);
3903 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3904 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3905 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3907 emit_storereg(CCREG,2);
3908 restore_regs(reglist);
3909 emit_jmp(stubs[n].retaddr); // return address
3912 #ifndef multdiv_assemble
3913 void multdiv_assemble(int i,struct regstat *i_regs)
3915 printf("Need multdiv_assemble for this architecture.\n");
3920 static void mov_assemble(int i, const struct regstat *i_regs)
3922 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3923 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3926 tl=get_reg(i_regs->regmap,dops[i].rt1);
3929 sl=get_reg(i_regs->regmap,dops[i].rs1);
3930 if(sl>=0) emit_mov(sl,tl);
3931 else emit_loadreg(dops[i].rs1,tl);
3934 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3935 multdiv_do_stall(i, i_regs);
3938 // call interpreter, exception handler, things that change pc/regs/cycles ...
3939 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3941 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3942 assert(ccreg==HOST_CCREG);
3943 assert(!is_delayslot);
3946 emit_movimm(pc,3); // Get PC
3947 emit_readword(&last_count,2);
3948 emit_writeword(3,&psxRegs.pc);
3949 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3950 emit_add(2,HOST_CCREG,2);
3951 emit_writeword(2,&psxRegs.cycle);
3952 emit_far_call(func);
3953 emit_far_jump(jump_to_new_pc);
3956 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3958 // 'break' tends to be littered around to catch things like
3959 // division by 0 and is almost never executed, so don't emit much code here
3960 void *func = (dops[i].opcode2 == 0x0C)
3961 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
3962 : (is_delayslot ? jump_break_ds : jump_break);
3963 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
3964 emit_movimm(start + i*4, 2); // pc
3965 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
3966 emit_far_jump(func);
3969 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3971 void *hlefunc = psxNULL;
3972 uint32_t hleCode = source[i] & 0x03ffffff;
3973 if (hleCode < ARRAY_SIZE(psxHLEt))
3974 hlefunc = psxHLEt[hleCode];
3976 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
3979 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3981 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
3984 static void speculate_mov(int rs,int rt)
3987 smrv_strong_next|=1<<rt;
3992 static void speculate_mov_weak(int rs,int rt)
3995 smrv_weak_next|=1<<rt;
4000 static void speculate_register_values(int i)
4003 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4004 // gp,sp are likely to stay the same throughout the block
4005 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4006 smrv_weak_next=~smrv_strong_next;
4007 //printf(" llr %08x\n", smrv[4]);
4009 smrv_strong=smrv_strong_next;
4010 smrv_weak=smrv_weak_next;
4011 switch(dops[i].itype) {
4013 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4014 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4015 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4016 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4018 smrv_strong_next&=~(1<<dops[i].rt1);
4019 smrv_weak_next&=~(1<<dops[i].rt1);
4023 smrv_strong_next&=~(1<<dops[i].rt1);
4024 smrv_weak_next&=~(1<<dops[i].rt1);
4027 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4028 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
4030 if(get_final_value(hr,i,&value))
4031 smrv[dops[i].rt1]=value;
4032 else smrv[dops[i].rt1]=constmap[i][hr];
4033 smrv_strong_next|=1<<dops[i].rt1;
4037 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4038 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4042 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4043 // special case for BIOS
4044 smrv[dops[i].rt1]=0xa0000000;
4045 smrv_strong_next|=1<<dops[i].rt1;
4052 smrv_strong_next&=~(1<<dops[i].rt1);
4053 smrv_weak_next&=~(1<<dops[i].rt1);
4057 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4058 smrv_strong_next&=~(1<<dops[i].rt1);
4059 smrv_weak_next&=~(1<<dops[i].rt1);
4063 if (dops[i].opcode==0x32) { // LWC2
4064 smrv_strong_next&=~(1<<dops[i].rt1);
4065 smrv_weak_next&=~(1<<dops[i].rt1);
4071 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4072 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4076 static void ujump_assemble(int i, const struct regstat *i_regs);
4077 static void rjump_assemble(int i, const struct regstat *i_regs);
4078 static void cjump_assemble(int i, const struct regstat *i_regs);
4079 static void sjump_assemble(int i, const struct regstat *i_regs);
4080 static void pagespan_assemble(int i, const struct regstat *i_regs);
4082 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4085 switch (dops[i].itype) {
4087 alu_assemble(i, i_regs);
4090 imm16_assemble(i, i_regs);
4093 shift_assemble(i, i_regs);
4096 shiftimm_assemble(i, i_regs);
4099 load_assemble(i, i_regs, ccadj_);
4102 loadlr_assemble(i, i_regs, ccadj_);
4105 store_assemble(i, i_regs, ccadj_);
4108 storelr_assemble(i, i_regs, ccadj_);
4111 cop0_assemble(i, i_regs, ccadj_);
4114 cop1_assemble(i, i_regs);
4117 c1ls_assemble(i, i_regs);
4120 cop2_assemble(i, i_regs);
4123 c2ls_assemble(i, i_regs, ccadj_);
4126 c2op_assemble(i, i_regs);
4129 multdiv_assemble(i, i_regs);
4130 multdiv_prepare_stall(i, i_regs, ccadj_);
4133 mov_assemble(i, i_regs);
4136 syscall_assemble(i, i_regs, ccadj_);
4139 hlecall_assemble(i, i_regs, ccadj_);
4142 intcall_assemble(i, i_regs, ccadj_);
4145 ujump_assemble(i, i_regs);
4149 rjump_assemble(i, i_regs);
4153 cjump_assemble(i, i_regs);
4157 sjump_assemble(i, i_regs);
4161 pagespan_assemble(i, i_regs);
4166 // not handled, just skip
4174 static void ds_assemble(int i, const struct regstat *i_regs)
4176 speculate_register_values(i);
4178 switch (dops[i].itype) {
4187 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4190 assemble(i, i_regs, ccadj[i]);
4195 // Is the branch target a valid internal jump?
4196 static int internal_branch(int addr)
4198 if(addr&1) return 0; // Indirect (register) jump
4199 if(addr>=start && addr<start+slen*4-4)
4206 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4209 for(hr=0;hr<HOST_REGS;hr++) {
4210 if(hr!=EXCLUDE_REG) {
4211 if(pre[hr]!=entry[hr]) {
4214 if(get_reg(entry,pre[hr])<0) {
4216 if(!((u>>pre[hr])&1))
4217 emit_storereg(pre[hr],hr);
4224 // Move from one register to another (no writeback)
4225 for(hr=0;hr<HOST_REGS;hr++) {
4226 if(hr!=EXCLUDE_REG) {
4227 if(pre[hr]!=entry[hr]) {
4228 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4230 if((nr=get_reg(entry,pre[hr]))>=0) {
4239 // Load the specified registers
4240 // This only loads the registers given as arguments because
4241 // we don't want to load things that will be overwritten
4242 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4246 for(hr=0;hr<HOST_REGS;hr++) {
4247 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4248 if(entry[hr]!=regmap[hr]) {
4249 if(regmap[hr]==rs1||regmap[hr]==rs2)
4256 emit_loadreg(regmap[hr],hr);
4264 // Load registers prior to the start of a loop
4265 // so that they are not loaded within the loop
4266 static void loop_preload(signed char pre[],signed char entry[])
4269 for(hr=0;hr<HOST_REGS;hr++) {
4270 if(hr!=EXCLUDE_REG) {
4271 if(pre[hr]!=entry[hr]) {
4273 if(get_reg(pre,entry[hr])<0) {
4274 assem_debug("loop preload:\n");
4275 //printf("loop preload: %d\n",hr);
4279 else if(entry[hr]<TEMPREG)
4281 emit_loadreg(entry[hr],hr);
4283 else if(entry[hr]-64<TEMPREG)
4285 emit_loadreg(entry[hr],hr);
4294 // Generate address for load/store instruction
4295 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4296 void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4298 if (dops[i].is_load || dops[i].is_store) {
4300 int agr=AGEN1+(i&1);
4301 if(dops[i].itype==LOAD) {
4302 ra=get_reg(i_regs->regmap,dops[i].rt1);
4303 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4306 if(dops[i].itype==LOADLR) {
4307 ra=get_reg(i_regs->regmap,FTEMP);
4309 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4310 ra=get_reg(i_regs->regmap,agr);
4311 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4313 if(dops[i].itype==C2LS) {
4314 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4315 ra=get_reg(i_regs->regmap,FTEMP);
4316 else { // SWC1/SDC1/SWC2/SDC2
4317 ra=get_reg(i_regs->regmap,agr);
4318 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4321 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4324 int c=(i_regs->wasconst>>rs)&1;
4325 if(dops[i].rs1==0) {
4326 // Using r0 as a base address
4327 if(!entry||entry[ra]!=agr) {
4328 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4329 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4330 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4331 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4333 emit_movimm(offset,ra);
4335 } // else did it in the previous cycle
4338 if(!entry||entry[ra]!=dops[i].rs1)
4339 emit_loadreg(dops[i].rs1,ra);
4340 //if(!entry||entry[ra]!=dops[i].rs1)
4341 // printf("poor load scheduling!\n");
4344 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4345 if(!entry||entry[ra]!=agr) {
4346 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4347 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4348 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4349 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4351 emit_movimm(constmap[i][rs]+offset,ra);
4352 regs[i].loadedconst|=1<<ra;
4354 } // else did it in the previous cycle
4355 } // else load_consts already did it
4357 if(offset&&!c&&dops[i].rs1) {
4359 emit_addimm(rs,offset,ra);
4361 emit_addimm(ra,offset,ra);
4366 // Preload constants for next instruction
4367 if (dops[i+1].is_load || dops[i+1].is_store) {
4370 agr=AGEN1+((i+1)&1);
4371 ra=get_reg(i_regs->regmap,agr);
4373 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4374 int offset=imm[i+1];
4375 int c=(regs[i+1].wasconst>>rs)&1;
4376 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4377 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4378 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4379 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4380 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4382 emit_movimm(constmap[i+1][rs]+offset,ra);
4383 regs[i+1].loadedconst|=1<<ra;
4386 else if(dops[i+1].rs1==0) {
4387 // Using r0 as a base address
4388 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4389 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4390 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4391 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4393 emit_movimm(offset,ra);
4400 static int get_final_value(int hr, int i, int *value)
4402 int reg=regs[i].regmap[hr];
4404 if(regs[i+1].regmap[hr]!=reg) break;
4405 if(!((regs[i+1].isconst>>hr)&1)) break;
4406 if(dops[i+1].bt) break;
4410 if (dops[i].is_jump) {
4411 *value=constmap[i][hr];
4415 if (dops[i+1].is_jump) {
4416 // Load in delay slot, out-of-order execution
4417 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4419 // Precompute load address
4420 *value=constmap[i][hr]+imm[i+2];
4424 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4426 // Precompute load address
4427 *value=constmap[i][hr]+imm[i+1];
4428 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4433 *value=constmap[i][hr];
4434 //printf("c=%lx\n",(long)constmap[i][hr]);
4435 if(i==slen-1) return 1;
4437 return !((unneeded_reg[i+1]>>reg)&1);
4440 // Load registers with known constants
4441 static void load_consts(signed char pre[],signed char regmap[],int i)
4444 // propagate loaded constant flags
4445 if(i==0||dops[i].bt)
4446 regs[i].loadedconst=0;
4448 for(hr=0;hr<HOST_REGS;hr++) {
4449 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4450 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4452 regs[i].loadedconst|=1<<hr;
4457 for(hr=0;hr<HOST_REGS;hr++) {
4458 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4459 //if(entry[hr]!=regmap[hr]) {
4460 if(!((regs[i].loadedconst>>hr)&1)) {
4461 assert(regmap[hr]<64);
4462 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4463 int value,similar=0;
4464 if(get_final_value(hr,i,&value)) {
4465 // see if some other register has similar value
4466 for(hr2=0;hr2<HOST_REGS;hr2++) {
4467 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4468 if(is_similar_value(value,constmap[i][hr2])) {
4476 if(get_final_value(hr2,i,&value2)) // is this needed?
4477 emit_movimm_from(value2,hr2,value,hr);
4479 emit_movimm(value,hr);
4485 emit_movimm(value,hr);
4488 regs[i].loadedconst|=1<<hr;
4495 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4499 for(hr=0;hr<HOST_REGS;hr++) {
4500 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4501 assert(regmap[hr] < 64);
4502 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4503 int value=constmap[i][hr];
4508 emit_movimm(value,hr);
4515 // Write out all dirty registers (except cycle count)
4516 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4519 for(hr=0;hr<HOST_REGS;hr++) {
4520 if(hr!=EXCLUDE_REG) {
4521 if(i_regmap[hr]>0) {
4522 if(i_regmap[hr]!=CCREG) {
4523 if((i_dirty>>hr)&1) {
4524 assert(i_regmap[hr]<64);
4525 emit_storereg(i_regmap[hr],hr);
4533 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4534 // This writes the registers not written by store_regs_bt
4535 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4538 int t=(addr-start)>>2;
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG) {
4541 if(i_regmap[hr]>0) {
4542 if(i_regmap[hr]!=CCREG) {
4543 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4544 if((i_dirty>>hr)&1) {
4545 assert(i_regmap[hr]<64);
4546 emit_storereg(i_regmap[hr],hr);
4555 // Load all registers (except cycle count)
4556 static void load_all_regs(const signed char i_regmap[])
4559 for(hr=0;hr<HOST_REGS;hr++) {
4560 if(hr!=EXCLUDE_REG) {
4561 if(i_regmap[hr]==0) {
4565 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4567 emit_loadreg(i_regmap[hr],hr);
4573 // Load all current registers also needed by next instruction
4574 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4577 for(hr=0;hr<HOST_REGS;hr++) {
4578 if(hr!=EXCLUDE_REG) {
4579 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4580 if(i_regmap[hr]==0) {
4584 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4586 emit_loadreg(i_regmap[hr],hr);
4593 // Load all regs, storing cycle count if necessary
4594 static void load_regs_entry(int t)
4597 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4598 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4599 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4600 emit_storereg(CCREG,HOST_CCREG);
4603 for(hr=0;hr<HOST_REGS;hr++) {
4604 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4605 if(regs[t].regmap_entry[hr]==0) {
4608 else if(regs[t].regmap_entry[hr]!=CCREG)
4610 emit_loadreg(regs[t].regmap_entry[hr],hr);
4616 // Store dirty registers prior to branch
4617 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4619 if(internal_branch(addr))
4621 int t=(addr-start)>>2;
4623 for(hr=0;hr<HOST_REGS;hr++) {
4624 if(hr!=EXCLUDE_REG) {
4625 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4626 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4627 if((i_dirty>>hr)&1) {
4628 assert(i_regmap[hr]<64);
4629 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4630 emit_storereg(i_regmap[hr],hr);
4639 // Branch out of this block, write out all dirty regs
4640 wb_dirtys(i_regmap,i_dirty);
4644 // Load all needed registers for branch target
4645 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4647 //if(addr>=start && addr<(start+slen*4))
4648 if(internal_branch(addr))
4650 int t=(addr-start)>>2;
4652 // Store the cycle count before loading something else
4653 if(i_regmap[HOST_CCREG]!=CCREG) {
4654 assert(i_regmap[HOST_CCREG]==-1);
4656 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4657 emit_storereg(CCREG,HOST_CCREG);
4660 for(hr=0;hr<HOST_REGS;hr++) {
4661 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4662 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4663 if(regs[t].regmap_entry[hr]==0) {
4666 else if(regs[t].regmap_entry[hr]!=CCREG)
4668 emit_loadreg(regs[t].regmap_entry[hr],hr);
4676 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4678 if(addr>=start && addr<start+slen*4-4)
4680 int t=(addr-start)>>2;
4682 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4683 for(hr=0;hr<HOST_REGS;hr++)
4687 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4689 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4696 if(i_regmap[hr]<TEMPREG)
4698 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4701 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4707 else // Same register but is it 32-bit or dirty?
4710 if(!((regs[t].dirty>>hr)&1))
4714 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4716 //printf("%x: dirty no match\n",addr);
4724 // Delay slots are not valid branch targets
4725 //if(t>0&&(dops[t-1].is_jump) return 0;
4726 // Delay slots require additional processing, so do not match
4727 if(dops[t].is_ds) return 0;
4732 for(hr=0;hr<HOST_REGS;hr++)
4738 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4753 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4755 extern void do_insn_cmp();
4757 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4759 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4761 // write out changed consts to match the interpreter
4762 if (i > 0 && !dops[i].bt) {
4763 for (hr = 0; hr < HOST_REGS; hr++) {
4764 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4765 if (hr == EXCLUDE_REG || reg < 0)
4767 if (!((regs[i-1].isconst >> hr) & 1))
4769 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4771 emit_movimm(constmap[i-1][hr],0);
4772 emit_storereg(reg, 0);
4775 emit_movimm(start+i*4,0);
4776 emit_writeword(0,&pcaddr);
4777 int cc = get_reg(regs[i].regmap_entry, CCREG);
4779 emit_loadreg(CCREG, cc = 0);
4780 emit_addimm(cc, ccadj_, 0);
4781 emit_writeword(0, &psxRegs.cycle);
4782 emit_far_call(do_insn_cmp);
4783 //emit_readword(&cycle,0);
4784 //emit_addimm(0,2,0);
4785 //emit_writeword(0,&cycle);
4787 restore_regs(reglist);
4788 assem_debug("\\\\do_insn_cmp\n");
4791 #define drc_dbg_emit_do_cmp(x,y)
4794 // Used when a branch jumps into the delay slot of another branch
4795 static void ds_assemble_entry(int i)
4797 int t = (ba[i] - start) >> 2;
4798 int ccadj_ = -CLOCK_ADJUST(1);
4800 instr_addr[t] = out;
4801 assem_debug("Assemble delay slot at %x\n",ba[i]);
4802 assem_debug("<->\n");
4803 drc_dbg_emit_do_cmp(t, ccadj_);
4804 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4805 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4806 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4807 address_generation(t,®s[t],regs[t].regmap_entry);
4808 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4809 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4810 if (dops[t].is_store)
4811 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4813 switch (dops[t].itype) {
4822 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4825 assemble(t, ®s[t], ccadj_);
4827 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4828 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4829 if(internal_branch(ba[i]+4))
4830 assem_debug("branch: internal\n");
4832 assem_debug("branch: external\n");
4833 assert(internal_branch(ba[i]+4));
4834 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4838 static void emit_extjump(void *addr, u_int target)
4840 emit_extjump2(addr, target, dyna_linker);
4843 static void emit_extjump_ds(void *addr, u_int target)
4845 emit_extjump2(addr, target, dyna_linker_ds);
4848 // Load 2 immediates optimizing for small code size
4849 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4851 emit_movimm(imm1,rt1);
4852 emit_movimm_from(imm1,rt1,imm2,rt2);
4855 static void do_cc(int i, const signed char i_regmap[], int *adj,
4856 int addr, int taken, int invert)
4858 int count, count_plus2;
4862 if(dops[i].itype==RJUMP)
4866 //if(ba[i]>=start && ba[i]<(start+slen*4))
4867 if(internal_branch(ba[i]))
4870 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4878 count_plus2 = count + CLOCK_ADJUST(2);
4879 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4881 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4883 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4884 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4888 else if(*adj==0||invert) {
4889 int cycles = count_plus2;
4894 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4895 cycles=*adj+count+2-*adj;
4898 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4904 emit_cmpimm(HOST_CCREG, -count_plus2);
4908 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4911 static void do_ccstub(int n)
4914 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4915 set_jump_target(stubs[n].addr, out);
4917 if(stubs[n].d==NULLDS) {
4918 // Delay slot instruction is nullified ("likely" branch)
4919 wb_dirtys(regs[i].regmap,regs[i].dirty);
4921 else if(stubs[n].d!=TAKEN) {
4922 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4925 if(internal_branch(ba[i]))
4926 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4930 // Save PC as return address
4931 emit_movimm(stubs[n].c,EAX);
4932 emit_writeword(EAX,&pcaddr);
4936 // Return address depends on which way the branch goes
4937 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4939 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4940 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4946 else if(dops[i].rs2==0)
4951 #ifdef DESTRUCTIVE_WRITEBACK
4953 if((branch_regs[i].dirty>>s1l)&&1)
4954 emit_loadreg(dops[i].rs1,s1l);
4957 if((branch_regs[i].dirty>>s1l)&1)
4958 emit_loadreg(dops[i].rs2,s1l);
4961 if((branch_regs[i].dirty>>s2l)&1)
4962 emit_loadreg(dops[i].rs2,s2l);
4965 int addr=-1,alt=-1,ntaddr=-1;
4968 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4969 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4970 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4978 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4979 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4980 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4986 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4990 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4991 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4992 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4998 assert(hr<HOST_REGS);
5000 if((dops[i].opcode&0x2f)==4) // BEQ
5002 #ifdef HAVE_CMOV_IMM
5003 if(s2l>=0) emit_cmp(s1l,s2l);
5004 else emit_test(s1l,s1l);
5005 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5007 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5008 if(s2l>=0) emit_cmp(s1l,s2l);
5009 else emit_test(s1l,s1l);
5010 emit_cmovne_reg(alt,addr);
5013 if((dops[i].opcode&0x2f)==5) // BNE
5015 #ifdef HAVE_CMOV_IMM
5016 if(s2l>=0) emit_cmp(s1l,s2l);
5017 else emit_test(s1l,s1l);
5018 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5020 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5021 if(s2l>=0) emit_cmp(s1l,s2l);
5022 else emit_test(s1l,s1l);
5023 emit_cmovne_reg(alt,addr);
5026 if((dops[i].opcode&0x2f)==6) // BLEZ
5028 //emit_movimm(ba[i],alt);
5029 //emit_movimm(start+i*4+8,addr);
5030 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5032 emit_cmovl_reg(alt,addr);
5034 if((dops[i].opcode&0x2f)==7) // BGTZ
5036 //emit_movimm(ba[i],addr);
5037 //emit_movimm(start+i*4+8,ntaddr);
5038 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5040 emit_cmovl_reg(ntaddr,addr);
5042 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5044 //emit_movimm(ba[i],alt);
5045 //emit_movimm(start+i*4+8,addr);
5046 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5048 emit_cmovs_reg(alt,addr);
5050 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5052 //emit_movimm(ba[i],addr);
5053 //emit_movimm(start+i*4+8,alt);
5054 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5056 emit_cmovs_reg(alt,addr);
5058 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5059 if(source[i]&0x10000) // BC1T
5061 //emit_movimm(ba[i],alt);
5062 //emit_movimm(start+i*4+8,addr);
5063 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5064 emit_testimm(s1l,0x800000);
5065 emit_cmovne_reg(alt,addr);
5069 //emit_movimm(ba[i],addr);
5070 //emit_movimm(start+i*4+8,alt);
5071 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5072 emit_testimm(s1l,0x800000);
5073 emit_cmovne_reg(alt,addr);
5076 emit_writeword(addr,&pcaddr);
5079 if(dops[i].itype==RJUMP)
5081 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5082 if (ds_writes_rjump_rs(i)) {
5083 r=get_reg(branch_regs[i].regmap,RTEMP);
5085 emit_writeword(r,&pcaddr);
5087 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5089 // Update cycle count
5090 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5091 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5092 emit_far_call(cc_interrupt);
5093 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5094 if(stubs[n].d==TAKEN) {
5095 if(internal_branch(ba[i]))
5096 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5097 else if(dops[i].itype==RJUMP) {
5098 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5099 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5101 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5103 }else if(stubs[n].d==NOTTAKEN) {
5104 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5105 else load_all_regs(branch_regs[i].regmap);
5106 }else if(stubs[n].d==NULLDS) {
5107 // Delay slot instruction is nullified ("likely" branch)
5108 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5109 else load_all_regs(regs[i].regmap);
5111 load_all_regs(branch_regs[i].regmap);
5113 if (stubs[n].retaddr)
5114 emit_jmp(stubs[n].retaddr);
5116 do_jump_vaddr(stubs[n].e);
5119 static void add_to_linker(void *addr, u_int target, int ext)
5121 assert(linkcount < ARRAY_SIZE(link_addr));
5122 link_addr[linkcount].addr = addr;
5123 link_addr[linkcount].target = target;
5124 link_addr[linkcount].ext = ext;
5128 static void ujump_assemble_write_ra(int i)
5131 unsigned int return_address;
5132 rt=get_reg(branch_regs[i].regmap,31);
5133 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5135 return_address=start+i*4+8;
5138 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5139 int temp=-1; // note: must be ds-safe
5143 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5144 else emit_movimm(return_address,rt);
5152 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5155 emit_movimm(return_address,rt); // PC into link register
5157 emit_prefetch(hash_table_get(return_address));
5163 static void ujump_assemble(int i, const struct regstat *i_regs)
5166 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5167 address_generation(i+1,i_regs,regs[i].regmap_entry);
5169 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5170 if(dops[i].rt1==31&&temp>=0)
5172 signed char *i_regmap=i_regs->regmap;
5173 int return_address=start+i*4+8;
5174 if(get_reg(branch_regs[i].regmap,31)>0)
5175 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5178 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5179 ujump_assemble_write_ra(i); // writeback ra for DS
5182 ds_assemble(i+1,i_regs);
5183 uint64_t bc_unneeded=branch_regs[i].u;
5184 bc_unneeded|=1|(1LL<<dops[i].rt1);
5185 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5186 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5187 if(!ra_done&&dops[i].rt1==31)
5188 ujump_assemble_write_ra(i);
5190 cc=get_reg(branch_regs[i].regmap,CCREG);
5191 assert(cc==HOST_CCREG);
5192 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5194 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5196 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5197 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5198 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5199 if(internal_branch(ba[i]))
5200 assem_debug("branch: internal\n");
5202 assem_debug("branch: external\n");
5203 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5204 ds_assemble_entry(i);
5207 add_to_linker(out,ba[i],internal_branch(ba[i]));
5212 static void rjump_assemble_write_ra(int i)
5214 int rt,return_address;
5215 assert(dops[i+1].rt1!=dops[i].rt1);
5216 assert(dops[i+1].rt2!=dops[i].rt1);
5217 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5218 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5220 return_address=start+i*4+8;
5224 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5227 emit_movimm(return_address,rt); // PC into link register
5229 emit_prefetch(hash_table_get(return_address));
5233 static void rjump_assemble(int i, const struct regstat *i_regs)
5238 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5240 if (ds_writes_rjump_rs(i)) {
5241 // Delay slot abuse, make a copy of the branch address register
5242 temp=get_reg(branch_regs[i].regmap,RTEMP);
5244 assert(regs[i].regmap[temp]==RTEMP);
5248 address_generation(i+1,i_regs,regs[i].regmap_entry);
5252 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5253 signed char *i_regmap=i_regs->regmap;
5254 int return_address=start+i*4+8;
5255 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5260 if(dops[i].rs1==31) {
5261 int rh=get_reg(regs[i].regmap,RHASH);
5262 if(rh>=0) do_preload_rhash(rh);
5265 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5266 rjump_assemble_write_ra(i);
5269 ds_assemble(i+1,i_regs);
5270 uint64_t bc_unneeded=branch_regs[i].u;
5271 bc_unneeded|=1|(1LL<<dops[i].rt1);
5272 bc_unneeded&=~(1LL<<dops[i].rs1);
5273 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5274 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5275 if(!ra_done&&dops[i].rt1!=0)
5276 rjump_assemble_write_ra(i);
5277 cc=get_reg(branch_regs[i].regmap,CCREG);
5278 assert(cc==HOST_CCREG);
5281 int rh=get_reg(branch_regs[i].regmap,RHASH);
5282 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5283 if(dops[i].rs1==31) {
5284 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5285 do_preload_rhtbl(ht);
5289 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5290 #ifdef DESTRUCTIVE_WRITEBACK
5291 if((branch_regs[i].dirty>>rs)&1) {
5292 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5293 emit_loadreg(dops[i].rs1,rs);
5298 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5301 if(dops[i].rs1==31) {
5302 do_miniht_load(ht,rh);
5305 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5306 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5308 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5309 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5310 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5311 // special case for RFE
5315 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5317 if(dops[i].rs1==31) {
5318 do_miniht_jump(rs,rh,ht);
5325 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5326 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5330 static void cjump_assemble(int i, const struct regstat *i_regs)
5332 const signed char *i_regmap = i_regs->regmap;
5335 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5336 assem_debug("match=%d\n",match);
5338 int unconditional=0,nop=0;
5340 int internal=internal_branch(ba[i]);
5341 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5342 if(!match) invert=1;
5343 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5344 if(i>(ba[i]-start)>>2) invert=1;
5347 invert=1; // because of near cond. branches
5351 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5352 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5355 s1l=get_reg(i_regmap,dops[i].rs1);
5356 s2l=get_reg(i_regmap,dops[i].rs2);
5358 if(dops[i].rs1==0&&dops[i].rs2==0)
5360 if(dops[i].opcode&1) nop=1;
5361 else unconditional=1;
5362 //assert(dops[i].opcode!=5);
5363 //assert(dops[i].opcode!=7);
5364 //assert(dops[i].opcode!=0x15);
5365 //assert(dops[i].opcode!=0x17);
5367 else if(dops[i].rs1==0)
5372 else if(dops[i].rs2==0)
5378 // Out of order execution (delay slot first)
5380 address_generation(i+1,i_regs,regs[i].regmap_entry);
5381 ds_assemble(i+1,i_regs);
5383 uint64_t bc_unneeded=branch_regs[i].u;
5384 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5386 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5387 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5388 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5389 cc=get_reg(branch_regs[i].regmap,CCREG);
5390 assert(cc==HOST_CCREG);
5392 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5393 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5394 //assem_debug("cycle count (adj)\n");
5396 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5397 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5398 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5399 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5401 assem_debug("branch: internal\n");
5403 assem_debug("branch: external\n");
5404 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5405 ds_assemble_entry(i);
5408 add_to_linker(out,ba[i],internal);
5411 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5412 if(((u_int)out)&7) emit_addnop(0);
5417 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5420 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5423 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5424 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5425 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5427 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5429 if(dops[i].opcode==4) // BEQ
5431 if(s2l>=0) emit_cmp(s1l,s2l);
5432 else emit_test(s1l,s1l);
5437 add_to_linker(out,ba[i],internal);
5441 if(dops[i].opcode==5) // BNE
5443 if(s2l>=0) emit_cmp(s1l,s2l);
5444 else emit_test(s1l,s1l);
5449 add_to_linker(out,ba[i],internal);
5453 if(dops[i].opcode==6) // BLEZ
5460 add_to_linker(out,ba[i],internal);
5464 if(dops[i].opcode==7) // BGTZ
5471 add_to_linker(out,ba[i],internal);
5476 if(taken) set_jump_target(taken, out);
5477 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5478 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5480 emit_addimm(cc,-adj,cc);
5481 add_to_linker(out,ba[i],internal);
5484 add_to_linker(out,ba[i],internal*2);
5490 if(adj) emit_addimm(cc,-adj,cc);
5491 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5492 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5494 assem_debug("branch: internal\n");
5496 assem_debug("branch: external\n");
5497 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5498 ds_assemble_entry(i);
5501 add_to_linker(out,ba[i],internal);
5505 set_jump_target(nottaken, out);
5508 if(nottaken1) set_jump_target(nottaken1, out);
5510 if(!invert) emit_addimm(cc,adj,cc);
5512 } // (!unconditional)
5516 // In-order execution (branch first)
5517 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5518 if(!unconditional&&!nop) {
5519 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5521 if((dops[i].opcode&0x2f)==4) // BEQ
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
5528 if((dops[i].opcode&0x2f)==5) // BNE
5530 if(s2l>=0) emit_cmp(s1l,s2l);
5531 else emit_test(s1l,s1l);
5535 if((dops[i].opcode&0x2f)==6) // BLEZ
5541 if((dops[i].opcode&0x2f)==7) // BGTZ
5547 } // if(!unconditional)
5549 uint64_t ds_unneeded=branch_regs[i].u;
5550 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5554 if(taken) set_jump_target(taken, out);
5555 assem_debug("1:\n");
5556 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5558 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5559 address_generation(i+1,&branch_regs[i],0);
5561 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5562 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5563 ds_assemble(i+1,&branch_regs[i]);
5564 cc=get_reg(branch_regs[i].regmap,CCREG);
5566 emit_loadreg(CCREG,cc=HOST_CCREG);
5567 // CHECK: Is the following instruction (fall thru) allocated ok?
5569 assert(cc==HOST_CCREG);
5570 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5571 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5572 assem_debug("cycle count (adj)\n");
5573 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5574 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5576 assem_debug("branch: internal\n");
5578 assem_debug("branch: external\n");
5579 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5580 ds_assemble_entry(i);
5583 add_to_linker(out,ba[i],internal);
5588 if(!unconditional) {
5589 if(nottaken1) set_jump_target(nottaken1, out);
5590 set_jump_target(nottaken, out);
5591 assem_debug("2:\n");
5592 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5594 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5595 address_generation(i+1,&branch_regs[i],0);
5597 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5598 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5599 ds_assemble(i+1,&branch_regs[i]);
5600 cc=get_reg(branch_regs[i].regmap,CCREG);
5602 // Cycle count isn't in a register, temporarily load it then write it out
5603 emit_loadreg(CCREG,HOST_CCREG);
5604 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5607 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5608 emit_storereg(CCREG,HOST_CCREG);
5611 cc=get_reg(i_regmap,CCREG);
5612 assert(cc==HOST_CCREG);
5613 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5616 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5622 static void sjump_assemble(int i, const struct regstat *i_regs)
5624 const signed char *i_regmap = i_regs->regmap;
5627 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5628 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5630 int unconditional=0,nevertaken=0;
5632 int internal=internal_branch(ba[i]);
5633 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5634 if(!match) invert=1;
5635 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5636 if(i>(ba[i]-start)>>2) invert=1;
5639 invert=1; // because of near cond. branches
5642 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5643 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5646 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5649 s1l=get_reg(i_regmap,dops[i].rs1);
5653 if(dops[i].opcode2&1) unconditional=1;
5655 // These are never taken (r0 is never less than zero)
5656 //assert(dops[i].opcode2!=0);
5657 //assert(dops[i].opcode2!=2);
5658 //assert(dops[i].opcode2!=0x10);
5659 //assert(dops[i].opcode2!=0x12);
5663 // Out of order execution (delay slot first)
5665 address_generation(i+1,i_regs,regs[i].regmap_entry);
5666 ds_assemble(i+1,i_regs);
5668 uint64_t bc_unneeded=branch_regs[i].u;
5669 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5671 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5672 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5673 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5674 if(dops[i].rt1==31) {
5675 int rt,return_address;
5676 rt=get_reg(branch_regs[i].regmap,31);
5677 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5679 // Save the PC even if the branch is not taken
5680 return_address=start+i*4+8;
5681 emit_movimm(return_address,rt); // PC into link register
5683 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5687 cc=get_reg(branch_regs[i].regmap,CCREG);
5688 assert(cc==HOST_CCREG);
5690 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5691 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5692 assem_debug("cycle count (adj)\n");
5694 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5695 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5696 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5697 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5699 assem_debug("branch: internal\n");
5701 assem_debug("branch: external\n");
5702 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5703 ds_assemble_entry(i);
5706 add_to_linker(out,ba[i],internal);
5709 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5710 if(((u_int)out)&7) emit_addnop(0);
5714 else if(nevertaken) {
5715 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5718 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5721 void *nottaken = NULL;
5722 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5723 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5726 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5733 add_to_linker(out,ba[i],internal);
5737 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5744 add_to_linker(out,ba[i],internal);
5751 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5752 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5754 emit_addimm(cc,-adj,cc);
5755 add_to_linker(out,ba[i],internal);
5758 add_to_linker(out,ba[i],internal*2);
5764 if(adj) emit_addimm(cc,-adj,cc);
5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5766 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5768 assem_debug("branch: internal\n");
5770 assem_debug("branch: external\n");
5771 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5772 ds_assemble_entry(i);
5775 add_to_linker(out,ba[i],internal);
5779 set_jump_target(nottaken, out);
5783 if(!invert) emit_addimm(cc,adj,cc);
5785 } // (!unconditional)
5789 // In-order execution (branch first)
5791 void *nottaken = NULL;
5792 if(dops[i].rt1==31) {
5793 int rt,return_address;
5794 rt=get_reg(branch_regs[i].regmap,31);
5796 // Save the PC even if the branch is not taken
5797 return_address=start+i*4+8;
5798 emit_movimm(return_address,rt); // PC into link register
5800 emit_prefetch(hash_table_get(return_address));
5804 if(!unconditional) {
5805 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5807 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5813 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5819 } // if(!unconditional)
5821 uint64_t ds_unneeded=branch_regs[i].u;
5822 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5826 //assem_debug("1:\n");
5827 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5829 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5830 address_generation(i+1,&branch_regs[i],0);
5832 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5833 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5834 ds_assemble(i+1,&branch_regs[i]);
5835 cc=get_reg(branch_regs[i].regmap,CCREG);
5837 emit_loadreg(CCREG,cc=HOST_CCREG);
5838 // CHECK: Is the following instruction (fall thru) allocated ok?
5840 assert(cc==HOST_CCREG);
5841 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5842 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5843 assem_debug("cycle count (adj)\n");
5844 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5845 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5847 assem_debug("branch: internal\n");
5849 assem_debug("branch: external\n");
5850 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5851 ds_assemble_entry(i);
5854 add_to_linker(out,ba[i],internal);
5859 if(!unconditional) {
5860 set_jump_target(nottaken, out);
5861 assem_debug("1:\n");
5862 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5863 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5864 address_generation(i+1,&branch_regs[i],0);
5866 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5867 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5868 ds_assemble(i+1,&branch_regs[i]);
5869 cc=get_reg(branch_regs[i].regmap,CCREG);
5871 // Cycle count isn't in a register, temporarily load it then write it out
5872 emit_loadreg(CCREG,HOST_CCREG);
5873 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5876 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5877 emit_storereg(CCREG,HOST_CCREG);
5880 cc=get_reg(i_regmap,CCREG);
5881 assert(cc==HOST_CCREG);
5882 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5885 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5891 static void pagespan_assemble(int i, const struct regstat *i_regs)
5893 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5894 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5896 void *nottaken = NULL;
5897 int unconditional=0;
5903 else if(dops[i].rs2==0)
5908 int addr=-1,alt=-1,ntaddr=-1;
5909 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5913 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5914 i_regs->regmap[hr]!=dops[i].rs1 &&
5915 i_regs->regmap[hr]!=dops[i].rs2 )
5924 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5925 i_regs->regmap[hr]!=dops[i].rs1 &&
5926 i_regs->regmap[hr]!=dops[i].rs2 )
5932 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5936 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5937 i_regs->regmap[hr]!=dops[i].rs1 &&
5938 i_regs->regmap[hr]!=dops[i].rs2 )
5945 assert(hr<HOST_REGS);
5946 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5947 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5949 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5950 if(dops[i].opcode==2) // J
5954 if(dops[i].opcode==3) // JAL
5957 int rt=get_reg(i_regs->regmap,31);
5958 emit_movimm(start+i*4+8,rt);
5961 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5964 if(dops[i].opcode2==9) // JALR
5966 int rt=get_reg(i_regs->regmap,dops[i].rt1);
5967 emit_movimm(start+i*4+8,rt);
5970 if((dops[i].opcode&0x3f)==4) // BEQ
5972 if(dops[i].rs1==dops[i].rs2)
5977 #ifdef HAVE_CMOV_IMM
5979 if(s2l>=0) emit_cmp(s1l,s2l);
5980 else emit_test(s1l,s1l);
5981 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5987 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5988 if(s2l>=0) emit_cmp(s1l,s2l);
5989 else emit_test(s1l,s1l);
5990 emit_cmovne_reg(alt,addr);
5993 if((dops[i].opcode&0x3f)==5) // BNE
5995 #ifdef HAVE_CMOV_IMM
5996 if(s2l>=0) emit_cmp(s1l,s2l);
5997 else emit_test(s1l,s1l);
5998 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6001 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6002 if(s2l>=0) emit_cmp(s1l,s2l);
6003 else emit_test(s1l,s1l);
6004 emit_cmovne_reg(alt,addr);
6007 if((dops[i].opcode&0x3f)==0x14) // BEQL
6009 if(s2l>=0) emit_cmp(s1l,s2l);
6010 else emit_test(s1l,s1l);
6011 if(nottaken) set_jump_target(nottaken, out);
6015 if((dops[i].opcode&0x3f)==0x15) // BNEL
6017 if(s2l>=0) emit_cmp(s1l,s2l);
6018 else emit_test(s1l,s1l);
6021 if(taken) set_jump_target(taken, out);
6023 if((dops[i].opcode&0x3f)==6) // BLEZ
6025 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6027 emit_cmovl_reg(alt,addr);
6029 if((dops[i].opcode&0x3f)==7) // BGTZ
6031 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6033 emit_cmovl_reg(ntaddr,addr);
6035 if((dops[i].opcode&0x3f)==0x16) // BLEZL
6037 assert((dops[i].opcode&0x3f)!=0x16);
6039 if((dops[i].opcode&0x3f)==0x17) // BGTZL
6041 assert((dops[i].opcode&0x3f)!=0x17);
6043 assert(dops[i].opcode!=1); // BLTZ/BGEZ
6045 //FIXME: Check CSREG
6046 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
6047 if((source[i]&0x30000)==0) // BC1F
6049 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6050 emit_testimm(s1l,0x800000);
6051 emit_cmovne_reg(alt,addr);
6053 if((source[i]&0x30000)==0x10000) // BC1T
6055 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6056 emit_testimm(s1l,0x800000);
6057 emit_cmovne_reg(alt,addr);
6059 if((source[i]&0x30000)==0x20000) // BC1FL
6061 emit_testimm(s1l,0x800000);
6065 if((source[i]&0x30000)==0x30000) // BC1TL
6067 emit_testimm(s1l,0x800000);
6073 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6074 wb_dirtys(regs[i].regmap,regs[i].dirty);
6077 emit_movimm(ba[i],HOST_BTREG);
6079 else if(addr!=HOST_BTREG)
6081 emit_mov(addr,HOST_BTREG);
6083 void *branch_addr=out;
6085 int target_addr=start+i*4+5;
6087 void *compiled_target_addr=check_addr(target_addr);
6088 emit_extjump_ds(branch_addr, target_addr);
6089 if(compiled_target_addr) {
6090 set_jump_target(branch_addr, compiled_target_addr);
6091 add_jump_out(target_addr,stub);
6093 else set_jump_target(branch_addr, stub);
6096 // Assemble the delay slot for the above
6097 static void pagespan_ds()
6099 assem_debug("initial delay slot:\n");
6100 u_int vaddr=start+1;
6101 u_int page=get_page(vaddr);
6102 u_int vpage=get_vpage(vaddr);
6103 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6104 do_dirty_stub_ds(slen*4);
6105 ll_add(jump_in+page,vaddr,(void *)out);
6106 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6107 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6108 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
6109 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6110 emit_writeword(HOST_BTREG,&branch_target);
6111 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
6112 address_generation(0,®s[0],regs[0].regmap_entry);
6113 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6114 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6115 if (dops[0].is_store)
6116 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
6118 switch (dops[0].itype) {
6127 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6130 assemble(0, ®s[0], 0);
6132 int btaddr=get_reg(regs[0].regmap,BTREG);
6134 btaddr=get_reg_temp(regs[0].regmap);
6135 emit_readword(&branch_target,btaddr);
6137 assert(btaddr!=HOST_CCREG);
6138 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6140 host_tempreg_acquire();
6141 emit_movimm(start+4,HOST_TEMPREG);
6142 emit_cmp(btaddr,HOST_TEMPREG);
6143 host_tempreg_release();
6145 emit_cmpimm(btaddr,start+4);
6149 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
6150 do_jump_vaddr(btaddr);
6151 set_jump_target(branch, out);
6152 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6153 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6156 static void check_regmap(signed char *regmap)
6160 for (i = 0; i < HOST_REGS; i++) {
6163 for (j = i + 1; j < HOST_REGS; j++)
6164 assert(regmap[i] != regmap[j]);
6169 // Basic liveness analysis for MIPS registers
6170 static void unneeded_registers(int istart,int iend,int r)
6173 uint64_t u,gte_u,b,gte_b;
6174 uint64_t temp_u,temp_gte_u=0;
6175 uint64_t gte_u_unknown=0;
6176 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6180 gte_u=gte_u_unknown;
6182 //u=unneeded_reg[iend+1];
6184 gte_u=gte_unneeded[iend+1];
6187 for (i=iend;i>=istart;i--)
6189 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6192 // If subroutine call, flag return address as a possible branch target
6193 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6195 if(ba[i]<start || ba[i]>=(start+slen*4))
6197 // Branch out of this block, flush all regs
6199 gte_u=gte_u_unknown;
6200 branch_unneeded_reg[i]=u;
6201 // Merge in delay slot
6202 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6203 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6206 gte_u&=~gte_rs[i+1];
6210 // Internal branch, flag target
6211 dops[(ba[i]-start)>>2].bt=1;
6212 if(ba[i]<=start+i*4) {
6214 if(dops[i].is_ujump)
6216 // Unconditional branch
6220 // Conditional branch (not taken case)
6221 temp_u=unneeded_reg[i+2];
6222 temp_gte_u&=gte_unneeded[i+2];
6224 // Merge in delay slot
6225 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6226 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6228 temp_gte_u|=gte_rt[i+1];
6229 temp_gte_u&=~gte_rs[i+1];
6230 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6231 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6233 temp_gte_u|=gte_rt[i];
6234 temp_gte_u&=~gte_rs[i];
6235 unneeded_reg[i]=temp_u;
6236 gte_unneeded[i]=temp_gte_u;
6237 // Only go three levels deep. This recursion can take an
6238 // excessive amount of time if there are a lot of nested loops.
6240 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6242 unneeded_reg[(ba[i]-start)>>2]=1;
6243 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6246 if (dops[i].is_ujump)
6248 // Unconditional branch
6249 u=unneeded_reg[(ba[i]-start)>>2];
6250 gte_u=gte_unneeded[(ba[i]-start)>>2];
6251 branch_unneeded_reg[i]=u;
6252 // Merge in delay slot
6253 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6254 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6257 gte_u&=~gte_rs[i+1];
6259 // Conditional branch
6260 b=unneeded_reg[(ba[i]-start)>>2];
6261 gte_b=gte_unneeded[(ba[i]-start)>>2];
6262 branch_unneeded_reg[i]=b;
6263 // Branch delay slot
6264 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6265 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6268 gte_b&=~gte_rs[i+1];
6272 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6274 branch_unneeded_reg[i]=1;
6280 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6282 // SYSCALL instruction (software interrupt)
6285 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6287 // ERET instruction (return from interrupt)
6291 // Written registers are unneeded
6292 u|=1LL<<dops[i].rt1;
6293 u|=1LL<<dops[i].rt2;
6295 // Accessed registers are needed
6296 u&=~(1LL<<dops[i].rs1);
6297 u&=~(1LL<<dops[i].rs2);
6299 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6300 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6301 // Source-target dependencies
6302 // R0 is always unneeded
6306 gte_unneeded[i]=gte_u;
6308 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6311 for(r=1;r<=CCREG;r++) {
6312 if((unneeded_reg[i]>>r)&1) {
6313 if(r==HIREG) printf(" HI");
6314 else if(r==LOREG) printf(" LO");
6315 else printf(" r%d",r);
6323 // Write back dirty registers as soon as we will no longer modify them,
6324 // so that we don't end up with lots of writes at the branches.
6325 void clean_registers(int istart,int iend,int wr)
6329 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6330 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6332 will_dirty_i=will_dirty_next=0;
6333 wont_dirty_i=wont_dirty_next=0;
6335 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6336 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6338 for (i=iend;i>=istart;i--)
6340 __builtin_prefetch(regs[i-1].regmap);
6343 if(ba[i]<start || ba[i]>=(start+slen*4))
6345 // Branch out of this block, flush all regs
6346 if (dops[i].is_ujump)
6348 // Unconditional branch
6351 // Merge in delay slot (will dirty)
6352 for(r=0;r<HOST_REGS;r++) {
6353 if(r!=EXCLUDE_REG) {
6354 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6355 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6356 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6357 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6358 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6359 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6360 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6361 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6362 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6363 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6364 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6365 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6366 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6367 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6373 // Conditional branch
6375 wont_dirty_i=wont_dirty_next;
6376 // Merge in delay slot (will dirty)
6377 for(r=0;r<HOST_REGS;r++) {
6378 if(r!=EXCLUDE_REG) {
6379 if (1) { // !dops[i].likely)
6380 // Might not dirty if likely branch is not taken
6381 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6382 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6383 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6384 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6385 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6386 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6387 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6388 //if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6389 //if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6390 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6391 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6392 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6393 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6394 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6399 // Merge in delay slot (wont dirty)
6400 for(r=0;r<HOST_REGS;r++) {
6401 if(r!=EXCLUDE_REG) {
6402 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6403 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6404 if(regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6405 if(regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
6406 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6407 if(branch_regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6408 if(branch_regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6409 if(branch_regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6410 if(branch_regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
6411 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6415 #ifndef DESTRUCTIVE_WRITEBACK
6416 branch_regs[i].dirty&=wont_dirty_i;
6418 branch_regs[i].dirty|=will_dirty_i;
6424 if(ba[i]<=start+i*4) {
6426 if (dops[i].is_ujump)
6428 // Unconditional branch
6431 // Merge in delay slot (will dirty)
6432 for(r=0;r<HOST_REGS;r++) {
6433 if(r!=EXCLUDE_REG) {
6434 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6435 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6436 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6437 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6438 if(branch_regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
6439 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6440 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6441 if(regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6442 if(regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6443 if(regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6444 if(regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6445 if(regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
6446 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6447 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6451 // Conditional branch (not taken case)
6452 temp_will_dirty=will_dirty_next;
6453 temp_wont_dirty=wont_dirty_next;
6454 // Merge in delay slot (will dirty)
6455 for(r=0;r<HOST_REGS;r++) {
6456 if(r!=EXCLUDE_REG) {
6457 if (1) { // !dops[i].likely)
6458 // Will not dirty if likely branch is not taken
6459 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6460 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6461 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6462 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6463 if(branch_regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
6464 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6465 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6466 //if(regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6467 //if(regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6468 if(regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6469 if(regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6470 if(regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
6471 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6472 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6477 // Merge in delay slot (wont dirty)
6478 for(r=0;r<HOST_REGS;r++) {
6479 if(r!=EXCLUDE_REG) {
6480 if(regs[i].regmap[r]==dops[i].rt1) temp_wont_dirty|=1<<r;
6481 if(regs[i].regmap[r]==dops[i].rt2) temp_wont_dirty|=1<<r;
6482 if(regs[i].regmap[r]==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6483 if(regs[i].regmap[r]==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6484 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6485 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_wont_dirty|=1<<r;
6486 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_wont_dirty|=1<<r;
6487 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6488 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6489 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6492 // Deal with changed mappings
6494 for(r=0;r<HOST_REGS;r++) {
6495 if(r!=EXCLUDE_REG) {
6496 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6497 temp_will_dirty&=~(1<<r);
6498 temp_wont_dirty&=~(1<<r);
6499 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
6500 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6501 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6503 temp_will_dirty|=1<<r;
6504 temp_wont_dirty|=1<<r;
6511 will_dirty[i]=temp_will_dirty;
6512 wont_dirty[i]=temp_wont_dirty;
6513 clean_registers((ba[i]-start)>>2,i-1,0);
6515 // Limit recursion. It can take an excessive amount
6516 // of time if there are a lot of nested loops.
6517 will_dirty[(ba[i]-start)>>2]=0;
6518 wont_dirty[(ba[i]-start)>>2]=-1;
6523 if (dops[i].is_ujump)
6525 // Unconditional branch
6528 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6529 for(r=0;r<HOST_REGS;r++) {
6530 if(r!=EXCLUDE_REG) {
6531 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6532 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6533 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6535 if(branch_regs[i].regmap[r]>=0) {
6536 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
6537 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
6542 // Merge in delay slot
6543 for(r=0;r<HOST_REGS;r++) {
6544 if(r!=EXCLUDE_REG) {
6545 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6546 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6547 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6548 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6549 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6550 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6551 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6552 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6553 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6554 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6555 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6556 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6557 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6558 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6562 // Conditional branch
6563 will_dirty_i=will_dirty_next;
6564 wont_dirty_i=wont_dirty_next;
6565 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
6566 for(r=0;r<HOST_REGS;r++) {
6567 if(r!=EXCLUDE_REG) {
6568 signed char target_reg=branch_regs[i].regmap[r];
6569 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6570 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6571 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6573 else if(target_reg>=0) {
6574 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
6575 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
6579 // Merge in delay slot
6580 for(r=0;r<HOST_REGS;r++) {
6581 if(r!=EXCLUDE_REG) {
6582 if (1) { // !dops[i].likely)
6583 // Might not dirty if likely branch is not taken
6584 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6585 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6586 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6587 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6588 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6589 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6590 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6591 //if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6592 //if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6593 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6594 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6595 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6596 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6597 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6602 // Merge in delay slot (won't dirty)
6603 for(r=0;r<HOST_REGS;r++) {
6604 if(r!=EXCLUDE_REG) {
6605 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6606 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6607 if(regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6608 if(regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
6609 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6610 if(branch_regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6611 if(branch_regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6612 if(branch_regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6613 if(branch_regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
6614 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6618 #ifndef DESTRUCTIVE_WRITEBACK
6619 branch_regs[i].dirty&=wont_dirty_i;
6621 branch_regs[i].dirty|=will_dirty_i;
6626 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6628 // SYSCALL instruction (software interrupt)
6632 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6634 // ERET instruction (return from interrupt)
6638 will_dirty_next=will_dirty_i;
6639 wont_dirty_next=wont_dirty_i;
6640 for(r=0;r<HOST_REGS;r++) {
6641 if(r!=EXCLUDE_REG) {
6642 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6643 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6644 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
6645 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6646 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6647 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6648 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6649 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6651 if (!dops[i].is_jump)
6653 // Don't store a register immediately after writing it,
6654 // may prevent dual-issue.
6655 if(regs[i].regmap[r]==dops[i-1].rt1) wont_dirty_i|=1<<r;
6656 if(regs[i].regmap[r]==dops[i-1].rt2) wont_dirty_i|=1<<r;
6662 will_dirty[i]=will_dirty_i;
6663 wont_dirty[i]=wont_dirty_i;
6664 // Mark registers that won't be dirtied as not dirty
6666 regs[i].dirty|=will_dirty_i;
6667 #ifndef DESTRUCTIVE_WRITEBACK
6668 regs[i].dirty&=wont_dirty_i;
6671 if (i < iend-1 && !dops[i].is_ujump) {
6672 for(r=0;r<HOST_REGS;r++) {
6673 if(r!=EXCLUDE_REG) {
6674 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6675 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6676 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6684 for(r=0;r<HOST_REGS;r++) {
6685 if(r!=EXCLUDE_REG) {
6686 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6687 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6688 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6695 // Deal with changed mappings
6696 temp_will_dirty=will_dirty_i;
6697 temp_wont_dirty=wont_dirty_i;
6698 for(r=0;r<HOST_REGS;r++) {
6699 if(r!=EXCLUDE_REG) {
6701 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6703 #ifndef DESTRUCTIVE_WRITEBACK
6704 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6706 regs[i].wasdirty|=will_dirty_i&(1<<r);
6709 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6710 // Register moved to a different register
6711 will_dirty_i&=~(1<<r);
6712 wont_dirty_i&=~(1<<r);
6713 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6714 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6716 #ifndef DESTRUCTIVE_WRITEBACK
6717 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6719 regs[i].wasdirty|=will_dirty_i&(1<<r);
6723 will_dirty_i&=~(1<<r);
6724 wont_dirty_i&=~(1<<r);
6725 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
6726 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6727 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6730 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6739 #include <inttypes.h>
6740 void print_regmap(const char *name, const signed char *regmap)
6744 fputs(name, stdout);
6745 for (i = 0; i < HOST_REGS; i++) {
6748 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6752 printf(" r%d=%s", i, buf);
6754 fputs("\n", stdout);
6758 void disassemble_inst(int i)
6760 if (dops[i].bt) printf("*"); else printf(" ");
6761 switch(dops[i].itype) {
6763 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6765 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6767 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6769 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6770 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6772 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6775 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6777 if(dops[i].opcode==0xf) //LUI
6778 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6780 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6784 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6788 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6792 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6795 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6798 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6801 if((dops[i].opcode2&0x1d)==0x10)
6802 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6803 else if((dops[i].opcode2&0x1d)==0x11)
6804 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6806 printf (" %x: %s\n",start+i*4,insn[i]);
6809 if(dops[i].opcode2==0)
6810 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6811 else if(dops[i].opcode2==4)
6812 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6813 else printf (" %x: %s\n",start+i*4,insn[i]);
6816 if(dops[i].opcode2<3)
6817 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6818 else if(dops[i].opcode2>3)
6819 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6820 else printf (" %x: %s\n",start+i*4,insn[i]);
6823 if(dops[i].opcode2<3)
6824 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6825 else if(dops[i].opcode2>3)
6826 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6827 else printf (" %x: %s\n",start+i*4,insn[i]);
6830 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6833 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6836 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6839 //printf (" %s %8x\n",insn[i],source[i]);
6840 printf (" %x: %s\n",start+i*4,insn[i]);
6843 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6844 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6845 print_regmap("pre: ", regmap_pre[i]);
6846 print_regmap("entry: ", regs[i].regmap_entry);
6847 print_regmap("map: ", regs[i].regmap);
6848 if (dops[i].is_jump) {
6849 print_regmap("bentry:", branch_regs[i].regmap_entry);
6850 print_regmap("bmap: ", branch_regs[i].regmap);
6854 static void disassemble_inst(int i) {}
6857 #define DRC_TEST_VAL 0x74657374
6859 static void new_dynarec_test(void)
6861 int (*testfunc)(void);
6866 // check structure linkage
6867 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6869 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6872 SysPrintf("testing if we can run recompiled code @%p...\n", out);
6873 ((volatile u_int *)out)[0]++; // make cache dirty
6875 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6876 out = ndrc->translation_cache;
6877 beginning = start_block();
6878 emit_movimm(DRC_TEST_VAL + i, 0); // test
6881 end_block(beginning);
6882 testfunc = beginning;
6883 ret[i] = testfunc();
6886 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6887 SysPrintf("test passed.\n");
6889 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6890 out = ndrc->translation_cache;
6893 // clear the state completely, instead of just marking
6894 // things invalid like invalidate_all_pages() does
6895 void new_dynarec_clear_full(void)
6898 out = ndrc->translation_cache;
6899 memset(invalid_code,1,sizeof(invalid_code));
6900 memset(hash_table,0xff,sizeof(hash_table));
6901 memset(mini_ht,-1,sizeof(mini_ht));
6902 memset(restore_candidate,0,sizeof(restore_candidate));
6903 memset(shadow,0,sizeof(shadow));
6905 expirep=16384; // Expiry pointer, +2 blocks
6906 pending_exception=0;
6909 inv_code_start=inv_code_end=~0;
6913 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6914 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6915 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6917 cycle_multiplier_old = cycle_multiplier;
6918 new_dynarec_hacks_old = new_dynarec_hacks;
6921 void new_dynarec_init(void)
6923 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6928 #ifdef BASE_ADDR_DYNAMIC
6930 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6932 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6933 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6935 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6936 sceKernelOpenVMDomain();
6937 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6938 #elif defined(_MSC_VER)
6939 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6940 PAGE_EXECUTE_READWRITE);
6942 uintptr_t desired_addr = 0;
6945 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6947 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6948 PROT_READ | PROT_WRITE | PROT_EXEC,
6949 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6950 if (ndrc == MAP_FAILED) {
6951 SysPrintf("mmap() failed: %s\n", strerror(errno));
6956 #ifndef NO_WRITE_EXEC
6957 // not all systems allow execute in data segment by default
6958 // size must be 4K aligned for 3DS?
6959 if (mprotect(ndrc, sizeof(*ndrc),
6960 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6961 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6964 out = ndrc->translation_cache;
6965 cycle_multiplier=200;
6966 new_dynarec_clear_full();
6968 // Copy this into local area so we don't have to put it in every literal pool
6969 invc_ptr=invalid_code;
6973 ram_offset=(uintptr_t)rdram-0x80000000;
6975 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6978 void new_dynarec_cleanup(void)
6981 #ifdef BASE_ADDR_DYNAMIC
6983 // sceBlock is managed by retroarch's bootstrap code
6984 //sceKernelFreeMemBlock(sceBlock);
6987 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6988 SysPrintf("munmap() failed\n");
6991 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6992 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6993 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6995 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6999 static u_int *get_source_start(u_int addr, u_int *limit)
7001 if (addr < 0x00200000 ||
7002 (0xa0000000 <= addr && addr < 0xa0200000))
7004 // used for BIOS calls mostly?
7005 *limit = (addr&0xa0000000)|0x00200000;
7006 return (u_int *)(rdram + (addr&0x1fffff));
7008 else if (!Config.HLE && (
7009 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7010 (0xbfc00000 <= addr && addr < 0xbfc80000)))
7012 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
7013 // but timings in PCSX are too tied to the interpreter's BIAS
7014 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
7015 cycle_multiplier_active = 200;
7017 *limit = (addr & 0xfff00000) | 0x80000;
7018 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
7020 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7021 *limit = (addr & 0x80600000) + 0x00200000;
7022 return (u_int *)(rdram + (addr&0x1fffff));
7027 static u_int scan_for_ret(u_int addr)
7032 mem = get_source_start(addr, &limit);
7036 if (limit > addr + 0x1000)
7037 limit = addr + 0x1000;
7038 for (; addr < limit; addr += 4, mem++) {
7039 if (*mem == 0x03e00008) // jr $ra
7045 struct savestate_block {
7050 static int addr_cmp(const void *p1_, const void *p2_)
7052 const struct savestate_block *p1 = p1_, *p2 = p2_;
7053 return p1->addr - p2->addr;
7056 int new_dynarec_save_blocks(void *save, int size)
7058 struct savestate_block *blocks = save;
7059 int maxcount = size / sizeof(blocks[0]);
7060 struct savestate_block tmp_blocks[1024];
7061 struct ll_entry *head;
7062 int p, s, d, o, bcnt;
7066 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
7068 for (head = jump_in[p]; head != NULL; head = head->next) {
7069 tmp_blocks[bcnt].addr = head->vaddr;
7070 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7075 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7077 addr = tmp_blocks[0].addr;
7078 for (s = d = 0; s < bcnt; s++) {
7079 if (tmp_blocks[s].addr < addr)
7081 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7082 tmp_blocks[d++] = tmp_blocks[s];
7083 addr = scan_for_ret(tmp_blocks[s].addr);
7086 if (o + d > maxcount)
7088 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7092 return o * sizeof(blocks[0]);
7095 void new_dynarec_load_blocks(const void *save, int size)
7097 const struct savestate_block *blocks = save;
7098 int count = size / sizeof(blocks[0]);
7099 u_int regs_save[32];
7103 get_addr(psxRegs.pc);
7105 // change GPRs for speculation to at least partially work..
7106 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7107 for (i = 1; i < 32; i++)
7108 psxRegs.GPR.r[i] = 0x80000000;
7110 for (b = 0; b < count; b++) {
7111 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7113 psxRegs.GPR.r[i] = 0x1f800000;
7116 get_addr(blocks[b].addr);
7118 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7120 psxRegs.GPR.r[i] = 0x80000000;
7124 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7127 static int apply_hacks(void)
7130 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7132 /* special hack(s) */
7133 for (i = 0; i < slen - 4; i++)
7135 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7136 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7137 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7138 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7140 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7141 dops[i + 3].itype = NOP;
7145 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7146 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7147 && dops[i-7].itype == STORE)
7150 if (dops[i].itype == IMM16)
7152 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7153 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7154 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7156 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7164 int new_recompile_block(u_int addr)
7166 u_int pagelimit = 0;
7167 u_int state_rflags = 0;
7170 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7171 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7173 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7175 // this is just for speculation
7176 for (i = 1; i < 32; i++) {
7177 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7178 state_rflags |= 1 << i;
7181 start = (u_int)addr&~3;
7182 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
7183 new_dynarec_did_compile=1;
7184 if (Config.HLE && start == 0x80001000) // hlecall
7186 // XXX: is this enough? Maybe check hleSoftCall?
7187 void *beginning=start_block();
7188 u_int page=get_page(start);
7190 invalid_code[start>>12]=0;
7191 emit_movimm(start,0);
7192 emit_writeword(0,&pcaddr);
7193 emit_far_jump(new_dyna_leave);
7195 end_block(beginning);
7196 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7199 else if (f1_hack && hack_addr == 0) {
7200 void *beginning = start_block();
7201 u_int page = get_page(start);
7202 emit_movimm(start, 0);
7203 emit_writeword(0, &hack_addr);
7204 emit_readword(&psxRegs.GPR.n.sp, 0);
7205 emit_readptr(&mem_rtab, 1);
7206 emit_shrimm(0, 12, 2);
7207 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7208 emit_addimm(0, 0x18, 0);
7209 emit_adds_ptr(1, 1, 1);
7210 emit_ldr_dualindexed(1, 0, 0);
7211 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7212 emit_far_call(get_addr_ht);
7213 emit_jmpreg(0); // jr k0
7215 end_block(beginning);
7217 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7218 SysPrintf("F1 hack to %08x\n", start);
7222 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7223 ? cycle_multiplier_override : cycle_multiplier;
7225 source = get_source_start(start, &pagelimit);
7226 if (source == NULL) {
7227 if (addr != hack_addr) {
7228 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7235 /* Pass 1: disassemble */
7236 /* Pass 2: register dependencies, branch targets */
7237 /* Pass 3: register allocation */
7238 /* Pass 4: branch dependencies */
7239 /* Pass 5: pre-alloc */
7240 /* Pass 6: optimize clean/dirty state */
7241 /* Pass 7: flag 32-bit registers */
7242 /* Pass 8: assembly */
7243 /* Pass 9: linker */
7244 /* Pass 10: garbage collection / free memory */
7247 int done = 0, ni_count = 0;
7248 unsigned int type,op,op2;
7250 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7252 /* Pass 1 disassembly */
7254 for (i = 0; !done; i++)
7256 memset(&dops[i], 0, sizeof(dops[i]));
7258 minimum_free_regs[i]=0;
7259 dops[i].opcode=op=source[i]>>26;
7262 case 0x00: strcpy(insn[i],"special"); type=NI;
7266 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7267 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7268 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7269 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7270 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7271 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7272 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7273 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7274 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7275 case 0x0D: strcpy(insn[i],"BREAK"); type=SYSCALL; break;
7276 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7277 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7278 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7279 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7280 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7281 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7282 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7283 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7284 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7285 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7286 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7287 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7288 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7289 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7290 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7291 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7292 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7293 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7294 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7295 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7296 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7297 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7298 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7299 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7300 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7302 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7303 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7304 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7305 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7306 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7307 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7308 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7309 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7310 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7311 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7312 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7313 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7314 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7315 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7316 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7317 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7318 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7322 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7323 op2=(source[i]>>16)&0x1f;
7326 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7327 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7328 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7329 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7330 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7331 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7332 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7333 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7334 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7335 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7336 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7337 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7338 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7339 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7342 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7343 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7344 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7345 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7346 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7347 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7348 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7349 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7350 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7351 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7352 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7353 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7354 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7355 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7356 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7357 op2=(source[i]>>21)&0x1f;
7360 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7361 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7362 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7363 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7364 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7367 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7368 op2=(source[i]>>21)&0x1f;
7371 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7372 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7373 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7374 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7375 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7376 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7377 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7378 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7380 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7381 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7382 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7383 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7384 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7385 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7386 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7388 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7390 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7391 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7392 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7393 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7395 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7396 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7398 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7399 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7400 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7401 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7403 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7404 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7405 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7407 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7408 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7410 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7411 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7412 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7414 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7415 op2=(source[i]>>21)&0x1f;
7417 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7418 if (gte_handlers[source[i]&0x3f]!=NULL) {
7419 if (gte_regnames[source[i]&0x3f]!=NULL)
7420 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7422 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7428 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7429 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7430 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7431 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7434 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7435 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7436 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7437 default: strcpy(insn[i],"???"); type=NI;
7438 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7442 dops[i].opcode2=op2;
7443 /* Get registers/immediates */
7445 gte_rs[i]=gte_rt[i]=0;
7448 dops[i].rs1=(source[i]>>21)&0x1f;
7450 dops[i].rt1=(source[i]>>16)&0x1f;
7452 imm[i]=(short)source[i];
7456 dops[i].rs1=(source[i]>>21)&0x1f;
7457 dops[i].rs2=(source[i]>>16)&0x1f;
7460 imm[i]=(short)source[i];
7463 // LWL/LWR only load part of the register,
7464 // therefore the target register must be treated as a source too
7465 dops[i].rs1=(source[i]>>21)&0x1f;
7466 dops[i].rs2=(source[i]>>16)&0x1f;
7467 dops[i].rt1=(source[i]>>16)&0x1f;
7469 imm[i]=(short)source[i];
7472 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7473 else dops[i].rs1=(source[i]>>21)&0x1f;
7475 dops[i].rt1=(source[i]>>16)&0x1f;
7477 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7478 imm[i]=(unsigned short)source[i];
7480 imm[i]=(short)source[i];
7488 // The JAL instruction writes to r31.
7495 dops[i].rs1=(source[i]>>21)&0x1f;
7499 // The JALR instruction writes to rd.
7501 dops[i].rt1=(source[i]>>11)&0x1f;
7506 dops[i].rs1=(source[i]>>21)&0x1f;
7507 dops[i].rs2=(source[i]>>16)&0x1f;
7510 if(op&2) { // BGTZ/BLEZ
7515 dops[i].rs1=(source[i]>>21)&0x1f;
7519 if(op2&0x10) { // BxxAL
7521 // NOTE: If the branch is not taken, r31 is still overwritten
7525 dops[i].rs1=(source[i]>>21)&0x1f; // source
7526 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7527 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7531 dops[i].rs1=(source[i]>>21)&0x1f; // source
7532 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7541 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7542 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7543 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7544 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7545 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7546 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7549 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7550 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7551 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7555 dops[i].rs1=(source[i]>>16)&0x1f;
7557 dops[i].rt1=(source[i]>>11)&0x1f;
7559 imm[i]=(source[i]>>6)&0x1f;
7560 // DSxx32 instructions
7561 if(op2>=0x3c) imm[i]|=0x20;
7568 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7569 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7570 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7571 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7578 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7579 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7587 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7588 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7590 int gr=(source[i]>>11)&0x1F;
7593 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7594 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7595 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7596 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7600 dops[i].rs1=(source[i]>>21)&0x1F;
7604 imm[i]=(short)source[i];
7607 dops[i].rs1=(source[i]>>21)&0x1F;
7611 imm[i]=(short)source[i];
7612 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7613 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7620 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7621 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7622 gte_rt[i]|=1ll<<63; // every op changes flags
7623 if((source[i]&0x3f)==GTE_MVMVA) {
7624 int v = (source[i] >> 15) & 3;
7625 gte_rs[i]&=~0xe3fll;
7626 if(v==3) gte_rs[i]|=0xe00ll;
7627 else gte_rs[i]|=3ll<<(v*2);
7644 /* Calculate branch target addresses */
7646 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7647 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7648 ba[i]=start+i*4+8; // Ignore never taken branch
7649 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7650 ba[i]=start+i*4+8; // Ignore never taken branch
7651 else if(type==CJUMP||type==SJUMP)
7652 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7655 /* simplify always (not)taken branches */
7656 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7657 dops[i].rs1 = dops[i].rs2 = 0;
7659 dops[i].itype = type = UJUMP;
7660 dops[i].rs2 = CCREG;
7663 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7664 dops[i].itype = type = UJUMP;
7666 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7667 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7668 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7669 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
7671 /* messy cases to just pass over to the interpreter */
7672 if (i > 0 && dops[i-1].is_jump) {
7674 // branch in delay slot?
7675 if (dops[i].is_jump) {
7676 // don't handle first branch and call interpreter if it's hit
7677 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7680 // basic load delay detection
7681 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7682 int t=(ba[i-1]-start)/4;
7683 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7684 // jump target wants DS result - potential load delay effect
7685 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7687 dops[t+1].bt=1; // expected return from interpreter
7689 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7690 !(i>=3&&dops[i-3].is_jump)) {
7691 // v0 overwrite like this is a sign of trouble, bail out
7692 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7697 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7698 dops[i-1].itype = INTCALL;
7699 dops[i-1].rs1 = CCREG;
7702 i--; // don't compile the DS
7706 /* Is this the end of the block? */
7707 if (i > 0 && dops[i-1].is_ujump) {
7708 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7712 if(stop_after_jal) done=1;
7714 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7716 // Don't recompile stuff that's already compiled
7717 if(check_addr(start+i*4+4)) done=1;
7718 // Don't get too close to the limit
7719 if(i>MAXBLOCK/2) done=1;
7721 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7722 done = stop_after_jal ? 1 : 2;
7724 // Does the block continue due to a branch?
7727 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7728 if(ba[j]==start+i*4+4) done=j=0;
7729 if(ba[j]==start+i*4+8) done=j=0;
7732 //assert(i<MAXBLOCK-1);
7733 if(start+i*4==pagelimit-4) done=1;
7734 assert(start+i*4<pagelimit);
7735 if (i==MAXBLOCK-1) done=1;
7736 // Stop if we're compiling junk
7737 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7738 done=stop_after_jal=1;
7739 SysPrintf("Disabled speculative precompilation\n");
7743 if (dops[i-1].is_jump) {
7744 if(start+i*4==pagelimit) {
7745 dops[i-1].itype=SPAN;
7750 int clear_hack_addr = apply_hacks();
7752 /* Pass 2 - Register dependencies and branch targets */
7754 unneeded_registers(0,slen-1,0);
7756 /* Pass 3 - Register allocation */
7758 struct regstat current; // Current register allocations/status
7759 clear_all_regs(current.regmap_entry);
7760 clear_all_regs(current.regmap);
7761 current.wasdirty = current.dirty = 0;
7762 current.u = unneeded_reg[0];
7763 alloc_reg(¤t, 0, CCREG);
7764 dirty_reg(¤t, CCREG);
7765 current.wasconst = 0;
7766 current.isconst = 0;
7767 current.loadedconst = 0;
7768 current.waswritten = 0;
7774 // First instruction is delay slot
7779 current.regmap[HOST_BTREG]=BTREG;
7787 for(hr=0;hr<HOST_REGS;hr++)
7789 // Is this really necessary?
7790 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7793 current.waswritten=0;
7796 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7797 regs[i].wasconst=current.isconst;
7798 regs[i].wasdirty=current.dirty;
7802 regs[i].loadedconst=0;
7803 if (!dops[i].is_jump) {
7805 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7812 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7813 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7816 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7822 ds=0; // Skip delay slot, already allocated as part of branch
7823 // ...but we need to alloc it in case something jumps here
7825 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7827 current.u=branch_unneeded_reg[i-1];
7829 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7831 struct regstat temp;
7832 memcpy(&temp,¤t,sizeof(current));
7833 temp.wasdirty=temp.dirty;
7834 // TODO: Take into account unconditional branches, as below
7835 delayslot_alloc(&temp,i);
7836 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7837 regs[i].wasdirty=temp.wasdirty;
7838 regs[i].dirty=temp.dirty;
7842 // Create entry (branch target) regmap
7843 for(hr=0;hr<HOST_REGS;hr++)
7845 int r=temp.regmap[hr];
7847 if(r!=regmap_pre[i][hr]) {
7848 regs[i].regmap_entry[hr]=-1;
7853 if((current.u>>r)&1) {
7854 regs[i].regmap_entry[hr]=-1;
7855 regs[i].regmap[hr]=-1;
7856 //Don't clear regs in the delay slot as the branch might need them
7857 //current.regmap[hr]=-1;
7859 regs[i].regmap_entry[hr]=r;
7862 // First instruction expects CCREG to be allocated
7863 if(i==0&&hr==HOST_CCREG)
7864 regs[i].regmap_entry[hr]=CCREG;
7866 regs[i].regmap_entry[hr]=-1;
7870 else { // Not delay slot
7871 switch(dops[i].itype) {
7873 //current.isconst=0; // DEBUG
7874 //current.wasconst=0; // DEBUG
7875 //regs[i].wasconst=0; // DEBUG
7876 clear_const(¤t,dops[i].rt1);
7877 alloc_cc(¤t,i);
7878 dirty_reg(¤t,CCREG);
7879 if (dops[i].rt1==31) {
7880 alloc_reg(¤t,i,31);
7881 dirty_reg(¤t,31);
7882 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7883 //assert(dops[i+1].rt1!=dops[i].rt1);
7885 alloc_reg(¤t,i,PTEMP);
7889 delayslot_alloc(¤t,i+1);
7890 //current.isconst=0; // DEBUG
7892 //printf("i=%d, isconst=%x\n",i,current.isconst);
7895 //current.isconst=0;
7896 //current.wasconst=0;
7897 //regs[i].wasconst=0;
7898 clear_const(¤t,dops[i].rs1);
7899 clear_const(¤t,dops[i].rt1);
7900 alloc_cc(¤t,i);
7901 dirty_reg(¤t,CCREG);
7902 if (!ds_writes_rjump_rs(i)) {
7903 alloc_reg(¤t,i,dops[i].rs1);
7904 if (dops[i].rt1!=0) {
7905 alloc_reg(¤t,i,dops[i].rt1);
7906 dirty_reg(¤t,dops[i].rt1);
7907 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7908 assert(dops[i+1].rt1!=dops[i].rt1);
7910 alloc_reg(¤t,i,PTEMP);
7914 if(dops[i].rs1==31) { // JALR
7915 alloc_reg(¤t,i,RHASH);
7916 alloc_reg(¤t,i,RHTBL);
7919 delayslot_alloc(¤t,i+1);
7921 // The delay slot overwrites our source register,
7922 // allocate a temporary register to hold the old value.
7926 delayslot_alloc(¤t,i+1);
7928 alloc_reg(¤t,i,RTEMP);
7930 //current.isconst=0; // DEBUG
7935 //current.isconst=0;
7936 //current.wasconst=0;
7937 //regs[i].wasconst=0;
7938 clear_const(¤t,dops[i].rs1);
7939 clear_const(¤t,dops[i].rs2);
7940 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7942 alloc_cc(¤t,i);
7943 dirty_reg(¤t,CCREG);
7944 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7945 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7946 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7947 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7948 // The delay slot overwrites one of our conditions.
7949 // Allocate the branch condition registers instead.
7953 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7954 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7959 delayslot_alloc(¤t,i+1);
7963 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7965 alloc_cc(¤t,i);
7966 dirty_reg(¤t,CCREG);
7967 alloc_reg(¤t,i,dops[i].rs1);
7968 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7969 // The delay slot overwrites one of our conditions.
7970 // Allocate the branch condition registers instead.
7974 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7979 delayslot_alloc(¤t,i+1);
7983 // Don't alloc the delay slot yet because we might not execute it
7984 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7989 alloc_cc(¤t,i);
7990 dirty_reg(¤t,CCREG);
7991 alloc_reg(¤t,i,dops[i].rs1);
7992 alloc_reg(¤t,i,dops[i].rs2);
7995 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
8000 alloc_cc(¤t,i);
8001 dirty_reg(¤t,CCREG);
8002 alloc_reg(¤t,i,dops[i].rs1);
8005 //current.isconst=0;
8008 //current.isconst=0;
8009 //current.wasconst=0;
8010 //regs[i].wasconst=0;
8011 clear_const(¤t,dops[i].rs1);
8012 clear_const(¤t,dops[i].rt1);
8013 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
8014 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
8016 alloc_cc(¤t,i);
8017 dirty_reg(¤t,CCREG);
8018 alloc_reg(¤t,i,dops[i].rs1);
8019 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
8020 alloc_reg(¤t,i,31);
8021 dirty_reg(¤t,31);
8022 //#ifdef REG_PREFETCH
8023 //alloc_reg(¤t,i,PTEMP);
8026 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
8027 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
8028 // Allocate the branch condition registers instead.
8032 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
8037 delayslot_alloc(¤t,i+1);
8041 // Don't alloc the delay slot yet because we might not execute it
8042 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
8047 alloc_cc(¤t,i);
8048 dirty_reg(¤t,CCREG);
8049 alloc_reg(¤t,i,dops[i].rs1);
8052 //current.isconst=0;
8055 imm16_alloc(¤t,i);
8059 load_alloc(¤t,i);
8063 store_alloc(¤t,i);
8066 alu_alloc(¤t,i);
8069 shift_alloc(¤t,i);
8072 multdiv_alloc(¤t,i);
8075 shiftimm_alloc(¤t,i);
8078 mov_alloc(¤t,i);
8081 cop0_alloc(¤t,i);
8086 cop2_alloc(¤t,i);
8089 c1ls_alloc(¤t,i);
8092 c2ls_alloc(¤t,i);
8095 c2op_alloc(¤t,i);
8100 syscall_alloc(¤t,i);
8103 pagespan_alloc(¤t,i);
8107 // Create entry (branch target) regmap
8108 for(hr=0;hr<HOST_REGS;hr++)
8111 r=current.regmap[hr];
8113 if(r!=regmap_pre[i][hr]) {
8114 // TODO: delay slot (?)
8115 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8116 if(or<0||r>=TEMPREG){
8117 regs[i].regmap_entry[hr]=-1;
8121 // Just move it to a different register
8122 regs[i].regmap_entry[hr]=r;
8123 // If it was dirty before, it's still dirty
8124 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
8131 regs[i].regmap_entry[hr]=0;
8136 if((current.u>>r)&1) {
8137 regs[i].regmap_entry[hr]=-1;
8138 //regs[i].regmap[hr]=-1;
8139 current.regmap[hr]=-1;
8141 regs[i].regmap_entry[hr]=r;
8145 // Branches expect CCREG to be allocated at the target
8146 if(regmap_pre[i][hr]==CCREG)
8147 regs[i].regmap_entry[hr]=CCREG;
8149 regs[i].regmap_entry[hr]=-1;
8152 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8155 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8156 current.waswritten|=1<<dops[i-1].rs1;
8157 current.waswritten&=~(1<<dops[i].rt1);
8158 current.waswritten&=~(1<<dops[i].rt2);
8159 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8160 current.waswritten&=~(1<<dops[i].rs1);
8162 /* Branch post-alloc */
8165 current.wasdirty=current.dirty;
8166 switch(dops[i-1].itype) {
8168 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8169 branch_regs[i-1].isconst=0;
8170 branch_regs[i-1].wasconst=0;
8171 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8172 alloc_cc(&branch_regs[i-1],i-1);
8173 dirty_reg(&branch_regs[i-1],CCREG);
8174 if(dops[i-1].rt1==31) { // JAL
8175 alloc_reg(&branch_regs[i-1],i-1,31);
8176 dirty_reg(&branch_regs[i-1],31);
8178 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8179 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8182 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8183 branch_regs[i-1].isconst=0;
8184 branch_regs[i-1].wasconst=0;
8185 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8186 alloc_cc(&branch_regs[i-1],i-1);
8187 dirty_reg(&branch_regs[i-1],CCREG);
8188 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8189 if(dops[i-1].rt1!=0) { // JALR
8190 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8191 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
8194 if(dops[i-1].rs1==31) { // JALR
8195 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8196 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8199 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8200 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8203 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
8205 alloc_cc(¤t,i-1);
8206 dirty_reg(¤t,CCREG);
8207 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8208 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
8209 // The delay slot overwrote one of our conditions
8210 // Delay slot goes after the test (in order)
8211 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8213 delayslot_alloc(¤t,i);
8218 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8219 // Alloc the branch condition registers
8220 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
8221 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
8223 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8224 branch_regs[i-1].isconst=0;
8225 branch_regs[i-1].wasconst=0;
8226 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8227 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8230 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
8232 alloc_cc(¤t,i-1);
8233 dirty_reg(¤t,CCREG);
8234 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8235 // The delay slot overwrote the branch condition
8236 // Delay slot goes after the test (in order)
8237 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8239 delayslot_alloc(¤t,i);
8244 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8245 // Alloc the branch condition register
8246 alloc_reg(¤t,i-1,dops[i-1].rs1);
8248 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8249 branch_regs[i-1].isconst=0;
8250 branch_regs[i-1].wasconst=0;
8251 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8252 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8255 // Alloc the delay slot in case the branch is taken
8256 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8258 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8259 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8260 alloc_cc(&branch_regs[i-1],i);
8261 dirty_reg(&branch_regs[i-1],CCREG);
8262 delayslot_alloc(&branch_regs[i-1],i);
8263 branch_regs[i-1].isconst=0;
8264 alloc_reg(¤t,i,CCREG); // Not taken path
8265 dirty_reg(¤t,CCREG);
8266 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8269 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8271 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8272 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8273 alloc_cc(&branch_regs[i-1],i);
8274 dirty_reg(&branch_regs[i-1],CCREG);
8275 delayslot_alloc(&branch_regs[i-1],i);
8276 branch_regs[i-1].isconst=0;
8277 alloc_reg(¤t,i,CCREG); // Not taken path
8278 dirty_reg(¤t,CCREG);
8279 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8283 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8284 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8286 alloc_cc(¤t,i-1);
8287 dirty_reg(¤t,CCREG);
8288 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8289 // The delay slot overwrote the branch condition
8290 // Delay slot goes after the test (in order)
8291 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8293 delayslot_alloc(¤t,i);
8298 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8299 // Alloc the branch condition register
8300 alloc_reg(¤t,i-1,dops[i-1].rs1);
8302 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8303 branch_regs[i-1].isconst=0;
8304 branch_regs[i-1].wasconst=0;
8305 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8306 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8309 // Alloc the delay slot in case the branch is taken
8310 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8312 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8313 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8314 alloc_cc(&branch_regs[i-1],i);
8315 dirty_reg(&branch_regs[i-1],CCREG);
8316 delayslot_alloc(&branch_regs[i-1],i);
8317 branch_regs[i-1].isconst=0;
8318 alloc_reg(¤t,i,CCREG); // Not taken path
8319 dirty_reg(¤t,CCREG);
8320 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8322 // FIXME: BLTZAL/BGEZAL
8323 if(dops[i-1].opcode2&0x10) { // BxxZAL
8324 alloc_reg(&branch_regs[i-1],i-1,31);
8325 dirty_reg(&branch_regs[i-1],31);
8330 if (dops[i-1].is_ujump)
8332 if(dops[i-1].rt1==31) // JAL/JALR
8334 // Subroutine call will return here, don't alloc any registers
8336 clear_all_regs(current.regmap);
8337 alloc_reg(¤t,i,CCREG);
8338 dirty_reg(¤t,CCREG);
8342 // Internal branch will jump here, match registers to caller
8344 clear_all_regs(current.regmap);
8345 alloc_reg(¤t,i,CCREG);
8346 dirty_reg(¤t,CCREG);
8349 if(ba[j]==start+i*4+4) {
8350 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8351 current.dirty=branch_regs[j].dirty;
8356 if(ba[j]==start+i*4+4) {
8357 for(hr=0;hr<HOST_REGS;hr++) {
8358 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8359 current.regmap[hr]=-1;
8361 current.dirty&=branch_regs[j].dirty;
8370 // Count cycles in between branches
8371 ccadj[i] = CLOCK_ADJUST(cc);
8372 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8376 #if !defined(DRC_DBG)
8377 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
8379 // this should really be removed since the real stalls have been implemented,
8380 // but doing so causes sizeable perf regression against the older version
8381 u_int gtec = gte_cycletab[source[i] & 0x3f];
8382 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8384 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8388 else if(dops[i].itype==C2LS)
8390 // same as with C2OP
8391 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8399 if(!dops[i].is_ds) {
8400 regs[i].dirty=current.dirty;
8401 regs[i].isconst=current.isconst;
8402 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8404 for(hr=0;hr<HOST_REGS;hr++) {
8405 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
8406 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8407 regs[i].wasconst&=~(1<<hr);
8411 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8412 regs[i].waswritten=current.waswritten;
8415 /* Pass 4 - Cull unused host registers */
8419 for (i=slen-1;i>=0;i--)
8424 if(ba[i]<start || ba[i]>=(start+slen*4))
8426 // Branch out of this block, don't need anything
8432 // Need whatever matches the target
8434 int t=(ba[i]-start)>>2;
8435 for(hr=0;hr<HOST_REGS;hr++)
8437 if(regs[i].regmap_entry[hr]>=0) {
8438 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8442 // Conditional branch may need registers for following instructions
8443 if (!dops[i].is_ujump)
8446 nr|=needed_reg[i+2];
8447 for(hr=0;hr<HOST_REGS;hr++)
8449 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8450 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8454 // Don't need stuff which is overwritten
8455 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8456 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8457 // Merge in delay slot
8458 for(hr=0;hr<HOST_REGS;hr++)
8460 if(dops[i+1].rt1&&dops[i+1].rt1==regs[i].regmap[hr]) nr&=~(1<<hr);
8461 if(dops[i+1].rt2&&dops[i+1].rt2==regs[i].regmap[hr]) nr&=~(1<<hr);
8462 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8463 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8464 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8465 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8466 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8467 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8468 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8470 if(dops[i+1].is_store) {
8471 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8472 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8476 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8478 // SYSCALL instruction (software interrupt)
8481 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8483 // ERET instruction (return from interrupt)
8489 for(hr=0;hr<HOST_REGS;hr++) {
8490 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8491 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8492 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8493 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8497 for(hr=0;hr<HOST_REGS;hr++)
8499 // Overwritten registers are not needed
8500 if(dops[i].rt1&&dops[i].rt1==regs[i].regmap[hr]) nr&=~(1<<hr);
8501 if(dops[i].rt2&&dops[i].rt2==regs[i].regmap[hr]) nr&=~(1<<hr);
8502 if(FTEMP==regs[i].regmap[hr]) nr&=~(1<<hr);
8503 // Source registers are needed
8504 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8505 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8506 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8507 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8508 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8509 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8510 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8512 if(dops[i].is_store) {
8513 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8514 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8516 // Don't store a register immediately after writing it,
8517 // may prevent dual-issue.
8518 // But do so if this is a branch target, otherwise we
8519 // might have to load the register before the branch.
8520 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8521 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8522 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
8523 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
8525 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8526 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8527 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8531 // Cycle count is needed at branches. Assume it is needed at the target too.
8532 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8533 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8534 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8539 // Deallocate unneeded registers
8540 for(hr=0;hr<HOST_REGS;hr++)
8543 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8546 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8547 if (dops[i+1].is_load || dops[i+1].is_store)
8549 if (dops[i+1].is_store)
8551 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8553 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8554 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8555 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
8556 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8557 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
8558 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8559 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8560 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8562 regs[i].regmap[hr]=-1;
8563 regs[i].isconst&=~(1<<hr);
8564 regs[i].dirty&=~(1<<hr);
8565 regs[i+1].wasdirty&=~(1<<hr);
8566 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
8567 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
8568 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
8569 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8570 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8571 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8572 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8573 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8575 branch_regs[i].regmap[hr]=-1;
8576 branch_regs[i].regmap_entry[hr]=-1;
8577 if (!dops[i].is_ujump)
8580 regmap_pre[i+2][hr]=-1;
8581 regs[i+2].wasconst&=~(1<<hr);
8592 int map1 = -1, map2 = -1, temp=-1;
8593 if (dops[i].is_load || dops[i].is_store)
8595 if (dops[i].is_store)
8597 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8599 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8600 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8601 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8602 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8603 regs[i].regmap[hr] != CCREG)
8605 if(i<slen-1&&!dops[i].is_ds) {
8606 assert(regs[i].regmap[hr]<64);
8607 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8608 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8610 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8611 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8613 regmap_pre[i+1][hr]=-1;
8614 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8615 regs[i+1].wasconst&=~(1<<hr);
8617 regs[i].regmap[hr]=-1;
8618 regs[i].isconst&=~(1<<hr);
8619 regs[i].dirty&=~(1<<hr);
8620 regs[i+1].wasdirty&=~(1<<hr);
8628 /* Pass 5 - Pre-allocate registers */
8630 // If a register is allocated during a loop, try to allocate it for the
8631 // entire loop, if possible. This avoids loading/storing registers
8632 // inside of the loop.
8634 signed char f_regmap[HOST_REGS];
8635 clear_all_regs(f_regmap);
8636 for(i=0;i<slen-1;i++)
8638 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8640 if(ba[i]>=start && ba[i]<(start+i*4))
8641 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8642 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8643 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8644 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8645 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8647 int t=(ba[i]-start)>>2;
8648 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8649 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8650 for(hr=0;hr<HOST_REGS;hr++)
8652 if(regs[i].regmap[hr]>=0) {
8653 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8654 // dealloc old register
8656 for(n=0;n<HOST_REGS;n++)
8658 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8660 // and alloc new one
8661 f_regmap[hr]=regs[i].regmap[hr];
8664 if(branch_regs[i].regmap[hr]>=0) {
8665 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8666 // dealloc old register
8668 for(n=0;n<HOST_REGS;n++)
8670 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8672 // and alloc new one
8673 f_regmap[hr]=branch_regs[i].regmap[hr];
8677 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8678 f_regmap[hr]=branch_regs[i].regmap[hr];
8680 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8681 f_regmap[hr]=branch_regs[i].regmap[hr];
8683 // Avoid dirty->clean transition
8684 #ifdef DESTRUCTIVE_WRITEBACK
8685 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8687 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8688 // case above, however it's always a good idea. We can't hoist the
8689 // load if the register was already allocated, so there's no point
8690 // wasting time analyzing most of these cases. It only "succeeds"
8691 // when the mapping was different and the load can be replaced with
8692 // a mov, which is of negligible benefit. So such cases are
8694 if(f_regmap[hr]>0) {
8695 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8699 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8700 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8702 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8703 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8705 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8706 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8707 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8709 while(k>1&®s[k-1].regmap[hr]==-1) {
8710 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8711 //printf("no free regs for store %x\n",start+(k-1)*4);
8714 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8715 //printf("no-match due to different register\n");
8718 if (dops[k-2].is_jump) {
8719 //printf("no-match due to branch\n");
8722 // call/ret fast path assumes no registers allocated
8723 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8728 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8729 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8731 regs[k].regmap_entry[hr]=f_regmap[hr];
8732 regs[k].regmap[hr]=f_regmap[hr];
8733 regmap_pre[k+1][hr]=f_regmap[hr];
8734 regs[k].wasdirty&=~(1<<hr);
8735 regs[k].dirty&=~(1<<hr);
8736 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8737 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8738 regs[k].wasconst&=~(1<<hr);
8739 regs[k].isconst&=~(1<<hr);
8744 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8747 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8748 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8749 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8750 regs[i].regmap_entry[hr]=f_regmap[hr];
8751 regs[i].regmap[hr]=f_regmap[hr];
8752 regs[i].wasdirty&=~(1<<hr);
8753 regs[i].dirty&=~(1<<hr);
8754 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8755 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8756 regs[i].wasconst&=~(1<<hr);
8757 regs[i].isconst&=~(1<<hr);
8758 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8759 branch_regs[i].wasdirty&=~(1<<hr);
8760 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8761 branch_regs[i].regmap[hr]=f_regmap[hr];
8762 branch_regs[i].dirty&=~(1<<hr);
8763 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8764 branch_regs[i].wasconst&=~(1<<hr);
8765 branch_regs[i].isconst&=~(1<<hr);
8766 if (!dops[i].is_ujump) {
8767 regmap_pre[i+2][hr]=f_regmap[hr];
8768 regs[i+2].wasdirty&=~(1<<hr);
8769 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8774 // Alloc register clean at beginning of loop,
8775 // but may dirty it in pass 6
8776 regs[k].regmap_entry[hr]=f_regmap[hr];
8777 regs[k].regmap[hr]=f_regmap[hr];
8778 regs[k].dirty&=~(1<<hr);
8779 regs[k].wasconst&=~(1<<hr);
8780 regs[k].isconst&=~(1<<hr);
8781 if (dops[k].is_jump) {
8782 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8783 branch_regs[k].regmap[hr]=f_regmap[hr];
8784 branch_regs[k].dirty&=~(1<<hr);
8785 branch_regs[k].wasconst&=~(1<<hr);
8786 branch_regs[k].isconst&=~(1<<hr);
8787 if (!dops[k].is_ujump) {
8788 regmap_pre[k+2][hr]=f_regmap[hr];
8789 regs[k+2].wasdirty&=~(1<<hr);
8794 regmap_pre[k+1][hr]=f_regmap[hr];
8795 regs[k+1].wasdirty&=~(1<<hr);
8798 if(regs[j].regmap[hr]==f_regmap[hr])
8799 regs[j].regmap_entry[hr]=f_regmap[hr];
8803 if(regs[j].regmap[hr]>=0)
8805 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8806 //printf("no-match due to different register\n");
8809 if (dops[j].is_ujump)
8811 // Stop on unconditional branch
8814 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8817 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8820 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8823 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8824 //printf("no-match due to different register (branch)\n");
8828 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8829 //printf("No free regs for store %x\n",start+j*4);
8832 assert(f_regmap[hr]<64);
8839 // Non branch or undetermined branch target
8840 for(hr=0;hr<HOST_REGS;hr++)
8842 if(hr!=EXCLUDE_REG) {
8843 if(regs[i].regmap[hr]>=0) {
8844 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8845 // dealloc old register
8847 for(n=0;n<HOST_REGS;n++)
8849 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8851 // and alloc new one
8852 f_regmap[hr]=regs[i].regmap[hr];
8857 // Try to restore cycle count at branch targets
8859 for(j=i;j<slen-1;j++) {
8860 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8861 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8862 //printf("no free regs for store %x\n",start+j*4);
8866 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8868 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8870 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8871 regs[k].regmap[HOST_CCREG]=CCREG;
8872 regmap_pre[k+1][HOST_CCREG]=CCREG;
8873 regs[k+1].wasdirty|=1<<HOST_CCREG;
8874 regs[k].dirty|=1<<HOST_CCREG;
8875 regs[k].wasconst&=~(1<<HOST_CCREG);
8876 regs[k].isconst&=~(1<<HOST_CCREG);
8879 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8881 // Work backwards from the branch target
8882 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8884 //printf("Extend backwards\n");
8887 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8888 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8889 //printf("no free regs for store %x\n",start+(k-1)*4);
8894 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8895 //printf("Extend CC, %x ->\n",start+k*4);
8897 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8898 regs[k].regmap[HOST_CCREG]=CCREG;
8899 regmap_pre[k+1][HOST_CCREG]=CCREG;
8900 regs[k+1].wasdirty|=1<<HOST_CCREG;
8901 regs[k].dirty|=1<<HOST_CCREG;
8902 regs[k].wasconst&=~(1<<HOST_CCREG);
8903 regs[k].isconst&=~(1<<HOST_CCREG);
8908 //printf("Fail Extend CC, %x ->\n",start+k*4);
8912 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8913 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8914 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8916 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8921 // This allocates registers (if possible) one instruction prior
8922 // to use, which can avoid a load-use penalty on certain CPUs.
8923 for(i=0;i<slen-1;i++)
8925 if (!i || !dops[i-1].is_jump)
8929 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8930 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8933 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8935 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8937 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8938 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8939 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8940 regs[i].isconst&=~(1<<hr);
8941 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8942 constmap[i][hr]=constmap[i+1][hr];
8943 regs[i+1].wasdirty&=~(1<<hr);
8944 regs[i].dirty&=~(1<<hr);
8949 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8951 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8953 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8954 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8955 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8956 regs[i].isconst&=~(1<<hr);
8957 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8958 constmap[i][hr]=constmap[i+1][hr];
8959 regs[i+1].wasdirty&=~(1<<hr);
8960 regs[i].dirty&=~(1<<hr);
8964 // Preload target address for load instruction (non-constant)
8965 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8966 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8968 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8970 regs[i].regmap[hr]=dops[i+1].rs1;
8971 regmap_pre[i+1][hr]=dops[i+1].rs1;
8972 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8973 regs[i].isconst&=~(1<<hr);
8974 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8975 constmap[i][hr]=constmap[i+1][hr];
8976 regs[i+1].wasdirty&=~(1<<hr);
8977 regs[i].dirty&=~(1<<hr);
8981 // Load source into target register
8982 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8983 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8985 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8987 regs[i].regmap[hr]=dops[i+1].rs1;
8988 regmap_pre[i+1][hr]=dops[i+1].rs1;
8989 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8990 regs[i].isconst&=~(1<<hr);
8991 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8992 constmap[i][hr]=constmap[i+1][hr];
8993 regs[i+1].wasdirty&=~(1<<hr);
8994 regs[i].dirty&=~(1<<hr);
8998 // Address for store instruction (non-constant)
8999 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
9000 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
9001 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
9002 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9003 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
9005 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
9006 regs[i+1].isconst&=~(1<<hr);
9009 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9011 regs[i].regmap[hr]=dops[i+1].rs1;
9012 regmap_pre[i+1][hr]=dops[i+1].rs1;
9013 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
9014 regs[i].isconst&=~(1<<hr);
9015 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9016 constmap[i][hr]=constmap[i+1][hr];
9017 regs[i+1].wasdirty&=~(1<<hr);
9018 regs[i].dirty&=~(1<<hr);
9022 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
9023 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
9025 hr=get_reg(regs[i+1].regmap,FTEMP);
9027 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9029 regs[i].regmap[hr]=dops[i+1].rs1;
9030 regmap_pre[i+1][hr]=dops[i+1].rs1;
9031 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
9032 regs[i].isconst&=~(1<<hr);
9033 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9034 constmap[i][hr]=constmap[i+1][hr];
9035 regs[i+1].wasdirty&=~(1<<hr);
9036 regs[i].dirty&=~(1<<hr);
9038 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9040 // move it to another register
9041 regs[i+1].regmap[hr]=-1;
9042 regmap_pre[i+2][hr]=-1;
9043 regs[i+1].regmap[nr]=FTEMP;
9044 regmap_pre[i+2][nr]=FTEMP;
9045 regs[i].regmap[nr]=dops[i+1].rs1;
9046 regmap_pre[i+1][nr]=dops[i+1].rs1;
9047 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
9048 regs[i].isconst&=~(1<<nr);
9049 regs[i+1].isconst&=~(1<<nr);
9050 regs[i].dirty&=~(1<<nr);
9051 regs[i+1].wasdirty&=~(1<<nr);
9052 regs[i+1].dirty&=~(1<<nr);
9053 regs[i+2].wasdirty&=~(1<<nr);
9057 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
9058 if(dops[i+1].itype==LOAD)
9059 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
9060 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
9061 hr=get_reg(regs[i+1].regmap,FTEMP);
9062 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
9063 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9064 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
9066 if(hr>=0&®s[i].regmap[hr]<0) {
9067 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
9068 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9069 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9070 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9071 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9072 regs[i].isconst&=~(1<<hr);
9073 regs[i+1].wasdirty&=~(1<<hr);
9074 regs[i].dirty&=~(1<<hr);
9083 /* Pass 6 - Optimize clean/dirty state */
9084 clean_registers(0,slen-1,1);
9086 /* Pass 7 - Identify 32-bit registers */
9087 for (i=slen-1;i>=0;i--)
9089 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9091 // Conditional branch
9092 if((source[i]>>16)!=0x1000&&i<slen-2) {
9093 // Mark this address as a branch target since it may be called
9094 // upon return from interrupt
9100 if(dops[slen-1].itype==SPAN) {
9101 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
9104 #ifdef REG_ALLOC_PRINT
9105 /* Debug/disassembly */
9110 for(r=1;r<=CCREG;r++) {
9111 if((unneeded_reg[i]>>r)&1) {
9112 if(r==HIREG) printf(" HI");
9113 else if(r==LOREG) printf(" LO");
9114 else printf(" r%d",r);
9118 #if defined(__i386__) || defined(__x86_64__)
9119 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9122 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9124 #if defined(__i386__) || defined(__x86_64__)
9126 if(needed_reg[i]&1) printf("eax ");
9127 if((needed_reg[i]>>1)&1) printf("ecx ");
9128 if((needed_reg[i]>>2)&1) printf("edx ");
9129 if((needed_reg[i]>>3)&1) printf("ebx ");
9130 if((needed_reg[i]>>5)&1) printf("ebp ");
9131 if((needed_reg[i]>>6)&1) printf("esi ");
9132 if((needed_reg[i]>>7)&1) printf("edi ");
9134 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9136 if(regs[i].wasdirty&1) printf("eax ");
9137 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9138 if((regs[i].wasdirty>>2)&1) printf("edx ");
9139 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9140 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9141 if((regs[i].wasdirty>>6)&1) printf("esi ");
9142 if((regs[i].wasdirty>>7)&1) printf("edi ");
9145 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9147 if(regs[i].wasdirty&1) printf("r0 ");
9148 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9149 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9150 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9151 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9152 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9153 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9154 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9155 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9156 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9157 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9158 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9161 disassemble_inst(i);
9162 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9163 #if defined(__i386__) || defined(__x86_64__)
9164 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9165 if(regs[i].dirty&1) printf("eax ");
9166 if((regs[i].dirty>>1)&1) printf("ecx ");
9167 if((regs[i].dirty>>2)&1) printf("edx ");
9168 if((regs[i].dirty>>3)&1) printf("ebx ");
9169 if((regs[i].dirty>>5)&1) printf("ebp ");
9170 if((regs[i].dirty>>6)&1) printf("esi ");
9171 if((regs[i].dirty>>7)&1) printf("edi ");
9174 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9175 if(regs[i].dirty&1) printf("r0 ");
9176 if((regs[i].dirty>>1)&1) printf("r1 ");
9177 if((regs[i].dirty>>2)&1) printf("r2 ");
9178 if((regs[i].dirty>>3)&1) printf("r3 ");
9179 if((regs[i].dirty>>4)&1) printf("r4 ");
9180 if((regs[i].dirty>>5)&1) printf("r5 ");
9181 if((regs[i].dirty>>6)&1) printf("r6 ");
9182 if((regs[i].dirty>>7)&1) printf("r7 ");
9183 if((regs[i].dirty>>8)&1) printf("r8 ");
9184 if((regs[i].dirty>>9)&1) printf("r9 ");
9185 if((regs[i].dirty>>10)&1) printf("r10 ");
9186 if((regs[i].dirty>>12)&1) printf("r12 ");
9189 if(regs[i].isconst) {
9190 printf("constants: ");
9191 #if defined(__i386__) || defined(__x86_64__)
9192 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9193 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9194 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9195 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9196 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9197 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9198 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
9200 #if defined(__arm__) || defined(__aarch64__)
9202 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9203 if ((regs[i].isconst >> r) & 1)
9204 printf(" r%d=%x", r, (u_int)constmap[i][r]);
9208 if(dops[i].is_jump) {
9209 #if defined(__i386__) || defined(__x86_64__)
9210 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9211 if(branch_regs[i].dirty&1) printf("eax ");
9212 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9213 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9214 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9215 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9216 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9217 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9220 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9221 if(branch_regs[i].dirty&1) printf("r0 ");
9222 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9223 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9224 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9225 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9226 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9227 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9228 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9229 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9230 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9231 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9232 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9236 #endif // REG_ALLOC_PRINT
9238 /* Pass 8 - Assembly */
9239 linkcount=0;stubcount=0;
9240 ds=0;is_delayslot=0;
9242 void *beginning=start_block();
9247 void *instr_addr0_override = NULL;
9249 if (start == 0x80030000) {
9250 // nasty hack for the fastbios thing
9251 // override block entry to this code
9252 instr_addr0_override = out;
9253 emit_movimm(start,0);
9254 // abuse io address var as a flag that we
9255 // have already returned here once
9256 emit_readword(&address,1);
9257 emit_writeword(0,&pcaddr);
9258 emit_writeword(0,&address);
9261 emit_jeq(out + 4*2);
9262 emit_far_jump(new_dyna_leave);
9264 emit_jne(new_dyna_leave);
9269 __builtin_prefetch(regs[i+1].regmap);
9270 check_regmap(regmap_pre[i]);
9271 check_regmap(regs[i].regmap_entry);
9272 check_regmap(regs[i].regmap);
9273 //if(ds) printf("ds: ");
9274 disassemble_inst(i);
9276 ds=0; // Skip delay slot
9277 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9278 instr_addr[i] = NULL;
9280 speculate_register_values(i);
9281 #ifndef DESTRUCTIVE_WRITEBACK
9282 if (i < 2 || !dops[i-2].is_ujump)
9284 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9286 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9287 dirty_pre=branch_regs[i].dirty;
9289 dirty_pre=regs[i].dirty;
9293 if (i < 2 || !dops[i-2].is_ujump)
9295 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9296 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9298 // branch target entry point
9299 instr_addr[i] = out;
9300 assem_debug("<->\n");
9301 drc_dbg_emit_do_cmp(i, ccadj[i]);
9302 if (clear_hack_addr) {
9304 emit_writeword(0, &hack_addr);
9305 clear_hack_addr = 0;
9309 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9310 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9311 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9312 address_generation(i,®s[i],regs[i].regmap_entry);
9313 load_consts(regmap_pre[i],regs[i].regmap,i);
9316 // Load the delay slot registers if necessary
9317 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9318 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9319 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9320 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9321 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9322 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9323 if (dops[i+1].is_store)
9324 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9328 // Preload registers for following instruction
9329 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9330 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9331 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9332 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9333 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9334 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9336 // TODO: if(is_ooo(i)) address_generation(i+1);
9337 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9338 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9339 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9340 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9341 if (dops[i].is_store)
9342 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9344 ds = assemble(i, ®s[i], ccadj[i]);
9346 if (dops[i].is_ujump)
9349 literal_pool_jumpover(256);
9354 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9355 // no ending needed for this block since INTCALL never returns
9357 // If the block did not end with an unconditional branch,
9358 // add a jump to the next instruction.
9360 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9361 assert(!dops[i-1].is_jump);
9363 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9364 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9365 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9366 emit_loadreg(CCREG,HOST_CCREG);
9367 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9371 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9372 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9374 add_to_linker(out,start+i*4,0);
9381 assert(!dops[i-1].is_jump);
9382 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9383 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9384 emit_loadreg(CCREG,HOST_CCREG);
9385 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9386 add_to_linker(out,start+i*4,0);
9390 // TODO: delay slot stubs?
9392 for(i=0;i<stubcount;i++)
9394 switch(stubs[i].type)
9402 do_readstub(i);break;
9407 do_writestub(i);break;
9411 do_invstub(i);break;
9413 do_cop1stub(i);break;
9415 do_unalignedwritestub(i);break;
9419 if (instr_addr0_override)
9420 instr_addr[0] = instr_addr0_override;
9422 /* Pass 9 - Linker */
9423 for(i=0;i<linkcount;i++)
9425 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9427 if (!link_addr[i].ext)
9430 void *addr = check_addr(link_addr[i].target);
9431 emit_extjump(link_addr[i].addr, link_addr[i].target);
9433 set_jump_target(link_addr[i].addr, addr);
9434 add_jump_out(link_addr[i].target,stub);
9437 set_jump_target(link_addr[i].addr, stub);
9442 int target=(link_addr[i].target-start)>>2;
9443 assert(target>=0&&target<slen);
9444 assert(instr_addr[target]);
9445 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9446 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9448 set_jump_target(link_addr[i].addr, instr_addr[target]);
9453 u_int source_len = slen*4;
9454 if (dops[slen-1].itype == INTCALL && source_len > 4)
9455 // no need to treat the last instruction as compiled
9456 // as interpreter fully handles it
9459 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9462 // External Branch Targets (jump_in)
9465 if(dops[i].bt||i==0)
9467 if(instr_addr[i]) // TODO - delay slots (=null)
9469 u_int vaddr=start+i*4;
9470 u_int page=get_page(vaddr);
9471 u_int vpage=get_vpage(vaddr);
9474 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9475 assem_debug("jump_in: %x\n",start+i*4);
9476 ll_add(jump_dirty+vpage,vaddr,out);
9477 void *entry_point = do_dirty_stub(i, source_len);
9478 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9479 // If there was an existing entry in the hash table,
9480 // replace it with the new address.
9481 // Don't add new entries. We'll insert the
9482 // ones that actually get used in check_addr().
9483 struct ht_entry *ht_bin = hash_table_get(vaddr);
9484 if (ht_bin->vaddr[0] == vaddr)
9485 ht_bin->tcaddr[0] = entry_point;
9486 if (ht_bin->vaddr[1] == vaddr)
9487 ht_bin->tcaddr[1] = entry_point;
9492 // Write out the literal pool if necessary
9494 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9496 if(((u_int)out)&7) emit_addnop(13);
9498 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9499 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9500 memcpy(copy, source, source_len);
9503 end_block(beginning);
9505 // If we're within 256K of the end of the buffer,
9506 // start over from the beginning. (Is 256K enough?)
9507 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9508 out = ndrc->translation_cache;
9510 // Trap writes to any of the pages we compiled
9511 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9514 inv_code_start=inv_code_end=~0;
9516 // for PCSX we need to mark all mirrors too
9517 if(get_page(start)<(RAM_SIZE>>12))
9518 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9519 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9520 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9521 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9523 /* Pass 10 - Free memory by expiring oldest blocks */
9525 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9528 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9529 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9530 uintptr_t base_offs_s = base_offs >> shift;
9531 inv_debug("EXP: Phase %d\n",expirep);
9532 switch((expirep>>11)&3)
9535 // Clear jump_in and jump_dirty
9536 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9537 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9538 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9539 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9543 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9544 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9549 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9550 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9551 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9552 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9553 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9554 ht_bin->vaddr[1] = -1;
9555 ht_bin->tcaddr[1] = NULL;
9557 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9558 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9559 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9560 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9561 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9562 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9563 ht_bin->vaddr[1] = -1;
9564 ht_bin->tcaddr[1] = NULL;
9570 if((expirep&2047)==0)
9572 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9573 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9576 expirep=(expirep+1)&65535;
9584 // vim:shiftwidth=2:expandtab