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drc: rm unneeded &63 masking
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
57871462 32
d148d265 33#include "new_dynarec_config.h"
3968e69e 34#include "../psxhle.h"
35#include "../psxinterpreter.h"
81dbbf4c 36#include "../gte.h"
37#include "emu_if.h" // emulator interface
57871462 38
d1e4ebd9 39#define noinline __attribute__((noinline,noclone))
b14b6a8f 40#ifndef ARRAY_SIZE
41#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
42#endif
e3c6bdb5 43#ifndef min
44#define min(a, b) ((b) < (a) ? (b) : (a))
45#endif
32631e6a 46#ifndef max
47#define max(a, b) ((b) > (a) ? (b) : (a))
48#endif
b14b6a8f 49
4600ba03 50//#define DISASM
32631e6a 51//#define ASSEM_PRINT
d1150cd6 52//#define REG_ALLOC_PRINT
32631e6a 53
54#ifdef ASSEM_PRINT
55#define assem_debug printf
56#else
4600ba03 57#define assem_debug(...)
32631e6a 58#endif
59//#define inv_debug printf
4600ba03 60#define inv_debug(...)
57871462 61
62#ifdef __i386__
63#include "assem_x86.h"
64#endif
65#ifdef __x86_64__
66#include "assem_x64.h"
67#endif
68#ifdef __arm__
69#include "assem_arm.h"
70#endif
be516ebe 71#ifdef __aarch64__
72#include "assem_arm64.h"
73#endif
57871462 74
81dbbf4c 75#define RAM_SIZE 0x200000
57871462 76#define MAXBLOCK 4096
77#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 78
66ea165f 79#ifdef VITA
80// apparently Vita has a 16MB limit, so either we cut tc in half,
81// or use this hack (it's a hack because tc size was designed to be power-of-2)
82#define TC_REDUCE_BYTES 4096
83#else
84#define TC_REDUCE_BYTES 0
85#endif
86
2a014d73 87struct ndrc_mem
88{
66ea165f 89 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
2a014d73 90 struct
91 {
92 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
93 const void *f[2048 / sizeof(void *)];
94 } tramp;
95};
96
97#ifdef BASE_ADDR_DYNAMIC
98static struct ndrc_mem *ndrc;
99#else
100static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
101static struct ndrc_mem *ndrc = &ndrc_;
102#endif
103
b14b6a8f 104// stubs
105enum stub_type {
106 CC_STUB = 1,
107 FP_STUB = 2,
108 LOADB_STUB = 3,
109 LOADH_STUB = 4,
110 LOADW_STUB = 5,
111 LOADD_STUB = 6,
112 LOADBU_STUB = 7,
113 LOADHU_STUB = 8,
114 STOREB_STUB = 9,
115 STOREH_STUB = 10,
116 STOREW_STUB = 11,
117 STORED_STUB = 12,
118 STORELR_STUB = 13,
119 INVCODE_STUB = 14,
120};
121
6cc8d23c 122// regmap_pre[i] - regs before [i] insn starts; dirty things here that
123// don't match .regmap will be written back
124// [i].regmap_entry - regs that must be set up if someone jumps here
125// [i].regmap - regs [i] insn will read/(over)write
2acc46cd 126// branch_regs[i].* - same as above but for branches, takes delay slot into account
57871462 127struct regstat
128{
6cc8d23c 129 signed char regmap_entry[HOST_REGS];
57871462 130 signed char regmap[HOST_REGS];
57871462 131 uint64_t wasdirty;
132 uint64_t dirty;
133 uint64_t u;
24058131 134 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
135 u_int isconst; // ... but isconst is false when r2 is known
8575a877 136 u_int loadedconst; // host regs that have constants loaded
137 u_int waswritten; // MIPS regs that were used as store base before
57871462 138};
139
de5a60c3 140// note: asm depends on this layout
57871462 141struct ll_entry
142{
143 u_int vaddr;
de5a60c3 144 u_int reg_sv_flags;
57871462 145 void *addr;
146 struct ll_entry *next;
147};
148
df4dc2b1 149struct ht_entry
150{
151 u_int vaddr[2];
152 void *tcaddr[2];
153};
154
b14b6a8f 155struct code_stub
156{
157 enum stub_type type;
158 void *addr;
159 void *retaddr;
160 u_int a;
161 uintptr_t b;
162 uintptr_t c;
163 u_int d;
164 u_int e;
165};
166
643aeae3 167struct link_entry
168{
169 void *addr;
170 u_int target;
171 u_int ext;
172};
173
cf95b4f0 174static struct decoded_insn
175{
176 u_char itype;
177 u_char opcode;
178 u_char opcode2;
179 u_char rs1;
180 u_char rs2;
181 u_char rt1;
182 u_char rt2;
183 u_char lt1;
184 u_char bt:1;
cf95b4f0 185 u_char ooo:1;
186 u_char is_ds:1;
fe807a8a 187 u_char is_jump:1;
188 u_char is_ujump:1;
37387d8b 189 u_char is_load:1;
190 u_char is_store:1;
cf95b4f0 191} dops[MAXBLOCK];
192
e2b5e7aa 193 // used by asm:
194 u_char *out;
df4dc2b1 195 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 196 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
197 struct ll_entry *jump_dirty[4096];
198
199 static struct ll_entry *jump_out[4096];
200 static u_int start;
201 static u_int *source;
202 static char insn[MAXBLOCK][10];
bedfea38 203 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
204 static uint64_t gte_rt[MAXBLOCK];
205 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 206 static u_int smrv[32]; // speculated MIPS register values
207 static u_int smrv_strong; // mask or regs that are likely to have correct values
208 static u_int smrv_weak; // same, but somewhat less likely
209 static u_int smrv_strong_next; // same, but after current insn executes
210 static u_int smrv_weak_next;
e2b5e7aa 211 static int imm[MAXBLOCK];
212 static u_int ba[MAXBLOCK];
e2b5e7aa 213 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 214 static uint64_t branch_unneeded_reg[MAXBLOCK];
6cc8d23c 215 // see 'struct regstat' for a description
2330734f 216 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 217 // contains 'real' consts at [i] insn, but may differ from what's actually
218 // loaded in host reg as 'final' value is always loaded, see get_final_value()
219 static uint32_t current_constmap[HOST_REGS];
220 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 221 static struct regstat regs[MAXBLOCK];
222 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 223 static signed char minimum_free_regs[MAXBLOCK];
224 static u_int needed_reg[MAXBLOCK];
225 static u_int wont_dirty[MAXBLOCK];
226 static u_int will_dirty[MAXBLOCK];
227 static int ccadj[MAXBLOCK];
228 static int slen;
df4dc2b1 229 static void *instr_addr[MAXBLOCK];
643aeae3 230 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 231 static int linkcount;
b14b6a8f 232 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 233 static int stubcount;
234 static u_int literals[1024][2];
235 static int literalcount;
236 static int is_delayslot;
e2b5e7aa 237 static char shadow[1048576] __attribute__((aligned(16)));
238 static void *copy;
239 static int expirep;
240 static u_int stop_after_jal;
7f94b097 241 static u_int f1_hack;
e2b5e7aa 242
243 int new_dynarec_hacks;
d62c125a 244 int new_dynarec_hacks_pergame;
32631e6a 245 int new_dynarec_hacks_old;
e2b5e7aa 246 int new_dynarec_did_compile;
687b4580 247
d62c125a 248 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
249
687b4580 250 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
251 extern int last_count; // last absolute target, often = next_interupt
252 extern int pcaddr;
253 extern int pending_exception;
254 extern int branch_target;
37387d8b 255 extern uintptr_t ram_offset;
d1e4ebd9 256 extern uintptr_t mini_ht[32][2];
57871462 257 extern u_char restore_candidate[512];
57871462 258
259 /* registers that may be allocated */
260 /* 1-31 gpr */
7c3a5182 261#define LOREG 32 // lo
262#define HIREG 33 // hi
00fa9369 263//#define FSREG 34 // FPU status (FCSR)
57871462 264#define CSREG 35 // Coprocessor status
265#define CCREG 36 // Cycle count
266#define INVCP 37 // Pointer to invalid_code
1edfcc68 267//#define MMREG 38 // Pointer to memory_map
37387d8b 268#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 269#define TEMPREG 40
270#define FTEMP 40 // FPU temporary register
271#define PTEMP 41 // Prefetch temporary register
1edfcc68 272//#define TLREG 42 // TLB mapping offset
619e5ded 273#define RHASH 43 // Return address hash
274#define RHTBL 44 // Return address hash table address
275#define RTEMP 45 // JR/JALR address register
276#define MAXREG 45
277#define AGEN1 46 // Address generation temporary register
1edfcc68 278//#define AGEN2 47 // Address generation temporary register
279//#define MGEN1 48 // Maptable address generation temporary register
280//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 281#define BTREG 50 // Branch target temporary register
57871462 282
283 /* instruction types */
284#define NOP 0 // No operation
285#define LOAD 1 // Load
286#define STORE 2 // Store
287#define LOADLR 3 // Unaligned load
288#define STORELR 4 // Unaligned store
9f51b4b9 289#define MOV 5 // Move
57871462 290#define ALU 6 // Arithmetic/logic
291#define MULTDIV 7 // Multiply/divide
292#define SHIFT 8 // Shift by register
293#define SHIFTIMM 9// Shift by immediate
294#define IMM16 10 // 16-bit immediate
295#define RJUMP 11 // Unconditional jump to register
296#define UJUMP 12 // Unconditional jump
297#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
298#define SJUMP 14 // Conditional branch (regimm format)
299#define COP0 15 // Coprocessor 0
300#define COP1 16 // Coprocessor 1
301#define C1LS 17 // Coprocessor 1 load/store
ad49de89 302//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 303//#define FLOAT 19 // Floating point unit
304//#define FCONV 20 // Convert integer to float
305//#define FCOMP 21 // Floating point compare (sets FSREG)
d1150cd6 306#define SYSCALL 22// SYSCALL,BREAK
57871462 307#define OTHER 23 // Other
308#define SPAN 24 // Branch/delay slot spans 2 pages
309#define NI 25 // Not implemented
7139f3c8 310#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 311#define COP2 27 // Coprocessor 2 move
312#define C2LS 28 // Coprocessor 2 load/store
313#define C2OP 29 // Coprocessor 2 operation
1e973cb0 314#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 315
57871462 316 /* branch codes */
317#define TAKEN 1
318#define NOTTAKEN 2
319#define NULLDS 3
320
7c3a5182 321#define DJT_1 (void *)1l // no function, just a label in assem_debug log
322#define DJT_2 (void *)2l
323
57871462 324// asm linkage
3968e69e 325int new_recompile_block(u_int addr);
57871462 326void *get_addr_ht(u_int vaddr);
327void invalidate_block(u_int block);
328void invalidate_addr(u_int addr);
329void remove_hash(int vaddr);
57871462 330void dyna_linker();
331void dyna_linker_ds();
332void verify_code();
57871462 333void verify_code_ds();
334void cc_interrupt();
335void fp_exception();
336void fp_exception_ds();
d1150cd6 337void jump_syscall (u_int u0, u_int u1, u_int pc);
338void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
339void jump_break (u_int u0, u_int u1, u_int pc);
340void jump_break_ds(u_int u0, u_int u1, u_int pc);
3968e69e 341void jump_to_new_pc();
81dbbf4c 342void call_gteStall();
7139f3c8 343void new_dyna_leave();
57871462 344
57871462 345// Needed by assembler
2330734f 346static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
347static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
348static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
349static void load_all_regs(const signed char i_regmap[]);
350static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 351static void load_regs_entry(int t);
2330734f 352static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 353static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 354
3968e69e 355static int verify_dirty(const u_int *ptr);
e2b5e7aa 356static int get_final_value(int hr, int i, int *value);
b14b6a8f 357static void add_stub(enum stub_type type, void *addr, void *retaddr,
358 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
359static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 360 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 361static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 362static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
363 int addr, int *offset_reg, int *addr_reg_override);
687b4580 364static void *get_direct_memhandler(void *table, u_int addr,
365 enum stub_type type, uintptr_t *addr_host);
32631e6a 366static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 367static void pass_args(int a0, int a1);
2a014d73 368static void emit_far_jump(const void *f);
369static void emit_far_call(const void *f);
57871462 370
9c67c98f 371#ifdef VITA
372#include <psp2/kernel/sysmem.h>
373static int sceBlock;
374// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
375extern int getVMBlock();
376int _newlib_vm_size_user = sizeof(*ndrc);
377#endif
378
d148d265 379static void mprotect_w_x(void *start, void *end, int is_x)
380{
381#ifdef NO_WRITE_EXEC
1e212a25 382 #if defined(VITA)
383 // *Open* enables write on all memory that was
384 // allocated by sceKernelAllocMemBlockForVM()?
385 if (is_x)
386 sceKernelCloseVMDomain();
387 else
388 sceKernelOpenVMDomain();
389 #else
d148d265 390 u_long mstart = (u_long)start & ~4095ul;
391 u_long mend = (u_long)end;
392 if (mprotect((void *)mstart, mend - mstart,
393 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
394 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 395 #endif
d148d265 396#endif
397}
398
399static void start_tcache_write(void *start, void *end)
400{
401 mprotect_w_x(start, end, 0);
402}
403
404static void end_tcache_write(void *start, void *end)
405{
919981d0 406#if defined(__arm__) || defined(__aarch64__)
d148d265 407 size_t len = (char *)end - (char *)start;
408 #if defined(__BLACKBERRY_QNX__)
409 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
410 #elif defined(__MACH__)
411 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
412 #elif defined(VITA)
1e212a25 413 sceKernelSyncVMDomain(sceBlock, start, len);
414 #elif defined(_3DS)
415 ctr_flush_invalidate_cache();
919981d0 416 #elif defined(__aarch64__)
417 // as of 2021, __clear_cache() is still broken on arm64
418 // so here is a custom one :(
419 clear_cache_arm64(start, end);
d148d265 420 #else
421 __clear_cache(start, end);
422 #endif
423 (void)len;
424#endif
425
426 mprotect_w_x(start, end, 1);
427}
428
429static void *start_block(void)
430{
431 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 432 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
433 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 434 start_tcache_write(out, end);
435 return out;
436}
437
438static void end_block(void *start)
439{
440 end_tcache_write(start, out);
441}
442
919981d0 443// also takes care of w^x mappings when patching code
444static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
445
446static void mark_clear_cache(void *target)
447{
448 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
449 u_int mask = 1u << ((offset >> 12) & 31);
450 if (!(needs_clear_cache[offset >> 17] & mask)) {
451 char *start = (char *)((uintptr_t)target & ~4095l);
452 start_tcache_write(start, start + 4095);
453 needs_clear_cache[offset >> 17] |= mask;
454 }
455}
456
457// Clearing the cache is rather slow on ARM Linux, so mark the areas
458// that need to be cleared, and then only clear these areas once.
459static void do_clear_cache(void)
460{
461 int i, j;
462 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
463 {
464 u_int bitmap = needs_clear_cache[i];
465 if (!bitmap)
466 continue;
467 for (j = 0; j < 32; j++)
468 {
469 u_char *start, *end;
470 if (!(bitmap & (1<<j)))
471 continue;
472
473 start = ndrc->translation_cache + i*131072 + j*4096;
474 end = start + 4095;
475 for (j++; j < 32; j++) {
476 if (!(bitmap & (1<<j)))
477 break;
478 end += 4096;
479 }
480 end_tcache_write(start, end);
481 }
482 needs_clear_cache[i] = 0;
483 }
484}
485
57871462 486//#define DEBUG_CYCLE_COUNT 1
487
b6e87b2b 488#define NO_CYCLE_PENALTY_THR 12
489
26bd3dad 490int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 491int cycle_multiplier_override;
32631e6a 492int cycle_multiplier_old;
24058131 493static int cycle_multiplier_active;
4e9dcd7f 494
495static int CLOCK_ADJUST(int x)
496{
24058131 497 int m = cycle_multiplier_active;
498 int s = (x >> 31) | 1;
a3203cf4 499 return (x * m + s * 50) / 100;
4e9dcd7f 500}
501
4919de1e 502static int ds_writes_rjump_rs(int i)
503{
cf95b4f0 504 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 505}
506
94d23bb9 507static u_int get_page(u_int vaddr)
57871462 508{
0ce47d46 509 u_int page=vaddr&~0xe0000000;
510 if (page < 0x1000000)
511 page &= ~0x0e00000; // RAM mirrors
512 page>>=12;
57871462 513 if(page>2048) page=2048+(page&2047);
94d23bb9 514 return page;
515}
516
d25604ca 517// no virtual mem in PCSX
518static u_int get_vpage(u_int vaddr)
519{
520 return get_page(vaddr);
521}
94d23bb9 522
df4dc2b1 523static struct ht_entry *hash_table_get(u_int vaddr)
524{
525 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
526}
527
528static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
529{
530 ht_bin->vaddr[1] = ht_bin->vaddr[0];
531 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
532 ht_bin->vaddr[0] = vaddr;
533 ht_bin->tcaddr[0] = tcaddr;
534}
535
536// some messy ari64's code, seems to rely on unsigned 32bit overflow
537static int doesnt_expire_soon(void *tcaddr)
538{
539 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
540 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
541}
542
94d23bb9 543// Get address from virtual address
544// This is called from the recompiled JR/JALR instructions
d1e4ebd9 545void noinline *get_addr(u_int vaddr)
94d23bb9 546{
547 u_int page=get_page(vaddr);
548 u_int vpage=get_vpage(vaddr);
57871462 549 struct ll_entry *head;
550 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
551 head=jump_in[page];
552 while(head!=NULL) {
de5a60c3 553 if(head->vaddr==vaddr) {
643aeae3 554 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 555 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 556 return head->addr;
557 }
558 head=head->next;
559 }
560 head=jump_dirty[vpage];
561 while(head!=NULL) {
de5a60c3 562 if(head->vaddr==vaddr) {
643aeae3 563 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 564 // Don't restore blocks which are about to expire from the cache
df4dc2b1 565 if (doesnt_expire_soon(head->addr))
566 if (verify_dirty(head->addr)) {
57871462 567 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
568 invalid_code[vaddr>>12]=0;
9be4ba64 569 inv_code_start=inv_code_end=~0;
57871462 570 if(vpage<2048) {
57871462 571 restore_candidate[vpage>>3]|=1<<(vpage&7);
572 }
573 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 574 struct ht_entry *ht_bin = hash_table_get(vaddr);
575 if (ht_bin->vaddr[0] == vaddr)
576 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 577 else
df4dc2b1 578 hash_table_add(ht_bin, vaddr, head->addr);
579
57871462 580 return head->addr;
581 }
582 }
583 head=head->next;
584 }
585 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
586 int r=new_recompile_block(vaddr);
587 if(r==0) return get_addr(vaddr);
b4ab351d 588 // generate an address error
57871462 589 Status|=2;
b4ab351d 590 Cause=(vaddr<<31)|(4<<2);
57871462 591 EPC=(vaddr&1)?vaddr-5:vaddr;
592 BadVAddr=(vaddr&~1);
b4ab351d 593 return get_addr_ht(0x80000080);
57871462 594}
595// Look up address in hash table first
596void *get_addr_ht(u_int vaddr)
597{
598 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 599 const struct ht_entry *ht_bin = hash_table_get(vaddr);
600 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
601 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 602 return get_addr(vaddr);
603}
604
6cc8d23c 605static void clear_all_regs(signed char regmap[])
57871462 606{
6cc8d23c 607 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
57871462 608}
609
9de8a0c3 610static signed char get_reg(const signed char regmap[], signed char r)
57871462 611{
612 int hr;
9de8a0c3 613 for (hr = 0; hr < HOST_REGS; hr++) {
614 if (hr == EXCLUDE_REG)
615 continue;
616 if (regmap[hr] == r)
617 return hr;
618 }
619 return -1;
620}
621
622static signed char get_reg_temp(const signed char regmap[])
623{
624 int hr;
625 for (hr = 0; hr < HOST_REGS; hr++) {
626 if (hr == EXCLUDE_REG)
627 continue;
628 if (regmap[hr] == (signed char)-1)
629 return hr;
630 }
57871462 631 return -1;
632}
633
634// Find a register that is available for two consecutive cycles
d1e4ebd9 635static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 636{
637 int hr;
638 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
639 return -1;
640}
641
9de8a0c3 642static int count_free_regs(const signed char regmap[])
57871462 643{
644 int count=0;
645 int hr;
646 for(hr=0;hr<HOST_REGS;hr++)
647 {
648 if(hr!=EXCLUDE_REG) {
649 if(regmap[hr]<0) count++;
650 }
651 }
652 return count;
653}
654
9de8a0c3 655static void dirty_reg(struct regstat *cur, signed char reg)
57871462 656{
657 int hr;
9de8a0c3 658 if (!reg) return;
659 hr = get_reg(cur->regmap, reg);
660 if (hr >= 0)
661 cur->dirty |= 1<<hr;
57871462 662}
663
40fca85b 664static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 665{
666 int hr;
9de8a0c3 667 if (!reg) return;
668 hr = get_reg(cur->regmap, reg);
669 if (hr >= 0) {
670 cur->isconst |= 1<<hr;
671 current_constmap[hr] = value;
57871462 672 }
673}
674
40fca85b 675static void clear_const(struct regstat *cur, signed char reg)
57871462 676{
677 int hr;
9de8a0c3 678 if (!reg) return;
679 hr = get_reg(cur->regmap, reg);
680 if (hr >= 0)
681 cur->isconst &= ~(1<<hr);
57871462 682}
683
9de8a0c3 684static int is_const(const struct regstat *cur, signed char reg)
57871462 685{
686 int hr;
9de8a0c3 687 if (reg < 0) return 0;
688 if (!reg) return 1;
689 hr = get_reg(cur->regmap, reg);
690 if (hr >= 0)
691 return (cur->isconst>>hr)&1;
57871462 692 return 0;
693}
40fca85b 694
9de8a0c3 695static uint32_t get_const(const struct regstat *cur, signed char reg)
57871462 696{
697 int hr;
9de8a0c3 698 if (!reg) return 0;
699 hr = get_reg(cur->regmap, reg);
700 if (hr >= 0)
701 return current_constmap[hr];
702
703 SysPrintf("Unknown constant in r%d\n", reg);
7c3a5182 704 abort();
57871462 705}
706
707// Least soon needed registers
708// Look at the next ten instructions and see which registers
709// will be used. Try not to reallocate these.
710void lsn(u_char hsn[], int i, int *preferred_reg)
711{
712 int j;
713 int b=-1;
714 for(j=0;j<9;j++)
715 {
716 if(i+j>=slen) {
717 j=slen-i-1;
718 break;
719 }
fe807a8a 720 if (dops[i+j].is_ujump)
57871462 721 {
722 // Don't go past an unconditonal jump
723 j++;
724 break;
725 }
726 }
727 for(;j>=0;j--)
728 {
cf95b4f0 729 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
730 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
731 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
732 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
733 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 734 // Stores can allocate zero
cf95b4f0 735 hsn[dops[i+j].rs1]=j;
736 hsn[dops[i+j].rs2]=j;
57871462 737 }
37387d8b 738 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
739 hsn[ROREG] = j;
57871462 740 // On some architectures stores need invc_ptr
741 #if defined(HOST_IMM8)
37387d8b 742 if (dops[i+j].is_store)
743 hsn[INVCP] = j;
57871462 744 #endif
cf95b4f0 745 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 746 {
747 hsn[CCREG]=j;
748 b=j;
749 }
750 }
751 if(b>=0)
752 {
753 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
754 {
755 // Follow first branch
756 int t=(ba[i+b]-start)>>2;
757 j=7-b;if(t+j>=slen) j=slen-t-1;
758 for(;j>=0;j--)
759 {
cf95b4f0 760 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
761 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
762 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
763 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 764 }
765 }
766 // TODO: preferred register based on backward branch
767 }
768 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 769 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 770 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
771 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 772 hsn[CCREG]=1;
773 // ...or hash tables
774 hsn[RHASH]=1;
775 hsn[RHTBL]=1;
776 }
777 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 778 if(dops[i].itype==C2LS) {
57871462 779 hsn[FTEMP]=0;
780 }
781 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 782 if(dops[i].itype==LOADLR) {
57871462 783 hsn[FTEMP]=0;
784 }
b7918751 785 // Also SWL/SWR/SDL/SDR
cf95b4f0 786 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 787 hsn[FTEMP]=0;
788 }
57871462 789 // Don't remove the miniht registers
cf95b4f0 790 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 791 {
792 hsn[RHASH]=0;
793 hsn[RHTBL]=0;
794 }
795}
796
797// We only want to allocate registers if we're going to use them again soon
798int needed_again(int r, int i)
799{
800 int j;
801 int b=-1;
802 int rn=10;
9f51b4b9 803
fe807a8a 804 if (i > 0 && dops[i-1].is_ujump)
57871462 805 {
806 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
807 return 0; // Don't need any registers if exiting the block
808 }
809 for(j=0;j<9;j++)
810 {
811 if(i+j>=slen) {
812 j=slen-i-1;
813 break;
814 }
fe807a8a 815 if (dops[i+j].is_ujump)
57871462 816 {
817 // Don't go past an unconditonal jump
818 j++;
819 break;
820 }
cf95b4f0 821 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 822 {
823 break;
824 }
825 }
826 for(;j>=1;j--)
827 {
cf95b4f0 828 if(dops[i+j].rs1==r) rn=j;
829 if(dops[i+j].rs2==r) rn=j;
57871462 830 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 831 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 832 {
833 b=j;
834 }
835 }
b7217e13 836 if(rn<10) return 1;
581335b0 837 (void)b;
57871462 838 return 0;
839}
840
841// Try to match register allocations at the end of a loop with those
842// at the beginning
843int loop_reg(int i, int r, int hr)
844{
845 int j,k;
846 for(j=0;j<9;j++)
847 {
848 if(i+j>=slen) {
849 j=slen-i-1;
850 break;
851 }
fe807a8a 852 if (dops[i+j].is_ujump)
57871462 853 {
854 // Don't go past an unconditonal jump
855 j++;
856 break;
857 }
858 }
859 k=0;
860 if(i>0){
cf95b4f0 861 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 862 k--;
863 }
864 for(;k<j;k++)
865 {
00fa9369 866 assert(r < 64);
867 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 868 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 869 {
870 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
871 {
872 int t=(ba[i+k]-start)>>2;
873 int reg=get_reg(regs[t].regmap_entry,r);
874 if(reg>=0) return reg;
875 //reg=get_reg(regs[t+1].regmap_entry,r);
876 //if(reg>=0) return reg;
877 }
878 }
879 }
880 return hr;
881}
882
883
884// Allocate every register, preserving source/target regs
885void alloc_all(struct regstat *cur,int i)
886{
887 int hr;
9f51b4b9 888
57871462 889 for(hr=0;hr<HOST_REGS;hr++) {
890 if(hr!=EXCLUDE_REG) {
9de8a0c3 891 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
892 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
57871462 893 {
894 cur->regmap[hr]=-1;
895 cur->dirty&=~(1<<hr);
896 }
897 // Don't need zeros
9de8a0c3 898 if(cur->regmap[hr]==0)
57871462 899 {
900 cur->regmap[hr]=-1;
901 cur->dirty&=~(1<<hr);
902 }
903 }
904 }
905}
906
d1e4ebd9 907#ifndef NDEBUG
908static int host_tempreg_in_use;
909
910static void host_tempreg_acquire(void)
911{
912 assert(!host_tempreg_in_use);
913 host_tempreg_in_use = 1;
914}
915
916static void host_tempreg_release(void)
917{
918 host_tempreg_in_use = 0;
919}
920#else
921static void host_tempreg_acquire(void) {}
922static void host_tempreg_release(void) {}
923#endif
924
32631e6a 925#ifdef ASSEM_PRINT
8062d65a 926extern void gen_interupt();
927extern void do_insn_cmp();
d1e4ebd9 928#define FUNCNAME(f) { f, " " #f }
8062d65a 929static const struct {
d1e4ebd9 930 void *addr;
8062d65a 931 const char *name;
932} function_names[] = {
933 FUNCNAME(cc_interrupt),
934 FUNCNAME(gen_interupt),
935 FUNCNAME(get_addr_ht),
936 FUNCNAME(get_addr),
937 FUNCNAME(jump_handler_read8),
938 FUNCNAME(jump_handler_read16),
939 FUNCNAME(jump_handler_read32),
940 FUNCNAME(jump_handler_write8),
941 FUNCNAME(jump_handler_write16),
942 FUNCNAME(jump_handler_write32),
943 FUNCNAME(invalidate_addr),
3968e69e 944 FUNCNAME(jump_to_new_pc),
d1150cd6 945 FUNCNAME(jump_break),
946 FUNCNAME(jump_break_ds),
947 FUNCNAME(jump_syscall),
948 FUNCNAME(jump_syscall_ds),
81dbbf4c 949 FUNCNAME(call_gteStall),
8062d65a 950 FUNCNAME(new_dyna_leave),
951 FUNCNAME(pcsx_mtc0),
952 FUNCNAME(pcsx_mtc0_ds),
32631e6a 953#ifdef DRC_DBG
8062d65a 954 FUNCNAME(do_insn_cmp),
32631e6a 955#endif
3968e69e 956#ifdef __arm__
957 FUNCNAME(verify_code),
958#endif
8062d65a 959};
960
d1e4ebd9 961static const char *func_name(const void *a)
8062d65a 962{
963 int i;
964 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
965 if (function_names[i].addr == a)
966 return function_names[i].name;
967 return "";
968}
969#else
970#define func_name(x) ""
971#endif
972
57871462 973#ifdef __i386__
974#include "assem_x86.c"
975#endif
976#ifdef __x86_64__
977#include "assem_x64.c"
978#endif
979#ifdef __arm__
980#include "assem_arm.c"
981#endif
be516ebe 982#ifdef __aarch64__
983#include "assem_arm64.c"
984#endif
57871462 985
2a014d73 986static void *get_trampoline(const void *f)
987{
988 size_t i;
989
990 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
991 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
992 break;
993 }
994 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
995 SysPrintf("trampoline table is full, last func %p\n", f);
996 abort();
997 }
998 if (ndrc->tramp.f[i] == NULL) {
999 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1000 ndrc->tramp.f[i] = f;
1001 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1002 }
1003 return &ndrc->tramp.ops[i];
1004}
1005
1006static void emit_far_jump(const void *f)
1007{
1008 if (can_jump_or_call(f)) {
1009 emit_jmp(f);
1010 return;
1011 }
1012
1013 f = get_trampoline(f);
1014 emit_jmp(f);
1015}
1016
1017static void emit_far_call(const void *f)
1018{
1019 if (can_jump_or_call(f)) {
1020 emit_call(f);
1021 return;
1022 }
1023
1024 f = get_trampoline(f);
1025 emit_call(f);
1026}
1027
57871462 1028// Add virtual address mapping to linked list
1029void ll_add(struct ll_entry **head,int vaddr,void *addr)
1030{
1031 struct ll_entry *new_entry;
1032 new_entry=malloc(sizeof(struct ll_entry));
1033 assert(new_entry!=NULL);
1034 new_entry->vaddr=vaddr;
de5a60c3 1035 new_entry->reg_sv_flags=0;
57871462 1036 new_entry->addr=addr;
1037 new_entry->next=*head;
1038 *head=new_entry;
1039}
1040
de5a60c3 1041void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1042{
7139f3c8 1043 ll_add(head,vaddr,addr);
de5a60c3 1044 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1045}
1046
1047// Check if an address is already compiled
1048// but don't return addresses which are about to expire from the cache
1049void *check_addr(u_int vaddr)
1050{
df4dc2b1 1051 struct ht_entry *ht_bin = hash_table_get(vaddr);
1052 size_t i;
b14b6a8f 1053 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1054 if (ht_bin->vaddr[i] == vaddr)
1055 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1056 if (isclean(ht_bin->tcaddr[i]))
1057 return ht_bin->tcaddr[i];
57871462 1058 }
94d23bb9 1059 u_int page=get_page(vaddr);
57871462 1060 struct ll_entry *head;
1061 head=jump_in[page];
df4dc2b1 1062 while (head != NULL) {
1063 if (head->vaddr == vaddr) {
1064 if (doesnt_expire_soon(head->addr)) {
57871462 1065 // Update existing entry with current address
df4dc2b1 1066 if (ht_bin->vaddr[0] == vaddr) {
1067 ht_bin->tcaddr[0] = head->addr;
57871462 1068 return head->addr;
1069 }
df4dc2b1 1070 if (ht_bin->vaddr[1] == vaddr) {
1071 ht_bin->tcaddr[1] = head->addr;
57871462 1072 return head->addr;
1073 }
1074 // Insert into hash table with low priority.
1075 // Don't evict existing entries, as they are probably
1076 // addresses that are being accessed frequently.
df4dc2b1 1077 if (ht_bin->vaddr[0] == -1) {
1078 ht_bin->vaddr[0] = vaddr;
1079 ht_bin->tcaddr[0] = head->addr;
1080 }
1081 else if (ht_bin->vaddr[1] == -1) {
1082 ht_bin->vaddr[1] = vaddr;
1083 ht_bin->tcaddr[1] = head->addr;
57871462 1084 }
1085 return head->addr;
1086 }
1087 }
1088 head=head->next;
1089 }
1090 return 0;
1091}
1092
1093void remove_hash(int vaddr)
1094{
1095 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1096 struct ht_entry *ht_bin = hash_table_get(vaddr);
1097 if (ht_bin->vaddr[1] == vaddr) {
1098 ht_bin->vaddr[1] = -1;
1099 ht_bin->tcaddr[1] = NULL;
57871462 1100 }
df4dc2b1 1101 if (ht_bin->vaddr[0] == vaddr) {
1102 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1103 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1104 ht_bin->vaddr[1] = -1;
1105 ht_bin->tcaddr[1] = NULL;
57871462 1106 }
1107}
1108
943f42f3 1109static void ll_remove_matching_addrs(struct ll_entry **head,
1110 uintptr_t base_offs_s, int shift)
57871462 1111{
1112 struct ll_entry *next;
1113 while(*head) {
943f42f3 1114 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1115 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1116 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1117 {
643aeae3 1118 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1119 remove_hash((*head)->vaddr);
1120 next=(*head)->next;
1121 free(*head);
1122 *head=next;
1123 }
1124 else
1125 {
1126 head=&((*head)->next);
1127 }
1128 }
1129}
1130
1131// Remove all entries from linked list
1132void ll_clear(struct ll_entry **head)
1133{
1134 struct ll_entry *cur;
1135 struct ll_entry *next;
581335b0 1136 if((cur=*head)) {
57871462 1137 *head=0;
1138 while(cur) {
1139 next=cur->next;
1140 free(cur);
1141 cur=next;
1142 }
1143 }
1144}
1145
1146// Dereference the pointers and remove if it matches
943f42f3 1147static void ll_kill_pointers(struct ll_entry *head,
1148 uintptr_t base_offs_s, int shift)
57871462 1149{
1150 while(head) {
943f42f3 1151 u_char *ptr = get_pointer(head->addr);
1152 uintptr_t o1 = ptr - ndrc->translation_cache;
1153 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1154 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1155 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1156 {
643aeae3 1157 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1158 void *host_addr=find_extjump_insn(head->addr);
919981d0 1159 mark_clear_cache(host_addr);
df4dc2b1 1160 set_jump_target(host_addr, head->addr);
57871462 1161 }
1162 head=head->next;
1163 }
1164}
1165
1166// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1167static void invalidate_page(u_int page)
57871462 1168{
57871462 1169 struct ll_entry *head;
1170 struct ll_entry *next;
1171 head=jump_in[page];
1172 jump_in[page]=0;
1173 while(head!=NULL) {
1174 inv_debug("INVALIDATE: %x\n",head->vaddr);
1175 remove_hash(head->vaddr);
1176 next=head->next;
1177 free(head);
1178 head=next;
1179 }
1180 head=jump_out[page];
1181 jump_out[page]=0;
1182 while(head!=NULL) {
643aeae3 1183 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1184 void *host_addr=find_extjump_insn(head->addr);
919981d0 1185 mark_clear_cache(host_addr);
3d680478 1186 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1187 next=head->next;
1188 free(head);
1189 head=next;
1190 }
57871462 1191}
9be4ba64 1192
1193static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1194{
94d23bb9 1195 u_int page=get_page(block<<12);
57871462 1196 //printf("first=%d last=%d\n",first,last);
f76eeef9 1197 invalidate_page(page);
57871462 1198 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1199 assert(last<page+5);
1200 // Invalidate the adjacent pages if a block crosses a 4K boundary
1201 while(first<page) {
1202 invalidate_page(first);
1203 first++;
1204 }
1205 for(first=page+1;first<last;first++) {
1206 invalidate_page(first);
1207 }
919981d0 1208 do_clear_cache();
9f51b4b9 1209
57871462 1210 // Don't trap writes
1211 invalid_code[block]=1;
f76eeef9 1212
57871462 1213 #ifdef USE_MINI_HT
1214 memset(mini_ht,-1,sizeof(mini_ht));
1215 #endif
1216}
9be4ba64 1217
1218void invalidate_block(u_int block)
1219{
1220 u_int page=get_page(block<<12);
1221 u_int vpage=get_vpage(block<<12);
1222 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1223 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1224 u_int first,last;
1225 first=last=page;
1226 struct ll_entry *head;
1227 head=jump_dirty[vpage];
1228 //printf("page=%d vpage=%d\n",page,vpage);
1229 while(head!=NULL) {
9be4ba64 1230 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1231 u_char *start, *end;
1232 get_bounds(head->addr, &start, &end);
1233 //printf("start: %p end: %p\n", start, end);
1234 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1235 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1236 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1237 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1238 }
1239 }
9be4ba64 1240 }
1241 head=head->next;
1242 }
1243 invalidate_block_range(block,first,last);
1244}
1245
57871462 1246void invalidate_addr(u_int addr)
1247{
9be4ba64 1248 //static int rhits;
1249 // this check is done by the caller
1250 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1251 u_int page=get_vpage(addr);
9be4ba64 1252 if(page<2048) { // RAM
1253 struct ll_entry *head;
1254 u_int addr_min=~0, addr_max=0;
4a35de07 1255 u_int mask=RAM_SIZE-1;
1256 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1257 int pg1;
4a35de07 1258 inv_code_start=addr_main&~0xfff;
1259 inv_code_end=addr_main|0xfff;
9be4ba64 1260 pg1=page;
1261 if (pg1>0) {
1262 // must check previous page too because of spans..
1263 pg1--;
1264 inv_code_start-=0x1000;
1265 }
1266 for(;pg1<=page;pg1++) {
1267 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1268 u_char *start_h, *end_h;
1269 u_int start, end;
1270 get_bounds(head->addr, &start_h, &end_h);
1271 start = (uintptr_t)start_h - ram_offset;
1272 end = (uintptr_t)end_h - ram_offset;
4a35de07 1273 if(start<=addr_main&&addr_main<end) {
9be4ba64 1274 if(start<addr_min) addr_min=start;
1275 if(end>addr_max) addr_max=end;
1276 }
4a35de07 1277 else if(addr_main<start) {
9be4ba64 1278 if(start<inv_code_end)
1279 inv_code_end=start-1;
1280 }
1281 else {
1282 if(end>inv_code_start)
1283 inv_code_start=end;
1284 }
1285 }
1286 }
1287 if (addr_min!=~0) {
1288 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1289 inv_code_start=inv_code_end=~0;
1290 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1291 return;
1292 }
1293 else {
4a35de07 1294 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1295 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1296 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1297 return;
d25604ca 1298 }
9be4ba64 1299 }
57871462 1300 invalidate_block(addr>>12);
1301}
9be4ba64 1302
dd3a91a1 1303// This is called when loading a save state.
1304// Anything could have changed, so invalidate everything.
919981d0 1305void invalidate_all_pages(void)
57871462 1306{
581335b0 1307 u_int page;
57871462 1308 for(page=0;page<4096;page++)
1309 invalidate_page(page);
1310 for(page=0;page<1048576;page++)
1311 if(!invalid_code[page]) {
1312 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1313 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1314 }
57871462 1315 #ifdef USE_MINI_HT
1316 memset(mini_ht,-1,sizeof(mini_ht));
1317 #endif
919981d0 1318 do_clear_cache();
57871462 1319}
1320
d1e4ebd9 1321static void do_invstub(int n)
1322{
1323 literal_pool(20);
1324 u_int reglist=stubs[n].a;
1325 set_jump_target(stubs[n].addr, out);
1326 save_regs(reglist);
1327 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1328 emit_far_call(invalidate_addr);
d1e4ebd9 1329 restore_regs(reglist);
1330 emit_jmp(stubs[n].retaddr); // return address
1331}
1332
57871462 1333// Add an entry to jump_out after making a link
d1e4ebd9 1334// src should point to code by emit_extjump2()
3d680478 1335void add_jump_out(u_int vaddr,void *src)
57871462 1336{
94d23bb9 1337 u_int page=get_page(vaddr);
3d680478 1338 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1339 check_extjump2(src);
57871462 1340 ll_add(jump_out+page,vaddr,src);
3d680478 1341 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1342}
1343
1344// If a code block was found to be unmodified (bit was set in
1345// restore_candidate) and it remains unmodified (bit is clear
1346// in invalid_code) then move the entries for that 4K page from
1347// the dirty list to the clean list.
1348void clean_blocks(u_int page)
1349{
1350 struct ll_entry *head;
1351 inv_debug("INV: clean_blocks page=%d\n",page);
1352 head=jump_dirty[page];
1353 while(head!=NULL) {
1354 if(!invalid_code[head->vaddr>>12]) {
1355 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1356 if (doesnt_expire_soon(head->addr)) {
581335b0 1357 if(verify_dirty(head->addr)) {
01d26796 1358 u_char *start, *end;
643aeae3 1359 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1360 u_int i;
1361 u_int inv=0;
01d26796 1362 get_bounds(head->addr, &start, &end);
1363 if (start - rdram < RAM_SIZE) {
1364 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1365 inv|=invalid_code[i];
1366 }
1367 }
4cb76aa4 1368 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1369 inv=1;
1370 }
1371 if(!inv) {
df4dc2b1 1372 void *clean_addr = get_clean_addr(head->addr);
1373 if (doesnt_expire_soon(clean_addr)) {
57871462 1374 u_int ppage=page;
643aeae3 1375 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1376 //printf("page=%x, addr=%x\n",page,head->vaddr);
1377 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1378 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1379 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1380 if (ht_bin->vaddr[0] == head->vaddr)
1381 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1382 if (ht_bin->vaddr[1] == head->vaddr)
1383 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1384 }
1385 }
1386 }
1387 }
1388 }
1389 head=head->next;
1390 }
1391}
1392
8062d65a 1393/* Register allocation */
1394
1395// Note: registers are allocated clean (unmodified state)
1396// if you intend to modify the register, you must call dirty_reg().
1397static void alloc_reg(struct regstat *cur,int i,signed char reg)
1398{
1399 int r,hr;
b7ec323c 1400 int preferred_reg = PREFERRED_REG_FIRST
1401 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1402 if (reg == CCREG) preferred_reg = HOST_CCREG;
1403 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1404 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1405
1406 // Don't allocate unused registers
1407 if((cur->u>>reg)&1) return;
1408
1409 // see if it's already allocated
1410 for(hr=0;hr<HOST_REGS;hr++)
1411 {
1412 if(cur->regmap[hr]==reg) return;
1413 }
1414
1415 // Keep the same mapping if the register was already allocated in a loop
1416 preferred_reg = loop_reg(i,reg,preferred_reg);
1417
1418 // Try to allocate the preferred register
1419 if(cur->regmap[preferred_reg]==-1) {
1420 cur->regmap[preferred_reg]=reg;
1421 cur->dirty&=~(1<<preferred_reg);
1422 cur->isconst&=~(1<<preferred_reg);
1423 return;
1424 }
1425 r=cur->regmap[preferred_reg];
1426 assert(r < 64);
1427 if((cur->u>>r)&1) {
1428 cur->regmap[preferred_reg]=reg;
1429 cur->dirty&=~(1<<preferred_reg);
1430 cur->isconst&=~(1<<preferred_reg);
1431 return;
1432 }
1433
1434 // Clear any unneeded registers
1435 // We try to keep the mapping consistent, if possible, because it
1436 // makes branches easier (especially loops). So we try to allocate
1437 // first (see above) before removing old mappings. If this is not
1438 // possible then go ahead and clear out the registers that are no
1439 // longer needed.
1440 for(hr=0;hr<HOST_REGS;hr++)
1441 {
1442 r=cur->regmap[hr];
1443 if(r>=0) {
1444 assert(r < 64);
1445 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1446 }
1447 }
b7ec323c 1448
8062d65a 1449 // Try to allocate any available register, but prefer
1450 // registers that have not been used recently.
b7ec323c 1451 if (i > 0) {
1452 for (hr = PREFERRED_REG_FIRST; ; ) {
1453 if (cur->regmap[hr] < 0) {
1454 int oldreg = regs[i-1].regmap[hr];
1455 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1456 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1457 {
8062d65a 1458 cur->regmap[hr]=reg;
1459 cur->dirty&=~(1<<hr);
1460 cur->isconst&=~(1<<hr);
1461 return;
1462 }
1463 }
b7ec323c 1464 hr++;
1465 if (hr == EXCLUDE_REG)
1466 hr++;
1467 if (hr == HOST_REGS)
1468 hr = 0;
1469 if (hr == PREFERRED_REG_FIRST)
1470 break;
8062d65a 1471 }
1472 }
b7ec323c 1473
8062d65a 1474 // Try to allocate any available register
b7ec323c 1475 for (hr = PREFERRED_REG_FIRST; ; ) {
1476 if (cur->regmap[hr] < 0) {
8062d65a 1477 cur->regmap[hr]=reg;
1478 cur->dirty&=~(1<<hr);
1479 cur->isconst&=~(1<<hr);
1480 return;
1481 }
b7ec323c 1482 hr++;
1483 if (hr == EXCLUDE_REG)
1484 hr++;
1485 if (hr == HOST_REGS)
1486 hr = 0;
1487 if (hr == PREFERRED_REG_FIRST)
1488 break;
8062d65a 1489 }
1490
1491 // Ok, now we have to evict someone
1492 // Pick a register we hopefully won't need soon
1493 u_char hsn[MAXREG+1];
1494 memset(hsn,10,sizeof(hsn));
1495 int j;
1496 lsn(hsn,i,&preferred_reg);
1497 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1498 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1499 if(i>0) {
1500 // Don't evict the cycle count at entry points, otherwise the entry
1501 // stub will have to write it.
cf95b4f0 1502 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1503 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1504 for(j=10;j>=3;j--)
1505 {
1506 // Alloc preferred register if available
1507 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1508 for(hr=0;hr<HOST_REGS;hr++) {
1509 // Evict both parts of a 64-bit register
9de8a0c3 1510 if(cur->regmap[hr]==r) {
8062d65a 1511 cur->regmap[hr]=-1;
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1514 }
1515 }
1516 cur->regmap[preferred_reg]=reg;
1517 return;
1518 }
1519 for(r=1;r<=MAXREG;r++)
1520 {
cf95b4f0 1521 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1522 for(hr=0;hr<HOST_REGS;hr++) {
1523 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1524 if(cur->regmap[hr]==r) {
1525 cur->regmap[hr]=reg;
1526 cur->dirty&=~(1<<hr);
1527 cur->isconst&=~(1<<hr);
1528 return;
1529 }
1530 }
1531 }
1532 }
1533 }
1534 }
1535 }
1536 for(j=10;j>=0;j--)
1537 {
1538 for(r=1;r<=MAXREG;r++)
1539 {
1540 if(hsn[r]==j) {
8062d65a 1541 for(hr=0;hr<HOST_REGS;hr++) {
1542 if(cur->regmap[hr]==r) {
1543 cur->regmap[hr]=reg;
1544 cur->dirty&=~(1<<hr);
1545 cur->isconst&=~(1<<hr);
1546 return;
1547 }
1548 }
1549 }
1550 }
1551 }
7c3a5182 1552 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1553}
1554
1555// Allocate a temporary register. This is done without regard to
1556// dirty status or whether the register we request is on the unneeded list
1557// Note: This will only allocate one register, even if called multiple times
1558static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1559{
1560 int r,hr;
1561 int preferred_reg = -1;
1562
1563 // see if it's already allocated
1564 for(hr=0;hr<HOST_REGS;hr++)
1565 {
1566 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1567 }
1568
1569 // Try to allocate any available register
1570 for(hr=HOST_REGS-1;hr>=0;hr--) {
1571 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1572 cur->regmap[hr]=reg;
1573 cur->dirty&=~(1<<hr);
1574 cur->isconst&=~(1<<hr);
1575 return;
1576 }
1577 }
1578
1579 // Find an unneeded register
1580 for(hr=HOST_REGS-1;hr>=0;hr--)
1581 {
1582 r=cur->regmap[hr];
1583 if(r>=0) {
1584 assert(r < 64);
1585 if((cur->u>>r)&1) {
1586 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1587 cur->regmap[hr]=reg;
1588 cur->dirty&=~(1<<hr);
1589 cur->isconst&=~(1<<hr);
1590 return;
1591 }
1592 }
1593 }
1594 }
1595
1596 // Ok, now we have to evict someone
1597 // Pick a register we hopefully won't need soon
1598 // TODO: we might want to follow unconditional jumps here
1599 // TODO: get rid of dupe code and make this into a function
1600 u_char hsn[MAXREG+1];
1601 memset(hsn,10,sizeof(hsn));
1602 int j;
1603 lsn(hsn,i,&preferred_reg);
1604 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1605 if(i>0) {
1606 // Don't evict the cycle count at entry points, otherwise the entry
1607 // stub will have to write it.
cf95b4f0 1608 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1609 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1610 for(j=10;j>=3;j--)
1611 {
1612 for(r=1;r<=MAXREG;r++)
1613 {
cf95b4f0 1614 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1615 for(hr=0;hr<HOST_REGS;hr++) {
1616 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1617 if(cur->regmap[hr]==r) {
1618 cur->regmap[hr]=reg;
1619 cur->dirty&=~(1<<hr);
1620 cur->isconst&=~(1<<hr);
1621 return;
1622 }
1623 }
1624 }
1625 }
1626 }
1627 }
1628 }
1629 for(j=10;j>=0;j--)
1630 {
1631 for(r=1;r<=MAXREG;r++)
1632 {
1633 if(hsn[r]==j) {
8062d65a 1634 for(hr=0;hr<HOST_REGS;hr++) {
1635 if(cur->regmap[hr]==r) {
1636 cur->regmap[hr]=reg;
1637 cur->dirty&=~(1<<hr);
1638 cur->isconst&=~(1<<hr);
1639 return;
1640 }
1641 }
1642 }
1643 }
1644 }
7c3a5182 1645 SysPrintf("This shouldn't happen");abort();
8062d65a 1646}
1647
ad49de89 1648static void mov_alloc(struct regstat *current,int i)
57871462 1649{
cf95b4f0 1650 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1651 alloc_cc(current,i); // for stalls
1652 dirty_reg(current,CCREG);
32631e6a 1653 }
1654
57871462 1655 // Note: Don't need to actually alloc the source registers
cf95b4f0 1656 //alloc_reg(current,i,dops[i].rs1);
1657 alloc_reg(current,i,dops[i].rt1);
ad49de89 1658
cf95b4f0 1659 clear_const(current,dops[i].rs1);
1660 clear_const(current,dops[i].rt1);
1661 dirty_reg(current,dops[i].rt1);
57871462 1662}
1663
ad49de89 1664static void shiftimm_alloc(struct regstat *current,int i)
57871462 1665{
cf95b4f0 1666 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1667 {
cf95b4f0 1668 if(dops[i].rt1) {
1669 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1670 else dops[i].lt1=dops[i].rs1;
1671 alloc_reg(current,i,dops[i].rt1);
1672 dirty_reg(current,dops[i].rt1);
1673 if(is_const(current,dops[i].rs1)) {
1674 int v=get_const(current,dops[i].rs1);
1675 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1676 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1677 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1678 }
cf95b4f0 1679 else clear_const(current,dops[i].rt1);
57871462 1680 }
1681 }
dc49e339 1682 else
1683 {
cf95b4f0 1684 clear_const(current,dops[i].rs1);
1685 clear_const(current,dops[i].rt1);
dc49e339 1686 }
1687
cf95b4f0 1688 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1689 {
9c45ca93 1690 assert(0);
57871462 1691 }
cf95b4f0 1692 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1693 {
9c45ca93 1694 assert(0);
57871462 1695 }
cf95b4f0 1696 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1697 {
9c45ca93 1698 assert(0);
57871462 1699 }
cf95b4f0 1700 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1701 {
9c45ca93 1702 assert(0);
57871462 1703 }
1704}
1705
ad49de89 1706static void shift_alloc(struct regstat *current,int i)
57871462 1707{
cf95b4f0 1708 if(dops[i].rt1) {
1709 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1710 {
cf95b4f0 1711 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1712 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1713 alloc_reg(current,i,dops[i].rt1);
1714 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1715 alloc_reg_temp(current,i,-1);
1716 minimum_free_regs[i]=1;
1717 }
57871462 1718 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1719 assert(0);
57871462 1720 }
cf95b4f0 1721 clear_const(current,dops[i].rs1);
1722 clear_const(current,dops[i].rs2);
1723 clear_const(current,dops[i].rt1);
1724 dirty_reg(current,dops[i].rt1);
57871462 1725 }
1726}
1727
ad49de89 1728static void alu_alloc(struct regstat *current,int i)
57871462 1729{
cf95b4f0 1730 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1731 if(dops[i].rt1) {
1732 if(dops[i].rs1&&dops[i].rs2) {
1733 alloc_reg(current,i,dops[i].rs1);
1734 alloc_reg(current,i,dops[i].rs2);
57871462 1735 }
1736 else {
cf95b4f0 1737 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1738 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1739 }
cf95b4f0 1740 alloc_reg(current,i,dops[i].rt1);
57871462 1741 }
57871462 1742 }
cf95b4f0 1743 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1744 if(dops[i].rt1) {
1745 alloc_reg(current,i,dops[i].rs1);
1746 alloc_reg(current,i,dops[i].rs2);
1747 alloc_reg(current,i,dops[i].rt1);
57871462 1748 }
57871462 1749 }
cf95b4f0 1750 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1751 if(dops[i].rt1) {
1752 if(dops[i].rs1&&dops[i].rs2) {
1753 alloc_reg(current,i,dops[i].rs1);
1754 alloc_reg(current,i,dops[i].rs2);
57871462 1755 }
1756 else
1757 {
cf95b4f0 1758 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1759 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1760 }
cf95b4f0 1761 alloc_reg(current,i,dops[i].rt1);
57871462 1762 }
1763 }
cf95b4f0 1764 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1765 assert(0);
57871462 1766 }
cf95b4f0 1767 clear_const(current,dops[i].rs1);
1768 clear_const(current,dops[i].rs2);
1769 clear_const(current,dops[i].rt1);
1770 dirty_reg(current,dops[i].rt1);
57871462 1771}
1772
ad49de89 1773static void imm16_alloc(struct regstat *current,int i)
57871462 1774{
cf95b4f0 1775 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1776 else dops[i].lt1=dops[i].rs1;
1777 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1778 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1779 assert(0);
57871462 1780 }
cf95b4f0 1781 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1782 clear_const(current,dops[i].rs1);
1783 clear_const(current,dops[i].rt1);
57871462 1784 }
cf95b4f0 1785 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1786 if(is_const(current,dops[i].rs1)) {
1787 int v=get_const(current,dops[i].rs1);
1788 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1789 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1790 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1791 }
cf95b4f0 1792 else clear_const(current,dops[i].rt1);
57871462 1793 }
cf95b4f0 1794 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1795 if(is_const(current,dops[i].rs1)) {
1796 int v=get_const(current,dops[i].rs1);
1797 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1798 }
cf95b4f0 1799 else clear_const(current,dops[i].rt1);
57871462 1800 }
1801 else {
cf95b4f0 1802 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1803 }
cf95b4f0 1804 dirty_reg(current,dops[i].rt1);
57871462 1805}
1806
ad49de89 1807static void load_alloc(struct regstat *current,int i)
57871462 1808{
cf95b4f0 1809 clear_const(current,dops[i].rt1);
1810 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1811 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1812 if (needed_again(dops[i].rs1, i))
1813 alloc_reg(current, i, dops[i].rs1);
1814 if (ram_offset)
1815 alloc_reg(current, i, ROREG);
cf95b4f0 1816 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1817 alloc_reg(current,i,dops[i].rt1);
1818 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1819 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1820 {
ad49de89 1821 assert(0);
57871462 1822 }
cf95b4f0 1823 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1824 {
ad49de89 1825 assert(0);
57871462 1826 }
cf95b4f0 1827 dirty_reg(current,dops[i].rt1);
57871462 1828 // LWL/LWR need a temporary register for the old value
cf95b4f0 1829 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1830 {
1831 alloc_reg(current,i,FTEMP);
1832 alloc_reg_temp(current,i,-1);
e1190b87 1833 minimum_free_regs[i]=1;
57871462 1834 }
1835 }
1836 else
1837 {
373d1d07 1838 // Load to r0 or unneeded register (dummy load)
57871462 1839 // but we still need a register to calculate the address
cf95b4f0 1840 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1841 {
1842 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1843 }
57871462 1844 alloc_reg_temp(current,i,-1);
e1190b87 1845 minimum_free_regs[i]=1;
cf95b4f0 1846 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1847 {
ad49de89 1848 assert(0);
535d208a 1849 }
57871462 1850 }
1851}
1852
1853void store_alloc(struct regstat *current,int i)
1854{
cf95b4f0 1855 clear_const(current,dops[i].rs2);
1856 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1857 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1858 alloc_reg(current,i,dops[i].rs2);
1859 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1860 assert(0);
57871462 1861 }
37387d8b 1862 if (ram_offset)
1863 alloc_reg(current, i, ROREG);
57871462 1864 #if defined(HOST_IMM8)
1865 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1866 alloc_reg(current, i, INVCP);
57871462 1867 #endif
cf95b4f0 1868 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1869 alloc_reg(current,i,FTEMP);
1870 }
1871 // We need a temporary register for address generation
1872 alloc_reg_temp(current,i,-1);
e1190b87 1873 minimum_free_regs[i]=1;
57871462 1874}
1875
1876void c1ls_alloc(struct regstat *current,int i)
1877{
cf95b4f0 1878 clear_const(current,dops[i].rt1);
57871462 1879 alloc_reg(current,i,CSREG); // Status
57871462 1880}
1881
b9b61529 1882void c2ls_alloc(struct regstat *current,int i)
1883{
cf95b4f0 1884 clear_const(current,dops[i].rt1);
1885 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1886 alloc_reg(current,i,FTEMP);
37387d8b 1887 if (ram_offset)
1888 alloc_reg(current, i, ROREG);
b9b61529 1889 #if defined(HOST_IMM8)
1890 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1891 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1892 alloc_reg(current,i,INVCP);
1893 #endif
1894 // We need a temporary register for address generation
1895 alloc_reg_temp(current,i,-1);
e1190b87 1896 minimum_free_regs[i]=1;
b9b61529 1897}
1898
57871462 1899#ifndef multdiv_alloc
1900void multdiv_alloc(struct regstat *current,int i)
1901{
1902 // case 0x18: MULT
1903 // case 0x19: MULTU
1904 // case 0x1A: DIV
1905 // case 0x1B: DIVU
1906 // case 0x1C: DMULT
1907 // case 0x1D: DMULTU
1908 // case 0x1E: DDIV
1909 // case 0x1F: DDIVU
cf95b4f0 1910 clear_const(current,dops[i].rs1);
1911 clear_const(current,dops[i].rs2);
32631e6a 1912 alloc_cc(current,i); // for stalls
cf95b4f0 1913 if(dops[i].rs1&&dops[i].rs2)
57871462 1914 {
cf95b4f0 1915 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1916 {
1917 current->u&=~(1LL<<HIREG);
1918 current->u&=~(1LL<<LOREG);
1919 alloc_reg(current,i,HIREG);
1920 alloc_reg(current,i,LOREG);
cf95b4f0 1921 alloc_reg(current,i,dops[i].rs1);
1922 alloc_reg(current,i,dops[i].rs2);
57871462 1923 dirty_reg(current,HIREG);
1924 dirty_reg(current,LOREG);
1925 }
1926 else // 64-bit
1927 {
00fa9369 1928 assert(0);
57871462 1929 }
1930 }
1931 else
1932 {
1933 // Multiply by zero is zero.
1934 // MIPS does not have a divide by zero exception.
1935 // The result is undefined, we return zero.
1936 alloc_reg(current,i,HIREG);
1937 alloc_reg(current,i,LOREG);
57871462 1938 dirty_reg(current,HIREG);
1939 dirty_reg(current,LOREG);
1940 }
1941}
1942#endif
1943
1944void cop0_alloc(struct regstat *current,int i)
1945{
cf95b4f0 1946 if(dops[i].opcode2==0) // MFC0
57871462 1947 {
cf95b4f0 1948 if(dops[i].rt1) {
1949 clear_const(current,dops[i].rt1);
57871462 1950 alloc_all(current,i);
cf95b4f0 1951 alloc_reg(current,i,dops[i].rt1);
1952 dirty_reg(current,dops[i].rt1);
57871462 1953 }
1954 }
cf95b4f0 1955 else if(dops[i].opcode2==4) // MTC0
57871462 1956 {
cf95b4f0 1957 if(dops[i].rs1){
1958 clear_const(current,dops[i].rs1);
1959 alloc_reg(current,i,dops[i].rs1);
57871462 1960 alloc_all(current,i);
1961 }
1962 else {
1963 alloc_all(current,i); // FIXME: Keep r0
1964 current->u&=~1LL;
1965 alloc_reg(current,i,0);
1966 }
1967 }
1968 else
1969 {
1970 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1971 assert(dops[i].opcode2==0x10);
57871462 1972 alloc_all(current,i);
1973 }
e1190b87 1974 minimum_free_regs[i]=HOST_REGS;
57871462 1975}
1976
81dbbf4c 1977static void cop2_alloc(struct regstat *current,int i)
57871462 1978{
cf95b4f0 1979 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1980 {
81dbbf4c 1981 alloc_cc(current,i); // for stalls
1982 dirty_reg(current,CCREG);
cf95b4f0 1983 if(dops[i].rt1){
1984 clear_const(current,dops[i].rt1);
1985 alloc_reg(current,i,dops[i].rt1);
1986 dirty_reg(current,dops[i].rt1);
57871462 1987 }
57871462 1988 }
cf95b4f0 1989 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1990 {
cf95b4f0 1991 if(dops[i].rs1){
1992 clear_const(current,dops[i].rs1);
1993 alloc_reg(current,i,dops[i].rs1);
57871462 1994 }
1995 else {
1996 current->u&=~1LL;
1997 alloc_reg(current,i,0);
57871462 1998 }
1999 }
81dbbf4c 2000 alloc_reg_temp(current,i,-1);
e1190b87 2001 minimum_free_regs[i]=1;
57871462 2002}
00fa9369 2003
b9b61529 2004void c2op_alloc(struct regstat *current,int i)
2005{
81dbbf4c 2006 alloc_cc(current,i); // for stalls
2007 dirty_reg(current,CCREG);
b9b61529 2008 alloc_reg_temp(current,i,-1);
2009}
57871462 2010
2011void syscall_alloc(struct regstat *current,int i)
2012{
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 alloc_all(current,i);
e1190b87 2016 minimum_free_regs[i]=HOST_REGS;
57871462 2017 current->isconst=0;
2018}
2019
2020void delayslot_alloc(struct regstat *current,int i)
2021{
cf95b4f0 2022 switch(dops[i].itype) {
57871462 2023 case UJUMP:
2024 case CJUMP:
2025 case SJUMP:
2026 case RJUMP:
57871462 2027 case SYSCALL:
7139f3c8 2028 case HLECALL:
57871462 2029 case SPAN:
7c3a5182 2030 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2031 SysPrintf("Disabled speculative precompilation\n");
57871462 2032 stop_after_jal=1;
2033 break;
2034 case IMM16:
2035 imm16_alloc(current,i);
2036 break;
2037 case LOAD:
2038 case LOADLR:
2039 load_alloc(current,i);
2040 break;
2041 case STORE:
2042 case STORELR:
2043 store_alloc(current,i);
2044 break;
2045 case ALU:
2046 alu_alloc(current,i);
2047 break;
2048 case SHIFT:
2049 shift_alloc(current,i);
2050 break;
2051 case MULTDIV:
2052 multdiv_alloc(current,i);
2053 break;
2054 case SHIFTIMM:
2055 shiftimm_alloc(current,i);
2056 break;
2057 case MOV:
2058 mov_alloc(current,i);
2059 break;
2060 case COP0:
2061 cop0_alloc(current,i);
2062 break;
2063 case COP1:
81dbbf4c 2064 break;
b9b61529 2065 case COP2:
81dbbf4c 2066 cop2_alloc(current,i);
57871462 2067 break;
2068 case C1LS:
2069 c1ls_alloc(current,i);
2070 break;
b9b61529 2071 case C2LS:
2072 c2ls_alloc(current,i);
2073 break;
b9b61529 2074 case C2OP:
2075 c2op_alloc(current,i);
2076 break;
57871462 2077 }
2078}
2079
2080// Special case where a branch and delay slot span two pages in virtual memory
2081static void pagespan_alloc(struct regstat *current,int i)
2082{
2083 current->isconst=0;
2084 current->wasconst=0;
2085 regs[i].wasconst=0;
e1190b87 2086 minimum_free_regs[i]=HOST_REGS;
57871462 2087 alloc_all(current,i);
2088 alloc_cc(current,i);
2089 dirty_reg(current,CCREG);
cf95b4f0 2090 if(dops[i].opcode==3) // JAL
57871462 2091 {
2092 alloc_reg(current,i,31);
2093 dirty_reg(current,31);
2094 }
cf95b4f0 2095 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2096 {
cf95b4f0 2097 alloc_reg(current,i,dops[i].rs1);
2098 if (dops[i].rt1!=0) {
2099 alloc_reg(current,i,dops[i].rt1);
2100 dirty_reg(current,dops[i].rt1);
57871462 2101 }
2102 }
cf95b4f0 2103 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2104 {
cf95b4f0 2105 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2106 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2107 }
2108 else
cf95b4f0 2109 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2110 {
cf95b4f0 2111 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2112 }
57871462 2113 //else ...
2114}
2115
b14b6a8f 2116static void add_stub(enum stub_type type, void *addr, void *retaddr,
2117 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2118{
d1e4ebd9 2119 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2120 stubs[stubcount].type = type;
2121 stubs[stubcount].addr = addr;
2122 stubs[stubcount].retaddr = retaddr;
2123 stubs[stubcount].a = a;
2124 stubs[stubcount].b = b;
2125 stubs[stubcount].c = c;
2126 stubs[stubcount].d = d;
2127 stubs[stubcount].e = e;
57871462 2128 stubcount++;
2129}
2130
b14b6a8f 2131static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2132 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2133{
2134 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2135}
2136
57871462 2137// Write out a single register
2330734f 2138static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2139{
2140 int hr;
2141 for(hr=0;hr<HOST_REGS;hr++) {
2142 if(hr!=EXCLUDE_REG) {
9de8a0c3 2143 if(regmap[hr]==r) {
57871462 2144 if((dirty>>hr)&1) {
ad49de89 2145 assert(regmap[hr]<64);
2146 emit_storereg(r,hr);
57871462 2147 }
2148 }
2149 }
2150 }
2151}
2152
8062d65a 2153static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2154{
2155 //if(dirty_pre==dirty) return;
2156 int hr,reg;
2157 for(hr=0;hr<HOST_REGS;hr++) {
2158 if(hr!=EXCLUDE_REG) {
2159 reg=pre[hr];
9de8a0c3 2160 if(((~u)>>reg)&1) {
8062d65a 2161 if(reg>0) {
2162 if(((dirty_pre&~dirty)>>hr)&1) {
2163 if(reg>0&&reg<34) {
2164 emit_storereg(reg,hr);
2165 }
2166 else if(reg>=64) {
2167 assert(0);
2168 }
2169 }
2170 }
2171 }
2172 }
2173 }
2174}
2175
687b4580 2176// trashes r2
2177static void pass_args(int a0, int a1)
2178{
2179 if(a0==1&&a1==0) {
2180 // must swap
2181 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2182 }
2183 else if(a0!=0&&a1==0) {
2184 emit_mov(a1,1);
2185 if (a0>=0) emit_mov(a0,0);
2186 }
2187 else {
2188 if(a0>=0&&a0!=0) emit_mov(a0,0);
2189 if(a1>=0&&a1!=1) emit_mov(a1,1);
2190 }
2191}
2192
2330734f 2193static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2194{
cf95b4f0 2195 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2196 if(dops[i].rt1) {
57871462 2197 signed char s1,s2,t;
cf95b4f0 2198 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2199 if(t>=0) {
cf95b4f0 2200 s1=get_reg(i_regs->regmap,dops[i].rs1);
2201 s2=get_reg(i_regs->regmap,dops[i].rs2);
2202 if(dops[i].rs1&&dops[i].rs2) {
57871462 2203 assert(s1>=0);
2204 assert(s2>=0);
cf95b4f0 2205 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2206 else emit_add(s1,s2,t);
2207 }
cf95b4f0 2208 else if(dops[i].rs1) {
57871462 2209 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2210 else emit_loadreg(dops[i].rs1,t);
57871462 2211 }
cf95b4f0 2212 else if(dops[i].rs2) {
57871462 2213 if(s2>=0) {
cf95b4f0 2214 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2215 else emit_mov(s2,t);
2216 }
2217 else {
cf95b4f0 2218 emit_loadreg(dops[i].rs2,t);
2219 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2220 }
2221 }
2222 else emit_zeroreg(t);
2223 }
2224 }
2225 }
cf95b4f0 2226 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2227 assert(0);
57871462 2228 }
cf95b4f0 2229 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2230 if(dops[i].rt1) {
ad49de89 2231 signed char s1l,s2l,t;
57871462 2232 {
cf95b4f0 2233 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2234 //assert(t>=0);
2235 if(t>=0) {
cf95b4f0 2236 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2237 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2238 if(dops[i].rs2==0) // rx<r0
57871462 2239 {
cf95b4f0 2240 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2241 assert(s1l>=0);
57871462 2242 emit_shrimm(s1l,31,t);
06e425d7 2243 }
2244 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2245 emit_zeroreg(t);
2246 }
cf95b4f0 2247 else if(dops[i].rs1==0) // r0<rx
57871462 2248 {
2249 assert(s2l>=0);
cf95b4f0 2250 if(dops[i].opcode2==0x2a) // SLT
57871462 2251 emit_set_gz32(s2l,t);
2252 else // SLTU (set if not zero)
2253 emit_set_nz32(s2l,t);
2254 }
2255 else{
2256 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2257 if(dops[i].opcode2==0x2a) // SLT
57871462 2258 emit_set_if_less32(s1l,s2l,t);
2259 else // SLTU
2260 emit_set_if_carry32(s1l,s2l,t);
2261 }
2262 }
2263 }
2264 }
2265 }
cf95b4f0 2266 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2267 if(dops[i].rt1) {
ad49de89 2268 signed char s1l,s2l,tl;
cf95b4f0 2269 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2270 {
57871462 2271 if(tl>=0) {
cf95b4f0 2272 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2273 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2274 if(dops[i].rs1&&dops[i].rs2) {
57871462 2275 assert(s1l>=0);
2276 assert(s2l>=0);
cf95b4f0 2277 if(dops[i].opcode2==0x24) { // AND
57871462 2278 emit_and(s1l,s2l,tl);
2279 } else
cf95b4f0 2280 if(dops[i].opcode2==0x25) { // OR
57871462 2281 emit_or(s1l,s2l,tl);
2282 } else
cf95b4f0 2283 if(dops[i].opcode2==0x26) { // XOR
57871462 2284 emit_xor(s1l,s2l,tl);
2285 } else
cf95b4f0 2286 if(dops[i].opcode2==0x27) { // NOR
57871462 2287 emit_or(s1l,s2l,tl);
2288 emit_not(tl,tl);
2289 }
2290 }
2291 else
2292 {
cf95b4f0 2293 if(dops[i].opcode2==0x24) { // AND
57871462 2294 emit_zeroreg(tl);
2295 } else
cf95b4f0 2296 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2297 if(dops[i].rs1){
57871462 2298 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2299 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2300 }
2301 else
cf95b4f0 2302 if(dops[i].rs2){
57871462 2303 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2304 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2305 }
2306 else emit_zeroreg(tl);
2307 } else
cf95b4f0 2308 if(dops[i].opcode2==0x27) { // NOR
2309 if(dops[i].rs1){
57871462 2310 if(s1l>=0) emit_not(s1l,tl);
2311 else {
cf95b4f0 2312 emit_loadreg(dops[i].rs1,tl);
57871462 2313 emit_not(tl,tl);
2314 }
2315 }
2316 else
cf95b4f0 2317 if(dops[i].rs2){
57871462 2318 if(s2l>=0) emit_not(s2l,tl);
2319 else {
cf95b4f0 2320 emit_loadreg(dops[i].rs2,tl);
57871462 2321 emit_not(tl,tl);
2322 }
2323 }
2324 else emit_movimm(-1,tl);
2325 }
2326 }
2327 }
2328 }
2329 }
2330 }
2331}
2332
2330734f 2333static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2334{
cf95b4f0 2335 if (dops[i].opcode==0x0f) { // LUI
2336 if(dops[i].rt1) {
57871462 2337 signed char t;
cf95b4f0 2338 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2339 //assert(t>=0);
2340 if(t>=0) {
2341 if(!((i_regs->isconst>>t)&1))
2342 emit_movimm(imm[i]<<16,t);
2343 }
2344 }
2345 }
cf95b4f0 2346 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2347 if(dops[i].rt1) {
57871462 2348 signed char s,t;
cf95b4f0 2349 t=get_reg(i_regs->regmap,dops[i].rt1);
2350 s=get_reg(i_regs->regmap,dops[i].rs1);
2351 if(dops[i].rs1) {
57871462 2352 //assert(t>=0);
2353 //assert(s>=0);
2354 if(t>=0) {
2355 if(!((i_regs->isconst>>t)&1)) {
2356 if(s<0) {
cf95b4f0 2357 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2358 emit_addimm(t,imm[i],t);
2359 }else{
2360 if(!((i_regs->wasconst>>s)&1))
2361 emit_addimm(s,imm[i],t);
2362 else
2363 emit_movimm(constmap[i][s]+imm[i],t);
2364 }
2365 }
2366 }
2367 } else {
2368 if(t>=0) {
2369 if(!((i_regs->isconst>>t)&1))
2370 emit_movimm(imm[i],t);
2371 }
2372 }
2373 }
2374 }
cf95b4f0 2375 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2376 if(dops[i].rt1) {
7c3a5182 2377 signed char sl,tl;
cf95b4f0 2378 tl=get_reg(i_regs->regmap,dops[i].rt1);
2379 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2380 if(tl>=0) {
cf95b4f0 2381 if(dops[i].rs1) {
57871462 2382 assert(sl>=0);
7c3a5182 2383 emit_addimm(sl,imm[i],tl);
57871462 2384 } else {
2385 emit_movimm(imm[i],tl);
57871462 2386 }
2387 }
2388 }
2389 }
cf95b4f0 2390 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2391 if(dops[i].rt1) {
2392 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2393 signed char sl,t;
cf95b4f0 2394 t=get_reg(i_regs->regmap,dops[i].rt1);
2395 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2396 //assert(t>=0);
2397 if(t>=0) {
cf95b4f0 2398 if(dops[i].rs1>0) {
2399 if(dops[i].opcode==0x0a) { // SLTI
57871462 2400 if(sl<0) {
cf95b4f0 2401 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2402 emit_slti32(t,imm[i],t);
2403 }else{
2404 emit_slti32(sl,imm[i],t);
2405 }
2406 }
2407 else { // SLTIU
2408 if(sl<0) {
cf95b4f0 2409 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2410 emit_sltiu32(t,imm[i],t);
2411 }else{
2412 emit_sltiu32(sl,imm[i],t);
2413 }
2414 }
57871462 2415 }else{
2416 // SLTI(U) with r0 is just stupid,
2417 // nonetheless examples can be found
cf95b4f0 2418 if(dops[i].opcode==0x0a) // SLTI
57871462 2419 if(0<imm[i]) emit_movimm(1,t);
2420 else emit_zeroreg(t);
2421 else // SLTIU
2422 {
2423 if(imm[i]) emit_movimm(1,t);
2424 else emit_zeroreg(t);
2425 }
2426 }
2427 }
2428 }
2429 }
cf95b4f0 2430 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2431 if(dops[i].rt1) {
7c3a5182 2432 signed char sl,tl;
cf95b4f0 2433 tl=get_reg(i_regs->regmap,dops[i].rt1);
2434 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2435 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2436 if(dops[i].opcode==0x0c) //ANDI
57871462 2437 {
cf95b4f0 2438 if(dops[i].rs1) {
57871462 2439 if(sl<0) {
cf95b4f0 2440 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2441 emit_andimm(tl,imm[i],tl);
2442 }else{
2443 if(!((i_regs->wasconst>>sl)&1))
2444 emit_andimm(sl,imm[i],tl);
2445 else
2446 emit_movimm(constmap[i][sl]&imm[i],tl);
2447 }
2448 }
2449 else
2450 emit_zeroreg(tl);
57871462 2451 }
2452 else
2453 {
cf95b4f0 2454 if(dops[i].rs1) {
57871462 2455 if(sl<0) {
cf95b4f0 2456 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2457 }
cf95b4f0 2458 if(dops[i].opcode==0x0d) { // ORI
581335b0 2459 if(sl<0) {
2460 emit_orimm(tl,imm[i],tl);
2461 }else{
2462 if(!((i_regs->wasconst>>sl)&1))
2463 emit_orimm(sl,imm[i],tl);
2464 else
2465 emit_movimm(constmap[i][sl]|imm[i],tl);
2466 }
57871462 2467 }
cf95b4f0 2468 if(dops[i].opcode==0x0e) { // XORI
581335b0 2469 if(sl<0) {
2470 emit_xorimm(tl,imm[i],tl);
2471 }else{
2472 if(!((i_regs->wasconst>>sl)&1))
2473 emit_xorimm(sl,imm[i],tl);
2474 else
2475 emit_movimm(constmap[i][sl]^imm[i],tl);
2476 }
57871462 2477 }
2478 }
2479 else {
2480 emit_movimm(imm[i],tl);
57871462 2481 }
2482 }
2483 }
2484 }
2485 }
2486}
2487
2330734f 2488static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2489{
cf95b4f0 2490 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2491 {
cf95b4f0 2492 if(dops[i].rt1) {
57871462 2493 signed char s,t;
cf95b4f0 2494 t=get_reg(i_regs->regmap,dops[i].rt1);
2495 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2496 //assert(t>=0);
dc49e339 2497 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2498 if(dops[i].rs1==0)
57871462 2499 {
2500 emit_zeroreg(t);
2501 }
2502 else
2503 {
cf95b4f0 2504 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2505 if(imm[i]) {
cf95b4f0 2506 if(dops[i].opcode2==0) // SLL
57871462 2507 {
2508 emit_shlimm(s<0?t:s,imm[i],t);
2509 }
cf95b4f0 2510 if(dops[i].opcode2==2) // SRL
57871462 2511 {
2512 emit_shrimm(s<0?t:s,imm[i],t);
2513 }
cf95b4f0 2514 if(dops[i].opcode2==3) // SRA
57871462 2515 {
2516 emit_sarimm(s<0?t:s,imm[i],t);
2517 }
2518 }else{
2519 // Shift by zero
2520 if(s>=0 && s!=t) emit_mov(s,t);
2521 }
2522 }
2523 }
cf95b4f0 2524 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2525 }
2526 }
cf95b4f0 2527 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2528 {
9c45ca93 2529 assert(0);
57871462 2530 }
cf95b4f0 2531 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2532 {
9c45ca93 2533 assert(0);
57871462 2534 }
cf95b4f0 2535 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2536 {
9c45ca93 2537 assert(0);
57871462 2538 }
cf95b4f0 2539 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2540 {
9c45ca93 2541 assert(0);
57871462 2542 }
2543}
2544
2545#ifndef shift_assemble
2330734f 2546static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2547{
3968e69e 2548 signed char s,t,shift;
cf95b4f0 2549 if (dops[i].rt1 == 0)
3968e69e 2550 return;
cf95b4f0 2551 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2552 t = get_reg(i_regs->regmap, dops[i].rt1);
2553 s = get_reg(i_regs->regmap, dops[i].rs1);
2554 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2555 if (t < 0)
2556 return;
2557
cf95b4f0 2558 if(dops[i].rs1==0)
3968e69e 2559 emit_zeroreg(t);
cf95b4f0 2560 else if(dops[i].rs2==0) {
3968e69e 2561 assert(s>=0);
2562 if(s!=t) emit_mov(s,t);
2563 }
2564 else {
2565 host_tempreg_acquire();
2566 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2567 switch(dops[i].opcode2) {
3968e69e 2568 case 4: // SLLV
2569 emit_shl(s,HOST_TEMPREG,t);
2570 break;
2571 case 6: // SRLV
2572 emit_shr(s,HOST_TEMPREG,t);
2573 break;
2574 case 7: // SRAV
2575 emit_sar(s,HOST_TEMPREG,t);
2576 break;
2577 default:
2578 assert(0);
2579 }
2580 host_tempreg_release();
2581 }
57871462 2582}
3968e69e 2583
57871462 2584#endif
2585
8062d65a 2586enum {
2587 MTYPE_8000 = 0,
2588 MTYPE_8020,
2589 MTYPE_0000,
2590 MTYPE_A000,
2591 MTYPE_1F80,
2592};
2593
2594static int get_ptr_mem_type(u_int a)
2595{
2596 if(a < 0x00200000) {
2597 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2598 // return wrong, must use memhandler for BIOS self-test to pass
2599 // 007 does similar stuff from a00 mirror, weird stuff
2600 return MTYPE_8000;
2601 return MTYPE_0000;
2602 }
2603 if(0x1f800000 <= a && a < 0x1f801000)
2604 return MTYPE_1F80;
2605 if(0x80200000 <= a && a < 0x80800000)
2606 return MTYPE_8020;
2607 if(0xa0000000 <= a && a < 0xa0200000)
2608 return MTYPE_A000;
2609 return MTYPE_8000;
2610}
2611
37387d8b 2612static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2613{
2614 int r = get_reg(i_regs->regmap, ROREG);
2615 if (r < 0 && host_tempreg_free) {
2616 host_tempreg_acquire();
2617 emit_loadreg(ROREG, r = HOST_TEMPREG);
2618 }
2619 if (r < 0)
2620 abort();
2621 return r;
2622}
2623
2624static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2625 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2626{
2627 void *jaddr = NULL;
37387d8b 2628 int type = 0;
2629 int mr = dops[i].rs1;
2630 *offset_reg = -1;
8062d65a 2631 if(((smrv_strong|smrv_weak)>>mr)&1) {
2632 type=get_ptr_mem_type(smrv[mr]);
2633 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2634 }
2635 else {
2636 // use the mirror we are running on
2637 type=get_ptr_mem_type(start);
2638 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2639 }
2640
2641 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2642 host_tempreg_acquire();
8062d65a 2643 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2644 addr=*addr_reg_override=HOST_TEMPREG;
2645 type=0;
2646 }
2647 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2648 host_tempreg_acquire();
8062d65a 2649 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2650 addr=*addr_reg_override=HOST_TEMPREG;
2651 type=0;
2652 }
2653 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2654 host_tempreg_acquire();
8062d65a 2655 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2656 addr=*addr_reg_override=HOST_TEMPREG;
2657 type=0;
2658 }
2659 else if(type==MTYPE_1F80) { // scratchpad
2660 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2661 host_tempreg_acquire();
3968e69e 2662 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2663 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2664 host_tempreg_release();
8062d65a 2665 jaddr=out;
2666 emit_jc(0);
2667 }
2668 else {
2669 // do the usual RAM check, jump will go to the right handler
2670 type=0;
2671 }
2672 }
2673
37387d8b 2674 if (type == 0) // need ram check
8062d65a 2675 {
2676 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2677 jaddr = out;
8062d65a 2678 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2679 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2680 if (dops[i].rs1 >= 28)
8062d65a 2681 emit_jno_unlikely(0);
2682 else
2683 #endif
2684 emit_jno(0);
37387d8b 2685 if (ram_offset != 0)
2686 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2687 }
2688
2689 return jaddr;
2690}
2691
687b4580 2692// return memhandler, or get directly accessable address and return 0
2693static void *get_direct_memhandler(void *table, u_int addr,
2694 enum stub_type type, uintptr_t *addr_host)
2695{
c979e8c2 2696 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2697 uintptr_t l1, l2 = 0;
2698 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2699 if (!(l1 & msb)) {
687b4580 2700 uintptr_t v = l1 << 1;
2701 *addr_host = v + addr;
2702 return NULL;
2703 }
2704 else {
2705 l1 <<= 1;
2706 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2707 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2708 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2709 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2710 else
c979e8c2 2711 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2712 if (!(l2 & msb)) {
687b4580 2713 uintptr_t v = l2 << 1;
2714 *addr_host = v + (addr&0xfff);
2715 return NULL;
2716 }
2717 return (void *)(l2 << 1);
2718 }
2719}
2720
81dbbf4c 2721static u_int get_host_reglist(const signed char *regmap)
2722{
2723 u_int reglist = 0, hr;
2724 for (hr = 0; hr < HOST_REGS; hr++) {
2725 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2726 reglist |= 1 << hr;
2727 }
2728 return reglist;
2729}
2730
2731static u_int reglist_exclude(u_int reglist, int r1, int r2)
2732{
2733 if (r1 >= 0)
2734 reglist &= ~(1u << r1);
2735 if (r2 >= 0)
2736 reglist &= ~(1u << r2);
2737 return reglist;
2738}
2739
e3c6bdb5 2740// find a temp caller-saved register not in reglist (so assumed to be free)
2741static int reglist_find_free(u_int reglist)
2742{
2743 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2744 if (free_regs == 0)
2745 return -1;
2746 return __builtin_ctz(free_regs);
2747}
2748
37387d8b 2749static void do_load_word(int a, int rt, int offset_reg)
2750{
2751 if (offset_reg >= 0)
2752 emit_ldr_dualindexed(offset_reg, a, rt);
2753 else
2754 emit_readword_indexed(0, a, rt);
2755}
2756
2757static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2758{
2759 if (offset_reg < 0) {
2760 emit_writeword_indexed(rt, ofs, a);
2761 return;
2762 }
2763 if (ofs != 0)
2764 emit_addimm(a, ofs, a);
2765 emit_str_dualindexed(offset_reg, a, rt);
2766 if (ofs != 0 && preseve_a)
2767 emit_addimm(a, -ofs, a);
2768}
2769
2770static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2771{
2772 if (offset_reg < 0) {
2773 emit_writehword_indexed(rt, ofs, a);
2774 return;
2775 }
2776 if (ofs != 0)
2777 emit_addimm(a, ofs, a);
2778 emit_strh_dualindexed(offset_reg, a, rt);
2779 if (ofs != 0 && preseve_a)
2780 emit_addimm(a, -ofs, a);
2781}
2782
2783static void do_store_byte(int a, int rt, int offset_reg)
2784{
2785 if (offset_reg >= 0)
2786 emit_strb_dualindexed(offset_reg, a, rt);
2787 else
2788 emit_writebyte_indexed(rt, 0, a);
2789}
2790
2330734f 2791static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2792{
7c3a5182 2793 int s,tl,addr;
57871462 2794 int offset;
b14b6a8f 2795 void *jaddr=0;
5bf843dc 2796 int memtarget=0,c=0;
37387d8b 2797 int offset_reg = -1;
2798 int fastio_reg_override = -1;
81dbbf4c 2799 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2800 tl=get_reg(i_regs->regmap,dops[i].rt1);
2801 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2802 offset=imm[i];
57871462 2803 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2804 if(s>=0) {
2805 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2806 if (c) {
2807 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2808 }
57871462 2809 }
57871462 2810 //printf("load_assemble: c=%d\n",c);
643aeae3 2811 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2812 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2813 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2814 ||dops[i].rt1==0) {
5bf843dc 2815 // could be FIFO, must perform the read
f18c0f46 2816 // ||dummy read
5bf843dc 2817 assem_debug("(forced read)\n");
9de8a0c3 2818 tl=get_reg_temp(i_regs->regmap);
5bf843dc 2819 assert(tl>=0);
5bf843dc 2820 }
2821 if(offset||s<0||c) addr=tl;
2822 else addr=s;
9de8a0c3 2823 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
535d208a 2824 if(tl>=0) {
2825 //printf("load_assemble: c=%d\n",c);
643aeae3 2826 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2827 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2828 reglist&=~(1<<tl);
1edfcc68 2829 if(!c) {
1edfcc68 2830 #ifdef R29_HACK
2831 // Strmnnrmn's speed hack
cf95b4f0 2832 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2833 #endif
2834 {
37387d8b 2835 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2836 &offset_reg, &fastio_reg_override);
535d208a 2837 }
1edfcc68 2838 }
37387d8b 2839 else if (ram_offset && memtarget) {
2840 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2841 }
cf95b4f0 2842 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2843 switch (dops[i].opcode) {
2844 case 0x20: // LB
535d208a 2845 if(!c||memtarget) {
2846 if(!dummy) {
37387d8b 2847 int a = tl;
2848 if (!c) a = addr;
2849 if (fastio_reg_override >= 0)
2850 a = fastio_reg_override;
b1570849 2851
37387d8b 2852 if (offset_reg >= 0)
2853 emit_ldrsb_dualindexed(offset_reg, a, tl);
2854 else
2855 emit_movsbl_indexed(0, a, tl);
57871462 2856 }
535d208a 2857 if(jaddr)
2330734f 2858 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2859 }
535d208a 2860 else
2330734f 2861 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2862 break;
2863 case 0x21: // LH
535d208a 2864 if(!c||memtarget) {
2865 if(!dummy) {
37387d8b 2866 int a = tl;
2867 if (!c) a = addr;
2868 if (fastio_reg_override >= 0)
2869 a = fastio_reg_override;
2870 if (offset_reg >= 0)
2871 emit_ldrsh_dualindexed(offset_reg, a, tl);
2872 else
2873 emit_movswl_indexed(0, a, tl);
57871462 2874 }
535d208a 2875 if(jaddr)
2330734f 2876 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2877 }
535d208a 2878 else
2330734f 2879 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2880 break;
2881 case 0x23: // LW
535d208a 2882 if(!c||memtarget) {
2883 if(!dummy) {
37387d8b 2884 int a = addr;
2885 if (fastio_reg_override >= 0)
2886 a = fastio_reg_override;
2887 do_load_word(a, tl, offset_reg);
57871462 2888 }
535d208a 2889 if(jaddr)
2330734f 2890 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2891 }
535d208a 2892 else
2330734f 2893 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2894 break;
2895 case 0x24: // LBU
535d208a 2896 if(!c||memtarget) {
2897 if(!dummy) {
37387d8b 2898 int a = tl;
2899 if (!c) a = addr;
2900 if (fastio_reg_override >= 0)
2901 a = fastio_reg_override;
b1570849 2902
37387d8b 2903 if (offset_reg >= 0)
2904 emit_ldrb_dualindexed(offset_reg, a, tl);
2905 else
2906 emit_movzbl_indexed(0, a, tl);
57871462 2907 }
535d208a 2908 if(jaddr)
2330734f 2909 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2910 }
535d208a 2911 else
2330734f 2912 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2913 break;
2914 case 0x25: // LHU
535d208a 2915 if(!c||memtarget) {
2916 if(!dummy) {
37387d8b 2917 int a = tl;
2918 if(!c) a = addr;
2919 if (fastio_reg_override >= 0)
2920 a = fastio_reg_override;
2921 if (offset_reg >= 0)
2922 emit_ldrh_dualindexed(offset_reg, a, tl);
2923 else
2924 emit_movzwl_indexed(0, a, tl);
57871462 2925 }
535d208a 2926 if(jaddr)
2330734f 2927 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2928 }
535d208a 2929 else
2330734f 2930 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2931 break;
2932 case 0x27: // LWU
2933 case 0x37: // LD
2934 default:
9c45ca93 2935 assert(0);
57871462 2936 }
535d208a 2937 }
37387d8b 2938 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2939 host_tempreg_release();
57871462 2940}
2941
2942#ifndef loadlr_assemble
2330734f 2943static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2944{
3968e69e 2945 int s,tl,temp,temp2,addr;
2946 int offset;
2947 void *jaddr=0;
2948 int memtarget=0,c=0;
37387d8b 2949 int offset_reg = -1;
2950 int fastio_reg_override = -1;
81dbbf4c 2951 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2952 tl=get_reg(i_regs->regmap,dops[i].rt1);
2953 s=get_reg(i_regs->regmap,dops[i].rs1);
9de8a0c3 2954 temp=get_reg_temp(i_regs->regmap);
3968e69e 2955 temp2=get_reg(i_regs->regmap,FTEMP);
2956 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2957 assert(addr<0);
2958 offset=imm[i];
3968e69e 2959 reglist|=1<<temp;
2960 if(offset||s<0||c) addr=temp2;
2961 else addr=s;
2962 if(s>=0) {
2963 c=(i_regs->wasconst>>s)&1;
2964 if(c) {
2965 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2966 }
2967 }
2968 if(!c) {
2969 emit_shlimm(addr,3,temp);
cf95b4f0 2970 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2971 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2972 }else{
2973 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2974 }
37387d8b 2975 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2976 &offset_reg, &fastio_reg_override);
3968e69e 2977 }
2978 else {
37387d8b 2979 if (ram_offset && memtarget) {
2980 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2981 }
cf95b4f0 2982 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2983 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2984 }else{
2985 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2986 }
2987 }
cf95b4f0 2988 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2989 if(!c||memtarget) {
37387d8b 2990 int a = temp2;
2991 if (fastio_reg_override >= 0)
2992 a = fastio_reg_override;
2993 do_load_word(a, temp2, offset_reg);
2994 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2995 host_tempreg_release();
2330734f 2996 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2997 }
2998 else
2330734f 2999 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 3000 if(dops[i].rt1) {
3968e69e 3001 assert(tl>=0);
3002 emit_andimm(temp,24,temp);
cf95b4f0 3003 if (dops[i].opcode==0x22) // LWL
3968e69e 3004 emit_xorimm(temp,24,temp);
3005 host_tempreg_acquire();
3006 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 3007 if (dops[i].opcode==0x26) {
3968e69e 3008 emit_shr(temp2,temp,temp2);
3009 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3010 }else{
3011 emit_shl(temp2,temp,temp2);
3012 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3013 }
3014 host_tempreg_release();
3015 emit_or(temp2,tl,tl);
3016 }
cf95b4f0 3017 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 3018 }
cf95b4f0 3019 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 3020 assert(0);
3021 }
57871462 3022}
3023#endif
3024
2330734f 3025static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3026{
9c45ca93 3027 int s,tl;
57871462 3028 int addr,temp;
3029 int offset;
b14b6a8f 3030 void *jaddr=0;
37387d8b 3031 enum stub_type type=0;
666a299d 3032 int memtarget=0,c=0;
57871462 3033 int agr=AGEN1+(i&1);
37387d8b 3034 int offset_reg = -1;
3035 int fastio_reg_override = -1;
81dbbf4c 3036 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3037 tl=get_reg(i_regs->regmap,dops[i].rs2);
3038 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3039 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3040 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3041 offset=imm[i];
3042 if(s>=0) {
3043 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3044 if(c) {
3045 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3046 }
57871462 3047 }
3048 assert(tl>=0);
3049 assert(temp>=0);
57871462 3050 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3051 if(offset||s<0||c) addr=temp;
3052 else addr=s;
37387d8b 3053 if (!c) {
3054 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3055 &offset_reg, &fastio_reg_override);
1edfcc68 3056 }
37387d8b 3057 else if (ram_offset && memtarget) {
3058 offset_reg = get_ro_reg(i_regs, 0);
57871462 3059 }
3060
37387d8b 3061 switch (dops[i].opcode) {
3062 case 0x28: // SB
57871462 3063 if(!c||memtarget) {
37387d8b 3064 int a = temp;
3065 if (!c) a = addr;
3066 if (fastio_reg_override >= 0)
3067 a = fastio_reg_override;
3068 do_store_byte(a, tl, offset_reg);
3069 }
3070 type = STOREB_STUB;
3071 break;
3072 case 0x29: // SH
57871462 3073 if(!c||memtarget) {
37387d8b 3074 int a = temp;
3075 if (!c) a = addr;
3076 if (fastio_reg_override >= 0)
3077 a = fastio_reg_override;
3078 do_store_hword(a, 0, tl, offset_reg, 1);
3079 }
3080 type = STOREH_STUB;
3081 break;
3082 case 0x2B: // SW
dadf55f2 3083 if(!c||memtarget) {
37387d8b 3084 int a = addr;
3085 if (fastio_reg_override >= 0)
3086 a = fastio_reg_override;
3087 do_store_word(a, 0, tl, offset_reg, 1);
3088 }
3089 type = STOREW_STUB;
3090 break;
3091 case 0x3F: // SD
3092 default:
9c45ca93 3093 assert(0);
57871462 3094 }
37387d8b 3095 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3096 host_tempreg_release();
b96d3df7 3097 if(jaddr) {
3098 // PCSX store handlers don't check invcode again
3099 reglist|=1<<addr;
2330734f 3100 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3101 jaddr=0;
3102 }
cf95b4f0 3103 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3104 if(!c||memtarget) {
3105 #ifdef DESTRUCTIVE_SHIFT
3106 // The x86 shift operation is 'destructive'; it overwrites the
3107 // source register, so we need to make a copy first and use that.
3108 addr=temp;
3109 #endif
3110 #if defined(HOST_IMM8)
3111 int ir=get_reg(i_regs->regmap,INVCP);
3112 assert(ir>=0);
3113 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3114 #else
643aeae3 3115 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3116 #endif
0bbd1454 3117 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3118 emit_callne(invalidate_addr_reg[addr]);
3119 #else
b14b6a8f 3120 void *jaddr2 = out;
57871462 3121 emit_jne(0);
b14b6a8f 3122 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3123 #endif
57871462 3124 }
3125 }
7a518516 3126 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3127 if(jaddr) {
2330734f 3128 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3129 } else if(c&&!memtarget) {
2330734f 3130 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3131 }
3132 // basic current block modification detection..
3133 // not looking back as that should be in mips cache already
3968e69e 3134 // (see Spyro2 title->attract mode)
7a518516 3135 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3136 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3137 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3138 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3139 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3140 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3141 emit_movimm(start+i*4+4,0);
643aeae3 3142 emit_writeword(0,&pcaddr);
d1e4ebd9 3143 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3144 emit_far_call(get_addr_ht);
d1e4ebd9 3145 emit_jmpreg(0);
7a518516 3146 }
3eaa7048 3147 }
57871462 3148}
3149
2330734f 3150static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3151{
9c45ca93 3152 int s,tl;
57871462 3153 int temp;
57871462 3154 int offset;
b14b6a8f 3155 void *jaddr=0;
37387d8b 3156 void *case1, *case23, *case3;
df4dc2b1 3157 void *done0, *done1, *done2;
af4ee1fe 3158 int memtarget=0,c=0;
fab5d06d 3159 int agr=AGEN1+(i&1);
37387d8b 3160 int offset_reg = -1;
81dbbf4c 3161 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3162 tl=get_reg(i_regs->regmap,dops[i].rs2);
3163 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3164 temp=get_reg(i_regs->regmap,agr);
9de8a0c3 3165 if(temp<0) temp=get_reg_temp(i_regs->regmap);
57871462 3166 offset=imm[i];
3167 if(s>=0) {
3168 c=(i_regs->isconst>>s)&1;
af4ee1fe 3169 if(c) {
3170 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3171 }
57871462 3172 }
3173 assert(tl>=0);
535d208a 3174 assert(temp>=0);
1edfcc68 3175 if(!c) {
3176 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3177 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3178 jaddr=out;
1edfcc68 3179 emit_jno(0);
3180 }
3181 else
3182 {
cf95b4f0 3183 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3184 jaddr=out;
535d208a 3185 emit_jmp(0);
57871462 3186 }
535d208a 3187 }
37387d8b 3188 if (ram_offset)
3189 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3190
cf95b4f0 3191 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3192 assert(0);
535d208a 3193 }
57871462 3194
535d208a 3195 emit_testimm(temp,2);
37387d8b 3196 case23=out;
535d208a 3197 emit_jne(0);
3198 emit_testimm(temp,1);
df4dc2b1 3199 case1=out;
535d208a 3200 emit_jne(0);
3201 // 0
37387d8b 3202 if (dops[i].opcode == 0x2A) { // SWL
3203 // Write msb into least significant byte
3204 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3205 do_store_byte(temp, tl, offset_reg);
3206 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3207 }
37387d8b 3208 else if (dops[i].opcode == 0x2E) { // SWR
3209 // Write entire word
3210 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3211 }
37387d8b 3212 done0 = out;
535d208a 3213 emit_jmp(0);
3214 // 1
df4dc2b1 3215 set_jump_target(case1, out);
37387d8b 3216 if (dops[i].opcode == 0x2A) { // SWL
3217 // Write two msb into two least significant bytes
3218 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3219 do_store_hword(temp, -1, tl, offset_reg, 0);
3220 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3221 }
37387d8b 3222 else if (dops[i].opcode == 0x2E) { // SWR
3223 // Write 3 lsb into three most significant bytes
3224 do_store_byte(temp, tl, offset_reg);
3225 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3226 do_store_hword(temp, 1, tl, offset_reg, 0);
3227 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3228 }
df4dc2b1 3229 done1=out;
535d208a 3230 emit_jmp(0);
37387d8b 3231 // 2,3
3232 set_jump_target(case23, out);
535d208a 3233 emit_testimm(temp,1);
37387d8b 3234 case3 = out;
535d208a 3235 emit_jne(0);
37387d8b 3236 // 2
cf95b4f0 3237 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3238 // Write 3 msb into three least significant bytes
3239 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3240 do_store_hword(temp, -2, tl, offset_reg, 1);
3241 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3242 do_store_byte(temp, tl, offset_reg);
3243 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3244 }
37387d8b 3245 else if (dops[i].opcode == 0x2E) { // SWR
3246 // Write two lsb into two most significant bytes
3247 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3248 }
37387d8b 3249 done2 = out;
535d208a 3250 emit_jmp(0);
3251 // 3
df4dc2b1 3252 set_jump_target(case3, out);
37387d8b 3253 if (dops[i].opcode == 0x2A) { // SWL
3254 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3255 }
37387d8b 3256 else if (dops[i].opcode == 0x2E) { // SWR
3257 do_store_byte(temp, tl, offset_reg);
535d208a 3258 }
df4dc2b1 3259 set_jump_target(done0, out);
3260 set_jump_target(done1, out);
3261 set_jump_target(done2, out);
37387d8b 3262 if (offset_reg == HOST_TEMPREG)
3263 host_tempreg_release();
535d208a 3264 if(!c||!memtarget)
2330734f 3265 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3266 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3267 #if defined(HOST_IMM8)
3268 int ir=get_reg(i_regs->regmap,INVCP);
3269 assert(ir>=0);
3270 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3271 #else
643aeae3 3272 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3273 #endif
535d208a 3274 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3275 emit_callne(invalidate_addr_reg[temp]);
3276 #else
b14b6a8f 3277 void *jaddr2 = out;
57871462 3278 emit_jne(0);
b14b6a8f 3279 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3280 #endif
57871462 3281 }
57871462 3282}
3283
2330734f 3284static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3285{
cf95b4f0 3286 if(dops[i].opcode2==0) // MFC0
8062d65a 3287 {
cf95b4f0 3288 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3289 u_int copr=(source[i]>>11)&0x1f;
3290 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3291 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3292 emit_readword(&reg_cop0[copr],t);
3293 }
3294 }
cf95b4f0 3295 else if(dops[i].opcode2==4) // MTC0
8062d65a 3296 {
cf95b4f0 3297 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3298 char copr=(source[i]>>11)&0x1f;
3299 assert(s>=0);
cf95b4f0 3300 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3301 if(copr==9||copr==11||copr==12||copr==13) {
3302 emit_readword(&last_count,HOST_TEMPREG);
3303 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3304 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3305 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3306 emit_writeword(HOST_CCREG,&Count);
3307 }
3308 // What a mess. The status register (12) can enable interrupts,
3309 // so needs a special case to handle a pending interrupt.
3310 // The interrupt must be taken immediately, because a subsequent
3311 // instruction might disable interrupts again.
3312 if(copr==12||copr==13) {
3313 if (is_delayslot) {
3314 // burn cycles to cause cc_interrupt, which will
3315 // reschedule next_interupt. Relies on CCREG from above.
3316 assem_debug("MTC0 DS %d\n", copr);
3317 emit_writeword(HOST_CCREG,&last_count);
3318 emit_movimm(0,HOST_CCREG);
3319 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3320 emit_loadreg(dops[i].rs1,1);
8062d65a 3321 emit_movimm(copr,0);
2a014d73 3322 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3323 emit_loadreg(dops[i].rs1,s);
8062d65a 3324 return;
3325 }
3326 emit_movimm(start+i*4+4,HOST_TEMPREG);
3327 emit_writeword(HOST_TEMPREG,&pcaddr);
3328 emit_movimm(0,HOST_TEMPREG);
3329 emit_writeword(HOST_TEMPREG,&pending_exception);
3330 }
8062d65a 3331 if(s==HOST_CCREG)
cf95b4f0 3332 emit_loadreg(dops[i].rs1,1);
8062d65a 3333 else if(s!=1)
3334 emit_mov(s,1);
3335 emit_movimm(copr,0);
2a014d73 3336 emit_far_call(pcsx_mtc0);
8062d65a 3337 if(copr==9||copr==11||copr==12||copr==13) {
3338 emit_readword(&Count,HOST_CCREG);
3339 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3340 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3341 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3342 emit_writeword(HOST_TEMPREG,&last_count);
3343 emit_storereg(CCREG,HOST_CCREG);
3344 }
3345 if(copr==12||copr==13) {
3346 assert(!is_delayslot);
3347 emit_readword(&pending_exception,14);
3348 emit_test(14,14);
d1e4ebd9 3349 void *jaddr = out;
3350 emit_jeq(0);
3351 emit_readword(&pcaddr, 0);
3352 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3353 emit_far_call(get_addr_ht);
d1e4ebd9 3354 emit_jmpreg(0);
3355 set_jump_target(jaddr, out);
8062d65a 3356 }
cf95b4f0 3357 emit_loadreg(dops[i].rs1,s);
8062d65a 3358 }
3359 else
3360 {
cf95b4f0 3361 assert(dops[i].opcode2==0x10);
8062d65a 3362 //if((source[i]&0x3f)==0x10) // RFE
3363 {
3364 emit_readword(&Status,0);
3365 emit_andimm(0,0x3c,1);
3366 emit_andimm(0,~0xf,0);
3367 emit_orrshr_imm(1,2,0);
3368 emit_writeword(0,&Status);
3369 }
3370 }
3371}
3372
2330734f 3373static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3374{
3375 // XXX: should just just do the exception instead
3376 //if(!cop1_usable)
3377 {
3378 void *jaddr=out;
3379 emit_jmp(0);
3380 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3381 }
3382}
3383
2330734f 3384static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3385{
3386 cop1_unusable(i, i_regs);
3387}
3388
2330734f 3389static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3390{
3d624f89 3391 cop1_unusable(i, i_regs);
57871462 3392}
3393
8062d65a 3394// FP_STUB
3395static void do_cop1stub(int n)
3396{
3397 literal_pool(256);
3398 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3399 set_jump_target(stubs[n].addr, out);
3400 int i=stubs[n].a;
3401// int rs=stubs[n].b;
3402 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3403 int ds=stubs[n].d;
3404 if(!ds) {
3405 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3406 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3407 }
3408 //else {printf("fp exception in delay slot\n");}
3409 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3410 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3411 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3412 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3413 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3414}
3415
e3c6bdb5 3416static int cop2_is_stalling_op(int i, int *cycles)
3417{
cf95b4f0 3418 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3419 *cycles = 0;
3420 return 1;
3421 }
cf95b4f0 3422 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3423 *cycles = 0;
3424 return 1;
3425 }
cf95b4f0 3426 if (dops[i].itype == C2OP) {
e3c6bdb5 3427 *cycles = gte_cycletab[source[i] & 0x3f];
3428 return 1;
3429 }
3430 // ... what about MTC2/CTC2/LWC2?
3431 return 0;
3432}
3433
3434#if 0
3435static void log_gte_stall(int stall, u_int cycle)
3436{
3437 if ((u_int)stall <= 44)
3438 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3439}
3440
3441static void emit_log_gte_stall(int i, int stall, u_int reglist)
3442{
3443 save_regs(reglist);
3444 if (stall > 0)
3445 emit_movimm(stall, 0);
3446 else
3447 emit_mov(HOST_TEMPREG, 0);
2330734f 3448 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3449 emit_far_call(log_gte_stall);
3450 restore_regs(reglist);
3451}
3452#endif
3453
32631e6a 3454static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3455{
e3c6bdb5 3456 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3457 int rtmp = reglist_find_free(reglist);
3458
32631e6a 3459 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3460 return;
81dbbf4c 3461 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3462 // happens occasionally... cc evicted? Don't bother then
3463 //printf("no cc %08x\n", start + i*4);
3464 return;
3465 }
cf95b4f0 3466 if (!dops[i].bt) {
e3c6bdb5 3467 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3468 //if (dops[j].is_ds) break;
3469 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3470 break;
2330734f 3471 if (j > 0 && ccadj[j - 1] > ccadj[j])
3472 break;
e3c6bdb5 3473 }
32631e6a 3474 j = max(j, 0);
e3c6bdb5 3475 }
2330734f 3476 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3477 if (other_gte_op_cycles >= 0)
3478 stall = other_gte_op_cycles - cycles_passed;
3479 else if (cycles_passed >= 44)
3480 stall = 0; // can't stall
3481 if (stall == -MAXBLOCK && rtmp >= 0) {
3482 // unknown stall, do the expensive runtime check
32631e6a 3483 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3484#if 0 // too slow
3485 save_regs(reglist);
3486 emit_movimm(gte_cycletab[op], 0);
2330734f 3487 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3488 emit_far_call(call_gteStall);
3489 restore_regs(reglist);
3490#else
3491 host_tempreg_acquire();
3492 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3493 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3494 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3495 emit_cmpimm(HOST_TEMPREG, 44);
3496 emit_cmovb_reg(rtmp, HOST_CCREG);
3497 //emit_log_gte_stall(i, 0, reglist);
3498 host_tempreg_release();
3499#endif
3500 }
3501 else if (stall > 0) {
3502 //emit_log_gte_stall(i, stall, reglist);
3503 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3504 }
3505
3506 // save gteBusyCycle, if needed
3507 if (gte_cycletab[op] == 0)
3508 return;
3509 other_gte_op_cycles = -1;
3510 for (j = i + 1; j < slen; j++) {
3511 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3512 break;
fe807a8a 3513 if (dops[j].is_jump) {
e3c6bdb5 3514 // check ds
3515 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3516 j++;
3517 break;
3518 }
3519 }
3520 if (other_gte_op_cycles >= 0)
3521 // will handle stall when assembling that op
3522 return;
2330734f 3523 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3524 if (cycles_passed >= 44)
3525 return;
3526 assem_debug("; save gteBusyCycle\n");
3527 host_tempreg_acquire();
3528#if 0
3529 emit_readword(&last_count, HOST_TEMPREG);
3530 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3531 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3532 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3533 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3534#else
2330734f 3535 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3536 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3537#endif
3538 host_tempreg_release();
81dbbf4c 3539}
3540
32631e6a 3541static int is_mflohi(int i)
3542{
cf95b4f0 3543 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3544}
3545
3546static int check_multdiv(int i, int *cycles)
3547{
cf95b4f0 3548 if (dops[i].itype != MULTDIV)
32631e6a 3549 return 0;
cf95b4f0 3550 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3551 *cycles = 11; // approx from 7 11 14
3552 else
3553 *cycles = 37;
3554 return 1;
3555}
3556
2330734f 3557static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3558{
3559 int j, found = 0, c = 0;
3560 if (HACK_ENABLED(NDHACK_NO_STALLS))
3561 return;
3562 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3563 // happens occasionally... cc evicted? Don't bother then
3564 return;
3565 }
3566 for (j = i + 1; j < slen; j++) {
cf95b4f0 3567 if (dops[j].bt)
32631e6a 3568 break;
3569 if ((found = is_mflohi(j)))
3570 break;
fe807a8a 3571 if (dops[j].is_jump) {
32631e6a 3572 // check ds
3573 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3574 j++;
3575 break;
3576 }
3577 }
3578 if (found)
3579 // handle all in multdiv_do_stall()
3580 return;
3581 check_multdiv(i, &c);
3582 assert(c > 0);
3583 assem_debug("; muldiv prepare stall %d\n", c);
3584 host_tempreg_acquire();
2330734f 3585 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3586 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3587 host_tempreg_release();
3588}
3589
3590static void multdiv_do_stall(int i, const struct regstat *i_regs)
3591{
3592 int j, known_cycles = 0;
3593 u_int reglist = get_host_reglist(i_regs->regmap);
9de8a0c3 3594 int rtmp = get_reg_temp(i_regs->regmap);
32631e6a 3595 if (rtmp < 0)
3596 rtmp = reglist_find_free(reglist);
3597 if (HACK_ENABLED(NDHACK_NO_STALLS))
3598 return;
3599 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3600 // happens occasionally... cc evicted? Don't bother then
3601 //printf("no cc/rtmp %08x\n", start + i*4);
3602 return;
3603 }
cf95b4f0 3604 if (!dops[i].bt) {
32631e6a 3605 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3606 if (dops[j].is_ds) break;
2330734f 3607 if (check_multdiv(j, &known_cycles))
32631e6a 3608 break;
3609 if (is_mflohi(j))
3610 // already handled by this op
3611 return;
2330734f 3612 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3613 break;
32631e6a 3614 }
3615 j = max(j, 0);
3616 }
3617 if (known_cycles > 0) {
2330734f 3618 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3619 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3620 if (known_cycles > 0)
3621 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3622 return;
3623 }
3624 assem_debug("; muldiv stall unresolved\n");
3625 host_tempreg_acquire();
3626 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3627 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3628 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3629 emit_cmpimm(HOST_TEMPREG, 37);
3630 emit_cmovb_reg(rtmp, HOST_CCREG);
3631 //emit_log_gte_stall(i, 0, reglist);
3632 host_tempreg_release();
3633}
3634
8062d65a 3635static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3636{
3637 switch (copr) {
3638 case 1:
3639 case 3:
3640 case 5:
3641 case 8:
3642 case 9:
3643 case 10:
3644 case 11:
3645 emit_readword(&reg_cop2d[copr],tl);
3646 emit_signextend16(tl,tl);
3647 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3648 break;
3649 case 7:
3650 case 16:
3651 case 17:
3652 case 18:
3653 case 19:
3654 emit_readword(&reg_cop2d[copr],tl);
3655 emit_andimm(tl,0xffff,tl);
3656 emit_writeword(tl,&reg_cop2d[copr]);
3657 break;
3658 case 15:
3659 emit_readword(&reg_cop2d[14],tl); // SXY2
3660 emit_writeword(tl,&reg_cop2d[copr]);
3661 break;
3662 case 28:
3663 case 29:
3968e69e 3664 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3665 break;
3666 default:
3667 emit_readword(&reg_cop2d[copr],tl);
3668 break;
3669 }
3670}
3671
3672static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3673{
3674 switch (copr) {
3675 case 15:
3676 emit_readword(&reg_cop2d[13],temp); // SXY1
3677 emit_writeword(sl,&reg_cop2d[copr]);
3678 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3679 emit_readword(&reg_cop2d[14],temp); // SXY2
3680 emit_writeword(sl,&reg_cop2d[14]);
3681 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3682 break;
3683 case 28:
3684 emit_andimm(sl,0x001f,temp);
3685 emit_shlimm(temp,7,temp);
3686 emit_writeword(temp,&reg_cop2d[9]);
3687 emit_andimm(sl,0x03e0,temp);
3688 emit_shlimm(temp,2,temp);
3689 emit_writeword(temp,&reg_cop2d[10]);
3690 emit_andimm(sl,0x7c00,temp);
3691 emit_shrimm(temp,3,temp);
3692 emit_writeword(temp,&reg_cop2d[11]);
3693 emit_writeword(sl,&reg_cop2d[28]);
3694 break;
3695 case 30:
3968e69e 3696 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3697#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3698 emit_clz(temp,temp);
3699#else
3700 emit_movs(temp,HOST_TEMPREG);
3701 emit_movimm(0,temp);
3702 emit_jeq((int)out+4*4);
3703 emit_addpl_imm(temp,1,temp);
3704 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3705 emit_jns((int)out-2*4);
3706#endif
3707 emit_writeword(sl,&reg_cop2d[30]);
3708 emit_writeword(temp,&reg_cop2d[31]);
3709 break;
3710 case 31:
3711 break;
3712 default:
3713 emit_writeword(sl,&reg_cop2d[copr]);
3714 break;
3715 }
3716}
3717
2330734f 3718static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3719{
3720 int s,tl;
3721 int ar;
3722 int offset;
1fd1aceb 3723 int memtarget=0,c=0;
b14b6a8f 3724 void *jaddr2=NULL;
3725 enum stub_type type;
b9b61529 3726 int agr=AGEN1+(i&1);
37387d8b 3727 int offset_reg = -1;
3728 int fastio_reg_override = -1;
81dbbf4c 3729 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3730 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3731 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3732 tl=get_reg(i_regs->regmap,FTEMP);
3733 offset=imm[i];
cf95b4f0 3734 assert(dops[i].rs1>0);
b9b61529 3735 assert(tl>=0);
b9b61529 3736
b9b61529 3737 if(i_regs->regmap[HOST_CCREG]==CCREG)
3738 reglist&=~(1<<HOST_CCREG);
3739
3740 // get the address
cf95b4f0 3741 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3742 ar=get_reg(i_regs->regmap,agr);
9de8a0c3 3743 if(ar<0) ar=get_reg_temp(i_regs->regmap);
b9b61529 3744 reglist|=1<<ar;
3745 } else { // LWC2
3746 ar=tl;
3747 }
1fd1aceb 3748 if(s>=0) c=(i_regs->wasconst>>s)&1;
3749 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3750 if (!offset&&!c&&s>=0) ar=s;
3751 assert(ar>=0);
3752
32631e6a 3753 cop2_do_stall_check(0, i, i_regs, reglist);
3754
cf95b4f0 3755 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3756 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3757 type=STOREW_STUB;
b9b61529 3758 }
1fd1aceb 3759 else
b9b61529 3760 type=LOADW_STUB;
1fd1aceb 3761
3762 if(c&&!memtarget) {
b14b6a8f 3763 jaddr2=out;
1fd1aceb 3764 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3765 }
1fd1aceb 3766 else {
3767 if(!c) {
37387d8b 3768 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3769 &offset_reg, &fastio_reg_override);
3770 }
3771 else if (ram_offset && memtarget) {
3772 offset_reg = get_ro_reg(i_regs, 0);
3773 }
3774 switch (dops[i].opcode) {
3775 case 0x32: { // LWC2
3776 int a = ar;
3777 if (fastio_reg_override >= 0)
3778 a = fastio_reg_override;
3779 do_load_word(a, tl, offset_reg);
3780 break;
1fd1aceb 3781 }
37387d8b 3782 case 0x3a: { // SWC2
1fd1aceb 3783 #ifdef DESTRUCTIVE_SHIFT
3784 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3785 #endif
37387d8b 3786 int a = ar;
3787 if (fastio_reg_override >= 0)
3788 a = fastio_reg_override;
3789 do_store_word(a, 0, tl, offset_reg, 1);
3790 break;
3791 }
3792 default:
3793 assert(0);
1fd1aceb 3794 }
b9b61529 3795 }
37387d8b 3796 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3797 host_tempreg_release();
b9b61529 3798 if(jaddr2)
2330734f 3799 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3800 if(dops[i].opcode==0x3a) // SWC2
3801 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3802#if defined(HOST_IMM8)
3803 int ir=get_reg(i_regs->regmap,INVCP);
3804 assert(ir>=0);
3805 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3806#else
643aeae3 3807 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3808#endif
0bbd1454 3809 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3810 emit_callne(invalidate_addr_reg[ar]);
3811 #else
b14b6a8f 3812 void *jaddr3 = out;
b9b61529 3813 emit_jne(0);
b14b6a8f 3814 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3815 #endif
b9b61529 3816 }
cf95b4f0 3817 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3818 host_tempreg_acquire();
b9b61529 3819 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3820 host_tempreg_release();
b9b61529 3821 }
3822}
3823
81dbbf4c 3824static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3825{
81dbbf4c 3826 u_int copr = (source[i]>>11) & 0x1f;
9de8a0c3 3827 signed char temp = get_reg_temp(i_regs->regmap);
81dbbf4c 3828
32631e6a 3829 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3830 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3831 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3832 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3833 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3834 }
32631e6a 3835 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3836 }
cf95b4f0 3837 if (dops[i].opcode2==0) { // MFC2
3838 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3839 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3840 cop2_get_dreg(copr,tl,temp);
3841 }
cf95b4f0 3842 else if (dops[i].opcode2==4) { // MTC2
3843 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3844 cop2_put_dreg(copr,sl,temp);
3845 }
cf95b4f0 3846 else if (dops[i].opcode2==2) // CFC2
8062d65a 3847 {
cf95b4f0 3848 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3849 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3850 emit_readword(&reg_cop2c[copr],tl);
3851 }
cf95b4f0 3852 else if (dops[i].opcode2==6) // CTC2
8062d65a 3853 {
cf95b4f0 3854 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3855 switch(copr) {
3856 case 4:
3857 case 12:
3858 case 20:
3859 case 26:
3860 case 27:
3861 case 29:
3862 case 30:
3863 emit_signextend16(sl,temp);
3864 break;
3865 case 31:
3968e69e 3866 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3867 break;
3868 default:
3869 temp=sl;
3870 break;
3871 }
3872 emit_writeword(temp,&reg_cop2c[copr]);
3873 assert(sl>=0);
3874 }
3875}
3876
3968e69e 3877static void do_unalignedwritestub(int n)
3878{
3879 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3880 literal_pool(256);
3881 set_jump_target(stubs[n].addr, out);
3882
3883 int i=stubs[n].a;
3884 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3885 int addr=stubs[n].b;
3886 u_int reglist=stubs[n].e;
3887 signed char *i_regmap=i_regs->regmap;
3888 int temp2=get_reg(i_regmap,FTEMP);
3889 int rt;
cf95b4f0 3890 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3891 assert(rt>=0);
3892 assert(addr>=0);
cf95b4f0 3893 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3894 reglist|=(1<<addr);
3895 reglist&=~(1<<temp2);
3896
3968e69e 3897 // don't bother with it and call write handler
3898 save_regs(reglist);
3899 pass_args(addr,rt);
3900 int cc=get_reg(i_regmap,CCREG);
3901 if(cc<0)
3902 emit_loadreg(CCREG,2);
2330734f 3903 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3904 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3905 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3906 if(cc<0)
3907 emit_storereg(CCREG,2);
3908 restore_regs(reglist);
3909 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3910}
3911
57871462 3912#ifndef multdiv_assemble
3913void multdiv_assemble(int i,struct regstat *i_regs)
3914{
3915 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3916 abort();
57871462 3917}
3918#endif
3919
2330734f 3920static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3921{
cf95b4f0 3922 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3923 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3924 if(dops[i].rt1) {
7c3a5182 3925 signed char sl,tl;
cf95b4f0 3926 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3927 //assert(tl>=0);
3928 if(tl>=0) {
cf95b4f0 3929 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3930 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3931 else emit_loadreg(dops[i].rs1,tl);
57871462 3932 }
3933 }
cf95b4f0 3934 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3935 multdiv_do_stall(i, i_regs);
57871462 3936}
3937
3968e69e 3938// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3939static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3940{
3941 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3942 assert(ccreg==HOST_CCREG);
3943 assert(!is_delayslot);
581335b0 3944 (void)ccreg;
3968e69e 3945
3946 emit_movimm(pc,3); // Get PC
3947 emit_readword(&last_count,2);
3948 emit_writeword(3,&psxRegs.pc);
2330734f 3949 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3950 emit_add(2,HOST_CCREG,2);
3951 emit_writeword(2,&psxRegs.cycle);
2a014d73 3952 emit_far_call(func);
3953 emit_far_jump(jump_to_new_pc);
3968e69e 3954}
3955
2330734f 3956static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3957{
d1150cd6 3958 // 'break' tends to be littered around to catch things like
3959 // division by 0 and is almost never executed, so don't emit much code here
3960 void *func = (dops[i].opcode2 == 0x0C)
3961 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
3962 : (is_delayslot ? jump_break_ds : jump_break);
2acc46cd 3963 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
d1150cd6 3964 emit_movimm(start + i*4, 2); // pc
3965 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
3966 emit_far_jump(func);
7139f3c8 3967}
3968
2330734f 3969static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3970{
3968e69e 3971 void *hlefunc = psxNULL;
dd79da89 3972 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3973 if (hleCode < ARRAY_SIZE(psxHLEt))
3974 hlefunc = psxHLEt[hleCode];
3975
2330734f 3976 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3977}
3978
2330734f 3979static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3980{
2330734f 3981 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3982}
3983
8062d65a 3984static void speculate_mov(int rs,int rt)
3985{
3986 if(rt!=0) {
3987 smrv_strong_next|=1<<rt;
3988 smrv[rt]=smrv[rs];
3989 }
3990}
3991
3992static void speculate_mov_weak(int rs,int rt)
3993{
3994 if(rt!=0) {
3995 smrv_weak_next|=1<<rt;
3996 smrv[rt]=smrv[rs];
3997 }
3998}
3999
4000static void speculate_register_values(int i)
4001{
4002 if(i==0) {
4003 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4004 // gp,sp are likely to stay the same throughout the block
4005 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4006 smrv_weak_next=~smrv_strong_next;
4007 //printf(" llr %08x\n", smrv[4]);
4008 }
4009 smrv_strong=smrv_strong_next;
4010 smrv_weak=smrv_weak_next;
cf95b4f0 4011 switch(dops[i].itype) {
8062d65a 4012 case ALU:
cf95b4f0 4013 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4014 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4015 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4016 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 4017 else {
cf95b4f0 4018 smrv_strong_next&=~(1<<dops[i].rt1);
4019 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4020 }
4021 break;
4022 case SHIFTIMM:
cf95b4f0 4023 smrv_strong_next&=~(1<<dops[i].rt1);
4024 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4025 // fallthrough
4026 case IMM16:
cf95b4f0 4027 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4028 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 4029 if(hr>=0) {
4030 if(get_final_value(hr,i,&value))
cf95b4f0 4031 smrv[dops[i].rt1]=value;
4032 else smrv[dops[i].rt1]=constmap[i][hr];
4033 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4034 }
4035 }
4036 else {
cf95b4f0 4037 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4038 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4039 }
4040 break;
4041 case LOAD:
cf95b4f0 4042 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4043 // special case for BIOS
cf95b4f0 4044 smrv[dops[i].rt1]=0xa0000000;
4045 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4046 break;
4047 }
4048 // fallthrough
4049 case SHIFT:
4050 case LOADLR:
4051 case MOV:
cf95b4f0 4052 smrv_strong_next&=~(1<<dops[i].rt1);
4053 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4054 break;
4055 case COP0:
4056 case COP2:
cf95b4f0 4057 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4058 smrv_strong_next&=~(1<<dops[i].rt1);
4059 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4060 }
4061 break;
4062 case C2LS:
cf95b4f0 4063 if (dops[i].opcode==0x32) { // LWC2
4064 smrv_strong_next&=~(1<<dops[i].rt1);
4065 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4066 }
4067 break;
4068 }
4069#if 0
4070 int r=4;
4071 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4072 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4073#endif
4074}
4075
2330734f 4076static void ujump_assemble(int i, const struct regstat *i_regs);
4077static void rjump_assemble(int i, const struct regstat *i_regs);
4078static void cjump_assemble(int i, const struct regstat *i_regs);
4079static void sjump_assemble(int i, const struct regstat *i_regs);
4080static void pagespan_assemble(int i, const struct regstat *i_regs);
4081
4082static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4083{
2330734f 4084 int ds = 0;
4085 switch (dops[i].itype) {
57871462 4086 case ALU:
2330734f 4087 alu_assemble(i, i_regs);
4088 break;
57871462 4089 case IMM16:
2330734f 4090 imm16_assemble(i, i_regs);
4091 break;
57871462 4092 case SHIFT:
2330734f 4093 shift_assemble(i, i_regs);
4094 break;
57871462 4095 case SHIFTIMM:
2330734f 4096 shiftimm_assemble(i, i_regs);
4097 break;
57871462 4098 case LOAD:
2330734f 4099 load_assemble(i, i_regs, ccadj_);
4100 break;
57871462 4101 case LOADLR:
2330734f 4102 loadlr_assemble(i, i_regs, ccadj_);
4103 break;
57871462 4104 case STORE:
2330734f 4105 store_assemble(i, i_regs, ccadj_);
4106 break;
57871462 4107 case STORELR:
2330734f 4108 storelr_assemble(i, i_regs, ccadj_);
4109 break;
57871462 4110 case COP0:
2330734f 4111 cop0_assemble(i, i_regs, ccadj_);
4112 break;
57871462 4113 case COP1:
2330734f 4114 cop1_assemble(i, i_regs);
4115 break;
57871462 4116 case C1LS:
2330734f 4117 c1ls_assemble(i, i_regs);
4118 break;
b9b61529 4119 case COP2:
2330734f 4120 cop2_assemble(i, i_regs);
4121 break;
b9b61529 4122 case C2LS:
2330734f 4123 c2ls_assemble(i, i_regs, ccadj_);
4124 break;
b9b61529 4125 case C2OP:
2330734f 4126 c2op_assemble(i, i_regs);
4127 break;
57871462 4128 case MULTDIV:
2330734f 4129 multdiv_assemble(i, i_regs);
4130 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4131 break;
57871462 4132 case MOV:
2330734f 4133 mov_assemble(i, i_regs);
4134 break;
4135 case SYSCALL:
4136 syscall_assemble(i, i_regs, ccadj_);
4137 break;
4138 case HLECALL:
4139 hlecall_assemble(i, i_regs, ccadj_);
4140 break;
4141 case INTCALL:
4142 intcall_assemble(i, i_regs, ccadj_);
4143 break;
4144 case UJUMP:
4145 ujump_assemble(i, i_regs);
4146 ds = 1;
4147 break;
4148 case RJUMP:
4149 rjump_assemble(i, i_regs);
4150 ds = 1;
4151 break;
4152 case CJUMP:
4153 cjump_assemble(i, i_regs);
4154 ds = 1;
4155 break;
4156 case SJUMP:
4157 sjump_assemble(i, i_regs);
4158 ds = 1;
4159 break;
4160 case SPAN:
4161 pagespan_assemble(i, i_regs);
4162 break;
24058131 4163 case NOP:
2330734f 4164 case OTHER:
4165 case NI:
4166 // not handled, just skip
4167 break;
4168 default:
4169 assert(0);
4170 }
4171 return ds;
4172}
4173
4174static void ds_assemble(int i, const struct regstat *i_regs)
4175{
4176 speculate_register_values(i);
4177 is_delayslot = 1;
4178 switch (dops[i].itype) {
57871462 4179 case SYSCALL:
7139f3c8 4180 case HLECALL:
1e973cb0 4181 case INTCALL:
57871462 4182 case SPAN:
4183 case UJUMP:
4184 case RJUMP:
4185 case CJUMP:
4186 case SJUMP:
c43b5311 4187 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4188 break;
4189 default:
4190 assemble(i, i_regs, ccadj[i]);
57871462 4191 }
2330734f 4192 is_delayslot = 0;
57871462 4193}
4194
4195// Is the branch target a valid internal jump?
ad49de89 4196static int internal_branch(int addr)
57871462 4197{
4198 if(addr&1) return 0; // Indirect (register) jump
4199 if(addr>=start && addr<start+slen*4-4)
4200 {
71e490c5 4201 return 1;
57871462 4202 }
4203 return 0;
4204}
4205
ad49de89 4206static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4207{
4208 int hr;
4209 for(hr=0;hr<HOST_REGS;hr++) {
4210 if(hr!=EXCLUDE_REG) {
4211 if(pre[hr]!=entry[hr]) {
4212 if(pre[hr]>=0) {
4213 if((dirty>>hr)&1) {
4214 if(get_reg(entry,pre[hr])<0) {
00fa9369 4215 assert(pre[hr]<64);
4216 if(!((u>>pre[hr])&1))
4217 emit_storereg(pre[hr],hr);
57871462 4218 }
4219 }
4220 }
4221 }
4222 }
4223 }
4224 // Move from one register to another (no writeback)
4225 for(hr=0;hr<HOST_REGS;hr++) {
4226 if(hr!=EXCLUDE_REG) {
4227 if(pre[hr]!=entry[hr]) {
9de8a0c3 4228 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
57871462 4229 int nr;
4230 if((nr=get_reg(entry,pre[hr]))>=0) {
4231 emit_mov(hr,nr);
4232 }
4233 }
4234 }
4235 }
4236 }
4237}
57871462 4238
4239// Load the specified registers
4240// This only loads the registers given as arguments because
4241// we don't want to load things that will be overwritten
ad49de89 4242static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4243{
4244 int hr;
4245 // Load 32-bit regs
4246 for(hr=0;hr<HOST_REGS;hr++) {
4247 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4248 if(entry[hr]!=regmap[hr]) {
4249 if(regmap[hr]==rs1||regmap[hr]==rs2)
4250 {
4251 if(regmap[hr]==0) {
4252 emit_zeroreg(hr);
4253 }
4254 else
4255 {
4256 emit_loadreg(regmap[hr],hr);
4257 }
4258 }
4259 }
4260 }
4261 }
57871462 4262}
4263
4264// Load registers prior to the start of a loop
4265// so that they are not loaded within the loop
4266static void loop_preload(signed char pre[],signed char entry[])
4267{
4268 int hr;
4269 for(hr=0;hr<HOST_REGS;hr++) {
4270 if(hr!=EXCLUDE_REG) {
4271 if(pre[hr]!=entry[hr]) {
4272 if(entry[hr]>=0) {
4273 if(get_reg(pre,entry[hr])<0) {
4274 assem_debug("loop preload:\n");
4275 //printf("loop preload: %d\n",hr);
4276 if(entry[hr]==0) {
4277 emit_zeroreg(hr);
4278 }
4279 else if(entry[hr]<TEMPREG)
4280 {
4281 emit_loadreg(entry[hr],hr);
4282 }
4283 else if(entry[hr]-64<TEMPREG)
4284 {
4285 emit_loadreg(entry[hr],hr);
4286 }
4287 }
4288 }
4289 }
4290 }
4291 }
4292}
4293
4294// Generate address for load/store instruction
b9b61529 4295// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4296void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4297{
37387d8b 4298 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4299 int ra=-1;
57871462 4300 int agr=AGEN1+(i&1);
cf95b4f0 4301 if(dops[i].itype==LOAD) {
4302 ra=get_reg(i_regs->regmap,dops[i].rt1);
9de8a0c3 4303 if(ra<0) ra=get_reg_temp(i_regs->regmap);
535d208a 4304 assert(ra>=0);
57871462 4305 }
cf95b4f0 4306 if(dops[i].itype==LOADLR) {
57871462 4307 ra=get_reg(i_regs->regmap,FTEMP);
4308 }
cf95b4f0 4309 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4310 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4311 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4312 }
37387d8b 4313 if(dops[i].itype==C2LS) {
cf95b4f0 4314 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4315 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4316 else { // SWC1/SDC1/SWC2/SDC2
57871462 4317 ra=get_reg(i_regs->regmap,agr);
9de8a0c3 4318 if(ra<0) ra=get_reg_temp(i_regs->regmap);
57871462 4319 }
4320 }
cf95b4f0 4321 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4322 if(ra>=0) {
4323 int offset=imm[i];
4324 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4325 if(dops[i].rs1==0) {
57871462 4326 // Using r0 as a base address
57871462 4327 if(!entry||entry[ra]!=agr) {
cf95b4f0 4328 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4329 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4330 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4331 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4332 }else{
4333 emit_movimm(offset,ra);
4334 }
4335 } // else did it in the previous cycle
4336 }
4337 else if(rs<0) {
cf95b4f0 4338 if(!entry||entry[ra]!=dops[i].rs1)
4339 emit_loadreg(dops[i].rs1,ra);
4340 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4341 // printf("poor load scheduling!\n");
4342 }
4343 else if(c) {
cf95b4f0 4344 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4345 if(!entry||entry[ra]!=agr) {
cf95b4f0 4346 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4347 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4348 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4349 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4350 }else{
57871462 4351 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4352 regs[i].loadedconst|=1<<ra;
57871462 4353 }
4354 } // else did it in the previous cycle
4355 } // else load_consts already did it
4356 }
cf95b4f0 4357 if(offset&&!c&&dops[i].rs1) {
57871462 4358 if(rs>=0) {
4359 emit_addimm(rs,offset,ra);
4360 }else{
4361 emit_addimm(ra,offset,ra);
4362 }
4363 }
4364 }
4365 }
4366 // Preload constants for next instruction
37387d8b 4367 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4368 int agr,ra;
57871462 4369 // Actual address
4370 agr=AGEN1+((i+1)&1);
4371 ra=get_reg(i_regs->regmap,agr);
4372 if(ra>=0) {
cf95b4f0 4373 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4374 int offset=imm[i+1];
4375 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4376 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4377 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4378 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4379 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4380 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4381 }else{
57871462 4382 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4383 regs[i+1].loadedconst|=1<<ra;
57871462 4384 }
4385 }
cf95b4f0 4386 else if(dops[i+1].rs1==0) {
57871462 4387 // Using r0 as a base address
cf95b4f0 4388 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4389 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4390 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4391 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4392 }else{
4393 emit_movimm(offset,ra);
4394 }
4395 }
4396 }
4397 }
4398}
4399
e2b5e7aa 4400static int get_final_value(int hr, int i, int *value)
57871462 4401{
4402 int reg=regs[i].regmap[hr];
4403 while(i<slen-1) {
4404 if(regs[i+1].regmap[hr]!=reg) break;
4405 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4406 if(dops[i+1].bt) break;
57871462 4407 i++;
4408 }
4409 if(i<slen-1) {
fe807a8a 4410 if (dops[i].is_jump) {
57871462 4411 *value=constmap[i][hr];
4412 return 1;
4413 }
cf95b4f0 4414 if(!dops[i+1].bt) {
fe807a8a 4415 if (dops[i+1].is_jump) {
57871462 4416 // Load in delay slot, out-of-order execution
cf95b4f0 4417 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4418 {
57871462 4419 // Precompute load address
4420 *value=constmap[i][hr]+imm[i+2];
4421 return 1;
4422 }
4423 }
cf95b4f0 4424 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4425 {
57871462 4426 // Precompute load address
4427 *value=constmap[i][hr]+imm[i+1];
643aeae3 4428 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4429 return 1;
4430 }
4431 }
4432 }
4433 *value=constmap[i][hr];
643aeae3 4434 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4435 if(i==slen-1) return 1;
00fa9369 4436 assert(reg < 64);
4437 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4438}
4439
4440// Load registers with known constants
ad49de89 4441static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4442{
8575a877 4443 int hr,hr2;
4444 // propagate loaded constant flags
cf95b4f0 4445 if(i==0||dops[i].bt)
8575a877 4446 regs[i].loadedconst=0;
4447 else {
4448 for(hr=0;hr<HOST_REGS;hr++) {
4449 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4450 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4451 {
4452 regs[i].loadedconst|=1<<hr;
4453 }
4454 }
4455 }
57871462 4456 // Load 32-bit regs
4457 for(hr=0;hr<HOST_REGS;hr++) {
4458 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4459 //if(entry[hr]!=regmap[hr]) {
8575a877 4460 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4461 assert(regmap[hr]<64);
4462 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4463 int value,similar=0;
57871462 4464 if(get_final_value(hr,i,&value)) {
8575a877 4465 // see if some other register has similar value
4466 for(hr2=0;hr2<HOST_REGS;hr2++) {
4467 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4468 if(is_similar_value(value,constmap[i][hr2])) {
4469 similar=1;
4470 break;
4471 }
4472 }
4473 }
4474 if(similar) {
4475 int value2;
4476 if(get_final_value(hr2,i,&value2)) // is this needed?
4477 emit_movimm_from(value2,hr2,value,hr);
4478 else
4479 emit_movimm(value,hr);
4480 }
4481 else if(value==0) {
57871462 4482 emit_zeroreg(hr);
4483 }
4484 else {
4485 emit_movimm(value,hr);
4486 }
4487 }
8575a877 4488 regs[i].loadedconst|=1<<hr;
57871462 4489 }
4490 }
4491 }
4492 }
57871462 4493}
ad49de89 4494
2330734f 4495static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4496{
4497 int hr;
4498 // Load 32-bit regs
4499 for(hr=0;hr<HOST_REGS;hr++) {
4500 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4501 assert(regmap[hr] < 64);
4502 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4503 int value=constmap[i][hr];
4504 if(value==0) {
4505 emit_zeroreg(hr);
4506 }
4507 else {
4508 emit_movimm(value,hr);
4509 }
4510 }
4511 }
4512 }
57871462 4513}
4514
4515// Write out all dirty registers (except cycle count)
2330734f 4516static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4517{
4518 int hr;
4519 for(hr=0;hr<HOST_REGS;hr++) {
4520 if(hr!=EXCLUDE_REG) {
4521 if(i_regmap[hr]>0) {
4522 if(i_regmap[hr]!=CCREG) {
4523 if((i_dirty>>hr)&1) {
00fa9369 4524 assert(i_regmap[hr]<64);
4525 emit_storereg(i_regmap[hr],hr);
57871462 4526 }
4527 }
4528 }
4529 }
4530 }
4531}
ad49de89 4532
57871462 4533// Write out dirty registers that we need to reload (pair with load_needed_regs)
4534// This writes the registers not written by store_regs_bt
2330734f 4535static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4536{
4537 int hr;
4538 int t=(addr-start)>>2;
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG) {
4541 if(i_regmap[hr]>0) {
4542 if(i_regmap[hr]!=CCREG) {
ad49de89 4543 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4544 if((i_dirty>>hr)&1) {
00fa9369 4545 assert(i_regmap[hr]<64);
4546 emit_storereg(i_regmap[hr],hr);
57871462 4547 }
4548 }
4549 }
4550 }
4551 }
4552 }
4553}
4554
4555// Load all registers (except cycle count)
2330734f 4556static void load_all_regs(const signed char i_regmap[])
57871462 4557{
4558 int hr;
4559 for(hr=0;hr<HOST_REGS;hr++) {
4560 if(hr!=EXCLUDE_REG) {
4561 if(i_regmap[hr]==0) {
4562 emit_zeroreg(hr);
4563 }
4564 else
9de8a0c3 4565 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4566 {
4567 emit_loadreg(i_regmap[hr],hr);
4568 }
4569 }
4570 }
4571}
4572
4573// Load all current registers also needed by next instruction
2330734f 4574static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4575{
4576 int hr;
4577 for(hr=0;hr<HOST_REGS;hr++) {
4578 if(hr!=EXCLUDE_REG) {
4579 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4580 if(i_regmap[hr]==0) {
4581 emit_zeroreg(hr);
4582 }
4583 else
9de8a0c3 4584 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4585 {
4586 emit_loadreg(i_regmap[hr],hr);
4587 }
4588 }
4589 }
4590 }
4591}
4592
4593// Load all regs, storing cycle count if necessary
2330734f 4594static void load_regs_entry(int t)
57871462 4595{
4596 int hr;
cf95b4f0 4597 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4598 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4599 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4600 emit_storereg(CCREG,HOST_CCREG);
4601 }
4602 // Load 32-bit regs
4603 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4604 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4605 if(regs[t].regmap_entry[hr]==0) {
4606 emit_zeroreg(hr);
4607 }
4608 else if(regs[t].regmap_entry[hr]!=CCREG)
4609 {
4610 emit_loadreg(regs[t].regmap_entry[hr],hr);
4611 }
4612 }
4613 }
57871462 4614}
4615
4616// Store dirty registers prior to branch
ad49de89 4617void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4618{
ad49de89 4619 if(internal_branch(addr))
57871462 4620 {
4621 int t=(addr-start)>>2;
4622 int hr;
4623 for(hr=0;hr<HOST_REGS;hr++) {
4624 if(hr!=EXCLUDE_REG) {
4625 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4626 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4627 if((i_dirty>>hr)&1) {
00fa9369 4628 assert(i_regmap[hr]<64);
4629 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4630 emit_storereg(i_regmap[hr],hr);
57871462 4631 }
4632 }
4633 }
4634 }
4635 }
4636 }
4637 else
4638 {
4639 // Branch out of this block, write out all dirty regs
ad49de89 4640 wb_dirtys(i_regmap,i_dirty);
57871462 4641 }
4642}
4643
4644// Load all needed registers for branch target
ad49de89 4645static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4646{
4647 //if(addr>=start && addr<(start+slen*4))
ad49de89 4648 if(internal_branch(addr))
57871462 4649 {
4650 int t=(addr-start)>>2;
4651 int hr;
4652 // Store the cycle count before loading something else
4653 if(i_regmap[HOST_CCREG]!=CCREG) {
4654 assert(i_regmap[HOST_CCREG]==-1);
4655 }
4656 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4657 emit_storereg(CCREG,HOST_CCREG);
4658 }
4659 // Load 32-bit regs
4660 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4661 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4662 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4663 if(regs[t].regmap_entry[hr]==0) {
4664 emit_zeroreg(hr);
4665 }
4666 else if(regs[t].regmap_entry[hr]!=CCREG)
4667 {
4668 emit_loadreg(regs[t].regmap_entry[hr],hr);
4669 }
4670 }
4671 }
4672 }
57871462 4673 }
4674}
4675
ad49de89 4676static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4677{
4678 if(addr>=start && addr<start+slen*4-4)
4679 {
4680 int t=(addr-start)>>2;
4681 int hr;
4682 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4683 for(hr=0;hr<HOST_REGS;hr++)
4684 {
4685 if(hr!=EXCLUDE_REG)
4686 {
4687 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4688 {
ea3d2e6e 4689 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4690 {
4691 return 0;
4692 }
9f51b4b9 4693 else
57871462 4694 if((i_dirty>>hr)&1)
4695 {
ea3d2e6e 4696 if(i_regmap[hr]<TEMPREG)
57871462 4697 {
4698 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4699 return 0;
4700 }
ea3d2e6e 4701 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4702 {
00fa9369 4703 assert(0);
57871462 4704 }
4705 }
4706 }
4707 else // Same register but is it 32-bit or dirty?
4708 if(i_regmap[hr]>=0)
4709 {
4710 if(!((regs[t].dirty>>hr)&1))
4711 {
4712 if((i_dirty>>hr)&1)
4713 {
4714 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4715 {
4716 //printf("%x: dirty no match\n",addr);
4717 return 0;
4718 }
4719 }
4720 }
57871462 4721 }
4722 }
4723 }
57871462 4724 // Delay slots are not valid branch targets
fe807a8a 4725 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4726 // Delay slots require additional processing, so do not match
cf95b4f0 4727 if(dops[t].is_ds) return 0;
57871462 4728 }
4729 else
4730 {
4731 int hr;
4732 for(hr=0;hr<HOST_REGS;hr++)
4733 {
4734 if(hr!=EXCLUDE_REG)
4735 {
4736 if(i_regmap[hr]>=0)
4737 {
4738 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4739 {
4740 if((i_dirty>>hr)&1)
4741 {
4742 return 0;
4743 }
4744 }
4745 }
4746 }
4747 }
4748 }
4749 return 1;
4750}
4751
dd114d7d 4752#ifdef DRC_DBG
2330734f 4753static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4754{
4755 extern void do_insn_cmp();
3968e69e 4756 //extern int cycle;
81dbbf4c 4757 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4758
40fca85b 4759 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4760 save_regs(reglist);
40fca85b 4761 // write out changed consts to match the interpreter
cf95b4f0 4762 if (i > 0 && !dops[i].bt) {
40fca85b 4763 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4764 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4765 if (hr == EXCLUDE_REG || reg < 0)
4766 continue;
4767 if (!((regs[i-1].isconst >> hr) & 1))
4768 continue;
4769 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4770 continue;
4771 emit_movimm(constmap[i-1][hr],0);
4772 emit_storereg(reg, 0);
4773 }
4774 }
dd114d7d 4775 emit_movimm(start+i*4,0);
643aeae3 4776 emit_writeword(0,&pcaddr);
2330734f 4777 int cc = get_reg(regs[i].regmap_entry, CCREG);
4778 if (cc < 0)
4779 emit_loadreg(CCREG, cc = 0);
4780 emit_addimm(cc, ccadj_, 0);
4781 emit_writeword(0, &psxRegs.cycle);
2a014d73 4782 emit_far_call(do_insn_cmp);
643aeae3 4783 //emit_readword(&cycle,0);
dd114d7d 4784 //emit_addimm(0,2,0);
643aeae3 4785 //emit_writeword(0,&cycle);
3968e69e 4786 (void)get_reg2;
dd114d7d 4787 restore_regs(reglist);
40fca85b 4788 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4789}
4790#else
2330734f 4791#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4792#endif
4793
57871462 4794// Used when a branch jumps into the delay slot of another branch
7c3a5182 4795static void ds_assemble_entry(int i)
57871462 4796{
2330734f 4797 int t = (ba[i] - start) >> 2;
4798 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4799 if (!instr_addr[t])
4800 instr_addr[t] = out;
57871462 4801 assem_debug("Assemble delay slot at %x\n",ba[i]);
4802 assem_debug("<->\n");
2330734f 4803 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4804 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4805 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4806 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4807 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4808 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4809 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4810 if (dops[t].is_store)
ad49de89 4811 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4812 is_delayslot=0;
2330734f 4813 switch (dops[t].itype) {
57871462 4814 case SYSCALL:
7139f3c8 4815 case HLECALL:
1e973cb0 4816 case INTCALL:
57871462 4817 case SPAN:
4818 case UJUMP:
4819 case RJUMP:
4820 case CJUMP:
4821 case SJUMP:
c43b5311 4822 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4823 break;
4824 default:
4825 assemble(t, &regs[t], ccadj_);
57871462 4826 }
ad49de89 4827 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4828 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4829 if(internal_branch(ba[i]+4))
57871462 4830 assem_debug("branch: internal\n");
4831 else
4832 assem_debug("branch: external\n");
ad49de89 4833 assert(internal_branch(ba[i]+4));
4834 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4835 emit_jmp(0);
4836}
4837
7c3a5182 4838static void emit_extjump(void *addr, u_int target)
4839{
4840 emit_extjump2(addr, target, dyna_linker);
4841}
4842
4843static void emit_extjump_ds(void *addr, u_int target)
4844{
4845 emit_extjump2(addr, target, dyna_linker_ds);
4846}
4847
d1e4ebd9 4848// Load 2 immediates optimizing for small code size
4849static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4850{
4851 emit_movimm(imm1,rt1);
4852 emit_movimm_from(imm1,rt1,imm2,rt2);
4853}
4854
2330734f 4855static void do_cc(int i, const signed char i_regmap[], int *adj,
4856 int addr, int taken, int invert)
57871462 4857{
2330734f 4858 int count, count_plus2;
b14b6a8f 4859 void *jaddr;
4860 void *idle=NULL;
b6e87b2b 4861 int t=0;
cf95b4f0 4862 if(dops[i].itype==RJUMP)
57871462 4863 {
4864 *adj=0;
4865 }
4866 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4867 if(internal_branch(ba[i]))
57871462 4868 {
b6e87b2b 4869 t=(ba[i]-start)>>2;
2330734f 4870 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4871 else *adj=ccadj[t];
4872 }
4873 else
4874 {
4875 *adj=0;
4876 }
2330734f 4877 count = ccadj[i];
4878 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4879 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4880 // Idle loop
4881 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4882 idle=out;
57871462 4883 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4884 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4885 jaddr=out;
57871462 4886 emit_jmp(0);
4887 }
4888 else if(*adj==0||invert) {
2330734f 4889 int cycles = count_plus2;
b6e87b2b 4890 // faster loop HACK
bb4f300c 4891#if 0
b6e87b2b 4892 if (t&&*adj) {
4893 int rel=t-i;
4894 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4895 cycles=*adj+count+2-*adj;
b6e87b2b 4896 }
bb4f300c 4897#endif
2330734f 4898 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4899 jaddr = out;
57871462 4900 emit_jns(0);
4901 }
4902 else
4903 {
2330734f 4904 emit_cmpimm(HOST_CCREG, -count_plus2);
4905 jaddr = out;
57871462 4906 emit_jns(0);
4907 }
2330734f 4908 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4909}
4910
b14b6a8f 4911static void do_ccstub(int n)
57871462 4912{
4913 literal_pool(256);
d1e4ebd9 4914 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4915 set_jump_target(stubs[n].addr, out);
4916 int i=stubs[n].b;
4917 if(stubs[n].d==NULLDS) {
57871462 4918 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4919 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4920 }
b14b6a8f 4921 else if(stubs[n].d!=TAKEN) {
ad49de89 4922 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4923 }
4924 else {
ad49de89 4925 if(internal_branch(ba[i]))
4926 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4927 }
b14b6a8f 4928 if(stubs[n].c!=-1)
57871462 4929 {
4930 // Save PC as return address
b14b6a8f 4931 emit_movimm(stubs[n].c,EAX);
643aeae3 4932 emit_writeword(EAX,&pcaddr);
57871462 4933 }
4934 else
4935 {
4936 // Return address depends on which way the branch goes
cf95b4f0 4937 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4938 {
cf95b4f0 4939 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4940 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4941 if(dops[i].rs1==0)
57871462 4942 {
ad49de89 4943 s1l=s2l;
4944 s2l=-1;
57871462 4945 }
cf95b4f0 4946 else if(dops[i].rs2==0)
57871462 4947 {
ad49de89 4948 s2l=-1;
57871462 4949 }
4950 assert(s1l>=0);
4951 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4952 if(dops[i].rs1) {
ad49de89 4953 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4954 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4955 }
57871462 4956 else {
ad49de89 4957 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4958 emit_loadreg(dops[i].rs2,s1l);
57871462 4959 }
4960 if(s2l>=0)
ad49de89 4961 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4962 emit_loadreg(dops[i].rs2,s2l);
57871462 4963 #endif
4964 int hr=0;
5194fb95 4965 int addr=-1,alt=-1,ntaddr=-1;
57871462 4966 while(hr<HOST_REGS)
4967 {
4968 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 4969 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4970 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 4971 {
4972 addr=hr++;break;
4973 }
4974 hr++;
4975 }
4976 while(hr<HOST_REGS)
4977 {
4978 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 4979 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4980 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 4981 {
4982 alt=hr++;break;
4983 }
4984 hr++;
4985 }
cf95b4f0 4986 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4987 {
4988 while(hr<HOST_REGS)
4989 {
4990 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 4991 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4992 branch_regs[i].regmap[hr]!=dops[i].rs2 )
57871462 4993 {
4994 ntaddr=hr;break;
4995 }
4996 hr++;
4997 }
4998 assert(hr<HOST_REGS);
4999 }
cf95b4f0 5000 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5001 {
5002 #ifdef HAVE_CMOV_IMM
ad49de89 5003 if(s2l>=0) emit_cmp(s1l,s2l);
5004 else emit_test(s1l,s1l);
5005 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5006 #else
5007 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5008 if(s2l>=0) emit_cmp(s1l,s2l);
5009 else emit_test(s1l,s1l);
5010 emit_cmovne_reg(alt,addr);
57871462 5011 #endif
57871462 5012 }
cf95b4f0 5013 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5014 {
5015 #ifdef HAVE_CMOV_IMM
ad49de89 5016 if(s2l>=0) emit_cmp(s1l,s2l);
5017 else emit_test(s1l,s1l);
5018 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5019 #else
5020 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5021 if(s2l>=0) emit_cmp(s1l,s2l);
5022 else emit_test(s1l,s1l);
5023 emit_cmovne_reg(alt,addr);
57871462 5024 #endif
57871462 5025 }
cf95b4f0 5026 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5027 {
5028 //emit_movimm(ba[i],alt);
5029 //emit_movimm(start+i*4+8,addr);
5030 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5031 emit_cmpimm(s1l,1);
57871462 5032 emit_cmovl_reg(alt,addr);
57871462 5033 }
cf95b4f0 5034 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5035 {
5036 //emit_movimm(ba[i],addr);
5037 //emit_movimm(start+i*4+8,ntaddr);
5038 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5039 emit_cmpimm(s1l,1);
57871462 5040 emit_cmovl_reg(ntaddr,addr);
57871462 5041 }
cf95b4f0 5042 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5043 {
5044 //emit_movimm(ba[i],alt);
5045 //emit_movimm(start+i*4+8,addr);
5046 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5047 emit_test(s1l,s1l);
57871462 5048 emit_cmovs_reg(alt,addr);
5049 }
cf95b4f0 5050 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5051 {
5052 //emit_movimm(ba[i],addr);
5053 //emit_movimm(start+i*4+8,alt);
5054 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5055 emit_test(s1l,s1l);
57871462 5056 emit_cmovs_reg(alt,addr);
5057 }
cf95b4f0 5058 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5059 if(source[i]&0x10000) // BC1T
5060 {
5061 //emit_movimm(ba[i],alt);
5062 //emit_movimm(start+i*4+8,addr);
5063 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5064 emit_testimm(s1l,0x800000);
5065 emit_cmovne_reg(alt,addr);
5066 }
5067 else // BC1F
5068 {
5069 //emit_movimm(ba[i],addr);
5070 //emit_movimm(start+i*4+8,alt);
5071 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5072 emit_testimm(s1l,0x800000);
5073 emit_cmovne_reg(alt,addr);
5074 }
5075 }
643aeae3 5076 emit_writeword(addr,&pcaddr);
57871462 5077 }
5078 else
cf95b4f0 5079 if(dops[i].itype==RJUMP)
57871462 5080 {
cf95b4f0 5081 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5082 if (ds_writes_rjump_rs(i)) {
57871462 5083 r=get_reg(branch_regs[i].regmap,RTEMP);
5084 }
643aeae3 5085 emit_writeword(r,&pcaddr);
57871462 5086 }
7c3a5182 5087 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5088 }
5089 // Update cycle count
5090 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5091 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5092 emit_far_call(cc_interrupt);
2330734f 5093 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5094 if(stubs[n].d==TAKEN) {
ad49de89 5095 if(internal_branch(ba[i]))
57871462 5096 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5097 else if(dops[i].itype==RJUMP) {
57871462 5098 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5099 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5100 else
cf95b4f0 5101 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5102 }
b14b6a8f 5103 }else if(stubs[n].d==NOTTAKEN) {
57871462 5104 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5105 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5106 }else if(stubs[n].d==NULLDS) {
57871462 5107 // Delay slot instruction is nullified ("likely" branch)
5108 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5109 else load_all_regs(regs[i].regmap);
5110 }else{
5111 load_all_regs(branch_regs[i].regmap);
5112 }
d1e4ebd9 5113 if (stubs[n].retaddr)
5114 emit_jmp(stubs[n].retaddr);
5115 else
5116 do_jump_vaddr(stubs[n].e);
57871462 5117}
5118
643aeae3 5119static void add_to_linker(void *addr, u_int target, int ext)
57871462 5120{
643aeae3 5121 assert(linkcount < ARRAY_SIZE(link_addr));
5122 link_addr[linkcount].addr = addr;
5123 link_addr[linkcount].target = target;
5124 link_addr[linkcount].ext = ext;
57871462 5125 linkcount++;
5126}
5127
eba830cd 5128static void ujump_assemble_write_ra(int i)
5129{
5130 int rt;
5131 unsigned int return_address;
5132 rt=get_reg(branch_regs[i].regmap,31);
5133 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5134 //assert(rt>=0);
5135 return_address=start+i*4+8;
5136 if(rt>=0) {
5137 #ifdef USE_MINI_HT
cf95b4f0 5138 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5139 int temp=-1; // note: must be ds-safe
5140 #ifdef HOST_TEMPREG
5141 temp=HOST_TEMPREG;
5142 #endif
5143 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5144 else emit_movimm(return_address,rt);
5145 }
5146 else
5147 #endif
5148 {
5149 #ifdef REG_PREFETCH
9f51b4b9 5150 if(temp>=0)
eba830cd 5151 {
643aeae3 5152 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5153 }
5154 #endif
5155 emit_movimm(return_address,rt); // PC into link register
5156 #ifdef IMM_PREFETCH
df4dc2b1 5157 emit_prefetch(hash_table_get(return_address));
eba830cd 5158 #endif
5159 }
5160 }
5161}
5162
2330734f 5163static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5164{
eba830cd 5165 int ra_done=0;
57871462 5166 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5167 address_generation(i+1,i_regs,regs[i].regmap_entry);
5168 #ifdef REG_PREFETCH
5169 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5170 if(dops[i].rt1==31&&temp>=0)
57871462 5171 {
581335b0 5172 signed char *i_regmap=i_regs->regmap;
57871462 5173 int return_address=start+i*4+8;
9f51b4b9 5174 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5175 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5176 }
5177 #endif
cf95b4f0 5178 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5179 ujump_assemble_write_ra(i); // writeback ra for DS
5180 ra_done=1;
57871462 5181 }
4ef8f67d 5182 ds_assemble(i+1,i_regs);
5183 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5184 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5185 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5186 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5187 if(!ra_done&&dops[i].rt1==31)
eba830cd 5188 ujump_assemble_write_ra(i);
57871462 5189 int cc,adj;
5190 cc=get_reg(branch_regs[i].regmap,CCREG);
5191 assert(cc==HOST_CCREG);
ad49de89 5192 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5193 #ifdef REG_PREFETCH
cf95b4f0 5194 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5195 #endif
5196 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5197 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5198 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5199 if(internal_branch(ba[i]))
57871462 5200 assem_debug("branch: internal\n");
5201 else
5202 assem_debug("branch: external\n");
cf95b4f0 5203 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5204 ds_assemble_entry(i);
5205 }
5206 else {
ad49de89 5207 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5208 emit_jmp(0);
5209 }
5210}
5211
eba830cd 5212static void rjump_assemble_write_ra(int i)
5213{
5214 int rt,return_address;
cf95b4f0 5215 assert(dops[i+1].rt1!=dops[i].rt1);
5216 assert(dops[i+1].rt2!=dops[i].rt1);
5217 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5218 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5219 assert(rt>=0);
5220 return_address=start+i*4+8;
5221 #ifdef REG_PREFETCH
9f51b4b9 5222 if(temp>=0)
eba830cd 5223 {
643aeae3 5224 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5225 }
5226 #endif
5227 emit_movimm(return_address,rt); // PC into link register
5228 #ifdef IMM_PREFETCH
df4dc2b1 5229 emit_prefetch(hash_table_get(return_address));
eba830cd 5230 #endif
5231}
5232
2330734f 5233static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5234{
57871462 5235 int temp;
581335b0 5236 int rs,cc;
eba830cd 5237 int ra_done=0;
cf95b4f0 5238 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5239 assert(rs>=0);
4919de1e 5240 if (ds_writes_rjump_rs(i)) {
57871462 5241 // Delay slot abuse, make a copy of the branch address register
5242 temp=get_reg(branch_regs[i].regmap,RTEMP);
5243 assert(temp>=0);
5244 assert(regs[i].regmap[temp]==RTEMP);
5245 emit_mov(rs,temp);
5246 rs=temp;
5247 }
5248 address_generation(i+1,i_regs,regs[i].regmap_entry);
5249 #ifdef REG_PREFETCH
cf95b4f0 5250 if(dops[i].rt1==31)
57871462 5251 {
5252 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5253 signed char *i_regmap=i_regs->regmap;
57871462 5254 int return_address=start+i*4+8;
643aeae3 5255 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5256 }
5257 }
5258 #endif
5259 #ifdef USE_MINI_HT
cf95b4f0 5260 if(dops[i].rs1==31) {
57871462 5261 int rh=get_reg(regs[i].regmap,RHASH);
5262 if(rh>=0) do_preload_rhash(rh);
5263 }
5264 #endif
cf95b4f0 5265 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5266 rjump_assemble_write_ra(i);
5267 ra_done=1;
57871462 5268 }
d5910d5d 5269 ds_assemble(i+1,i_regs);
5270 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5271 bc_unneeded|=1|(1LL<<dops[i].rt1);
5272 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5273 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5274 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5275 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5276 rjump_assemble_write_ra(i);
57871462 5277 cc=get_reg(branch_regs[i].regmap,CCREG);
5278 assert(cc==HOST_CCREG);
581335b0 5279 (void)cc;
57871462 5280 #ifdef USE_MINI_HT
5281 int rh=get_reg(branch_regs[i].regmap,RHASH);
5282 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5283 if(dops[i].rs1==31) {
57871462 5284 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5285 do_preload_rhtbl(ht);
5286 do_rhash(rs,rh);
5287 }
5288 #endif
ad49de89 5289 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5290 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5291 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5292 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5293 emit_loadreg(dops[i].rs1,rs);
57871462 5294 }
5295 }
5296 #endif
5297 #ifdef REG_PREFETCH
cf95b4f0 5298 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5299 #endif
5300 #ifdef USE_MINI_HT
cf95b4f0 5301 if(dops[i].rs1==31) {
57871462 5302 do_miniht_load(ht,rh);
5303 }
5304 #endif
5305 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5306 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5307 //assert(adj==0);
2330734f 5308 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5309 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5310 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5311 // special case for RFE
5312 emit_jmp(0);
5313 else
71e490c5 5314 emit_jns(0);
ad49de89 5315 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5316 #ifdef USE_MINI_HT
cf95b4f0 5317 if(dops[i].rs1==31) {
57871462 5318 do_miniht_jump(rs,rh,ht);
5319 }
5320 else
5321 #endif
5322 {
d1e4ebd9 5323 do_jump_vaddr(rs);
57871462 5324 }
57871462 5325 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5326 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5327 #endif
5328}
5329
2330734f 5330static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5331{
2330734f 5332 const signed char *i_regmap = i_regs->regmap;
57871462 5333 int cc;
5334 int match;
ad49de89 5335 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5336 assem_debug("match=%d\n",match);
ad49de89 5337 int s1l,s2l;
57871462 5338 int unconditional=0,nop=0;
57871462 5339 int invert=0;
ad49de89 5340 int internal=internal_branch(ba[i]);
57871462 5341 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5342 if(!match) invert=1;
5343 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5344 if(i>(ba[i]-start)>>2) invert=1;
5345 #endif
3968e69e 5346 #ifdef __aarch64__
5347 invert=1; // because of near cond. branches
5348 #endif
9f51b4b9 5349
cf95b4f0 5350 if(dops[i].ooo) {
5351 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5352 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5353 }
5354 else {
cf95b4f0 5355 s1l=get_reg(i_regmap,dops[i].rs1);
5356 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5357 }
cf95b4f0 5358 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5359 {
cf95b4f0 5360 if(dops[i].opcode&1) nop=1;
57871462 5361 else unconditional=1;
cf95b4f0 5362 //assert(dops[i].opcode!=5);
5363 //assert(dops[i].opcode!=7);
5364 //assert(dops[i].opcode!=0x15);
5365 //assert(dops[i].opcode!=0x17);
57871462 5366 }
cf95b4f0 5367 else if(dops[i].rs1==0)
57871462 5368 {
ad49de89 5369 s1l=s2l;
5370 s2l=-1;
57871462 5371 }
cf95b4f0 5372 else if(dops[i].rs2==0)
57871462 5373 {
ad49de89 5374 s2l=-1;
57871462 5375 }
5376
cf95b4f0 5377 if(dops[i].ooo) {
57871462 5378 // Out of order execution (delay slot first)
5379 //printf("OOOE\n");
5380 address_generation(i+1,i_regs,regs[i].regmap_entry);
5381 ds_assemble(i+1,i_regs);
5382 int adj;
5383 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5384 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5385 bc_unneeded|=1;
ad49de89 5386 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5387 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5388 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5389 cc=get_reg(branch_regs[i].regmap,CCREG);
5390 assert(cc==HOST_CCREG);
9f51b4b9 5391 if(unconditional)
ad49de89 5392 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5393 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5394 //assem_debug("cycle count (adj)\n");
5395 if(unconditional) {
5396 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5397 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5398 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5399 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5400 if(internal)
5401 assem_debug("branch: internal\n");
5402 else
5403 assem_debug("branch: external\n");
cf95b4f0 5404 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5405 ds_assemble_entry(i);
5406 }
5407 else {
643aeae3 5408 add_to_linker(out,ba[i],internal);
57871462 5409 emit_jmp(0);
5410 }
5411 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5412 if(((u_int)out)&7) emit_addnop(0);
5413 #endif
5414 }
5415 }
5416 else if(nop) {
2330734f 5417 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5418 void *jaddr=out;
57871462 5419 emit_jns(0);
b14b6a8f 5420 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5421 }
5422 else {
df4dc2b1 5423 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5424 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5425 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5426
57871462 5427 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5428 assert(s1l>=0);
cf95b4f0 5429 if(dops[i].opcode==4) // BEQ
57871462 5430 {
5431 if(s2l>=0) emit_cmp(s1l,s2l);
5432 else emit_test(s1l,s1l);
5433 if(invert){
df4dc2b1 5434 nottaken=out;
7c3a5182 5435 emit_jne(DJT_1);
57871462 5436 }else{
643aeae3 5437 add_to_linker(out,ba[i],internal);
57871462 5438 emit_jeq(0);
5439 }
5440 }
cf95b4f0 5441 if(dops[i].opcode==5) // BNE
57871462 5442 {
5443 if(s2l>=0) emit_cmp(s1l,s2l);
5444 else emit_test(s1l,s1l);
5445 if(invert){
df4dc2b1 5446 nottaken=out;
7c3a5182 5447 emit_jeq(DJT_1);
57871462 5448 }else{
643aeae3 5449 add_to_linker(out,ba[i],internal);
57871462 5450 emit_jne(0);
5451 }
5452 }
cf95b4f0 5453 if(dops[i].opcode==6) // BLEZ
57871462 5454 {
5455 emit_cmpimm(s1l,1);
5456 if(invert){
df4dc2b1 5457 nottaken=out;
7c3a5182 5458 emit_jge(DJT_1);
57871462 5459 }else{
643aeae3 5460 add_to_linker(out,ba[i],internal);
57871462 5461 emit_jl(0);
5462 }
5463 }
cf95b4f0 5464 if(dops[i].opcode==7) // BGTZ
57871462 5465 {
5466 emit_cmpimm(s1l,1);
5467 if(invert){
df4dc2b1 5468 nottaken=out;
7c3a5182 5469 emit_jl(DJT_1);
57871462 5470 }else{
643aeae3 5471 add_to_linker(out,ba[i],internal);
57871462 5472 emit_jge(0);
5473 }
5474 }
5475 if(invert) {
df4dc2b1 5476 if(taken) set_jump_target(taken, out);
57871462 5477 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5478 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5479 if(adj) {
2330734f 5480 emit_addimm(cc,-adj,cc);
643aeae3 5481 add_to_linker(out,ba[i],internal);
57871462 5482 }else{
5483 emit_addnop(13);
643aeae3 5484 add_to_linker(out,ba[i],internal*2);
57871462 5485 }
5486 emit_jmp(0);
5487 }else
5488 #endif
5489 {
2330734f 5490 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5491 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5492 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5493 if(internal)
5494 assem_debug("branch: internal\n");
5495 else
5496 assem_debug("branch: external\n");
cf95b4f0 5497 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5498 ds_assemble_entry(i);
5499 }
5500 else {
643aeae3 5501 add_to_linker(out,ba[i],internal);
57871462 5502 emit_jmp(0);
5503 }
5504 }
df4dc2b1 5505 set_jump_target(nottaken, out);
57871462 5506 }
5507
df4dc2b1 5508 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5509 if(adj) {
2330734f 5510 if(!invert) emit_addimm(cc,adj,cc);
57871462 5511 }
5512 } // (!unconditional)
5513 } // if(ooo)
5514 else
5515 {
5516 // In-order execution (branch first)
df4dc2b1 5517 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5518 if(!unconditional&&!nop) {
57871462 5519 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5520 assert(s1l>=0);
cf95b4f0 5521 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5522 {
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
df4dc2b1 5525 nottaken=out;
7c3a5182 5526 emit_jne(DJT_2);
57871462 5527 }
cf95b4f0 5528 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5529 {
5530 if(s2l>=0) emit_cmp(s1l,s2l);
5531 else emit_test(s1l,s1l);
df4dc2b1 5532 nottaken=out;
7c3a5182 5533 emit_jeq(DJT_2);
57871462 5534 }
cf95b4f0 5535 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5536 {
5537 emit_cmpimm(s1l,1);
df4dc2b1 5538 nottaken=out;
7c3a5182 5539 emit_jge(DJT_2);
57871462 5540 }
cf95b4f0 5541 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5542 {
5543 emit_cmpimm(s1l,1);
df4dc2b1 5544 nottaken=out;
7c3a5182 5545 emit_jl(DJT_2);
57871462 5546 }
5547 } // if(!unconditional)
5548 int adj;
5549 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5550 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5551 ds_unneeded|=1;
57871462 5552 // branch taken
5553 if(!nop) {
df4dc2b1 5554 if(taken) set_jump_target(taken, out);
57871462 5555 assem_debug("1:\n");
ad49de89 5556 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5557 // load regs
cf95b4f0 5558 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5559 address_generation(i+1,&branch_regs[i],0);
37387d8b 5560 if (ram_offset)
5561 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5562 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5563 ds_assemble(i+1,&branch_regs[i]);
5564 cc=get_reg(branch_regs[i].regmap,CCREG);
5565 if(cc==-1) {
5566 emit_loadreg(CCREG,cc=HOST_CCREG);
5567 // CHECK: Is the following instruction (fall thru) allocated ok?
5568 }
5569 assert(cc==HOST_CCREG);
ad49de89 5570 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5571 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5572 assem_debug("cycle count (adj)\n");
2330734f 5573 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5574 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5575 if(internal)
5576 assem_debug("branch: internal\n");
5577 else
5578 assem_debug("branch: external\n");
cf95b4f0 5579 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5580 ds_assemble_entry(i);
5581 }
5582 else {
643aeae3 5583 add_to_linker(out,ba[i],internal);
57871462 5584 emit_jmp(0);
5585 }
5586 }
5587 // branch not taken
57871462 5588 if(!unconditional) {
df4dc2b1 5589 if(nottaken1) set_jump_target(nottaken1, out);
5590 set_jump_target(nottaken, out);
57871462 5591 assem_debug("2:\n");
fe807a8a 5592 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5593 // load regs
fe807a8a 5594 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5595 address_generation(i+1,&branch_regs[i],0);
37387d8b 5596 if (ram_offset)
5597 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5598 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5599 ds_assemble(i+1,&branch_regs[i]);
57871462 5600 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5601 if (cc == -1) {
57871462 5602 // Cycle count isn't in a register, temporarily load it then write it out
5603 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5604 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5605 void *jaddr=out;
57871462 5606 emit_jns(0);
b14b6a8f 5607 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5608 emit_storereg(CCREG,HOST_CCREG);
5609 }
5610 else{
5611 cc=get_reg(i_regmap,CCREG);
5612 assert(cc==HOST_CCREG);
2330734f 5613 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5614 void *jaddr=out;
57871462 5615 emit_jns(0);
fe807a8a 5616 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5617 }
5618 }
5619 }
5620}
5621
2330734f 5622static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5623{
2330734f 5624 const signed char *i_regmap = i_regs->regmap;
57871462 5625 int cc;
5626 int match;
ad49de89 5627 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
2acc46cd 5628 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
ad49de89 5629 int s1l;
57871462 5630 int unconditional=0,nevertaken=0;
57871462 5631 int invert=0;
ad49de89 5632 int internal=internal_branch(ba[i]);
57871462 5633 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5634 if(!match) invert=1;
5635 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5636 if(i>(ba[i]-start)>>2) invert=1;
5637 #endif
3968e69e 5638 #ifdef __aarch64__
5639 invert=1; // because of near cond. branches
5640 #endif
57871462 5641
cf95b4f0 5642 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5643 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5644
cf95b4f0 5645 if(dops[i].ooo) {
5646 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5647 }
5648 else {
cf95b4f0 5649 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5650 }
cf95b4f0 5651 if(dops[i].rs1==0)
57871462 5652 {
cf95b4f0 5653 if(dops[i].opcode2&1) unconditional=1;
57871462 5654 else nevertaken=1;
5655 // These are never taken (r0 is never less than zero)
cf95b4f0 5656 //assert(dops[i].opcode2!=0);
5657 //assert(dops[i].opcode2!=2);
5658 //assert(dops[i].opcode2!=0x10);
5659 //assert(dops[i].opcode2!=0x12);
57871462 5660 }
57871462 5661
cf95b4f0 5662 if(dops[i].ooo) {
57871462 5663 // Out of order execution (delay slot first)
5664 //printf("OOOE\n");
5665 address_generation(i+1,i_regs,regs[i].regmap_entry);
5666 ds_assemble(i+1,i_regs);
5667 int adj;
5668 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5669 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5670 bc_unneeded|=1;
ad49de89 5671 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5672 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5673 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5674 if(dops[i].rt1==31) {
57871462 5675 int rt,return_address;
57871462 5676 rt=get_reg(branch_regs[i].regmap,31);
5677 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5678 if(rt>=0) {
5679 // Save the PC even if the branch is not taken
5680 return_address=start+i*4+8;
5681 emit_movimm(return_address,rt); // PC into link register
5682 #ifdef IMM_PREFETCH
df4dc2b1 5683 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5684 #endif
5685 }
5686 }
5687 cc=get_reg(branch_regs[i].regmap,CCREG);
5688 assert(cc==HOST_CCREG);
9f51b4b9 5689 if(unconditional)
ad49de89 5690 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5691 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5692 assem_debug("cycle count (adj)\n");
5693 if(unconditional) {
5694 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5695 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5696 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5697 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5698 if(internal)
5699 assem_debug("branch: internal\n");
5700 else
5701 assem_debug("branch: external\n");
cf95b4f0 5702 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5703 ds_assemble_entry(i);
5704 }
5705 else {
643aeae3 5706 add_to_linker(out,ba[i],internal);
57871462 5707 emit_jmp(0);
5708 }
5709 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5710 if(((u_int)out)&7) emit_addnop(0);
5711 #endif
5712 }
5713 }
5714 else if(nevertaken) {
2330734f 5715 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5716 void *jaddr=out;
57871462 5717 emit_jns(0);
b14b6a8f 5718 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5719 }
5720 else {
df4dc2b1 5721 void *nottaken = NULL;
57871462 5722 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5723 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5724 {
5725 assert(s1l>=0);
cf95b4f0 5726 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5727 {
5728 emit_test(s1l,s1l);
5729 if(invert){
df4dc2b1 5730 nottaken=out;
7c3a5182 5731 emit_jns(DJT_1);
57871462 5732 }else{
643aeae3 5733 add_to_linker(out,ba[i],internal);
57871462 5734 emit_js(0);
5735 }
5736 }
cf95b4f0 5737 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5738 {
5739 emit_test(s1l,s1l);
5740 if(invert){
df4dc2b1 5741 nottaken=out;
7c3a5182 5742 emit_js(DJT_1);
57871462 5743 }else{
643aeae3 5744 add_to_linker(out,ba[i],internal);
57871462 5745 emit_jns(0);
5746 }
5747 }
ad49de89 5748 }
9f51b4b9 5749
57871462 5750 if(invert) {
5751 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5752 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5753 if(adj) {
2330734f 5754 emit_addimm(cc,-adj,cc);
643aeae3 5755 add_to_linker(out,ba[i],internal);
57871462 5756 }else{
5757 emit_addnop(13);
643aeae3 5758 add_to_linker(out,ba[i],internal*2);
57871462 5759 }
5760 emit_jmp(0);
5761 }else
5762 #endif
5763 {
2330734f 5764 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5766 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5767 if(internal)
5768 assem_debug("branch: internal\n");
5769 else
5770 assem_debug("branch: external\n");
cf95b4f0 5771 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5772 ds_assemble_entry(i);
5773 }
5774 else {
643aeae3 5775 add_to_linker(out,ba[i],internal);
57871462 5776 emit_jmp(0);
5777 }
5778 }
df4dc2b1 5779 set_jump_target(nottaken, out);
57871462 5780 }
5781
5782 if(adj) {
2330734f 5783 if(!invert) emit_addimm(cc,adj,cc);
57871462 5784 }
5785 } // (!unconditional)
5786 } // if(ooo)
5787 else
5788 {
5789 // In-order execution (branch first)
5790 //printf("IOE\n");
df4dc2b1 5791 void *nottaken = NULL;
cf95b4f0 5792 if(dops[i].rt1==31) {
a6491170 5793 int rt,return_address;
a6491170 5794 rt=get_reg(branch_regs[i].regmap,31);
5795 if(rt>=0) {
5796 // Save the PC even if the branch is not taken
5797 return_address=start+i*4+8;
5798 emit_movimm(return_address,rt); // PC into link register
5799 #ifdef IMM_PREFETCH
df4dc2b1 5800 emit_prefetch(hash_table_get(return_address));
a6491170 5801 #endif
5802 }
5803 }
57871462 5804 if(!unconditional) {
5805 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5806 assert(s1l>=0);
cf95b4f0 5807 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5808 {
5809 emit_test(s1l,s1l);
df4dc2b1 5810 nottaken=out;
7c3a5182 5811 emit_jns(DJT_1);
57871462 5812 }
cf95b4f0 5813 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5814 {
5815 emit_test(s1l,s1l);
df4dc2b1 5816 nottaken=out;
7c3a5182 5817 emit_js(DJT_1);
57871462 5818 }
57871462 5819 } // if(!unconditional)
5820 int adj;
5821 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5822 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5823 ds_unneeded|=1;
57871462 5824 // branch taken
5825 if(!nevertaken) {
5826 //assem_debug("1:\n");
ad49de89 5827 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5828 // load regs
cf95b4f0 5829 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5830 address_generation(i+1,&branch_regs[i],0);
37387d8b 5831 if (ram_offset)
5832 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5833 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5834 ds_assemble(i+1,&branch_regs[i]);
5835 cc=get_reg(branch_regs[i].regmap,CCREG);
5836 if(cc==-1) {
5837 emit_loadreg(CCREG,cc=HOST_CCREG);
5838 // CHECK: Is the following instruction (fall thru) allocated ok?
5839 }
5840 assert(cc==HOST_CCREG);
ad49de89 5841 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5842 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5843 assem_debug("cycle count (adj)\n");
2330734f 5844 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5845 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5846 if(internal)
5847 assem_debug("branch: internal\n");
5848 else
5849 assem_debug("branch: external\n");
cf95b4f0 5850 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5851 ds_assemble_entry(i);
5852 }
5853 else {
643aeae3 5854 add_to_linker(out,ba[i],internal);
57871462 5855 emit_jmp(0);
5856 }
5857 }
5858 // branch not taken
57871462 5859 if(!unconditional) {
df4dc2b1 5860 set_jump_target(nottaken, out);
57871462 5861 assem_debug("1:\n");
fe807a8a 5862 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5863 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5864 address_generation(i+1,&branch_regs[i],0);
5a18ce2e 5865 if (ram_offset)
5866 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5867 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5868 ds_assemble(i+1,&branch_regs[i]);
57871462 5869 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5870 if (cc == -1) {
57871462 5871 // Cycle count isn't in a register, temporarily load it then write it out
5872 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5873 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5874 void *jaddr=out;
57871462 5875 emit_jns(0);
b14b6a8f 5876 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5877 emit_storereg(CCREG,HOST_CCREG);
5878 }
5879 else{
5880 cc=get_reg(i_regmap,CCREG);
5881 assert(cc==HOST_CCREG);
2330734f 5882 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5883 void *jaddr=out;
57871462 5884 emit_jns(0);
fe807a8a 5885 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5886 }
5887 }
5888 }
5889}
5890
2330734f 5891static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5892{
cf95b4f0 5893 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5894 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5895 void *taken = NULL;
5896 void *nottaken = NULL;
57871462 5897 int unconditional=0;
cf95b4f0 5898 if(dops[i].rs1==0)
57871462 5899 {
ad49de89 5900 s1l=s2l;
5901 s2l=-1;
57871462 5902 }
cf95b4f0 5903 else if(dops[i].rs2==0)
57871462 5904 {
ad49de89 5905 s2l=-1;
57871462 5906 }
5907 int hr=0;
581335b0 5908 int addr=-1,alt=-1,ntaddr=-1;
57871462 5909 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5910 else {
5911 while(hr<HOST_REGS)
5912 {
5913 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
9de8a0c3 5914 i_regs->regmap[hr]!=dops[i].rs1 &&
5915 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5916 {
5917 addr=hr++;break;
5918 }
5919 hr++;
5920 }
5921 }
5922 while(hr<HOST_REGS)
5923 {
5924 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
9de8a0c3 5925 i_regs->regmap[hr]!=dops[i].rs1 &&
5926 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5927 {
5928 alt=hr++;break;
5929 }
5930 hr++;
5931 }
cf95b4f0 5932 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5933 {
5934 while(hr<HOST_REGS)
5935 {
5936 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
9de8a0c3 5937 i_regs->regmap[hr]!=dops[i].rs1 &&
5938 i_regs->regmap[hr]!=dops[i].rs2 )
57871462 5939 {
5940 ntaddr=hr;break;
5941 }
5942 hr++;
5943 }
5944 }
5945 assert(hr<HOST_REGS);
cf95b4f0 5946 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5947 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5948 }
2330734f 5949 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5950 if(dops[i].opcode==2) // J
57871462 5951 {
5952 unconditional=1;
5953 }
cf95b4f0 5954 if(dops[i].opcode==3) // JAL
57871462 5955 {
5956 // TODO: mini_ht
5957 int rt=get_reg(i_regs->regmap,31);
5958 emit_movimm(start+i*4+8,rt);
5959 unconditional=1;
5960 }
cf95b4f0 5961 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5962 {
5963 emit_mov(s1l,addr);
cf95b4f0 5964 if(dops[i].opcode2==9) // JALR
57871462 5965 {
cf95b4f0 5966 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5967 emit_movimm(start+i*4+8,rt);
5968 }
5969 }
cf95b4f0 5970 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5971 {
cf95b4f0 5972 if(dops[i].rs1==dops[i].rs2)
57871462 5973 {
5974 unconditional=1;
5975 }
5976 else
5977 #ifdef HAVE_CMOV_IMM
ad49de89 5978 if(1) {
57871462 5979 if(s2l>=0) emit_cmp(s1l,s2l);
5980 else emit_test(s1l,s1l);
5981 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5982 }
5983 else
5984 #endif
5985 {
5986 assert(s1l>=0);
5987 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5988 if(s2l>=0) emit_cmp(s1l,s2l);
5989 else emit_test(s1l,s1l);
5990 emit_cmovne_reg(alt,addr);
5991 }
5992 }
cf95b4f0 5993 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5994 {
5995 #ifdef HAVE_CMOV_IMM
ad49de89 5996 if(s2l>=0) emit_cmp(s1l,s2l);
5997 else emit_test(s1l,s1l);
5998 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5999 #else
6000 assert(s1l>=0);
6001 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6002 if(s2l>=0) emit_cmp(s1l,s2l);
6003 else emit_test(s1l,s1l);
6004 emit_cmovne_reg(alt,addr);
57871462 6005 #endif
57871462 6006 }
cf95b4f0 6007 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 6008 {
57871462 6009 if(s2l>=0) emit_cmp(s1l,s2l);
6010 else emit_test(s1l,s1l);
df4dc2b1 6011 if(nottaken) set_jump_target(nottaken, out);
6012 nottaken=out;
57871462 6013 emit_jne(0);
6014 }
cf95b4f0 6015 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 6016 {
57871462 6017 if(s2l>=0) emit_cmp(s1l,s2l);
6018 else emit_test(s1l,s1l);
df4dc2b1 6019 nottaken=out;
57871462 6020 emit_jeq(0);
df4dc2b1 6021 if(taken) set_jump_target(taken, out);
57871462 6022 }
cf95b4f0 6023 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 6024 {
6025 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6026 emit_cmpimm(s1l,1);
57871462 6027 emit_cmovl_reg(alt,addr);
57871462 6028 }
cf95b4f0 6029 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 6030 {
6031 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6032 emit_cmpimm(s1l,1);
57871462 6033 emit_cmovl_reg(ntaddr,addr);
57871462 6034 }
cf95b4f0 6035 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 6036 {
cf95b4f0 6037 assert((dops[i].opcode&0x3f)!=0x16);
57871462 6038 }
cf95b4f0 6039 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6040 {
cf95b4f0 6041 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6042 }
cf95b4f0 6043 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6044
6045 //FIXME: Check CSREG
cf95b4f0 6046 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6047 if((source[i]&0x30000)==0) // BC1F
6048 {
6049 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6050 emit_testimm(s1l,0x800000);
6051 emit_cmovne_reg(alt,addr);
6052 }
6053 if((source[i]&0x30000)==0x10000) // BC1T
6054 {
6055 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6056 emit_testimm(s1l,0x800000);
6057 emit_cmovne_reg(alt,addr);
6058 }
6059 if((source[i]&0x30000)==0x20000) // BC1FL
6060 {
6061 emit_testimm(s1l,0x800000);
df4dc2b1 6062 nottaken=out;
57871462 6063 emit_jne(0);
6064 }
6065 if((source[i]&0x30000)==0x30000) // BC1TL
6066 {
6067 emit_testimm(s1l,0x800000);
df4dc2b1 6068 nottaken=out;
57871462 6069 emit_jeq(0);
6070 }
6071 }
6072
6073 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6074 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6075 if(unconditional)
57871462 6076 {
6077 emit_movimm(ba[i],HOST_BTREG);
6078 }
6079 else if(addr!=HOST_BTREG)
6080 {
6081 emit_mov(addr,HOST_BTREG);
6082 }
6083 void *branch_addr=out;
6084 emit_jmp(0);
6085 int target_addr=start+i*4+5;
6086 void *stub=out;
6087 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6088 emit_extjump_ds(branch_addr, target_addr);
57871462 6089 if(compiled_target_addr) {
df4dc2b1 6090 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6091 add_jump_out(target_addr,stub);
57871462 6092 }
df4dc2b1 6093 else set_jump_target(branch_addr, stub);
57871462 6094}
6095
6096// Assemble the delay slot for the above
6097static void pagespan_ds()
6098{
6099 assem_debug("initial delay slot:\n");
6100 u_int vaddr=start+1;
94d23bb9 6101 u_int page=get_page(vaddr);
6102 u_int vpage=get_vpage(vaddr);
57871462 6103 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6104 do_dirty_stub_ds(slen*4);
57871462 6105 ll_add(jump_in+page,vaddr,(void *)out);
6106 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6107 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6108 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6109 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6110 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6111 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6112 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6113 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6114 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6115 if (dops[0].is_store)
ad49de89 6116 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6117 is_delayslot=0;
2330734f 6118 switch (dops[0].itype) {
57871462 6119 case SYSCALL:
7139f3c8 6120 case HLECALL:
1e973cb0 6121 case INTCALL:
57871462 6122 case SPAN:
6123 case UJUMP:
6124 case RJUMP:
6125 case CJUMP:
6126 case SJUMP:
c43b5311 6127 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6128 break;
6129 default:
6130 assemble(0, &regs[0], 0);
57871462 6131 }
6132 int btaddr=get_reg(regs[0].regmap,BTREG);
6133 if(btaddr<0) {
9de8a0c3 6134 btaddr=get_reg_temp(regs[0].regmap);
643aeae3 6135 emit_readword(&branch_target,btaddr);
57871462 6136 }
6137 assert(btaddr!=HOST_CCREG);
6138 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6139#ifdef HOST_IMM8
d1e4ebd9 6140 host_tempreg_acquire();
57871462 6141 emit_movimm(start+4,HOST_TEMPREG);
6142 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6143 host_tempreg_release();
57871462 6144#else
6145 emit_cmpimm(btaddr,start+4);
6146#endif
df4dc2b1 6147 void *branch = out;
57871462 6148 emit_jeq(0);
ad49de89 6149 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6150 do_jump_vaddr(btaddr);
df4dc2b1 6151 set_jump_target(branch, out);
ad49de89 6152 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6153 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6154}
6155
670c0f22 6156static void check_regmap(signed char *regmap)
6157{
6158#ifndef NDEBUG
6159 int i,j;
6160 for (i = 0; i < HOST_REGS; i++) {
6161 if (regmap[i] < 0)
6162 continue;
6163 for (j = i + 1; j < HOST_REGS; j++)
6164 assert(regmap[i] != regmap[j]);
6165 }
6166#endif
6167}
6168
57871462 6169// Basic liveness analysis for MIPS registers
670c0f22 6170static void unneeded_registers(int istart,int iend,int r)
57871462 6171{
6172 int i;
00fa9369 6173 uint64_t u,gte_u,b,gte_b;
6174 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6175 uint64_t gte_u_unknown=0;
d62c125a 6176 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6177 gte_u_unknown=~0ll;
57871462 6178 if(iend==slen-1) {
00fa9369 6179 u=1;
0ff8c62c 6180 gte_u=gte_u_unknown;
57871462 6181 }else{
00fa9369 6182 //u=unneeded_reg[iend+1];
6183 u=1;
0ff8c62c 6184 gte_u=gte_unneeded[iend+1];
57871462 6185 }
bedfea38 6186
57871462 6187 for (i=iend;i>=istart;i--)
6188 {
6189 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6190 if(dops[i].is_jump)
57871462 6191 {
6192 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6193 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6194
57871462 6195 if(ba[i]<start || ba[i]>=(start+slen*4))
6196 {
6197 // Branch out of this block, flush all regs
6198 u=1;
0ff8c62c 6199 gte_u=gte_u_unknown;
57871462 6200 branch_unneeded_reg[i]=u;
57871462 6201 // Merge in delay slot
cf95b4f0 6202 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6203 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6204 u|=1;
bedfea38 6205 gte_u|=gte_rt[i+1];
6206 gte_u&=~gte_rs[i+1];
57871462 6207 }
6208 else
6209 {
6210 // Internal branch, flag target
cf95b4f0 6211 dops[(ba[i]-start)>>2].bt=1;
57871462 6212 if(ba[i]<=start+i*4) {
6213 // Backward branch
fe807a8a 6214 if(dops[i].is_ujump)
57871462 6215 {
6216 // Unconditional branch
00fa9369 6217 temp_u=1;
bedfea38 6218 temp_gte_u=0;
57871462 6219 } else {
6220 // Conditional branch (not taken case)
6221 temp_u=unneeded_reg[i+2];
bedfea38 6222 temp_gte_u&=gte_unneeded[i+2];
57871462 6223 }
6224 // Merge in delay slot
cf95b4f0 6225 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6226 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6227 temp_u|=1;
bedfea38 6228 temp_gte_u|=gte_rt[i+1];
6229 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6230 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6231 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6232 temp_u|=1;
bedfea38 6233 temp_gte_u|=gte_rt[i];
6234 temp_gte_u&=~gte_rs[i];
57871462 6235 unneeded_reg[i]=temp_u;
bedfea38 6236 gte_unneeded[i]=temp_gte_u;
57871462 6237 // Only go three levels deep. This recursion can take an
6238 // excessive amount of time if there are a lot of nested loops.
6239 if(r<2) {
6240 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6241 }else{
6242 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6243 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6244 }
6245 } /*else*/ if(1) {
fe807a8a 6246 if (dops[i].is_ujump)
57871462 6247 {
6248 // Unconditional branch
6249 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6250 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6251 branch_unneeded_reg[i]=u;
57871462 6252 // Merge in delay slot
cf95b4f0 6253 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6254 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6255 u|=1;
bedfea38 6256 gte_u|=gte_rt[i+1];
6257 gte_u&=~gte_rs[i+1];
57871462 6258 } else {
6259 // Conditional branch
6260 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6261 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6262 branch_unneeded_reg[i]=b;
57871462 6263 // Branch delay slot
cf95b4f0 6264 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6265 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6266 b|=1;
6267 gte_b|=gte_rt[i+1];
6268 gte_b&=~gte_rs[i+1];
fe807a8a 6269 u&=b;
6270 gte_u&=gte_b;
57871462 6271 if(i<slen-1) {
6272 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6273 } else {
6274 branch_unneeded_reg[i]=1;
57871462 6275 }
6276 }
6277 }
6278 }
6279 }
cf95b4f0 6280 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6281 {
6282 // SYSCALL instruction (software interrupt)
6283 u=1;
57871462 6284 }
cf95b4f0 6285 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6286 {
6287 // ERET instruction (return from interrupt)
6288 u=1;
57871462 6289 }
00fa9369 6290 //u=1; // DEBUG
57871462 6291 // Written registers are unneeded
cf95b4f0 6292 u|=1LL<<dops[i].rt1;
6293 u|=1LL<<dops[i].rt2;
bedfea38 6294 gte_u|=gte_rt[i];
57871462 6295 // Accessed registers are needed
cf95b4f0 6296 u&=~(1LL<<dops[i].rs1);
6297 u&=~(1LL<<dops[i].rs2);
bedfea38 6298 gte_u&=~gte_rs[i];
cf95b4f0 6299 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6300 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6301 // Source-target dependencies
57871462 6302 // R0 is always unneeded
00fa9369 6303 u|=1;
57871462 6304 // Save it
6305 unneeded_reg[i]=u;
bedfea38 6306 gte_unneeded[i]=gte_u;
57871462 6307 /*
6308 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6309 printf("U:");
6310 int r;
6311 for(r=1;r<=CCREG;r++) {
6312 if((unneeded_reg[i]>>r)&1) {
6313 if(r==HIREG) printf(" HI");
6314 else if(r==LOREG) printf(" LO");
6315 else printf(" r%d",r);
6316 }
6317 }
00fa9369 6318 printf("\n");
6319 */
252c20fc 6320 }
57871462 6321}
6322
71e490c5 6323// Write back dirty registers as soon as we will no longer modify them,
6324// so that we don't end up with lots of writes at the branches.
6325void clean_registers(int istart,int iend,int wr)
57871462 6326{
71e490c5 6327 int i;
6328 int r;
6329 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6330 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6331 if(iend==slen-1) {
6332 will_dirty_i=will_dirty_next=0;
6333 wont_dirty_i=wont_dirty_next=0;
6334 }else{
6335 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6336 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6337 }
6338 for (i=iend;i>=istart;i--)
57871462 6339 {
9de8a0c3 6340 __builtin_prefetch(regs[i-1].regmap);
fe807a8a 6341 if(dops[i].is_jump)
57871462 6342 {
71e490c5 6343 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6344 {
71e490c5 6345 // Branch out of this block, flush all regs
fe807a8a 6346 if (dops[i].is_ujump)
57871462 6347 {
6348 // Unconditional branch
6349 will_dirty_i=0;
6350 wont_dirty_i=0;
6351 // Merge in delay slot (will dirty)
6352 for(r=0;r<HOST_REGS;r++) {
6353 if(r!=EXCLUDE_REG) {
9de8a0c3 6354 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6355 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6356 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6357 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6358 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6359 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6360 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
9de8a0c3 6361 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6362 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6363 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6364 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6365 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6366 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6367 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6368 }
6369 }
6370 }
6371 else
6372 {
6373 // Conditional branch
6374 will_dirty_i=0;
6375 wont_dirty_i=wont_dirty_next;
6376 // Merge in delay slot (will dirty)
6377 for(r=0;r<HOST_REGS;r++) {
6378 if(r!=EXCLUDE_REG) {
9de8a0c3 6379 if (1) { // !dops[i].likely)
57871462 6380 // Might not dirty if likely branch is not taken
9de8a0c3 6381 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6382 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6383 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6384 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6385 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6386 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6387 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
9de8a0c3 6388 //if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6389 //if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6390 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6391 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6392 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6393 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6394 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6395 }
6396 }
6397 }
6398 }
6399 // Merge in delay slot (wont dirty)
6400 for(r=0;r<HOST_REGS;r++) {
6401 if(r!=EXCLUDE_REG) {
9de8a0c3 6402 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6403 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6404 if(regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6405 if(regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6406 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
9de8a0c3 6407 if(branch_regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6408 if(branch_regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6409 if(branch_regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6410 if(branch_regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6411 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6412 }
6413 }
6414 if(wr) {
6415 #ifndef DESTRUCTIVE_WRITEBACK
6416 branch_regs[i].dirty&=wont_dirty_i;
6417 #endif
6418 branch_regs[i].dirty|=will_dirty_i;
6419 }
6420 }
6421 else
6422 {
6423 // Internal branch
6424 if(ba[i]<=start+i*4) {
6425 // Backward branch
fe807a8a 6426 if (dops[i].is_ujump)
57871462 6427 {
6428 // Unconditional branch
6429 temp_will_dirty=0;
6430 temp_wont_dirty=0;
6431 // Merge in delay slot (will dirty)
6432 for(r=0;r<HOST_REGS;r++) {
6433 if(r!=EXCLUDE_REG) {
9de8a0c3 6434 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6435 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6436 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6437 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6438 if(branch_regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
57871462 6439 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6440 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
9de8a0c3 6441 if(regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6442 if(regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6443 if(regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6444 if(regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6445 if(regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
57871462 6446 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6447 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6448 }
6449 }
6450 } else {
6451 // Conditional branch (not taken case)
6452 temp_will_dirty=will_dirty_next;
6453 temp_wont_dirty=wont_dirty_next;
6454 // Merge in delay slot (will dirty)
6455 for(r=0;r<HOST_REGS;r++) {
6456 if(r!=EXCLUDE_REG) {
9de8a0c3 6457 if (1) { // !dops[i].likely)
57871462 6458 // Will not dirty if likely branch is not taken
9de8a0c3 6459 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6460 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6461 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6462 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6463 if(branch_regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
57871462 6464 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6465 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
9de8a0c3 6466 //if(regs[i].regmap[r]==dops[i].rt1) temp_will_dirty|=1<<r;
6467 //if(regs[i].regmap[r]==dops[i].rt2) temp_will_dirty|=1<<r;
6468 if(regs[i].regmap[r]==dops[i+1].rt1) temp_will_dirty|=1<<r;
6469 if(regs[i].regmap[r]==dops[i+1].rt2) temp_will_dirty|=1<<r;
6470 if(regs[i].regmap[r]>33) temp_will_dirty&=~(1<<r);
57871462 6471 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6472 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6473 }
6474 }
6475 }
6476 }
6477 // Merge in delay slot (wont dirty)
6478 for(r=0;r<HOST_REGS;r++) {
6479 if(r!=EXCLUDE_REG) {
9de8a0c3 6480 if(regs[i].regmap[r]==dops[i].rt1) temp_wont_dirty|=1<<r;
6481 if(regs[i].regmap[r]==dops[i].rt2) temp_wont_dirty|=1<<r;
6482 if(regs[i].regmap[r]==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6483 if(regs[i].regmap[r]==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6484 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
9de8a0c3 6485 if(branch_regs[i].regmap[r]==dops[i].rt1) temp_wont_dirty|=1<<r;
6486 if(branch_regs[i].regmap[r]==dops[i].rt2) temp_wont_dirty|=1<<r;
6487 if(branch_regs[i].regmap[r]==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6488 if(branch_regs[i].regmap[r]==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6489 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6490 }
6491 }
6492 // Deal with changed mappings
6493 if(i<iend) {
6494 for(r=0;r<HOST_REGS;r++) {
6495 if(r!=EXCLUDE_REG) {
6496 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6497 temp_will_dirty&=~(1<<r);
6498 temp_wont_dirty&=~(1<<r);
9de8a0c3 6499 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
6500 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6501 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
57871462 6502 } else {
6503 temp_will_dirty|=1<<r;
6504 temp_wont_dirty|=1<<r;
6505 }
6506 }
6507 }
6508 }
6509 }
6510 if(wr) {
6511 will_dirty[i]=temp_will_dirty;
6512 wont_dirty[i]=temp_wont_dirty;
6513 clean_registers((ba[i]-start)>>2,i-1,0);
6514 }else{
6515 // Limit recursion. It can take an excessive amount
6516 // of time if there are a lot of nested loops.
6517 will_dirty[(ba[i]-start)>>2]=0;
6518 wont_dirty[(ba[i]-start)>>2]=-1;
6519 }
6520 }
6521 /*else*/ if(1)
6522 {
fe807a8a 6523 if (dops[i].is_ujump)
57871462 6524 {
6525 // Unconditional branch
6526 will_dirty_i=0;
6527 wont_dirty_i=0;
6528 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6529 for(r=0;r<HOST_REGS;r++) {
6530 if(r!=EXCLUDE_REG) {
6531 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6532 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6533 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6534 }
e3234ecf 6535 if(branch_regs[i].regmap[r]>=0) {
9de8a0c3 6536 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
6537 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
e3234ecf 6538 }
57871462 6539 }
6540 }
6541 //}
6542 // Merge in delay slot
6543 for(r=0;r<HOST_REGS;r++) {
6544 if(r!=EXCLUDE_REG) {
9de8a0c3 6545 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6546 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6547 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6548 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6549 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6550 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6551 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
9de8a0c3 6552 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6553 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6554 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6555 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6556 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6557 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6558 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6559 }
6560 }
6561 } else {
6562 // Conditional branch
6563 will_dirty_i=will_dirty_next;
6564 wont_dirty_i=wont_dirty_next;
9de8a0c3 6565 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
57871462 6566 for(r=0;r<HOST_REGS;r++) {
6567 if(r!=EXCLUDE_REG) {
e3234ecf 6568 signed char target_reg=branch_regs[i].regmap[r];
6569 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6570 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6571 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6572 }
e3234ecf 6573 else if(target_reg>=0) {
9de8a0c3 6574 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
6575 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
57871462 6576 }
57871462 6577 }
6578 }
57871462 6579 // Merge in delay slot
6580 for(r=0;r<HOST_REGS;r++) {
6581 if(r!=EXCLUDE_REG) {
9de8a0c3 6582 if (1) { // !dops[i].likely)
57871462 6583 // Might not dirty if likely branch is not taken
9de8a0c3 6584 if(branch_regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6585 if(branch_regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6586 if(branch_regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6587 if(branch_regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6588 if(branch_regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6589 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6590 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
9de8a0c3 6591 //if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6592 //if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6593 if(regs[i].regmap[r]==dops[i+1].rt1) will_dirty_i|=1<<r;
6594 if(regs[i].regmap[r]==dops[i+1].rt2) will_dirty_i|=1<<r;
6595 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6596 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6597 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6598 }
6599 }
6600 }
6601 }
e3234ecf 6602 // Merge in delay slot (won't dirty)
57871462 6603 for(r=0;r<HOST_REGS;r++) {
6604 if(r!=EXCLUDE_REG) {
9de8a0c3 6605 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6606 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6607 if(regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6608 if(regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6609 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
9de8a0c3 6610 if(branch_regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6611 if(branch_regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
6612 if(branch_regs[i].regmap[r]==dops[i+1].rt1) wont_dirty_i|=1<<r;
6613 if(branch_regs[i].regmap[r]==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6614 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6615 }
6616 }
6617 if(wr) {
6618 #ifndef DESTRUCTIVE_WRITEBACK
6619 branch_regs[i].dirty&=wont_dirty_i;
6620 #endif
6621 branch_regs[i].dirty|=will_dirty_i;
6622 }
6623 }
6624 }
6625 }
cf95b4f0 6626 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6627 {
6628 // SYSCALL instruction (software interrupt)
6629 will_dirty_i=0;
6630 wont_dirty_i=0;
6631 }
cf95b4f0 6632 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6633 {
6634 // ERET instruction (return from interrupt)
6635 will_dirty_i=0;
6636 wont_dirty_i=0;
6637 }
6638 will_dirty_next=will_dirty_i;
6639 wont_dirty_next=wont_dirty_i;
6640 for(r=0;r<HOST_REGS;r++) {
6641 if(r!=EXCLUDE_REG) {
9de8a0c3 6642 if(regs[i].regmap[r]==dops[i].rt1) will_dirty_i|=1<<r;
6643 if(regs[i].regmap[r]==dops[i].rt2) will_dirty_i|=1<<r;
6644 if(regs[i].regmap[r]>33) will_dirty_i&=~(1<<r);
57871462 6645 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6646 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
9de8a0c3 6647 if(regs[i].regmap[r]==dops[i].rt1) wont_dirty_i|=1<<r;
6648 if(regs[i].regmap[r]==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6649 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6650 if(i>istart) {
fe807a8a 6651 if (!dops[i].is_jump)
57871462 6652 {
6653 // Don't store a register immediately after writing it,
6654 // may prevent dual-issue.
9de8a0c3 6655 if(regs[i].regmap[r]==dops[i-1].rt1) wont_dirty_i|=1<<r;
6656 if(regs[i].regmap[r]==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6657 }
6658 }
6659 }
6660 }
6661 // Save it
6662 will_dirty[i]=will_dirty_i;
6663 wont_dirty[i]=wont_dirty_i;
6664 // Mark registers that won't be dirtied as not dirty
6665 if(wr) {
57871462 6666 regs[i].dirty|=will_dirty_i;
6667 #ifndef DESTRUCTIVE_WRITEBACK
6668 regs[i].dirty&=wont_dirty_i;
fe807a8a 6669 if(dops[i].is_jump)
57871462 6670 {
fe807a8a 6671 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6672 for(r=0;r<HOST_REGS;r++) {
6673 if(r!=EXCLUDE_REG) {
6674 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6675 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6676 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6677 }
6678 }
6679 }
6680 }
6681 else
6682 {
6683 if(i<iend) {
6684 for(r=0;r<HOST_REGS;r++) {
6685 if(r!=EXCLUDE_REG) {
6686 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6687 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6688 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6689 }
6690 }
6691 }
6692 }
6693 #endif
57871462 6694 }
6695 // Deal with changed mappings
6696 temp_will_dirty=will_dirty_i;
6697 temp_wont_dirty=wont_dirty_i;
6698 for(r=0;r<HOST_REGS;r++) {
6699 if(r!=EXCLUDE_REG) {
6700 int nr;
6701 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6702 if(wr) {
6703 #ifndef DESTRUCTIVE_WRITEBACK
6704 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6705 #endif
6706 regs[i].wasdirty|=will_dirty_i&(1<<r);
6707 }
6708 }
f776eb14 6709 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6710 // Register moved to a different register
6711 will_dirty_i&=~(1<<r);
6712 wont_dirty_i&=~(1<<r);
6713 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6714 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6715 if(wr) {
6716 #ifndef DESTRUCTIVE_WRITEBACK
6717 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6718 #endif
6719 regs[i].wasdirty|=will_dirty_i&(1<<r);
6720 }
6721 }
6722 else {
6723 will_dirty_i&=~(1<<r);
6724 wont_dirty_i&=~(1<<r);
9de8a0c3 6725 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
6726 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
6727 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
57871462 6728 } else {
6729 wont_dirty_i|=1<<r;
581335b0 6730 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6731 }
6732 }
6733 }
6734 }
6735 }
6736}
6737
4600ba03 6738#ifdef DISASM
2acc46cd 6739#include <inttypes.h>
6740void print_regmap(const char *name, const signed char *regmap)
6741{
6742 char buf[5];
6743 int i, l;
6744 fputs(name, stdout);
6745 for (i = 0; i < HOST_REGS; i++) {
6746 l = 0;
6747 if (regmap[i] >= 0)
6748 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6749 for (; l < 3; l++)
6750 buf[l] = ' ';
6751 buf[l] = 0;
6752 printf(" r%d=%s", i, buf);
6753 }
6754 fputs("\n", stdout);
6755}
6756
57871462 6757 /* disassembly */
6758void disassemble_inst(int i)
6759{
cf95b4f0 6760 if (dops[i].bt) printf("*"); else printf(" ");
6761 switch(dops[i].itype) {
57871462 6762 case UJUMP:
6763 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6764 case CJUMP:
cf95b4f0 6765 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6766 case SJUMP:
cf95b4f0 6767 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6768 case RJUMP:
cf95b4f0 6769 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6770 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6771 else
cf95b4f0 6772 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6773 break;
57871462 6774 case SPAN:
cf95b4f0 6775 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6776 case IMM16:
cf95b4f0 6777 if(dops[i].opcode==0xf) //LUI
6778 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6779 else
cf95b4f0 6780 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6781 break;
6782 case LOAD:
6783 case LOADLR:
cf95b4f0 6784 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6785 break;
6786 case STORE:
6787 case STORELR:
cf95b4f0 6788 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6789 break;
6790 case ALU:
6791 case SHIFT:
cf95b4f0 6792 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6793 break;
6794 case MULTDIV:
cf95b4f0 6795 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6796 break;
6797 case SHIFTIMM:
cf95b4f0 6798 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6799 break;
6800 case MOV:
cf95b4f0 6801 if((dops[i].opcode2&0x1d)==0x10)
6802 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6803 else if((dops[i].opcode2&0x1d)==0x11)
6804 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6805 else
6806 printf (" %x: %s\n",start+i*4,insn[i]);
6807 break;
6808 case COP0:
cf95b4f0 6809 if(dops[i].opcode2==0)
6810 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6811 else if(dops[i].opcode2==4)
6812 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6813 else printf (" %x: %s\n",start+i*4,insn[i]);
6814 break;
6815 case COP1:
cf95b4f0 6816 if(dops[i].opcode2<3)
6817 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6818 else if(dops[i].opcode2>3)
6819 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6820 else printf (" %x: %s\n",start+i*4,insn[i]);
6821 break;
b9b61529 6822 case COP2:
cf95b4f0 6823 if(dops[i].opcode2<3)
6824 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6825 else if(dops[i].opcode2>3)
6826 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6827 else printf (" %x: %s\n",start+i*4,insn[i]);
6828 break;
57871462 6829 case C1LS:
cf95b4f0 6830 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6831 break;
b9b61529 6832 case C2LS:
cf95b4f0 6833 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6834 break;
1e973cb0 6835 case INTCALL:
6836 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6837 break;
57871462 6838 default:
6839 //printf (" %s %8x\n",insn[i],source[i]);
6840 printf (" %x: %s\n",start+i*4,insn[i]);
6841 }
2acc46cd 6842 return;
6843 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6844 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6845 print_regmap("pre: ", regmap_pre[i]);
6846 print_regmap("entry: ", regs[i].regmap_entry);
6847 print_regmap("map: ", regs[i].regmap);
6848 if (dops[i].is_jump) {
6849 print_regmap("bentry:", branch_regs[i].regmap_entry);
6850 print_regmap("bmap: ", branch_regs[i].regmap);
6851 }
57871462 6852}
4600ba03 6853#else
6854static void disassemble_inst(int i) {}
6855#endif // DISASM
57871462 6856
d848b60a 6857#define DRC_TEST_VAL 0x74657374
6858
be516ebe 6859static void new_dynarec_test(void)
d848b60a 6860{
be516ebe 6861 int (*testfunc)(void);
d148d265 6862 void *beginning;
be516ebe 6863 int ret[2];
6864 size_t i;
d148d265 6865
687b4580 6866 // check structure linkage
7c3a5182 6867 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6868 {
7c3a5182 6869 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6870 }
6871
761fdd0a 6872 SysPrintf("testing if we can run recompiled code @%p...\n", out);
be516ebe 6873 ((volatile u_int *)out)[0]++; // make cache dirty
6874
6875 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6876 out = ndrc->translation_cache;
be516ebe 6877 beginning = start_block();
6878 emit_movimm(DRC_TEST_VAL + i, 0); // test
6879 emit_ret();
6880 literal_pool(0);
6881 end_block(beginning);
6882 testfunc = beginning;
6883 ret[i] = testfunc();
6884 }
6885
6886 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6887 SysPrintf("test passed.\n");
6888 else
be516ebe 6889 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6890 out = ndrc->translation_cache;
d848b60a 6891}
6892
dc990066 6893// clear the state completely, instead of just marking
6894// things invalid like invalidate_all_pages() does
919981d0 6895void new_dynarec_clear_full(void)
57871462 6896{
57871462 6897 int n;
2a014d73 6898 out = ndrc->translation_cache;
35775df7 6899 memset(invalid_code,1,sizeof(invalid_code));
6900 memset(hash_table,0xff,sizeof(hash_table));
57871462 6901 memset(mini_ht,-1,sizeof(mini_ht));
6902 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6903 memset(shadow,0,sizeof(shadow));
57871462 6904 copy=shadow;
6905 expirep=16384; // Expiry pointer, +2 blocks
6906 pending_exception=0;
6907 literalcount=0;
57871462 6908 stop_after_jal=0;
9be4ba64 6909 inv_code_start=inv_code_end=~0;
7f94b097 6910 hack_addr=0;
39b71d9a 6911 f1_hack=0;
57871462 6912 // TLB
dc990066 6913 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6914 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6915 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6916
6917 cycle_multiplier_old = cycle_multiplier;
6918 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6919}
6920
919981d0 6921void new_dynarec_init(void)
dc990066 6922{
66ea165f 6923 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
1e212a25 6924
0aeb0cb9 6925#ifdef _3DS
6926 check_rosalina();
6927#endif
2a014d73 6928#ifdef BASE_ADDR_DYNAMIC
1e212a25 6929 #ifdef VITA
0aeb0cb9 6930 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
66ea165f 6931 if (sceBlock <= 0)
6932 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
2a014d73 6933 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6934 if (ret < 0)
66ea165f 6935 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
0aeb0cb9 6936 sceKernelOpenVMDomain();
6937 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6938 #elif defined(_MSC_VER)
6939 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6940 PAGE_EXECUTE_READWRITE);
1e212a25 6941 #else
2a014d73 6942 uintptr_t desired_addr = 0;
6943 #ifdef __ELF__
6944 extern char _end;
6945 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6946 #endif
6947 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6948 PROT_READ | PROT_WRITE | PROT_EXEC,
6949 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6950 if (ndrc == MAP_FAILED) {
d848b60a 6951 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6952 abort();
d848b60a 6953 }
1e212a25 6954 #endif
6955#else
6956 #ifndef NO_WRITE_EXEC
bdeade46 6957 // not all systems allow execute in data segment by default
761fdd0a 6958 // size must be 4K aligned for 3DS?
6959 if (mprotect(ndrc, sizeof(*ndrc),
2a014d73 6960 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6961 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6962 #endif
dc990066 6963#endif
2a014d73 6964 out = ndrc->translation_cache;
2573466a 6965 cycle_multiplier=200;
dc990066 6966 new_dynarec_clear_full();
6967#ifdef HOST_IMM8
6968 // Copy this into local area so we don't have to put it in every literal pool
6969 invc_ptr=invalid_code;
6970#endif
57871462 6971 arch_init();
d848b60a 6972 new_dynarec_test();
01d26796 6973 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6974 if (ram_offset!=0)
c43b5311 6975 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6976}
6977
919981d0 6978void new_dynarec_cleanup(void)
57871462 6979{
6980 int n;
2a014d73 6981#ifdef BASE_ADDR_DYNAMIC
1e212a25 6982 #ifdef VITA
66ea165f 6983 // sceBlock is managed by retroarch's bootstrap code
9c67c98f 6984 //sceKernelFreeMemBlock(sceBlock);
6985 //sceBlock = -1;
1e212a25 6986 #else
2a014d73 6987 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6988 SysPrintf("munmap() failed\n");
bdeade46 6989 #endif
1e212a25 6990#endif
57871462 6991 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6992 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6993 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6994 #ifdef ROM_COPY
c43b5311 6995 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6996 #endif
6997}
6998
03f55e6b 6999static u_int *get_source_start(u_int addr, u_int *limit)
57871462 7000{
03f55e6b 7001 if (addr < 0x00200000 ||
a3203cf4 7002 (0xa0000000 <= addr && addr < 0xa0200000))
7003 {
03f55e6b 7004 // used for BIOS calls mostly?
7005 *limit = (addr&0xa0000000)|0x00200000;
01d26796 7006 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 7007 }
7008 else if (!Config.HLE && (
7009 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 7010 (0xbfc00000 <= addr && addr < 0xbfc80000)))
7011 {
7012 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
7013 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 7014 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
24058131 7015 cycle_multiplier_active = 200;
a3203cf4 7016
03f55e6b 7017 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 7018 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 7019 }
7020 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7021 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 7022 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 7023 }
581335b0 7024 return NULL;
03f55e6b 7025}
7026
7027static u_int scan_for_ret(u_int addr)
7028{
7029 u_int limit = 0;
7030 u_int *mem;
7031
7032 mem = get_source_start(addr, &limit);
7033 if (mem == NULL)
7034 return addr;
7035
7036 if (limit > addr + 0x1000)
7037 limit = addr + 0x1000;
7038 for (; addr < limit; addr += 4, mem++) {
7039 if (*mem == 0x03e00008) // jr $ra
7040 return addr + 8;
57871462 7041 }
581335b0 7042 return addr;
03f55e6b 7043}
7044
7045struct savestate_block {
7046 uint32_t addr;
7047 uint32_t regflags;
7048};
7049
7050static int addr_cmp(const void *p1_, const void *p2_)
7051{
7052 const struct savestate_block *p1 = p1_, *p2 = p2_;
7053 return p1->addr - p2->addr;
7054}
7055
7056int new_dynarec_save_blocks(void *save, int size)
7057{
7058 struct savestate_block *blocks = save;
7059 int maxcount = size / sizeof(blocks[0]);
7060 struct savestate_block tmp_blocks[1024];
7061 struct ll_entry *head;
7062 int p, s, d, o, bcnt;
7063 u_int addr;
7064
7065 o = 0;
b14b6a8f 7066 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 7067 bcnt = 0;
7068 for (head = jump_in[p]; head != NULL; head = head->next) {
7069 tmp_blocks[bcnt].addr = head->vaddr;
7070 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7071 bcnt++;
7072 }
7073 if (bcnt < 1)
7074 continue;
7075 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7076
7077 addr = tmp_blocks[0].addr;
7078 for (s = d = 0; s < bcnt; s++) {
7079 if (tmp_blocks[s].addr < addr)
7080 continue;
7081 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7082 tmp_blocks[d++] = tmp_blocks[s];
7083 addr = scan_for_ret(tmp_blocks[s].addr);
7084 }
7085
7086 if (o + d > maxcount)
7087 d = maxcount - o;
7088 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7089 o += d;
7090 }
7091
7092 return o * sizeof(blocks[0]);
7093}
7094
7095void new_dynarec_load_blocks(const void *save, int size)
7096{
7097 const struct savestate_block *blocks = save;
7098 int count = size / sizeof(blocks[0]);
7099 u_int regs_save[32];
7100 uint32_t f;
7101 int i, b;
7102
7103 get_addr(psxRegs.pc);
7104
7105 // change GPRs for speculation to at least partially work..
7106 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7107 for (i = 1; i < 32; i++)
7108 psxRegs.GPR.r[i] = 0x80000000;
7109
7110 for (b = 0; b < count; b++) {
7111 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7112 if (f & 1)
7113 psxRegs.GPR.r[i] = 0x1f800000;
7114 }
7115
7116 get_addr(blocks[b].addr);
7117
7118 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7119 if (f & 1)
7120 psxRegs.GPR.r[i] = 0x80000000;
7121 }
7122 }
7123
7124 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7125}
7126
7f94b097 7127static int apply_hacks(void)
24058131 7128{
7129 int i;
7130 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7f94b097 7131 return 0;
24058131 7132 /* special hack(s) */
7133 for (i = 0; i < slen - 4; i++)
7134 {
7135 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7136 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7137 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7138 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7139 {
7140 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7141 dops[i + 3].itype = NOP;
7142 }
7143 }
7144 i = slen;
7145 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7146 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7147 && dops[i-7].itype == STORE)
7148 {
7149 i = i-8;
7150 if (dops[i].itype == IMM16)
7151 i--;
7152 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7153 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7154 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7155 {
7f94b097 7156 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7157 f1_hack = 1;
7158 return 1;
24058131 7159 }
7160 }
7f94b097 7161 return 0;
24058131 7162}
7163
3968e69e 7164int new_recompile_block(u_int addr)
03f55e6b 7165{
7166 u_int pagelimit = 0;
7167 u_int state_rflags = 0;
7168 int i;
7169
1a4301c4 7170 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7171 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7172 //if(debug)
57871462 7173 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7174
7175 // this is just for speculation
7176 for (i = 1; i < 32; i++) {
7177 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7178 state_rflags |= 1 << i;
7179 }
7180
57871462 7181 start = (u_int)addr&~3;
7c3a5182 7182 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7183 new_dynarec_did_compile=1;
9ad4d757 7184 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7185 {
7139f3c8 7186 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7187 void *beginning=start_block();
7139f3c8 7188 u_int page=get_page(start);
d148d265 7189
7139f3c8 7190 invalid_code[start>>12]=0;
7191 emit_movimm(start,0);
643aeae3 7192 emit_writeword(0,&pcaddr);
2a014d73 7193 emit_far_jump(new_dyna_leave);
15776b68 7194 literal_pool(0);
d148d265 7195 end_block(beginning);
03f55e6b 7196 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7197 return 0;
7198 }
7f94b097 7199 else if (f1_hack && hack_addr == 0) {
39b71d9a 7200 void *beginning = start_block();
7201 u_int page = get_page(start);
7f94b097 7202 emit_movimm(start, 0);
7203 emit_writeword(0, &hack_addr);
39b71d9a 7204 emit_readword(&psxRegs.GPR.n.sp, 0);
7205 emit_readptr(&mem_rtab, 1);
7206 emit_shrimm(0, 12, 2);
7207 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7208 emit_addimm(0, 0x18, 0);
7209 emit_adds_ptr(1, 1, 1);
7210 emit_ldr_dualindexed(1, 0, 0);
7211 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7212 emit_far_call(get_addr_ht);
7213 emit_jmpreg(0); // jr k0
7214 literal_pool(0);
7215 end_block(beginning);
7216
7217 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7218 SysPrintf("F1 hack to %08x\n", start);
39b71d9a 7219 return 0;
7220 }
03f55e6b 7221
24058131 7222 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7223 ? cycle_multiplier_override : cycle_multiplier;
7224
03f55e6b 7225 source = get_source_start(start, &pagelimit);
7226 if (source == NULL) {
b4ab351d 7227 if (addr != hack_addr) {
7228 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7229 hack_addr = addr;
7230 }
7231 //abort();
7232 return -1;
57871462 7233 }
7234
7235 /* Pass 1: disassemble */
7236 /* Pass 2: register dependencies, branch targets */
7237 /* Pass 3: register allocation */
7238 /* Pass 4: branch dependencies */
7239 /* Pass 5: pre-alloc */
7240 /* Pass 6: optimize clean/dirty state */
7241 /* Pass 7: flag 32-bit registers */
7242 /* Pass 8: assembly */
7243 /* Pass 9: linker */
7244 /* Pass 10: garbage collection / free memory */
7245
03f55e6b 7246 int j;
b4ab351d 7247 int done = 0, ni_count = 0;
57871462 7248 unsigned int type,op,op2;
7249
7250 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7251
57871462 7252 /* Pass 1 disassembly */
7253
7ebfcedf 7254 for (i = 0; !done; i++)
7255 {
7256 memset(&dops[i], 0, sizeof(dops[i]));
cf95b4f0 7257 op2=0;
e1190b87 7258 minimum_free_regs[i]=0;
cf95b4f0 7259 dops[i].opcode=op=source[i]>>26;
57871462 7260 switch(op)
7261 {
7262 case 0x00: strcpy(insn[i],"special"); type=NI;
7263 op2=source[i]&0x3f;
7264 switch(op2)
7265 {
7266 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7267 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7268 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7269 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7270 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7271 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7272 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7273 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7274 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
d1150cd6 7275 case 0x0D: strcpy(insn[i],"BREAK"); type=SYSCALL; break;
57871462 7276 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7277 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7278 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7279 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7280 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7281 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7282 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7283 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7284 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7285 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7286 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7287 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7288 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7289 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7290 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7291 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7292 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7293 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7294 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7295 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7296 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7297 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7298 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7299 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7300 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7301#if 0
7f2607ea 7302 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7303 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7304 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7305 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7306 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7307 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7308 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7309 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7310 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7311 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7312 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7313 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7314 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7315 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7316 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7317 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7318 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7319#endif
57871462 7320 }
7321 break;
7322 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7323 op2=(source[i]>>16)&0x1f;
7324 switch(op2)
7325 {
7326 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7327 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7328 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7329 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7330 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7331 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7332 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7333 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7334 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7335 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7336 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7337 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7338 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7339 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7340 }
7341 break;
7342 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7343 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7344 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7345 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7346 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7347 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7348 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7349 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7350 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7351 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7352 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7353 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7354 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7355 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7356 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7357 op2=(source[i]>>21)&0x1f;
7358 switch(op2)
7359 {
7360 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7361 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7362 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7363 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7364 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7365 }
7366 break;
00fa9369 7367 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7368 op2=(source[i]>>21)&0x1f;
57871462 7369 break;
71e490c5 7370#if 0
57871462 7371 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7372 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7373 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7374 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7375 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7376 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7377 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7378 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7379#endif
57871462 7380 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7381 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7382 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7383 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7384 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7385 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7386 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7387#if 0
57871462 7388 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7389#endif
57871462 7390 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7391 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7392 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7393 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7394#if 0
57871462 7395 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7396 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7397#endif
57871462 7398 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7399 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7400 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7401 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7402#if 0
57871462 7403 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7404 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7405 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7406#endif
57871462 7407 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7408 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7409#if 0
57871462 7410 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7411 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7412 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7413#endif
b9b61529 7414 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7415 op2=(source[i]>>21)&0x1f;
be516ebe 7416 //if (op2 & 0x10)
bedfea38 7417 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7418 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7419 if (gte_regnames[source[i]&0x3f]!=NULL)
7420 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7421 else
7422 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7423 type=C2OP;
7424 }
7425 }
7426 else switch(op2)
b9b61529 7427 {
7428 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7429 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7430 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7431 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7432 }
7433 break;
7434 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7435 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7436 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7437 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7438 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7439 break;
57871462 7440 }
cf95b4f0 7441 dops[i].itype=type;
7442 dops[i].opcode2=op2;
57871462 7443 /* Get registers/immediates */
cf95b4f0 7444 dops[i].lt1=0;
bedfea38 7445 gte_rs[i]=gte_rt[i]=0;
57871462 7446 switch(type) {
7447 case LOAD:
cf95b4f0 7448 dops[i].rs1=(source[i]>>21)&0x1f;
7449 dops[i].rs2=0;
7450 dops[i].rt1=(source[i]>>16)&0x1f;
7451 dops[i].rt2=0;
57871462 7452 imm[i]=(short)source[i];
7453 break;
7454 case STORE:
7455 case STORELR:
cf95b4f0 7456 dops[i].rs1=(source[i]>>21)&0x1f;
7457 dops[i].rs2=(source[i]>>16)&0x1f;
7458 dops[i].rt1=0;
7459 dops[i].rt2=0;
57871462 7460 imm[i]=(short)source[i];
57871462 7461 break;
7462 case LOADLR:
7463 // LWL/LWR only load part of the register,
7464 // therefore the target register must be treated as a source too
cf95b4f0 7465 dops[i].rs1=(source[i]>>21)&0x1f;
7466 dops[i].rs2=(source[i]>>16)&0x1f;
7467 dops[i].rt1=(source[i]>>16)&0x1f;
7468 dops[i].rt2=0;
57871462 7469 imm[i]=(short)source[i];
57871462 7470 break;
7471 case IMM16:
cf95b4f0 7472 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7473 else dops[i].rs1=(source[i]>>21)&0x1f;
7474 dops[i].rs2=0;
7475 dops[i].rt1=(source[i]>>16)&0x1f;
7476 dops[i].rt2=0;
57871462 7477 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7478 imm[i]=(unsigned short)source[i];
7479 }else{
7480 imm[i]=(short)source[i];
7481 }
57871462 7482 break;
7483 case UJUMP:
cf95b4f0 7484 dops[i].rs1=0;
7485 dops[i].rs2=0;
7486 dops[i].rt1=0;
7487 dops[i].rt2=0;
57871462 7488 // The JAL instruction writes to r31.
7489 if (op&1) {
cf95b4f0 7490 dops[i].rt1=31;
57871462 7491 }
cf95b4f0 7492 dops[i].rs2=CCREG;
57871462 7493 break;
7494 case RJUMP:
cf95b4f0 7495 dops[i].rs1=(source[i]>>21)&0x1f;
7496 dops[i].rs2=0;
7497 dops[i].rt1=0;
7498 dops[i].rt2=0;
5067f341 7499 // The JALR instruction writes to rd.
57871462 7500 if (op2&1) {
cf95b4f0 7501 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7502 }
cf95b4f0 7503 dops[i].rs2=CCREG;
57871462 7504 break;
7505 case CJUMP:
cf95b4f0 7506 dops[i].rs1=(source[i]>>21)&0x1f;
7507 dops[i].rs2=(source[i]>>16)&0x1f;
7508 dops[i].rt1=0;
7509 dops[i].rt2=0;
57871462 7510 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7511 dops[i].rs2=0;
57871462 7512 }
57871462 7513 break;
7514 case SJUMP:
cf95b4f0 7515 dops[i].rs1=(source[i]>>21)&0x1f;
7516 dops[i].rs2=CCREG;
7517 dops[i].rt1=0;
7518 dops[i].rt2=0;
57871462 7519 if(op2&0x10) { // BxxAL
cf95b4f0 7520 dops[i].rt1=31;
57871462 7521 // NOTE: If the branch is not taken, r31 is still overwritten
7522 }
57871462 7523 break;
57871462 7524 case ALU:
cf95b4f0 7525 dops[i].rs1=(source[i]>>21)&0x1f; // source
7526 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7527 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7528 dops[i].rt2=0;
57871462 7529 break;
7530 case MULTDIV:
cf95b4f0 7531 dops[i].rs1=(source[i]>>21)&0x1f; // source
7532 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7533 dops[i].rt1=HIREG;
7534 dops[i].rt2=LOREG;
57871462 7535 break;
7536 case MOV:
cf95b4f0 7537 dops[i].rs1=0;
7538 dops[i].rs2=0;
7539 dops[i].rt1=0;
7540 dops[i].rt2=0;
7541 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7542 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7543 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7544 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7545 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7546 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7547 break;
7548 case SHIFT:
cf95b4f0 7549 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7550 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7551 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7552 dops[i].rt2=0;
57871462 7553 break;
7554 case SHIFTIMM:
cf95b4f0 7555 dops[i].rs1=(source[i]>>16)&0x1f;
7556 dops[i].rs2=0;
7557 dops[i].rt1=(source[i]>>11)&0x1f;
7558 dops[i].rt2=0;
57871462 7559 imm[i]=(source[i]>>6)&0x1f;
7560 // DSxx32 instructions
7561 if(op2>=0x3c) imm[i]|=0x20;
57871462 7562 break;
7563 case COP0:
cf95b4f0 7564 dops[i].rs1=0;
7565 dops[i].rs2=0;
7566 dops[i].rt1=0;
7567 dops[i].rt2=0;
7568 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7569 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7570 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7571 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7572 break;
7573 case COP1:
cf95b4f0 7574 dops[i].rs1=0;
7575 dops[i].rs2=0;
7576 dops[i].rt1=0;
7577 dops[i].rt2=0;
7578 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7579 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7580 dops[i].rs2=CSREG;
57871462 7581 break;
bedfea38 7582 case COP2:
cf95b4f0 7583 dops[i].rs1=0;
7584 dops[i].rs2=0;
7585 dops[i].rt1=0;
7586 dops[i].rt2=0;
7587 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7588 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7589 dops[i].rs2=CSREG;
bedfea38 7590 int gr=(source[i]>>11)&0x1F;
7591 switch(op2)
7592 {
7593 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7594 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7595 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7596 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7597 }
7598 break;
57871462 7599 case C1LS:
cf95b4f0 7600 dops[i].rs1=(source[i]>>21)&0x1F;
7601 dops[i].rs2=CSREG;
7602 dops[i].rt1=0;
7603 dops[i].rt2=0;
57871462 7604 imm[i]=(short)source[i];
7605 break;
b9b61529 7606 case C2LS:
cf95b4f0 7607 dops[i].rs1=(source[i]>>21)&0x1F;
7608 dops[i].rs2=0;
7609 dops[i].rt1=0;
7610 dops[i].rt2=0;
b9b61529 7611 imm[i]=(short)source[i];
bedfea38 7612 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7613 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7614 break;
7615 case C2OP:
cf95b4f0 7616 dops[i].rs1=0;
7617 dops[i].rs2=0;
7618 dops[i].rt1=0;
7619 dops[i].rt2=0;
2167bef6 7620 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7621 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7622 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7623 if((source[i]&0x3f)==GTE_MVMVA) {
7624 int v = (source[i] >> 15) & 3;
7625 gte_rs[i]&=~0xe3fll;
7626 if(v==3) gte_rs[i]|=0xe00ll;
7627 else gte_rs[i]|=3ll<<(v*2);
7628 }
b9b61529 7629 break;
57871462 7630 case SYSCALL:
7139f3c8 7631 case HLECALL:
1e973cb0 7632 case INTCALL:
cf95b4f0 7633 dops[i].rs1=CCREG;
7634 dops[i].rs2=0;
7635 dops[i].rt1=0;
7636 dops[i].rt2=0;
57871462 7637 break;
7638 default:
cf95b4f0 7639 dops[i].rs1=0;
7640 dops[i].rs2=0;
7641 dops[i].rt1=0;
7642 dops[i].rt2=0;
57871462 7643 }
7644 /* Calculate branch target addresses */
7645 if(type==UJUMP)
7646 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7647 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7648 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7649 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7650 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7651 else if(type==CJUMP||type==SJUMP)
57871462 7652 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7653 else ba[i]=-1;
4919de1e 7654
7655 /* simplify always (not)taken branches */
cf95b4f0 7656 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7657 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7658 if (!(op & 1)) {
cf95b4f0 7659 dops[i].itype = type = UJUMP;
7660 dops[i].rs2 = CCREG;
4919de1e 7661 }
7662 }
cf95b4f0 7663 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7664 dops[i].itype = type = UJUMP;
4919de1e 7665
fe807a8a 7666 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7667 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7668 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7669 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7670
4919de1e 7671 /* messy cases to just pass over to the interpreter */
fe807a8a 7672 if (i > 0 && dops[i-1].is_jump) {
3e535354 7673 int do_in_intrp=0;
7674 // branch in delay slot?
fe807a8a 7675 if (dops[i].is_jump) {
3e535354 7676 // don't handle first branch and call interpreter if it's hit
c43b5311 7677 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7678 do_in_intrp=1;
7679 }
7680 // basic load delay detection
cf95b4f0 7681 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7682 int t=(ba[i-1]-start)/4;
cf95b4f0 7683 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7684 // jump target wants DS result - potential load delay effect
c43b5311 7685 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7686 do_in_intrp=1;
cf95b4f0 7687 dops[t+1].bt=1; // expected return from interpreter
3e535354 7688 }
cf95b4f0 7689 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7690 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7691 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7692 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7693 do_in_intrp=1;
7694 }
7695 }
7ebfcedf 7696 if (do_in_intrp) {
7697 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7698 dops[i-1].itype = INTCALL;
7699 dops[i-1].rs1 = CCREG;
7700 ba[i-1] = -1;
7701 done = 2;
3e535354 7702 i--; // don't compile the DS
26869094 7703 }
3e535354 7704 }
4919de1e 7705
3e535354 7706 /* Is this the end of the block? */
fe807a8a 7707 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7708 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7709 done=2;
57871462 7710 }
7711 else {
7712 if(stop_after_jal) done=1;
7713 // Stop on BREAK
7714 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7715 }
7716 // Don't recompile stuff that's already compiled
7717 if(check_addr(start+i*4+4)) done=1;
7718 // Don't get too close to the limit
7719 if(i>MAXBLOCK/2) done=1;
7720 }
d1150cd6 7721 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7722 done = stop_after_jal ? 1 : 2;
7723 if (done == 2) {
1e973cb0 7724 // Does the block continue due to a branch?
7725 for(j=i-1;j>=0;j--)
7726 {
2a706964 7727 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7728 if(ba[j]==start+i*4+4) done=j=0;
7729 if(ba[j]==start+i*4+8) done=j=0;
7730 }
7731 }
75dec299 7732 //assert(i<MAXBLOCK-1);
57871462 7733 if(start+i*4==pagelimit-4) done=1;
7734 assert(start+i*4<pagelimit);
7735 if (i==MAXBLOCK-1) done=1;
7736 // Stop if we're compiling junk
b4ab351d 7737 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
57871462 7738 done=stop_after_jal=1;
c43b5311 7739 SysPrintf("Disabled speculative precompilation\n");
57871462 7740 }
7741 }
7742 slen=i;
fe807a8a 7743 if (dops[i-1].is_jump) {
57871462 7744 if(start+i*4==pagelimit) {
cf95b4f0 7745 dops[i-1].itype=SPAN;
57871462 7746 }
7747 }
7748 assert(slen>0);
7749
7f94b097 7750 int clear_hack_addr = apply_hacks();
39b71d9a 7751
57871462 7752 /* Pass 2 - Register dependencies and branch targets */
7753
7754 unneeded_registers(0,slen-1,0);
9f51b4b9 7755
57871462 7756 /* Pass 3 - Register allocation */
7757
7758 struct regstat current; // Current register allocations/status
6cc8d23c 7759 clear_all_regs(current.regmap_entry);
57871462 7760 clear_all_regs(current.regmap);
6cc8d23c 7761 current.wasdirty = current.dirty = 0;
7762 current.u = unneeded_reg[0];
7763 alloc_reg(&current, 0, CCREG);
7764 dirty_reg(&current, CCREG);
7765 current.wasconst = 0;
7766 current.isconst = 0;
7767 current.loadedconst = 0;
7768 current.waswritten = 0;
57871462 7769 int ds=0;
7770 int cc=0;
5194fb95 7771 int hr=-1;
6ebf4adf 7772
57871462 7773 if((u_int)addr&1) {
7774 // First instruction is delay slot
7775 cc=-1;
cf95b4f0 7776 dops[1].bt=1;
57871462 7777 ds=1;
7778 unneeded_reg[0]=1;
57871462 7779 current.regmap[HOST_BTREG]=BTREG;
7780 }
9f51b4b9 7781
57871462 7782 for(i=0;i<slen;i++)
7783 {
cf95b4f0 7784 if(dops[i].bt)
57871462 7785 {
7786 int hr;
7787 for(hr=0;hr<HOST_REGS;hr++)
7788 {
7789 // Is this really necessary?
7790 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7791 }
7792 current.isconst=0;
27727b63 7793 current.waswritten=0;
57871462 7794 }
24385cae 7795
57871462 7796 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7797 regs[i].wasconst=current.isconst;
57871462 7798 regs[i].wasdirty=current.dirty;
6cc8d23c 7799 regs[i].dirty=0;
7800 regs[i].u=0;
7801 regs[i].isconst=0;
8575a877 7802 regs[i].loadedconst=0;
fe807a8a 7803 if (!dops[i].is_jump) {
57871462 7804 if(i+1<slen) {
cf95b4f0 7805 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7806 current.u|=1;
57871462 7807 } else {
7808 current.u=1;
57871462 7809 }
7810 } else {
7811 if(i+1<slen) {
cf95b4f0 7812 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7813 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7814 current.u|=1;
7ebfcedf 7815 } else {
7816 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7817 abort();
7818 }
57871462 7819 }
cf95b4f0 7820 dops[i].is_ds=ds;
57871462 7821 if(ds) {
7822 ds=0; // Skip delay slot, already allocated as part of branch
7823 // ...but we need to alloc it in case something jumps here
7824 if(i+1<slen) {
7825 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7826 }else{
7827 current.u=branch_unneeded_reg[i-1];
57871462 7828 }
cf95b4f0 7829 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7830 current.u|=1;
57871462 7831 struct regstat temp;
7832 memcpy(&temp,&current,sizeof(current));
7833 temp.wasdirty=temp.dirty;
57871462 7834 // TODO: Take into account unconditional branches, as below
7835 delayslot_alloc(&temp,i);
7836 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7837 regs[i].wasdirty=temp.wasdirty;
57871462 7838 regs[i].dirty=temp.dirty;
57871462 7839 regs[i].isconst=0;
7840 regs[i].wasconst=0;
7841 current.isconst=0;
7842 // Create entry (branch target) regmap
7843 for(hr=0;hr<HOST_REGS;hr++)
7844 {
7845 int r=temp.regmap[hr];
7846 if(r>=0) {
7847 if(r!=regmap_pre[i][hr]) {
7848 regs[i].regmap_entry[hr]=-1;
7849 }
7850 else
7851 {
7c3a5182 7852 assert(r < 64);
57871462 7853 if((current.u>>r)&1) {
7854 regs[i].regmap_entry[hr]=-1;
7855 regs[i].regmap[hr]=-1;
7856 //Don't clear regs in the delay slot as the branch might need them
7857 //current.regmap[hr]=-1;
7858 }else
7859 regs[i].regmap_entry[hr]=r;
57871462 7860 }
7861 } else {
7862 // First instruction expects CCREG to be allocated
9f51b4b9 7863 if(i==0&&hr==HOST_CCREG)
57871462 7864 regs[i].regmap_entry[hr]=CCREG;
7865 else
7866 regs[i].regmap_entry[hr]=-1;
7867 }
7868 }
7869 }
7870 else { // Not delay slot
cf95b4f0 7871 switch(dops[i].itype) {
57871462 7872 case UJUMP:
7873 //current.isconst=0; // DEBUG
7874 //current.wasconst=0; // DEBUG
7875 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7876 clear_const(&current,dops[i].rt1);
57871462 7877 alloc_cc(&current,i);
7878 dirty_reg(&current,CCREG);
cf95b4f0 7879 if (dops[i].rt1==31) {
57871462 7880 alloc_reg(&current,i,31);
7881 dirty_reg(&current,31);
cf95b4f0 7882 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7883 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7884 #ifdef REG_PREFETCH
7885 alloc_reg(&current,i,PTEMP);
7886 #endif
57871462 7887 }
cf95b4f0 7888 dops[i].ooo=1;
269bb29a 7889 delayslot_alloc(&current,i+1);
57871462 7890 //current.isconst=0; // DEBUG
7891 ds=1;
7892 //printf("i=%d, isconst=%x\n",i,current.isconst);
7893 break;
7894 case RJUMP:
7895 //current.isconst=0;
7896 //current.wasconst=0;
7897 //regs[i].wasconst=0;
cf95b4f0 7898 clear_const(&current,dops[i].rs1);
7899 clear_const(&current,dops[i].rt1);
57871462 7900 alloc_cc(&current,i);
7901 dirty_reg(&current,CCREG);
4919de1e 7902 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7903 alloc_reg(&current,i,dops[i].rs1);
7904 if (dops[i].rt1!=0) {
7905 alloc_reg(&current,i,dops[i].rt1);
7906 dirty_reg(&current,dops[i].rt1);
7907 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7908 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7909 #ifdef REG_PREFETCH
7910 alloc_reg(&current,i,PTEMP);
7911 #endif
7912 }
7913 #ifdef USE_MINI_HT
cf95b4f0 7914 if(dops[i].rs1==31) { // JALR
57871462 7915 alloc_reg(&current,i,RHASH);
57871462 7916 alloc_reg(&current,i,RHTBL);
57871462 7917 }
7918 #endif
7919 delayslot_alloc(&current,i+1);
7920 } else {
7921 // The delay slot overwrites our source register,
7922 // allocate a temporary register to hold the old value.
7923 current.isconst=0;
7924 current.wasconst=0;
7925 regs[i].wasconst=0;
7926 delayslot_alloc(&current,i+1);
7927 current.isconst=0;
7928 alloc_reg(&current,i,RTEMP);
7929 }
7930 //current.isconst=0; // DEBUG
cf95b4f0 7931 dops[i].ooo=1;
57871462 7932 ds=1;
7933 break;
7934 case CJUMP:
7935 //current.isconst=0;
7936 //current.wasconst=0;
7937 //regs[i].wasconst=0;
cf95b4f0 7938 clear_const(&current,dops[i].rs1);
7939 clear_const(&current,dops[i].rs2);
7940 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7941 {
7942 alloc_cc(&current,i);
7943 dirty_reg(&current,CCREG);
cf95b4f0 7944 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7945 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7946 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7947 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7948 // The delay slot overwrites one of our conditions.
7949 // Allocate the branch condition registers instead.
57871462 7950 current.isconst=0;
7951 current.wasconst=0;
7952 regs[i].wasconst=0;
cf95b4f0 7953 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7954 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7955 }
e1190b87 7956 else
7957 {
cf95b4f0 7958 dops[i].ooo=1;
e1190b87 7959 delayslot_alloc(&current,i+1);
7960 }
57871462 7961 }
7962 else
cf95b4f0 7963 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7964 {
7965 alloc_cc(&current,i);
7966 dirty_reg(&current,CCREG);
cf95b4f0 7967 alloc_reg(&current,i,dops[i].rs1);
7968 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7969 // The delay slot overwrites one of our conditions.
7970 // Allocate the branch condition registers instead.
57871462 7971 current.isconst=0;
7972 current.wasconst=0;
7973 regs[i].wasconst=0;
cf95b4f0 7974 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7975 }
e1190b87 7976 else
7977 {
cf95b4f0 7978 dops[i].ooo=1;
e1190b87 7979 delayslot_alloc(&current,i+1);
7980 }
57871462 7981 }
7982 else
7983 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7984 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7985 {
7986 current.isconst=0;
7987 current.wasconst=0;
7988 regs[i].wasconst=0;
7989 alloc_cc(&current,i);
7990 dirty_reg(&current,CCREG);
cf95b4f0 7991 alloc_reg(&current,i,dops[i].rs1);
7992 alloc_reg(&current,i,dops[i].rs2);
57871462 7993 }
7994 else
cf95b4f0 7995 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7996 {
7997 current.isconst=0;
7998 current.wasconst=0;
7999 regs[i].wasconst=0;
8000 alloc_cc(&current,i);
8001 dirty_reg(&current,CCREG);
cf95b4f0 8002 alloc_reg(&current,i,dops[i].rs1);
57871462 8003 }
8004 ds=1;
8005 //current.isconst=0;
8006 break;
8007 case SJUMP:
8008 //current.isconst=0;
8009 //current.wasconst=0;
8010 //regs[i].wasconst=0;
cf95b4f0 8011 clear_const(&current,dops[i].rs1);
8012 clear_const(&current,dops[i].rt1);
8013 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
8014 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 8015 {
8016 alloc_cc(&current,i);
8017 dirty_reg(&current,CCREG);
cf95b4f0 8018 alloc_reg(&current,i,dops[i].rs1);
8019 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 8020 alloc_reg(&current,i,31);
8021 dirty_reg(&current,31);
57871462 8022 //#ifdef REG_PREFETCH
8023 //alloc_reg(&current,i,PTEMP);
8024 //#endif
57871462 8025 }
cf95b4f0 8026 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
8027 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 8028 // Allocate the branch condition registers instead.
57871462 8029 current.isconst=0;
8030 current.wasconst=0;
8031 regs[i].wasconst=0;
cf95b4f0 8032 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 8033 }
e1190b87 8034 else
8035 {
cf95b4f0 8036 dops[i].ooo=1;
e1190b87 8037 delayslot_alloc(&current,i+1);
8038 }
57871462 8039 }
8040 else
8041 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 8042 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 8043 {
8044 current.isconst=0;
8045 current.wasconst=0;
8046 regs[i].wasconst=0;
8047 alloc_cc(&current,i);
8048 dirty_reg(&current,CCREG);
cf95b4f0 8049 alloc_reg(&current,i,dops[i].rs1);
57871462 8050 }
8051 ds=1;
8052 //current.isconst=0;
8053 break;
57871462 8054 case IMM16:
8055 imm16_alloc(&current,i);
8056 break;
8057 case LOAD:
8058 case LOADLR:
8059 load_alloc(&current,i);
8060 break;
8061 case STORE:
8062 case STORELR:
8063 store_alloc(&current,i);
8064 break;
8065 case ALU:
8066 alu_alloc(&current,i);
8067 break;
8068 case SHIFT:
8069 shift_alloc(&current,i);
8070 break;
8071 case MULTDIV:
8072 multdiv_alloc(&current,i);
8073 break;
8074 case SHIFTIMM:
8075 shiftimm_alloc(&current,i);
8076 break;
8077 case MOV:
8078 mov_alloc(&current,i);
8079 break;
8080 case COP0:
8081 cop0_alloc(&current,i);
8082 break;
8083 case COP1:
81dbbf4c 8084 break;
b9b61529 8085 case COP2:
81dbbf4c 8086 cop2_alloc(&current,i);
57871462 8087 break;
8088 case C1LS:
8089 c1ls_alloc(&current,i);
8090 break;
b9b61529 8091 case C2LS:
8092 c2ls_alloc(&current,i);
8093 break;
8094 case C2OP:
8095 c2op_alloc(&current,i);
8096 break;
57871462 8097 case SYSCALL:
7139f3c8 8098 case HLECALL:
1e973cb0 8099 case INTCALL:
57871462 8100 syscall_alloc(&current,i);
8101 break;
8102 case SPAN:
8103 pagespan_alloc(&current,i);
8104 break;
8105 }
9f51b4b9 8106
57871462 8107 // Create entry (branch target) regmap
8108 for(hr=0;hr<HOST_REGS;hr++)
8109 {
581335b0 8110 int r,or;
57871462 8111 r=current.regmap[hr];
8112 if(r>=0) {
8113 if(r!=regmap_pre[i][hr]) {
8114 // TODO: delay slot (?)
8115 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9de8a0c3 8116 if(or<0||r>=TEMPREG){
57871462 8117 regs[i].regmap_entry[hr]=-1;
8118 }
8119 else
8120 {
8121 // Just move it to a different register
8122 regs[i].regmap_entry[hr]=r;
8123 // If it was dirty before, it's still dirty
9de8a0c3 8124 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
57871462 8125 }
8126 }
8127 else
8128 {
8129 // Unneeded
8130 if(r==0){
8131 regs[i].regmap_entry[hr]=0;
8132 }
8133 else
7c3a5182 8134 {
8135 assert(r<64);
57871462 8136 if((current.u>>r)&1) {
8137 regs[i].regmap_entry[hr]=-1;
8138 //regs[i].regmap[hr]=-1;
8139 current.regmap[hr]=-1;
8140 }else
8141 regs[i].regmap_entry[hr]=r;
8142 }
57871462 8143 }
8144 } else {
8145 // Branches expect CCREG to be allocated at the target
9f51b4b9 8146 if(regmap_pre[i][hr]==CCREG)
57871462 8147 regs[i].regmap_entry[hr]=CCREG;
8148 else
8149 regs[i].regmap_entry[hr]=-1;
8150 }
8151 }
8152 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8153 }
27727b63 8154
cf95b4f0 8155 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8156 current.waswritten|=1<<dops[i-1].rs1;
8157 current.waswritten&=~(1<<dops[i].rt1);
8158 current.waswritten&=~(1<<dops[i].rt2);
8159 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8160 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8161
57871462 8162 /* Branch post-alloc */
8163 if(i>0)
8164 {
57871462 8165 current.wasdirty=current.dirty;
cf95b4f0 8166 switch(dops[i-1].itype) {
57871462 8167 case UJUMP:
8168 memcpy(&branch_regs[i-1],&current,sizeof(current));
8169 branch_regs[i-1].isconst=0;
8170 branch_regs[i-1].wasconst=0;
cf95b4f0 8171 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8172 alloc_cc(&branch_regs[i-1],i-1);
8173 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8174 if(dops[i-1].rt1==31) { // JAL
57871462 8175 alloc_reg(&branch_regs[i-1],i-1,31);
8176 dirty_reg(&branch_regs[i-1],31);
57871462 8177 }
8178 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8179 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8180 break;
8181 case RJUMP:
8182 memcpy(&branch_regs[i-1],&current,sizeof(current));
8183 branch_regs[i-1].isconst=0;
8184 branch_regs[i-1].wasconst=0;
cf95b4f0 8185 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8186 alloc_cc(&branch_regs[i-1],i-1);
8187 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8188 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8189 if(dops[i-1].rt1!=0) { // JALR
8190 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8191 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8192 }
8193 #ifdef USE_MINI_HT
cf95b4f0 8194 if(dops[i-1].rs1==31) { // JALR
57871462 8195 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8196 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8197 }
8198 #endif
8199 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8200 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8201 break;
8202 case CJUMP:
cf95b4f0 8203 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8204 {
8205 alloc_cc(&current,i-1);
8206 dirty_reg(&current,CCREG);
cf95b4f0 8207 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8208 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8209 // The delay slot overwrote one of our conditions
8210 // Delay slot goes after the test (in order)
cf95b4f0 8211 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8212 current.u|=1;
57871462 8213 delayslot_alloc(&current,i);
8214 current.isconst=0;
8215 }
8216 else
8217 {
cf95b4f0 8218 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8219 // Alloc the branch condition registers
cf95b4f0 8220 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8221 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8222 }
8223 memcpy(&branch_regs[i-1],&current,sizeof(current));
8224 branch_regs[i-1].isconst=0;
8225 branch_regs[i-1].wasconst=0;
8226 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8227 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8228 }
8229 else
cf95b4f0 8230 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8231 {
8232 alloc_cc(&current,i-1);
8233 dirty_reg(&current,CCREG);
cf95b4f0 8234 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8235 // The delay slot overwrote the branch condition
8236 // Delay slot goes after the test (in order)
cf95b4f0 8237 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8238 current.u|=1;
57871462 8239 delayslot_alloc(&current,i);
8240 current.isconst=0;
8241 }
8242 else
8243 {
cf95b4f0 8244 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8245 // Alloc the branch condition register
cf95b4f0 8246 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8247 }
8248 memcpy(&branch_regs[i-1],&current,sizeof(current));
8249 branch_regs[i-1].isconst=0;
8250 branch_regs[i-1].wasconst=0;
8251 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8252 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8253 }
8254 else
8255 // Alloc the delay slot in case the branch is taken
cf95b4f0 8256 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8257 {
8258 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8259 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8260 alloc_cc(&branch_regs[i-1],i);
8261 dirty_reg(&branch_regs[i-1],CCREG);
8262 delayslot_alloc(&branch_regs[i-1],i);
8263 branch_regs[i-1].isconst=0;
8264 alloc_reg(&current,i,CCREG); // Not taken path
8265 dirty_reg(&current,CCREG);
8266 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8267 }
8268 else
cf95b4f0 8269 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8270 {
8271 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8272 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8273 alloc_cc(&branch_regs[i-1],i);
8274 dirty_reg(&branch_regs[i-1],CCREG);
8275 delayslot_alloc(&branch_regs[i-1],i);
8276 branch_regs[i-1].isconst=0;
8277 alloc_reg(&current,i,CCREG); // Not taken path
8278 dirty_reg(&current,CCREG);
8279 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8280 }
8281 break;
8282 case SJUMP:
cf95b4f0 8283 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8284 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8285 {
8286 alloc_cc(&current,i-1);
8287 dirty_reg(&current,CCREG);
cf95b4f0 8288 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8289 // The delay slot overwrote the branch condition
8290 // Delay slot goes after the test (in order)
cf95b4f0 8291 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8292 current.u|=1;
57871462 8293 delayslot_alloc(&current,i);
8294 current.isconst=0;
8295 }
8296 else
8297 {
cf95b4f0 8298 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8299 // Alloc the branch condition register
cf95b4f0 8300 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8301 }
8302 memcpy(&branch_regs[i-1],&current,sizeof(current));
8303 branch_regs[i-1].isconst=0;
8304 branch_regs[i-1].wasconst=0;
8305 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8306 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8307 }
8308 else
8309 // Alloc the delay slot in case the branch is taken
cf95b4f0 8310 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8311 {
8312 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8313 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8314 alloc_cc(&branch_regs[i-1],i);
8315 dirty_reg(&branch_regs[i-1],CCREG);
8316 delayslot_alloc(&branch_regs[i-1],i);
8317 branch_regs[i-1].isconst=0;
8318 alloc_reg(&current,i,CCREG); // Not taken path
8319 dirty_reg(&current,CCREG);
8320 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8321 }
8322 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8323 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8324 alloc_reg(&branch_regs[i-1],i-1,31);
8325 dirty_reg(&branch_regs[i-1],31);
57871462 8326 }
8327 break;
57871462 8328 }
8329
fe807a8a 8330 if (dops[i-1].is_ujump)
57871462 8331 {
cf95b4f0 8332 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8333 {
8334 // Subroutine call will return here, don't alloc any registers
57871462 8335 current.dirty=0;
8336 clear_all_regs(current.regmap);
8337 alloc_reg(&current,i,CCREG);
8338 dirty_reg(&current,CCREG);
8339 }
8340 else if(i+1<slen)
8341 {
8342 // Internal branch will jump here, match registers to caller
57871462 8343 current.dirty=0;
8344 clear_all_regs(current.regmap);
8345 alloc_reg(&current,i,CCREG);
8346 dirty_reg(&current,CCREG);
8347 for(j=i-1;j>=0;j--)
8348 {
8349 if(ba[j]==start+i*4+4) {
8350 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8351 current.dirty=branch_regs[j].dirty;
8352 break;
8353 }
8354 }
8355 while(j>=0) {
8356 if(ba[j]==start+i*4+4) {
8357 for(hr=0;hr<HOST_REGS;hr++) {
8358 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8359 current.regmap[hr]=-1;
8360 }
57871462 8361 current.dirty&=branch_regs[j].dirty;
8362 }
8363 }
8364 j--;
8365 }
8366 }
8367 }
8368 }
8369
8370 // Count cycles in between branches
2330734f 8371 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8372 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8373 {
8374 cc=0;
8375 }
71e490c5 8376#if !defined(DRC_DBG)
cf95b4f0 8377 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8378 {
81dbbf4c 8379 // this should really be removed since the real stalls have been implemented,
8380 // but doing so causes sizeable perf regression against the older version
8381 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8382 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8383 }
cf95b4f0 8384 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8385 {
8386 cc+=4;
8387 }
cf95b4f0 8388 else if(dops[i].itype==C2LS)
fb407447 8389 {
81dbbf4c 8390 // same as with C2OP
32631e6a 8391 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8392 }
8393#endif
57871462 8394 else
8395 {
8396 cc++;
8397 }
8398
cf95b4f0 8399 if(!dops[i].is_ds) {
57871462 8400 regs[i].dirty=current.dirty;
8401 regs[i].isconst=current.isconst;
40fca85b 8402 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8403 }
8404 for(hr=0;hr<HOST_REGS;hr++) {
8405 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8406 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8407 regs[i].wasconst&=~(1<<hr);
8408 }
8409 }
8410 }
8411 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8412 regs[i].waswritten=current.waswritten;
57871462 8413 }
9f51b4b9 8414
57871462 8415 /* Pass 4 - Cull unused host registers */
9f51b4b9 8416
57871462 8417 uint64_t nr=0;
9f51b4b9 8418
57871462 8419 for (i=slen-1;i>=0;i--)
8420 {
8421 int hr;
fe807a8a 8422 if(dops[i].is_jump)
57871462 8423 {
8424 if(ba[i]<start || ba[i]>=(start+slen*4))
8425 {
8426 // Branch out of this block, don't need anything
8427 nr=0;
8428 }
8429 else
8430 {
8431 // Internal branch
8432 // Need whatever matches the target
8433 nr=0;
8434 int t=(ba[i]-start)>>2;
8435 for(hr=0;hr<HOST_REGS;hr++)
8436 {
8437 if(regs[i].regmap_entry[hr]>=0) {
8438 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8439 }
8440 }
8441 }
8442 // Conditional branch may need registers for following instructions
fe807a8a 8443 if (!dops[i].is_ujump)
57871462 8444 {
8445 if(i<slen-2) {
8446 nr|=needed_reg[i+2];
8447 for(hr=0;hr<HOST_REGS;hr++)
8448 {
8449 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8450 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8451 }
8452 }
8453 }
8454 // Don't need stuff which is overwritten
f5955059 8455 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8456 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8457 // Merge in delay slot
8458 for(hr=0;hr<HOST_REGS;hr++)
8459 {
9de8a0c3 8460 if(dops[i+1].rt1&&dops[i+1].rt1==regs[i].regmap[hr]) nr&=~(1<<hr);
8461 if(dops[i+1].rt2&&dops[i+1].rt2==regs[i].regmap[hr]) nr&=~(1<<hr);
cf95b4f0 8462 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8463 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8464 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8465 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8466 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8467 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8468 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8469 }
8470 if(dops[i+1].is_store) {
57871462 8471 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8472 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8473 }
8474 }
8475 }
cf95b4f0 8476 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8477 {
8478 // SYSCALL instruction (software interrupt)
8479 nr=0;
8480 }
cf95b4f0 8481 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8482 {
8483 // ERET instruction (return from interrupt)
8484 nr=0;
8485 }
8486 else // Non-branch
8487 {
8488 if(i<slen-1) {
8489 for(hr=0;hr<HOST_REGS;hr++) {
8490 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8491 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8492 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8493 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8494 }
8495 }
8496 }
8497 for(hr=0;hr<HOST_REGS;hr++)
8498 {
8499 // Overwritten registers are not needed
9de8a0c3 8500 if(dops[i].rt1&&dops[i].rt1==regs[i].regmap[hr]) nr&=~(1<<hr);
8501 if(dops[i].rt2&&dops[i].rt2==regs[i].regmap[hr]) nr&=~(1<<hr);
8502 if(FTEMP==regs[i].regmap[hr]) nr&=~(1<<hr);
57871462 8503 // Source registers are needed
cf95b4f0 8504 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8505 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8506 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8507 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8508 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8509 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8510 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8511 }
8512 if(dops[i].is_store) {
57871462 8513 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8514 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8515 }
8516 // Don't store a register immediately after writing it,
8517 // may prevent dual-issue.
8518 // But do so if this is a branch target, otherwise we
8519 // might have to load the register before the branch.
cf95b4f0 8520 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8521 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
9de8a0c3 8522 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
8523 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
57871462 8524 }
7c3a5182 8525 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
9de8a0c3 8526 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8527 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
57871462 8528 }
8529 }
8530 }
8531 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8532 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8533 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8534 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8535 }
8536 // Save it
8537 needed_reg[i]=nr;
9f51b4b9 8538
57871462 8539 // Deallocate unneeded registers
8540 for(hr=0;hr<HOST_REGS;hr++)
8541 {
8542 if(!((nr>>hr)&1)) {
8543 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8544 if(dops[i].is_jump)
57871462 8545 {
37387d8b 8546 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8547 if (dops[i+1].is_load || dops[i+1].is_store)
8548 map1 = ROREG;
8549 if (dops[i+1].is_store)
8550 map2 = INVCP;
8551 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8552 temp = FTEMP;
9de8a0c3 8553 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8554 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8555 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 8556 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8557 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
57871462 8558 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8559 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8560 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8561 {
8562 regs[i].regmap[hr]=-1;
8563 regs[i].isconst&=~(1<<hr);
a550c61c 8564 regs[i].dirty&=~(1<<hr);
8565 regs[i+1].wasdirty&=~(1<<hr);
9de8a0c3 8566 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
8567 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
8568 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
cf95b4f0 8569 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
9de8a0c3 8570 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
57871462 8571 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8572 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8573 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8574 {
8575 branch_regs[i].regmap[hr]=-1;
8576 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8577 if (!dops[i].is_ujump)
57871462 8578 {
fe807a8a 8579 if (i < slen-2) {
57871462 8580 regmap_pre[i+2][hr]=-1;
79c75f1b 8581 regs[i+2].wasconst&=~(1<<hr);
57871462 8582 }
8583 }
8584 }
8585 }
8586 }
8587 else
8588 {
8589 // Non-branch
8590 if(i>0)
8591 {
37387d8b 8592 int map1 = -1, map2 = -1, temp=-1;
8593 if (dops[i].is_load || dops[i].is_store)
8594 map1 = ROREG;
8595 if (dops[i].is_store)
8596 map2 = INVCP;
8597 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8598 temp = FTEMP;
9de8a0c3 8599 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
cf95b4f0 8600 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
9de8a0c3 8601 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8602 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8603 regs[i].regmap[hr] != CCREG)
57871462 8604 {
cf95b4f0 8605 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8606 assert(regs[i].regmap[hr]<64);
afec9d44 8607 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8608 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8609 {
c43b5311 8610 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8611 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8612 }
8613 regmap_pre[i+1][hr]=-1;
8614 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8615 regs[i+1].wasconst&=~(1<<hr);
57871462 8616 }
8617 regs[i].regmap[hr]=-1;
8618 regs[i].isconst&=~(1<<hr);
a550c61c 8619 regs[i].dirty&=~(1<<hr);
8620 regs[i+1].wasdirty&=~(1<<hr);
57871462 8621 }
8622 }
8623 }
3968e69e 8624 } // if needed
8625 } // for hr
57871462 8626 }
9f51b4b9 8627
57871462 8628 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8629
57871462 8630 // If a register is allocated during a loop, try to allocate it for the
8631 // entire loop, if possible. This avoids loading/storing registers
8632 // inside of the loop.
9f51b4b9 8633
57871462 8634 signed char f_regmap[HOST_REGS];
8635 clear_all_regs(f_regmap);
8636 for(i=0;i<slen-1;i++)
8637 {
cf95b4f0 8638 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8639 {
9f51b4b9 8640 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8641 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8642 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8643 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8644 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8645 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8646 {
8647 int t=(ba[i]-start)>>2;
fe807a8a 8648 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8649 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8650 for(hr=0;hr<HOST_REGS;hr++)
8651 {
7c3a5182 8652 if(regs[i].regmap[hr]>=0) {
b372a952 8653 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8654 // dealloc old register
8655 int n;
8656 for(n=0;n<HOST_REGS;n++)
8657 {
8658 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8659 }
8660 // and alloc new one
8661 f_regmap[hr]=regs[i].regmap[hr];
8662 }
8663 }
7c3a5182 8664 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8665 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8666 // dealloc old register
8667 int n;
8668 for(n=0;n<HOST_REGS;n++)
8669 {
8670 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8671 }
8672 // and alloc new one
8673 f_regmap[hr]=branch_regs[i].regmap[hr];
8674 }
8675 }
cf95b4f0 8676 if(dops[i].ooo) {
9f51b4b9 8677 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8678 f_regmap[hr]=branch_regs[i].regmap[hr];
8679 }else{
9f51b4b9 8680 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8681 f_regmap[hr]=branch_regs[i].regmap[hr];
8682 }
8683 // Avoid dirty->clean transition
e1190b87 8684 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8685 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8686 #endif
8687 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8688 // case above, however it's always a good idea. We can't hoist the
8689 // load if the register was already allocated, so there's no point
8690 // wasting time analyzing most of these cases. It only "succeeds"
8691 // when the mapping was different and the load can be replaced with
8692 // a mov, which is of negligible benefit. So such cases are
8693 // skipped below.
57871462 8694 if(f_regmap[hr]>0) {
198df76f 8695 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8696 int r=f_regmap[hr];
8697 for(j=t;j<=i;j++)
8698 {
8699 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8700 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8701 assert(r < 64);
9de8a0c3 8702 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
57871462 8703 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8704 int k;
8705 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
670c0f22 8706 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
57871462 8707 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
57871462 8708 k=i;
8709 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8710 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8711 //printf("no free regs for store %x\n",start+(k-1)*4);
8712 break;
57871462 8713 }
57871462 8714 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8715 //printf("no-match due to different register\n");
8716 break;
8717 }
fe807a8a 8718 if (dops[k-2].is_jump) {
57871462 8719 //printf("no-match due to branch\n");
8720 break;
8721 }
8722 // call/ret fast path assumes no registers allocated
cf95b4f0 8723 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8724 break;
8725 }
57871462 8726 k--;
8727 }
57871462 8728 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8729 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8730 while(k<i) {
8731 regs[k].regmap_entry[hr]=f_regmap[hr];
8732 regs[k].regmap[hr]=f_regmap[hr];
8733 regmap_pre[k+1][hr]=f_regmap[hr];
8734 regs[k].wasdirty&=~(1<<hr);
8735 regs[k].dirty&=~(1<<hr);
8736 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8737 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8738 regs[k].wasconst&=~(1<<hr);
8739 regs[k].isconst&=~(1<<hr);
8740 k++;
8741 }
8742 }
8743 else {
8744 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8745 break;
8746 }
8747 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8748 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8749 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8750 regs[i].regmap_entry[hr]=f_regmap[hr];
8751 regs[i].regmap[hr]=f_regmap[hr];
8752 regs[i].wasdirty&=~(1<<hr);
8753 regs[i].dirty&=~(1<<hr);
8754 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8755 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8756 regs[i].wasconst&=~(1<<hr);
8757 regs[i].isconst&=~(1<<hr);
8758 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8759 branch_regs[i].wasdirty&=~(1<<hr);
8760 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8761 branch_regs[i].regmap[hr]=f_regmap[hr];
8762 branch_regs[i].dirty&=~(1<<hr);
8763 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8764 branch_regs[i].wasconst&=~(1<<hr);
8765 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8766 if (!dops[i].is_ujump) {
57871462 8767 regmap_pre[i+2][hr]=f_regmap[hr];
8768 regs[i+2].wasdirty&=~(1<<hr);
8769 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8770 }
8771 }
8772 }
8773 for(k=t;k<j;k++) {
e1190b87 8774 // Alloc register clean at beginning of loop,
8775 // but may dirty it in pass 6
57871462 8776 regs[k].regmap_entry[hr]=f_regmap[hr];
8777 regs[k].regmap[hr]=f_regmap[hr];
57871462 8778 regs[k].dirty&=~(1<<hr);
8779 regs[k].wasconst&=~(1<<hr);
8780 regs[k].isconst&=~(1<<hr);
fe807a8a 8781 if (dops[k].is_jump) {
e1190b87 8782 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8783 branch_regs[k].regmap[hr]=f_regmap[hr];
8784 branch_regs[k].dirty&=~(1<<hr);
8785 branch_regs[k].wasconst&=~(1<<hr);
8786 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8787 if (!dops[k].is_ujump) {
e1190b87 8788 regmap_pre[k+2][hr]=f_regmap[hr];
8789 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8790 }
8791 }
8792 else
8793 {
8794 regmap_pre[k+1][hr]=f_regmap[hr];
8795 regs[k+1].wasdirty&=~(1<<hr);
8796 }
57871462 8797 }
8798 if(regs[j].regmap[hr]==f_regmap[hr])
8799 regs[j].regmap_entry[hr]=f_regmap[hr];
8800 break;
8801 }
8802 if(j==i) break;
8803 if(regs[j].regmap[hr]>=0)
8804 break;
8805 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8806 //printf("no-match due to different register\n");
8807 break;
8808 }
fe807a8a 8809 if (dops[j].is_ujump)
e1190b87 8810 {
8811 // Stop on unconditional branch
8812 break;
8813 }
cf95b4f0 8814 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8815 {
cf95b4f0 8816 if(dops[j].ooo) {
9f51b4b9 8817 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8818 break;
8819 }else{
9f51b4b9 8820 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8821 break;
8822 }
8823 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8824 //printf("no-match due to different register (branch)\n");
57871462 8825 break;
8826 }
8827 }
e1190b87 8828 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8829 //printf("No free regs for store %x\n",start+j*4);
8830 break;
8831 }
ad49de89 8832 assert(f_regmap[hr]<64);
57871462 8833 }
8834 }
8835 }
8836 }
8837 }
8838 }else{
198df76f 8839 // Non branch or undetermined branch target
57871462 8840 for(hr=0;hr<HOST_REGS;hr++)
8841 {
8842 if(hr!=EXCLUDE_REG) {
7c3a5182 8843 if(regs[i].regmap[hr]>=0) {
b372a952 8844 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8845 // dealloc old register
8846 int n;
8847 for(n=0;n<HOST_REGS;n++)
8848 {
8849 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8850 }
8851 // and alloc new one
8852 f_regmap[hr]=regs[i].regmap[hr];
8853 }
8854 }
57871462 8855 }
8856 }
8857 // Try to restore cycle count at branch targets
cf95b4f0 8858 if(dops[i].bt) {
57871462 8859 for(j=i;j<slen-1;j++) {
8860 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8861 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8862 //printf("no free regs for store %x\n",start+j*4);
8863 break;
57871462 8864 }
57871462 8865 }
8866 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8867 int k=i;
8868 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8869 while(k<j) {
8870 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8871 regs[k].regmap[HOST_CCREG]=CCREG;
8872 regmap_pre[k+1][HOST_CCREG]=CCREG;
8873 regs[k+1].wasdirty|=1<<HOST_CCREG;
8874 regs[k].dirty|=1<<HOST_CCREG;
8875 regs[k].wasconst&=~(1<<HOST_CCREG);
8876 regs[k].isconst&=~(1<<HOST_CCREG);
8877 k++;
8878 }
9f51b4b9 8879 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8880 }
8881 // Work backwards from the branch target
8882 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8883 {
8884 //printf("Extend backwards\n");
8885 int k;
8886 k=i;
8887 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8888 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8889 //printf("no free regs for store %x\n",start+(k-1)*4);
8890 break;
57871462 8891 }
57871462 8892 k--;
8893 }
8894 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8895 //printf("Extend CC, %x ->\n",start+k*4);
8896 while(k<=i) {
8897 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8898 regs[k].regmap[HOST_CCREG]=CCREG;
8899 regmap_pre[k+1][HOST_CCREG]=CCREG;
8900 regs[k+1].wasdirty|=1<<HOST_CCREG;
8901 regs[k].dirty|=1<<HOST_CCREG;
8902 regs[k].wasconst&=~(1<<HOST_CCREG);
8903 regs[k].isconst&=~(1<<HOST_CCREG);
8904 k++;
8905 }
8906 }
8907 else {
8908 //printf("Fail Extend CC, %x ->\n",start+k*4);
8909 }
8910 }
8911 }
cf95b4f0 8912 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8913 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8914 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8915 {
8916 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8917 }
8918 }
8919 }
9f51b4b9 8920
57871462 8921 // This allocates registers (if possible) one instruction prior
8922 // to use, which can avoid a load-use penalty on certain CPUs.
8923 for(i=0;i<slen-1;i++)
8924 {
fe807a8a 8925 if (!i || !dops[i-1].is_jump)
57871462 8926 {
cf95b4f0 8927 if(!dops[i+1].bt)
57871462 8928 {
cf95b4f0 8929 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8930 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8931 {
cf95b4f0 8932 if(dops[i+1].rs1) {
8933 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8934 {
8935 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8936 {
8937 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8938 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8939 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8940 regs[i].isconst&=~(1<<hr);
8941 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8942 constmap[i][hr]=constmap[i+1][hr];
8943 regs[i+1].wasdirty&=~(1<<hr);
8944 regs[i].dirty&=~(1<<hr);
8945 }
8946 }
8947 }
cf95b4f0 8948 if(dops[i+1].rs2) {
8949 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8950 {
8951 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8952 {
8953 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8954 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8955 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8956 regs[i].isconst&=~(1<<hr);
8957 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8958 constmap[i][hr]=constmap[i+1][hr];
8959 regs[i+1].wasdirty&=~(1<<hr);
8960 regs[i].dirty&=~(1<<hr);
8961 }
8962 }
8963 }
198df76f 8964 // Preload target address for load instruction (non-constant)
cf95b4f0 8965 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8966 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8967 {
8968 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8969 {
cf95b4f0 8970 regs[i].regmap[hr]=dops[i+1].rs1;
8971 regmap_pre[i+1][hr]=dops[i+1].rs1;
8972 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8973 regs[i].isconst&=~(1<<hr);
8974 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8975 constmap[i][hr]=constmap[i+1][hr];
8976 regs[i+1].wasdirty&=~(1<<hr);
8977 regs[i].dirty&=~(1<<hr);
8978 }
8979 }
8980 }
9f51b4b9 8981 // Load source into target register
cf95b4f0 8982 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8983 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8984 {
8985 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8986 {
cf95b4f0 8987 regs[i].regmap[hr]=dops[i+1].rs1;
8988 regmap_pre[i+1][hr]=dops[i+1].rs1;
8989 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8990 regs[i].isconst&=~(1<<hr);
8991 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8992 constmap[i][hr]=constmap[i+1][hr];
8993 regs[i+1].wasdirty&=~(1<<hr);
8994 regs[i].dirty&=~(1<<hr);
8995 }
8996 }
8997 }
198df76f 8998 // Address for store instruction (non-constant)
cf95b4f0 8999 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
9000 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
9001 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 9002 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9de8a0c3 9003 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
6cc8d23c 9004 else {
9005 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
9006 regs[i+1].isconst&=~(1<<hr);
9007 }
57871462 9008 assert(hr>=0);
9009 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9010 {
cf95b4f0 9011 regs[i].regmap[hr]=dops[i+1].rs1;
9012 regmap_pre[i+1][hr]=dops[i+1].rs1;
9013 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 9014 regs[i].isconst&=~(1<<hr);
9015 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9016 constmap[i][hr]=constmap[i+1][hr];
9017 regs[i+1].wasdirty&=~(1<<hr);
9018 regs[i].dirty&=~(1<<hr);
9019 }
9020 }
9021 }
cf95b4f0 9022 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
9023 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 9024 int nr;
9025 hr=get_reg(regs[i+1].regmap,FTEMP);
9026 assert(hr>=0);
9027 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9028 {
cf95b4f0 9029 regs[i].regmap[hr]=dops[i+1].rs1;
9030 regmap_pre[i+1][hr]=dops[i+1].rs1;
9031 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 9032 regs[i].isconst&=~(1<<hr);
9033 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9034 constmap[i][hr]=constmap[i+1][hr];
9035 regs[i+1].wasdirty&=~(1<<hr);
9036 regs[i].dirty&=~(1<<hr);
9037 }
9038 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9039 {
9040 // move it to another register
9041 regs[i+1].regmap[hr]=-1;
9042 regmap_pre[i+2][hr]=-1;
9043 regs[i+1].regmap[nr]=FTEMP;
9044 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 9045 regs[i].regmap[nr]=dops[i+1].rs1;
9046 regmap_pre[i+1][nr]=dops[i+1].rs1;
9047 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 9048 regs[i].isconst&=~(1<<nr);
9049 regs[i+1].isconst&=~(1<<nr);
9050 regs[i].dirty&=~(1<<nr);
9051 regs[i+1].wasdirty&=~(1<<nr);
9052 regs[i+1].dirty&=~(1<<nr);
9053 regs[i+2].wasdirty&=~(1<<nr);
9054 }
9055 }
9056 }
cf95b4f0 9057 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
9058 if(dops[i+1].itype==LOAD)
9059 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
9060 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 9061 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 9062 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 9063 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9de8a0c3 9064 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
57871462 9065 }
9066 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 9067 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 9068 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9069 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9070 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9071 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9072 regs[i].isconst&=~(1<<hr);
9073 regs[i+1].wasdirty&=~(1<<hr);
9074 regs[i].dirty&=~(1<<hr);
9075 }
9076 }
9077 }
9078 }
9079 }
9080 }
9081 }
9f51b4b9 9082
57871462 9083 /* Pass 6 - Optimize clean/dirty state */
9084 clean_registers(0,slen-1,1);
9f51b4b9 9085
57871462 9086 /* Pass 7 - Identify 32-bit registers */
04fd948a 9087 for (i=slen-1;i>=0;i--)
9088 {
cf95b4f0 9089 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 9090 {
9091 // Conditional branch
9092 if((source[i]>>16)!=0x1000&&i<slen-2) {
9093 // Mark this address as a branch target since it may be called
9094 // upon return from interrupt
cf95b4f0 9095 dops[i+2].bt=1;
04fd948a 9096 }
9097 }
9098 }
57871462 9099
cf95b4f0 9100 if(dops[slen-1].itype==SPAN) {
9101 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 9102 }
4600ba03 9103
d1150cd6 9104#ifdef REG_ALLOC_PRINT
57871462 9105 /* Debug/disassembly */
57871462 9106 for(i=0;i<slen;i++)
9107 {
9108 printf("U:");
9109 int r;
9110 for(r=1;r<=CCREG;r++) {
9111 if((unneeded_reg[i]>>r)&1) {
9112 if(r==HIREG) printf(" HI");
9113 else if(r==LOREG) printf(" LO");
9114 else printf(" r%d",r);
9115 }
9116 }
57871462 9117 printf("\n");
9118 #if defined(__i386__) || defined(__x86_64__)
9119 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9120 #endif
9121 #ifdef __arm__
9122 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9123 #endif
7c3a5182 9124 #if defined(__i386__) || defined(__x86_64__)
57871462 9125 printf("needs: ");
9126 if(needed_reg[i]&1) printf("eax ");
9127 if((needed_reg[i]>>1)&1) printf("ecx ");
9128 if((needed_reg[i]>>2)&1) printf("edx ");
9129 if((needed_reg[i]>>3)&1) printf("ebx ");
9130 if((needed_reg[i]>>5)&1) printf("ebp ");
9131 if((needed_reg[i]>>6)&1) printf("esi ");
9132 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9133 printf("\n");
57871462 9134 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9135 printf("dirty: ");
9136 if(regs[i].wasdirty&1) printf("eax ");
9137 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9138 if((regs[i].wasdirty>>2)&1) printf("edx ");
9139 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9140 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9141 if((regs[i].wasdirty>>6)&1) printf("esi ");
9142 if((regs[i].wasdirty>>7)&1) printf("edi ");
9143 #endif
9144 #ifdef __arm__
9145 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9146 printf("dirty: ");
9147 if(regs[i].wasdirty&1) printf("r0 ");
9148 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9149 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9150 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9151 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9152 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9153 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9154 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9155 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9156 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9157 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9158 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9159 #endif
9160 printf("\n");
9161 disassemble_inst(i);
9162 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9163 #if defined(__i386__) || defined(__x86_64__)
9164 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9165 if(regs[i].dirty&1) printf("eax ");
9166 if((regs[i].dirty>>1)&1) printf("ecx ");
9167 if((regs[i].dirty>>2)&1) printf("edx ");
9168 if((regs[i].dirty>>3)&1) printf("ebx ");
9169 if((regs[i].dirty>>5)&1) printf("ebp ");
9170 if((regs[i].dirty>>6)&1) printf("esi ");
9171 if((regs[i].dirty>>7)&1) printf("edi ");
9172 #endif
9173 #ifdef __arm__
9174 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9175 if(regs[i].dirty&1) printf("r0 ");
9176 if((regs[i].dirty>>1)&1) printf("r1 ");
9177 if((regs[i].dirty>>2)&1) printf("r2 ");
9178 if((regs[i].dirty>>3)&1) printf("r3 ");
9179 if((regs[i].dirty>>4)&1) printf("r4 ");
9180 if((regs[i].dirty>>5)&1) printf("r5 ");
9181 if((regs[i].dirty>>6)&1) printf("r6 ");
9182 if((regs[i].dirty>>7)&1) printf("r7 ");
9183 if((regs[i].dirty>>8)&1) printf("r8 ");
9184 if((regs[i].dirty>>9)&1) printf("r9 ");
9185 if((regs[i].dirty>>10)&1) printf("r10 ");
9186 if((regs[i].dirty>>12)&1) printf("r12 ");
9187 #endif
9188 printf("\n");
9189 if(regs[i].isconst) {
9190 printf("constants: ");
9191 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9192 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9193 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9194 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9195 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9196 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9197 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9198 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9199 #endif
7c3a5182 9200 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9201 int r;
9202 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9203 if ((regs[i].isconst >> r) & 1)
9204 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9205 #endif
9206 printf("\n");
9207 }
fe807a8a 9208 if(dops[i].is_jump) {
57871462 9209 #if defined(__i386__) || defined(__x86_64__)
9210 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9211 if(branch_regs[i].dirty&1) printf("eax ");
9212 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9213 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9214 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9215 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9216 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9217 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9218 #endif
9219 #ifdef __arm__
9220 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9221 if(branch_regs[i].dirty&1) printf("r0 ");
9222 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9223 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9224 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9225 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9226 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9227 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9228 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9229 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9230 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9231 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9232 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9233 #endif
57871462 9234 }
9235 }
d1150cd6 9236#endif // REG_ALLOC_PRINT
57871462 9237
9238 /* Pass 8 - Assembly */
9239 linkcount=0;stubcount=0;
9240 ds=0;is_delayslot=0;
57871462 9241 u_int dirty_pre=0;
d148d265 9242 void *beginning=start_block();
57871462 9243 if((u_int)addr&1) {
9244 ds=1;
9245 pagespan_ds();
9246 }
df4dc2b1 9247 void *instr_addr0_override = NULL;
9ad4d757 9248
9ad4d757 9249 if (start == 0x80030000) {
3968e69e 9250 // nasty hack for the fastbios thing
96186eba 9251 // override block entry to this code
df4dc2b1 9252 instr_addr0_override = out;
9ad4d757 9253 emit_movimm(start,0);
96186eba 9254 // abuse io address var as a flag that we
9255 // have already returned here once
643aeae3 9256 emit_readword(&address,1);
9257 emit_writeword(0,&pcaddr);
9258 emit_writeword(0,&address);
9ad4d757 9259 emit_cmp(0,1);
3968e69e 9260 #ifdef __aarch64__
9261 emit_jeq(out + 4*2);
2a014d73 9262 emit_far_jump(new_dyna_leave);
3968e69e 9263 #else
643aeae3 9264 emit_jne(new_dyna_leave);
3968e69e 9265 #endif
9ad4d757 9266 }
57871462 9267 for(i=0;i<slen;i++)
9268 {
9de8a0c3 9269 __builtin_prefetch(regs[i+1].regmap);
670c0f22 9270 check_regmap(regmap_pre[i]);
9271 check_regmap(regs[i].regmap_entry);
9272 check_regmap(regs[i].regmap);
57871462 9273 //if(ds) printf("ds: ");
4600ba03 9274 disassemble_inst(i);
57871462 9275 if(ds) {
9276 ds=0; // Skip delay slot
cf95b4f0 9277 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9278 instr_addr[i] = NULL;
57871462 9279 } else {
ffb0b9e0 9280 speculate_register_values(i);
57871462 9281 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9282 if (i < 2 || !dops[i-2].is_ujump)
57871462 9283 {
ad49de89 9284 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9285 }
fe807a8a 9286 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9287 dirty_pre=branch_regs[i].dirty;
9288 }else{
f776eb14 9289 dirty_pre=regs[i].dirty;
9290 }
57871462 9291 #endif
9292 // write back
fe807a8a 9293 if (i < 2 || !dops[i-2].is_ujump)
57871462 9294 {
ad49de89 9295 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9296 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9297 }
9298 // branch target entry point
df4dc2b1 9299 instr_addr[i] = out;
57871462 9300 assem_debug("<->\n");
2330734f 9301 drc_dbg_emit_do_cmp(i, ccadj[i]);
7f94b097 9302 if (clear_hack_addr) {
9303 emit_movimm(0, 0);
9304 emit_writeword(0, &hack_addr);
9305 clear_hack_addr = 0;
9306 }
dd114d7d 9307
57871462 9308 // load regs
9309 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9310 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9311 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9312 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9313 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9314 if(dops[i].is_jump)
57871462 9315 {
9316 // Load the delay slot registers if necessary
cf95b4f0 9317 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9318 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9319 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9320 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9321 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9322 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9323 if (dops[i+1].is_store)
ad49de89 9324 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9325 }
9326 else if(i+1<slen)
9327 {
9328 // Preload registers for following instruction
cf95b4f0 9329 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9330 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9331 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9332 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9333 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9334 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9335 }
9336 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9337 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9338 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9339 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9340 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9341 if (dops[i].is_store)
ad49de89 9342 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9343
9344 ds = assemble(i, &regs[i], ccadj[i]);
9345
fe807a8a 9346 if (dops[i].is_ujump)
57871462 9347 literal_pool(1024);
9348 else
9349 literal_pool_jumpover(256);
9350 }
9351 }
3d680478 9352
9353 assert(slen > 0);
cf95b4f0 9354 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9355 // no ending needed for this block since INTCALL never returns
9356 }
57871462 9357 // If the block did not end with an unconditional branch,
9358 // add a jump to the next instruction.
3d680478 9359 else if (i > 1) {
fe807a8a 9360 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9361 assert(!dops[i-1].is_jump);
57871462 9362 assert(i==slen);
cf95b4f0 9363 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9364 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9365 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9366 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9367 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9368 }
fe807a8a 9369 else
57871462 9370 {
ad49de89 9371 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9372 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9373 }
643aeae3 9374 add_to_linker(out,start+i*4,0);
57871462 9375 emit_jmp(0);
9376 }
9377 }
9378 else
9379 {
9380 assert(i>0);
fe807a8a 9381 assert(!dops[i-1].is_jump);
ad49de89 9382 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9383 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9384 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9385 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9386 add_to_linker(out,start+i*4,0);
57871462 9387 emit_jmp(0);
9388 }
9389
9390 // TODO: delay slot stubs?
9391 // Stubs
9392 for(i=0;i<stubcount;i++)
9393 {
b14b6a8f 9394 switch(stubs[i].type)
57871462 9395 {
9396 case LOADB_STUB:
9397 case LOADH_STUB:
9398 case LOADW_STUB:
9399 case LOADD_STUB:
9400 case LOADBU_STUB:
9401 case LOADHU_STUB:
9402 do_readstub(i);break;
9403 case STOREB_STUB:
9404 case STOREH_STUB:
9405 case STOREW_STUB:
9406 case STORED_STUB:
9407 do_writestub(i);break;
9408 case CC_STUB:
9409 do_ccstub(i);break;
9410 case INVCODE_STUB:
9411 do_invstub(i);break;
9412 case FP_STUB:
9413 do_cop1stub(i);break;
9414 case STORELR_STUB:
9415 do_unalignedwritestub(i);break;
9416 }
9417 }
9418
9ad4d757 9419 if (instr_addr0_override)
9420 instr_addr[0] = instr_addr0_override;
9421
57871462 9422 /* Pass 9 - Linker */
9423 for(i=0;i<linkcount;i++)
9424 {
643aeae3 9425 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9426 literal_pool(64);
643aeae3 9427 if (!link_addr[i].ext)
57871462 9428 {
643aeae3 9429 void *stub = out;
9430 void *addr = check_addr(link_addr[i].target);
9431 emit_extjump(link_addr[i].addr, link_addr[i].target);
9432 if (addr) {
9433 set_jump_target(link_addr[i].addr, addr);
3d680478 9434 add_jump_out(link_addr[i].target,stub);
57871462 9435 }
643aeae3 9436 else
9437 set_jump_target(link_addr[i].addr, stub);
57871462 9438 }
9439 else
9440 {
9441 // Internal branch
643aeae3 9442 int target=(link_addr[i].target-start)>>2;
57871462 9443 assert(target>=0&&target<slen);
9444 assert(instr_addr[target]);
9445 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9446 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9447 //#else
643aeae3 9448 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9449 //#endif
9450 }
9451 }
3d680478 9452
9453 u_int source_len = slen*4;
cf95b4f0 9454 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9455 // no need to treat the last instruction as compiled
9456 // as interpreter fully handles it
9457 source_len -= 4;
9458
9459 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9460 copy = shadow;
9461
57871462 9462 // External Branch Targets (jump_in)
57871462 9463 for(i=0;i<slen;i++)
9464 {
cf95b4f0 9465 if(dops[i].bt||i==0)
57871462 9466 {
9467 if(instr_addr[i]) // TODO - delay slots (=null)
9468 {
9469 u_int vaddr=start+i*4;
94d23bb9 9470 u_int page=get_page(vaddr);
9471 u_int vpage=get_vpage(vaddr);
57871462 9472 literal_pool(256);
57871462 9473 {
df4dc2b1 9474 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9475 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9476 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9477 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9478 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9479 // If there was an existing entry in the hash table,
9480 // replace it with the new address.
9481 // Don't add new entries. We'll insert the
9482 // ones that actually get used in check_addr().
df4dc2b1 9483 struct ht_entry *ht_bin = hash_table_get(vaddr);
9484 if (ht_bin->vaddr[0] == vaddr)
9485 ht_bin->tcaddr[0] = entry_point;
9486 if (ht_bin->vaddr[1] == vaddr)
9487 ht_bin->tcaddr[1] = entry_point;
57871462 9488 }
57871462 9489 }
9490 }
9491 }
9492 // Write out the literal pool if necessary
9493 literal_pool(0);
9494 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9495 // Align code
9496 if(((u_int)out)&7) emit_addnop(13);
9497 #endif
01d26796 9498 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9499 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9500 memcpy(copy, source, source_len);
9501 copy += source_len;
9f51b4b9 9502
d148d265 9503 end_block(beginning);
9f51b4b9 9504
57871462 9505 // If we're within 256K of the end of the buffer,
9506 // start over from the beginning. (Is 256K enough?)
2a014d73 9507 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9508 out = ndrc->translation_cache;
9f51b4b9 9509
57871462 9510 // Trap writes to any of the pages we compiled
9511 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9512 invalid_code[i]=0;
57871462 9513 }
9be4ba64 9514 inv_code_start=inv_code_end=~0;
71e490c5 9515
b96d3df7 9516 // for PCSX we need to mark all mirrors too
b12c9fb8 9517 if(get_page(start)<(RAM_SIZE>>12))
9518 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9519 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9520 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9521 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9522
57871462 9523 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9524
2a014d73 9525 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9526 while(expirep!=end)
9527 {
9528 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9529 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9530 uintptr_t base_offs_s = base_offs >> shift;
57871462 9531 inv_debug("EXP: Phase %d\n",expirep);
9532 switch((expirep>>11)&3)
9533 {
9534 case 0:
9535 // Clear jump_in and jump_dirty
943f42f3 9536 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9537 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9538 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9539 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9540 break;
9541 case 1:
9542 // Clear pointers
943f42f3 9543 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9544 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9545 break;
9546 case 2:
9547 // Clear hash table
9548 for(i=0;i<32;i++) {
df4dc2b1 9549 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9550 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9551 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9552 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9553 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9554 ht_bin->vaddr[1] = -1;
9555 ht_bin->tcaddr[1] = NULL;
9556 }
943f42f3 9557 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9558 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9559 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9560 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9561 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9562 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9563 ht_bin->vaddr[1] = -1;
9564 ht_bin->tcaddr[1] = NULL;
57871462 9565 }
9566 }
9567 break;
9568 case 3:
9569 // Clear jump_out
9f51b4b9 9570 if((expirep&2047)==0)
dd3a91a1 9571 do_clear_cache();
943f42f3 9572 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9573 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9574 break;
9575 }
9576 expirep=(expirep+1)&65535;
9577 }
37387d8b 9578#ifdef ASSEM_PRINT
9579 fflush(stdout);
9580#endif
57871462 9581 return 0;
9582}
b9b61529 9583
9584// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork