FAME integration finished, some adjustments of CPU core stuff
[picodrive.git] / Pico / cd / Pico.c
CommitLineData
672ad671 1// (c) Copyright 2007 notaz, All rights reserved.
cc68a136 2
3
4#include "../PicoInt.h"
cc68a136 5
6
76276b0b 7extern unsigned char formatted_bram[4*0x10];
89fa852d 8extern unsigned int s68k_poll_adclk;
9
721cd396 10void (*PicoMCDopenTray)(void) = NULL;
11int (*PicoMCDcloseTray)(void) = NULL;
89fa852d 12
13#define dump_ram(ram,fname) \
14{ \
15 int i, d; \
16 FILE *f; \
17\
18 for (i = 0; i < sizeof(ram); i+=2) { \
19 d = (ram[i]<<8) | ram[i+1]; \
20 *(unsigned short *)(ram+i) = d; \
21 } \
22 f = fopen(fname, "wb"); \
23 if (f) { \
24 fwrite(ram, 1, sizeof(ram), f); \
25 fclose(f); \
26 } \
27 for (i = 0; i < sizeof(ram); i+=2) { \
28 d = (ram[i]<<8) | ram[i+1]; \
29 *(unsigned short *)(ram+i) = d; \
30 } \
31}
cc68a136 32
33
eff55556 34PICO_INTERNAL int PicoInitMCD(void)
cc68a136 35{
36 SekInitS68k();
37 Init_CD_Driver();
38
39 return 0;
40}
41
42
eff55556 43PICO_INTERNAL void PicoExitMCD(void)
cc68a136 44{
45 End_CD_Driver();
89fa852d 46
47 //dump_ram(Pico_mcd->prg_ram, "prg.bin");
48 //dump_ram(Pico.ram, "ram.bin");
cc68a136 49}
50
eff55556 51PICO_INTERNAL int PicoResetMCD(int hard)
cc68a136 52{
51a902ae 53 if (hard) {
a4030801 54 int fmt_size = sizeof(formatted_bram);
55 memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
56 memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
57 memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
58 memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
59 memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
51a902ae 60 }
61 memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7 62 memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605 63 memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae 64
d1df8786 65 *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
c008977e 66 Pico_mcd->m.state_flags |= 1; // s68k reset pending
672ad671 67 Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
cc68a136 68
cc68a136 69 Reset_CD();
5c69a605 70 LC89510_Reset();
51a902ae 71 gfx_cd_reset();
4ff2d527 72 PicoMemResetCD(1);
3aa1e148 73#ifdef _ASM_CD_MEMORY_C
00bd648e 74 //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527 75#endif
cc68a136 76
6cadc2da 77 // use SRam.data for RAM cart
78 if (SRam.data) free(SRam.data);
79 SRam.data = NULL;
80 if (PicoOpt&0x8000)
81 SRam.data = calloc(1, 0x12000);
82
cc68a136 83 return 0;
84}
85
eff55556 86static __inline void SekRunM68k(int cyc)
cc68a136 87{
88 int cyc_do;
89 SekCycleAim+=cyc;
90 if((cyc_do=SekCycleAim-SekCycleCnt) < 0) return;
b837b69b 91#if defined(EMU_C68K)
3aa1e148 92 PicoCpuCM68k.cycles=cyc_do;
93 CycloneRun(&PicoCpuCM68k);
94 SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
b837b69b 95#elif defined(EMU_M68K)
3aa1e148 96 m68k_set_context(&PicoCpuMM68k);
cc68a136 97 SekCycleCnt+=m68k_execute(cyc_do);
3aa1e148 98#elif defined(EMU_F68K)
99 g_m68kcontext=&PicoCpuFM68k;
100 SekCycleCnt+=m68k_emulate(cyc_do);
cc68a136 101#endif
102}
103
104static __inline void SekRunS68k(int cyc)
105{
106 int cyc_do;
107 SekCycleAimS68k+=cyc;
108 if((cyc_do=SekCycleAimS68k-SekCycleCntS68k) < 0) return;
b837b69b 109#if defined(EMU_C68K)
3aa1e148 110 PicoCpuCS68k.cycles=cyc_do;
111 CycloneRun(&PicoCpuCS68k);
112 SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
b837b69b 113#elif defined(EMU_M68K)
3aa1e148 114 m68k_set_context(&PicoCpuMS68k);
cc68a136 115 SekCycleCntS68k+=m68k_execute(cyc_do);
3aa1e148 116#elif defined(EMU_F68K)
117 g_m68kcontext=&PicoCpuFS68k;
118 SekCycleCntS68k+=m68k_emulate(cyc_do);
cc68a136 119#endif
120}
121
7336a99a 122#define PS_STEP_M68K ((488<<16)/20) // ~24
123//#define PS_STEP_S68K 13
68cba51e 124
a4030801 125#ifdef _ASM_CD_PICO_C
126void SekRunPS(int cyc_m68k, int cyc_s68k);
127#else
68cba51e 128static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
129{
7336a99a 130 int cycn, cycn_s68k, cyc_do;
68cba51e 131 SekCycleAim+=cyc_m68k;
132 SekCycleAimS68k+=cyc_s68k;
7336a99a 133
134// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
135// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
136
137 /* loop 488 downto 0 in steps of PS_STEP */
138 for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
139 {
7336a99a 140 cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
7336a99a 141 if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
68cba51e 142#if defined(EMU_C68K)
3aa1e148 143 PicoCpuCM68k.cycles = cyc_do;
144 CycloneRun(&PicoCpuCM68k);
145 SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
68cba51e 146#elif defined(EMU_M68K)
3aa1e148 147 m68k_set_context(&PicoCpuMM68k);
148 SekCycleCnt += m68k_execute(cyc_do);
149#elif defined(EMU_F68K)
150 g_m68kcontext = &PicoCpuFM68k;
151 SekCycleCnt += m68k_emulate(cyc_do);
68cba51e 152#endif
7336a99a 153 }
7336a99a 154 if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
68cba51e 155#if defined(EMU_C68K)
3aa1e148 156 PicoCpuCS68k.cycles = cyc_do;
157 CycloneRun(&PicoCpuCS68k);
158 SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
68cba51e 159#elif defined(EMU_M68K)
3aa1e148 160 m68k_set_context(&PicoCpuMS68k);
161 SekCycleCntS68k += m68k_execute(cyc_do);
162#elif defined(EMU_F68K)
163 g_m68kcontext = &PicoCpuFS68k;
164 SekCycleCntS68k += m68k_emulate(cyc_do);
68cba51e 165#endif
7336a99a 166 }
68cba51e 167 }
68cba51e 168}
7336a99a 169#endif
68cba51e 170
171
bf098bc5 172static __inline void check_cd_dma(void)
173{
174 int ddx;
175
c459aefd 176 if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
bf098bc5 177
178 ddx = Pico_mcd->s68k_regs[4] & 7;
179 if (ddx < 2) return; // invalid
c459aefd 180 if (ddx < 4) {
181 Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
182 return;
183 }
bf098bc5 184 if (ddx == 6) return; // invalid
185
186 Update_CDC_TRansfer(ddx); // now go and do the actual transfer
187}
188
4f265db7 189static __inline void update_chips(void)
190{
191 int counter_timer, int3_set;
192 int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
193
194 // 75Hz CDC update
195 if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
196 Pico_mcd->m.counter75hz -= counter75hz_lim;
197 Check_CD_Command();
198 }
199
200 // update timers
201 counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
202 Pico_mcd->m.timer_stopwatch += counter_timer;
203 if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
204 Pico_mcd->m.timer_int3 -= counter_timer;
205 if (Pico_mcd->m.timer_int3 < 0) {
206 if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
69996cb7 207 elprintf(EL_INTS, "s68k: timer irq 3");
4f265db7 208 SekInterruptS68k(3);
209 Pico_mcd->m.timer_int3 += int3_set << 16;
210 }
211 // is this really what happens if irq3 is masked out?
212 Pico_mcd->m.timer_int3 &= 0xffffff;
213 }
214 }
215
216 // update gfx chip
217 if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
218 gfx_cd_update();
89fa852d 219
220 // delayed setting of DMNA bit (needed for Silpheed)
221 if (Pico_mcd->m.state_flags & 2) {
222 Pico_mcd->m.state_flags &= ~2;
46969540 223 if (!(Pico_mcd->s68k_regs[3] & 4)) {
224 Pico_mcd->s68k_regs[3] |= 2;
225 Pico_mcd->s68k_regs[3] &= ~1;
89fa852d 226#ifdef USE_POLL_DETECT
46969540 227 if ((s68k_poll_adclk&0xfe) == 2) {
228 SekSetStopS68k(0); s68k_poll_adclk = 0;
229 }
89fa852d 230#endif
46969540 231 }
89fa852d 232 }
4f265db7 233}
234
b837b69b 235
bf5fbbb4 236static __inline void getSamples(int y)
cc68a136 237{
bf5fbbb4 238 int len = sound_render(0, PsndLen);
239 if (PicoWriteSound) PicoWriteSound(len);
240 // clear sound buffer
241 sound_clear();
242}
cc68a136 243
cc68a136 244
bf5fbbb4 245#define PICO_CD
246#include "../PicoFrameHints.c"
cc68a136 247
248
eff55556 249PICO_INTERNAL int PicoFrameMCD(void)
cc68a136 250{
251 if(!(PicoOpt&0x10))
252 PicoFrameStart();
253
bf5fbbb4 254 PicoFrameHints();
cc68a136 255
256 return 0;
257}
258
259