[picodrive.git] / Pico / cd / Pico.c

// (c) Copyright 2007 notaz, All rights reserved.


#include "../PicoInt.h"


extern unsigned char formatted_bram[4*0x10];
extern unsigned int s68k_poll_adclk;

void (*PicoMCDopenTray)(void) = NULL;
int  (*PicoMCDcloseTray)(void) = NULL;

#define dump_ram(ram,fname) \
{ \
  int i, d; \
  FILE *f; \
\
  for (i = 0; i < sizeof(ram); i+=2) { \
    d = (ram[i]<<8) | ram[i+1]; \
    *(unsigned short *)(ram+i) = d; \
  } \
  f = fopen(fname, "wb"); \
  if (f) { \
    fwrite(ram, 1, sizeof(ram), f); \
    fclose(f); \
  } \
  for (i = 0; i < sizeof(ram); i+=2) { \
    d = (ram[i]<<8) | ram[i+1]; \
    *(unsigned short *)(ram+i) = d; \
  } \
}


PICO_INTERNAL int PicoInitMCD(void)
{
  SekInitS68k();
  Init_CD_Driver();

  return 0;
}


PICO_INTERNAL void PicoExitMCD(void)
{
  End_CD_Driver();

  //dump_ram(Pico_mcd->prg_ram, "prg.bin");
  //dump_ram(Pico.ram, "ram.bin");
}

PICO_INTERNAL int PicoResetMCD(int hard)
{
  if (hard) {
    int fmt_size = sizeof(formatted_bram);
    memset(Pico_mcd->prg_ram,    0, sizeof(Pico_mcd->prg_ram));
    memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
    memset(Pico_mcd->pcm_ram,    0, sizeof(Pico_mcd->pcm_ram));
    memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
    memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
  }
  memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
  memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
  memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));

  *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
  Pico_mcd->m.state_flags |= 1; // s68k reset pending
  Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset

  Reset_CD();
  LC89510_Reset();
  gfx_cd_reset();
  PicoMemResetCD(1);
#ifdef _ASM_CD_MEMORY_C
  //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
#endif

  // use SRam.data for RAM cart
  if (SRam.data) free(SRam.data);
  SRam.data = NULL;
  if (PicoOpt&0x8000)
    SRam.data = calloc(1, 0x12000);
  SRam.start = SRam.end = 0; // unused

  return 0;
}

static __inline void SekRunM68k(int cyc)
{
  int cyc_do;
  SekCycleAim+=cyc;
  if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
#if defined(EMU_CORE_DEBUG)
  SekCycleCnt+=CM_compareRun(cyc_do, 0);
#elif defined(EMU_C68K)
  PicoCpuCM68k.cycles=cyc_do;
  CycloneRun(&PicoCpuCM68k);
  SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
  m68k_set_context(&PicoCpuMM68k);
  SekCycleCnt+=m68k_execute(cyc_do);
#elif defined(EMU_F68K)
  g_m68kcontext=&PicoCpuFM68k;
  SekCycleCnt+=fm68k_emulate(cyc_do, 0);
#endif
}

static __inline void SekRunS68k(int cyc)
{
  int cyc_do;
  SekCycleAimS68k+=cyc;
  if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
#if defined(EMU_CORE_DEBUG)
  SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
#elif defined(EMU_C68K)
  PicoCpuCS68k.cycles=cyc_do;
  CycloneRun(&PicoCpuCS68k);
  SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
  m68k_set_context(&PicoCpuMS68k);
  SekCycleCntS68k+=m68k_execute(cyc_do);
#elif defined(EMU_F68K)
  g_m68kcontext=&PicoCpuFS68k;
  SekCycleCntS68k+=fm68k_emulate(cyc_do, 0);
#endif
}

#define PS_STEP_M68K ((488<<16)/20) // ~24
//#define PS_STEP_S68K 13

#if defined(_ASM_CD_PICO_C)
extern void SekRunPS(int cyc_m68k, int cyc_s68k);
#elif defined(EMU_F68K)
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
  SekCycleAim+=cyc_m68k;
  SekCycleAimS68k+=cyc_s68k;
  fm68k_emulate(0, 1);
}
#else
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
  int cycn, cycn_s68k, cyc_do;
  SekCycleAim+=cyc_m68k;
  SekCycleAimS68k+=cyc_s68k;

//  fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
//  		SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);

  /* loop 488 downto 0 in steps of PS_STEP */
  for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
  {
    cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
    if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
#if defined(EMU_C68K)
      PicoCpuCM68k.cycles = cyc_do;
      CycloneRun(&PicoCpuCM68k);
      SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
      m68k_set_context(&PicoCpuMM68k);
      SekCycleCnt += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
      g_m68kcontext = &PicoCpuFM68k;
      SekCycleCnt += fm68k_emulate(cyc_do, 0);
#endif
    }
    if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
#if defined(EMU_C68K)
      PicoCpuCS68k.cycles = cyc_do;
      CycloneRun(&PicoCpuCS68k);
      SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
      m68k_set_context(&PicoCpuMS68k);
      SekCycleCntS68k += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
      g_m68kcontext = &PicoCpuFS68k;
      SekCycleCntS68k += fm68k_emulate(cyc_do, 0);
#endif
    }
  }
}
#endif


static __inline void check_cd_dma(void)
{
	int ddx;

	if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;

	ddx = Pico_mcd->s68k_regs[4] & 7;
	if (ddx <  2) return; // invalid
	if (ddx <  4) {
		Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
		return;
	}
	if (ddx == 6) return; // invalid

	Update_CDC_TRansfer(ddx); // now go and do the actual transfer
}

static __inline void update_chips(void)
{
	int counter_timer, int3_set;
	int counter75hz_lim = Pico.m.pal ? 2080 : 2096;

	// 75Hz CDC update
	if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
		Pico_mcd->m.counter75hz -= counter75hz_lim;
		Check_CD_Command();
	}

	// update timers
	counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
	Pico_mcd->m.timer_stopwatch += counter_timer;
	if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
		Pico_mcd->m.timer_int3 -= counter_timer;
		if (Pico_mcd->m.timer_int3 < 0) {
			if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
				elprintf(EL_INTS, "s68k: timer irq 3");
				SekInterruptS68k(3);
				Pico_mcd->m.timer_int3 += int3_set << 16;
			}
			// is this really what happens if irq3 is masked out?
			Pico_mcd->m.timer_int3 &= 0xffffff;
		}
	}

	// update gfx chip
	if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
		gfx_cd_update();

	// delayed setting of DMNA bit (needed for Silpheed)
	if (Pico_mcd->m.state_flags & 2) {
		Pico_mcd->m.state_flags &= ~2;
		if (!(Pico_mcd->s68k_regs[3] & 4)) {
			Pico_mcd->s68k_regs[3] |=  2;
			Pico_mcd->s68k_regs[3] &= ~1;
#ifdef USE_POLL_DETECT
			if ((s68k_poll_adclk&0xfe) == 2) {
				SekSetStopS68k(0); s68k_poll_adclk = 0;
			}
#endif
		}
	}
}


static __inline void getSamples(int y)
{
  int len = PsndRender(0, PsndLen);
  if (PicoWriteSound) PicoWriteSound(len);
  // clear sound buffer
  PsndClear();
}


#define PICO_CD
#include "../PicoFrameHints.c"


PICO_INTERNAL int PicoFrameMCD(void)
{
  if(!(PicoOpt&0x10))
    PicoFrameStart();

  PicoFrameHints();

  return 0;
}
Commit	Line	Data
672ad671	1	// (c) Copyright 2007 notaz, All rights reserved.
cc68a136	2
	3
	4	#include "../PicoInt.h"
cc68a136	5
cc68a136	6
76276b0b	7	extern unsigned char formatted_bram[4*0x10];
89fa852d	8	extern unsigned int s68k_poll_adclk;
89fa852d	9
721cd396	10	void (*PicoMCDopenTray)(void) = NULL;
721cd396	11	int (*PicoMCDcloseTray)(void) = NULL;
89fa852d	12
	13	#define dump_ram(ram,fname) \
	14	{ \
	15	int i, d; \
	16	FILE *f; \
	17	\
	18	for (i = 0; i < sizeof(ram); i+=2) { \
	19	d = (ram[i]<<8) \| ram[i+1]; \
	20	(unsigned short )(ram+i) = d; \
	21	} \
	22	f = fopen(fname, "wb"); \
	23	if (f) { \
	24	fwrite(ram, 1, sizeof(ram), f); \
	25	fclose(f); \
	26	} \
	27	for (i = 0; i < sizeof(ram); i+=2) { \
	28	d = (ram[i]<<8) \| ram[i+1]; \
	29	(unsigned short )(ram+i) = d; \
	30	} \
	31	}
cc68a136	32
cc68a136	33
eff55556	34	PICO_INTERNAL int PicoInitMCD(void)
cc68a136	35	{
	36	SekInitS68k();
	37	Init_CD_Driver();
	38
	39	return 0;
	40	}
	41
	42
eff55556	43	PICO_INTERNAL void PicoExitMCD(void)
cc68a136	44	{
cc68a136	45	End_CD_Driver();
89fa852d	46
	47	//dump_ram(Pico_mcd->prg_ram, "prg.bin");
	48	//dump_ram(Pico.ram, "ram.bin");
cc68a136	49	}
cc68a136	50
eff55556	51	PICO_INTERNAL int PicoResetMCD(int hard)
cc68a136	52	{
51a902ae	53	if (hard) {
a4030801	54	int fmt_size = sizeof(formatted_bram);
	55	memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
	56	memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
	57	memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
	58	memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
	59	memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
51a902ae	60	}
51a902ae	61	memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7	62	memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605	63	memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae	64
d1df8786	65	(unsigned int )(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
c008977e	66	Pico_mcd->m.state_flags \|= 1; // s68k reset pending
672ad671	67	Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
cc68a136	68
cc68a136	69	Reset_CD();
5c69a605	70	LC89510_Reset();
51a902ae	71	gfx_cd_reset();
4ff2d527	72	PicoMemResetCD(1);
3aa1e148	73	#ifdef _ASM_CD_MEMORY_C
00bd648e	74	//PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527	75	#endif
cc68a136	76
6cadc2da	77	// use SRam.data for RAM cart
	78	if (SRam.data) free(SRam.data);
	79	SRam.data = NULL;
	80	if (PicoOpt&0x8000)
	81	SRam.data = calloc(1, 0x12000);
b542be46	82	SRam.start = SRam.end = 0; // unused
6cadc2da	83
cc68a136	84	return 0;
	85	}
	86
eff55556	87	static __inline void SekRunM68k(int cyc)
cc68a136	88	{
	89	int cyc_do;
	90	SekCycleAim+=cyc;
3ec29f01	91	if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
b5e5172d	92	#if defined(EMU_CORE_DEBUG)
	93	SekCycleCnt+=CM_compareRun(cyc_do, 0);
	94	#elif defined(EMU_C68K)
3aa1e148	95	PicoCpuCM68k.cycles=cyc_do;
	96	CycloneRun(&PicoCpuCM68k);
	97	SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
b837b69b	98	#elif defined(EMU_M68K)
3aa1e148	99	m68k_set_context(&PicoCpuMM68k);
cc68a136	100	SekCycleCnt+=m68k_execute(cyc_do);
3aa1e148	101	#elif defined(EMU_F68K)
3aa1e148	102	g_m68kcontext=&PicoCpuFM68k;
8022f53d	103	SekCycleCnt+=fm68k_emulate(cyc_do, 0);
cc68a136	104	#endif
	105	}
	106
	107	static __inline void SekRunS68k(int cyc)
	108	{
	109	int cyc_do;
	110	SekCycleAimS68k+=cyc;
3ec29f01	111	if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
b5e5172d	112	#if defined(EMU_CORE_DEBUG)
	113	SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
	114	#elif defined(EMU_C68K)
3aa1e148	115	PicoCpuCS68k.cycles=cyc_do;
	116	CycloneRun(&PicoCpuCS68k);
	117	SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
b837b69b	118	#elif defined(EMU_M68K)
3aa1e148	119	m68k_set_context(&PicoCpuMS68k);
cc68a136	120	SekCycleCntS68k+=m68k_execute(cyc_do);
3aa1e148	121	#elif defined(EMU_F68K)
3aa1e148	122	g_m68kcontext=&PicoCpuFS68k;
8022f53d	123	SekCycleCntS68k+=fm68k_emulate(cyc_do, 0);
cc68a136	124	#endif
	125	}
	126
7336a99a	127	#define PS_STEP_M68K ((488<<16)/20) // ~24
7336a99a	128	//#define PS_STEP_S68K 13
68cba51e	129
8022f53d	130	#if defined(_ASM_CD_PICO_C)
	131	extern void SekRunPS(int cyc_m68k, int cyc_s68k);
	132	#elif defined(EMU_F68K)
	133	static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
	134	{
	135	SekCycleAim+=cyc_m68k;
	136	SekCycleAimS68k+=cyc_s68k;
	137	fm68k_emulate(0, 1);
	138	}
a4030801	139	#else
68cba51e	140	static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
68cba51e	141	{
7336a99a	142	int cycn, cycn_s68k, cyc_do;
68cba51e	143	SekCycleAim+=cyc_m68k;
68cba51e	144	SekCycleAimS68k+=cyc_s68k;
7336a99a	145
	146	// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
	147	// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
	148
	149	/* loop 488 downto 0 in steps of PS_STEP */
	150	for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
	151	{
7336a99a	152	cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
7336a99a	153	if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
68cba51e	154	#if defined(EMU_C68K)
3aa1e148	155	PicoCpuCM68k.cycles = cyc_do;
	156	CycloneRun(&PicoCpuCM68k);
	157	SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
68cba51e	158	#elif defined(EMU_M68K)
3aa1e148	159	m68k_set_context(&PicoCpuMM68k);
	160	SekCycleCnt += m68k_execute(cyc_do);
	161	#elif defined(EMU_F68K)
	162	g_m68kcontext = &PicoCpuFM68k;
8022f53d	163	SekCycleCnt += fm68k_emulate(cyc_do, 0);
68cba51e	164	#endif
7336a99a	165	}
7336a99a	166	if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
68cba51e	167	#if defined(EMU_C68K)
3aa1e148	168	PicoCpuCS68k.cycles = cyc_do;
	169	CycloneRun(&PicoCpuCS68k);
	170	SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
68cba51e	171	#elif defined(EMU_M68K)
3aa1e148	172	m68k_set_context(&PicoCpuMS68k);
	173	SekCycleCntS68k += m68k_execute(cyc_do);
	174	#elif defined(EMU_F68K)
	175	g_m68kcontext = &PicoCpuFS68k;
8022f53d	176	SekCycleCntS68k += fm68k_emulate(cyc_do, 0);
68cba51e	177	#endif
7336a99a	178	}
68cba51e	179	}
68cba51e	180	}
7336a99a	181	#endif
68cba51e	182
68cba51e	183
bf098bc5	184	static __inline void check_cd_dma(void)
	185	{
	186	int ddx;
	187
c459aefd	188	if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
bf098bc5	189
	190	ddx = Pico_mcd->s68k_regs[4] & 7;
	191	if (ddx < 2) return; // invalid
c459aefd	192	if (ddx < 4) {
	193	Pico_mcd->s68k_regs[4] \|= 0x40; // Data set ready in host port
	194	return;
	195	}
bf098bc5	196	if (ddx == 6) return; // invalid
	197
	198	Update_CDC_TRansfer(ddx); // now go and do the actual transfer
	199	}
	200
4f265db7	201	static __inline void update_chips(void)
	202	{
	203	int counter_timer, int3_set;
	204	int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
	205
	206	// 75Hz CDC update
	207	if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
	208	Pico_mcd->m.counter75hz -= counter75hz_lim;
	209	Check_CD_Command();
	210	}
	211
	212	// update timers
	213	counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
	214	Pico_mcd->m.timer_stopwatch += counter_timer;
	215	if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
	216	Pico_mcd->m.timer_int3 -= counter_timer;
	217	if (Pico_mcd->m.timer_int3 < 0) {
	218	if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
69996cb7	219	elprintf(EL_INTS, "s68k: timer irq 3");
4f265db7	220	SekInterruptS68k(3);
	221	Pico_mcd->m.timer_int3 += int3_set << 16;
	222	}
	223	// is this really what happens if irq3 is masked out?
	224	Pico_mcd->m.timer_int3 &= 0xffffff;
	225	}
	226	}
	227
	228	// update gfx chip
	229	if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
	230	gfx_cd_update();
89fa852d	231
	232	// delayed setting of DMNA bit (needed for Silpheed)
	233	if (Pico_mcd->m.state_flags & 2) {
	234	Pico_mcd->m.state_flags &= ~2;
46969540	235	if (!(Pico_mcd->s68k_regs[3] & 4)) {
	236	Pico_mcd->s68k_regs[3] \|= 2;
	237	Pico_mcd->s68k_regs[3] &= ~1;
89fa852d	238	#ifdef USE_POLL_DETECT
46969540	239	if ((s68k_poll_adclk&0xfe) == 2) {
	240	SekSetStopS68k(0); s68k_poll_adclk = 0;
	241	}
89fa852d	242	#endif
46969540	243	}
89fa852d	244	}
4f265db7	245	}
4f265db7	246
b837b69b	247
bf5fbbb4	248	static __inline void getSamples(int y)
cc68a136	249	{
9d917eea	250	int len = PsndRender(0, PsndLen);
bf5fbbb4	251	if (PicoWriteSound) PicoWriteSound(len);
bf5fbbb4	252	// clear sound buffer
9d917eea	253	PsndClear();
bf5fbbb4	254	}
cc68a136	255
cc68a136	256
bf5fbbb4	257	#define PICO_CD
bf5fbbb4	258	#include "../PicoFrameHints.c"
cc68a136	259
cc68a136	260
eff55556	261	PICO_INTERNAL int PicoFrameMCD(void)
cc68a136	262	{
	263	if(!(PicoOpt&0x10))
	264	PicoFrameStart();
	265
bf5fbbb4	266	PicoFrameHints();
cc68a136	267
	268	return 0;
	269	}
	270
	271