[picodrive.git] / Pico / cd / Pico.c

// (c) Copyright 2007 notaz, All rights reserved.


#include "../PicoInt.h"
#include "../sound/ym2612.h"

extern unsigned char formatted_bram[4*0x10];
extern unsigned int s68k_poll_adclk;

void (*PicoMCDopenTray)(void) = NULL;
int  (*PicoMCDcloseTray)(void) = NULL;

#define dump_ram(ram,fname) \
{ \
  int i, d; \
  FILE *f; \
\
  for (i = 0; i < sizeof(ram); i+=2) { \
    d = (ram[i]<<8) | ram[i+1]; \
    *(unsigned short *)(ram+i) = d; \
  } \
  f = fopen(fname, "wb"); \
  if (f) { \
    fwrite(ram, 1, sizeof(ram), f); \
    fclose(f); \
  } \
  for (i = 0; i < sizeof(ram); i+=2) { \
    d = (ram[i]<<8) | ram[i+1]; \
    *(unsigned short *)(ram+i) = d; \
  } \
}


PICO_INTERNAL int PicoInitMCD(void)
{
  SekInitS68k();
  Init_CD_Driver();

  return 0;
}


PICO_INTERNAL void PicoExitMCD(void)
{
  End_CD_Driver();

  //dump_ram(Pico_mcd->prg_ram, "prg.bin");
  //dump_ram(Pico.ram, "ram.bin");
}

PICO_INTERNAL void PicoPowerMCD(void)
{
  int fmt_size = sizeof(formatted_bram);
  memset(Pico_mcd->prg_ram,    0, sizeof(Pico_mcd->prg_ram));
  memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
  memset(Pico_mcd->pcm_ram,    0, sizeof(Pico_mcd->pcm_ram));
  memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
  memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
}

PICO_INTERNAL int PicoResetMCD(void)
{
  memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
  memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
  memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));

  *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
  Pico_mcd->m.state_flags |= 1; // s68k reset pending
  Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset

  Reset_CD();
  LC89510_Reset();
  gfx_cd_reset();
  PicoMemResetCD(1);
#ifdef _ASM_CD_MEMORY_C
  //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
#endif

  // use SRam.data for RAM cart
  if (PicoOpt&POPT_EN_MCD_RAMCART) {
    if (SRam.data == NULL)
      SRam.data = calloc(1, 0x12000);
  }
  else if (SRam.data != NULL) {
    free(SRam.data);
    SRam.data = NULL;
  }
  SRam.start = SRam.end = 0; // unused

  return 0;
}

static __inline void SekRunM68k(int cyc)
{
  int cyc_do;
  SekCycleAim+=cyc;
  if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
#if defined(EMU_CORE_DEBUG)
  SekCycleCnt+=CM_compareRun(cyc_do, 0);
#elif defined(EMU_C68K)
  PicoCpuCM68k.cycles=cyc_do;
  CycloneRun(&PicoCpuCM68k);
  SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
  m68k_set_context(&PicoCpuMM68k);
  SekCycleCnt+=m68k_execute(cyc_do);
#elif defined(EMU_F68K)
  g_m68kcontext=&PicoCpuFM68k;
  SekCycleCnt+=fm68k_emulate(cyc_do, 0);
#endif
}

static __inline void SekRunS68k(int cyc)
{
  int cyc_do;
  SekCycleAimS68k+=cyc;
  if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
#if defined(EMU_CORE_DEBUG)
  SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
#elif defined(EMU_C68K)
  PicoCpuCS68k.cycles=cyc_do;
  CycloneRun(&PicoCpuCS68k);
  SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
  m68k_set_context(&PicoCpuMS68k);
  SekCycleCntS68k+=m68k_execute(cyc_do);
#elif defined(EMU_F68K)
  g_m68kcontext=&PicoCpuFS68k;
  SekCycleCntS68k+=fm68k_emulate(cyc_do, 0);
#endif
}

#define PS_STEP_M68K ((488<<16)/20) // ~24
//#define PS_STEP_S68K 13

#if defined(_ASM_CD_PICO_C)
extern void SekRunPS(int cyc_m68k, int cyc_s68k);
#elif defined(EMU_F68K)
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
  SekCycleAim+=cyc_m68k;
  SekCycleAimS68k+=cyc_s68k;
  fm68k_emulate(0, 1);
}
#else
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
  int cycn, cycn_s68k, cyc_do;
  SekCycleAim+=cyc_m68k;
  SekCycleAimS68k+=cyc_s68k;

//  fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
//  		SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);

  /* loop 488 downto 0 in steps of PS_STEP */
  for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
  {
    cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
    if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
#if defined(EMU_C68K)
      PicoCpuCM68k.cycles = cyc_do;
      CycloneRun(&PicoCpuCM68k);
      SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
      m68k_set_context(&PicoCpuMM68k);
      SekCycleCnt += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
      g_m68kcontext = &PicoCpuFM68k;
      SekCycleCnt += fm68k_emulate(cyc_do, 0);
#endif
    }
    if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
#if defined(EMU_C68K)
      PicoCpuCS68k.cycles = cyc_do;
      CycloneRun(&PicoCpuCS68k);
      SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
      m68k_set_context(&PicoCpuMS68k);
      SekCycleCntS68k += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
      g_m68kcontext = &PicoCpuFS68k;
      SekCycleCntS68k += fm68k_emulate(cyc_do, 0);
#endif
    }
  }
}
#endif


static __inline void check_cd_dma(void)
{
	int ddx;

	if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;

	ddx = Pico_mcd->s68k_regs[4] & 7;
	if (ddx <  2) return; // invalid
	if (ddx <  4) {
		Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
		return;
	}
	if (ddx == 6) return; // invalid

	Update_CDC_TRansfer(ddx); // now go and do the actual transfer
}

static __inline void update_chips(void)
{
	int counter_timer, int3_set;
	int counter75hz_lim = Pico.m.pal ? 2080 : 2096;

	// 75Hz CDC update
	if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
		Pico_mcd->m.counter75hz -= counter75hz_lim;
		Check_CD_Command();
	}

	// update timers
	counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
	Pico_mcd->m.timer_stopwatch += counter_timer;
	if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
		Pico_mcd->m.timer_int3 -= counter_timer;
		if (Pico_mcd->m.timer_int3 < 0) {
			if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
				elprintf(EL_INTS, "s68k: timer irq 3");
				SekInterruptS68k(3);
				Pico_mcd->m.timer_int3 += int3_set << 16;
			}
			// is this really what happens if irq3 is masked out?
			Pico_mcd->m.timer_int3 &= 0xffffff;
		}
	}

	// update gfx chip
	if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
		gfx_cd_update();

	// delayed setting of DMNA bit (needed for Silpheed)
	if (Pico_mcd->m.state_flags & 2) {
		Pico_mcd->m.state_flags &= ~2;
		if (!(Pico_mcd->s68k_regs[3] & 4)) {
			Pico_mcd->s68k_regs[3] |=  2;
			Pico_mcd->s68k_regs[3] &= ~1;
#ifdef USE_POLL_DETECT
			if ((s68k_poll_adclk&0xfe) == 2) {
				SekSetStopS68k(0); s68k_poll_adclk = 0;
			}
#endif
		}
	}
}


static __inline void getSamples(int y)
{
  int len = PsndRender(0, PsndLen);
  if (PicoWriteSound) PicoWriteSound(len);
  // clear sound buffer
  PsndClear();
}


#define PICO_CD
#include "../PicoFrameHints.c"


PICO_INTERNAL int PicoFrameMCD(void)
{
  if (!(PicoOpt&POPT_ALT_RENDERER))
    PicoFrameStart();

  PicoFrameHints();

  return 0;
}
Commit	Line	Data
672ad671	1	// (c) Copyright 2007 notaz, All rights reserved.
cc68a136	2
	3
	4	#include "../PicoInt.h"
43e6eaad	5	#include "../sound/ym2612.h"
cc68a136	6
76276b0b	7	extern unsigned char formatted_bram[4*0x10];
89fa852d	8	extern unsigned int s68k_poll_adclk;
89fa852d	9
721cd396	10	void (*PicoMCDopenTray)(void) = NULL;
721cd396	11	int (*PicoMCDcloseTray)(void) = NULL;
89fa852d	12
	13	#define dump_ram(ram,fname) \
	14	{ \
	15	int i, d; \
	16	FILE *f; \
	17	\
	18	for (i = 0; i < sizeof(ram); i+=2) { \
	19	d = (ram[i]<<8) \| ram[i+1]; \
	20	(unsigned short )(ram+i) = d; \
	21	} \
	22	f = fopen(fname, "wb"); \
	23	if (f) { \
	24	fwrite(ram, 1, sizeof(ram), f); \
	25	fclose(f); \
	26	} \
	27	for (i = 0; i < sizeof(ram); i+=2) { \
	28	d = (ram[i]<<8) \| ram[i+1]; \
	29	(unsigned short )(ram+i) = d; \
	30	} \
	31	}
cc68a136	32
cc68a136	33
eff55556	34	PICO_INTERNAL int PicoInitMCD(void)
cc68a136	35	{
	36	SekInitS68k();
	37	Init_CD_Driver();
	38
	39	return 0;
	40	}
	41
	42
eff55556	43	PICO_INTERNAL void PicoExitMCD(void)
cc68a136	44	{
cc68a136	45	End_CD_Driver();
89fa852d	46
	47	//dump_ram(Pico_mcd->prg_ram, "prg.bin");
	48	//dump_ram(Pico.ram, "ram.bin");
cc68a136	49	}
cc68a136	50
1cb1584b	51	PICO_INTERNAL void PicoPowerMCD(void)
	52	{
	53	int fmt_size = sizeof(formatted_bram);
	54	memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
	55	memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
	56	memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
	57	memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
	58	memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
	59	}
	60
	61	PICO_INTERNAL int PicoResetMCD(void)
cc68a136	62	{
51a902ae	63	memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7	64	memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605	65	memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae	66
d1df8786	67	(unsigned int )(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
c008977e	68	Pico_mcd->m.state_flags \|= 1; // s68k reset pending
672ad671	69	Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
cc68a136	70
cc68a136	71	Reset_CD();
5c69a605	72	LC89510_Reset();
51a902ae	73	gfx_cd_reset();
4ff2d527	74	PicoMemResetCD(1);
3aa1e148	75	#ifdef _ASM_CD_MEMORY_C
00bd648e	76	//PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527	77	#endif
cc68a136	78
6cadc2da	79	// use SRam.data for RAM cart
602133e1	80	if (PicoOpt&POPT_EN_MCD_RAMCART) {
d6114368	81	if (SRam.data == NULL)
	82	SRam.data = calloc(1, 0x12000);
	83	}
	84	else if (SRam.data != NULL) {
	85	free(SRam.data);
	86	SRam.data = NULL;
	87	}
b542be46	88	SRam.start = SRam.end = 0; // unused
6cadc2da	89
cc68a136	90	return 0;
	91	}
	92
eff55556	93	static __inline void SekRunM68k(int cyc)
cc68a136	94	{
	95	int cyc_do;
	96	SekCycleAim+=cyc;
3ec29f01	97	if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
b5e5172d	98	#if defined(EMU_CORE_DEBUG)
	99	SekCycleCnt+=CM_compareRun(cyc_do, 0);
	100	#elif defined(EMU_C68K)
3aa1e148	101	PicoCpuCM68k.cycles=cyc_do;
	102	CycloneRun(&PicoCpuCM68k);
	103	SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
b837b69b	104	#elif defined(EMU_M68K)
3aa1e148	105	m68k_set_context(&PicoCpuMM68k);
cc68a136	106	SekCycleCnt+=m68k_execute(cyc_do);
3aa1e148	107	#elif defined(EMU_F68K)
3aa1e148	108	g_m68kcontext=&PicoCpuFM68k;
8022f53d	109	SekCycleCnt+=fm68k_emulate(cyc_do, 0);
cc68a136	110	#endif
	111	}
	112
	113	static __inline void SekRunS68k(int cyc)
	114	{
	115	int cyc_do;
	116	SekCycleAimS68k+=cyc;
3ec29f01	117	if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
b5e5172d	118	#if defined(EMU_CORE_DEBUG)
	119	SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
	120	#elif defined(EMU_C68K)
3aa1e148	121	PicoCpuCS68k.cycles=cyc_do;
	122	CycloneRun(&PicoCpuCS68k);
	123	SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
b837b69b	124	#elif defined(EMU_M68K)
3aa1e148	125	m68k_set_context(&PicoCpuMS68k);
cc68a136	126	SekCycleCntS68k+=m68k_execute(cyc_do);
3aa1e148	127	#elif defined(EMU_F68K)
3aa1e148	128	g_m68kcontext=&PicoCpuFS68k;
8022f53d	129	SekCycleCntS68k+=fm68k_emulate(cyc_do, 0);
cc68a136	130	#endif
	131	}
	132
7336a99a	133	#define PS_STEP_M68K ((488<<16)/20) // ~24
7336a99a	134	//#define PS_STEP_S68K 13
68cba51e	135
8022f53d	136	#if defined(_ASM_CD_PICO_C)
	137	extern void SekRunPS(int cyc_m68k, int cyc_s68k);
	138	#elif defined(EMU_F68K)
	139	static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
	140	{
	141	SekCycleAim+=cyc_m68k;
	142	SekCycleAimS68k+=cyc_s68k;
	143	fm68k_emulate(0, 1);
	144	}
a4030801	145	#else
68cba51e	146	static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
68cba51e	147	{
7336a99a	148	int cycn, cycn_s68k, cyc_do;
68cba51e	149	SekCycleAim+=cyc_m68k;
68cba51e	150	SekCycleAimS68k+=cyc_s68k;
7336a99a	151
	152	// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
	153	// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
	154
	155	/* loop 488 downto 0 in steps of PS_STEP */
	156	for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
	157	{
7336a99a	158	cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
7336a99a	159	if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
68cba51e	160	#if defined(EMU_C68K)
3aa1e148	161	PicoCpuCM68k.cycles = cyc_do;
	162	CycloneRun(&PicoCpuCM68k);
	163	SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
68cba51e	164	#elif defined(EMU_M68K)
3aa1e148	165	m68k_set_context(&PicoCpuMM68k);
	166	SekCycleCnt += m68k_execute(cyc_do);
	167	#elif defined(EMU_F68K)
	168	g_m68kcontext = &PicoCpuFM68k;
8022f53d	169	SekCycleCnt += fm68k_emulate(cyc_do, 0);
68cba51e	170	#endif
7336a99a	171	}
7336a99a	172	if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
68cba51e	173	#if defined(EMU_C68K)
3aa1e148	174	PicoCpuCS68k.cycles = cyc_do;
	175	CycloneRun(&PicoCpuCS68k);
	176	SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
68cba51e	177	#elif defined(EMU_M68K)
3aa1e148	178	m68k_set_context(&PicoCpuMS68k);
	179	SekCycleCntS68k += m68k_execute(cyc_do);
	180	#elif defined(EMU_F68K)
	181	g_m68kcontext = &PicoCpuFS68k;
8022f53d	182	SekCycleCntS68k += fm68k_emulate(cyc_do, 0);
68cba51e	183	#endif
7336a99a	184	}
68cba51e	185	}
68cba51e	186	}
7336a99a	187	#endif
68cba51e	188
68cba51e	189
bf098bc5	190	static __inline void check_cd_dma(void)
	191	{
	192	int ddx;
	193
c459aefd	194	if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
bf098bc5	195
	196	ddx = Pico_mcd->s68k_regs[4] & 7;
	197	if (ddx < 2) return; // invalid
c459aefd	198	if (ddx < 4) {
	199	Pico_mcd->s68k_regs[4] \|= 0x40; // Data set ready in host port
	200	return;
	201	}
bf098bc5	202	if (ddx == 6) return; // invalid
	203
	204	Update_CDC_TRansfer(ddx); // now go and do the actual transfer
	205	}
	206
4f265db7	207	static __inline void update_chips(void)
	208	{
	209	int counter_timer, int3_set;
	210	int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
	211
	212	// 75Hz CDC update
	213	if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
	214	Pico_mcd->m.counter75hz -= counter75hz_lim;
	215	Check_CD_Command();
	216	}
	217
	218	// update timers
	219	counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
	220	Pico_mcd->m.timer_stopwatch += counter_timer;
	221	if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
	222	Pico_mcd->m.timer_int3 -= counter_timer;
	223	if (Pico_mcd->m.timer_int3 < 0) {
	224	if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
69996cb7	225	elprintf(EL_INTS, "s68k: timer irq 3");
4f265db7	226	SekInterruptS68k(3);
	227	Pico_mcd->m.timer_int3 += int3_set << 16;
	228	}
	229	// is this really what happens if irq3 is masked out?
	230	Pico_mcd->m.timer_int3 &= 0xffffff;
	231	}
	232	}
	233
	234	// update gfx chip
	235	if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
	236	gfx_cd_update();
89fa852d	237
	238	// delayed setting of DMNA bit (needed for Silpheed)
	239	if (Pico_mcd->m.state_flags & 2) {
	240	Pico_mcd->m.state_flags &= ~2;
46969540	241	if (!(Pico_mcd->s68k_regs[3] & 4)) {
	242	Pico_mcd->s68k_regs[3] \|= 2;
	243	Pico_mcd->s68k_regs[3] &= ~1;
89fa852d	244	#ifdef USE_POLL_DETECT
46969540	245	if ((s68k_poll_adclk&0xfe) == 2) {
	246	SekSetStopS68k(0); s68k_poll_adclk = 0;
	247	}
89fa852d	248	#endif
46969540	249	}
89fa852d	250	}
4f265db7	251	}
4f265db7	252
b837b69b	253
bf5fbbb4	254	static __inline void getSamples(int y)
cc68a136	255	{
9d917eea	256	int len = PsndRender(0, PsndLen);
bf5fbbb4	257	if (PicoWriteSound) PicoWriteSound(len);
bf5fbbb4	258	// clear sound buffer
9d917eea	259	PsndClear();
bf5fbbb4	260	}
cc68a136	261
cc68a136	262
bf5fbbb4	263	#define PICO_CD
bf5fbbb4	264	#include "../PicoFrameHints.c"
cc68a136	265
cc68a136	266
eff55556	267	PICO_INTERNAL int PicoFrameMCD(void)
cc68a136	268	{
602133e1	269	if (!(PicoOpt&POPT_ALT_RENDERER))
cc68a136	270	PicoFrameStart();
cc68a136	271
bf5fbbb4	272	PicoFrameHints();
cc68a136	273
	274	return 0;
	275	}
	276
	277