e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
3 | */ |
f0d7b1fa |
4 | #include <stddef.h> |
679af8a3 |
5 | #include <stdio.h> |
6 | #include <stdlib.h> |
7 | #include <assert.h> |
41397701 |
8 | |
f4bb5d6b |
9 | #include "../../pico/pico_int.h" |
679af8a3 |
10 | #include "sh2.h" |
11 | #include "compiler.h" |
12 | #include "../drc/cmn.h" |
13 | |
e898de13 |
14 | #ifndef DRC_DEBUG |
15 | #define DRC_DEBUG 0 |
16 | #endif |
17 | |
553c3eaa |
18 | #if DRC_DEBUG |
f4bb5d6b |
19 | #define dbg(l,...) { \ |
20 | if ((l) & DRC_DEBUG) \ |
21 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
22 | } |
23 | |
e898de13 |
24 | #include "mame/sh2dasm.h" |
25 | #include <platform/linux/host_dasm.h> |
26 | static int insns_compiled, hash_collisions, host_insn_count; |
553c3eaa |
27 | #define COUNT_OP \ |
28 | host_insn_count++ |
29 | #else // !DRC_DEBUG |
30 | #define COUNT_OP |
31 | #define dbg(...) |
e898de13 |
32 | #endif |
553c3eaa |
33 | |
e898de13 |
34 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
35 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
36 | static char sh2dasm_buff[64]; |
f4bb5d6b |
37 | #define do_host_disasm(tcid) \ |
38 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
39 | tcache_dsm_ptrs[tcid] = tcache_ptr |
40 | #else |
41 | #define do_host_disasm(x) |
e898de13 |
42 | #endif |
43 | |
679af8a3 |
44 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
45 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
46 | |
47 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
48 | // BIOS shares tcache with data array because it's only used for init |
49 | // and can be discarded early |
50 | static const int tcache_sizes[3] = { |
51 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
52 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
53 | DRC_TCACHE_SIZE / 8, // ... slave |
54 | }; |
679af8a3 |
55 | |
f4bb5d6b |
56 | static u8 *tcache_bases[3]; |
57 | static u8 *tcache_ptrs[3]; |
58 | |
59 | // ptr for code emiters |
60 | static u8 *tcache_ptr; |
e898de13 |
61 | |
c18edb34 |
62 | // host register tracking |
63 | enum { |
64 | HR_FREE, |
65 | HR_CACHED, // 'val' has sh2_reg_e |
66 | HR_CACHED_DIRTY, |
67 | HR_CONST, // 'val' has constant |
68 | HR_TEMP, // reg used for temp storage |
69 | }; |
70 | |
71 | typedef struct { |
72 | u8 reg; |
73 | u8 type; |
74 | u16 stamp; // kind of a timestamp |
75 | u32 val; |
76 | } temp_reg_t; |
77 | |
80599a42 |
78 | // note: reg_temp[] must have at least the amount of |
3863edbd |
79 | // registers used by handlers in worst case (currently 4) |
65c75cb0 |
80 | #ifdef ARM |
81 | #include "../drc/emit_arm.c" |
82 | |
83 | static const int reg_map_g2h[] = { |
c18edb34 |
84 | -1, -1, -1, -1, |
85 | -1, -1, -1, -1, |
86 | -1, -1, -1, -1, |
87 | -1, -1, -1, -1, |
88 | -1, -1, -1, -1, |
89 | -1, -1, -1, -1, |
90 | }; |
91 | |
92 | static temp_reg_t reg_temp[] = { |
93 | { 0, }, |
94 | { 1, }, |
95 | { 12, }, |
96 | { 14, }, |
97 | { 2, }, |
98 | { 3, }, |
65c75cb0 |
99 | }; |
100 | |
101 | #else |
e898de13 |
102 | #include "../drc/emit_x86.c" |
103 | |
65c75cb0 |
104 | static const int reg_map_g2h[] = { |
c18edb34 |
105 | -1, -1, -1, -1, |
106 | -1, -1, -1, -1, |
107 | -1, -1, -1, -1, |
108 | -1, -1, -1, -1, |
109 | -1, -1, -1, -1, |
110 | -1, -1, -1, -1, |
111 | }; |
112 | |
3863edbd |
113 | // ax, cx, dx are usually temporaries by convention |
c18edb34 |
114 | static temp_reg_t reg_temp[] = { |
115 | { xAX, }, |
3863edbd |
116 | { xBX, }, |
c18edb34 |
117 | { xCX, }, |
118 | { xDX, }, |
65c75cb0 |
119 | }; |
120 | |
121 | #endif |
122 | |
80599a42 |
123 | #define T 0x00000001 |
124 | #define S 0x00000002 |
125 | #define I 0x000000f0 |
126 | #define Q 0x00000100 |
127 | #define M 0x00000200 |
128 | |
f0d7b1fa |
129 | #define Q_SHIFT 8 |
130 | #define M_SHIFT 9 |
131 | |
679af8a3 |
132 | typedef struct block_desc_ { |
133 | u32 addr; // SH2 PC address |
f4bb5d6b |
134 | u32 end_addr; // TODO rm? |
679af8a3 |
135 | void *tcache_ptr; // translated block for above PC |
f4bb5d6b |
136 | struct block_desc_ *next; // next block with the same PC hash |
137 | #if (DRC_DEBUG & 1) |
138 | int refcount; |
139 | #endif |
679af8a3 |
140 | } block_desc; |
141 | |
f4bb5d6b |
142 | static const int block_max_counts[3] = { |
143 | 4*1024, |
144 | 256, |
145 | 256, |
146 | }; |
147 | static block_desc *block_tables[3]; |
148 | static int block_counts[3]; |
679af8a3 |
149 | |
f4bb5d6b |
150 | // ROM hash table |
679af8a3 |
151 | #define MAX_HASH_ENTRIES 1024 |
152 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
153 | static void **hash_table; |
679af8a3 |
154 | |
679af8a3 |
155 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
156 | extern void sh2_drc_exit(void); |
157 | |
158 | // tmp |
553c3eaa |
159 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
160 | static void REGPARM(1) sh2_test_irq(SH2 *sh2); |
679af8a3 |
161 | |
f4bb5d6b |
162 | static void flush_tcache(int tcid) |
163 | { |
553c3eaa |
164 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
f4bb5d6b |
165 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
166 | block_counts[tcid], block_max_counts[tcid]); |
167 | |
168 | block_counts[tcid] = 0; |
169 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
170 | if (tcid == 0) { // ROM, RAM |
171 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
172 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
173 | } |
174 | else |
175 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
176 | #if (DRC_DEBUG & 2) |
177 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
178 | #endif |
179 | } |
180 | |
679af8a3 |
181 | static void *dr_find_block(block_desc *tab, u32 addr) |
182 | { |
183 | for (tab = tab->next; tab != NULL; tab = tab->next) |
184 | if (tab->addr == addr) |
185 | break; |
186 | |
187 | if (tab != NULL) |
188 | return tab->tcache_ptr; |
189 | |
190 | printf("block miss for %08x\n", addr); |
191 | return NULL; |
192 | } |
193 | |
f4bb5d6b |
194 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
679af8a3 |
195 | { |
f4bb5d6b |
196 | int *bcount = &block_counts[tcache_id]; |
679af8a3 |
197 | block_desc *bd; |
198 | |
f4bb5d6b |
199 | if (*bcount >= block_max_counts[tcache_id]) |
200 | return NULL; |
679af8a3 |
201 | |
f4bb5d6b |
202 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
203 | bd->addr = addr; |
204 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
205 | *blk_id = *bcount; |
206 | (*bcount)++; |
679af8a3 |
207 | |
208 | return bd; |
209 | } |
210 | |
211 | #define HASH_FUNC(hash_tab, addr) \ |
212 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
213 | |
214 | // --------------------------------------------------------------- |
215 | |
c18edb34 |
216 | // register chache |
217 | static u16 rcache_counter; |
218 | |
219 | static temp_reg_t *rcache_evict(void) |
41397701 |
220 | { |
c18edb34 |
221 | // evict reg with oldest stamp |
222 | int i, oldest = -1; |
223 | u16 min_stamp = (u16)-1; |
224 | |
225 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
226 | if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) |
227 | if (reg_temp[i].stamp <= min_stamp) { |
228 | min_stamp = reg_temp[i].stamp; |
229 | oldest = i; |
230 | } |
231 | } |
232 | |
233 | if (oldest == -1) { |
80599a42 |
234 | printf("no registers to evict, aborting\n"); |
c18edb34 |
235 | exit(1); |
236 | } |
237 | |
238 | i = oldest; |
239 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
240 | // writeback |
241 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
242 | } |
243 | |
244 | return ®_temp[i]; |
679af8a3 |
245 | } |
246 | |
c18edb34 |
247 | typedef enum { |
248 | RC_GR_READ, |
249 | RC_GR_WRITE, |
250 | RC_GR_RMW, |
251 | } rc_gr_mode; |
252 | |
80599a42 |
253 | // note: must not be called when doing conditional code |
c18edb34 |
254 | static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode) |
679af8a3 |
255 | { |
c18edb34 |
256 | temp_reg_t *tr; |
257 | int i; |
258 | |
259 | // maybe already statically mapped? |
260 | i = reg_map_g2h[r]; |
261 | if (i != -1) |
262 | return i; |
679af8a3 |
263 | |
c18edb34 |
264 | rcache_counter++; |
265 | |
266 | // maybe already cached? |
267 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
268 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
269 | reg_temp[i].val == r) |
270 | { |
271 | reg_temp[i].stamp = rcache_counter; |
272 | if (mode != RC_GR_READ) |
273 | reg_temp[i].type = HR_CACHED_DIRTY; |
274 | return reg_temp[i].reg; |
275 | } |
679af8a3 |
276 | } |
277 | |
c18edb34 |
278 | // use any free reg |
279 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
280 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
281 | tr = ®_temp[i]; |
282 | goto do_alloc; |
283 | } |
284 | } |
285 | |
286 | tr = rcache_evict(); |
287 | |
288 | do_alloc: |
289 | if (mode != RC_GR_WRITE) |
290 | emith_ctx_read(tr->reg, r * 4); |
679af8a3 |
291 | |
c18edb34 |
292 | tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED; |
293 | tr->val = r; |
294 | tr->stamp = rcache_counter; |
295 | return tr->reg; |
679af8a3 |
296 | } |
297 | |
c18edb34 |
298 | static int rcache_get_tmp(void) |
679af8a3 |
299 | { |
c18edb34 |
300 | temp_reg_t *tr; |
301 | int i; |
302 | |
303 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
304 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
305 | tr = ®_temp[i]; |
306 | goto do_alloc; |
307 | } |
308 | |
309 | tr = rcache_evict(); |
310 | |
311 | do_alloc: |
312 | tr->type = HR_TEMP; |
313 | return tr->reg; |
314 | } |
315 | |
80599a42 |
316 | static int rcache_get_arg_id(int arg) |
317 | { |
318 | int i, r = 0; |
319 | host_arg2reg(r, arg); |
320 | |
321 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
322 | if (reg_temp[i].reg == r) |
323 | break; |
324 | |
325 | if (i == ARRAY_SIZE(reg_temp)) |
326 | // let's just say it's untracked arg reg |
327 | return r; |
328 | |
329 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
330 | // writeback |
331 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
332 | } |
333 | else if (reg_temp[i].type == HR_TEMP) { |
334 | printf("arg %d reg %d already used, aborting\n", arg, r); |
335 | exit(1); |
336 | } |
337 | |
338 | return i; |
339 | } |
340 | |
341 | // get a reg to be used as function arg |
342 | // it's assumed that regs are cleaned before call |
343 | static int rcache_get_tmp_arg(int arg) |
344 | { |
345 | int id = rcache_get_arg_id(arg); |
346 | reg_temp[id].type = HR_TEMP; |
347 | |
348 | return reg_temp[id].reg; |
349 | } |
350 | |
351 | // same but caches reg. RC_GR_READ only. |
352 | static int rcache_get_reg_arg(int arg, sh2_reg_e r) |
353 | { |
354 | int i, srcr, dstr, dstid; |
355 | |
356 | dstid = rcache_get_arg_id(arg); |
357 | dstr = reg_temp[dstid].reg; |
358 | |
359 | // maybe already statically mapped? |
360 | srcr = reg_map_g2h[r]; |
361 | if (srcr != -1) |
362 | goto do_cache; |
363 | |
364 | // maybe already cached? |
365 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
366 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
367 | reg_temp[i].val == r) |
368 | { |
369 | srcr = reg_temp[i].reg; |
370 | goto do_cache; |
371 | } |
372 | } |
373 | |
374 | // must read |
375 | srcr = dstr; |
376 | emith_ctx_read(srcr, r * 4); |
377 | |
378 | do_cache: |
379 | if (srcr != dstr) |
380 | emith_move_r_r(dstr, srcr); |
381 | |
382 | reg_temp[dstid].stamp = ++rcache_counter; |
383 | reg_temp[dstid].type = HR_CACHED; |
384 | reg_temp[dstid].val = r; |
385 | return dstr; |
386 | } |
387 | |
c18edb34 |
388 | static void rcache_free_tmp(int hr) |
389 | { |
390 | int i; |
391 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
392 | if (reg_temp[i].reg == hr) |
393 | break; |
394 | |
80599a42 |
395 | if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) { |
c18edb34 |
396 | printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type); |
80599a42 |
397 | return; |
398 | } |
399 | |
400 | reg_temp[i].type = HR_FREE; |
c18edb34 |
401 | } |
402 | |
80599a42 |
403 | static void rcache_clean(void) |
c18edb34 |
404 | { |
405 | int i; |
80599a42 |
406 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
407 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
408 | // writeback |
409 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
80599a42 |
410 | reg_temp[i].type = HR_CACHED; |
c18edb34 |
411 | } |
80599a42 |
412 | } |
413 | |
414 | static void rcache_invalidate(void) |
415 | { |
416 | int i; |
417 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
418 | reg_temp[i].type = HR_FREE; |
c18edb34 |
419 | rcache_counter = 0; |
420 | } |
421 | |
80599a42 |
422 | static void rcache_flush(void) |
423 | { |
424 | rcache_clean(); |
425 | rcache_invalidate(); |
426 | } |
427 | |
c18edb34 |
428 | // --------------------------------------------------------------- |
429 | |
430 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
431 | { |
52d759c3 |
432 | // TODO: propagate this constant |
c18edb34 |
433 | int hr = rcache_get_reg(dst, RC_GR_WRITE); |
434 | emith_move_r_imm(hr, imm); |
435 | } |
436 | |
437 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
438 | { |
439 | int hr_d = rcache_get_reg(dst, RC_GR_WRITE); |
440 | int hr_s = rcache_get_reg(src, RC_GR_READ); |
441 | |
442 | emith_move_r_r(hr_d, hr_s); |
679af8a3 |
443 | } |
444 | |
52d759c3 |
445 | // T must be clear, and comparison done just before this |
446 | static void emit_or_t_if_eq(int srr) |
447 | { |
448 | EMITH_SJMP_START(DCOND_NE); |
449 | emith_or_r_imm_c(DCOND_EQ, srr, T); |
450 | EMITH_SJMP_END(DCOND_NE); |
451 | } |
452 | |
80599a42 |
453 | // arguments must be ready |
454 | // reg cache must be clean before call |
455 | static int emit_memhandler_read(int size) |
679af8a3 |
456 | { |
80599a42 |
457 | int ctxr; |
458 | host_arg2reg(ctxr, 1); |
459 | emith_move_r_r(ctxr, CONTEXT_REG); |
460 | switch (size) { |
461 | case 0: // 8 |
462 | emith_call(p32x_sh2_read8); |
463 | break; |
464 | case 1: // 16 |
465 | emith_call(p32x_sh2_read16); |
466 | break; |
467 | case 2: // 32 |
468 | emith_call(p32x_sh2_read32); |
679af8a3 |
469 | break; |
470 | } |
80599a42 |
471 | rcache_invalidate(); |
472 | // assuming arg0 and retval reg matches |
473 | return rcache_get_tmp_arg(0); |
474 | } |
679af8a3 |
475 | |
80599a42 |
476 | static void emit_memhandler_write(int size) |
477 | { |
478 | int ctxr; |
479 | host_arg2reg(ctxr, 2); |
480 | emith_move_r_r(ctxr, CONTEXT_REG); |
481 | switch (size) { |
482 | case 0: // 8 |
483 | emith_call(p32x_sh2_write8); |
484 | break; |
485 | case 1: // 16 |
486 | emith_call(p32x_sh2_write16); |
487 | break; |
488 | case 2: // 32 |
489 | emith_call(p32x_sh2_write32); |
490 | break; |
491 | } |
492 | rcache_invalidate(); |
679af8a3 |
493 | } |
80599a42 |
494 | |
52d759c3 |
495 | // @(Rx,Ry) |
496 | static int emit_indirect_indexed_read(int rx, int ry, int size) |
497 | { |
498 | int a0, t; |
499 | rcache_clean(); |
500 | a0 = rcache_get_reg_arg(0, rx); |
501 | t = rcache_get_reg(ry, RC_GR_READ); |
502 | emith_add_r_r(a0, t); |
503 | return emit_memhandler_read(size); |
504 | } |
505 | |
506 | // Rwr -> @(Rx,Ry) |
507 | static void emit_indirect_indexed_write(int rx, int ry, int wr, int size) |
508 | { |
509 | int a0, t; |
510 | rcache_clean(); |
511 | rcache_get_reg_arg(1, wr); |
512 | a0 = rcache_get_reg_arg(0, rx); |
513 | t = rcache_get_reg(ry, RC_GR_READ); |
514 | emith_add_r_r(a0, t); |
515 | emit_memhandler_write(size); |
516 | } |
517 | |
f0d7b1fa |
518 | // read @Rn, @rm |
519 | static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size) |
520 | { |
521 | int tmp; |
522 | |
523 | rcache_clean(); |
524 | rcache_get_reg_arg(0, rn); |
525 | tmp = emit_memhandler_read(size); |
526 | emith_ctx_write(tmp, offsetof(SH2, drc_tmp)); |
527 | rcache_free_tmp(tmp); |
528 | tmp = rcache_get_reg(rn, RC_GR_RMW); |
529 | emith_add_r_imm(tmp, 1 << size); |
530 | |
531 | rcache_clean(); |
532 | rcache_get_reg_arg(0, rm); |
533 | *rmr = emit_memhandler_read(size); |
534 | *rnr = rcache_get_tmp(); |
535 | emith_ctx_read(*rnr, offsetof(SH2, drc_tmp)); |
536 | tmp = rcache_get_reg(rm, RC_GR_RMW); |
537 | emith_add_r_imm(tmp, 1 << size); |
538 | } |
539 | |
540 | // fixup for saturated MAC, to be called from generated code |
541 | // FIXME: statically alloced regs need to be fixed |
542 | static void sh2_macl_sat_fixup(void) |
543 | { |
544 | if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000) |
545 | { |
546 | sh2->mach = 0x00008000; |
547 | sh2->macl = 0x00000000; |
548 | } |
549 | else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff) |
550 | { |
551 | sh2->mach = 0x00007fff; |
552 | sh2->macl = 0xffffffff; |
553 | } |
554 | } |
555 | |
556 | static void sh2_macw_sat_fixup(void) |
557 | { |
558 | signed int t = sh2->mach; |
559 | if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000))) |
560 | { |
561 | sh2->mach = 0xffffffff; // ? |
562 | sh2->macl = 0x80000000; |
563 | } |
564 | else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000))) |
565 | { |
566 | sh2->mach = 0x7fffffff; |
567 | sh2->macl = 0xffffffff; |
568 | } |
569 | } |
679af8a3 |
570 | |
e898de13 |
571 | #define DELAYED_OP \ |
572 | delayed_op = 2 |
573 | |
574 | #define CHECK_UNHANDLED_BITS(mask) { \ |
575 | if ((op & (mask)) != 0) \ |
576 | goto default_; \ |
577 | } |
578 | |
80599a42 |
579 | #define GET_Fx() \ |
580 | ((op >> 4) & 0x0f) |
581 | |
582 | #define GET_Rm GET_Fx |
583 | |
584 | #define GET_Rn() \ |
585 | ((op >> 8) & 0x0f) |
586 | |
ed8cf79b |
587 | #define CHECK_FX_LT(n) \ |
52d759c3 |
588 | if (GET_Fx() >= n) \ |
80599a42 |
589 | goto default_ |
590 | |
679af8a3 |
591 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
592 | { |
f4bb5d6b |
593 | void *block_entry; |
679af8a3 |
594 | block_desc *this_block; |
41397701 |
595 | unsigned int pc = sh2->pc; |
e898de13 |
596 | int op, delayed_op = 0, test_irq = 0; |
f4bb5d6b |
597 | int tcache_id = 0, blkid = 0; |
679af8a3 |
598 | int cycles = 0; |
f0d7b1fa |
599 | u32 tmp, tmp2, tmp3, tmp4, sr; |
679af8a3 |
600 | |
f4bb5d6b |
601 | // validate PC |
602 | tmp = sh2->pc >> 29; |
603 | if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { |
604 | printf("invalid PC, aborting: %08x\n", sh2->pc); |
605 | // FIXME: be less destructive |
606 | exit(1); |
607 | } |
608 | |
609 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
610 | // data_array, BIOS have separate tcache (shared) |
611 | tcache_id = 1 + sh2->is_slave; |
612 | } |
613 | |
614 | tcache_ptr = tcache_ptrs[tcache_id]; |
615 | this_block = dr_add_block(pc, tcache_id, &blkid); |
616 | |
617 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
618 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { |
619 | flush_tcache(tcache_id); |
620 | tcache_ptr = tcache_ptrs[tcache_id]; |
621 | other_block = NULL; // also gone too due to flush |
622 | this_block = dr_add_block(pc, tcache_id, &blkid); |
623 | } |
e898de13 |
624 | |
f4bb5d6b |
625 | this_block->next = other_block; |
626 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
627 | HASH_FUNC(hash_table, pc) = this_block; |
679af8a3 |
628 | |
f4bb5d6b |
629 | block_entry = tcache_ptr; |
e898de13 |
630 | #if (DRC_DEBUG & 1) |
f4bb5d6b |
631 | printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
632 | tcache_id, block_counts[tcache_id], pc, block_entry); |
e898de13 |
633 | if (other_block != NULL) { |
634 | printf(" hash collision with %08x\n", other_block->addr); |
635 | hash_collisions++; |
636 | } |
679af8a3 |
637 | #endif |
638 | |
e898de13 |
639 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
679af8a3 |
640 | { |
e898de13 |
641 | if (delayed_op > 0) |
642 | delayed_op--; |
643 | |
2b2b46b0 |
644 | op = p32x_sh2_read16(pc, sh2); |
e898de13 |
645 | |
646 | #if (DRC_DEBUG & 3) |
647 | insns_compiled++; |
648 | #if (DRC_DEBUG & 2) |
649 | DasmSH2(sh2dasm_buff, pc, op); |
650 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
651 | #endif |
679af8a3 |
652 | #endif |
679af8a3 |
653 | |
654 | pc += 2; |
655 | cycles++; |
656 | |
657 | switch ((op >> 12) & 0x0f) |
658 | { |
3863edbd |
659 | ///////////////////////////////////////////// |
679af8a3 |
660 | case 0x00: |
80599a42 |
661 | switch (op & 0x0f) |
662 | { |
663 | case 0x02: |
664 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
665 | switch (GET_Fx()) |
666 | { |
667 | case 0: // STC SR,Rn 0000nnnn00000010 |
668 | tmp2 = SHR_SR; |
669 | break; |
670 | case 1: // STC GBR,Rn 0000nnnn00010010 |
671 | tmp2 = SHR_GBR; |
672 | break; |
673 | case 2: // STC VBR,Rn 0000nnnn00100010 |
674 | tmp2 = SHR_VBR; |
675 | break; |
676 | default: |
677 | goto default_; |
678 | } |
ed8cf79b |
679 | tmp3 = rcache_get_reg(tmp2, RC_GR_READ); |
680 | emith_move_r_r(tmp, tmp3); |
681 | if (tmp2 == SHR_SR) |
682 | emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0 |
80599a42 |
683 | goto end_op; |
e898de13 |
684 | case 0x03: |
685 | CHECK_UNHANDLED_BITS(0xd0); |
686 | // BRAF Rm 0000mmmm00100011 |
687 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
688 | DELAYED_OP; |
e898de13 |
689 | if (!(op & 0x20)) |
690 | emit_move_r_imm32(SHR_PR, pc + 2); |
c18edb34 |
691 | tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE); |
80599a42 |
692 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
c18edb34 |
693 | emith_move_r_r(tmp, tmp2); |
694 | emith_add_r_imm(tmp, pc + 2); |
679af8a3 |
695 | cycles++; |
e898de13 |
696 | goto end_op; |
80599a42 |
697 | case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 |
698 | case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 |
699 | case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 |
52d759c3 |
700 | emit_indirect_indexed_write(SHR_R0, GET_Rn(), GET_Rm(), op & 3); |
80599a42 |
701 | goto end_op; |
702 | case 0x07: |
703 | // MUL.L Rm,Rn 0000nnnnmmmm0111 |
704 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
705 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
706 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
707 | emith_mul(tmp3, tmp2, tmp); |
708 | cycles++; |
709 | goto end_op; |
710 | case 0x08: |
711 | CHECK_UNHANDLED_BITS(0xf00); |
712 | switch (GET_Fx()) |
713 | { |
714 | case 0: // CLRT 0000000000001000 |
715 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
716 | emith_bic_r_imm(tmp, T); |
717 | break; |
718 | case 1: // SETT 0000000000011000 |
719 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
720 | emith_or_r_imm(tmp, T); |
721 | break; |
722 | case 2: // CLRMAC 0000000000101000 |
723 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
724 | emith_move_r_imm(tmp, 0); |
725 | tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
726 | emith_move_r_imm(tmp, 0); |
727 | break; |
728 | default: |
729 | goto default_; |
730 | } |
731 | goto end_op; |
e898de13 |
732 | case 0x09: |
80599a42 |
733 | switch (GET_Fx()) |
734 | { |
735 | case 0: // NOP 0000000000001001 |
736 | CHECK_UNHANDLED_BITS(0xf00); |
737 | break; |
738 | case 1: // DIV0U 0000000000011001 |
739 | CHECK_UNHANDLED_BITS(0xf00); |
740 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
741 | emith_bic_r_imm(tmp, M|Q|T); |
742 | break; |
743 | case 2: // MOVT Rn 0000nnnn00101001 |
744 | tmp = rcache_get_reg(SHR_SR, RC_GR_READ); |
745 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
746 | emith_clear_msb(tmp2, tmp, 31); |
747 | break; |
748 | default: |
749 | goto default_; |
750 | } |
751 | goto end_op; |
752 | case 0x0a: |
753 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
754 | switch (GET_Fx()) |
755 | { |
756 | case 0: // STS MACH,Rn 0000nnnn00001010 |
ed8cf79b |
757 | tmp2 = SHR_MACH; |
80599a42 |
758 | break; |
759 | case 1: // STS MACL,Rn 0000nnnn00011010 |
ed8cf79b |
760 | tmp2 = SHR_MACL; |
80599a42 |
761 | break; |
762 | case 2: // STS PR,Rn 0000nnnn00101010 |
ed8cf79b |
763 | tmp2 = SHR_PR; |
80599a42 |
764 | break; |
765 | default: |
766 | goto default_; |
767 | } |
ed8cf79b |
768 | tmp2 = rcache_get_reg(tmp2, RC_GR_READ); |
80599a42 |
769 | emith_move_r_r(tmp, tmp2); |
e898de13 |
770 | goto end_op; |
771 | case 0x0b: |
80599a42 |
772 | CHECK_UNHANDLED_BITS(0xf00); |
773 | switch (GET_Fx()) |
774 | { |
775 | case 0: // RTS 0000000000001011 |
776 | DELAYED_OP; |
e898de13 |
777 | emit_move_r_r(SHR_PPC, SHR_PR); |
778 | cycles++; |
80599a42 |
779 | break; |
780 | case 1: // SLEEP 0000000000011011 |
781 | emit_move_r_imm32(SHR_PC, pc - 2); |
782 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
783 | emith_clear_msb(tmp, tmp, 20); // clear cycles |
784 | test_irq = 1; |
785 | cycles = 1; |
786 | break; |
787 | case 2: // RTE 0000000000101011 |
52d759c3 |
788 | DELAYED_OP; |
789 | rcache_clean(); |
790 | // pop PC |
791 | rcache_get_reg_arg(0, SHR_SP); |
792 | tmp = emit_memhandler_read(2); |
793 | tmp2 = rcache_get_reg(SHR_PPC, RC_GR_WRITE); |
794 | emith_move_r_r(tmp2, tmp); |
795 | rcache_free_tmp(tmp); |
796 | rcache_clean(); |
797 | // pop SR |
798 | tmp = rcache_get_reg_arg(0, SHR_SP); |
799 | emith_add_r_imm(tmp, 4); |
800 | tmp = emit_memhandler_read(2); |
801 | emith_write_sr(tmp); |
802 | rcache_free_tmp(tmp); |
803 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
804 | emith_add_r_imm(tmp, 4*2); |
e898de13 |
805 | test_irq = 1; |
806 | cycles += 3; |
80599a42 |
807 | break; |
808 | default: |
809 | goto default_; |
e898de13 |
810 | } |
811 | goto end_op; |
80599a42 |
812 | case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 |
813 | case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 |
814 | case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 |
52d759c3 |
815 | tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3); |
80599a42 |
816 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
80599a42 |
817 | if ((op & 3) != 2) { |
818 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
819 | } else |
820 | emith_move_r_r(tmp2, tmp); |
52d759c3 |
821 | rcache_free_tmp(tmp); |
80599a42 |
822 | goto end_op; |
823 | case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 |
f0d7b1fa |
824 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2); |
825 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
826 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
827 | /* MS 16 MAC bits unused if saturated */ |
828 | emith_tst_r_imm(tmp3, S); |
829 | EMITH_SJMP_START(DCOND_EQ); |
830 | emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16); |
831 | EMITH_SJMP_END(DCOND_EQ); |
832 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR |
833 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
834 | rcache_free_tmp(tmp); |
835 | rcache_free_tmp(tmp2); |
836 | rcache_clean(); |
837 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
838 | emith_tst_r_imm(tmp3, S); |
839 | EMITH_SJMP_START(DCOND_EQ); |
840 | emith_call_cond(DCOND_NE, sh2_macl_sat_fixup); |
841 | EMITH_SJMP_END(DCOND_EQ); |
842 | rcache_invalidate(); |
843 | cycles += 3; |
844 | goto end_op; |
80599a42 |
845 | } |
846 | goto default_; |
847 | |
3863edbd |
848 | ///////////////////////////////////////////// |
80599a42 |
849 | case 0x01: |
850 | // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd |
851 | rcache_clean(); |
852 | tmp = rcache_get_reg_arg(0, GET_Rn()); |
853 | tmp2 = rcache_get_reg_arg(1, GET_Rm()); |
854 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
855 | emit_memhandler_write(2); |
856 | goto end_op; |
857 | |
858 | case 0x02: |
859 | switch (op & 0x0f) |
860 | { |
861 | case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000 |
862 | case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001 |
863 | case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010 |
864 | rcache_clean(); |
865 | rcache_get_reg_arg(0, GET_Rn()); |
866 | rcache_get_reg_arg(1, GET_Rm()); |
867 | emit_memhandler_write(op & 3); |
868 | goto end_op; |
869 | case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 |
870 | case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 |
871 | case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110 |
872 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
873 | emith_sub_r_imm(tmp, (1 << (op & 3))); |
874 | rcache_clean(); |
875 | rcache_get_reg_arg(0, GET_Rn()); |
876 | rcache_get_reg_arg(1, GET_Rm()); |
877 | emit_memhandler_write(op & 3); |
878 | goto end_op; |
879 | case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 |
880 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
881 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
882 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
883 | emith_bic_r_imm(tmp, M|Q|T); |
884 | emith_tst_r_imm(tmp2, (1<<31)); |
885 | EMITH_SJMP_START(DCOND_EQ); |
886 | emith_or_r_imm_c(DCOND_NE, tmp, Q); |
887 | EMITH_SJMP_END(DCOND_EQ); |
888 | emith_tst_r_imm(tmp3, (1<<31)); |
889 | EMITH_SJMP_START(DCOND_EQ); |
890 | emith_or_r_imm_c(DCOND_NE, tmp, M); |
891 | EMITH_SJMP_END(DCOND_EQ); |
892 | emith_teq_r_r(tmp2, tmp3); |
893 | EMITH_SJMP_START(DCOND_PL); |
894 | emith_or_r_imm_c(DCOND_MI, tmp, T); |
895 | EMITH_SJMP_END(DCOND_PL); |
896 | goto end_op; |
3863edbd |
897 | case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 |
898 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
899 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
900 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
901 | emith_bic_r_imm(tmp, T); |
902 | emith_tst_r_r(tmp2, tmp3); |
52d759c3 |
903 | emit_or_t_if_eq(tmp); |
3863edbd |
904 | goto end_op; |
905 | case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 |
906 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
907 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
908 | emith_and_r_r(tmp, tmp2); |
909 | goto end_op; |
910 | case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010 |
911 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
912 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
913 | emith_eor_r_r(tmp, tmp2); |
914 | goto end_op; |
915 | case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011 |
916 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
917 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
918 | emith_or_r_r(tmp, tmp2); |
919 | goto end_op; |
920 | case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100 |
921 | tmp = rcache_get_tmp(); |
922 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
923 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
924 | emith_eor_r_r_r(tmp, tmp2, tmp3); |
925 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
926 | emith_bic_r_imm(tmp2, T); |
927 | emith_tst_r_imm(tmp, 0x000000ff); |
52d759c3 |
928 | emit_or_t_if_eq(tmp); |
3863edbd |
929 | emith_tst_r_imm(tmp, 0x0000ff00); |
52d759c3 |
930 | emit_or_t_if_eq(tmp); |
3863edbd |
931 | emith_tst_r_imm(tmp, 0x00ff0000); |
52d759c3 |
932 | emit_or_t_if_eq(tmp); |
3863edbd |
933 | emith_tst_r_imm(tmp, 0xff000000); |
52d759c3 |
934 | emit_or_t_if_eq(tmp); |
3863edbd |
935 | rcache_free_tmp(tmp); |
936 | goto end_op; |
937 | case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101 |
938 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
939 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
940 | emith_lsr(tmp, tmp, 16); |
f0d7b1fa |
941 | emith_or_r_r_lsl(tmp, tmp2, 16); |
3863edbd |
942 | goto end_op; |
943 | case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110 |
944 | case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111 |
945 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
946 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
947 | if (op & 1) { |
948 | emith_sext(tmp, tmp2, 16); |
949 | } else |
950 | emith_clear_msb(tmp, tmp2, 16); |
951 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
952 | tmp2 = rcache_get_tmp(); |
953 | if (op & 1) { |
954 | emith_sext(tmp2, tmp3, 16); |
955 | } else |
956 | emith_clear_msb(tmp2, tmp3, 16); |
957 | emith_mul(tmp, tmp, tmp2); |
958 | rcache_free_tmp(tmp2); |
959 | // FIXME: causes timing issues in Doom? |
960 | // cycles++; |
961 | goto end_op; |
679af8a3 |
962 | } |
963 | goto default_; |
964 | |
3863edbd |
965 | ///////////////////////////////////////////// |
966 | case 0x03: |
967 | switch (op & 0x0f) |
968 | { |
969 | case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000 |
970 | case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010 |
971 | case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 |
972 | case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 |
973 | case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 |
974 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
975 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
976 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
977 | emith_bic_r_imm(tmp, T); |
978 | emith_cmp_r_r(tmp2, tmp3); |
979 | switch (op & 0x07) |
980 | { |
981 | case 0x00: // CMP/EQ |
52d759c3 |
982 | emit_or_t_if_eq(tmp); |
3863edbd |
983 | break; |
984 | case 0x02: // CMP/HS |
985 | EMITH_SJMP_START(DCOND_LO); |
986 | emith_or_r_imm_c(DCOND_HS, tmp, T); |
987 | EMITH_SJMP_END(DCOND_LO); |
988 | break; |
989 | case 0x03: // CMP/GE |
990 | EMITH_SJMP_START(DCOND_LT); |
991 | emith_or_r_imm_c(DCOND_GE, tmp, T); |
992 | EMITH_SJMP_END(DCOND_LT); |
993 | break; |
994 | case 0x06: // CMP/HI |
995 | EMITH_SJMP_START(DCOND_LS); |
996 | emith_or_r_imm_c(DCOND_HI, tmp, T); |
997 | EMITH_SJMP_END(DCOND_LS); |
998 | break; |
999 | case 0x07: // CMP/GT |
1000 | EMITH_SJMP_START(DCOND_LE); |
1001 | emith_or_r_imm_c(DCOND_GT, tmp, T); |
1002 | EMITH_SJMP_END(DCOND_LE); |
1003 | break; |
1004 | } |
1005 | goto end_op; |
1006 | case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100 |
f0d7b1fa |
1007 | // Q1 = carry(Rn = (Rn << 1) | T) |
1008 | // if Q ^ M |
1009 | // Q2 = carry(Rn += Rm) |
1010 | // else |
1011 | // Q2 = carry(Rn -= Rm) |
1012 | // Q = M ^ Q1 ^ Q2 |
1013 | // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2) |
1014 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1015 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1016 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1017 | emith_set_carry(sr); |
1018 | emith_adcf_r_r(tmp2, tmp2); |
1019 | emith_carry_to_t(sr, 0); // keep Q1 in T for now |
1020 | tmp4 = rcache_get_tmp(); |
1021 | emith_and_r_r_imm(tmp4, sr, M); |
1022 | emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M |
1023 | rcache_free_tmp(tmp4); |
1024 | // add or sub, invert T if carry to get Q1 ^ Q2 |
1025 | // in: (Q ^ M) passed in Q, Q1 in T |
1026 | emith_sh2_div1_step(tmp2, tmp3, sr); |
1027 | emith_bic_r_imm(sr, Q); |
1028 | emith_tst_r_imm(sr, M); |
1029 | EMITH_SJMP_START(DCOND_EQ); |
1030 | emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M |
1031 | EMITH_SJMP_END(DCOND_EQ); |
1032 | emith_tst_r_imm(sr, T); |
1033 | EMITH_SJMP_START(DCOND_EQ); |
1034 | emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 |
1035 | EMITH_SJMP_END(DCOND_EQ); |
1036 | emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) |
1037 | goto end_op; |
3863edbd |
1038 | case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 |
1039 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1040 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1041 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1042 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1043 | emith_mul_u64(tmp3, tmp4, tmp, tmp2); |
1044 | goto end_op; |
1045 | case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 |
1046 | case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 |
1047 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1048 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1049 | if (op & 4) { |
1050 | emith_add_r_r(tmp, tmp2); |
1051 | } else |
1052 | emith_sub_r_r(tmp, tmp2); |
1053 | goto end_op; |
1054 | case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010 |
1055 | case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 |
1056 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1057 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1058 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1059 | if (op & 4) { // adc |
1060 | emith_set_carry(tmp3); |
1061 | emith_adcf_r_r(tmp, tmp2); |
ed8cf79b |
1062 | emith_carry_to_t(tmp3, 0); |
3863edbd |
1063 | } else { |
1064 | emith_set_carry_sub(tmp3); |
1065 | emith_sbcf_r_r(tmp, tmp2); |
ed8cf79b |
1066 | emith_carry_to_t(tmp3, 1); |
3863edbd |
1067 | } |
3863edbd |
1068 | goto end_op; |
1069 | case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 |
1070 | case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 |
1071 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1072 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1073 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1074 | emith_bic_r_imm(tmp3, T); |
1075 | if (op & 4) { |
1076 | emith_addf_r_r(tmp, tmp2); |
1077 | } else |
1078 | emith_subf_r_r(tmp, tmp2); |
1079 | EMITH_SJMP_START(DCOND_VC); |
1080 | emith_or_r_imm_c(DCOND_VS, tmp3, T); |
1081 | EMITH_SJMP_END(DCOND_VC); |
1082 | goto end_op; |
1083 | case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 |
1084 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1085 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1086 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1087 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1088 | emith_mul_s64(tmp3, tmp4, tmp, tmp2); |
1089 | goto end_op; |
1090 | } |
1091 | goto default_; |
1092 | |
1093 | ///////////////////////////////////////////// |
679af8a3 |
1094 | case 0x04: |
3863edbd |
1095 | switch (op & 0x0f) |
1096 | { |
c18edb34 |
1097 | case 0x00: |
3863edbd |
1098 | switch (GET_Fx()) |
1099 | { |
1100 | case 0: // SHLL Rn 0100nnnn00000000 |
1101 | case 2: // SHAL Rn 0100nnnn00100000 |
1102 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1103 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1104 | emith_lslf(tmp, tmp, 1); |
ed8cf79b |
1105 | emith_carry_to_t(tmp2, 0); |
3863edbd |
1106 | goto end_op; |
1107 | case 1: // DT Rn 0100nnnn00010000 |
1108 | if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 |
1109 | emith_sh2_dtbf_loop(); |
1110 | goto end_op; |
1111 | } |
1112 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1113 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1114 | emith_bic_r_imm(tmp2, T); |
1115 | emith_subf_r_imm(tmp, 1); |
52d759c3 |
1116 | emit_or_t_if_eq(tmp2); |
80599a42 |
1117 | goto end_op; |
1118 | } |
3863edbd |
1119 | goto default_; |
ed8cf79b |
1120 | case 0x01: |
1121 | switch (GET_Fx()) |
1122 | { |
1123 | case 0: // SHLR Rn 0100nnnn00000001 |
1124 | case 2: // SHAR Rn 0100nnnn00100001 |
1125 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1126 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1127 | if (op & 0x20) { |
1128 | emith_asrf(tmp, tmp, 1); |
1129 | } else |
1130 | emith_lsrf(tmp, tmp, 1); |
1131 | emith_carry_to_t(tmp2, 0); |
1132 | goto end_op; |
1133 | case 1: // CMP/PZ Rn 0100nnnn00010001 |
1134 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1135 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1136 | emith_bic_r_imm(tmp2, T); |
1137 | emith_cmp_r_imm(tmp, 0); |
1138 | EMITH_SJMP_START(DCOND_LT); |
1139 | emith_or_r_imm_c(DCOND_GE, tmp2, T); |
1140 | EMITH_SJMP_END(DCOND_LT); |
1141 | goto end_op; |
1142 | } |
1143 | goto default_; |
1144 | case 0x02: |
1145 | case 0x03: |
1146 | switch (op & 0x3f) |
1147 | { |
1148 | case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010 |
1149 | tmp = SHR_MACH; |
1150 | break; |
1151 | case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010 |
1152 | tmp = SHR_MACL; |
1153 | break; |
1154 | case 0x22: // STS.L PR,@–Rn 0100nnnn00100010 |
1155 | tmp = SHR_PR; |
1156 | break; |
1157 | case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 |
1158 | tmp = SHR_SR; |
1159 | break; |
1160 | case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 |
1161 | tmp = SHR_GBR; |
1162 | break; |
1163 | case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 |
1164 | tmp = SHR_VBR; |
1165 | break; |
1166 | default: |
e898de13 |
1167 | goto default_; |
ed8cf79b |
1168 | } |
1169 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1170 | emith_sub_r_imm(tmp2, 4); |
1171 | rcache_clean(); |
1172 | rcache_get_reg_arg(0, GET_Rn()); |
1173 | tmp3 = rcache_get_reg_arg(1, tmp); |
1174 | if (tmp == SHR_SR) |
1175 | emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0 |
1176 | emit_memhandler_write(2); |
1177 | goto end_op; |
1178 | case 0x04: |
1179 | case 0x05: |
1180 | switch (op & 0x3f) |
1181 | { |
1182 | case 0x04: // ROTL Rn 0100nnnn00000100 |
1183 | case 0x05: // ROTR Rn 0100nnnn00000101 |
1184 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1185 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1186 | if (op & 1) { |
1187 | emith_rorf(tmp, tmp, 1); |
1188 | } else |
1189 | emith_rolf(tmp, tmp, 1); |
1190 | emith_carry_to_t(tmp2, 0); |
1191 | goto end_op; |
1192 | case 0x24: // ROTCL Rn 0100nnnn00100100 |
1193 | case 0x25: // ROTCR Rn 0100nnnn00100101 |
1194 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1195 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1196 | emith_set_carry(tmp2); |
1197 | if (op & 1) { |
1198 | emith_rorcf(tmp); |
1199 | } else |
1200 | emith_rolcf(tmp); |
1201 | emith_carry_to_t(tmp2, 0); |
1202 | goto end_op; |
1203 | case 0x15: // CMP/PL Rn 0100nnnn00010101 |
1204 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1205 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1206 | emith_bic_r_imm(tmp2, T); |
1207 | emith_cmp_r_imm(tmp, 0); |
1208 | EMITH_SJMP_START(DCOND_LE); |
1209 | emith_or_r_imm_c(DCOND_GT, tmp2, T); |
1210 | EMITH_SJMP_END(DCOND_LE); |
1211 | goto end_op; |
1212 | } |
e898de13 |
1213 | goto default_; |
ed8cf79b |
1214 | case 0x06: |
1215 | case 0x07: |
1216 | switch (op & 0x3f) |
1217 | { |
1218 | case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110 |
1219 | tmp = SHR_MACH; |
1220 | break; |
1221 | case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110 |
1222 | tmp = SHR_MACL; |
1223 | break; |
1224 | case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110 |
1225 | tmp = SHR_PR; |
1226 | break; |
1227 | case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 |
1228 | tmp = SHR_SR; |
1229 | break; |
1230 | case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 |
1231 | tmp = SHR_GBR; |
1232 | break; |
1233 | case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 |
1234 | tmp = SHR_VBR; |
1235 | break; |
1236 | default: |
1237 | goto default_; |
1238 | } |
1239 | rcache_clean(); |
1240 | rcache_get_reg_arg(0, GET_Rn()); |
1241 | tmp2 = emit_memhandler_read(2); |
1242 | if (tmp == SHR_SR) { |
1243 | emith_write_sr(tmp2); |
1244 | test_irq = 1; |
1245 | } else { |
1246 | tmp = rcache_get_reg(tmp, RC_GR_WRITE); |
1247 | emith_move_r_r(tmp, tmp2); |
1248 | } |
1249 | rcache_free_tmp(tmp2); |
1250 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1251 | emith_add_r_imm(tmp, 4); |
1252 | goto end_op; |
52d759c3 |
1253 | case 0x08: |
1254 | case 0x09: |
1255 | switch (GET_Fx()) |
1256 | { |
1257 | case 0: |
1258 | // SHLL2 Rn 0100nnnn00001000 |
1259 | // SHLR2 Rn 0100nnnn00001001 |
1260 | tmp = 2; |
1261 | break; |
1262 | case 1: |
1263 | // SHLL8 Rn 0100nnnn00011000 |
1264 | // SHLR8 Rn 0100nnnn00011001 |
1265 | tmp = 8; |
1266 | break; |
1267 | case 2: |
1268 | // SHLL16 Rn 0100nnnn00101000 |
1269 | // SHLR16 Rn 0100nnnn00101001 |
1270 | tmp = 16; |
1271 | break; |
1272 | default: |
1273 | goto default_; |
1274 | } |
1275 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1276 | if (op & 1) { |
1277 | emith_lsr(tmp2, tmp2, tmp); |
1278 | } else |
1279 | emith_lsl(tmp2, tmp2, tmp); |
1280 | goto end_op; |
1281 | case 0x0a: |
1282 | switch (GET_Fx()) |
1283 | { |
1284 | case 0: // LDS Rm,MACH 0100mmmm00001010 |
1285 | tmp2 = SHR_MACH; |
1286 | break; |
1287 | case 1: // LDS Rm,MACL 0100mmmm00011010 |
1288 | tmp2 = SHR_MACL; |
1289 | break; |
1290 | case 2: // LDS Rm,PR 0100mmmm00101010 |
1291 | tmp2 = SHR_PR; |
1292 | break; |
1293 | default: |
1294 | goto default_; |
1295 | } |
1296 | emit_move_r_r(tmp2, GET_Rn()); |
1297 | goto end_op; |
e898de13 |
1298 | case 0x0b: |
52d759c3 |
1299 | switch (GET_Fx()) |
1300 | { |
1301 | case 0: // JSR @Rm 0100mmmm00001011 |
1302 | case 2: // JMP @Rm 0100mmmm00101011 |
1303 | DELAYED_OP; |
1304 | if (!(op & 0x20)) |
1305 | emit_move_r_imm32(SHR_PR, pc + 2); |
1306 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
1307 | cycles++; |
1308 | break; |
1309 | case 1: // TAS.B @Rn 0100nnnn00011011 |
1310 | // XXX: is TAS working on 32X? |
1311 | rcache_clean(); |
1312 | rcache_get_reg_arg(0, GET_Rn()); |
1313 | tmp = emit_memhandler_read(0); |
1314 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1315 | emith_bic_r_imm(tmp2, T); |
1316 | emith_cmp_r_imm(tmp, 0); |
1317 | emit_or_t_if_eq(tmp2); |
1318 | rcache_clean(); |
1319 | emith_or_r_imm(tmp, 0x80); |
1320 | tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp |
1321 | emith_move_r_r(tmp2, tmp); |
1322 | rcache_free_tmp(tmp); |
1323 | rcache_get_reg_arg(0, GET_Rn()); |
1324 | emit_memhandler_write(0); |
1325 | cycles += 3; |
1326 | break; |
1327 | default: |
e898de13 |
1328 | goto default_; |
52d759c3 |
1329 | } |
e898de13 |
1330 | goto end_op; |
1331 | case 0x0e: |
52d759c3 |
1332 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1333 | switch (GET_Fx()) |
1334 | { |
1335 | case 0: // LDC Rm,SR 0100mmmm00001110 |
1336 | tmp2 = SHR_SR; |
1337 | break; |
1338 | case 1: // LDC Rm,GBR 0100mmmm00011110 |
1339 | tmp2 = SHR_GBR; |
1340 | break; |
1341 | case 2: // LDC Rm,VBR 0100mmmm00101110 |
1342 | tmp2 = SHR_VBR; |
1343 | break; |
1344 | default: |
e898de13 |
1345 | goto default_; |
52d759c3 |
1346 | } |
1347 | if (tmp2 == SHR_SR) { |
1348 | emith_write_sr(tmp); |
52d759c3 |
1349 | test_irq = 1; |
1350 | } else { |
1351 | tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE); |
1352 | emith_move_r_r(tmp2, tmp); |
1353 | } |
1354 | goto end_op; |
1355 | case 0x0f: |
1356 | // MAC @Rm+,@Rn+ 0100nnnnmmmm1111 |
f0d7b1fa |
1357 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1); |
1358 | emith_sext(tmp, tmp, 16); |
1359 | emith_sext(tmp2, tmp2, 16); |
1360 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); |
1361 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
1362 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
1363 | rcache_free_tmp(tmp); |
1364 | rcache_free_tmp(tmp2); |
1365 | rcache_clean(); |
1366 | // XXX: MACH should be untouched when S is set? |
1367 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
1368 | emith_tst_r_imm(tmp3, S); |
1369 | EMITH_SJMP_START(DCOND_EQ); |
1370 | emith_call_cond(DCOND_NE, sh2_macw_sat_fixup); |
1371 | EMITH_SJMP_END(DCOND_EQ); |
1372 | rcache_invalidate(); |
1373 | cycles += 2; |
1374 | goto end_op; |
679af8a3 |
1375 | } |
1376 | goto default_; |
1377 | |
52d759c3 |
1378 | ///////////////////////////////////////////// |
1379 | case 0x05: |
1380 | // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd |
1381 | rcache_clean(); |
1382 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1383 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
1384 | tmp = emit_memhandler_read(2); |
1385 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1386 | emith_move_r_r(tmp2, tmp); |
1387 | rcache_free_tmp(tmp); |
1388 | goto end_op; |
1389 | |
1390 | ///////////////////////////////////////////// |
1391 | case 0x06: |
1392 | switch (op & 0x0f) |
1393 | { |
1394 | case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000 |
1395 | case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001 |
1396 | case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010 |
1397 | case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100 |
1398 | case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101 |
1399 | case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110 |
1400 | rcache_clean(); |
1401 | rcache_get_reg_arg(0, GET_Rm()); |
1402 | tmp = emit_memhandler_read(op & 3); |
1403 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1404 | if ((op & 3) != 2) { |
1405 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
1406 | } else |
1407 | emith_move_r_r(tmp2, tmp); |
1408 | rcache_free_tmp(tmp); |
1409 | if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) { |
1410 | tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW); |
1411 | emith_add_r_imm(tmp, (1 << (op & 3))); |
1412 | } |
1413 | goto end_op; |
1414 | case 0x03: |
1415 | case 0x07 ... 0x0f: |
1416 | tmp = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1417 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1418 | switch (op & 0x0f) |
1419 | { |
1420 | case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011 |
1421 | emith_move_r_r(tmp2, tmp); |
1422 | break; |
1423 | case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111 |
1424 | emith_mvn_r_r(tmp2, tmp); |
1425 | break; |
1426 | case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000 |
1427 | tmp3 = tmp2; |
1428 | if (tmp == tmp2) |
1429 | tmp3 = rcache_get_tmp(); |
1430 | tmp4 = rcache_get_tmp(); |
1431 | emith_lsr(tmp3, tmp, 16); |
f0d7b1fa |
1432 | emith_or_r_r_lsl(tmp3, tmp, 24); |
52d759c3 |
1433 | emith_and_r_r_imm(tmp4, tmp, 0xff00); |
f0d7b1fa |
1434 | emith_or_r_r_lsl(tmp3, tmp4, 8); |
52d759c3 |
1435 | emith_rol(tmp2, tmp3, 16); |
1436 | rcache_free_tmp(tmp4); |
1437 | if (tmp == tmp2) |
1438 | rcache_free_tmp(tmp3); |
1439 | break; |
1440 | case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001 |
1441 | emith_rol(tmp2, tmp, 16); |
1442 | break; |
1443 | case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 |
1444 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1445 | emith_set_carry_sub(tmp3); |
1446 | emith_negcf_r_r(tmp2, tmp); |
1447 | emith_carry_to_t(tmp3, 1); |
1448 | break; |
1449 | case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011 |
1450 | emith_neg_r_r(tmp2, tmp); |
1451 | break; |
1452 | case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100 |
1453 | emith_clear_msb(tmp2, tmp, 24); |
1454 | break; |
1455 | case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101 |
1456 | emith_clear_msb(tmp2, tmp, 16); |
1457 | break; |
1458 | case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110 |
1459 | emith_sext(tmp2, tmp, 8); |
1460 | break; |
1461 | case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111 |
1462 | emith_sext(tmp2, tmp, 16); |
1463 | break; |
1464 | } |
1465 | goto end_op; |
1466 | } |
1467 | goto default_; |
1468 | |
1469 | ///////////////////////////////////////////// |
1470 | case 0x07: |
1471 | // ADD #imm,Rn 0111nnnniiiiiiii |
1472 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1473 | if (op & 0x80) { // adding negative |
1474 | emith_sub_r_imm(tmp, -op & 0xff); |
1475 | } else |
1476 | emith_add_r_imm(tmp, op & 0xff); |
1477 | goto end_op; |
1478 | |
3863edbd |
1479 | ///////////////////////////////////////////// |
e898de13 |
1480 | case 0x08: |
52d759c3 |
1481 | switch (op & 0x0f00) |
1482 | { |
1483 | case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd |
1484 | case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd |
1485 | rcache_clean(); |
1486 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1487 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
1488 | tmp3 = (op & 0x100) >> 8; |
1489 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
1490 | emit_memhandler_write(tmp3); |
1491 | goto end_op; |
1492 | case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd |
1493 | case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd |
1494 | rcache_clean(); |
1495 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1496 | tmp3 = (op & 0x100) >> 8; |
1497 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
1498 | tmp = emit_memhandler_read(tmp3); |
1499 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
1500 | emith_sext(tmp2, tmp, 8 << tmp3); |
1501 | rcache_free_tmp(tmp); |
1502 | goto end_op; |
1503 | case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii |
1504 | // XXX: could use cmn |
1505 | tmp = rcache_get_tmp(); |
1506 | tmp2 = rcache_get_reg(0, RC_GR_READ); |
1507 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1508 | emith_move_r_imm_s8(tmp, op & 0xff); |
1509 | emith_bic_r_imm(tmp3, T); |
1510 | emith_cmp_r_r(tmp2, tmp); |
1511 | emit_or_t_if_eq(tmp3); |
1512 | rcache_free_tmp(tmp); |
1513 | goto end_op; |
1514 | case 0x0d00: // BT/S label 10001101dddddddd |
1515 | case 0x0f00: // BF/S label 10001111dddddddd |
679af8a3 |
1516 | DELAYED_OP; |
1517 | cycles--; |
679af8a3 |
1518 | // fallthrough |
52d759c3 |
1519 | case 0x0900: // BT label 10001001dddddddd |
1520 | case 0x0b00: { // BF label 10001011dddddddd |
80599a42 |
1521 | // jmp_cond ~ cond when guest doesn't jump |
1522 | int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ; |
1523 | int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; |
1524 | signed int offs = ((signed int)(op << 24) >> 23); |
1525 | tmp = rcache_get_reg(delayed_op ? SHR_PPC : SHR_PC, RC_GR_WRITE); |
1526 | emith_move_r_imm(tmp, pc + (delayed_op ? 2 : 0)); |
1527 | emith_sh2_test_t(); |
1528 | EMITH_SJMP_START(jmp_cond); |
1529 | if (!delayed_op) |
1530 | offs += 2; |
1531 | if (offs < 0) { |
1532 | emith_sub_r_imm_c(insn_cond, tmp, -offs); |
1533 | } else |
1534 | emith_add_r_imm_c(insn_cond, tmp, offs); |
1535 | EMITH_SJMP_END(jmp_cond); |
e898de13 |
1536 | cycles += 2; |
1537 | if (!delayed_op) |
52d759c3 |
1538 | goto end_block_btf; |
e898de13 |
1539 | goto end_op; |
80599a42 |
1540 | }} |
679af8a3 |
1541 | goto default_; |
679af8a3 |
1542 | |
52d759c3 |
1543 | ///////////////////////////////////////////// |
1544 | case 0x09: |
1545 | // MOV.W @(disp,PC),Rn 1001nnnndddddddd |
f0d7b1fa |
1546 | rcache_clean(); |
1547 | tmp = rcache_get_tmp_arg(0); |
1548 | emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2); |
1549 | tmp = emit_memhandler_read(1); |
1550 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1551 | emith_sext(tmp2, tmp, 16); |
1552 | rcache_free_tmp(tmp); |
1553 | goto end_op; |
52d759c3 |
1554 | |
3863edbd |
1555 | ///////////////////////////////////////////// |
679af8a3 |
1556 | case 0x0a: |
1557 | // BRA label 1010dddddddddddd |
1558 | DELAYED_OP; |
1559 | do_bra: |
1560 | tmp = ((signed int)(op << 20) >> 19); |
e898de13 |
1561 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
679af8a3 |
1562 | cycles++; |
e898de13 |
1563 | break; |
679af8a3 |
1564 | |
3863edbd |
1565 | ///////////////////////////////////////////// |
679af8a3 |
1566 | case 0x0b: |
1567 | // BSR label 1011dddddddddddd |
1568 | DELAYED_OP; |
e898de13 |
1569 | emit_move_r_imm32(SHR_PR, pc + 2); |
679af8a3 |
1570 | goto do_bra; |
1571 | |
52d759c3 |
1572 | ///////////////////////////////////////////// |
1573 | case 0x0c: |
1574 | switch (op & 0x0f00) |
1575 | { |
1576 | case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd |
1577 | case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd |
1578 | case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd |
1579 | rcache_clean(); |
1580 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
1581 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
1582 | tmp3 = (op & 0x300) >> 8; |
1583 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
1584 | emit_memhandler_write(tmp3); |
1585 | goto end_op; |
1586 | case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd |
1587 | case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd |
1588 | case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd |
1589 | rcache_clean(); |
1590 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
1591 | tmp3 = (op & 0x300) >> 8; |
1592 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
1593 | tmp = emit_memhandler_read(tmp3); |
1594 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
1595 | if (tmp3 != 2) { |
1596 | emith_sext(tmp2, tmp, 8 << tmp3); |
1597 | } else |
1598 | emith_move_r_r(tmp2, tmp); |
1599 | rcache_free_tmp(tmp); |
1600 | goto end_op; |
1601 | case 0x0300: // TRAPA #imm 11000011iiiiiiii |
1602 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
1603 | emith_sub_r_imm(tmp, 4*2); |
1604 | rcache_clean(); |
1605 | // push SR |
1606 | tmp = rcache_get_reg_arg(0, SHR_SP); |
1607 | emith_add_r_imm(tmp, 4); |
1608 | tmp = rcache_get_reg_arg(1, SHR_SR); |
1609 | emith_clear_msb(tmp, tmp, 20); |
1610 | emit_memhandler_write(2); |
1611 | // push PC |
1612 | rcache_get_reg_arg(0, SHR_SP); |
1613 | tmp = rcache_get_tmp_arg(1); |
1614 | emith_move_r_imm(tmp, pc); |
1615 | emit_memhandler_write(2); |
1616 | // obtain new PC |
1617 | tmp = rcache_get_reg_arg(0, SHR_VBR); |
1618 | emith_add_r_imm(tmp, (op & 0xff) * 4); |
1619 | tmp = emit_memhandler_read(2); |
1620 | tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
1621 | emith_move_r_r(tmp2, tmp); |
1622 | rcache_free_tmp(tmp); |
1623 | cycles += 7; |
1624 | goto end_block_btf; |
1625 | case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd |
1626 | emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3); |
1627 | goto end_op; |
1628 | case 0x0800: // TST #imm,R0 11001000iiiiiiii |
1629 | tmp = rcache_get_reg(SHR_R0, RC_GR_READ); |
1630 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1631 | emith_bic_r_imm(tmp2, T); |
1632 | emith_tst_r_imm(tmp, op & 0xff); |
1633 | emit_or_t_if_eq(tmp2); |
1634 | goto end_op; |
1635 | case 0x0900: // AND #imm,R0 11001001iiiiiiii |
1636 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1637 | emith_and_r_imm(tmp, op & 0xff); |
1638 | goto end_op; |
1639 | case 0x0a00: // XOR #imm,R0 11001010iiiiiiii |
1640 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1641 | emith_eor_r_imm(tmp, op & 0xff); |
1642 | goto end_op; |
1643 | case 0x0b00: // OR #imm,R0 11001011iiiiiiii |
1644 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1645 | emith_or_r_imm(tmp, op & 0xff); |
1646 | goto end_op; |
1647 | case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii |
1648 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1649 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1650 | emith_bic_r_imm(tmp2, T); |
1651 | emith_tst_r_imm(tmp, op & 0xff); |
1652 | emit_or_t_if_eq(tmp2); |
1653 | rcache_free_tmp(tmp); |
1654 | cycles += 2; |
1655 | goto end_op; |
1656 | case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii |
1657 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1658 | emith_and_r_imm(tmp, op & 0xff); |
1659 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1660 | cycles += 2; |
1661 | goto end_op; |
1662 | case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii |
1663 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1664 | emith_eor_r_imm(tmp, op & 0xff); |
1665 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1666 | cycles += 2; |
1667 | goto end_op; |
1668 | case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii |
1669 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1670 | emith_or_r_imm(tmp, op & 0xff); |
1671 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1672 | cycles += 2; |
1673 | goto end_op; |
1674 | } |
1675 | goto default_; |
1676 | |
1677 | ///////////////////////////////////////////// |
1678 | case 0x0d: |
1679 | // MOV.L @(disp,PC),Rn 1101nnnndddddddd |
f0d7b1fa |
1680 | rcache_clean(); |
1681 | tmp = rcache_get_tmp_arg(0); |
1682 | emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3); |
1683 | tmp = emit_memhandler_read(2); |
1684 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1685 | emith_move_r_r(tmp2, tmp); |
1686 | rcache_free_tmp(tmp); |
1687 | goto end_op; |
52d759c3 |
1688 | |
1689 | ///////////////////////////////////////////// |
1690 | case 0x0e: |
1691 | // MOV #imm,Rn 1110nnnniiiiiiii |
1692 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1693 | emith_move_r_imm_s8(tmp, op & 0xff); |
1694 | goto end_op; |
1695 | |
679af8a3 |
1696 | default: |
1697 | default_: |
f0d7b1fa |
1698 | elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", |
1699 | sh2->is_slave ? 's' : 'm', op, pc - 2); |
1700 | #ifdef DRC_DEBUG_INTERP |
679af8a3 |
1701 | emit_move_r_imm32(SHR_PC, pc - 2); |
c18edb34 |
1702 | rcache_flush(); |
f4bb5d6b |
1703 | emith_pass_arg_r(0, CONTEXT_REG); |
1704 | emith_pass_arg_imm(1, op); |
679af8a3 |
1705 | emith_call(sh2_do_op); |
f0d7b1fa |
1706 | #endif |
679af8a3 |
1707 | break; |
1708 | } |
1709 | |
e898de13 |
1710 | end_op: |
6add7875 |
1711 | if (delayed_op == 1) |
e898de13 |
1712 | emit_move_r_r(SHR_PC, SHR_PPC); |
6add7875 |
1713 | |
e898de13 |
1714 | if (test_irq && delayed_op != 2) { |
f0d7b1fa |
1715 | if (!delayed_op) |
1716 | emit_move_r_imm32(SHR_PC, pc); |
c18edb34 |
1717 | rcache_flush(); |
f4bb5d6b |
1718 | emith_pass_arg_r(0, CONTEXT_REG); |
e898de13 |
1719 | emith_call(sh2_test_irq); |
f0d7b1fa |
1720 | goto end_block_btf; |
e898de13 |
1721 | } |
6add7875 |
1722 | if (delayed_op == 1) |
1723 | break; |
e898de13 |
1724 | |
f4bb5d6b |
1725 | do_host_disasm(tcache_id); |
679af8a3 |
1726 | } |
1727 | |
52d759c3 |
1728 | // delayed_op means some kind of branch - PC already handled |
1729 | if (!delayed_op) |
1730 | emit_move_r_imm32(SHR_PC, pc); |
1731 | |
1732 | end_block_btf: |
f4bb5d6b |
1733 | this_block->end_addr = pc; |
1734 | |
1735 | // mark memory blocks as containing compiled code |
1736 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
1737 | // data array, BIOS |
1738 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
1739 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
1740 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
1741 | Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; |
1742 | for (++tmp; tmp < tmp2; tmp++) { |
1743 | if (drcblk[tmp]) |
1744 | break; // dont overwrite overlay block |
1745 | drcblk[tmp] = blkid << 1; |
1746 | } |
1747 | } |
1748 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
1749 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
1750 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
1751 | Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; |
1752 | for (++tmp; tmp < tmp2; tmp++) { |
1753 | if (Pico32xMem->drcblk_ram[tmp]) |
1754 | break; |
1755 | Pico32xMem->drcblk_ram[tmp] = blkid << 1; |
1756 | } |
679af8a3 |
1757 | } |
1758 | |
c18edb34 |
1759 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1760 | emith_sub_r_imm(tmp, cycles << 12); |
1761 | rcache_flush(); |
679af8a3 |
1762 | emith_jump(sh2_drc_exit); |
f4bb5d6b |
1763 | tcache_ptrs[tcache_id] = tcache_ptr; |
1764 | |
553c3eaa |
1765 | #ifdef ARM |
1766 | cache_flush_d_inval_i(block_entry, tcache_ptr); |
1767 | #endif |
1768 | |
f4bb5d6b |
1769 | do_host_disasm(tcache_id); |
1770 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
1771 | tcache_id, block_counts[tcache_id], |
1772 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
1773 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
1774 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
1775 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
553c3eaa |
1776 | #if (DRC_DEBUG & 2) |
1777 | fflush(stdout); |
1778 | #endif |
1779 | |
679af8a3 |
1780 | return block_entry; |
f4bb5d6b |
1781 | /* |
679af8a3 |
1782 | unimplemented: |
1783 | // last op |
f4bb5d6b |
1784 | do_host_disasm(tcache_id); |
679af8a3 |
1785 | exit(1); |
f4bb5d6b |
1786 | */ |
679af8a3 |
1787 | } |
1788 | |
1789 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
1790 | { |
52d759c3 |
1791 | // TODO: need to handle self-caused interrupts |
1792 | sh2_test_irq(sh2); |
1793 | |
679af8a3 |
1794 | while (((signed int)sh2->sr >> 12) > 0) |
1795 | { |
679af8a3 |
1796 | void *block = NULL; |
f4bb5d6b |
1797 | block_desc *bd = NULL; |
6add7875 |
1798 | |
1799 | // FIXME: must avoid doing it so often.. |
52d759c3 |
1800 | //sh2_test_irq(sh2); |
6add7875 |
1801 | |
f4bb5d6b |
1802 | // we have full block id tables for data_array and RAM |
1803 | // BIOS goes to data_array table too |
1804 | if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
1805 | int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
1806 | if (blkid & 1) { |
1807 | bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; |
1808 | block = bd->tcache_ptr; |
1809 | } |
1810 | } |
1811 | // RAM |
1812 | else if ((sh2->pc & 0xc6000000) == 0x06000000) { |
1813 | int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
1814 | if (blkid & 1) { |
1815 | bd = &block_tables[0][blkid >> 1]; |
679af8a3 |
1816 | block = bd->tcache_ptr; |
f4bb5d6b |
1817 | } |
1818 | } |
1819 | // ROM |
1820 | else if ((sh2->pc & 0xc6000000) == 0x02000000) { |
1821 | bd = HASH_FUNC(hash_table, sh2->pc); |
1822 | |
1823 | if (bd != NULL) { |
1824 | if (bd->addr == sh2->pc) |
1825 | block = bd->tcache_ptr; |
1826 | else |
1827 | block = dr_find_block(bd, sh2->pc); |
1828 | } |
679af8a3 |
1829 | } |
1830 | |
1831 | if (block == NULL) |
1832 | block = sh2_translate(sh2, bd); |
1833 | |
f4bb5d6b |
1834 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
1835 | sh2->pc, block, (signed int)sh2->sr >> 12); |
1836 | #if (DRC_DEBUG & 1) |
1837 | if (bd != NULL) |
1838 | bd->refcount++; |
679af8a3 |
1839 | #endif |
1840 | sh2_drc_entry(sh2, block); |
1841 | } |
1842 | } |
1843 | |
f4bb5d6b |
1844 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
1845 | { |
1846 | u16 id = *p >> 1; |
1847 | block_desc *bd = btab + id; |
1848 | |
1849 | dbg(1, " killing block %08x", bd->addr); |
1850 | bd->addr = bd->end_addr = 0; |
1851 | |
1852 | while (p > drcblk && (p[-1] >> 1) == id) |
1853 | p--; |
1854 | |
1855 | // check for possible overlay block |
1856 | if (p > 0 && p[-1] != 0) { |
1857 | bd = btab + (p[-1] >> 1); |
1858 | if (bd->addr <= a && a < bd->end_addr) |
1859 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
1860 | } |
1861 | |
1862 | do { |
1863 | *p++ = 0; |
1864 | } |
1865 | while ((*p >> 1) == id); |
1866 | } |
1867 | |
1868 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
1869 | { |
1870 | u16 *drcblk = Pico32xMem->drcblk_ram; |
1871 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
1872 | |
1873 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
1874 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
1875 | } |
1876 | |
1877 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
1878 | { |
1879 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
1880 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
1881 | |
1882 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
1883 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
1884 | } |
1885 | |
52d759c3 |
1886 | void sh2_execute(SH2 *sh2c, int cycles) |
679af8a3 |
1887 | { |
52d759c3 |
1888 | sh2 = sh2c; // XXX |
1889 | |
1890 | sh2c->cycles_aim += cycles; |
1891 | cycles = sh2c->cycles_aim - sh2c->cycles_done; |
679af8a3 |
1892 | |
1893 | // cycles are kept in SHR_SR unused bits (upper 20) |
52d759c3 |
1894 | sh2c->sr &= 0x3f3; |
1895 | sh2c->sr |= cycles << 12; |
1896 | sh2_drc_dispatcher(sh2c); |
679af8a3 |
1897 | |
52d759c3 |
1898 | sh2c->cycles_done += cycles - ((signed int)sh2c->sr >> 12); |
679af8a3 |
1899 | } |
1900 | |
553c3eaa |
1901 | static void REGPARM(1) sh2_test_irq(SH2 *sh2) |
679af8a3 |
1902 | { |
6add7875 |
1903 | if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
1904 | { |
1905 | if (sh2->pending_irl > sh2->pending_int_irq) |
1906 | sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); |
1907 | else { |
1908 | sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
1909 | sh2->pending_int_irq = 0; // auto-clear |
1910 | sh2->pending_level = sh2->pending_irl; |
1911 | } |
1912 | } |
679af8a3 |
1913 | } |
1914 | |
f4bb5d6b |
1915 | #if (DRC_DEBUG & 1) |
1916 | static void block_stats(void) |
1917 | { |
1918 | int c, b, i, total = 0; |
1919 | |
1920 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
1921 | for (i = 0; i < block_counts[b]; i++) |
1922 | if (block_tables[b][i].addr != 0) |
1923 | total += block_tables[b][i].refcount; |
1924 | |
1925 | for (c = 0; c < 10; c++) { |
1926 | block_desc *blk, *maxb = NULL; |
1927 | int max = 0; |
1928 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
1929 | for (i = 0; i < block_counts[b]; i++) { |
1930 | blk = &block_tables[b][i]; |
1931 | if (blk->addr != 0 && blk->refcount > max) { |
1932 | max = blk->refcount; |
1933 | maxb = blk; |
1934 | } |
1935 | } |
1936 | } |
1937 | if (maxb == NULL) |
1938 | break; |
1939 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
1940 | (double)maxb->refcount / total * 100.0); |
1941 | maxb->refcount = 0; |
1942 | } |
553c3eaa |
1943 | |
1944 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
1945 | for (i = 0; i < block_counts[b]; i++) |
1946 | block_tables[b][i].refcount = 0; |
f4bb5d6b |
1947 | } |
553c3eaa |
1948 | #else |
1949 | #define block_stats() |
f4bb5d6b |
1950 | #endif |
1951 | |
553c3eaa |
1952 | void sh2_drc_flush_all(void) |
1953 | { |
1954 | block_stats(); |
1955 | flush_tcache(0); |
1956 | flush_tcache(1); |
1957 | flush_tcache(2); |
1958 | } |
1959 | |
679af8a3 |
1960 | int sh2_drc_init(SH2 *sh2) |
1961 | { |
f4bb5d6b |
1962 | if (block_tables[0] == NULL) { |
1963 | int i, cnt; |
7f5a3fc1 |
1964 | |
1965 | drc_cmn_init(); |
1966 | |
f4bb5d6b |
1967 | cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; |
1968 | block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); |
1969 | if (block_tables[0] == NULL) |
e898de13 |
1970 | return -1; |
1971 | |
f4bb5d6b |
1972 | memset(block_counts, 0, sizeof(block_counts)); |
1973 | tcache_bases[0] = tcache_ptrs[0] = tcache; |
1974 | |
1975 | for (i = 1; i < ARRAY_SIZE(block_tables); i++) { |
1976 | block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; |
1977 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
1978 | } |
1979 | |
553c3eaa |
1980 | // tmp |
1981 | PicoOpt |= POPT_DIS_VDP_FIFO; |
1982 | |
f4bb5d6b |
1983 | #if (DRC_DEBUG & 2) |
1984 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
1985 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
1986 | #endif |
e898de13 |
1987 | #if (DRC_DEBUG & 1) |
1988 | hash_collisions = 0; |
1989 | #endif |
679af8a3 |
1990 | } |
1991 | |
f4bb5d6b |
1992 | if (hash_table == NULL) { |
1993 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
1994 | if (hash_table == NULL) |
1995 | return -1; |
1996 | } |
41397701 |
1997 | |
679af8a3 |
1998 | return 0; |
41397701 |
1999 | } |
2000 | |
e898de13 |
2001 | void sh2_drc_finish(SH2 *sh2) |
2002 | { |
f4bb5d6b |
2003 | if (block_tables[0] != NULL) { |
f4bb5d6b |
2004 | block_stats(); |
f4bb5d6b |
2005 | free(block_tables[0]); |
2006 | memset(block_tables, 0, sizeof(block_tables)); |
7f5a3fc1 |
2007 | |
2008 | drc_cmn_cleanup(); |
e898de13 |
2009 | } |
2010 | |
f4bb5d6b |
2011 | if (hash_table != NULL) { |
2012 | free(hash_table); |
2013 | hash_table = NULL; |
2014 | } |
e898de13 |
2015 | } |