be2c4208 |
1 | #include "../pico_int.h" |
2 | #include "../memory.h" |
3 | |
4 | static const char str_mars[] = "MARS"; |
5 | |
974fdb5b |
6 | struct Pico32xMem *Pico32xMem; |
7 | |
5e49c3a8 |
8 | static void bank_switch(int b); |
9 | |
acd35d4c |
10 | #define MSB8(x) ((x) >> 8) |
11 | |
266c6afa |
12 | // poll detection |
4ea707e1 |
13 | #define POLL_THRESHOLD 6 |
14 | |
266c6afa |
15 | struct poll_det { |
b78efee2 |
16 | int addr, pc, cnt, flag; |
266c6afa |
17 | }; |
b78efee2 |
18 | static struct poll_det m68k_poll, sh2_poll[2]; |
266c6afa |
19 | |
b78efee2 |
20 | static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 pc, int is_vdp) |
266c6afa |
21 | { |
b78efee2 |
22 | int ret = 0, flag = pd->flag; |
23 | |
24 | if (is_vdp) |
25 | flag <<= 3; |
266c6afa |
26 | |
87accdf7 |
27 | if (a - 2 <= pd->addr && pd->addr <= a + 2) { // && pd->pc == pc) { |
266c6afa |
28 | pd->cnt++; |
29 | if (pd->cnt > POLL_THRESHOLD) { |
30 | if (!(Pico32x.emu_flags & flag)) { |
31 | elprintf(EL_32X, "%s poll addr %08x @ %06x", |
32 | flag == P32XF_68KPOLL ? "m68k" : (flag == P32XF_MSH2POLL ? "msh2" : "ssh2"), a, pc); |
33 | ret = 1; |
34 | } |
35 | Pico32x.emu_flags |= flag; |
36 | } |
37 | } |
38 | else |
39 | pd->cnt = 0; |
40 | pd->addr = a; |
41 | pd->pc = pc; |
42 | |
43 | return ret; |
44 | } |
45 | |
b78efee2 |
46 | static int p32x_poll_undetect(struct poll_det *pd, int is_vdp) |
266c6afa |
47 | { |
b78efee2 |
48 | int ret = 0, flag = pd->flag; |
49 | if (is_vdp) |
50 | flag <<= 3; |
266c6afa |
51 | if (pd->cnt > POLL_THRESHOLD) |
52 | ret = 1; |
53 | pd->addr = pd->cnt = 0; |
54 | Pico32x.emu_flags &= ~flag; |
55 | return ret; |
56 | } |
57 | |
87accdf7 |
58 | void p32x_poll_event(int cpu_mask, int is_vdp) |
4ea707e1 |
59 | { |
87accdf7 |
60 | if (cpu_mask & 1) |
61 | p32x_poll_undetect(&sh2_poll[0], is_vdp); |
62 | if (cpu_mask & 2) |
63 | p32x_poll_undetect(&sh2_poll[1], is_vdp); |
4ea707e1 |
64 | } |
65 | |
974fdb5b |
66 | // SH2 faking |
b78efee2 |
67 | //#define FAKE_SH2 |
acd35d4c |
68 | int p32x_csum_faked; |
69 | #ifdef FAKE_SH2 |
974fdb5b |
70 | static const u16 comm_fakevals[] = { |
71 | 0x4d5f, 0x4f4b, // M_OK |
72 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
73 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
74 | 0x5331, 0x4d31, // Darxide |
75 | 0x5332, 0x4d32, |
76 | 0x5333, 0x4d33, |
77 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
78 | 0x0002, // Mortal Kombat |
acd35d4c |
79 | // 0, // pad |
be2c4208 |
80 | }; |
acd35d4c |
81 | |
82 | static u32 sh2_comm_faker(u32 a) |
83 | { |
84 | static int f = 0; |
85 | if (a == 0x28 && !p32x_csum_faked) { |
86 | p32x_csum_faked = 1; |
87 | return *(unsigned short *)(Pico.rom + 0x18e); |
88 | } |
89 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
90 | f = 0; |
91 | return comm_fakevals[f++]; |
92 | } |
93 | #endif |
be2c4208 |
94 | |
4ea707e1 |
95 | // DMAC handling |
96 | static struct { |
97 | unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count |
98 | unsigned int chcr0; // chan ctl |
99 | unsigned int sar1, dar1, tcr1; // same for chan 1 |
100 | unsigned int chcr1; |
101 | int pad[4]; |
102 | unsigned int dmaor; |
103 | } * dmac0; |
104 | |
105 | static void dma_68k2sh2_do(void) |
106 | { |
107 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
108 | int i; |
109 | |
110 | if (dmac0->tcr0 != *dreqlen) |
111 | elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); |
112 | |
113 | for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { |
b78efee2 |
114 | extern void p32x_sh2_write16(u32 a, u32 d, int id); |
4ea707e1 |
115 | elprintf(EL_32X|EL_ANOMALY, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); |
b78efee2 |
116 | p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0); |
4ea707e1 |
117 | dmac0->dar0 += 2; |
118 | dmac0->tcr0--; |
119 | (*dreqlen)--; |
120 | } |
121 | |
122 | Pico32x.dmac_ptr = 0; // HACK |
123 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
124 | if (*dreqlen == 0) |
125 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
126 | if (dmac0->tcr0 == 0) |
127 | dmac0->chcr0 |= 2; // DMA has ended normally |
4ea707e1 |
128 | } |
129 | |
130 | // ------------------------------------------------------------------ |
b78efee2 |
131 | // 68k regs |
4ea707e1 |
132 | |
be2c4208 |
133 | static u32 p32x_reg_read16(u32 a) |
134 | { |
135 | a &= 0x3e; |
136 | |
87accdf7 |
137 | if (a == 2) // INTM, INTS |
138 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
3cf9570b |
139 | #if 0 |
974fdb5b |
140 | if ((a & 0x30) == 0x20) |
acd35d4c |
141 | return sh2_comm_faker(a); |
266c6afa |
142 | #else |
db1d3564 |
143 | if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekPc, 0)) { |
266c6afa |
144 | SekEndRun(16); |
145 | } |
acd35d4c |
146 | #endif |
87accdf7 |
147 | |
db1d3564 |
148 | if ((a & 0x30) == 0x30) |
149 | return p32x_pwm_read16(a); |
974fdb5b |
150 | |
be2c4208 |
151 | return Pico32x.regs[a / 2]; |
152 | } |
153 | |
be2c4208 |
154 | static void p32x_reg_write8(u32 a, u32 d) |
155 | { |
acd35d4c |
156 | u16 *r = Pico32x.regs; |
be2c4208 |
157 | a &= 0x3f; |
158 | |
97d3f47f |
159 | // for things like bset on comm port |
160 | m68k_poll.cnt = 0; |
161 | |
acd35d4c |
162 | if (a == 1 && !(r[0] & 1)) { |
163 | r[0] |= 1; |
be2c4208 |
164 | Pico32xStartup(); |
165 | return; |
166 | } |
5e49c3a8 |
167 | |
acd35d4c |
168 | if (!(r[0] & 1)) |
5e49c3a8 |
169 | return; |
170 | |
acd35d4c |
171 | switch (a) { |
4ea707e1 |
172 | case 0: // adapter ctl |
acd35d4c |
173 | r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); |
174 | break; |
4ea707e1 |
175 | case 3: // irq ctl |
176 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
177 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
178 | p32x_update_irls(); |
87accdf7 |
179 | SekEndRun(16); |
4ea707e1 |
180 | } |
b78efee2 |
181 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
182 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
183 | p32x_update_irls(); |
87accdf7 |
184 | SekEndRun(16); |
b78efee2 |
185 | } |
4ea707e1 |
186 | break; |
187 | case 5: // bank |
acd35d4c |
188 | d &= 7; |
4ea707e1 |
189 | if (r[4 / 2] != d) { |
190 | r[4 / 2] = d; |
acd35d4c |
191 | bank_switch(d); |
192 | } |
193 | break; |
4ea707e1 |
194 | case 7: // DREQ ctl |
97d3f47f |
195 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
4ea707e1 |
196 | break; |
87accdf7 |
197 | case 0x1b: // TV |
198 | r[0x1a / 2] = d; |
199 | break; |
5e49c3a8 |
200 | } |
201 | } |
202 | |
203 | static void p32x_reg_write16(u32 a, u32 d) |
204 | { |
acd35d4c |
205 | u16 *r = Pico32x.regs; |
206 | a &= 0x3e; |
207 | |
97d3f47f |
208 | // for things like bset on comm port |
209 | m68k_poll.cnt = 0; |
210 | |
acd35d4c |
211 | switch (a) { |
4ea707e1 |
212 | case 0x00: // adapter ctl |
acd35d4c |
213 | r[0] = (r[0] & 0x83) | (d & P32XS_FM); |
214 | return; |
4ea707e1 |
215 | case 0x10: // DREQ len |
216 | r[a / 2] = d & ~3; |
217 | return; |
218 | case 0x12: // FIFO reg |
219 | if (!(r[6 / 2] & P32XS_68S)) { |
220 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
221 | return; |
222 | } |
223 | if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) { |
224 | Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d; |
225 | if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) |
226 | dma_68k2sh2_do(); |
227 | if (Pico32x.dmac_ptr == DMAC_FIFO_LEN) |
228 | r[6 / 2] |= P32XS_FULL; |
229 | } |
230 | break; |
acd35d4c |
231 | } |
232 | |
4ea707e1 |
233 | // DREQ src, dst |
234 | if ((a & 0x38) == 0x08) { |
235 | r[a / 2] = d; |
236 | return; |
237 | } |
238 | // comm port |
239 | else if ((a & 0x30) == 0x20 && r[a / 2] != d) { |
acd35d4c |
240 | r[a / 2] = d; |
b78efee2 |
241 | if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0)) |
242 | // if some SH2 is busy waiting, it needs to see the result ASAP |
3cf9570b |
243 | SekEndRun(16); |
acd35d4c |
244 | return; |
245 | } |
db1d3564 |
246 | // PWM |
247 | else if ((a & 0x30) == 0x30) { |
248 | p32x_pwm_write16(a, d); |
249 | return; |
250 | } |
acd35d4c |
251 | |
5e49c3a8 |
252 | p32x_reg_write8(a + 1, d); |
be2c4208 |
253 | } |
254 | |
4ea707e1 |
255 | // ------------------------------------------------------------------ |
be2c4208 |
256 | // VDP regs |
257 | static u32 p32x_vdp_read16(u32 a) |
258 | { |
259 | a &= 0x0e; |
260 | |
261 | return Pico32x.vdp_regs[a / 2]; |
262 | } |
263 | |
be2c4208 |
264 | static void p32x_vdp_write8(u32 a, u32 d) |
265 | { |
974fdb5b |
266 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
267 | a &= 0x0f; |
268 | |
4ea707e1 |
269 | // for FEN checks between writes |
b78efee2 |
270 | sh2_poll[0].cnt = 0; |
4ea707e1 |
271 | |
974fdb5b |
272 | // TODO: verify what's writeable |
be2c4208 |
273 | switch (a) { |
974fdb5b |
274 | case 0x01: |
5e49c3a8 |
275 | // priority inversion is handled in palette |
276 | if ((r[0] ^ d) & P32XV_PRI) |
277 | Pico32x.dirty_pal = 1; |
974fdb5b |
278 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
279 | break; |
be2c4208 |
280 | case 0x0b: |
974fdb5b |
281 | d &= 1; |
282 | Pico32x.pending_fb = d; |
283 | // if we are blanking and FS bit is changing |
4ea707e1 |
284 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
974fdb5b |
285 | r[0x0a/2] ^= 1; |
286 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
287 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
288 | } |
289 | break; |
290 | } |
291 | } |
292 | |
974fdb5b |
293 | static void p32x_vdp_write16(u32 a, u32 d) |
294 | { |
295 | p32x_vdp_write8(a | 1, d); |
296 | } |
297 | |
4ea707e1 |
298 | // ------------------------------------------------------------------ |
acd35d4c |
299 | // SH2 regs |
b78efee2 |
300 | |
301 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
302 | { |
4ea707e1 |
303 | u16 *r = Pico32x.regs; |
304 | a &= 0xfe; // ? |
266c6afa |
305 | |
4ea707e1 |
306 | switch (a) { |
307 | case 0x00: // adapter/irq ctl |
87accdf7 |
308 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; |
309 | case 0x04: // H count |
310 | return Pico32x.sh2_regs[4 / 2]; |
4ea707e1 |
311 | case 0x10: // DREQ len |
312 | return r[a / 2]; |
acd35d4c |
313 | } |
4ea707e1 |
314 | |
db1d3564 |
315 | // DREQ src, dst |
316 | if ((a & 0x38) == 0x08) |
4ea707e1 |
317 | return r[a / 2]; |
db1d3564 |
318 | // comm port |
319 | if ((a & 0x30) == 0x20) { |
320 | if (p32x_poll_detect(&sh2_poll[cpuid], a, sh2_pc(cpuid), 0)) |
321 | ash2_end_run(8); |
322 | return r[a / 2]; |
323 | } |
324 | if ((a & 0x30) == 0x30) { |
325 | sh2_poll[cpuid].cnt = 0; |
326 | return p32x_pwm_read16(a); |
327 | } |
acd35d4c |
328 | |
329 | return 0; |
330 | } |
331 | |
b78efee2 |
332 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
333 | { |
4ea707e1 |
334 | a &= 0xff; |
87accdf7 |
335 | switch (a) { |
336 | case 0: // FM |
337 | Pico32x.regs[0] &= ~P32XS_FM; |
338 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
339 | break; |
340 | case 1: // |
341 | Pico32x.sh2irq_mask[cpuid] = d & 0x8f; |
342 | Pico32x.sh2_regs[0] &= ~0x80; |
343 | Pico32x.sh2_regs[0] |= d & 0x80; |
344 | p32x_update_irls(); |
345 | break; |
346 | case 5: // H count |
347 | Pico32x.sh2_regs[4 / 2] = d & 0xff; |
348 | break; |
4ea707e1 |
349 | } |
acd35d4c |
350 | } |
351 | |
b78efee2 |
352 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
353 | { |
4ea707e1 |
354 | a &= 0xfe; |
acd35d4c |
355 | |
db1d3564 |
356 | // comm |
4ea707e1 |
357 | if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) { |
b78efee2 |
358 | Pico32x.regs[a / 2] = d; |
359 | p32x_poll_undetect(&m68k_poll, 0); |
360 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
acd35d4c |
361 | return; |
362 | } |
db1d3564 |
363 | // PWM |
364 | else if ((a & 0x30) == 0x30) { |
365 | p32x_pwm_write16(a, d); |
366 | return; |
367 | } |
acd35d4c |
368 | |
4ea707e1 |
369 | switch (a) { |
87accdf7 |
370 | case 0: // FM |
371 | Pico32x.regs[0] &= ~P32XS_FM; |
372 | Pico32x.regs[0] |= d & P32XS_FM; |
373 | break; |
4ea707e1 |
374 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
375 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
376 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
377 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
4ea707e1 |
378 | case 0x1c: Pico32x.sh2irqs &= ~P32XI_PWM; goto irls; |
379 | } |
380 | |
b78efee2 |
381 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
382 | return; |
383 | |
384 | irls: |
385 | p32x_update_irls(); |
386 | } |
387 | |
87accdf7 |
388 | // ------------------------------------------------------------------ |
389 | // SH2 internal peripherals |
390 | static u32 sh2_peripheral_read8(u32 a, int id) |
391 | { |
392 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
393 | u32 d; |
394 | |
395 | a &= 0x1ff; |
396 | d = r[a]; |
397 | if (a == 4) |
398 | d = 0x84; // SCI SSR |
399 | |
400 | elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
401 | return d; |
402 | } |
403 | |
404 | static u32 sh2_peripheral_read32(u32 a, int id) |
4ea707e1 |
405 | { |
406 | u32 d; |
407 | a &= 0x1fc; |
97d3f47f |
408 | d = Pico32xMem->sh2_peri_regs[id][a / 4]; |
4ea707e1 |
409 | |
97d3f47f |
410 | elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
4ea707e1 |
411 | return d; |
acd35d4c |
412 | } |
413 | |
87accdf7 |
414 | static void sh2_peripheral_write8(u32 a, u32 d, int id) |
415 | { |
416 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
417 | elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
418 | |
419 | a &= 0x1ff; |
420 | r[a] = d; |
421 | } |
422 | |
423 | static void sh2_peripheral_write32(u32 a, u32 d, int id) |
4ea707e1 |
424 | { |
97d3f47f |
425 | unsigned int *r = Pico32xMem->sh2_peri_regs[id]; |
b78efee2 |
426 | elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
4ea707e1 |
427 | |
428 | a &= 0x1fc; |
429 | r[a / 4] = d; |
430 | |
97d3f47f |
431 | switch (a) { |
432 | // division unit: |
433 | case 0x104: // DVDNT: divident L, starts divide |
434 | elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); |
435 | if (r[0x100 / 4]) { |
436 | r[0x118 / 4] = r[0x110 / 4] = d % r[0x100 / 4]; |
437 | r[0x11c / 4] = r[0x114 / 4] = d / r[0x100 / 4]; |
438 | } |
439 | break; |
440 | case 0x114: |
441 | elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", |
442 | id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); |
443 | if (r[0x100 / 4]) { |
444 | long long divident = (long long)r[0x110 / 4] << 32 | d; |
445 | // XXX: undocumented mirroring to 0x118,0x11c? |
446 | r[0x118 / 4] = r[0x110 / 4] = divident % r[0x100 / 4]; |
447 | r[0x11c / 4] = r[0x114 / 4] = divident / r[0x100 / 4]; |
448 | } |
449 | break; |
450 | } |
451 | |
4ea707e1 |
452 | if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) { |
453 | elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x", |
b78efee2 |
454 | dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); |
4ea707e1 |
455 | dmac0->tcr0 &= 0xffffff; |
456 | // DREQ is only sent after first 4 words are written. |
457 | // we do multiple of 4 words to avoid messing up alignment |
458 | if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) { |
459 | elprintf(EL_32X, "68k -> sh2 DMA"); |
460 | dma_68k2sh2_do(); |
461 | } |
462 | } |
463 | } |
464 | |
465 | // ------------------------------------------------------------------ |
be2c4208 |
466 | // default 32x handlers |
467 | u32 PicoRead8_32x(u32 a) |
468 | { |
469 | u32 d = 0; |
470 | if ((a & 0xffc0) == 0x5100) { // a15100 |
471 | d = p32x_reg_read16(a); |
472 | goto out_16to8; |
473 | } |
474 | |
974fdb5b |
475 | if (!(Pico32x.regs[0] & 1)) |
476 | goto no_vdp; |
477 | |
478 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
479 | d = p32x_vdp_read16(a); |
480 | goto out_16to8; |
481 | } |
482 | |
974fdb5b |
483 | if ((a & 0xfe00) == 0x5200) { // a15200 |
484 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
485 | goto out_16to8; |
486 | } |
487 | |
488 | no_vdp: |
be2c4208 |
489 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
490 | d = str_mars[a & 3]; |
491 | goto out; |
492 | } |
493 | |
494 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
495 | return d; |
496 | |
497 | out_16to8: |
498 | if (a & 1) |
499 | d &= 0xff; |
500 | else |
501 | d >>= 8; |
502 | |
503 | out: |
504 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
505 | return d; |
506 | } |
507 | |
508 | u32 PicoRead16_32x(u32 a) |
509 | { |
510 | u32 d = 0; |
511 | if ((a & 0xffc0) == 0x5100) { // a15100 |
512 | d = p32x_reg_read16(a); |
513 | goto out; |
514 | } |
515 | |
974fdb5b |
516 | if (!(Pico32x.regs[0] & 1)) |
517 | goto no_vdp; |
518 | |
519 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
520 | d = p32x_vdp_read16(a); |
521 | goto out; |
522 | } |
523 | |
974fdb5b |
524 | if ((a & 0xfe00) == 0x5200) { // a15200 |
525 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
526 | goto out; |
527 | } |
528 | |
529 | no_vdp: |
be2c4208 |
530 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
531 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
532 | goto out; |
533 | } |
534 | |
535 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
536 | return d; |
537 | |
538 | out: |
539 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
540 | return d; |
541 | } |
542 | |
543 | void PicoWrite8_32x(u32 a, u32 d) |
544 | { |
545 | if ((a & 0xfc00) == 0x5000) |
546 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
547 | |
548 | if ((a & 0xffc0) == 0x5100) { // a15100 |
549 | p32x_reg_write8(a, d); |
550 | return; |
551 | } |
552 | |
974fdb5b |
553 | if (!(Pico32x.regs[0] & 1)) |
554 | goto no_vdp; |
555 | |
556 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
557 | p32x_vdp_write8(a, d); |
558 | return; |
559 | } |
560 | |
974fdb5b |
561 | // TODO: verify |
562 | if ((a & 0xfe00) == 0x5200) { // a15200 |
563 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
564 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
565 | Pico32x.dirty_pal = 1; |
566 | return; |
567 | } |
568 | |
569 | no_vdp: |
be2c4208 |
570 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
571 | } |
572 | |
573 | void PicoWrite16_32x(u32 a, u32 d) |
574 | { |
575 | if ((a & 0xfc00) == 0x5000) |
576 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
577 | |
578 | if ((a & 0xffc0) == 0x5100) { // a15100 |
579 | p32x_reg_write16(a, d); |
580 | return; |
581 | } |
582 | |
974fdb5b |
583 | if (!(Pico32x.regs[0] & 1)) |
584 | goto no_vdp; |
585 | |
586 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
587 | p32x_vdp_write16(a, d); |
588 | return; |
589 | } |
590 | |
974fdb5b |
591 | if ((a & 0xfe00) == 0x5200) { // a15200 |
592 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
593 | Pico32x.dirty_pal = 1; |
594 | return; |
595 | } |
596 | |
597 | no_vdp: |
be2c4208 |
598 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
599 | } |
600 | |
601 | // hint vector is writeable |
602 | static void PicoWrite8_hint(u32 a, u32 d) |
603 | { |
604 | if ((a & 0xfffc) == 0x0070) { |
605 | Pico32xMem->m68k_rom[a ^ 1] = d; |
606 | return; |
607 | } |
608 | |
609 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
610 | } |
611 | |
612 | static void PicoWrite16_hint(u32 a, u32 d) |
613 | { |
614 | if ((a & 0xfffc) == 0x0070) { |
615 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
616 | return; |
617 | } |
618 | |
619 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
620 | } |
621 | |
974fdb5b |
622 | void Pico32xSwapDRAM(int b) |
623 | { |
624 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
625 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
626 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
627 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
628 | } |
629 | |
5e49c3a8 |
630 | static void bank_switch(int b) |
631 | { |
632 | unsigned int rs, bank; |
633 | |
634 | bank = b << 20; |
635 | if (bank >= Pico.romsize) { |
636 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
637 | return; |
638 | } |
639 | |
640 | // 32X ROM (unbanked, XXX: consider mirroring?) |
641 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
642 | rs -= bank; |
643 | if (rs > 0x100000) |
644 | rs = 0x100000; |
645 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
646 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
647 | |
648 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
649 | } |
650 | |
acd35d4c |
651 | // ----------------------------------------------------------------- |
652 | // SH2 |
653 | // ----------------------------------------------------------------- |
654 | |
b78efee2 |
655 | u32 p32x_sh2_read8(u32 a, int id) |
acd35d4c |
656 | { |
657 | u32 d = 0; |
4ea707e1 |
658 | |
b78efee2 |
659 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
660 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
b78efee2 |
661 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
662 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
acd35d4c |
663 | |
87accdf7 |
664 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
665 | return Pico32xMem->sdram[(a & 0x3ffff) ^ 1]; |
666 | |
87accdf7 |
667 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
668 | if ((a & 0x003fffff) < Pico.romsize) |
669 | return Pico.rom[(a & 0x3fffff) ^ 1]; |
670 | |
b78efee2 |
671 | if ((a & ~0xfff) == 0xc0000000) |
672 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
673 | |
87accdf7 |
674 | if ((a & 0xdffe0000) == 0x04000000) { |
97d3f47f |
675 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
676 | return dram[(a & 0x1ffff) ^ 1]; |
677 | } |
678 | |
87accdf7 |
679 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
680 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
681 | goto out_16to8; |
acd35d4c |
682 | } |
683 | |
87accdf7 |
684 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
685 | d = p32x_vdp_read16(a); |
db1d3564 |
686 | if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1)) |
687 | ash2_end_run(8); |
688 | goto out_16to8; |
acd35d4c |
689 | } |
690 | |
87accdf7 |
691 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
692 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
693 | goto out_16to8; |
694 | } |
695 | |
87accdf7 |
696 | if ((a & 0xfffffe00) == 0xfffffe00) |
697 | return sh2_peripheral_read8(a, id); |
698 | |
b78efee2 |
699 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
700 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
701 | return d; |
702 | |
703 | out_16to8: |
704 | if (a & 1) |
705 | d &= 0xff; |
706 | else |
707 | d >>= 8; |
708 | |
b78efee2 |
709 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
710 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
711 | return d; |
712 | } |
713 | |
b78efee2 |
714 | u32 p32x_sh2_read16(u32 a, int id) |
acd35d4c |
715 | { |
716 | u32 d = 0; |
3cf9570b |
717 | |
b78efee2 |
718 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
719 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
b78efee2 |
720 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
721 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
acd35d4c |
722 | |
87accdf7 |
723 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
724 | return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2]; |
725 | |
87accdf7 |
726 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
727 | if ((a & 0x003fffff) < Pico.romsize) |
728 | return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2]; |
729 | |
b78efee2 |
730 | if ((a & ~0xfff) == 0xc0000000) |
731 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
732 | |
87accdf7 |
733 | if ((a & 0xdffe0000) == 0x04000000) |
97d3f47f |
734 | return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
735 | |
87accdf7 |
736 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
737 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
738 | goto out; |
acd35d4c |
739 | } |
740 | |
87accdf7 |
741 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
742 | d = p32x_vdp_read16(a); |
db1d3564 |
743 | if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1)) |
744 | ash2_end_run(8); |
745 | goto out; |
acd35d4c |
746 | } |
747 | |
87accdf7 |
748 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
749 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
750 | goto out; |
751 | } |
752 | |
b78efee2 |
753 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
754 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
755 | return d; |
756 | |
757 | out: |
b78efee2 |
758 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
759 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
760 | return d; |
761 | } |
762 | |
b78efee2 |
763 | u32 p32x_sh2_read32(u32 a, int id) |
acd35d4c |
764 | { |
4ea707e1 |
765 | if ((a & 0xfffffe00) == 0xfffffe00) |
87accdf7 |
766 | return sh2_peripheral_read32(a, id); |
4ea707e1 |
767 | |
acd35d4c |
768 | // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc()); |
b78efee2 |
769 | return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id); |
acd35d4c |
770 | } |
771 | |
b78efee2 |
772 | void p32x_sh2_write8(u32 a, u32 d, int id) |
acd35d4c |
773 | { |
87accdf7 |
774 | if ((a & 0xdffffc00) == 0x4000) |
b78efee2 |
775 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
776 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
777 | |
87accdf7 |
778 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
779 | Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d; |
780 | return; |
781 | } |
782 | |
87accdf7 |
783 | if ((a & 0xdffc0000) == 0x04000000) { |
784 | u8 *dram; |
785 | if (!(a & 0x20000) || d) { |
786 | dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
787 | dram[(a & 0x1ffff) ^ 1] = d; |
788 | return; |
789 | } |
266c6afa |
790 | } |
791 | |
b78efee2 |
792 | if ((a & ~0xfff) == 0xc0000000) { |
793 | Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; |
794 | return; |
795 | } |
796 | |
87accdf7 |
797 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
798 | p32x_vdp_write8(a, d); |
799 | return; |
800 | } |
801 | |
87accdf7 |
802 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
803 | p32x_sh2reg_write8(a, d, id); |
acd35d4c |
804 | return; |
805 | } |
806 | |
87accdf7 |
807 | if ((a & 0xfffffe00) == 0xfffffe00) { |
808 | sh2_peripheral_write8(a, d, id); |
809 | return; |
810 | } |
811 | |
b78efee2 |
812 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
813 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
814 | } |
815 | |
b78efee2 |
816 | void p32x_sh2_write16(u32 a, u32 d, int id) |
acd35d4c |
817 | { |
87accdf7 |
818 | if ((a & 0xdffffc00) == 0x4000) |
b78efee2 |
819 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
820 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
821 | |
87accdf7 |
822 | // ignore "Associative purge space" |
823 | if ((a & 0xf8000000) == 0x40000000) |
824 | return; |
825 | |
826 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
827 | ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d; |
828 | return; |
829 | } |
830 | |
b78efee2 |
831 | if ((a & ~0xfff) == 0xc0000000) { |
832 | ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; |
833 | return; |
834 | } |
835 | |
87accdf7 |
836 | if ((a & 0xdffc0000) == 0x04000000) { |
837 | u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
838 | if (!(a & 0x20000)) { |
839 | *pd = d; |
840 | return; |
841 | } |
842 | // overwrite |
843 | if (!(d & 0xff00)) d |= *pd & 0xff00; |
844 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; |
845 | *pd = d; |
266c6afa |
846 | return; |
847 | } |
848 | |
87accdf7 |
849 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
850 | p32x_vdp_write16(a, d); |
851 | return; |
852 | } |
853 | |
87accdf7 |
854 | if ((a & 0xdffffe00) == 0x4200) { |
acd35d4c |
855 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
856 | Pico32x.dirty_pal = 1; |
857 | return; |
858 | } |
859 | |
87accdf7 |
860 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
861 | p32x_sh2reg_write16(a, d, id); |
acd35d4c |
862 | return; |
863 | } |
864 | |
b78efee2 |
865 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
866 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
867 | } |
868 | |
b78efee2 |
869 | void p32x_sh2_write32(u32 a, u32 d, int id) |
acd35d4c |
870 | { |
4ea707e1 |
871 | if ((a & 0xfffffe00) == 0xfffffe00) { |
87accdf7 |
872 | sh2_peripheral_write32(a, d, id); |
4ea707e1 |
873 | return; |
874 | } |
875 | |
b78efee2 |
876 | p32x_sh2_write16(a, d >> 16, id); |
877 | p32x_sh2_write16(a + 2, d, id); |
acd35d4c |
878 | } |
879 | |
be2c4208 |
880 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
881 | void PicoMemSetup32x(void) |
882 | { |
883 | unsigned short *ps; |
884 | unsigned int *pl; |
5e49c3a8 |
885 | unsigned int rs; |
be2c4208 |
886 | int i; |
887 | |
888 | Pico32xMem = calloc(1, sizeof(*Pico32xMem)); |
889 | if (Pico32xMem == NULL) { |
890 | elprintf(EL_STATUS, "OOM"); |
891 | return; |
892 | } |
893 | |
4ea707e1 |
894 | dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; |
895 | |
be2c4208 |
896 | // generate 68k ROM |
897 | ps = (unsigned short *)Pico32xMem->m68k_rom; |
898 | pl = (unsigned int *)Pico32xMem->m68k_rom; |
899 | for (i = 1; i < 0xc0/4; i++) |
974fdb5b |
900 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
901 | |
902 | // fill with nops |
903 | for (i = 0xc0/2; i < 0x100/2; i++) |
904 | ps[i] = 0x4e71; |
905 | |
5e49c3a8 |
906 | #if 0 |
be2c4208 |
907 | ps[0xc0/2] = 0x46fc; |
908 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
909 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
910 | #else |
911 | ps[0xfe/2] = 0x4e75; // rts |
912 | #endif |
be2c4208 |
913 | |
914 | // fill remaining mem with ROM |
974fdb5b |
915 | memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100); |
be2c4208 |
916 | |
acd35d4c |
917 | // 32X ROM |
918 | // TODO: move |
919 | { |
920 | FILE *f = fopen("32X_M_BIOS.BIN", "rb"); |
921 | int i; |
922 | if (f == NULL) { |
b78efee2 |
923 | printf("missing 32X_M_BIOS.BIN\n"); |
acd35d4c |
924 | exit(1); |
925 | } |
926 | fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f); |
927 | fclose(f); |
b78efee2 |
928 | f = fopen("32X_S_BIOS.BIN", "rb"); |
929 | if (f == NULL) { |
930 | printf("missing 32X_S_BIOS.BIN\n"); |
931 | exit(1); |
932 | } |
933 | fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f); |
934 | fclose(f); |
935 | // byteswap |
acd35d4c |
936 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) { |
937 | int t = Pico32xMem->sh2_rom_m[i]; |
938 | Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1]; |
939 | Pico32xMem->sh2_rom_m[i + 1] = t; |
940 | } |
b78efee2 |
941 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) { |
942 | int t = Pico32xMem->sh2_rom_s[i]; |
943 | Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1]; |
944 | Pico32xMem->sh2_rom_s[i + 1] = t; |
945 | } |
acd35d4c |
946 | } |
947 | |
be2c4208 |
948 | // cartridge area becomes unmapped |
949 | // XXX: we take the easy way and don't unmap ROM, |
950 | // so that we can avoid handling the RV bit. |
951 | // m68k_map_unmap(0x000000, 0x3fffff); |
952 | |
953 | // MD ROM area |
974fdb5b |
954 | rs = sizeof(Pico32xMem->m68k_rom); |
955 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
956 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
957 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
958 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
959 | |
960 | // DRAM area |
961 | Pico32xSwapDRAM(1); |
be2c4208 |
962 | |
963 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
964 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
965 | if (rs > 0x80000) |
966 | rs = 0x80000; |
967 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
968 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
be2c4208 |
969 | |
970 | // 32X ROM (banked) |
5e49c3a8 |
971 | bank_switch(0); |
b78efee2 |
972 | |
973 | // setup poll detector |
974 | m68k_poll.flag = P32XF_68KPOLL; |
975 | sh2_poll[0].flag = P32XF_MSH2POLL; |
976 | sh2_poll[1].flag = P32XF_SSH2POLL; |
be2c4208 |
977 | } |
978 | |