[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "linkage_offsets.h"


#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define ndrc_patch_link		ESYM(ndrc_patch_link)
#define ndrc_get_addr_ht	ESYM(ndrc_get_addr_ht)
#define ndrc_get_addr_ht_param	ESYM(ndrc_get_addr_ht_param)
#define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
#define gen_interupt		ESYM(gen_interupt)
#define psxException		ESYM(psxException)
#define execI			ESYM(execI)
#endif

/* make mini_ht reachable with a single armv4 insn */
#if (LO_mini_ht & ~0xff0)
#error misligned mini_ht
#endif

	.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

@DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
@DRC_VAR(stop, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
@DRC_VAR(lo, 4)
@DRC_VAR(hi, 4)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
@DRC_VAR(code, 4)
@DRC_VAR(cycle, 4)
@DRC_VAR(interrupt, 4)
@DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
DRC_VAR(ram_offset, 4)
DRC_VAR(hash_table_ptr, 4)
DRC_VAR(mini_ht, 256)


	.syntax unified
	.text
	.align	2

#ifndef HAVE_ARMV5
.macro blx rd
	mov	lr, pc
	bx	\rd
.endm
#endif

.macro load_varadr reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(\var-(1678f+8))
	movt	\reg, #:upper16:(\var-(1678f+8))
1678:
	add	\reg, pc
#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	movw	\reg, #:lower16:\var
	movt	\reg, #:upper16:\var
#else
	ldr	\reg, =\var
#endif
.endm

.macro load_varadr_ext reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
1678:
	ldr	\reg, [pc, \reg]
#else
	load_varadr \reg \var
#endif
.endm

.macro mov_16 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #\imm
#else
	mov	\reg, #(\imm & 0x00ff)
	orr	\reg, #(\imm & 0xff00)
#endif
.endm

.macro mov_24 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #(\imm & 0xffff)
	movt	\reg, #(\imm >> 16)
#else
	mov	\reg, #(\imm & 0x0000ff)
	orr	\reg, #(\imm & 0x00ff00)
	orr	\reg, #(\imm & 0xff0000)
#endif
.endm

FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = pointer to an instruction to patch */
#if 1
	ldr	r7, [r1]
	mov	r4, r0
	add	r6, r7, #2
	mov	r5, r1
	lsl	r6, r6, #8
	/* must not compile - that might expire the caller block */
	ldr	r0, [fp, #LO_hash_table_ptr]
	mov	r1, r4
	mov	r2, #0 /* ndrc_compile_mode=ndrc_cm_no_compile */
	bl	ndrc_get_addr_ht_param

	movs	r8, r0
	beq	0f
	add	r6, r5, r6, asr #6  /* old target */
	teq	r0, r6
	bxeq	r0     /* Stale i-cache */
	mov	r0, r4
	mov	r1, r5
	mov	r2, r6
	mov	r3, r8
	bl	ndrc_patch_link
	bx	r8
0:
	mov	r0, r4
#endif
	ldr	r1, [fp, #LO_hash_table_ptr]
	bl	ndrc_get_addr_ht
	bx	r0
	.size	dyna_linker, .-dyna_linker

	.align	2
FUNCTION(jump_vaddr_r1):
	mov	r0, r1
	b	jump_vaddr_r0
	.size	jump_vaddr_r1, .-jump_vaddr_r1
FUNCTION(jump_vaddr_r2):
	mov	r0, r2
	b	jump_vaddr_r0
	.size	jump_vaddr_r2, .-jump_vaddr_r2
FUNCTION(jump_vaddr_r3):
	mov	r0, r3
	b	jump_vaddr_r0
	.size	jump_vaddr_r3, .-jump_vaddr_r3
FUNCTION(jump_vaddr_r4):
	mov	r0, r4
	b	jump_vaddr_r0
	.size	jump_vaddr_r4, .-jump_vaddr_r4
FUNCTION(jump_vaddr_r5):
	mov	r0, r5
	b	jump_vaddr_r0
	.size	jump_vaddr_r5, .-jump_vaddr_r5
FUNCTION(jump_vaddr_r6):
	mov	r0, r6
	b	jump_vaddr_r0
	.size	jump_vaddr_r6, .-jump_vaddr_r6
FUNCTION(jump_vaddr_r8):
	mov	r0, r8
	b	jump_vaddr_r0
	.size	jump_vaddr_r8, .-jump_vaddr_r8
FUNCTION(jump_vaddr_r9):
	mov	r0, r9
	b	jump_vaddr_r0
	.size	jump_vaddr_r9, .-jump_vaddr_r9
FUNCTION(jump_vaddr_r10):
	mov	r0, r10
	b	jump_vaddr_r0
	.size	jump_vaddr_r10, .-jump_vaddr_r10
FUNCTION(jump_vaddr_r12):
	mov	r0, r12
	b	jump_vaddr_r0
	.size	jump_vaddr_r12, .-jump_vaddr_r12
FUNCTION(jump_vaddr_r7):
	add	r0, r7, #0
	.size	jump_vaddr_r7, .-jump_vaddr_r7
FUNCTION(jump_vaddr_r0):
	ldr     r1, [fp, #LO_hash_table_ptr]
	bl	ndrc_get_addr_ht
	bx	r0
	.size	jump_vaddr_r0, .-jump_vaddr_r0

	.align	2
FUNCTION(cc_interrupt):
	ldr	r0, [fp, #LO_last_count]
	ldr	r9, [fp, #LO_pcaddr]
	add	r1, r0, r10
	str	r1, [fp, #LO_cycle]		/* PCSX cycles */
	mov	r10, lr

	add	r0, fp, #LO_reg_cop0            /* CP0 */
	bl	gen_interupt
	mov	lr, r10
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	ldr	r1, [fp, #LO_next_interupt]
	ldrb	r2, [fp, #LO_stop]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	tst	r2, r2
	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	cmp	r0, r9
	bxeq	lr
	ldr     r1, [fp, #LO_hash_table_ptr]
	bl	ndrc_get_addr_ht
	bx	r0
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(jump_addrerror_ds): /* R3000E_AdEL / R3000E_AdES in r0 */
	str	r1, [fp, #(LO_psxRegs + (34+8)*4)]  /* BadVaddr */
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_addrerror):
	str	r1, [fp, #(LO_psxRegs + (34+8)*4)]  /* BadVaddr */
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_overflow_ds):
	mov	r0, #(12<<2)  /* R3000E_Ov */
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_overflow):
	mov	r0, #(12<<2)
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_break_ds):
	mov	r0, #(9<<2)  /* R3000E_Bp */
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	r0, #(9<<2)
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	r0, #(8<<2)  /* R3000E_Syscall */
	mov	r1, #2
	b	call_psxException
FUNCTION(jump_syscall):
	mov	r0, #(8<<2)
	mov	r1, #0

call_psxException:
	ldr	r3, [fp, #LO_last_count]
	str	r2, [fp, #LO_pcaddr]
	add	r10, r3, r10
	str	r10, [fp, #LO_cycle]            /* PCSX cycles */
	add	r2, fp, #LO_reg_cop0            /* CP0 */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldrb	r2, [fp, #LO_stop]
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	tst	r2, r2
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	bne	new_dyna_leave
	ldr     r1, [fp, #LO_hash_table_ptr]
	bl	ndrc_get_addr_ht
	bx	r0
	.size	jump_to_new_pc, .-jump_to_new_pc

	.align	2
FUNCTION(new_dyna_leave):
	ldr	r0, [fp, #LO_last_count]
	add	r10, r0, r10
	str	r10, [fp, #LO_cycle]
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	.size	new_dyna_leave, .-new_dyna_leave

	.align	2
FUNCTION(invalidate_addr_r0):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	b	invalidate_addr_call
	.size	invalidate_addr_r0, .-invalidate_addr_r0
	.align	2
FUNCTION(invalidate_addr_r1):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r1
	b	invalidate_addr_call
	.size	invalidate_addr_r1, .-invalidate_addr_r1
	.align	2
FUNCTION(invalidate_addr_r2):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r2
	b	invalidate_addr_call
	.size	invalidate_addr_r2, .-invalidate_addr_r2
	.align	2
FUNCTION(invalidate_addr_r3):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r3
	b	invalidate_addr_call
	.size	invalidate_addr_r3, .-invalidate_addr_r3
	.align	2
FUNCTION(invalidate_addr_r4):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r4
	b	invalidate_addr_call
	.size	invalidate_addr_r4, .-invalidate_addr_r4
	.align	2
FUNCTION(invalidate_addr_r5):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r5
	b	invalidate_addr_call
	.size	invalidate_addr_r5, .-invalidate_addr_r5
	.align	2
FUNCTION(invalidate_addr_r6):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r6
	b	invalidate_addr_call
	.size	invalidate_addr_r6, .-invalidate_addr_r6
	.align	2
FUNCTION(invalidate_addr_r7):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r7
	b	invalidate_addr_call
	.size	invalidate_addr_r7, .-invalidate_addr_r7
	.align	2
FUNCTION(invalidate_addr_r8):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r8
	b	invalidate_addr_call
	.size	invalidate_addr_r8, .-invalidate_addr_r8
	.align	2
FUNCTION(invalidate_addr_r9):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r9
	b	invalidate_addr_call
	.size	invalidate_addr_r9, .-invalidate_addr_r9
	.align	2
FUNCTION(invalidate_addr_r10):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r10
	b	invalidate_addr_call
	.size	invalidate_addr_r10, .-invalidate_addr_r10
	.align	2
FUNCTION(invalidate_addr_r12):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r12
	.size	invalidate_addr_r12, .-invalidate_addr_r12
	.align	2
invalidate_addr_call:
	ldr	r12, [fp, #LO_inv_code_start]
	ldr	lr, [fp, #LO_inv_code_end]
	cmp	r0, r12
	cmpcs   lr, r0
	blcc	ndrc_write_invalidate_one
	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	.size	invalidate_addr_call, .-invalidate_addr_call

	.align	2
FUNCTION(new_dyna_start_at):
	/* ip is stored to conform EABI alignment */
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	mov     r0, r1
	b       new_dyna_start_at_e

FUNCTION(new_dyna_start):
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	ldr	r0, [fp, #LO_pcaddr]
	ldr     r1, [fp, #LO_hash_table_ptr]
	bl	ndrc_get_addr_ht
new_dyna_start_at_e:
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	bx	r0
	.size	new_dyna_start, .-new_dyna_start

/* --------------------------------------- */

.macro memhandler_post
	/* r2 = cycles_out, r3 = tmp */
	ldr	r3, [fp, #LO_next_interupt]
	ldr	r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
	str	r3, [fp, #LO_last_count]
	sub	r2, r2, r3
.endm

.align 2

.macro pcsx_read_mem_part readop tab_shift
	/* r0 = address, r1 = handler_tab, r2 = cycles */
	lsl	r3, r0, #20
	lsr	r3, #(20+\tab_shift)
	ldr	r12, [fp, #LO_last_count]
	ldr	r1, [r1, r3, lsl #2]
	add	r12, r2, r12
	lsls	r1, #1
.if \tab_shift == 1
	lsl	r3, #1
	\readop	r0, [r1, r3]
.else
	\readop	r0, [r1, r3, lsl #\tab_shift]
.endif
	bxcc	lr
	mov	r2, r12
	str	r12, [fp, #LO_cycle]
.endm

FUNCTION(jump_handler_read8):
	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_read_mem_part ldrbcc, 0
	bx	r1                           @ addr, unused, cycles

FUNCTION(jump_handler_read16):
	add     r1, #0x1000/4*4              @ shift to r16 part
	pcsx_read_mem_part ldrhcc, 1
	bx	r1                           @ addr, unused, cycles

FUNCTION(jump_handler_read32):
	pcsx_read_mem_part ldrcc, 2
	bx	r1                           @ addr, unused, cycles
#if 0
	str	lr, [fp, #LO_saved_lr]
	blx	r1
	ldr	lr, [fp, #LO_saved_lr]
	memhandler_post
	bx	lr
#endif

.macro pcsx_write_mem wrtop tab_shift
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	lsl	r12,r0, #20
	lsr	r12, #(20+\tab_shift)
	ldr	r3, [r3, r12, lsl #2]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	lsls	r3, #1
.if \tab_shift == 1
	lsl	r12, #1
	\wrtop	r1, [r3, r12]
.else
	\wrtop	r1, [r3, r12, lsl #\tab_shift]
.endif
	bxcc	lr
	ldr	r12, [fp, #LO_last_count]
	mov     r0, r1
	add	r2, r2, r12
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr
.endm

FUNCTION(jump_handler_write8):
	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_write_mem strbcc, 0

FUNCTION(jump_handler_write16):
	add     r3, #0x1000/4*4              @ shift to r16 part
	pcsx_write_mem strhcc, 1

FUNCTION(jump_handler_write32):
	pcsx_write_mem strcc, 2

FUNCTION(jump_handler_write_h):
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	ldr	r12, [fp, #LO_last_count]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	add	r2, r2, r12
	mov     r0, r1
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr

FUNCTION(jump_handle_swl):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	jump_handle_swx_interp
	add	r3, r0, r3
	mov	r0, r2
	tst	r3, #2
	beq	101f
	tst	r3, #1
	beq	2f
3:
	str	r1, [r3, #-3]
	bx	lr
2:
	lsr	r2, r1, #8
	lsr	r1, #24
	strh	r2, [r3, #-2]
	strb	r1, [r3]
	bx	lr
101:
	tst	r3, #1
	lsrne	r1, #16		@ 1
	lsreq	r12, r1, #24	@ 0
	strhne	r1, [r3, #-1]
	strbeq	r12, [r3]
	bx	lr

FUNCTION(jump_handle_swr):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	jump_handle_swx_interp
	add	r3, r0, r3
	and	r12,r3, #3
	mov	r0, r2
	cmp	r12,#2
	strbgt	r1, [r3]	@ 3
	strheq	r1, [r3]	@ 2
	cmp	r12,#1
	strlt	r1, [r3]	@ 0
	bxne	lr
	lsr	r2, r1, #8	@ 1
	strb	r1, [r3]
	strh	r2, [r3, #1]
	bx	lr

jump_handle_swx_interp: /* almost never happens */
	ldr	r3, [fp, #LO_last_count]
	add	r0, fp, #LO_psxRegs
	add	r2, r3, r2
	str	r2, [fp, #LO_cycle]           /* PCSX cycles */
	bl	execI
	b	jump_to_new_pc

.macro rcntx_read_mode0 num
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
	mov	r0, r2, lsl #16
	sub	r0, r0, r3, lsl #16
	lsr	r0, #16
	bx	lr
.endm

FUNCTION(rcnt0_read_count_m0):
	rcntx_read_mode0 0

FUNCTION(rcnt1_read_count_m0):
	rcntx_read_mode0 1

FUNCTION(rcnt2_read_count_m0):
	rcntx_read_mode0 2

FUNCTION(rcnt0_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
	mov_16	r1, 0x3334
	sub	r2, r2, r3
	mul	r0, r1, r2		@ /= 5
	lsr	r0, #16
	bx	lr

FUNCTION(rcnt1_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
	mov_24	r1, 0x1e6cde
	sub	r2, r2, r3
	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
	bx	lr

FUNCTION(rcnt2_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
	mov	r0, r2, lsl #16-3
	sub	r0, r0, r3, lsl #16-3
	lsr	r0, #16			@ /= 8
	bx	lr

#ifdef HAVE_ARMV6

FUNCTION(get_reg):
	ldr	r12, [r0]
	and	r1, r1, #0xff
	ldr	r2, [r0, #4]
	orr	r1, r1, r1, lsl #8
	ldr	r3, [r0, #8]
	orr	r1, r1, r1, lsl #16   @ searched char in every byte
	ldrb    r0, [r0, #12]         @ last byte
	eor	r12, r12, r1
	eor	r2, r2, r1
	eor	r3, r3, r1
	cmp     r0, r1, lsr #24
	mov	r0, #12
	mvn	r1, #0                @ r1=~0
	bxeq	lr
	orr	r3, r3, #0xff000000   @ EXCLUDE_REG
	uadd8	r0, r12, r1           @ add and set GE bits when not 0 (match)
	mov	r12, #0
	sel	r0, r12, r1           @ 0 if no match, else ff in some byte
	uadd8	r2, r2, r1
	sel	r2, r12, r1
	uadd8	r3, r3, r1
	sel	r3, r12, r1
	mov	r12, #3
	clz     r0, r0                @ 0, 8, 16, 24 or 32
	clz     r2, r2
	clz     r3, r3
	sub	r0, r12, r0, lsr #3   @ 3, 2, 1, 0 or -1
	sub	r2, r12, r2, lsr #3
	sub	r3, r12, r3, lsr #3
	orr	r2, r2, #4
	orr	r3, r3, #8
	and	r0, r0, r2
	and	r0, r0, r3
	bx	lr

#endif /* HAVE_ARMV6 */

@ vim:filetype=armasm
Commit	Line	Data
57871462	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
7e605697	2	* linkage_arm.s for PCSX *
0bbd1454	3	* Copyright (C) 2009-2011 Ari64 *
b1f89e6f	4	* Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas *
57871462	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
b021ee75	21
665f33e1	22	#include "arm_features.h"
d148d265	23	#include "new_dynarec_config.h"
b1f89e6f	24	#include "linkage_offsets.h"
	25
	26
	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
555d3b51	29	#define ndrc_patch_link ESYM(ndrc_patch_link)
104df9d3	30	#define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
104df9d3	31	#define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param)
9b495f6e	32	#define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
b1f89e6f	33	#define gen_interupt ESYM(gen_interupt)
d1150cd6	34	#define psxException ESYM(psxException)
c57af5e6	35	#define execI ESYM(execI)
22346d41	36	#endif
	37
	38	/* make mini_ht reachable with a single armv4 insn */
	39	#if (LO_mini_ht & ~0xff0)
	40	#error misligned mini_ht
b1f89e6f	41	#endif
f95a77f7	42
57871462	43	.bss
57871462	44	.align 4
b1f89e6f	45	.global dynarec_local
57871462	46	.type dynarec_local, %object
b1f89e6f	47	.size dynarec_local, LO_dynarec_local_size
57871462	48	dynarec_local:
b1f89e6f	49	.space LO_dynarec_local_size
	50
	51	#define DRC_VAR_(name, vname, size_) \
	52	vname = dynarec_local + LO_##name; \
	53	.global vname; \
	54	.type vname, %object; \
	55	.size vname, size_
	56
	57	#define DRC_VAR(name, size_) \
	58	DRC_VAR_(name, ESYM(name), size_)
	59
c87406ff	60	@DRC_VAR(next_interupt, 4)
b1f89e6f	61	DRC_VAR(cycle_count, 4)
b1f89e6f	62	DRC_VAR(last_count, 4)
c87406ff	63	@DRC_VAR(stop, 4)
b1f89e6f	64	DRC_VAR(address, 4)
7f94b097	65	DRC_VAR(hack_addr, 4)
b1f89e6f	66	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
f95a77f7	67
f95a77f7	68	/* psxRegs */
0b1633d7	69	@DRC_VAR(lo, 4)
0b1633d7	70	@DRC_VAR(hi, 4)
b1f89e6f	71	DRC_VAR(reg_cop2d, 128)
b1f89e6f	72	DRC_VAR(reg_cop2c, 128)
b1f89e6f	73	@DRC_VAR(code, 4)
	74	@DRC_VAR(cycle, 4)
	75	@DRC_VAR(interrupt, 4)
	76	@DRC_VAR(intCycle, 256)
	77
	78	DRC_VAR(rcnts, 744)
687b4580	79	DRC_VAR(inv_code_start, 4)
687b4580	80	DRC_VAR(inv_code_end, 4)
b1f89e6f	81	DRC_VAR(mem_rtab, 4)
	82	DRC_VAR(mem_wtab, 4)
	83	DRC_VAR(psxH_ptr, 4)
	84	DRC_VAR(zeromem_ptr, 4)
687b4580	85	DRC_VAR(invc_ptr, 4)
22346d41	86	DRC_VAR(scratch_buf_ptr, 4)
37387d8b	87	DRC_VAR(ram_offset, 4)
22346d41	88	DRC_VAR(hash_table_ptr, 4)
b1f89e6f	89	DRC_VAR(mini_ht, 256)
63cb0298	90
57871462	91
b861c0a9	92	.syntax unified
	93	.text
	94	.align 2
	95
665f33e1	96	#ifndef HAVE_ARMV5
	97	.macro blx rd
	98	mov lr, pc
	99	bx \rd
	100	.endm
	101	#endif
	102
c67af2ac	103	.macro load_varadr reg var
0e4ad319	104	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	105	movw \reg, #:lower16:(\var-(1678f+8))
1f4e070a	106	movt \reg, #:upper16:(\var-(1678f+8))
b861c0a9	107	1678:
b861c0a9	108	add \reg, pc
0e4ad319	109	#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	110	movw \reg, #:lower16:\var
	111	movt \reg, #:upper16:\var
c67af2ac	112	#else
274c4243	113	ldr \reg, =\var
c67af2ac	114	#endif
274c4243	115	.endm
274c4243	116
b861c0a9	117	.macro load_varadr_ext reg var
0e4ad319	118	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	119	movw \reg, #:lower16:(ptr_\var-(1678f+8))
1f4e070a	120	movt \reg, #:upper16:(ptr_\var-(1678f+8))
b861c0a9	121	1678:
	122	ldr \reg, [pc, \reg]
	123	#else
	124	load_varadr \reg \var
	125	#endif
	126	.endm
	127
b1be1eee	128	.macro mov_16 reg imm
8f2bb0cb	129	#ifdef HAVE_ARMV7
b1be1eee	130	movw \reg, #\imm
c67af2ac	131	#else
b1be1eee	132	mov \reg, #(\imm & 0x00ff)
b1be1eee	133	orr \reg, #(\imm & 0xff00)
c67af2ac	134	#endif
b1be1eee	135	.endm
	136
	137	.macro mov_24 reg imm
8f2bb0cb	138	#ifdef HAVE_ARMV7
b1be1eee	139	movw \reg, #(\imm & 0xffff)
b1be1eee	140	movt \reg, #(\imm >> 16)
c67af2ac	141	#else
b1be1eee	142	mov \reg, #(\imm & 0x0000ff)
	143	orr \reg, #(\imm & 0x00ff00)
	144	orr \reg, #(\imm & 0xff0000)
c67af2ac	145	#endif
b1be1eee	146	.endm
b1be1eee	147
104df9d3	148	FUNCTION(dyna_linker):
	149	/* r0 = virtual target address */
	150	/* r1 = pointer to an instruction to patch */
555d3b51	151	#if 1
104df9d3	152	ldr r7, [r1]
	153	mov r4, r0
	154	add r6, r7, #2
	155	mov r5, r1
	156	lsl r6, r6, #8
	157	/* must not compile - that might expire the caller block */
555d3b51	158	ldr r0, [fp, #LO_hash_table_ptr]
555d3b51	159	mov r1, r4
ea5c2d78	160	mov r2, #0 /* ndrc_compile_mode=ndrc_cm_no_compile */
104df9d3	161	bl ndrc_get_addr_ht_param
	162
	163	movs r8, r0
	164	beq 0f
	165	add r6, r5, r6, asr #6 /* old target */
398d6924	166	teq r0, r6
bbdd626a	167	bxeq r0 /* Stale i-cache */
398d6924	168	mov r0, r4
555d3b51	169	mov r1, r5
	170	mov r2, r6
	171	mov r3, r8
	172	bl ndrc_patch_link
bbdd626a	173	bx r8
104df9d3	174	0:
398d6924	175	mov r0, r4
d148d265	176	#endif
555d3b51	177	ldr r1, [fp, #LO_hash_table_ptr]
104df9d3	178	bl ndrc_get_addr_ht
bbdd626a	179	bx r0
4bdc30ab	180	.size dyna_linker, .-dyna_linker
7139f3c8	181
57871462	182	.align 2
5c6457c3	183	FUNCTION(jump_vaddr_r1):
57871462	184	mov r0, r1
104df9d3	185	b jump_vaddr_r0
57871462	186	.size jump_vaddr_r1, .-jump_vaddr_r1
5c6457c3	187	FUNCTION(jump_vaddr_r2):
57871462	188	mov r0, r2
104df9d3	189	b jump_vaddr_r0
57871462	190	.size jump_vaddr_r2, .-jump_vaddr_r2
5c6457c3	191	FUNCTION(jump_vaddr_r3):
57871462	192	mov r0, r3
104df9d3	193	b jump_vaddr_r0
57871462	194	.size jump_vaddr_r3, .-jump_vaddr_r3
5c6457c3	195	FUNCTION(jump_vaddr_r4):
57871462	196	mov r0, r4
104df9d3	197	b jump_vaddr_r0
57871462	198	.size jump_vaddr_r4, .-jump_vaddr_r4
5c6457c3	199	FUNCTION(jump_vaddr_r5):
57871462	200	mov r0, r5
104df9d3	201	b jump_vaddr_r0
57871462	202	.size jump_vaddr_r5, .-jump_vaddr_r5
5c6457c3	203	FUNCTION(jump_vaddr_r6):
57871462	204	mov r0, r6
104df9d3	205	b jump_vaddr_r0
57871462	206	.size jump_vaddr_r6, .-jump_vaddr_r6
5c6457c3	207	FUNCTION(jump_vaddr_r8):
57871462	208	mov r0, r8
104df9d3	209	b jump_vaddr_r0
57871462	210	.size jump_vaddr_r8, .-jump_vaddr_r8
5c6457c3	211	FUNCTION(jump_vaddr_r9):
57871462	212	mov r0, r9
104df9d3	213	b jump_vaddr_r0
57871462	214	.size jump_vaddr_r9, .-jump_vaddr_r9
5c6457c3	215	FUNCTION(jump_vaddr_r10):
57871462	216	mov r0, r10
104df9d3	217	b jump_vaddr_r0
57871462	218	.size jump_vaddr_r10, .-jump_vaddr_r10
5c6457c3	219	FUNCTION(jump_vaddr_r12):
57871462	220	mov r0, r12
104df9d3	221	b jump_vaddr_r0
57871462	222	.size jump_vaddr_r12, .-jump_vaddr_r12
5c6457c3	223	FUNCTION(jump_vaddr_r7):
57871462	224	add r0, r7, #0
57871462	225	.size jump_vaddr_r7, .-jump_vaddr_r7
104df9d3	226	FUNCTION(jump_vaddr_r0):
ea5c2d78	227	ldr r1, [fp, #LO_hash_table_ptr]
104df9d3	228	bl ndrc_get_addr_ht
bbdd626a	229	bx r0
104df9d3	230	.size jump_vaddr_r0, .-jump_vaddr_r0
7139f3c8	231
57871462	232	.align 2
5c6457c3	233	FUNCTION(cc_interrupt):
b1f89e6f	234	ldr r0, [fp, #LO_last_count]
e7172b26	235	ldr r9, [fp, #LO_pcaddr]
	236	add r1, r0, r10
	237	str r1, [fp, #LO_cycle] /* PCSX cycles */
57871462	238	mov r10, lr
398d6924	239
de6dbc52	240	add r0, fp, #LO_reg_cop0 /* CP0 */
57871462	241	bl gen_interupt
57871462	242	mov lr, r10
b1f89e6f	243	ldr r10, [fp, #LO_cycle]
e7172b26	244	ldr r0, [fp, #LO_pcaddr]
e7172b26	245	ldr r1, [fp, #LO_next_interupt]
bb17f8f4	246	ldrb r2, [fp, #LO_stop]
e7172b26	247	str r1, [fp, #LO_last_count]
e7172b26	248	sub r10, r10, r1
57871462	249	tst r2, r2
b861c0a9	250	ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
e7172b26	251	cmp r0, r9
bbdd626a	252	bxeq lr
ea5c2d78	253	ldr r1, [fp, #LO_hash_table_ptr]
104df9d3	254	bl ndrc_get_addr_ht
bbdd626a	255	bx r0
57871462	256	.size cc_interrupt, .-cc_interrupt
7139f3c8	257
57871462	258	.align 2
277718fa	259	FUNCTION(jump_addrerror_ds): /* R3000E_AdEL / R3000E_AdES in r0 */
	260	str r1, [fp, #(LO_psxRegs + (34+8)4)] / BadVaddr */
	261	mov r1, #1
	262	b call_psxException
	263	FUNCTION(jump_addrerror):
	264	str r1, [fp, #(LO_psxRegs + (34+8)4)] / BadVaddr */
	265	mov r1, #0
	266	b call_psxException
a5cd72d0	267	FUNCTION(jump_overflow_ds):
	268	mov r0, #(12<<2) /* R3000E_Ov */
	269	mov r1, #1
	270	b call_psxException
	271	FUNCTION(jump_overflow):
	272	mov r0, #(12<<2)
	273	mov r1, #0
	274	b call_psxException
d1150cd6	275	FUNCTION(jump_break_ds):
a5cd72d0	276	mov r0, #(9<<2) /* R3000E_Bp */
d1150cd6	277	mov r1, #1
	278	b call_psxException
	279	FUNCTION(jump_break):
a5cd72d0	280	mov r0, #(9<<2)
d1150cd6	281	mov r1, #0
	282	b call_psxException
	283	FUNCTION(jump_syscall_ds):
a5cd72d0	284	mov r0, #(8<<2) /* R3000E_Syscall */
bc7c5acb	285	mov r1, #2
d1150cd6	286	b call_psxException
5c6457c3	287	FUNCTION(jump_syscall):
a5cd72d0	288	mov r0, #(8<<2)
d1150cd6	289	mov r1, #0
	290
	291	call_psxException:
	292	ldr r3, [fp, #LO_last_count]
	293	str r2, [fp, #LO_pcaddr]
	294	add r10, r3, r10
6d75addf	295	str r10, [fp, #LO_cycle] /* PCSX cycles */
de6dbc52	296	add r2, fp, #LO_reg_cop0 /* CP0 */
d1150cd6	297	bl psxException
7139f3c8	298
b1f89e6f	299	/* note: psxException might do recursive recompiler call from it's HLE code,
7139f3c8	300	* so be ready for this */
3968e69e	301	FUNCTION(jump_to_new_pc):
bb17f8f4	302	ldrb r2, [fp, #LO_stop]
b1f89e6f	303	ldr r1, [fp, #LO_next_interupt]
	304	ldr r10, [fp, #LO_cycle]
	305	ldr r0, [fp, #LO_pcaddr]
dc4fa8bc	306	tst r2, r2
b1f89e6f	307	str r1, [fp, #LO_last_count]
dc4fa8bc	308	sub r10, r10, r1
dc4fa8bc	309	bne new_dyna_leave
ea5c2d78	310	ldr r1, [fp, #LO_hash_table_ptr]
104df9d3	311	bl ndrc_get_addr_ht
bbdd626a	312	bx r0
3968e69e	313	.size jump_to_new_pc, .-jump_to_new_pc
0d16cda2	314
7139f3c8	315	.align 2
5c6457c3	316	FUNCTION(new_dyna_leave):
b1f89e6f	317	ldr r0, [fp, #LO_last_count]
7139f3c8	318	add r10, r0, r10
b1f89e6f	319	str r10, [fp, #LO_cycle]
b021ee75	320	ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
7139f3c8	321	.size new_dyna_leave, .-new_dyna_leave
7139f3c8	322
0bbd1454	323	.align 2
5c6457c3	324	FUNCTION(invalidate_addr_r0):
5df0e313	325	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
0bbd1454	326	b invalidate_addr_call
	327	.size invalidate_addr_r0, .-invalidate_addr_r0
	328	.align 2
5c6457c3	329	FUNCTION(invalidate_addr_r1):
5df0e313	330	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	331	mov r0, r1
0bbd1454	332	b invalidate_addr_call
	333	.size invalidate_addr_r1, .-invalidate_addr_r1
	334	.align 2
5c6457c3	335	FUNCTION(invalidate_addr_r2):
5df0e313	336	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	337	mov r0, r2
0bbd1454	338	b invalidate_addr_call
	339	.size invalidate_addr_r2, .-invalidate_addr_r2
	340	.align 2
5c6457c3	341	FUNCTION(invalidate_addr_r3):
5df0e313	342	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	343	mov r0, r3
0bbd1454	344	b invalidate_addr_call
	345	.size invalidate_addr_r3, .-invalidate_addr_r3
	346	.align 2
5c6457c3	347	FUNCTION(invalidate_addr_r4):
5df0e313	348	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	349	mov r0, r4
0bbd1454	350	b invalidate_addr_call
	351	.size invalidate_addr_r4, .-invalidate_addr_r4
	352	.align 2
5c6457c3	353	FUNCTION(invalidate_addr_r5):
5df0e313	354	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	355	mov r0, r5
0bbd1454	356	b invalidate_addr_call
	357	.size invalidate_addr_r5, .-invalidate_addr_r5
	358	.align 2
5c6457c3	359	FUNCTION(invalidate_addr_r6):
5df0e313	360	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	361	mov r0, r6
0bbd1454	362	b invalidate_addr_call
	363	.size invalidate_addr_r6, .-invalidate_addr_r6
	364	.align 2
5c6457c3	365	FUNCTION(invalidate_addr_r7):
5df0e313	366	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	367	mov r0, r7
0bbd1454	368	b invalidate_addr_call
	369	.size invalidate_addr_r7, .-invalidate_addr_r7
	370	.align 2
5c6457c3	371	FUNCTION(invalidate_addr_r8):
5df0e313	372	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	373	mov r0, r8
0bbd1454	374	b invalidate_addr_call
	375	.size invalidate_addr_r8, .-invalidate_addr_r8
	376	.align 2
5c6457c3	377	FUNCTION(invalidate_addr_r9):
5df0e313	378	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	379	mov r0, r9
0bbd1454	380	b invalidate_addr_call
	381	.size invalidate_addr_r9, .-invalidate_addr_r9
	382	.align 2
5c6457c3	383	FUNCTION(invalidate_addr_r10):
5df0e313	384	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	385	mov r0, r10
0bbd1454	386	b invalidate_addr_call
	387	.size invalidate_addr_r10, .-invalidate_addr_r10
	388	.align 2
5c6457c3	389	FUNCTION(invalidate_addr_r12):
5df0e313	390	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	391	mov r0, r12
0bbd1454	392	.size invalidate_addr_r12, .-invalidate_addr_r12
0bbd1454	393	.align 2
b1f89e6f	394	invalidate_addr_call:
	395	ldr r12, [fp, #LO_inv_code_start]
	396	ldr lr, [fp, #LO_inv_code_end]
9be4ba64	397	cmp r0, r12
9be4ba64	398	cmpcs lr, r0
9b495f6e	399	blcc ndrc_write_invalidate_one
5df0e313	400	ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
0bbd1454	401	.size invalidate_addr_call, .-invalidate_addr_call
0bbd1454	402
57871462	403	.align 2
0b1633d7	404	FUNCTION(new_dyna_start_at):
b021ee75	405	/* ip is stored to conform EABI alignment */
0b1633d7	406	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	407	mov fp, r0 /* dynarec_local */
	408	mov r0, r1
	409	b new_dyna_start_at_e
	410
	411	FUNCTION(new_dyna_start):
b021ee75	412	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
be516ebe	413	mov fp, r0 /* dynarec_local */
b1f89e6f	414	ldr r0, [fp, #LO_pcaddr]
ea5c2d78	415	ldr r1, [fp, #LO_hash_table_ptr]
104df9d3	416	bl ndrc_get_addr_ht
0b1633d7	417	new_dyna_start_at_e:
b1f89e6f	418	ldr r1, [fp, #LO_next_interupt]
	419	ldr r10, [fp, #LO_cycle]
	420	str r1, [fp, #LO_last_count]
7139f3c8	421	sub r10, r10, r1
bbdd626a	422	bx r0
57871462	423	.size new_dyna_start, .-new_dyna_start
7139f3c8	424
7e605697	425	/* --------------------------------------- */
7139f3c8	426
7da5c7ad	427	.macro memhandler_post
	428	/* r2 = cycles_out, r3 = tmp */
	429	ldr r3, [fp, #LO_next_interupt]
	430	ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
	431	str r3, [fp, #LO_last_count]
	432	sub r2, r2, r3
	433	.endm
c6c3b1b3	434
7da5c7ad	435	.align 2
	436
	437	.macro pcsx_read_mem_part readop tab_shift
c6c3b1b3	438	/* r0 = address, r1 = handler_tab, r2 = cycles */
	439	lsl r3, r0, #20
	440	lsr r3, #(20+\tab_shift)
b1f89e6f	441	ldr r12, [fp, #LO_last_count]
c6c3b1b3	442	ldr r1, [r1, r3, lsl #2]
7da5c7ad	443	add r12, r2, r12
c6c3b1b3	444	lsls r1, #1
	445	.if \tab_shift == 1
	446	lsl r3, #1
	447	\readop r0, [r1, r3]
	448	.else
	449	\readop r0, [r1, r3, lsl #\tab_shift]
	450	.endif
bbdd626a	451	bxcc lr
7da5c7ad	452	mov r2, r12
7da5c7ad	453	str r12, [fp, #LO_cycle]
c6c3b1b3	454	.endm
c6c3b1b3	455
5c6457c3	456	FUNCTION(jump_handler_read8):
c6c3b1b3	457	add r1, #0x1000/44 + 0x1000/24 @ shift to r8 part
7da5c7ad	458	pcsx_read_mem_part ldrbcc, 0
7da5c7ad	459	bx r1 @ addr, unused, cycles
c6c3b1b3	460
5c6457c3	461	FUNCTION(jump_handler_read16):
c6c3b1b3	462	add r1, #0x1000/4*4 @ shift to r16 part
7da5c7ad	463	pcsx_read_mem_part ldrhcc, 1
7da5c7ad	464	bx r1 @ addr, unused, cycles
c6c3b1b3	465
5c6457c3	466	FUNCTION(jump_handler_read32):
7da5c7ad	467	pcsx_read_mem_part ldrcc, 2
	468	bx r1 @ addr, unused, cycles
	469	#if 0
	470	str lr, [fp, #LO_saved_lr]
	471	blx r1
	472	ldr lr, [fp, #LO_saved_lr]
	473	memhandler_post
	474	bx lr
	475	#endif
9b9af0d1	476
b96d3df7	477	.macro pcsx_write_mem wrtop tab_shift
	478	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	479	lsl r12,r0, #20
	480	lsr r12, #(20+\tab_shift)
	481	ldr r3, [r3, r12, lsl #2]
b1f89e6f	482	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	483	lsls r3, #1
b96d3df7	484	.if \tab_shift == 1
	485	lsl r12, #1
	486	\wrtop r1, [r3, r12]
	487	.else
	488	\wrtop r1, [r3, r12, lsl #\tab_shift]
	489	.endif
bbdd626a	490	bxcc lr
b1f89e6f	491	ldr r12, [fp, #LO_last_count]
b96d3df7	492	mov r0, r1
b96d3df7	493	add r2, r2, r12
b1f89e6f	494	str r2, [fp, #LO_cycle]
9b9af0d1	495
9b9af0d1	496	str lr, [fp, #LO_saved_lr]
b96d3df7	497	blx r3
9b9af0d1	498	ldr lr, [fp, #LO_saved_lr]
b96d3df7	499
9b9af0d1	500	memhandler_post
687b4580	501	bx lr
b96d3df7	502	.endm
b96d3df7	503
5c6457c3	504	FUNCTION(jump_handler_write8):
b96d3df7	505	add r3, #0x1000/44 + 0x1000/24 @ shift to r8 part
b861c0a9	506	pcsx_write_mem strbcc, 0
b96d3df7	507
5c6457c3	508	FUNCTION(jump_handler_write16):
b96d3df7	509	add r3, #0x1000/4*4 @ shift to r16 part
b861c0a9	510	pcsx_write_mem strhcc, 1
b96d3df7	511
5c6457c3	512	FUNCTION(jump_handler_write32):
b96d3df7	513	pcsx_write_mem strcc, 2
b96d3df7	514
5c6457c3	515	FUNCTION(jump_handler_write_h):
b96d3df7	516	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
b1f89e6f	517	ldr r12, [fp, #LO_last_count]
b1f89e6f	518	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	519	add r2, r2, r12
b96d3df7	520	mov r0, r1
b1f89e6f	521	str r2, [fp, #LO_cycle]
9b9af0d1	522
9b9af0d1	523	str lr, [fp, #LO_saved_lr]
b96d3df7	524	blx r3
9b9af0d1	525	ldr lr, [fp, #LO_saved_lr]
b96d3df7	526
9b9af0d1	527	memhandler_post
687b4580	528	bx lr
b96d3df7	529
5c6457c3	530	FUNCTION(jump_handle_swl):
b96d3df7	531	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	532	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	533	mov r12,r0,lsr #12
	534	ldr r3, [r3, r12, lsl #2]
	535	lsls r3, #1
de6dbc52	536	bcs jump_handle_swx_interp
b96d3df7	537	add r3, r0, r3
	538	mov r0, r2
	539	tst r3, #2
	540	beq 101f
	541	tst r3, #1
	542	beq 2f
	543	3:
	544	str r1, [r3, #-3]
	545	bx lr
	546	2:
	547	lsr r2, r1, #8
	548	lsr r1, #24
	549	strh r2, [r3, #-2]
	550	strb r1, [r3]
	551	bx lr
	552	101:
	553	tst r3, #1
	554	lsrne r1, #16 @ 1
	555	lsreq r12, r1, #24 @ 0
b861c0a9	556	strhne r1, [r3, #-1]
b861c0a9	557	strbeq r12, [r3]
b96d3df7	558	bx lr
b96d3df7	559
5c6457c3	560	FUNCTION(jump_handle_swr):
b96d3df7	561	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	562	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	563	mov r12,r0,lsr #12
	564	ldr r3, [r3, r12, lsl #2]
	565	lsls r3, #1
de6dbc52	566	bcs jump_handle_swx_interp
b96d3df7	567	add r3, r0, r3
	568	and r12,r3, #3
	569	mov r0, r2
	570	cmp r12,#2
b861c0a9	571	strbgt r1, [r3] @ 3
b861c0a9	572	strheq r1, [r3] @ 2
b96d3df7	573	cmp r12,#1
	574	strlt r1, [r3] @ 0
	575	bxne lr
	576	lsr r2, r1, #8 @ 1
	577	strb r1, [r3]
	578	strh r2, [r3, #1]
	579	bx lr
b96d3df7	580
de6dbc52	581	jump_handle_swx_interp: /* almost never happens */
	582	ldr r3, [fp, #LO_last_count]
	583	add r0, fp, #LO_psxRegs
	584	add r2, r3, r2
	585	str r2, [fp, #LO_cycle] /* PCSX cycles */
	586	bl execI
	587	b jump_to_new_pc
b96d3df7	588
b1be1eee	589	.macro rcntx_read_mode0 num
b1be1eee	590	/* r0 = address, r2 = cycles */
b1f89e6f	591	ldr r3, [fp, #LO_rcnts+64+74*\num] @ cycleStart
b1be1eee	592	mov r0, r2, lsl #16
b861c0a9	593	sub r0, r0, r3, lsl #16
b1be1eee	594	lsr r0, #16
	595	bx lr
	596	.endm
	597
5c6457c3	598	FUNCTION(rcnt0_read_count_m0):
b1be1eee	599	rcntx_read_mode0 0
b1be1eee	600
5c6457c3	601	FUNCTION(rcnt1_read_count_m0):
b1be1eee	602	rcntx_read_mode0 1
b1be1eee	603
5c6457c3	604	FUNCTION(rcnt2_read_count_m0):
b1be1eee	605	rcntx_read_mode0 2
b1be1eee	606
5c6457c3	607	FUNCTION(rcnt0_read_count_m1):
b1be1eee	608	/* r0 = address, r2 = cycles */
b1f89e6f	609	ldr r3, [fp, #LO_rcnts+64+74*0] @ cycleStart
b1be1eee	610	mov_16 r1, 0x3334
	611	sub r2, r2, r3
	612	mul r0, r1, r2 @ /= 5
	613	lsr r0, #16
	614	bx lr
	615
5c6457c3	616	FUNCTION(rcnt1_read_count_m1):
b1be1eee	617	/* r0 = address, r2 = cycles */
b1f89e6f	618	ldr r3, [fp, #LO_rcnts+64+74*1]
b1be1eee	619	mov_24 r1, 0x1e6cde
	620	sub r2, r2, r3
	621	umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
	622	bx lr
	623
5c6457c3	624	FUNCTION(rcnt2_read_count_m1):
b1be1eee	625	/* r0 = address, r2 = cycles */
b1f89e6f	626	ldr r3, [fp, #LO_rcnts+64+74*2]
b1be1eee	627	mov r0, r2, lsl #16-3
b861c0a9	628	sub r0, r0, r3, lsl #16-3
b1be1eee	629	lsr r0, #16 @ /= 8
	630	bx lr
	631
cdc2da64	632	#ifdef HAVE_ARMV6
	633
	634	FUNCTION(get_reg):
	635	ldr r12, [r0]
	636	and r1, r1, #0xff
	637	ldr r2, [r0, #4]
	638	orr r1, r1, r1, lsl #8
	639	ldr r3, [r0, #8]
	640	orr r1, r1, r1, lsl #16 @ searched char in every byte
	641	ldrb r0, [r0, #12] @ last byte
	642	eor r12, r12, r1
	643	eor r2, r2, r1
	644	eor r3, r3, r1
	645	cmp r0, r1, lsr #24
	646	mov r0, #12
	647	mvn r1, #0 @ r1=~0
	648	bxeq lr
	649	orr r3, r3, #0xff000000 @ EXCLUDE_REG
	650	uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
	651	mov r12, #0
	652	sel r0, r12, r1 @ 0 if no match, else ff in some byte
	653	uadd8 r2, r2, r1
	654	sel r2, r12, r1
	655	uadd8 r3, r3, r1
	656	sel r3, r12, r1
	657	mov r12, #3
	658	clz r0, r0 @ 0, 8, 16, 24 or 32
	659	clz r2, r2
	660	clz r3, r3
	661	sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
	662	sub r2, r12, r2, lsr #3
	663	sub r3, r12, r3, lsr #3
	664	orr r2, r2, #4
	665	orr r3, r3, #8
	666	and r0, r0, r2
	667	and r0, r0, r3
	668	bx lr
	669
	670	#endif /* HAVE_ARMV6 */
	671
7e605697	672	@ vim:filetype=armasm