7e605697 |
1 | /* |
274c4243 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
7e605697 |
3 | * |
4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
9 | #include "../psxhw.h" |
10 | #include "../cdrom.h" |
11 | #include "../mdec.h" |
ddbaf678 |
12 | #include "../gpu.h" |
87e5b45f |
13 | #include "../psxmem_map.h" |
7e605697 |
14 | #include "emu_if.h" |
15 | #include "pcsxmem.h" |
16 | |
5905989e |
17 | #ifdef __thumb__ |
9f704290 |
18 | #error the dynarec is incompatible with Thumb functions, |
19 | #error please add -marm to compile flags |
5905989e |
20 | #endif |
21 | |
7e605697 |
22 | //#define memprintf printf |
23 | #define memprintf(...) |
24 | |
b1be1eee |
25 | static u32 *mem_readtab; |
26 | static u32 *mem_writetab; |
27 | static u32 mem_iortab[(1+2+4) * 0x1000 / 4]; |
28 | static u32 mem_iowtab[(1+2+4) * 0x1000 / 4]; |
29 | static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
30 | //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
31 | static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
32 | |
578c6882 |
33 | // When this is called in a loop, and 'h' is a function pointer, clang will crash. |
34 | #ifdef __clang__ |
35 | static __attribute__ ((noinline)) void map_item(u32 *out, const void *h, u32 flag) |
36 | #else |
b1be1eee |
37 | static void map_item(u32 *out, const void *h, u32 flag) |
578c6882 |
38 | #endif |
b1be1eee |
39 | { |
40 | u32 hv = (u32)h; |
5905989e |
41 | if (hv & 1) { |
f29fbd53 |
42 | SysPrintf("FATAL: %p has LSB set\n", h); |
5905989e |
43 | abort(); |
44 | } |
b1be1eee |
45 | *out = (hv >> 1) | (flag << 31); |
46 | } |
47 | |
48 | // size must be power of 2, at least 4k |
49 | #define map_l1_mem(tab, i, addr, size, base) \ |
50 | map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0) |
51 | |
52 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
53 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
54 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
55 | |
054175e9 |
56 | u8 zero_mem[0x1000]; |
7a481d40 |
57 | |
63cb0298 |
58 | u32 read_mem_dummy() |
7e605697 |
59 | { |
63cb0298 |
60 | return 0; |
7e605697 |
61 | } |
62 | |
b96d3df7 |
63 | static void write_mem_dummy(u32 data) |
7e605697 |
64 | { |
b96d3df7 |
65 | memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle); |
7e605697 |
66 | } |
67 | |
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68 | /* IO handlers */ |
69 | static u32 io_read_sio16() |
70 | { |
71 | return sioRead8() | (sioRead8() << 8); |
72 | } |
73 | |
74 | static u32 io_read_sio32() |
75 | { |
76 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
77 | } |
78 | |
79 | static void io_write_sio16(u32 value) |
80 | { |
81 | sioWrite8((unsigned char)value); |
82 | sioWrite8((unsigned char)(value>>8)); |
83 | } |
84 | |
85 | static void io_write_sio32(u32 value) |
86 | { |
87 | sioWrite8((unsigned char)value); |
b96d3df7 |
88 | sioWrite8((unsigned char)(value >> 8)); |
89 | sioWrite8((unsigned char)(value >> 16)); |
90 | sioWrite8((unsigned char)(value >> 24)); |
7e605697 |
91 | } |
92 | |
19776aef |
93 | #ifndef DRC_DBG |
94 | |
b1be1eee |
95 | static void map_rcnt_rcount0(u32 mode) |
96 | { |
59fb0bb4 |
97 | if (mode & 0x100) { // pixel clock |
b1be1eee |
98 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); |
99 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); |
100 | } |
101 | else { |
102 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1); |
103 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1); |
104 | } |
105 | } |
106 | |
107 | static void map_rcnt_rcount1(u32 mode) |
108 | { |
59fb0bb4 |
109 | if (mode & 0x100) { // hcnt |
b1be1eee |
110 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); |
111 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); |
112 | } |
113 | else { |
114 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1); |
115 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1); |
116 | } |
117 | } |
118 | |
119 | static void map_rcnt_rcount2(u32 mode) |
120 | { |
121 | if (mode & 0x01) { // gate |
122 | map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); |
123 | map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); |
124 | } |
125 | else if (mode & 0x200) { // clk/8 |
126 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1); |
127 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1); |
128 | } |
129 | else { |
130 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1); |
131 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1); |
132 | } |
133 | } |
134 | |
19776aef |
135 | #else |
136 | #define map_rcnt_rcount0(mode) |
137 | #define map_rcnt_rcount1(mode) |
138 | #define map_rcnt_rcount2(mode) |
139 | #endif |
140 | |
7e605697 |
141 | #define make_rcnt_funcs(i) \ |
142 | static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ |
143 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
144 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
145 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
b1be1eee |
146 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \ |
7e605697 |
147 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
148 | |
149 | make_rcnt_funcs(0) |
150 | make_rcnt_funcs(1) |
151 | make_rcnt_funcs(2) |
152 | |
153 | static void io_write_ireg16(u32 value) |
154 | { |
9705788a |
155 | //if (Config.Sio) psxHu16ref(0x1070) |= 0x80; |
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156 | if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200; |
9705788a |
157 | psxHu16ref(0x1070) &= value; |
7e605697 |
158 | } |
159 | |
160 | static void io_write_imask16(u32 value) |
161 | { |
162 | psxHu16ref(0x1074) = value; |
163 | if (psxHu16ref(0x1070) & value) |
d28b54b1 |
164 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
7e605697 |
165 | } |
166 | |
167 | static void io_write_ireg32(u32 value) |
168 | { |
9705788a |
169 | //if (Config.Sio) psxHu32ref(0x1070) |= 0x80; |
7e605697 |
170 | if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200; |
9705788a |
171 | psxHu32ref(0x1070) &= value; |
7e605697 |
172 | } |
173 | |
174 | static void io_write_imask32(u32 value) |
175 | { |
176 | psxHu32ref(0x1074) = value; |
177 | if (psxHu32ref(0x1070) & value) |
d28b54b1 |
178 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
7e605697 |
179 | } |
180 | |
181 | static void io_write_dma_icr32(u32 value) |
182 | { |
1f77c863 |
183 | u32 tmp = value & 0x00ff803f; |
184 | tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; |
185 | if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) |
186 | || tmp & HW_DMA_ICR_BUS_ERROR) { |
187 | if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) |
188 | psxHu32ref(0x1070) |= SWAP32(8); |
189 | tmp |= HW_DMA_ICR_IRQ_SENT; |
190 | } |
191 | HW_DMA_ICR = SWAPu32(tmp); |
7e605697 |
192 | } |
193 | |
194 | #define make_dma_func(n) \ |
195 | static void io_write_chcr##n(u32 value) \ |
196 | { \ |
197 | HW_DMA##n##_CHCR = value; \ |
198 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
199 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
200 | } \ |
201 | } |
202 | |
203 | make_dma_func(0) |
204 | make_dma_func(1) |
205 | make_dma_func(2) |
206 | make_dma_func(3) |
207 | make_dma_func(4) |
208 | make_dma_func(6) |
209 | |
b96d3df7 |
210 | static void io_spu_write16(u32 value) |
211 | { |
212 | // meh |
650adfd2 |
213 | SPU_writeRegister(address, value, psxRegs.cycle); |
b96d3df7 |
214 | } |
215 | |
216 | static void io_spu_write32(u32 value) |
217 | { |
218 | SPUwriteRegister wfunc = SPU_writeRegister; |
219 | u32 a = address; |
220 | |
650adfd2 |
221 | wfunc(a, value & 0xffff, psxRegs.cycle); |
222 | wfunc(a + 2, value >> 16, psxRegs.cycle); |
b96d3df7 |
223 | } |
224 | |
ddbaf678 |
225 | static u32 io_gpu_read_status(void) |
226 | { |
0486fdc9 |
227 | u32 v; |
228 | |
ddbaf678 |
229 | // meh2, syncing for img bit, might want to avoid it.. |
230 | gpuSyncPluginSR(); |
0486fdc9 |
231 | v = HW_GPU_STATUS; |
232 | |
233 | // XXX: because of large timeslices can't use hSyncCount, using rough |
234 | // approximization instead. Perhaps better use hcounter code here or something. |
235 | if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) |
236 | v |= PSXGPU_LCF & (psxRegs.cycle << 20); |
237 | return v; |
ddbaf678 |
238 | } |
239 | |
240 | static void io_gpu_write_status(u32 value) |
241 | { |
242 | GPU_writeStatus(value); |
243 | gpuSyncPluginSR(); |
244 | } |
245 | |
b96d3df7 |
246 | static void map_ram_write(void) |
247 | { |
248 | int i; |
249 | |
250 | for (i = 0; i < (0x800000 >> 12); i++) { |
251 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
252 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
253 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
254 | } |
255 | } |
256 | |
257 | static void unmap_ram_write(void) |
258 | { |
259 | int i; |
260 | |
261 | for (i = 0; i < (0x800000 >> 12); i++) { |
262 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
263 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
264 | map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
265 | } |
266 | } |
267 | |
268 | static void write_biu(u32 value) |
269 | { |
270 | memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle); |
271 | |
272 | if (address != 0xfffe0130) |
273 | return; |
274 | |
275 | switch (value) { |
276 | case 0x800: case 0x804: |
277 | unmap_ram_write(); |
278 | break; |
279 | case 0: case 0x1e988: |
280 | map_ram_write(); |
281 | break; |
282 | default: |
283 | printf("write_biu: unexpected val: %08x\n", value); |
284 | break; |
285 | } |
286 | } |
287 | |
b1be1eee |
288 | void new_dyna_pcsx_mem_load_state(void) |
289 | { |
290 | map_rcnt_rcount0(rcnts[0].mode); |
291 | map_rcnt_rcount1(rcnts[1].mode); |
292 | map_rcnt_rcount2(rcnts[2].mode); |
293 | } |
294 | |
295 | int pcsxmem_is_handler_dynamic(u_int addr) |
296 | { |
297 | if ((addr & 0xfffff000) != 0x1f801000) |
298 | return 0; |
299 | |
300 | addr &= 0xffff; |
301 | return addr == 0x1100 || addr == 0x1110 || addr == 0x1120; |
302 | } |
303 | |
7e605697 |
304 | void new_dyna_pcsx_mem_init(void) |
305 | { |
306 | int i; |
63cb0298 |
307 | |
c6c3b1b3 |
308 | // have to map these further to keep tcache close to .text |
87e5b45f |
309 | mem_readtab = psxMap(0x08000000, 0x200000 * 4, 0, MAP_TAG_LUTS); |
310 | if (mem_readtab == NULL) { |
f29fbd53 |
311 | SysPrintf("failed to map mem tables\n"); |
c6c3b1b3 |
312 | exit(1); |
313 | } |
314 | mem_writetab = mem_readtab + 0x100000; |
315 | |
316 | // 1st level lookup: |
317 | // 0: direct mem |
318 | // 1: use 2nd lookup |
319 | // 2nd level lookup: |
320 | // 0: direct mem variable |
321 | // 1: memhandler |
322 | |
323 | // default/unmapped memhandlers |
324 | for (i = 0; i < 0x100000; i++) { |
325 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
054175e9 |
326 | map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem); |
c6c3b1b3 |
327 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
328 | } |
329 | |
330 | // RAM and it's mirrors |
331 | for (i = 0; i < (0x800000 >> 12); i++) { |
332 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
c6c3b1b3 |
333 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
c6c3b1b3 |
334 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
c6c3b1b3 |
335 | } |
b96d3df7 |
336 | map_ram_write(); |
c6c3b1b3 |
337 | |
338 | // BIOS and it's mirrors |
339 | for (i = 0; i < (0x80000 >> 12); i++) { |
340 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
341 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
342 | } |
343 | |
344 | // scratchpad |
345 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
346 | map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
347 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
348 | map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
349 | |
350 | // I/O |
351 | map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1); |
9dd7d179 |
352 | map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1); |
353 | map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1); |
c6c3b1b3 |
354 | map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1); |
9dd7d179 |
355 | map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1); |
356 | map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1); |
7e605697 |
357 | |
c6c3b1b3 |
358 | // L2 |
359 | // unmapped tables |
b96d3df7 |
360 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
c6c3b1b3 |
361 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
362 | |
363 | // fill IO tables |
364 | for (i = 0; i < 0x1000/4; i++) { |
365 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
366 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
367 | } |
368 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
369 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
370 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
371 | } |
372 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
373 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
374 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
375 | } |
376 | |
377 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
378 | map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1); |
379 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
380 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
381 | map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1); |
382 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
383 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
384 | map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1); |
385 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
386 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
387 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
ddbaf678 |
388 | map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1); |
c6c3b1b3 |
389 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
390 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
391 | |
392 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
393 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
394 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
395 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
396 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
397 | map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1); |
398 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
399 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
400 | map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1); |
401 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
402 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
403 | map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1); |
404 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
405 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
406 | |
407 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
408 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
409 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
410 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
411 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
412 | |
b96d3df7 |
413 | // write(u32 data) |
414 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
415 | map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1); |
416 | map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1); |
417 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
418 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
419 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
420 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
421 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
422 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
423 | map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1); |
424 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
425 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
426 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
427 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
428 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
429 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
430 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
431 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
432 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
433 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
ddbaf678 |
434 | map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1); |
b96d3df7 |
435 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
436 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
437 | |
438 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
439 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
440 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
441 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
442 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
443 | map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1); |
444 | map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1); |
445 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
446 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
447 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
448 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
449 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
450 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
451 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
452 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
453 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
454 | |
455 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
456 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
457 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
458 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
459 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
460 | |
461 | for (i = 0x1c00; i < 0x1e00; i += 2) { |
462 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
463 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
464 | } |
465 | |
466 | // misc |
467 | map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1); |
468 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) |
469 | map_item(&mem_ffwtab[i], write_biu, 1); |
470 | |
c6c3b1b3 |
471 | mem_rtab = mem_readtab; |
472 | mem_wtab = mem_writetab; |
b1be1eee |
473 | |
474 | new_dyna_pcsx_mem_load_state(); |
7e605697 |
475 | } |
476 | |
477 | void new_dyna_pcsx_mem_reset(void) |
478 | { |
c6c3b1b3 |
479 | int i; |
480 | |
7e605697 |
481 | // plugins might change so update the pointers |
c6c3b1b3 |
482 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
c6c3b1b3 |
483 | |
484 | for (i = 0x1c00; i < 0x1e00; i += 2) |
485 | map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); |
486 | |
b96d3df7 |
487 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
7e605697 |
488 | } |
92879b62 |
489 | |
490 | void new_dyna_pcsx_mem_shutdown(void) |
491 | { |
492 | psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS); |
493 | mem_writetab = mem_readtab = NULL; |
494 | } |