be2c4208 |
1 | #include "../pico_int.h" |
2 | #include "../memory.h" |
3 | |
c987bb5c |
4 | #if 1 |
5 | #undef ash2_end_run |
6 | #undef SekEndRun |
7 | #define ash2_end_run(x) |
8 | #define SekEndRun(x) |
9 | #endif |
10 | |
be2c4208 |
11 | static const char str_mars[] = "MARS"; |
12 | |
974fdb5b |
13 | struct Pico32xMem *Pico32xMem; |
14 | |
5e49c3a8 |
15 | static void bank_switch(int b); |
16 | |
266c6afa |
17 | // poll detection |
4ea707e1 |
18 | #define POLL_THRESHOLD 6 |
19 | |
266c6afa |
20 | struct poll_det { |
be20816c |
21 | u32 addr, cycles, cyc_max; |
22 | int cnt, flag; |
266c6afa |
23 | }; |
b78efee2 |
24 | static struct poll_det m68k_poll, sh2_poll[2]; |
266c6afa |
25 | |
be20816c |
26 | static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp) |
266c6afa |
27 | { |
b78efee2 |
28 | int ret = 0, flag = pd->flag; |
29 | |
30 | if (is_vdp) |
31 | flag <<= 3; |
266c6afa |
32 | |
be20816c |
33 | if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles < pd->cyc_max) { |
266c6afa |
34 | pd->cnt++; |
35 | if (pd->cnt > POLL_THRESHOLD) { |
36 | if (!(Pico32x.emu_flags & flag)) { |
be20816c |
37 | elprintf(EL_32X, "%s poll addr %08x, cyc %u", |
38 | flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" : |
39 | (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles); |
266c6afa |
40 | ret = 1; |
41 | } |
42 | Pico32x.emu_flags |= flag; |
43 | } |
44 | } |
c987bb5c |
45 | else { |
266c6afa |
46 | pd->cnt = 0; |
c987bb5c |
47 | pd->addr = a; |
48 | } |
be20816c |
49 | pd->cycles = cycles; |
266c6afa |
50 | |
51 | return ret; |
52 | } |
53 | |
b78efee2 |
54 | static int p32x_poll_undetect(struct poll_det *pd, int is_vdp) |
266c6afa |
55 | { |
b78efee2 |
56 | int ret = 0, flag = pd->flag; |
57 | if (is_vdp) |
be20816c |
58 | flag <<= 3; // VDP only |
59 | else |
60 | flag |= flag << 3; // both |
61 | if (Pico32x.emu_flags & flag) { |
62 | elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag); |
266c6afa |
63 | ret = 1; |
be20816c |
64 | } |
266c6afa |
65 | Pico32x.emu_flags &= ~flag; |
be20816c |
66 | pd->addr = pd->cnt = 0; |
266c6afa |
67 | return ret; |
68 | } |
69 | |
87accdf7 |
70 | void p32x_poll_event(int cpu_mask, int is_vdp) |
4ea707e1 |
71 | { |
87accdf7 |
72 | if (cpu_mask & 1) |
73 | p32x_poll_undetect(&sh2_poll[0], is_vdp); |
74 | if (cpu_mask & 2) |
75 | p32x_poll_undetect(&sh2_poll[1], is_vdp); |
4ea707e1 |
76 | } |
77 | |
974fdb5b |
78 | // SH2 faking |
b78efee2 |
79 | //#define FAKE_SH2 |
acd35d4c |
80 | int p32x_csum_faked; |
81 | #ifdef FAKE_SH2 |
974fdb5b |
82 | static const u16 comm_fakevals[] = { |
83 | 0x4d5f, 0x4f4b, // M_OK |
84 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
85 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
86 | 0x5331, 0x4d31, // Darxide |
87 | 0x5332, 0x4d32, |
88 | 0x5333, 0x4d33, |
89 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
90 | 0x0002, // Mortal Kombat |
acd35d4c |
91 | // 0, // pad |
be2c4208 |
92 | }; |
acd35d4c |
93 | |
94 | static u32 sh2_comm_faker(u32 a) |
95 | { |
96 | static int f = 0; |
97 | if (a == 0x28 && !p32x_csum_faked) { |
98 | p32x_csum_faked = 1; |
99 | return *(unsigned short *)(Pico.rom + 0x18e); |
100 | } |
101 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
102 | f = 0; |
103 | return comm_fakevals[f++]; |
104 | } |
105 | #endif |
be2c4208 |
106 | |
4ea707e1 |
107 | // DMAC handling |
108 | static struct { |
109 | unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count |
110 | unsigned int chcr0; // chan ctl |
111 | unsigned int sar1, dar1, tcr1; // same for chan 1 |
112 | unsigned int chcr1; |
113 | int pad[4]; |
114 | unsigned int dmaor; |
115 | } * dmac0; |
116 | |
117 | static void dma_68k2sh2_do(void) |
118 | { |
119 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
120 | int i; |
121 | |
122 | if (dmac0->tcr0 != *dreqlen) |
123 | elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); |
124 | |
1b3f5844 |
125 | // HACK: assume bus is busy and SH2 is halted |
126 | // XXX: use different mechanism for this, not poll det |
127 | Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL; |
128 | |
4ea707e1 |
129 | for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { |
b78efee2 |
130 | extern void p32x_sh2_write16(u32 a, u32 d, int id); |
be20816c |
131 | elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); |
b78efee2 |
132 | p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0); |
4ea707e1 |
133 | dmac0->dar0 += 2; |
134 | dmac0->tcr0--; |
135 | (*dreqlen)--; |
136 | } |
137 | |
138 | Pico32x.dmac_ptr = 0; // HACK |
139 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
140 | if (*dreqlen == 0) |
141 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
be20816c |
142 | if (dmac0->tcr0 == 0) { |
4ea707e1 |
143 | dmac0->chcr0 |= 2; // DMA has ended normally |
be20816c |
144 | p32x_poll_undetect(&sh2_poll[0], 0); |
145 | } |
4ea707e1 |
146 | } |
147 | |
148 | // ------------------------------------------------------------------ |
b78efee2 |
149 | // 68k regs |
4ea707e1 |
150 | |
be2c4208 |
151 | static u32 p32x_reg_read16(u32 a) |
152 | { |
153 | a &= 0x3e; |
154 | |
87accdf7 |
155 | if (a == 2) // INTM, INTS |
156 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
3cf9570b |
157 | #if 0 |
974fdb5b |
158 | if ((a & 0x30) == 0x20) |
acd35d4c |
159 | return sh2_comm_faker(a); |
266c6afa |
160 | #else |
be20816c |
161 | if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) { |
266c6afa |
162 | SekEndRun(16); |
163 | } |
acd35d4c |
164 | #endif |
87accdf7 |
165 | |
db1d3564 |
166 | if ((a & 0x30) == 0x30) |
167 | return p32x_pwm_read16(a); |
974fdb5b |
168 | |
be2c4208 |
169 | return Pico32x.regs[a / 2]; |
170 | } |
171 | |
be2c4208 |
172 | static void p32x_reg_write8(u32 a, u32 d) |
173 | { |
acd35d4c |
174 | u16 *r = Pico32x.regs; |
be2c4208 |
175 | a &= 0x3f; |
176 | |
97d3f47f |
177 | // for things like bset on comm port |
178 | m68k_poll.cnt = 0; |
179 | |
acd35d4c |
180 | if (a == 1 && !(r[0] & 1)) { |
181 | r[0] |= 1; |
be2c4208 |
182 | Pico32xStartup(); |
183 | return; |
184 | } |
5e49c3a8 |
185 | |
acd35d4c |
186 | if (!(r[0] & 1)) |
5e49c3a8 |
187 | return; |
188 | |
acd35d4c |
189 | switch (a) { |
4ea707e1 |
190 | case 0: // adapter ctl |
acd35d4c |
191 | r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); |
1b3f5844 |
192 | return; |
4ea707e1 |
193 | case 3: // irq ctl |
194 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
195 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
196 | p32x_update_irls(); |
87accdf7 |
197 | SekEndRun(16); |
4ea707e1 |
198 | } |
b78efee2 |
199 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
200 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
201 | p32x_update_irls(); |
87accdf7 |
202 | SekEndRun(16); |
b78efee2 |
203 | } |
1b3f5844 |
204 | return; |
4ea707e1 |
205 | case 5: // bank |
acd35d4c |
206 | d &= 7; |
4ea707e1 |
207 | if (r[4 / 2] != d) { |
208 | r[4 / 2] = d; |
acd35d4c |
209 | bank_switch(d); |
210 | } |
1b3f5844 |
211 | return; |
4ea707e1 |
212 | case 7: // DREQ ctl |
97d3f47f |
213 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
1b3f5844 |
214 | return; |
87accdf7 |
215 | case 0x1b: // TV |
216 | r[0x1a / 2] = d; |
1b3f5844 |
217 | return; |
218 | } |
219 | |
220 | if ((a & 0x30) == 0x20) { |
221 | u8 *r8 = (u8 *)r; |
222 | r8[a ^ 1] = d; |
223 | if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0)) |
224 | // if some SH2 is busy waiting, it needs to see the result ASAP |
225 | SekEndRun(16); |
226 | return; |
5e49c3a8 |
227 | } |
228 | } |
229 | |
230 | static void p32x_reg_write16(u32 a, u32 d) |
231 | { |
acd35d4c |
232 | u16 *r = Pico32x.regs; |
233 | a &= 0x3e; |
234 | |
97d3f47f |
235 | // for things like bset on comm port |
236 | m68k_poll.cnt = 0; |
237 | |
acd35d4c |
238 | switch (a) { |
4ea707e1 |
239 | case 0x00: // adapter ctl |
acd35d4c |
240 | r[0] = (r[0] & 0x83) | (d & P32XS_FM); |
241 | return; |
4ea707e1 |
242 | case 0x10: // DREQ len |
243 | r[a / 2] = d & ~3; |
244 | return; |
245 | case 0x12: // FIFO reg |
246 | if (!(r[6 / 2] & P32XS_68S)) { |
247 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
248 | return; |
249 | } |
250 | if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) { |
251 | Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d; |
252 | if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) |
253 | dma_68k2sh2_do(); |
254 | if (Pico32x.dmac_ptr == DMAC_FIFO_LEN) |
255 | r[6 / 2] |= P32XS_FULL; |
256 | } |
257 | break; |
acd35d4c |
258 | } |
259 | |
4ea707e1 |
260 | // DREQ src, dst |
261 | if ((a & 0x38) == 0x08) { |
262 | r[a / 2] = d; |
263 | return; |
264 | } |
265 | // comm port |
266 | else if ((a & 0x30) == 0x20 && r[a / 2] != d) { |
acd35d4c |
267 | r[a / 2] = d; |
b78efee2 |
268 | if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0)) |
269 | // if some SH2 is busy waiting, it needs to see the result ASAP |
3cf9570b |
270 | SekEndRun(16); |
acd35d4c |
271 | return; |
272 | } |
db1d3564 |
273 | // PWM |
274 | else if ((a & 0x30) == 0x30) { |
275 | p32x_pwm_write16(a, d); |
276 | return; |
277 | } |
acd35d4c |
278 | |
5e49c3a8 |
279 | p32x_reg_write8(a + 1, d); |
be2c4208 |
280 | } |
281 | |
4ea707e1 |
282 | // ------------------------------------------------------------------ |
be2c4208 |
283 | // VDP regs |
284 | static u32 p32x_vdp_read16(u32 a) |
285 | { |
286 | a &= 0x0e; |
287 | |
288 | return Pico32x.vdp_regs[a / 2]; |
289 | } |
290 | |
be2c4208 |
291 | static void p32x_vdp_write8(u32 a, u32 d) |
292 | { |
974fdb5b |
293 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
294 | a &= 0x0f; |
295 | |
4ea707e1 |
296 | // for FEN checks between writes |
b78efee2 |
297 | sh2_poll[0].cnt = 0; |
4ea707e1 |
298 | |
974fdb5b |
299 | // TODO: verify what's writeable |
be2c4208 |
300 | switch (a) { |
974fdb5b |
301 | case 0x01: |
5e49c3a8 |
302 | // priority inversion is handled in palette |
303 | if ((r[0] ^ d) & P32XV_PRI) |
304 | Pico32x.dirty_pal = 1; |
974fdb5b |
305 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
306 | if ((d & 3) == 3) |
307 | elprintf(EL_32X|EL_ANOMALY, "TODO: mode3"); |
308 | break; |
309 | case 0x05: // fill len |
310 | r[4 / 2] = d & 0xff; |
974fdb5b |
311 | break; |
be2c4208 |
312 | case 0x0b: |
974fdb5b |
313 | d &= 1; |
314 | Pico32x.pending_fb = d; |
315 | // if we are blanking and FS bit is changing |
4ea707e1 |
316 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
974fdb5b |
317 | r[0x0a/2] ^= 1; |
318 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
319 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
320 | } |
321 | break; |
322 | } |
323 | } |
324 | |
974fdb5b |
325 | static void p32x_vdp_write16(u32 a, u32 d) |
326 | { |
be20816c |
327 | a &= 0x0e; |
328 | if (a == 6) { // fill start |
329 | Pico32x.vdp_regs[6 / 2] = d; |
330 | return; |
331 | } |
332 | if (a == 8) { // fill data |
333 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
334 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
be20816c |
335 | a = Pico32x.vdp_regs[6 / 2]; |
336 | while (len--) { |
337 | dram[a] = d; |
338 | a = (a & 0xff00) | ((a + 1) & 0xff); |
339 | } |
340 | Pico32x.vdp_regs[6 / 2] = a; |
341 | Pico32x.vdp_regs[8 / 2] = d; |
342 | return; |
343 | } |
344 | |
974fdb5b |
345 | p32x_vdp_write8(a | 1, d); |
346 | } |
347 | |
4ea707e1 |
348 | // ------------------------------------------------------------------ |
acd35d4c |
349 | // SH2 regs |
b78efee2 |
350 | |
351 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
352 | { |
4ea707e1 |
353 | u16 *r = Pico32x.regs; |
354 | a &= 0xfe; // ? |
266c6afa |
355 | |
4ea707e1 |
356 | switch (a) { |
357 | case 0x00: // adapter/irq ctl |
87accdf7 |
358 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; |
c987bb5c |
359 | case 0x04: // H count (often as comm too) |
360 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
361 | ash2_end_run(8); |
87accdf7 |
362 | return Pico32x.sh2_regs[4 / 2]; |
4ea707e1 |
363 | case 0x10: // DREQ len |
364 | return r[a / 2]; |
acd35d4c |
365 | } |
4ea707e1 |
366 | |
db1d3564 |
367 | // DREQ src, dst |
368 | if ((a & 0x38) == 0x08) |
4ea707e1 |
369 | return r[a / 2]; |
db1d3564 |
370 | // comm port |
371 | if ((a & 0x30) == 0x20) { |
be20816c |
372 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
db1d3564 |
373 | ash2_end_run(8); |
374 | return r[a / 2]; |
375 | } |
376 | if ((a & 0x30) == 0x30) { |
377 | sh2_poll[cpuid].cnt = 0; |
378 | return p32x_pwm_read16(a); |
379 | } |
acd35d4c |
380 | |
381 | return 0; |
382 | } |
383 | |
b78efee2 |
384 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
385 | { |
4ea707e1 |
386 | a &= 0xff; |
87accdf7 |
387 | switch (a) { |
388 | case 0: // FM |
389 | Pico32x.regs[0] &= ~P32XS_FM; |
390 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
391 | return; |
87accdf7 |
392 | case 1: // |
393 | Pico32x.sh2irq_mask[cpuid] = d & 0x8f; |
394 | Pico32x.sh2_regs[0] &= ~0x80; |
395 | Pico32x.sh2_regs[0] |= d & 0x80; |
396 | p32x_update_irls(); |
1b3f5844 |
397 | return; |
87accdf7 |
398 | case 5: // H count |
399 | Pico32x.sh2_regs[4 / 2] = d & 0xff; |
c987bb5c |
400 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
1b3f5844 |
401 | return; |
402 | } |
403 | |
404 | if ((a & 0x30) == 0x20) { |
405 | u8 *r8 = (u8 *)Pico32x.regs; |
406 | r8[a ^ 1] = d; |
407 | p32x_poll_undetect(&m68k_poll, 0); |
408 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
409 | return; |
4ea707e1 |
410 | } |
acd35d4c |
411 | } |
412 | |
b78efee2 |
413 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
414 | { |
4ea707e1 |
415 | a &= 0xfe; |
acd35d4c |
416 | |
db1d3564 |
417 | // comm |
4ea707e1 |
418 | if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) { |
b78efee2 |
419 | Pico32x.regs[a / 2] = d; |
420 | p32x_poll_undetect(&m68k_poll, 0); |
421 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
acd35d4c |
422 | return; |
423 | } |
db1d3564 |
424 | // PWM |
425 | else if ((a & 0x30) == 0x30) { |
426 | p32x_pwm_write16(a, d); |
427 | return; |
428 | } |
acd35d4c |
429 | |
4ea707e1 |
430 | switch (a) { |
87accdf7 |
431 | case 0: // FM |
432 | Pico32x.regs[0] &= ~P32XS_FM; |
433 | Pico32x.regs[0] |= d & P32XS_FM; |
434 | break; |
4ea707e1 |
435 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
436 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
437 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
438 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
be20816c |
439 | case 0x1c: |
440 | Pico32x.sh2irqs &= ~P32XI_PWM; |
441 | p32x_pwm_irq_check(0); |
442 | goto irls; |
4ea707e1 |
443 | } |
444 | |
b78efee2 |
445 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
446 | return; |
447 | |
448 | irls: |
449 | p32x_update_irls(); |
450 | } |
451 | |
87accdf7 |
452 | // ------------------------------------------------------------------ |
453 | // SH2 internal peripherals |
454 | static u32 sh2_peripheral_read8(u32 a, int id) |
455 | { |
456 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
457 | u32 d; |
458 | |
459 | a &= 0x1ff; |
460 | d = r[a]; |
461 | if (a == 4) |
462 | d = 0x84; // SCI SSR |
463 | |
464 | elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
465 | return d; |
466 | } |
467 | |
468 | static u32 sh2_peripheral_read32(u32 a, int id) |
4ea707e1 |
469 | { |
470 | u32 d; |
471 | a &= 0x1fc; |
97d3f47f |
472 | d = Pico32xMem->sh2_peri_regs[id][a / 4]; |
4ea707e1 |
473 | |
97d3f47f |
474 | elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
4ea707e1 |
475 | return d; |
acd35d4c |
476 | } |
477 | |
87accdf7 |
478 | static void sh2_peripheral_write8(u32 a, u32 d, int id) |
479 | { |
480 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
481 | elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
482 | |
483 | a &= 0x1ff; |
484 | r[a] = d; |
485 | } |
486 | |
487 | static void sh2_peripheral_write32(u32 a, u32 d, int id) |
4ea707e1 |
488 | { |
be20816c |
489 | u32 *r = Pico32xMem->sh2_peri_regs[id]; |
b78efee2 |
490 | elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
4ea707e1 |
491 | |
492 | a &= 0x1fc; |
493 | r[a / 4] = d; |
494 | |
97d3f47f |
495 | switch (a) { |
be20816c |
496 | // division unit (TODO: verify): |
97d3f47f |
497 | case 0x104: // DVDNT: divident L, starts divide |
498 | elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); |
499 | if (r[0x100 / 4]) { |
be20816c |
500 | signed int divisor = r[0x100 / 4]; |
501 | r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; |
502 | r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; |
97d3f47f |
503 | } |
504 | break; |
505 | case 0x114: |
506 | elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", |
507 | id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); |
508 | if (r[0x100 / 4]) { |
be20816c |
509 | signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; |
510 | signed int divisor = r[0x100 / 4]; |
97d3f47f |
511 | // XXX: undocumented mirroring to 0x118,0x11c? |
be20816c |
512 | r[0x118 / 4] = r[0x110 / 4] = divident % divisor; |
513 | r[0x11c / 4] = r[0x114 / 4] = divident / divisor; |
97d3f47f |
514 | } |
515 | break; |
516 | } |
517 | |
4ea707e1 |
518 | if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) { |
519 | elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x", |
b78efee2 |
520 | dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); |
4ea707e1 |
521 | dmac0->tcr0 &= 0xffffff; |
be20816c |
522 | |
1b3f5844 |
523 | // HACK: assume 68k starts writing soon and end the timeslice |
524 | ash2_end_run(16); |
be20816c |
525 | |
4ea707e1 |
526 | // DREQ is only sent after first 4 words are written. |
527 | // we do multiple of 4 words to avoid messing up alignment |
528 | if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) { |
529 | elprintf(EL_32X, "68k -> sh2 DMA"); |
530 | dma_68k2sh2_do(); |
531 | } |
532 | } |
533 | } |
534 | |
535 | // ------------------------------------------------------------------ |
be2c4208 |
536 | // default 32x handlers |
537 | u32 PicoRead8_32x(u32 a) |
538 | { |
539 | u32 d = 0; |
540 | if ((a & 0xffc0) == 0x5100) { // a15100 |
541 | d = p32x_reg_read16(a); |
542 | goto out_16to8; |
543 | } |
544 | |
974fdb5b |
545 | if (!(Pico32x.regs[0] & 1)) |
546 | goto no_vdp; |
547 | |
548 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
549 | d = p32x_vdp_read16(a); |
550 | goto out_16to8; |
551 | } |
552 | |
974fdb5b |
553 | if ((a & 0xfe00) == 0x5200) { // a15200 |
554 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
555 | goto out_16to8; |
556 | } |
557 | |
558 | no_vdp: |
be2c4208 |
559 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
560 | d = str_mars[a & 3]; |
561 | goto out; |
562 | } |
563 | |
564 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
565 | return d; |
566 | |
567 | out_16to8: |
568 | if (a & 1) |
569 | d &= 0xff; |
570 | else |
571 | d >>= 8; |
572 | |
573 | out: |
574 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
575 | return d; |
576 | } |
577 | |
578 | u32 PicoRead16_32x(u32 a) |
579 | { |
580 | u32 d = 0; |
581 | if ((a & 0xffc0) == 0x5100) { // a15100 |
582 | d = p32x_reg_read16(a); |
583 | goto out; |
584 | } |
585 | |
974fdb5b |
586 | if (!(Pico32x.regs[0] & 1)) |
587 | goto no_vdp; |
588 | |
589 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
590 | d = p32x_vdp_read16(a); |
591 | goto out; |
592 | } |
593 | |
974fdb5b |
594 | if ((a & 0xfe00) == 0x5200) { // a15200 |
595 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
596 | goto out; |
597 | } |
598 | |
599 | no_vdp: |
be2c4208 |
600 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
601 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
602 | goto out; |
603 | } |
604 | |
605 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
606 | return d; |
607 | |
608 | out: |
609 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
610 | return d; |
611 | } |
612 | |
613 | void PicoWrite8_32x(u32 a, u32 d) |
614 | { |
615 | if ((a & 0xfc00) == 0x5000) |
616 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
617 | |
618 | if ((a & 0xffc0) == 0x5100) { // a15100 |
619 | p32x_reg_write8(a, d); |
620 | return; |
621 | } |
622 | |
974fdb5b |
623 | if (!(Pico32x.regs[0] & 1)) |
624 | goto no_vdp; |
625 | |
626 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
627 | p32x_vdp_write8(a, d); |
628 | return; |
629 | } |
630 | |
974fdb5b |
631 | // TODO: verify |
632 | if ((a & 0xfe00) == 0x5200) { // a15200 |
633 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
634 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
635 | Pico32x.dirty_pal = 1; |
636 | return; |
637 | } |
638 | |
639 | no_vdp: |
be2c4208 |
640 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
641 | } |
642 | |
643 | void PicoWrite16_32x(u32 a, u32 d) |
644 | { |
645 | if ((a & 0xfc00) == 0x5000) |
646 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
647 | |
648 | if ((a & 0xffc0) == 0x5100) { // a15100 |
649 | p32x_reg_write16(a, d); |
650 | return; |
651 | } |
652 | |
974fdb5b |
653 | if (!(Pico32x.regs[0] & 1)) |
654 | goto no_vdp; |
655 | |
656 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
657 | p32x_vdp_write16(a, d); |
658 | return; |
659 | } |
660 | |
974fdb5b |
661 | if ((a & 0xfe00) == 0x5200) { // a15200 |
662 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
663 | Pico32x.dirty_pal = 1; |
664 | return; |
665 | } |
666 | |
667 | no_vdp: |
be2c4208 |
668 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
669 | } |
670 | |
671 | // hint vector is writeable |
672 | static void PicoWrite8_hint(u32 a, u32 d) |
673 | { |
674 | if ((a & 0xfffc) == 0x0070) { |
675 | Pico32xMem->m68k_rom[a ^ 1] = d; |
676 | return; |
677 | } |
678 | |
679 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
680 | } |
681 | |
682 | static void PicoWrite16_hint(u32 a, u32 d) |
683 | { |
684 | if ((a & 0xfffc) == 0x0070) { |
685 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
686 | return; |
687 | } |
688 | |
689 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
690 | } |
691 | |
974fdb5b |
692 | void Pico32xSwapDRAM(int b) |
693 | { |
694 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
695 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
696 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
697 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
698 | } |
699 | |
5e49c3a8 |
700 | static void bank_switch(int b) |
701 | { |
702 | unsigned int rs, bank; |
703 | |
704 | bank = b << 20; |
705 | if (bank >= Pico.romsize) { |
706 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
707 | return; |
708 | } |
709 | |
710 | // 32X ROM (unbanked, XXX: consider mirroring?) |
711 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
712 | rs -= bank; |
713 | if (rs > 0x100000) |
714 | rs = 0x100000; |
715 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
716 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
717 | |
718 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
719 | } |
720 | |
acd35d4c |
721 | // ----------------------------------------------------------------- |
722 | // SH2 |
723 | // ----------------------------------------------------------------- |
724 | |
b78efee2 |
725 | u32 p32x_sh2_read8(u32 a, int id) |
acd35d4c |
726 | { |
727 | u32 d = 0; |
4ea707e1 |
728 | |
b78efee2 |
729 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
730 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
b78efee2 |
731 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
732 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
acd35d4c |
733 | |
87accdf7 |
734 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
735 | return Pico32xMem->sdram[(a & 0x3ffff) ^ 1]; |
736 | |
87accdf7 |
737 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
738 | if ((a & 0x003fffff) < Pico.romsize) |
739 | return Pico.rom[(a & 0x3fffff) ^ 1]; |
740 | |
b78efee2 |
741 | if ((a & ~0xfff) == 0xc0000000) |
742 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
743 | |
c987bb5c |
744 | if ((a & 0xdffc0000) == 0x04000000) { |
745 | /* XXX: overwrite readable as normal? */ |
97d3f47f |
746 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
747 | return dram[(a & 0x1ffff) ^ 1]; |
748 | } |
749 | |
87accdf7 |
750 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
751 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
752 | goto out_16to8; |
acd35d4c |
753 | } |
754 | |
87accdf7 |
755 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
756 | d = p32x_vdp_read16(a); |
be20816c |
757 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
758 | ash2_end_run(8); |
759 | goto out_16to8; |
acd35d4c |
760 | } |
761 | |
87accdf7 |
762 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
763 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
764 | goto out_16to8; |
765 | } |
766 | |
87accdf7 |
767 | if ((a & 0xfffffe00) == 0xfffffe00) |
768 | return sh2_peripheral_read8(a, id); |
769 | |
b78efee2 |
770 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
771 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
772 | return d; |
773 | |
774 | out_16to8: |
775 | if (a & 1) |
776 | d &= 0xff; |
777 | else |
778 | d >>= 8; |
779 | |
b78efee2 |
780 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
781 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
782 | return d; |
783 | } |
784 | |
b78efee2 |
785 | u32 p32x_sh2_read16(u32 a, int id) |
acd35d4c |
786 | { |
787 | u32 d = 0; |
3cf9570b |
788 | |
b78efee2 |
789 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
790 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
b78efee2 |
791 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
792 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
acd35d4c |
793 | |
87accdf7 |
794 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
795 | return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2]; |
796 | |
87accdf7 |
797 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
798 | if ((a & 0x003fffff) < Pico.romsize) |
799 | return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2]; |
800 | |
b78efee2 |
801 | if ((a & ~0xfff) == 0xc0000000) |
802 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
803 | |
87accdf7 |
804 | if ((a & 0xdffe0000) == 0x04000000) |
97d3f47f |
805 | return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
806 | |
87accdf7 |
807 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
808 | d = p32x_sh2reg_read16(a, id); |
1b3f5844 |
809 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
810 | return d; |
db1d3564 |
811 | goto out; |
acd35d4c |
812 | } |
813 | |
87accdf7 |
814 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
815 | d = p32x_vdp_read16(a); |
be20816c |
816 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
817 | ash2_end_run(8); |
818 | goto out; |
acd35d4c |
819 | } |
820 | |
87accdf7 |
821 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
822 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
823 | goto out; |
824 | } |
825 | |
b78efee2 |
826 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
827 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
828 | return d; |
829 | |
830 | out: |
b78efee2 |
831 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
832 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
833 | return d; |
834 | } |
835 | |
b78efee2 |
836 | u32 p32x_sh2_read32(u32 a, int id) |
acd35d4c |
837 | { |
4ea707e1 |
838 | if ((a & 0xfffffe00) == 0xfffffe00) |
87accdf7 |
839 | return sh2_peripheral_read32(a, id); |
4ea707e1 |
840 | |
acd35d4c |
841 | // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc()); |
b78efee2 |
842 | return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id); |
acd35d4c |
843 | } |
844 | |
b78efee2 |
845 | void p32x_sh2_write8(u32 a, u32 d, int id) |
acd35d4c |
846 | { |
87accdf7 |
847 | if ((a & 0xdffffc00) == 0x4000) |
b78efee2 |
848 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
849 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
850 | |
87accdf7 |
851 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
852 | Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d; |
853 | return; |
854 | } |
855 | |
87accdf7 |
856 | if ((a & 0xdffc0000) == 0x04000000) { |
857 | u8 *dram; |
858 | if (!(a & 0x20000) || d) { |
859 | dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
860 | dram[(a & 0x1ffff) ^ 1] = d; |
87accdf7 |
861 | } |
c987bb5c |
862 | return; |
266c6afa |
863 | } |
864 | |
b78efee2 |
865 | if ((a & ~0xfff) == 0xc0000000) { |
866 | Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; |
867 | return; |
868 | } |
869 | |
87accdf7 |
870 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
871 | p32x_vdp_write8(a, d); |
872 | return; |
873 | } |
874 | |
87accdf7 |
875 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
876 | p32x_sh2reg_write8(a, d, id); |
acd35d4c |
877 | return; |
878 | } |
879 | |
87accdf7 |
880 | if ((a & 0xfffffe00) == 0xfffffe00) { |
881 | sh2_peripheral_write8(a, d, id); |
882 | return; |
883 | } |
884 | |
b78efee2 |
885 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
886 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
887 | } |
888 | |
b78efee2 |
889 | void p32x_sh2_write16(u32 a, u32 d, int id) |
acd35d4c |
890 | { |
1b3f5844 |
891 | if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
b78efee2 |
892 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
893 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
894 | |
87accdf7 |
895 | // ignore "Associative purge space" |
896 | if ((a & 0xf8000000) == 0x40000000) |
897 | return; |
898 | |
899 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
900 | ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d; |
901 | return; |
902 | } |
903 | |
b78efee2 |
904 | if ((a & ~0xfff) == 0xc0000000) { |
905 | ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; |
906 | return; |
907 | } |
908 | |
87accdf7 |
909 | if ((a & 0xdffc0000) == 0x04000000) { |
910 | u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
911 | if (!(a & 0x20000)) { |
912 | *pd = d; |
913 | return; |
914 | } |
915 | // overwrite |
916 | if (!(d & 0xff00)) d |= *pd & 0xff00; |
917 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; |
918 | *pd = d; |
266c6afa |
919 | return; |
920 | } |
921 | |
87accdf7 |
922 | if ((a & 0xdfffff00) == 0x4100) { |
be20816c |
923 | sh2_poll[id].cnt = 0; // for poll before VDP accesses |
acd35d4c |
924 | p32x_vdp_write16(a, d); |
925 | return; |
926 | } |
927 | |
87accdf7 |
928 | if ((a & 0xdffffe00) == 0x4200) { |
acd35d4c |
929 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
930 | Pico32x.dirty_pal = 1; |
931 | return; |
932 | } |
933 | |
87accdf7 |
934 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
935 | p32x_sh2reg_write16(a, d, id); |
acd35d4c |
936 | return; |
937 | } |
938 | |
b78efee2 |
939 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
940 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
941 | } |
942 | |
b78efee2 |
943 | void p32x_sh2_write32(u32 a, u32 d, int id) |
acd35d4c |
944 | { |
4ea707e1 |
945 | if ((a & 0xfffffe00) == 0xfffffe00) { |
87accdf7 |
946 | sh2_peripheral_write32(a, d, id); |
4ea707e1 |
947 | return; |
948 | } |
949 | |
b78efee2 |
950 | p32x_sh2_write16(a, d >> 16, id); |
951 | p32x_sh2_write16(a + 2, d, id); |
acd35d4c |
952 | } |
953 | |
be2c4208 |
954 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
955 | void PicoMemSetup32x(void) |
956 | { |
957 | unsigned short *ps; |
958 | unsigned int *pl; |
5e49c3a8 |
959 | unsigned int rs; |
be2c4208 |
960 | int i; |
961 | |
962 | Pico32xMem = calloc(1, sizeof(*Pico32xMem)); |
963 | if (Pico32xMem == NULL) { |
964 | elprintf(EL_STATUS, "OOM"); |
965 | return; |
966 | } |
967 | |
4ea707e1 |
968 | dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; |
969 | |
be2c4208 |
970 | // generate 68k ROM |
971 | ps = (unsigned short *)Pico32xMem->m68k_rom; |
972 | pl = (unsigned int *)Pico32xMem->m68k_rom; |
973 | for (i = 1; i < 0xc0/4; i++) |
974fdb5b |
974 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
975 | |
976 | // fill with nops |
977 | for (i = 0xc0/2; i < 0x100/2; i++) |
978 | ps[i] = 0x4e71; |
979 | |
5e49c3a8 |
980 | #if 0 |
be2c4208 |
981 | ps[0xc0/2] = 0x46fc; |
982 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
983 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
984 | #else |
985 | ps[0xfe/2] = 0x4e75; // rts |
986 | #endif |
be2c4208 |
987 | |
988 | // fill remaining mem with ROM |
974fdb5b |
989 | memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100); |
be2c4208 |
990 | |
acd35d4c |
991 | // 32X ROM |
992 | // TODO: move |
993 | { |
994 | FILE *f = fopen("32X_M_BIOS.BIN", "rb"); |
995 | int i; |
996 | if (f == NULL) { |
b78efee2 |
997 | printf("missing 32X_M_BIOS.BIN\n"); |
acd35d4c |
998 | exit(1); |
999 | } |
1000 | fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f); |
1001 | fclose(f); |
b78efee2 |
1002 | f = fopen("32X_S_BIOS.BIN", "rb"); |
1003 | if (f == NULL) { |
1004 | printf("missing 32X_S_BIOS.BIN\n"); |
1005 | exit(1); |
1006 | } |
1007 | fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f); |
1008 | fclose(f); |
1009 | // byteswap |
acd35d4c |
1010 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) { |
1011 | int t = Pico32xMem->sh2_rom_m[i]; |
1012 | Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1]; |
1013 | Pico32xMem->sh2_rom_m[i + 1] = t; |
1014 | } |
b78efee2 |
1015 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) { |
1016 | int t = Pico32xMem->sh2_rom_s[i]; |
1017 | Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1]; |
1018 | Pico32xMem->sh2_rom_s[i + 1] = t; |
1019 | } |
acd35d4c |
1020 | } |
1021 | |
be2c4208 |
1022 | // cartridge area becomes unmapped |
1023 | // XXX: we take the easy way and don't unmap ROM, |
1024 | // so that we can avoid handling the RV bit. |
1025 | // m68k_map_unmap(0x000000, 0x3fffff); |
1026 | |
1027 | // MD ROM area |
974fdb5b |
1028 | rs = sizeof(Pico32xMem->m68k_rom); |
1029 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1030 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1031 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1032 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1033 | |
1034 | // DRAM area |
1035 | Pico32xSwapDRAM(1); |
be2c4208 |
1036 | |
1037 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
1038 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1039 | if (rs > 0x80000) |
1040 | rs = 0x80000; |
1041 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1042 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
be2c4208 |
1043 | |
1044 | // 32X ROM (banked) |
5e49c3a8 |
1045 | bank_switch(0); |
b78efee2 |
1046 | |
1047 | // setup poll detector |
1048 | m68k_poll.flag = P32XF_68KPOLL; |
be20816c |
1049 | m68k_poll.cyc_max = 64; |
b78efee2 |
1050 | sh2_poll[0].flag = P32XF_MSH2POLL; |
be20816c |
1051 | sh2_poll[0].cyc_max = 16; |
b78efee2 |
1052 | sh2_poll[1].flag = P32XF_SSH2POLL; |
be20816c |
1053 | sh2_poll[1].cyc_max = 16; |
be2c4208 |
1054 | } |
1055 | |