32x: interpreter-wrap drc works (demos only). SVP drc refactoring.
[picodrive.git] / pico / cd / pico.c
CommitLineData
672ad671 1// (c) Copyright 2007 notaz, All rights reserved.
cc68a136 2
3
efcba75f 4#include "../pico_int.h"
43e6eaad 5#include "../sound/ym2612.h"
cc68a136 6
76276b0b 7extern unsigned char formatted_bram[4*0x10];
89fa852d 8extern unsigned int s68k_poll_adclk;
9
721cd396 10void (*PicoMCDopenTray)(void) = NULL;
d687ef50 11void (*PicoMCDcloseTray)(void) = NULL;
89fa852d 12
cc68a136 13
2aa27095 14PICO_INTERNAL void PicoInitMCD(void)
cc68a136 15{
16 SekInitS68k();
17 Init_CD_Driver();
cc68a136 18}
19
eff55556 20PICO_INTERNAL void PicoExitMCD(void)
cc68a136 21{
22 End_CD_Driver();
23}
24
1cb1584b 25PICO_INTERNAL void PicoPowerMCD(void)
26{
27 int fmt_size = sizeof(formatted_bram);
28 memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
29 memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
30 memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
31 memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
32 memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
33}
34
35PICO_INTERNAL int PicoResetMCD(void)
cc68a136 36{
51a902ae 37 memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7 38 memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605 39 memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae 40
d1df8786 41 *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
c008977e 42 Pico_mcd->m.state_flags |= 1; // s68k reset pending
672ad671 43 Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
cc68a136 44
cc68a136 45 Reset_CD();
5c69a605 46 LC89510_Reset();
51a902ae 47 gfx_cd_reset();
3aa1e148 48#ifdef _ASM_CD_MEMORY_C
00bd648e 49 //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527 50#endif
cc68a136 51
6cadc2da 52 // use SRam.data for RAM cart
af37bca8 53 if (PicoOpt & POPT_EN_MCD_RAMCART) {
d6114368 54 if (SRam.data == NULL)
55 SRam.data = calloc(1, 0x12000);
56 }
57 else if (SRam.data != NULL) {
58 free(SRam.data);
59 SRam.data = NULL;
60 }
b542be46 61 SRam.start = SRam.end = 0; // unused
6cadc2da 62
cc68a136 63 return 0;
64}
65
eff55556 66static __inline void SekRunM68k(int cyc)
cc68a136 67{
68 int cyc_do;
69 SekCycleAim+=cyc;
3ec29f01 70 if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
b5e5172d 71#if defined(EMU_CORE_DEBUG)
72 SekCycleCnt+=CM_compareRun(cyc_do, 0);
73#elif defined(EMU_C68K)
3aa1e148 74 PicoCpuCM68k.cycles=cyc_do;
75 CycloneRun(&PicoCpuCM68k);
76 SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
b837b69b 77#elif defined(EMU_M68K)
3aa1e148 78 m68k_set_context(&PicoCpuMM68k);
cc68a136 79 SekCycleCnt+=m68k_execute(cyc_do);
3aa1e148 80#elif defined(EMU_F68K)
81 g_m68kcontext=&PicoCpuFM68k;
c060a9ab 82 SekCycleCnt+=fm68k_emulate(cyc_do, 0, 0);
cc68a136 83#endif
84}
85
86static __inline void SekRunS68k(int cyc)
87{
88 int cyc_do;
89 SekCycleAimS68k+=cyc;
3ec29f01 90 if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
b5e5172d 91#if defined(EMU_CORE_DEBUG)
92 SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
93#elif defined(EMU_C68K)
3aa1e148 94 PicoCpuCS68k.cycles=cyc_do;
95 CycloneRun(&PicoCpuCS68k);
96 SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
b837b69b 97#elif defined(EMU_M68K)
3aa1e148 98 m68k_set_context(&PicoCpuMS68k);
cc68a136 99 SekCycleCntS68k+=m68k_execute(cyc_do);
3aa1e148 100#elif defined(EMU_F68K)
101 g_m68kcontext=&PicoCpuFS68k;
c060a9ab 102 SekCycleCntS68k+=fm68k_emulate(cyc_do, 0, 0);
cc68a136 103#endif
104}
105
7336a99a 106#define PS_STEP_M68K ((488<<16)/20) // ~24
107//#define PS_STEP_S68K 13
68cba51e 108
8022f53d 109#if defined(_ASM_CD_PICO_C)
110extern void SekRunPS(int cyc_m68k, int cyc_s68k);
111#elif defined(EMU_F68K)
112static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
113{
114 SekCycleAim+=cyc_m68k;
115 SekCycleAimS68k+=cyc_s68k;
c060a9ab 116 fm68k_emulate(0, 1, 0);
8022f53d 117}
a4030801 118#else
68cba51e 119static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
120{
7336a99a 121 int cycn, cycn_s68k, cyc_do;
68cba51e 122 SekCycleAim+=cyc_m68k;
123 SekCycleAimS68k+=cyc_s68k;
7336a99a 124
125// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
126// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
127
128 /* loop 488 downto 0 in steps of PS_STEP */
129 for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
130 {
7336a99a 131 cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
7336a99a 132 if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
68cba51e 133#if defined(EMU_C68K)
3aa1e148 134 PicoCpuCM68k.cycles = cyc_do;
135 CycloneRun(&PicoCpuCM68k);
136 SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
68cba51e 137#elif defined(EMU_M68K)
3aa1e148 138 m68k_set_context(&PicoCpuMM68k);
139 SekCycleCnt += m68k_execute(cyc_do);
140#elif defined(EMU_F68K)
141 g_m68kcontext = &PicoCpuFM68k;
c060a9ab 142 SekCycleCnt += fm68k_emulate(cyc_do, 0, 0);
68cba51e 143#endif
7336a99a 144 }
7336a99a 145 if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
68cba51e 146#if defined(EMU_C68K)
3aa1e148 147 PicoCpuCS68k.cycles = cyc_do;
148 CycloneRun(&PicoCpuCS68k);
149 SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
68cba51e 150#elif defined(EMU_M68K)
3aa1e148 151 m68k_set_context(&PicoCpuMS68k);
152 SekCycleCntS68k += m68k_execute(cyc_do);
153#elif defined(EMU_F68K)
154 g_m68kcontext = &PicoCpuFS68k;
c060a9ab 155 SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0);
68cba51e 156#endif
7336a99a 157 }
68cba51e 158 }
68cba51e 159}
7336a99a 160#endif
68cba51e 161
162
bf098bc5 163static __inline void check_cd_dma(void)
164{
165 int ddx;
166
c459aefd 167 if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
bf098bc5 168
169 ddx = Pico_mcd->s68k_regs[4] & 7;
170 if (ddx < 2) return; // invalid
c459aefd 171 if (ddx < 4) {
172 Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
173 return;
174 }
bf098bc5 175 if (ddx == 6) return; // invalid
176
177 Update_CDC_TRansfer(ddx); // now go and do the actual transfer
178}
179
4f265db7 180static __inline void update_chips(void)
181{
182 int counter_timer, int3_set;
183 int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
184
185 // 75Hz CDC update
186 if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
187 Pico_mcd->m.counter75hz -= counter75hz_lim;
188 Check_CD_Command();
189 }
190
191 // update timers
192 counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
193 Pico_mcd->m.timer_stopwatch += counter_timer;
194 if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
195 Pico_mcd->m.timer_int3 -= counter_timer;
196 if (Pico_mcd->m.timer_int3 < 0) {
197 if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
69996cb7 198 elprintf(EL_INTS, "s68k: timer irq 3");
4f265db7 199 SekInterruptS68k(3);
200 Pico_mcd->m.timer_int3 += int3_set << 16;
201 }
202 // is this really what happens if irq3 is masked out?
203 Pico_mcd->m.timer_int3 &= 0xffffff;
204 }
205 }
206
207 // update gfx chip
208 if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
209 gfx_cd_update();
210}
211
b837b69b 212
bf5fbbb4 213#define PICO_CD
c987bb5c 214#define CPUS_RUN(m68k_cycles,s68k_cycles) \
215{ \
216 if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \
217 SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \
218 } else { \
219 SekRunM68k(m68k_cycles); \
220 if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \
221 SekRunS68k(s68k_cycles); \
222 } \
223}
efcba75f 224#include "../pico_cmn.c"
cc68a136 225
226
2aa27095 227PICO_INTERNAL void PicoFrameMCD(void)
cc68a136 228{
602133e1 229 if (!(PicoOpt&POPT_ALT_RENDERER))
cc68a136 230 PicoFrameStart();
231
bf5fbbb4 232 PicoFrameHints();
cc68a136 233}
234
235