[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2021 notaz                                              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "assem_arm64.h"
#include "linkage_offsets.h"

#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define ndrc_add_jump_out	ESYM(ndrc_add_jump_out)
#define ndrc_get_addr_ht	ESYM(ndrc_get_addr_ht)
#define gen_interupt		ESYM(gen_interupt)
#define gteCheckStallRaw	ESYM(gteCheckStallRaw)
#define psxException		ESYM(psxException)
#define execI			ESYM(execI)
#endif

#if (LO_mem_wtab & 7)
#error misligned pointers
#endif

.bss
	.align	4
	.global dynarec_local
	EOBJECT(dynarec_local)
	ESIZE(dynarec_local, LO_dynarec_local_size)
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name ASM_SEPARATOR \
	.globl vname; \
	EOBJECT(vname); \
	ESIZE(vname, LO_dynarec_local_size)

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
#DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
#DRC_VAR(code, 4)
#DRC_VAR(cycle, 4)
#DRC_VAR(interrupt, 4)
#DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 8)
DRC_VAR(mem_wtab, 8)
DRC_VAR(psxH_ptr, 8)
DRC_VAR(invc_ptr, 8)
DRC_VAR(zeromem_ptr, 8)
DRC_VAR(scratch_buf_ptr, 8)
DRC_VAR(ram_offset, 8)
DRC_VAR(mini_ht, 256)


	.text
	.align	2

FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	bl	ndrc_get_addr_ht
	br	x0
	ESIZE(dyna_linker, .-dyna_linker)

	.align	2
FUNCTION(cc_interrupt):
	ldr	w0, [rFP, #LO_last_count]
	add	rCC, w0, rCC
	str	wzr, [rFP, #LO_pending_exception]
	str	rCC, [rFP, #LO_cycle]		/* PCSX cycles */
	mov	x21, lr
1:
	add	x0, rFP, #LO_reg_cop0           /* CP0 */
	bl	gen_interupt
	mov	lr, x21
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_next_interupt]
	ldr	w1, [rFP, #LO_pending_exception]
	ldr	w2, [rFP, #LO_stop]
	str	w0, [rFP, #LO_last_count]
	sub	rCC, rCC, w0
	cbnz	w2, new_dyna_leave
	cbnz	w1, 2f
	ret
2:
	ldr	w0, [rFP, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	br	x0
	ESIZE(cc_interrupt, .-cc_interrupt)

	.align	2
FUNCTION(jump_addrerror_ds): /* R3000E_AdEL / R3000E_AdES in w0 */
	str	w1, [rFP, #(LO_psxRegs + (34+8)*4)]  /* BadVaddr */
	mov	w1, #1
	b	call_psxException
FUNCTION(jump_addrerror):
	str	w1, [rFP, #(LO_psxRegs + (34+8)*4)]  /* BadVaddr */
	mov	w1, #0
	b	call_psxException
FUNCTION(jump_overflow_ds):
	mov	w0, #(12<<2)  /* R3000E_Ov */
	mov	w1, #1
	b	call_psxException
FUNCTION(jump_overflow):
	mov	w0, #(12<<2)
	mov	w1, #0
	b	call_psxException
FUNCTION(jump_break_ds):
	mov	w0, #(9<<2)  /* R3000E_Bp */
	mov	w1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	w0, #(9<<2)
	mov	w1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	w0, #(8<<2)  /* R3000E_Syscall */
	mov	w1, #2
	b	call_psxException
FUNCTION(jump_syscall):
	mov	w0, #(8<<2)
	mov	w1, #0

call_psxException:
	ldr	w3, [rFP, #LO_last_count]
	str	w2, [rFP, #LO_pcaddr]
	add	rCC, w3, rCC
	str	rCC, [rFP, #LO_cycle]           /* PCSX cycles */
	add	x2, rFP, #LO_reg_cop0           /* CP0 */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	w2, [rFP, #LO_stop]
	ldr	w1, [rFP, #LO_next_interupt]
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_pcaddr]
	sub	rCC, rCC, w1
	str	w1, [rFP, #LO_last_count]
	cbnz	w2, new_dyna_leave
	bl	ndrc_get_addr_ht
	br	x0
	ESIZE(jump_to_new_pc, .-jump_to_new_pc)

	/* stack must be aligned by 16, and include space for save_regs() use */
	.align	2
FUNCTION(new_dyna_start):
	stp	x29, x30, [sp, #-SSP_ALL]!
	ldr	w1,  [x0, #LO_next_interupt]
	ldr	w2,  [x0, #LO_cycle]
	stp	x19, x20, [sp, #16*1]
	stp	x21, x22, [sp, #16*2]
	stp	x23, x24, [sp, #16*3]
	stp	x25, x26, [sp, #16*4]
	stp	x27, x28, [sp, #16*5]
	mov	rFP, x0
	ldr	w0,  [rFP, #LO_pcaddr]
	str	w1,  [rFP, #LO_last_count]
	sub	rCC, w2, w1
	bl	ndrc_get_addr_ht
	br	x0
	ESIZE(new_dyna_start, .-new_dyna_start)

	.align	2
FUNCTION(new_dyna_leave):
	ldr	w0,  [rFP, #LO_last_count]
	add	rCC, rCC, w0
	str	rCC, [rFP, #LO_cycle]
	ldp	x19, x20, [sp, #16*1]
	ldp	x21, x22, [sp, #16*2]
	ldp	x23, x24, [sp, #16*3]
	ldp	x25, x26, [sp, #16*4]
	ldp	x27, x28, [sp, #16*5]
	ldp	x29, x30, [sp], #SSP_ALL
	ret
	ESIZE(new_dyna_leave, .-new_dyna_leave)

/* --------------------------------------- */

.align	2

.macro memhandler_pre
	/* w0 = addr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
	ldr	w4, [rFP, #LO_last_count]
	add	w4, w4, w2
	str	w4, [rFP, #LO_cycle]
.endm

.macro memhandler_post
	ldr	w0, [rFP, #LO_next_interupt]
	ldr	w2, [rFP, #LO_cycle]        // memhandlers can modify cc, like dma
	str	w0, [rFP, #LO_last_count]
	sub	w0, w2, w0
.endm

FUNCTION(do_memhandler_pre):
	memhandler_pre
	ret

FUNCTION(do_memhandler_post):
	memhandler_post
	ret

.macro pcsx_read_mem readop tab_shift
	/* w0 = address, x1 = handler_tab, w2 = cycles */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x1, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	\readop	w0, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_read8):
	add     x1, x1, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_read_mem ldrb, 0
	b	handler_read_end

FUNCTION(jump_handler_read16):
	add     x1, x1, #0x1000/4*8               /* shift to r16 part */
	pcsx_read_mem ldrh, 1
	b	handler_read_end

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldr, 2

handler_read_end:
	ldp	xzr, x30, [sp], #16
	ret

.macro pcsx_write_mem wrtop movop tab_shift
	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	mov	w0, w2                    /* cycle return */
	\wrtop	w1, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	str	w0, [rFP, #LO_address]    /* some handlers still need it... */
	\movop	w0, w1
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_write8):
	add     x3, x3, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_write_mem strb, uxtb, 0
	b	handler_write_end

FUNCTION(jump_handler_write16):
	add     x3, x3, #0x1000/4*8               /* shift to r16 part */
	pcsx_write_mem strh, uxth, 1
	b	handler_write_end

FUNCTION(jump_handler_write32):
	pcsx_write_mem str, mov, 2

handler_write_end:
	memhandler_post
	ldp	xzr, x30, [sp], #16
	ret

FUNCTION(jump_handle_swl):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	orr	w4, wzr, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	jump_handle_swx_interp
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	stur	w1, [x3, #-3]
	ret
2:
	lsr	w2, w1, #8
	lsr	w1, w1, #24
	sturh	w2, [x3, #-2]
	strb	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w1, w1, #16
	sturh	w1, [x3, #-1]
	ret
0:
	lsr	w2, w1, #24
	strb	w2, [x3]
	ret

FUNCTION(jump_handle_swr):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	orr	w4, wzr, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	jump_handle_swx_interp
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	strb	w1, [x3]
	ret
2:
	strh	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w2, w1, #8
	strb	w1, [x3]
	sturh	w2, [x3, #1]
	ret
0:
	str	w1, [x3]
	ret

jump_handle_swx_interp: /* almost never happens */
	ldr	w3, [rFP, #LO_last_count]
	add	x0, rFP, #LO_psxRegs
	add	w2, w3, w2
	str	w2, [rFP, #LO_cycle]           /* PCSX cycles */
	bl	execI
	b	jump_to_new_pc

FUNCTION(call_gteStall):
	/* w0 = op_cycles, w1 = cycles */
	ldr	w2, [rFP, #LO_last_count]
	str	lr, [rFP, #LO_saved_lr]
	add	w1, w1, w2
	str	w1, [rFP, #LO_cycle]
	add	x1, rFP, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [rFP, #LO_saved_lr]
	add	rCC, rCC, w0
	ret

#ifdef DRC_DBG
#undef do_insn_cmp
FUNCTION(do_insn_cmp_arm64):
	stp	x2,  x3,  [sp, #(SSP_CALLEE_REGS + 2*8)]
	stp	x4,  x5,  [sp, #(SSP_CALLEE_REGS + 4*8)]
	stp	x6,  x7,  [sp, #(SSP_CALLEE_REGS + 6*8)]
	stp	x8,  x9,  [sp, #(SSP_CALLEE_REGS + 8*8)]
	stp	x10, x11, [sp, #(SSP_CALLEE_REGS + 10*8)]
	stp	x12, x13, [sp, #(SSP_CALLEE_REGS + 12*8)]
	stp	x14, x15, [sp, #(SSP_CALLEE_REGS + 14*8)]
	stp	x16, x17, [sp, #(SSP_CALLEE_REGS + 16*8)]
	stp	x18, x30, [sp, #(SSP_CALLEE_REGS + 18*8)]
	bl	do_insn_cmp
	ldp	x2,  x3,  [sp, #(SSP_CALLEE_REGS + 2*8)]
	ldp	x4,  x5,  [sp, #(SSP_CALLEE_REGS + 4*8)]
	ldp	x6,  x7,  [sp, #(SSP_CALLEE_REGS + 6*8)]
	ldp	x8,  x9,  [sp, #(SSP_CALLEE_REGS + 8*8)]
	ldp	x10, x11, [sp, #(SSP_CALLEE_REGS + 10*8)]
	ldp	x12, x13, [sp, #(SSP_CALLEE_REGS + 12*8)]
	ldp	x14, x15, [sp, #(SSP_CALLEE_REGS + 14*8)]
	ldp	x16, x17, [sp, #(SSP_CALLEE_REGS + 16*8)]
	ldp	x18, x30, [sp, #(SSP_CALLEE_REGS + 18*8)]
	ret
#endif
Commit	Line	Data
be516ebe	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2021 notaz *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "assem_arm64.h"
	25	#include "linkage_offsets.h"
	26
c57af5e6	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
	29	#define ndrc_add_jump_out ESYM(ndrc_add_jump_out)
	30	#define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
	31	#define gen_interupt ESYM(gen_interupt)
	32	#define gteCheckStallRaw ESYM(gteCheckStallRaw)
	33	#define psxException ESYM(psxException)
	34	#define execI ESYM(execI)
	35	#endif
	36
39b71d9a	37	#if (LO_mem_wtab & 7)
	38	#error misligned pointers
	39	#endif
	40
be516ebe	41	.bss
	42	.align 4
	43	.global dynarec_local
c57af5e6	44	EOBJECT(dynarec_local)
c57af5e6	45	ESIZE(dynarec_local, LO_dynarec_local_size)
be516ebe	46	dynarec_local:
	47	.space LO_dynarec_local_size
	48
	49	#define DRC_VAR_(name, vname, size_) \
c57af5e6	50	vname = dynarec_local + LO_##name ASM_SEPARATOR \
	51	.globl vname; \
	52	EOBJECT(vname); \
	53	ESIZE(vname, LO_dynarec_local_size)
be516ebe	54
	55	#define DRC_VAR(name, size_) \
	56	DRC_VAR_(name, ESYM(name), size_)
	57
	58	DRC_VAR(next_interupt, 4)
	59	DRC_VAR(cycle_count, 4)
	60	DRC_VAR(last_count, 4)
	61	DRC_VAR(pending_exception, 4)
	62	DRC_VAR(stop, 4)
687b4580	63	DRC_VAR(branch_target, 4)
be516ebe	64	DRC_VAR(address, 4)
7f94b097	65	DRC_VAR(hack_addr, 4)
be516ebe	66	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	67
	68	/* psxRegs */
7c3a5182	69	#DRC_VAR(reg, 128)
be516ebe	70	DRC_VAR(lo, 4)
	71	DRC_VAR(hi, 4)
	72	DRC_VAR(reg_cop0, 128)
	73	DRC_VAR(reg_cop2d, 128)
	74	DRC_VAR(reg_cop2c, 128)
	75	DRC_VAR(pcaddr, 4)
	76	#DRC_VAR(code, 4)
	77	#DRC_VAR(cycle, 4)
	78	#DRC_VAR(interrupt, 4)
	79	#DRC_VAR(intCycle, 256)
	80
	81	DRC_VAR(rcnts, 744)
be516ebe	82	DRC_VAR(inv_code_start, 4)
be516ebe	83	DRC_VAR(inv_code_end, 4)
687b4580	84	DRC_VAR(mem_rtab, 8)
	85	DRC_VAR(mem_wtab, 8)
	86	DRC_VAR(psxH_ptr, 8)
	87	DRC_VAR(invc_ptr, 8)
	88	DRC_VAR(zeromem_ptr, 8)
	89	DRC_VAR(scratch_buf_ptr, 8)
37387d8b	90	DRC_VAR(ram_offset, 8)
be516ebe	91	DRC_VAR(mini_ht, 256)
be516ebe	92
	93
	94	.text
	95	.align 2
	96
be516ebe	97	FUNCTION(dyna_linker):
	98	/* r0 = virtual target address */
	99	/* r1 = instruction to patch */
104df9d3	100	bl ndrc_get_addr_ht
4bdc30ab	101	br x0
c57af5e6	102	ESIZE(dyna_linker, .-dyna_linker)
be516ebe	103
be516ebe	104	.align 2
be516ebe	105	FUNCTION(cc_interrupt):
d1e4ebd9	106	ldr w0, [rFP, #LO_last_count]
d1e4ebd9	107	add rCC, w0, rCC
d1e4ebd9	108	str wzr, [rFP, #LO_pending_exception]
d1e4ebd9	109	str rCC, [rFP, #LO_cycle] /* PCSX cycles */
d1e4ebd9	110	mov x21, lr
d1e4ebd9	111	1:
de6dbc52	112	add x0, rFP, #LO_reg_cop0 /* CP0 */
d1e4ebd9	113	bl gen_interupt
	114	mov lr, x21
	115	ldr rCC, [rFP, #LO_cycle]
	116	ldr w0, [rFP, #LO_next_interupt]
	117	ldr w1, [rFP, #LO_pending_exception]
	118	ldr w2, [rFP, #LO_stop]
	119	str w0, [rFP, #LO_last_count]
	120	sub rCC, rCC, w0
	121	cbnz w2, new_dyna_leave
	122	cbnz w1, 2f
	123	ret
	124	2:
	125	ldr w0, [rFP, #LO_pcaddr]
104df9d3	126	bl ndrc_get_addr_ht
d1e4ebd9	127	br x0
c57af5e6	128	ESIZE(cc_interrupt, .-cc_interrupt)
be516ebe	129
be516ebe	130	.align 2
277718fa	131	FUNCTION(jump_addrerror_ds): /* R3000E_AdEL / R3000E_AdES in w0 */
	132	str w1, [rFP, #(LO_psxRegs + (34+8)4)] / BadVaddr */
	133	mov w1, #1
	134	b call_psxException
	135	FUNCTION(jump_addrerror):
	136	str w1, [rFP, #(LO_psxRegs + (34+8)4)] / BadVaddr */
	137	mov w1, #0
	138	b call_psxException
a5cd72d0	139	FUNCTION(jump_overflow_ds):
	140	mov w0, #(12<<2) /* R3000E_Ov */
	141	mov w1, #1
	142	b call_psxException
	143	FUNCTION(jump_overflow):
	144	mov w0, #(12<<2)
	145	mov w1, #0
	146	b call_psxException
d1150cd6	147	FUNCTION(jump_break_ds):
a5cd72d0	148	mov w0, #(9<<2) /* R3000E_Bp */
d1150cd6	149	mov w1, #1
	150	b call_psxException
	151	FUNCTION(jump_break):
a5cd72d0	152	mov w0, #(9<<2)
d1150cd6	153	mov w1, #0
	154	b call_psxException
	155	FUNCTION(jump_syscall_ds):
a5cd72d0	156	mov w0, #(8<<2) /* R3000E_Syscall */
bc7c5acb	157	mov w1, #2
d1150cd6	158	b call_psxException
be516ebe	159	FUNCTION(jump_syscall):
a5cd72d0	160	mov w0, #(8<<2)
d1150cd6	161	mov w1, #0
	162
	163	call_psxException:
	164	ldr w3, [rFP, #LO_last_count]
	165	str w2, [rFP, #LO_pcaddr]
	166	add rCC, w3, rCC
6d75addf	167	str rCC, [rFP, #LO_cycle] /* PCSX cycles */
de6dbc52	168	add x2, rFP, #LO_reg_cop0 /* CP0 */
d1150cd6	169	bl psxException
be516ebe	170
be516ebe	171	/* note: psxException might do recursive recompiler call from it's HLE code,
be516ebe	172	* so be ready for this */
3968e69e	173	FUNCTION(jump_to_new_pc):
dc4fa8bc	174	ldr w2, [rFP, #LO_stop]
81dbbf4c	175	ldr w1, [rFP, #LO_next_interupt]
	176	ldr rCC, [rFP, #LO_cycle]
	177	ldr w0, [rFP, #LO_pcaddr]
3968e69e	178	sub rCC, rCC, w1
81dbbf4c	179	str w1, [rFP, #LO_last_count]
dc4fa8bc	180	cbnz w2, new_dyna_leave
104df9d3	181	bl ndrc_get_addr_ht
be516ebe	182	br x0
c57af5e6	183	ESIZE(jump_to_new_pc, .-jump_to_new_pc)
be516ebe	184
687b4580	185	/* stack must be aligned by 16, and include space for save_regs() use */
be516ebe	186	.align 2
be516ebe	187	FUNCTION(new_dyna_start):
687b4580	188	stp x29, x30, [sp, #-SSP_ALL]!
be516ebe	189	ldr w1, [x0, #LO_next_interupt]
	190	ldr w2, [x0, #LO_cycle]
	191	stp x19, x20, [sp, #16*1]
	192	stp x21, x22, [sp, #16*2]
	193	stp x23, x24, [sp, #16*3]
	194	stp x25, x26, [sp, #16*4]
	195	stp x27, x28, [sp, #16*5]
	196	mov rFP, x0
	197	ldr w0, [rFP, #LO_pcaddr]
	198	str w1, [rFP, #LO_last_count]
	199	sub rCC, w2, w1
104df9d3	200	bl ndrc_get_addr_ht
be516ebe	201	br x0
c57af5e6	202	ESIZE(new_dyna_start, .-new_dyna_start)
be516ebe	203
	204	.align 2
	205	FUNCTION(new_dyna_leave):
	206	ldr w0, [rFP, #LO_last_count]
	207	add rCC, rCC, w0
	208	str rCC, [rFP, #LO_cycle]
	209	ldp x19, x20, [sp, #16*1]
	210	ldp x21, x22, [sp, #16*2]
	211	ldp x23, x24, [sp, #16*3]
	212	ldp x25, x26, [sp, #16*4]
	213	ldp x27, x28, [sp, #16*5]
687b4580	214	ldp x29, x30, [sp], #SSP_ALL
be516ebe	215	ret
c57af5e6	216	ESIZE(new_dyna_leave, .-new_dyna_leave)
be516ebe	217
	218	/* --------------------------------------- */
	219
	220	.align 2
	221
d1e4ebd9	222	.macro memhandler_pre
eb38e4a2	223	/* w0 = addr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
d1e4ebd9	224	ldr w4, [rFP, #LO_last_count]
	225	add w4, w4, w2
	226	str w4, [rFP, #LO_cycle]
	227	.endm
	228
	229	.macro memhandler_post
9b9af0d1	230	ldr w0, [rFP, #LO_next_interupt]
	231	ldr w2, [rFP, #LO_cycle] // memhandlers can modify cc, like dma
	232	str w0, [rFP, #LO_last_count]
	233	sub w0, w2, w0
d1e4ebd9	234	.endm
	235
	236	FUNCTION(do_memhandler_pre):
	237	memhandler_pre
	238	ret
	239
	240	FUNCTION(do_memhandler_post):
	241	memhandler_post
	242	ret
	243
	244	.macro pcsx_read_mem readop tab_shift
	245	/* w0 = address, x1 = handler_tab, w2 = cycles */
d1e4ebd9	246	ubfm w4, w0, #\tab_shift, #11
	247	ldr x3, [x1, w4, uxtw #3]
	248	adds x3, x3, x3
	249	bcs 0f
	250	\readop w0, [x3, w4, uxtw #\tab_shift]
	251	ret
	252	0:
3968e69e	253	stp xzr, x30, [sp, #-16]!
d1e4ebd9	254	memhandler_pre
	255	blr x3
	256	.endm
	257
be516ebe	258	FUNCTION(jump_handler_read8):
3968e69e	259	add x1, x1, #0x1000/48 + 0x1000/28 /* shift to r8 part */
d1e4ebd9	260	pcsx_read_mem ldrb, 0
d1e4ebd9	261	b handler_read_end
be516ebe	262
be516ebe	263	FUNCTION(jump_handler_read16):
3968e69e	264	add x1, x1, #0x1000/48 / shift to r16 part */
d1e4ebd9	265	pcsx_read_mem ldrh, 1
d1e4ebd9	266	b handler_read_end
be516ebe	267
be516ebe	268	FUNCTION(jump_handler_read32):
d1e4ebd9	269	pcsx_read_mem ldr, 2
	270
	271	handler_read_end:
	272	ldp xzr, x30, [sp], #16
	273	ret
	274
	275	.macro pcsx_write_mem wrtop movop tab_shift
	276	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
d1e4ebd9	277	ubfm w4, w0, #\tab_shift, #11
d1e4ebd9	278	ldr x3, [x3, w4, uxtw #3]
d1e4ebd9	279	adds x3, x3, x3
d1e4ebd9	280	bcs 0f
	281	mov w0, w2 /* cycle return */
	282	\wrtop w1, [x3, w4, uxtw #\tab_shift]
	283	ret
	284	0:
3968e69e	285	stp xzr, x30, [sp, #-16]!
3968e69e	286	str w0, [rFP, #LO_address] /* some handlers still need it... */
d1e4ebd9	287	\movop w0, w1
	288	memhandler_pre
	289	blr x3
	290	.endm
be516ebe	291
be516ebe	292	FUNCTION(jump_handler_write8):
3968e69e	293	add x3, x3, #0x1000/48 + 0x1000/28 /* shift to r8 part */
c57af5e6	294	pcsx_write_mem strb, uxtb, 0
d1e4ebd9	295	b handler_write_end
be516ebe	296
be516ebe	297	FUNCTION(jump_handler_write16):
3968e69e	298	add x3, x3, #0x1000/48 / shift to r16 part */
c57af5e6	299	pcsx_write_mem strh, uxth, 1
d1e4ebd9	300	b handler_write_end
be516ebe	301
be516ebe	302	FUNCTION(jump_handler_write32):
c57af5e6	303	pcsx_write_mem str, mov, 2
be516ebe	304
d1e4ebd9	305	handler_write_end:
	306	memhandler_post
	307	ldp xzr, x30, [sp], #16
	308	ret
be516ebe	309
be516ebe	310	FUNCTION(jump_handle_swl):
3968e69e	311	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	312	ldr x3, [rFP, #LO_mem_wtab]
48ce2528	313	orr w4, wzr, w0, lsr #12
3968e69e	314	ldr x3, [x3, w4, uxtw #3]
3968e69e	315	adds x3, x3, x3
de6dbc52	316	bcs jump_handle_swx_interp
3968e69e	317	add x3, x0, x3
	318	mov w0, w2
	319	tbz x3, #1, 10f // & 2
	320	tbz x3, #0, 2f // & 1
	321	3:
	322	stur w1, [x3, #-3]
	323	ret
	324	2:
	325	lsr w2, w1, #8
	326	lsr w1, w1, #24
	327	sturh w2, [x3, #-2]
	328	strb w1, [x3]
	329	ret
	330	10:
	331	tbz x3, #0, 0f // & 1
	332	1:
	333	lsr w1, w1, #16
	334	sturh w1, [x3, #-1]
	335	ret
	336	0:
	337	lsr w2, w1, #24
	338	strb w2, [x3]
	339	ret
be516ebe	340
be516ebe	341	FUNCTION(jump_handle_swr):
3968e69e	342	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	343	ldr x3, [rFP, #LO_mem_wtab]
48ce2528	344	orr w4, wzr, w0, lsr #12
3968e69e	345	ldr x3, [x3, w4, uxtw #3]
3968e69e	346	adds x3, x3, x3
de6dbc52	347	bcs jump_handle_swx_interp
3968e69e	348	add x3, x0, x3
	349	mov w0, w2
	350	tbz x3, #1, 10f // & 2
	351	tbz x3, #0, 2f // & 1
	352	3:
	353	strb w1, [x3]
	354	ret
	355	2:
	356	strh w1, [x3]
	357	ret
	358	10:
	359	tbz x3, #0, 0f // & 1
	360	1:
	361	lsr w2, w1, #8
	362	strb w1, [x3]
	363	sturh w2, [x3, #1]
	364	ret
	365	0:
	366	str w1, [x3]
	367	ret
de6dbc52	368
	369	jump_handle_swx_interp: /* almost never happens */
	370	ldr w3, [rFP, #LO_last_count]
	371	add x0, rFP, #LO_psxRegs
	372	add w2, w3, w2
	373	str w2, [rFP, #LO_cycle] /* PCSX cycles */
	374	bl execI
	375	b jump_to_new_pc
be516ebe	376
81dbbf4c	377	FUNCTION(call_gteStall):
	378	/* w0 = op_cycles, w1 = cycles */
	379	ldr w2, [rFP, #LO_last_count]
	380	str lr, [rFP, #LO_saved_lr]
	381	add w1, w1, w2
	382	str w1, [rFP, #LO_cycle]
	383	add x1, rFP, #LO_psxRegs
	384	bl gteCheckStallRaw
	385	ldr lr, [rFP, #LO_saved_lr]
	386	add rCC, rCC, w0
	387	ret
	388
33a1eda1	389	#ifdef DRC_DBG
	390	#undef do_insn_cmp
	391	FUNCTION(do_insn_cmp_arm64):
	392	stp x2, x3, [sp, #(SSP_CALLEE_REGS + 2*8)]
	393	stp x4, x5, [sp, #(SSP_CALLEE_REGS + 4*8)]
	394	stp x6, x7, [sp, #(SSP_CALLEE_REGS + 6*8)]
	395	stp x8, x9, [sp, #(SSP_CALLEE_REGS + 8*8)]
	396	stp x10, x11, [sp, #(SSP_CALLEE_REGS + 10*8)]
	397	stp x12, x13, [sp, #(SSP_CALLEE_REGS + 12*8)]
	398	stp x14, x15, [sp, #(SSP_CALLEE_REGS + 14*8)]
	399	stp x16, x17, [sp, #(SSP_CALLEE_REGS + 16*8)]
	400	stp x18, x30, [sp, #(SSP_CALLEE_REGS + 18*8)]
	401	bl do_insn_cmp
	402	ldp x2, x3, [sp, #(SSP_CALLEE_REGS + 2*8)]
	403	ldp x4, x5, [sp, #(SSP_CALLEE_REGS + 4*8)]
	404	ldp x6, x7, [sp, #(SSP_CALLEE_REGS + 6*8)]
	405	ldp x8, x9, [sp, #(SSP_CALLEE_REGS + 8*8)]
	406	ldp x10, x11, [sp, #(SSP_CALLEE_REGS + 10*8)]
	407	ldp x12, x13, [sp, #(SSP_CALLEE_REGS + 12*8)]
	408	ldp x14, x15, [sp, #(SSP_CALLEE_REGS + 14*8)]
	409	ldp x16, x17, [sp, #(SSP_CALLEE_REGS + 16*8)]
	410	ldp x18, x30, [sp, #(SSP_CALLEE_REGS + 18*8)]
	411	ret
	412	#endif