[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "../gpu.h"
#include "../psxmem_map.h"
#include "emu_if.h"
#include "pcsxmem.h"

#ifdef __thumb__
#error the dynarec is incompatible with Thumb functions,
#error please add -marm to compile flags
#endif

//#define memprintf printf
#define memprintf(...)

static uintptr_t *mem_readtab;
static uintptr_t *mem_writetab;
static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];

static
#ifdef __clang__
// When this is called in a loop, and 'h' is a function pointer, clang will crash.
__attribute__ ((noinline))
#endif
void map_item(uintptr_t *out, const void *h, uintptr_t flag)
{
	uintptr_t hv = (uintptr_t)h;
	if (hv & 1) {
		SysPrintf("FATAL: %p has LSB set\n", h);
		abort();
	}
	*out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
}

// size must be power of 2, at least 4k
#define map_l1_mem(tab, i, addr, size, base) \
	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)

#define IOMEM32(a) (((a) & 0xfff) / 4)
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))

u8 zero_mem[0x1000];

u32 read_mem_dummy()
{
	return 0;
}

static void write_mem_dummy(u32 data)
{
	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value >>  8));
	sioWrite8((unsigned char)(value >> 16));
	sioWrite8((unsigned char)(value >> 24));
}

#if !defined(DRC_DBG) && defined(__arm__)

static void map_rcnt_rcount0(u32 mode)
{
	if (mode & 0x100) { // pixel clock
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	}
}

static void map_rcnt_rcount1(u32 mode)
{
	if (mode & 0x100) { // hcnt
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	}
}

static void map_rcnt_rcount2(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	}
	else if (mode & 0x200) { // clk/8
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	}
}

#else
#define map_rcnt_rcount0(mode)
#define map_rcnt_rcount1(mode)
#define map_rcnt_rcount2(mode)
#endif

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

static void io_write_ireg16(u32 value)
{
	psxHu16ref(0x1070) &= value;
}

static void io_write_imask16(u32 value)
{
	psxHu16ref(0x1074) = value;
	if (psxHu16ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_ireg32(u32 value)
{
	psxHu32ref(0x1070) &= value;
}

static void io_write_imask32(u32 value)
{
	psxHu32ref(0x1074) = value;
	if (psxHu32ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_dma_icr32(u32 value)
{
	u32 tmp = value & 0x00ff803f;
	tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	    || tmp & HW_DMA_ICR_BUS_ERROR) {
		if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
			psxHu32ref(0x1070) |= SWAP32(8);
		tmp |= HW_DMA_ICR_IRQ_SENT;
	}
	HW_DMA_ICR = SWAPu32(tmp);
}

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

static void io_spu_write16(u32 value)
{
	// meh
	SPU_writeRegister(address, value, psxRegs.cycle);
}

static void io_spu_write32(u32 value)
{
	SPUwriteRegister wfunc = SPU_writeRegister;
	u32 a = address;

	wfunc(a, value & 0xffff, psxRegs.cycle);
	wfunc(a + 2, value >> 16, psxRegs.cycle);
}

static u32 io_gpu_read_status(void)
{
	u32 v;

	// meh2, syncing for img bit, might want to avoid it..
	gpuSyncPluginSR();
	v = HW_GPU_STATUS;

	// XXX: because of large timeslices can't use hSyncCount, using rough
	// approximization instead. Perhaps better use hcounter code here or something.
	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
		v |= PSXGPU_LCF & (psxRegs.cycle << 20);
	return v;
}

static void io_gpu_write_status(u32 value)
{
	GPU_writeStatus(value);
	gpuSyncPluginSR();
}

static void map_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	}
}

static void unmap_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
	}
}

static void write_biu(u32 value)
{
	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);

	if (address != 0xfffe0130)
		return;

	switch (value) {
	case 0x800: case 0x804:
		unmap_ram_write();
		break;
	case 0: case 0x1e988:
		map_ram_write();
		break;
	default:
		printf("write_biu: unexpected val: %08x\n", value);
		break;
	}
}

void new_dyna_pcsx_mem_load_state(void)
{
	map_rcnt_rcount0(rcnts[0].mode);
	map_rcnt_rcount1(rcnts[1].mode);
	map_rcnt_rcount2(rcnts[2].mode);
}

int pcsxmem_is_handler_dynamic(unsigned int addr)
{
	if ((addr & 0xfffff000) != 0x1f801000)
		return 0;

	addr &= 0xffff;
	return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
}

void new_dyna_pcsx_mem_init(void)
{
	int i;

	// have to map these further to keep tcache close to .text
	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
	if (mem_readtab == NULL) {
		SysPrintf("failed to map mem tables\n");
		exit(1);
	}
	mem_writetab = mem_readtab + 0x100000;

	// 1st level lookup:
	//   0: direct mem
	//   1: use 2nd lookup
	// 2nd level lookup:
	//   0: direct mem variable
	//   1: memhandler

	// default/unmapped memhandlers
	for (i = 0; i < 0x100000; i++) {
		//map_item(&mem_readtab[i], mem_unmrtab, 1);
		map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
		map_item(&mem_writetab[i], mem_unmwtab, 1);
	}

	// RAM and it's mirrors
	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
	}
	map_ram_write();

	// BIOS and it's mirrors
	for (i = 0; i < (0x80000 >> 12); i++) {
		map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
		map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	}

	// scratchpad
	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);

	// I/O
	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);

	// L2
	// unmapped tables
	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
		map_item(&mem_unmwtab[i], write_mem_dummy, 1);

	// fill IO tables
	for (i = 0; i < 0x1000/4; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}

	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
//	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);

	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);

	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);

	// write(u32 data)
	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);

	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);

	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2) {
		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	}

	// misc
	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
		map_item(&mem_ffwtab[i], write_biu, 1);

	mem_rtab = mem_readtab;
	mem_wtab = mem_writetab;

	new_dyna_pcsx_mem_load_state();
}

void new_dyna_pcsx_mem_reset(void)
{
	int i;

	// plugins might change so update the pointers
	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2)
		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);

	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
}

void new_dyna_pcsx_mem_shutdown(void)
{
	psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
	mem_writetab = mem_readtab = NULL;
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include "../psxhw.h"
	10	#include "../cdrom.h"
	11	#include "../mdec.h"
ddbaf678	12	#include "../gpu.h"
87e5b45f	13	#include "../psxmem_map.h"
7e605697	14	#include "emu_if.h"
	15	#include "pcsxmem.h"
	16
5905989e	17	#ifdef __thumb__
9f704290	18	#error the dynarec is incompatible with Thumb functions,
9f704290	19	#error please add -marm to compile flags
5905989e	20	#endif
5905989e	21
7e605697	22	//#define memprintf printf
	23	#define memprintf(...)
	24
be516ebe	25	static uintptr_t *mem_readtab;
	26	static uintptr_t *mem_writetab;
	27	static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
	28	static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
	29	static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
	30	//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
	31	static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
	32
	33	static
578c6882	34	#ifdef __clang__
be516ebe	35	// When this is called in a loop, and 'h' is a function pointer, clang will crash.
be516ebe	36	__attribute__ ((noinline))
578c6882	37	#endif
be516ebe	38	void map_item(uintptr_t out, const void h, uintptr_t flag)
b1be1eee	39	{
be516ebe	40	uintptr_t hv = (uintptr_t)h;
5905989e	41	if (hv & 1) {
f29fbd53	42	SysPrintf("FATAL: %p has LSB set\n", h);
5905989e	43	abort();
5905989e	44	}
be516ebe	45	out = (hv >> 1) \| (flag << (sizeof(hv) 8 - 1));
b1be1eee	46	}
	47
	48	// size must be power of 2, at least 4k
	49	#define map_l1_mem(tab, i, addr, size, base) \
	50	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
	51
	52	#define IOMEM32(a) (((a) & 0xfff) / 4)
	53	#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
	54	#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
	55
054175e9	56	u8 zero_mem[0x1000];
7a481d40	57
63cb0298	58	u32 read_mem_dummy()
7e605697	59	{
63cb0298	60	return 0;
7e605697	61	}
7e605697	62
b96d3df7	63	static void write_mem_dummy(u32 data)
7e605697	64	{
b96d3df7	65	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
7e605697	66	}
7e605697	67
7e605697	68	/* IO handlers */
	69	static u32 io_read_sio16()
	70	{
	71	return sioRead8() \| (sioRead8() << 8);
	72	}
	73
	74	static u32 io_read_sio32()
	75	{
	76	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	77	}
	78
	79	static void io_write_sio16(u32 value)
	80	{
	81	sioWrite8((unsigned char)value);
	82	sioWrite8((unsigned char)(value>>8));
	83	}
	84
	85	static void io_write_sio32(u32 value)
	86	{
	87	sioWrite8((unsigned char)value);
b96d3df7	88	sioWrite8((unsigned char)(value >> 8));
	89	sioWrite8((unsigned char)(value >> 16));
	90	sioWrite8((unsigned char)(value >> 24));
7e605697	91	}
7e605697	92
be516ebe	93	#if !defined(DRC_DBG) && defined(__arm__)
19776aef	94
b1be1eee	95	static void map_rcnt_rcount0(u32 mode)
b1be1eee	96	{
59fb0bb4	97	if (mode & 0x100) { // pixel clock
b1be1eee	98	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
	99	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	100	}
	101	else {
	102	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
	103	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	104	}
	105	}
	106
	107	static void map_rcnt_rcount1(u32 mode)
	108	{
59fb0bb4	109	if (mode & 0x100) { // hcnt
b1be1eee	110	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
	111	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	112	}
	113	else {
	114	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
	115	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	116	}
	117	}
	118
	119	static void map_rcnt_rcount2(u32 mode)
	120	{
	121	if (mode & 0x01) { // gate
	122	map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
	123	map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	124	}
	125	else if (mode & 0x200) { // clk/8
	126	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
	127	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	128	}
	129	else {
	130	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
	131	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	132	}
	133	}
	134
19776aef	135	#else
	136	#define map_rcnt_rcount0(mode)
	137	#define map_rcnt_rcount1(mode)
	138	#define map_rcnt_rcount2(mode)
	139	#endif
	140
7e605697	141	#define make_rcnt_funcs(i) \
	142	static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
	143	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	144	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	145	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
b1be1eee	146	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
7e605697	147	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	148
	149	make_rcnt_funcs(0)
	150	make_rcnt_funcs(1)
	151	make_rcnt_funcs(2)
	152
	153	static void io_write_ireg16(u32 value)
	154	{
9705788a	155	psxHu16ref(0x1070) &= value;
7e605697	156	}
	157
	158	static void io_write_imask16(u32 value)
	159	{
	160	psxHu16ref(0x1074) = value;
	161	if (psxHu16ref(0x1070) & value)
d28b54b1	162	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	163	}
	164
	165	static void io_write_ireg32(u32 value)
	166	{
9705788a	167	psxHu32ref(0x1070) &= value;
7e605697	168	}
	169
	170	static void io_write_imask32(u32 value)
	171	{
	172	psxHu32ref(0x1074) = value;
	173	if (psxHu32ref(0x1070) & value)
d28b54b1	174	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	175	}
	176
	177	static void io_write_dma_icr32(u32 value)
	178	{
1f77c863	179	u32 tmp = value & 0x00ff803f;
	180	tmp \|= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	181	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	182	\|\| tmp & HW_DMA_ICR_BUS_ERROR) {
	183	if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
	184	psxHu32ref(0x1070) \|= SWAP32(8);
	185	tmp \|= HW_DMA_ICR_IRQ_SENT;
	186	}
	187	HW_DMA_ICR = SWAPu32(tmp);
7e605697	188	}
	189
	190	#define make_dma_func(n) \
	191	static void io_write_chcr##n(u32 value) \
	192	{ \
	193	HW_DMA##n##_CHCR = value; \
	194	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	195	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	196	} \
	197	}
	198
	199	make_dma_func(0)
	200	make_dma_func(1)
	201	make_dma_func(2)
	202	make_dma_func(3)
	203	make_dma_func(4)
	204	make_dma_func(6)
	205
b96d3df7	206	static void io_spu_write16(u32 value)
	207	{
	208	// meh
650adfd2	209	SPU_writeRegister(address, value, psxRegs.cycle);
b96d3df7	210	}
	211
	212	static void io_spu_write32(u32 value)
	213	{
	214	SPUwriteRegister wfunc = SPU_writeRegister;
	215	u32 a = address;
	216
650adfd2	217	wfunc(a, value & 0xffff, psxRegs.cycle);
650adfd2	218	wfunc(a + 2, value >> 16, psxRegs.cycle);
b96d3df7	219	}
b96d3df7	220
ddbaf678	221	static u32 io_gpu_read_status(void)
ddbaf678	222	{
0486fdc9	223	u32 v;
0486fdc9	224
ddbaf678	225	// meh2, syncing for img bit, might want to avoid it..
ddbaf678	226	gpuSyncPluginSR();
0486fdc9	227	v = HW_GPU_STATUS;
	228
	229	// XXX: because of large timeslices can't use hSyncCount, using rough
	230	// approximization instead. Perhaps better use hcounter code here or something.
	231	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
	232	v \|= PSXGPU_LCF & (psxRegs.cycle << 20);
	233	return v;
ddbaf678	234	}
	235
	236	static void io_gpu_write_status(u32 value)
	237	{
	238	GPU_writeStatus(value);
	239	gpuSyncPluginSR();
	240	}
	241
b96d3df7	242	static void map_ram_write(void)
	243	{
	244	int i;
	245
	246	for (i = 0; i < (0x800000 >> 12); i++) {
	247	map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
	248	map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
	249	map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	250	}
	251	}
	252
	253	static void unmap_ram_write(void)
	254	{
	255	int i;
	256
	257	for (i = 0; i < (0x800000 >> 12); i++) {
	258	map_item(&mem_writetab[0x80000\|i], mem_unmwtab, 1);
	259	map_item(&mem_writetab[0x00000\|i], mem_unmwtab, 1);
	260	map_item(&mem_writetab[0xa0000\|i], mem_unmwtab, 1);
	261	}
	262	}
	263
	264	static void write_biu(u32 value)
	265	{
	266	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
	267
	268	if (address != 0xfffe0130)
	269	return;
	270
	271	switch (value) {
	272	case 0x800: case 0x804:
	273	unmap_ram_write();
	274	break;
	275	case 0: case 0x1e988:
	276	map_ram_write();
	277	break;
	278	default:
	279	printf("write_biu: unexpected val: %08x\n", value);
	280	break;
	281	}
	282	}
	283
b1be1eee	284	void new_dyna_pcsx_mem_load_state(void)
	285	{
	286	map_rcnt_rcount0(rcnts[0].mode);
	287	map_rcnt_rcount1(rcnts[1].mode);
	288	map_rcnt_rcount2(rcnts[2].mode);
	289	}
	290
003cfc63	291	int pcsxmem_is_handler_dynamic(unsigned int addr)
b1be1eee	292	{
	293	if ((addr & 0xfffff000) != 0x1f801000)
	294	return 0;
	295
	296	addr &= 0xffff;
	297	return addr == 0x1100 \|\| addr == 0x1110 \|\| addr == 0x1120;
	298	}
	299
7e605697	300	void new_dyna_pcsx_mem_init(void)
	301	{
	302	int i;
63cb0298	303
c6c3b1b3	304	// have to map these further to keep tcache close to .text
be516ebe	305	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
87e5b45f	306	if (mem_readtab == NULL) {
f29fbd53	307	SysPrintf("failed to map mem tables\n");
c6c3b1b3	308	exit(1);
	309	}
	310	mem_writetab = mem_readtab + 0x100000;
	311
	312	// 1st level lookup:
	313	// 0: direct mem
	314	// 1: use 2nd lookup
	315	// 2nd level lookup:
	316	// 0: direct mem variable
	317	// 1: memhandler
	318
	319	// default/unmapped memhandlers
	320	for (i = 0; i < 0x100000; i++) {
	321	//map_item(&mem_readtab[i], mem_unmrtab, 1);
054175e9	322	map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
c6c3b1b3	323	map_item(&mem_writetab[i], mem_unmwtab, 1);
	324	}
	325
	326	// RAM and it's mirrors
	327	for (i = 0; i < (0x800000 >> 12); i++) {
	328	map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
c6c3b1b3	329	map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
c6c3b1b3	330	map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
c6c3b1b3	331	}
b96d3df7	332	map_ram_write();
c6c3b1b3	333
	334	// BIOS and it's mirrors
	335	for (i = 0; i < (0x80000 >> 12); i++) {
	336	map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
	337	map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	338	}
	339
	340	// scratchpad
	341	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	342	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	343	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	344	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	345
	346	// I/O
	347	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
9dd7d179	348	map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
9dd7d179	349	map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
c6c3b1b3	350	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
9dd7d179	351	map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
9dd7d179	352	map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);
7e605697	353
c6c3b1b3	354	// L2
c6c3b1b3	355	// unmapped tables
b96d3df7	356	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
c6c3b1b3	357	map_item(&mem_unmwtab[i], write_mem_dummy, 1);
	358
	359	// fill IO tables
	360	for (i = 0; i < 0x1000/4; i++) {
	361	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	362	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	363	}
	364	for (; i < 0x1000/4 + 0x1000/2; i++) {
	365	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	366	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	367	}
	368	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	369	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	370	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	371	}
	372
	373	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	374	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	375	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	376	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	377	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	378	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	379	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	380	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	381	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	382	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
	383	// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
ddbaf678	384	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
c6c3b1b3	385	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	386	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
	387
	388	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	389	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	390	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	391	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	392	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	393	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	394	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	395	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	396	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	397	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	398	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	399	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	400	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	401	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
	402
	403	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	404	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	405	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	406	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	407	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
	408
b96d3df7	409	// write(u32 data)
	410	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	411	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	412	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	413	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	414	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	415	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	416	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	417	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	418	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	419	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	420	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	421	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	422	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	423	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	424	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	425	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	426	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	427	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	428	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
	429	// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
ddbaf678	430	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
b96d3df7	431	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	432	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
	433
	434	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	435	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	436	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	437	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	438	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	439	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	440	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	441	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	442	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	443	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	444	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	445	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	446	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	447	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	448	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	449	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
	450
	451	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	452	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	453	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	454	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	455	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
	456
	457	for (i = 0x1c00; i < 0x1e00; i += 2) {
	458	map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
	459	map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	460	}
	461
	462	// misc
	463	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	464	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
	465	map_item(&mem_ffwtab[i], write_biu, 1);
	466
c6c3b1b3	467	mem_rtab = mem_readtab;
c6c3b1b3	468	mem_wtab = mem_writetab;
b1be1eee	469
b1be1eee	470	new_dyna_pcsx_mem_load_state();
7e605697	471	}
	472
	473	void new_dyna_pcsx_mem_reset(void)
	474	{
c6c3b1b3	475	int i;
c6c3b1b3	476
7e605697	477	// plugins might change so update the pointers
c6c3b1b3	478	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
c6c3b1b3	479
	480	for (i = 0x1c00; i < 0x1e00; i += 2)
	481	map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
	482
b96d3df7	483	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
7e605697	484	}
92879b62	485
	486	void new_dyna_pcsx_mem_shutdown(void)
	487	{
	488	psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
	489	mem_writetab = mem_readtab = NULL;
	490	}