[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "../gpu.h"
#include "../psxmem_map.h"
#include "emu_if.h"
#include "pcsxmem.h"

#ifdef __thumb__
#error the dynarec is incompatible with Thumb functions,
#error please add -marm to compile flags
#endif

//#define memprintf printf
#define memprintf(...)

static uintptr_t *mem_readtab;
static uintptr_t *mem_writetab;
static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];

static
#ifdef __clang__
// When this is called in a loop, and 'h' is a function pointer, clang will crash.
__attribute__ ((noinline))
#endif
void map_item(uintptr_t *out, const void *h, uintptr_t flag)
{
	uintptr_t hv = (uintptr_t)h;
	if (hv & 1) {
		SysPrintf("FATAL: %p has LSB set\n", h);
		abort();
	}
	*out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
}

// size must be power of 2, at least 4k
#define map_l1_mem(tab, i, addr, size, base) \
	map_item(&tab[((addr)>>12) + i], \
		 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)

#define IOMEM32(a) (((a) & 0xfff) / 4)
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))

u8 zero_mem[0x1000];

u32 read_mem_dummy()
{
	return 0;
}

static void write_mem_dummy(u32 data)
{
	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value >>  8));
	sioWrite8((unsigned char)(value >> 16));
	sioWrite8((unsigned char)(value >> 24));
}

#if !defined(DRC_DBG) && defined(__arm__)

static void map_rcnt_rcount0(u32 mode)
{
	if (mode & 0x100) { // pixel clock
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	}
}

static void map_rcnt_rcount1(u32 mode)
{
	if (mode & 0x100) { // hcnt
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	}
}

static void map_rcnt_rcount2(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	}
	else if (mode & 0x200) { // clk/8
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	}
}

#else
#define map_rcnt_rcount0(mode)
#define map_rcnt_rcount1(mode)
#define map_rcnt_rcount2(mode)
#endif

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

static void io_write_ireg16(u32 value)
{
	psxHu16ref(0x1070) &= value;
}

static void io_write_imask16(u32 value)
{
	psxHu16ref(0x1074) = value;
	if (psxHu16ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_ireg32(u32 value)
{
	psxHu32ref(0x1070) &= value;
}

static void io_write_imask32(u32 value)
{
	psxHu32ref(0x1074) = value;
	if (psxHu32ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_dma_icr32(u32 value)
{
	u32 tmp = value & 0x00ff803f;
	tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	    || tmp & HW_DMA_ICR_BUS_ERROR) {
		if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
			psxHu32ref(0x1070) |= SWAP32(8);
		tmp |= HW_DMA_ICR_IRQ_SENT;
	}
	HW_DMA_ICR = SWAPu32(tmp);
}

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

static void io_spu_write16(u32 value)
{
	// meh
	SPU_writeRegister(address, value, psxRegs.cycle);
}

static void io_spu_write32(u32 value)
{
	SPUwriteRegister wfunc = SPU_writeRegister;
	u32 a = address;

	wfunc(a, value & 0xffff, psxRegs.cycle);
	wfunc(a + 2, value >> 16, psxRegs.cycle);
}

static u32 io_gpu_read_status(void)
{
	u32 v;

	// meh2, syncing for img bit, might want to avoid it..
	gpuSyncPluginSR();
	v = HW_GPU_STATUS;

	// XXX: because of large timeslices can't use hSyncCount, using rough
	// approximization instead. Perhaps better use hcounter code here or something.
	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
		v |= PSXGPU_LCF & (psxRegs.cycle << 20);
	return v;
}

static void io_gpu_write_status(u32 value)
{
	GPU_writeStatus(value);
	gpuSyncPluginSR();
}

static void map_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	}
}

static void unmap_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
	}
}

static void write_biu(u32 value)
{
	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);

	if (address != 0xfffe0130)
		return;

	switch (value) {
	case 0x800: case 0x804:
		unmap_ram_write();
		break;
	case 0: case 0x1e988:
		map_ram_write();
		break;
	default:
		printf("write_biu: unexpected val: %08x\n", value);
		break;
	}
}

void new_dyna_pcsx_mem_load_state(void)
{
	map_rcnt_rcount0(rcnts[0].mode);
	map_rcnt_rcount1(rcnts[1].mode);
	map_rcnt_rcount2(rcnts[2].mode);
}

int pcsxmem_is_handler_dynamic(unsigned int addr)
{
	if ((addr & 0xfffff000) != 0x1f801000)
		return 0;

	addr &= 0xffff;
	return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
}

void new_dyna_pcsx_mem_init(void)
{
	int i;

	// have to map these further to keep tcache close to .text
	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
	if (mem_readtab == NULL) {
		SysPrintf("failed to map mem tables\n");
		exit(1);
	}
	mem_writetab = mem_readtab + 0x100000;

	// 1st level lookup:
	//   0: direct mem
	//   1: use 2nd lookup
	// 2nd level lookup:
	//   0: direct mem variable
	//   1: memhandler

	// default/unmapped memhandlers
	for (i = 0; i < 0x100000; i++) {
		//map_item(&mem_readtab[i], mem_unmrtab, 1);
		map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
		map_item(&mem_writetab[i], mem_unmwtab, 1);
	}

	// RAM and it's mirrors
	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
	}
	map_ram_write();

	// BIOS and it's mirrors
	for (i = 0; i < (0x80000 >> 12); i++) {
		map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
		map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	}

	// scratchpad
	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);

	// I/O
	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);

	// L2
	// unmapped tables
	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
		map_item(&mem_unmwtab[i], write_mem_dummy, 1);

	// fill IO tables
	for (i = 0; i < 0x1000/4; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}

	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
//	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);

	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);

	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);

	// write(u32 data)
	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);

	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);

	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2) {
		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	}

	// misc
	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
		map_item(&mem_ffwtab[i], write_biu, 1);

	mem_rtab = mem_readtab;
	mem_wtab = mem_writetab;

	new_dyna_pcsx_mem_load_state();
}

void new_dyna_pcsx_mem_reset(void)
{
	int i;

	// plugins might change so update the pointers
	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2)
		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);

	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
}

void new_dyna_pcsx_mem_shutdown(void)
{
	psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
	mem_writetab = mem_readtab = NULL;
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include "../psxhw.h"
	10	#include "../cdrom.h"
	11	#include "../mdec.h"
ddbaf678	12	#include "../gpu.h"
87e5b45f	13	#include "../psxmem_map.h"
7e605697	14	#include "emu_if.h"
	15	#include "pcsxmem.h"
	16
5905989e	17	#ifdef __thumb__
9f704290	18	#error the dynarec is incompatible with Thumb functions,
9f704290	19	#error please add -marm to compile flags
5905989e	20	#endif
5905989e	21
7e605697	22	//#define memprintf printf
	23	#define memprintf(...)
	24
be516ebe	25	static uintptr_t *mem_readtab;
	26	static uintptr_t *mem_writetab;
	27	static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
	28	static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
	29	static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
	30	//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
	31	static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
	32
	33	static
578c6882	34	#ifdef __clang__
be516ebe	35	// When this is called in a loop, and 'h' is a function pointer, clang will crash.
be516ebe	36	__attribute__ ((noinline))
578c6882	37	#endif
be516ebe	38	void map_item(uintptr_t out, const void h, uintptr_t flag)
b1be1eee	39	{
be516ebe	40	uintptr_t hv = (uintptr_t)h;
5905989e	41	if (hv & 1) {
f29fbd53	42	SysPrintf("FATAL: %p has LSB set\n", h);
5905989e	43	abort();
5905989e	44	}
be516ebe	45	out = (hv >> 1) \| (flag << (sizeof(hv) 8 - 1));
b1be1eee	46	}
	47
	48	// size must be power of 2, at least 4k
	49	#define map_l1_mem(tab, i, addr, size, base) \
e3973c69	50	map_item(&tab[((addr)>>12) + i], \
e3973c69	51	(u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
b1be1eee	52
	53	#define IOMEM32(a) (((a) & 0xfff) / 4)
	54	#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
	55	#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
	56
054175e9	57	u8 zero_mem[0x1000];
7a481d40	58
63cb0298	59	u32 read_mem_dummy()
7e605697	60	{
63cb0298	61	return 0;
7e605697	62	}
7e605697	63
b96d3df7	64	static void write_mem_dummy(u32 data)
7e605697	65	{
b96d3df7	66	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
7e605697	67	}
7e605697	68
7e605697	69	/* IO handlers */
	70	static u32 io_read_sio16()
	71	{
	72	return sioRead8() \| (sioRead8() << 8);
	73	}
	74
	75	static u32 io_read_sio32()
	76	{
	77	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	78	}
	79
	80	static void io_write_sio16(u32 value)
	81	{
	82	sioWrite8((unsigned char)value);
	83	sioWrite8((unsigned char)(value>>8));
	84	}
	85
	86	static void io_write_sio32(u32 value)
	87	{
	88	sioWrite8((unsigned char)value);
b96d3df7	89	sioWrite8((unsigned char)(value >> 8));
	90	sioWrite8((unsigned char)(value >> 16));
	91	sioWrite8((unsigned char)(value >> 24));
7e605697	92	}
7e605697	93
be516ebe	94	#if !defined(DRC_DBG) && defined(__arm__)
19776aef	95
b1be1eee	96	static void map_rcnt_rcount0(u32 mode)
b1be1eee	97	{
59fb0bb4	98	if (mode & 0x100) { // pixel clock
b1be1eee	99	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
	100	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	101	}
	102	else {
	103	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
	104	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	105	}
	106	}
	107
	108	static void map_rcnt_rcount1(u32 mode)
	109	{
59fb0bb4	110	if (mode & 0x100) { // hcnt
b1be1eee	111	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
	112	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	113	}
	114	else {
	115	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
	116	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	117	}
	118	}
	119
	120	static void map_rcnt_rcount2(u32 mode)
	121	{
	122	if (mode & 0x01) { // gate
	123	map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
	124	map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	125	}
	126	else if (mode & 0x200) { // clk/8
	127	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
	128	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	129	}
	130	else {
	131	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
	132	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	133	}
	134	}
	135
19776aef	136	#else
	137	#define map_rcnt_rcount0(mode)
	138	#define map_rcnt_rcount1(mode)
	139	#define map_rcnt_rcount2(mode)
	140	#endif
	141
7e605697	142	#define make_rcnt_funcs(i) \
	143	static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
	144	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	145	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	146	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
b1be1eee	147	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
7e605697	148	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	149
	150	make_rcnt_funcs(0)
	151	make_rcnt_funcs(1)
	152	make_rcnt_funcs(2)
	153
	154	static void io_write_ireg16(u32 value)
	155	{
9705788a	156	psxHu16ref(0x1070) &= value;
7e605697	157	}
	158
	159	static void io_write_imask16(u32 value)
	160	{
	161	psxHu16ref(0x1074) = value;
	162	if (psxHu16ref(0x1070) & value)
d28b54b1	163	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	164	}
	165
	166	static void io_write_ireg32(u32 value)
	167	{
9705788a	168	psxHu32ref(0x1070) &= value;
7e605697	169	}
	170
	171	static void io_write_imask32(u32 value)
	172	{
	173	psxHu32ref(0x1074) = value;
	174	if (psxHu32ref(0x1070) & value)
d28b54b1	175	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	176	}
	177
	178	static void io_write_dma_icr32(u32 value)
	179	{
1f77c863	180	u32 tmp = value & 0x00ff803f;
	181	tmp \|= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	182	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	183	\|\| tmp & HW_DMA_ICR_BUS_ERROR) {
	184	if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
	185	psxHu32ref(0x1070) \|= SWAP32(8);
	186	tmp \|= HW_DMA_ICR_IRQ_SENT;
	187	}
	188	HW_DMA_ICR = SWAPu32(tmp);
7e605697	189	}
	190
	191	#define make_dma_func(n) \
	192	static void io_write_chcr##n(u32 value) \
	193	{ \
	194	HW_DMA##n##_CHCR = value; \
	195	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	196	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	197	} \
	198	}
	199
	200	make_dma_func(0)
	201	make_dma_func(1)
	202	make_dma_func(2)
	203	make_dma_func(3)
	204	make_dma_func(4)
	205	make_dma_func(6)
	206
b96d3df7	207	static void io_spu_write16(u32 value)
	208	{
	209	// meh
650adfd2	210	SPU_writeRegister(address, value, psxRegs.cycle);
b96d3df7	211	}
	212
	213	static void io_spu_write32(u32 value)
	214	{
	215	SPUwriteRegister wfunc = SPU_writeRegister;
	216	u32 a = address;
	217
650adfd2	218	wfunc(a, value & 0xffff, psxRegs.cycle);
650adfd2	219	wfunc(a + 2, value >> 16, psxRegs.cycle);
b96d3df7	220	}
b96d3df7	221
ddbaf678	222	static u32 io_gpu_read_status(void)
ddbaf678	223	{
0486fdc9	224	u32 v;
0486fdc9	225
ddbaf678	226	// meh2, syncing for img bit, might want to avoid it..
ddbaf678	227	gpuSyncPluginSR();
0486fdc9	228	v = HW_GPU_STATUS;
	229
	230	// XXX: because of large timeslices can't use hSyncCount, using rough
	231	// approximization instead. Perhaps better use hcounter code here or something.
	232	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
	233	v \|= PSXGPU_LCF & (psxRegs.cycle << 20);
	234	return v;
ddbaf678	235	}
	236
	237	static void io_gpu_write_status(u32 value)
	238	{
	239	GPU_writeStatus(value);
	240	gpuSyncPluginSR();
	241	}
	242
b96d3df7	243	static void map_ram_write(void)
	244	{
	245	int i;
	246
	247	for (i = 0; i < (0x800000 >> 12); i++) {
	248	map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
	249	map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
	250	map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	251	}
	252	}
	253
	254	static void unmap_ram_write(void)
	255	{
	256	int i;
	257
	258	for (i = 0; i < (0x800000 >> 12); i++) {
	259	map_item(&mem_writetab[0x80000\|i], mem_unmwtab, 1);
	260	map_item(&mem_writetab[0x00000\|i], mem_unmwtab, 1);
	261	map_item(&mem_writetab[0xa0000\|i], mem_unmwtab, 1);
	262	}
	263	}
	264
	265	static void write_biu(u32 value)
	266	{
	267	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
	268
	269	if (address != 0xfffe0130)
	270	return;
	271
	272	switch (value) {
	273	case 0x800: case 0x804:
	274	unmap_ram_write();
	275	break;
	276	case 0: case 0x1e988:
	277	map_ram_write();
	278	break;
	279	default:
	280	printf("write_biu: unexpected val: %08x\n", value);
	281	break;
	282	}
	283	}
	284
b1be1eee	285	void new_dyna_pcsx_mem_load_state(void)
	286	{
	287	map_rcnt_rcount0(rcnts[0].mode);
	288	map_rcnt_rcount1(rcnts[1].mode);
	289	map_rcnt_rcount2(rcnts[2].mode);
	290	}
	291
003cfc63	292	int pcsxmem_is_handler_dynamic(unsigned int addr)
b1be1eee	293	{
	294	if ((addr & 0xfffff000) != 0x1f801000)
	295	return 0;
	296
	297	addr &= 0xffff;
	298	return addr == 0x1100 \|\| addr == 0x1110 \|\| addr == 0x1120;
	299	}
	300
7e605697	301	void new_dyna_pcsx_mem_init(void)
	302	{
	303	int i;
63cb0298	304
c6c3b1b3	305	// have to map these further to keep tcache close to .text
be516ebe	306	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
87e5b45f	307	if (mem_readtab == NULL) {
f29fbd53	308	SysPrintf("failed to map mem tables\n");
c6c3b1b3	309	exit(1);
	310	}
	311	mem_writetab = mem_readtab + 0x100000;
	312
	313	// 1st level lookup:
	314	// 0: direct mem
	315	// 1: use 2nd lookup
	316	// 2nd level lookup:
	317	// 0: direct mem variable
	318	// 1: memhandler
	319
	320	// default/unmapped memhandlers
	321	for (i = 0; i < 0x100000; i++) {
	322	//map_item(&mem_readtab[i], mem_unmrtab, 1);
054175e9	323	map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
c6c3b1b3	324	map_item(&mem_writetab[i], mem_unmwtab, 1);
	325	}
	326
	327	// RAM and it's mirrors
	328	for (i = 0; i < (0x800000 >> 12); i++) {
	329	map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
c6c3b1b3	330	map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
c6c3b1b3	331	map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
c6c3b1b3	332	}
b96d3df7	333	map_ram_write();
c6c3b1b3	334
	335	// BIOS and it's mirrors
	336	for (i = 0; i < (0x80000 >> 12); i++) {
	337	map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
	338	map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	339	}
	340
	341	// scratchpad
	342	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	343	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	344	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	345	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	346
	347	// I/O
	348	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
9dd7d179	349	map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
9dd7d179	350	map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
c6c3b1b3	351	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
9dd7d179	352	map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
9dd7d179	353	map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);
7e605697	354
c6c3b1b3	355	// L2
c6c3b1b3	356	// unmapped tables
b96d3df7	357	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
c6c3b1b3	358	map_item(&mem_unmwtab[i], write_mem_dummy, 1);
	359
	360	// fill IO tables
	361	for (i = 0; i < 0x1000/4; i++) {
	362	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	363	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	364	}
	365	for (; i < 0x1000/4 + 0x1000/2; i++) {
	366	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	367	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	368	}
	369	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	370	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	371	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	372	}
	373
	374	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	375	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	376	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	377	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	378	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	379	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	380	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	381	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	382	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	383	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
	384	// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
ddbaf678	385	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
c6c3b1b3	386	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	387	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
	388
	389	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	390	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	391	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	392	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	393	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	394	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	395	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	396	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	397	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	398	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	399	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	400	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	401	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	402	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
	403
	404	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	405	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	406	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	407	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	408	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
	409
b96d3df7	410	// write(u32 data)
	411	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	412	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	413	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	414	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	415	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	416	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	417	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	418	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	419	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	420	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	421	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	422	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	423	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	424	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	425	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	426	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	427	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	428	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	429	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
	430	// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
ddbaf678	431	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
b96d3df7	432	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	433	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
	434
	435	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	436	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	437	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	438	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	439	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	440	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	441	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	442	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	443	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	444	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	445	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	446	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	447	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	448	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	449	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	450	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
	451
	452	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	453	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	454	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	455	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	456	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
	457
	458	for (i = 0x1c00; i < 0x1e00; i += 2) {
	459	map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
	460	map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	461	}
	462
	463	// misc
	464	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	465	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
	466	map_item(&mem_ffwtab[i], write_biu, 1);
	467
c6c3b1b3	468	mem_rtab = mem_readtab;
c6c3b1b3	469	mem_wtab = mem_writetab;
b1be1eee	470
b1be1eee	471	new_dyna_pcsx_mem_load_state();
7e605697	472	}
	473
	474	void new_dyna_pcsx_mem_reset(void)
	475	{
c6c3b1b3	476	int i;
c6c3b1b3	477
7e605697	478	// plugins might change so update the pointers
c6c3b1b3	479	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
c6c3b1b3	480
	481	for (i = 0x1c00; i < 0x1e00; i += 2)
	482	map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
	483
b96d3df7	484	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
7e605697	485	}
92879b62	486
	487	void new_dyna_pcsx_mem_shutdown(void)
	488	{
	489	psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
	490	mem_writetab = mem_readtab = NULL;
	491	}