e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
44e6452e |
3 | * |
4 | * notes: |
5 | * - tcache, block descriptor, link buffer overflows result in sh2_translate() |
6 | * failure, followed by full tcache invalidation for that region |
7 | * - jumps between blocks are tracked for SMC handling (in block_links[]) |
e898de13 |
8 | */ |
f0d7b1fa |
9 | #include <stddef.h> |
679af8a3 |
10 | #include <stdio.h> |
11 | #include <stdlib.h> |
12 | #include <assert.h> |
41397701 |
13 | |
f4bb5d6b |
14 | #include "../../pico/pico_int.h" |
679af8a3 |
15 | #include "sh2.h" |
16 | #include "compiler.h" |
17 | #include "../drc/cmn.h" |
18 | |
8796b7ee |
19 | // debug stuff { |
e898de13 |
20 | #ifndef DRC_DEBUG |
21 | #define DRC_DEBUG 0 |
22 | #endif |
23 | |
553c3eaa |
24 | #if DRC_DEBUG |
f4bb5d6b |
25 | #define dbg(l,...) { \ |
26 | if ((l) & DRC_DEBUG) \ |
27 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
28 | } |
29 | |
e898de13 |
30 | #include "mame/sh2dasm.h" |
31 | #include <platform/linux/host_dasm.h> |
32 | static int insns_compiled, hash_collisions, host_insn_count; |
553c3eaa |
33 | #define COUNT_OP \ |
34 | host_insn_count++ |
35 | #else // !DRC_DEBUG |
36 | #define COUNT_OP |
37 | #define dbg(...) |
e898de13 |
38 | #endif |
553c3eaa |
39 | |
e898de13 |
40 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
41 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
42 | static char sh2dasm_buff[64]; |
f4bb5d6b |
43 | #define do_host_disasm(tcid) \ |
44 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
45 | tcache_dsm_ptrs[tcid] = tcache_ptr |
46 | #else |
47 | #define do_host_disasm(x) |
e898de13 |
48 | #endif |
e05b81fc |
49 | |
50 | #if (DRC_DEBUG & 4) |
51 | static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr) |
52 | { |
53 | if (block != NULL) |
54 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
55 | sh2->pc, block, (signed int)sr >> 12); |
56 | return block; |
57 | } |
58 | #endif |
8796b7ee |
59 | // } debug |
e898de13 |
60 | |
679af8a3 |
61 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
62 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
44e6452e |
63 | #define TCACHE_BUFFERS 3 |
f4bb5d6b |
64 | |
65 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
66 | // BIOS shares tcache with data array because it's only used for init |
67 | // and can be discarded early |
8796b7ee |
68 | // XXX: need to tune sizes |
44e6452e |
69 | static const int tcache_sizes[TCACHE_BUFFERS] = { |
f4bb5d6b |
70 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
71 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
72 | DRC_TCACHE_SIZE / 8, // ... slave |
73 | }; |
679af8a3 |
74 | |
44e6452e |
75 | static u8 *tcache_bases[TCACHE_BUFFERS]; |
76 | static u8 *tcache_ptrs[TCACHE_BUFFERS]; |
f4bb5d6b |
77 | |
78 | // ptr for code emiters |
79 | static u8 *tcache_ptr; |
e898de13 |
80 | |
44e6452e |
81 | typedef struct block_desc_ { |
82 | u32 addr; // SH2 PC address |
83 | u32 end_addr; // TODO rm? |
84 | void *tcache_ptr; // translated block for above PC |
85 | struct block_desc_ *next; // next block with the same PC hash |
86 | #if (DRC_DEBUG & 1) |
87 | int refcount; |
88 | #endif |
89 | } block_desc; |
90 | |
91 | typedef struct block_link_ { |
92 | u32 target_pc; |
93 | void *jump; |
94 | // struct block_link_ *next; |
95 | } block_link; |
96 | |
97 | static const int block_max_counts[TCACHE_BUFFERS] = { |
98 | 4*1024, |
99 | 256, |
100 | 256, |
101 | }; |
102 | static block_desc *block_tables[TCACHE_BUFFERS]; |
103 | static block_link *block_links[TCACHE_BUFFERS]; |
104 | static int block_counts[TCACHE_BUFFERS]; |
105 | static int block_link_counts[TCACHE_BUFFERS]; |
106 | |
c18edb34 |
107 | // host register tracking |
108 | enum { |
109 | HR_FREE, |
110 | HR_CACHED, // 'val' has sh2_reg_e |
111 | HR_CACHED_DIRTY, |
112 | HR_CONST, // 'val' has constant |
113 | HR_TEMP, // reg used for temp storage |
114 | }; |
115 | |
116 | typedef struct { |
117 | u8 reg; |
118 | u8 type; |
119 | u16 stamp; // kind of a timestamp |
120 | u32 val; |
121 | } temp_reg_t; |
122 | |
80599a42 |
123 | // note: reg_temp[] must have at least the amount of |
3863edbd |
124 | // registers used by handlers in worst case (currently 4) |
65c75cb0 |
125 | #ifdef ARM |
126 | #include "../drc/emit_arm.c" |
127 | |
128 | static const int reg_map_g2h[] = { |
8b4f38f4 |
129 | 4, 5, 6, 7, |
130 | 8, -1, -1, -1, |
c18edb34 |
131 | -1, -1, -1, -1, |
8b4f38f4 |
132 | -1, -1, -1, 9, |
133 | -1, -1, -1, 10, |
c18edb34 |
134 | -1, -1, -1, -1, |
135 | }; |
136 | |
137 | static temp_reg_t reg_temp[] = { |
138 | { 0, }, |
139 | { 1, }, |
140 | { 12, }, |
141 | { 14, }, |
142 | { 2, }, |
143 | { 3, }, |
65c75cb0 |
144 | }; |
145 | |
e05b81fc |
146 | #elif defined(__i386__) |
e898de13 |
147 | #include "../drc/emit_x86.c" |
148 | |
65c75cb0 |
149 | static const int reg_map_g2h[] = { |
8b4f38f4 |
150 | xSI,-1, -1, -1, |
c18edb34 |
151 | -1, -1, -1, -1, |
152 | -1, -1, -1, -1, |
153 | -1, -1, -1, -1, |
8b4f38f4 |
154 | -1, -1, -1, xDI, |
c18edb34 |
155 | -1, -1, -1, -1, |
156 | }; |
157 | |
3863edbd |
158 | // ax, cx, dx are usually temporaries by convention |
c18edb34 |
159 | static temp_reg_t reg_temp[] = { |
160 | { xAX, }, |
3863edbd |
161 | { xBX, }, |
c18edb34 |
162 | { xCX, }, |
163 | { xDX, }, |
65c75cb0 |
164 | }; |
165 | |
e05b81fc |
166 | #else |
167 | #error unsupported arch |
65c75cb0 |
168 | #endif |
169 | |
80599a42 |
170 | #define T 0x00000001 |
171 | #define S 0x00000002 |
172 | #define I 0x000000f0 |
173 | #define Q 0x00000100 |
174 | #define M 0x00000200 |
18b94127 |
175 | #define T_save 0x00000800 |
80599a42 |
176 | |
e05b81fc |
177 | #define I_SHIFT 4 |
f0d7b1fa |
178 | #define Q_SHIFT 8 |
179 | #define M_SHIFT 9 |
180 | |
f4bb5d6b |
181 | // ROM hash table |
679af8a3 |
182 | #define MAX_HASH_ENTRIES 1024 |
183 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
184 | static void **hash_table; |
679af8a3 |
185 | |
18b94127 |
186 | #define HASH_FUNC(hash_tab, addr) \ |
187 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
188 | |
e05b81fc |
189 | static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2); |
190 | static void (*sh2_drc_dispatcher)(void); |
191 | static void (*sh2_drc_exit)(void); |
192 | static void (*sh2_drc_test_irq)(void); |
193 | static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d); |
194 | static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d); |
195 | static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); |
196 | static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d); |
679af8a3 |
197 | |
553c3eaa |
198 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
679af8a3 |
199 | |
f4bb5d6b |
200 | static void flush_tcache(int tcid) |
201 | { |
553c3eaa |
202 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
f4bb5d6b |
203 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
204 | block_counts[tcid], block_max_counts[tcid]); |
205 | |
206 | block_counts[tcid] = 0; |
207 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
208 | if (tcid == 0) { // ROM, RAM |
209 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
210 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
211 | } |
212 | else |
213 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
214 | #if (DRC_DEBUG & 2) |
215 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
216 | #endif |
217 | } |
218 | |
44e6452e |
219 | // add block links (tracked branches) |
220 | static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id) |
221 | { |
222 | block_link *bl = block_links[tcache_id]; |
223 | int cnt = block_link_counts[tcache_id]; |
224 | |
225 | if (cnt >= block_max_counts[tcache_id] * 2) { |
226 | printf("bl overflow for tcache %d\n", tcache_id); |
227 | return -1; |
228 | } |
229 | |
230 | bl[cnt].target_pc = target_pc; |
231 | bl[cnt].jump = jump; |
232 | block_link_counts[tcache_id]++; |
233 | |
234 | return 0; |
235 | } |
236 | |
679af8a3 |
237 | static void *dr_find_block(block_desc *tab, u32 addr) |
238 | { |
239 | for (tab = tab->next; tab != NULL; tab = tab->next) |
240 | if (tab->addr == addr) |
241 | break; |
242 | |
243 | if (tab != NULL) |
244 | return tab->tcache_ptr; |
245 | |
246 | printf("block miss for %08x\n", addr); |
247 | return NULL; |
248 | } |
249 | |
f4bb5d6b |
250 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
679af8a3 |
251 | { |
f4bb5d6b |
252 | int *bcount = &block_counts[tcache_id]; |
679af8a3 |
253 | block_desc *bd; |
254 | |
44e6452e |
255 | if (*bcount >= block_max_counts[tcache_id]) { |
256 | printf("bd overflow for tcache %d\n", tcache_id); |
f4bb5d6b |
257 | return NULL; |
44e6452e |
258 | } |
679af8a3 |
259 | |
f4bb5d6b |
260 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
261 | bd->addr = addr; |
262 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
263 | *blk_id = *bcount; |
264 | (*bcount)++; |
679af8a3 |
265 | |
18b94127 |
266 | if ((addr & 0xc6000000) == 0x02000000) { // ROM |
267 | bd->next = HASH_FUNC(hash_table, addr); |
268 | HASH_FUNC(hash_table, addr) = bd; |
269 | #if (DRC_DEBUG & 1) |
270 | if (bd->next != NULL) { |
271 | printf(" hash collision with %08x\n", bd->next->addr); |
272 | hash_collisions++; |
273 | } |
274 | #endif |
275 | } |
276 | |
679af8a3 |
277 | return bd; |
278 | } |
279 | |
44e6452e |
280 | #define ADD_TO_ARRAY(array, count, item, failcode) \ |
281 | array[count++] = item; \ |
282 | if (count >= ARRAY_SIZE(array)) { \ |
283 | printf("warning: " #array " overflow\n"); \ |
284 | failcode; \ |
285 | } |
286 | |
18b94127 |
287 | int find_in_array(u32 *array, size_t size, u32 what) |
288 | { |
289 | size_t i; |
290 | for (i = 0; i < size; i++) |
291 | if (what == array[i]) |
292 | return i; |
293 | |
294 | return -1; |
295 | } |
679af8a3 |
296 | |
297 | // --------------------------------------------------------------- |
298 | |
c18edb34 |
299 | // register chache |
300 | static u16 rcache_counter; |
301 | |
302 | static temp_reg_t *rcache_evict(void) |
41397701 |
303 | { |
c18edb34 |
304 | // evict reg with oldest stamp |
305 | int i, oldest = -1; |
306 | u16 min_stamp = (u16)-1; |
307 | |
308 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
309 | if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) |
310 | if (reg_temp[i].stamp <= min_stamp) { |
311 | min_stamp = reg_temp[i].stamp; |
312 | oldest = i; |
313 | } |
314 | } |
315 | |
316 | if (oldest == -1) { |
80599a42 |
317 | printf("no registers to evict, aborting\n"); |
c18edb34 |
318 | exit(1); |
319 | } |
320 | |
321 | i = oldest; |
322 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
323 | // writeback |
324 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
325 | } |
326 | |
327 | return ®_temp[i]; |
679af8a3 |
328 | } |
329 | |
c18edb34 |
330 | typedef enum { |
331 | RC_GR_READ, |
332 | RC_GR_WRITE, |
333 | RC_GR_RMW, |
334 | } rc_gr_mode; |
335 | |
80599a42 |
336 | // note: must not be called when doing conditional code |
c18edb34 |
337 | static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode) |
679af8a3 |
338 | { |
c18edb34 |
339 | temp_reg_t *tr; |
340 | int i; |
341 | |
342 | // maybe already statically mapped? |
343 | i = reg_map_g2h[r]; |
344 | if (i != -1) |
345 | return i; |
679af8a3 |
346 | |
c18edb34 |
347 | rcache_counter++; |
348 | |
349 | // maybe already cached? |
350 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
351 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
352 | reg_temp[i].val == r) |
353 | { |
354 | reg_temp[i].stamp = rcache_counter; |
355 | if (mode != RC_GR_READ) |
356 | reg_temp[i].type = HR_CACHED_DIRTY; |
357 | return reg_temp[i].reg; |
358 | } |
679af8a3 |
359 | } |
360 | |
c18edb34 |
361 | // use any free reg |
362 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
363 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
364 | tr = ®_temp[i]; |
365 | goto do_alloc; |
366 | } |
367 | } |
368 | |
369 | tr = rcache_evict(); |
370 | |
371 | do_alloc: |
372 | if (mode != RC_GR_WRITE) |
373 | emith_ctx_read(tr->reg, r * 4); |
679af8a3 |
374 | |
c18edb34 |
375 | tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED; |
376 | tr->val = r; |
377 | tr->stamp = rcache_counter; |
378 | return tr->reg; |
679af8a3 |
379 | } |
380 | |
c18edb34 |
381 | static int rcache_get_tmp(void) |
679af8a3 |
382 | { |
c18edb34 |
383 | temp_reg_t *tr; |
384 | int i; |
385 | |
386 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
387 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
388 | tr = ®_temp[i]; |
389 | goto do_alloc; |
390 | } |
391 | |
392 | tr = rcache_evict(); |
393 | |
394 | do_alloc: |
395 | tr->type = HR_TEMP; |
396 | return tr->reg; |
397 | } |
398 | |
80599a42 |
399 | static int rcache_get_arg_id(int arg) |
400 | { |
401 | int i, r = 0; |
402 | host_arg2reg(r, arg); |
403 | |
404 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
405 | if (reg_temp[i].reg == r) |
406 | break; |
407 | |
408 | if (i == ARRAY_SIZE(reg_temp)) |
409 | // let's just say it's untracked arg reg |
410 | return r; |
411 | |
412 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
413 | // writeback |
414 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
415 | } |
416 | else if (reg_temp[i].type == HR_TEMP) { |
417 | printf("arg %d reg %d already used, aborting\n", arg, r); |
418 | exit(1); |
419 | } |
420 | |
421 | return i; |
422 | } |
423 | |
424 | // get a reg to be used as function arg |
425 | // it's assumed that regs are cleaned before call |
426 | static int rcache_get_tmp_arg(int arg) |
427 | { |
428 | int id = rcache_get_arg_id(arg); |
429 | reg_temp[id].type = HR_TEMP; |
430 | |
431 | return reg_temp[id].reg; |
432 | } |
433 | |
434 | // same but caches reg. RC_GR_READ only. |
435 | static int rcache_get_reg_arg(int arg, sh2_reg_e r) |
436 | { |
437 | int i, srcr, dstr, dstid; |
438 | |
439 | dstid = rcache_get_arg_id(arg); |
440 | dstr = reg_temp[dstid].reg; |
441 | |
442 | // maybe already statically mapped? |
443 | srcr = reg_map_g2h[r]; |
444 | if (srcr != -1) |
445 | goto do_cache; |
446 | |
447 | // maybe already cached? |
448 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
449 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
450 | reg_temp[i].val == r) |
451 | { |
452 | srcr = reg_temp[i].reg; |
453 | goto do_cache; |
454 | } |
455 | } |
456 | |
457 | // must read |
458 | srcr = dstr; |
459 | emith_ctx_read(srcr, r * 4); |
460 | |
461 | do_cache: |
462 | if (srcr != dstr) |
463 | emith_move_r_r(dstr, srcr); |
464 | |
465 | reg_temp[dstid].stamp = ++rcache_counter; |
466 | reg_temp[dstid].type = HR_CACHED; |
467 | reg_temp[dstid].val = r; |
468 | return dstr; |
469 | } |
470 | |
c18edb34 |
471 | static void rcache_free_tmp(int hr) |
472 | { |
473 | int i; |
474 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
475 | if (reg_temp[i].reg == hr) |
476 | break; |
477 | |
80599a42 |
478 | if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) { |
c18edb34 |
479 | printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type); |
80599a42 |
480 | return; |
481 | } |
482 | |
483 | reg_temp[i].type = HR_FREE; |
c18edb34 |
484 | } |
485 | |
80599a42 |
486 | static void rcache_clean(void) |
c18edb34 |
487 | { |
488 | int i; |
80599a42 |
489 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
490 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
491 | // writeback |
492 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
80599a42 |
493 | reg_temp[i].type = HR_CACHED; |
c18edb34 |
494 | } |
80599a42 |
495 | } |
496 | |
497 | static void rcache_invalidate(void) |
498 | { |
499 | int i; |
500 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
501 | reg_temp[i].type = HR_FREE; |
c18edb34 |
502 | rcache_counter = 0; |
503 | } |
504 | |
80599a42 |
505 | static void rcache_flush(void) |
506 | { |
507 | rcache_clean(); |
508 | rcache_invalidate(); |
509 | } |
510 | |
c18edb34 |
511 | // --------------------------------------------------------------- |
512 | |
513 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
514 | { |
52d759c3 |
515 | // TODO: propagate this constant |
c18edb34 |
516 | int hr = rcache_get_reg(dst, RC_GR_WRITE); |
517 | emith_move_r_imm(hr, imm); |
518 | } |
519 | |
520 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
521 | { |
522 | int hr_d = rcache_get_reg(dst, RC_GR_WRITE); |
523 | int hr_s = rcache_get_reg(src, RC_GR_READ); |
524 | |
525 | emith_move_r_r(hr_d, hr_s); |
679af8a3 |
526 | } |
527 | |
52d759c3 |
528 | // T must be clear, and comparison done just before this |
529 | static void emit_or_t_if_eq(int srr) |
530 | { |
531 | EMITH_SJMP_START(DCOND_NE); |
532 | emith_or_r_imm_c(DCOND_EQ, srr, T); |
533 | EMITH_SJMP_END(DCOND_NE); |
534 | } |
535 | |
80599a42 |
536 | // arguments must be ready |
537 | // reg cache must be clean before call |
538 | static int emit_memhandler_read(int size) |
679af8a3 |
539 | { |
b081408f |
540 | int arg0, arg1; |
541 | host_arg2reg(arg0, 0); |
542 | |
543 | // must writeback cycles for poll detection stuff |
544 | if (reg_map_g2h[SHR_SR] != -1) |
545 | emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4); |
546 | arg1 = rcache_get_tmp_arg(1); |
547 | emith_move_r_r(arg1, CONTEXT_REG); |
548 | |
549 | #if 1 |
550 | if (Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) { |
551 | int tmp = rcache_get_tmp(); |
552 | emith_and_r_r_imm(tmp, arg0, 0xfb000000); |
553 | emith_cmp_r_imm(tmp, 0x02000000); |
554 | switch (size) { |
555 | case 0: // 8 |
556 | EMITH_SJMP3_START(DCOND_NE); |
557 | emith_eor_r_imm_c(DCOND_EQ, arg0, 1); |
558 | emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
559 | EMITH_SJMP3_MID(DCOND_NE); |
560 | emith_call_cond(DCOND_NE, p32x_sh2_read8); |
561 | EMITH_SJMP3_END(); |
562 | break; |
563 | case 1: // 16 |
564 | EMITH_SJMP3_START(DCOND_NE); |
565 | emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
566 | EMITH_SJMP3_MID(DCOND_NE); |
567 | emith_call_cond(DCOND_NE, p32x_sh2_read16); |
568 | EMITH_SJMP3_END(); |
569 | break; |
570 | case 2: // 32 |
571 | EMITH_SJMP3_START(DCOND_NE); |
572 | emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
573 | emith_ror_c(DCOND_EQ, arg0, arg0, 16); |
574 | EMITH_SJMP3_MID(DCOND_NE); |
575 | emith_call_cond(DCOND_NE, p32x_sh2_read32); |
576 | EMITH_SJMP3_END(); |
577 | break; |
578 | } |
579 | } |
580 | else |
581 | #endif |
582 | { |
583 | switch (size) { |
584 | case 0: // 8 |
585 | emith_call(p32x_sh2_read8); |
586 | break; |
587 | case 1: // 16 |
588 | emith_call(p32x_sh2_read16); |
589 | break; |
590 | case 2: // 32 |
591 | emith_call(p32x_sh2_read32); |
592 | break; |
593 | } |
679af8a3 |
594 | } |
80599a42 |
595 | rcache_invalidate(); |
596 | // assuming arg0 and retval reg matches |
597 | return rcache_get_tmp_arg(0); |
598 | } |
679af8a3 |
599 | |
e05b81fc |
600 | static void emit_memhandler_write(int size, u32 pc, int delay) |
80599a42 |
601 | { |
602 | int ctxr; |
603 | host_arg2reg(ctxr, 2); |
80599a42 |
604 | switch (size) { |
605 | case 0: // 8 |
e05b81fc |
606 | // XXX: consider inlining sh2_drc_write8 |
607 | if (delay) { |
608 | emith_call(sh2_drc_write8_slot); |
609 | } else { |
610 | emit_move_r_imm32(SHR_PC, pc); |
611 | rcache_clean(); |
612 | emith_call(sh2_drc_write8); |
613 | } |
80599a42 |
614 | break; |
615 | case 1: // 16 |
e05b81fc |
616 | if (delay) { |
617 | emith_call(sh2_drc_write16_slot); |
618 | } else { |
619 | emit_move_r_imm32(SHR_PC, pc); |
620 | rcache_clean(); |
621 | emith_call(sh2_drc_write16); |
622 | } |
80599a42 |
623 | break; |
624 | case 2: // 32 |
e05b81fc |
625 | emith_move_r_r(ctxr, CONTEXT_REG); |
80599a42 |
626 | emith_call(p32x_sh2_write32); |
627 | break; |
628 | } |
629 | rcache_invalidate(); |
679af8a3 |
630 | } |
80599a42 |
631 | |
52d759c3 |
632 | // @(Rx,Ry) |
633 | static int emit_indirect_indexed_read(int rx, int ry, int size) |
634 | { |
635 | int a0, t; |
636 | rcache_clean(); |
637 | a0 = rcache_get_reg_arg(0, rx); |
638 | t = rcache_get_reg(ry, RC_GR_READ); |
639 | emith_add_r_r(a0, t); |
640 | return emit_memhandler_read(size); |
641 | } |
642 | |
f0d7b1fa |
643 | // read @Rn, @rm |
644 | static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size) |
645 | { |
646 | int tmp; |
647 | |
648 | rcache_clean(); |
649 | rcache_get_reg_arg(0, rn); |
650 | tmp = emit_memhandler_read(size); |
651 | emith_ctx_write(tmp, offsetof(SH2, drc_tmp)); |
652 | rcache_free_tmp(tmp); |
653 | tmp = rcache_get_reg(rn, RC_GR_RMW); |
654 | emith_add_r_imm(tmp, 1 << size); |
655 | |
656 | rcache_clean(); |
657 | rcache_get_reg_arg(0, rm); |
658 | *rmr = emit_memhandler_read(size); |
659 | *rnr = rcache_get_tmp(); |
660 | emith_ctx_read(*rnr, offsetof(SH2, drc_tmp)); |
661 | tmp = rcache_get_reg(rm, RC_GR_RMW); |
662 | emith_add_r_imm(tmp, 1 << size); |
663 | } |
664 | |
8796b7ee |
665 | static void emit_do_static_regs(int is_write, int tmpr) |
f0d7b1fa |
666 | { |
8796b7ee |
667 | int i, r, count; |
668 | |
669 | for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) { |
670 | r = reg_map_g2h[i]; |
671 | if (r == -1) |
672 | continue; |
673 | |
674 | for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) { |
675 | if (reg_map_g2h[i + 1] != r + 1) |
676 | break; |
677 | count++; |
678 | } |
679 | |
680 | if (count > 1) { |
681 | // i, r point to last item |
682 | if (is_write) |
683 | emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr); |
684 | else |
685 | emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr); |
686 | } else { |
687 | if (is_write) |
688 | emith_ctx_write(r, i * 4); |
689 | else |
690 | emith_ctx_read(r, i * 4); |
691 | } |
f0d7b1fa |
692 | } |
693 | } |
694 | |
e05b81fc |
695 | static void emit_block_entry(void) |
f0d7b1fa |
696 | { |
e05b81fc |
697 | int arg0, arg1, arg2; |
8796b7ee |
698 | |
e05b81fc |
699 | host_arg2reg(arg0, 0); |
700 | host_arg2reg(arg1, 1); |
701 | host_arg2reg(arg2, 2); |
8796b7ee |
702 | |
e05b81fc |
703 | #if (DRC_DEBUG & 4) |
704 | emith_move_r_r(arg1, CONTEXT_REG); |
705 | emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ)); |
706 | emith_call(sh2_drc_announce_entry); |
707 | rcache_invalidate(); |
708 | #endif |
709 | emith_tst_r_r(arg0, arg0); |
710 | EMITH_SJMP_START(DCOND_EQ); |
711 | emith_jump_reg_c(DCOND_NE, arg0); |
712 | EMITH_SJMP_END(DCOND_EQ); |
713 | } |
8796b7ee |
714 | |
e05b81fc |
715 | static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id) |
716 | { |
717 | block_desc *bd = NULL; |
718 | void *block = NULL; |
719 | *tcache_id = 0; |
720 | |
721 | // we have full block id tables for data_array and RAM |
722 | // BIOS goes to data_array table too |
723 | if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) { |
724 | int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
725 | *tcache_id = 1 + is_slave; |
726 | if (blkid & 1) { |
727 | bd = &block_tables[*tcache_id][blkid >> 1]; |
728 | block = bd->tcache_ptr; |
729 | } |
730 | } |
731 | // RAM |
732 | else if ((pc & 0xc6000000) == 0x06000000) { |
733 | int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
734 | if (blkid & 1) { |
735 | bd = &block_tables[0][blkid >> 1]; |
736 | block = bd->tcache_ptr; |
737 | } |
738 | } |
739 | // ROM |
740 | else if ((pc & 0xc6000000) == 0x02000000) { |
741 | bd = HASH_FUNC(hash_table, pc); |
8796b7ee |
742 | |
e05b81fc |
743 | if (bd != NULL) { |
744 | if (bd->addr == pc) |
745 | block = bd->tcache_ptr; |
746 | else |
747 | block = dr_find_block(bd, pc); |
748 | } |
749 | } |
750 | |
751 | #if (DRC_DEBUG & 1) |
752 | if (bd != NULL) |
753 | bd->refcount++; |
754 | #endif |
755 | return block; |
f0d7b1fa |
756 | } |
679af8a3 |
757 | |
44e6452e |
758 | void dr_link_blocks(void *target, u32 pc, int tcache_id) |
759 | { |
760 | block_link *bl = block_links[tcache_id]; |
761 | int cnt = block_link_counts[tcache_id]; |
762 | int i; |
763 | |
764 | for (i = 0; i < cnt; i++) { |
765 | if (bl[i].target_pc == pc) { |
766 | dbg(1, "- link from %p", bl[i].jump); |
767 | emith_jump_patch(bl[i].jump, target); |
768 | // XXX: sync ARM caches (old jump should be fine)? |
769 | } |
770 | } |
771 | } |
772 | |
773 | void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id) |
774 | { |
775 | int target_tcache_id; |
776 | void *target; |
777 | int ret; |
778 | |
779 | target = lookup_block(pc, sh2->is_slave, &target_tcache_id); |
780 | if (target_tcache_id == tcache_id) { |
781 | // allow linking blocks only from local cache |
782 | ret = dr_add_block_link(pc, tcache_ptr, tcache_id); |
783 | if (ret < 0) |
784 | return NULL; |
785 | } |
786 | if (target == NULL || target_tcache_id != tcache_id) |
787 | target = sh2_drc_dispatcher; |
788 | |
789 | return target; |
790 | } |
791 | |
e898de13 |
792 | #define DELAYED_OP \ |
18b94127 |
793 | drcf.delayed_op = 2 |
794 | |
795 | #define DELAY_SAVE_T(sr) { \ |
796 | emith_bic_r_imm(sr, T_save); \ |
797 | emith_tst_r_imm(sr, T); \ |
798 | EMITH_SJMP_START(DCOND_EQ); \ |
799 | emith_or_r_imm_c(DCOND_NE, sr, T_save); \ |
800 | EMITH_SJMP_END(DCOND_EQ); \ |
801 | drcf.use_saved_t = 1; \ |
802 | } |
e898de13 |
803 | |
e05b81fc |
804 | #define FLUSH_CYCLES(sr) \ |
805 | if (cycles > 0) { \ |
806 | emith_sub_r_imm(sr, cycles << 12); \ |
807 | cycles = 0; \ |
808 | } |
809 | |
e898de13 |
810 | #define CHECK_UNHANDLED_BITS(mask) { \ |
811 | if ((op & (mask)) != 0) \ |
812 | goto default_; \ |
813 | } |
814 | |
80599a42 |
815 | #define GET_Fx() \ |
816 | ((op >> 4) & 0x0f) |
817 | |
818 | #define GET_Rm GET_Fx |
819 | |
820 | #define GET_Rn() \ |
821 | ((op >> 8) & 0x0f) |
822 | |
ed8cf79b |
823 | #define CHECK_FX_LT(n) \ |
52d759c3 |
824 | if (GET_Fx() >= n) \ |
80599a42 |
825 | goto default_ |
826 | |
44e6452e |
827 | #define MAX_LOCAL_BRANCHES 32 |
18b94127 |
828 | |
829 | // op_flags: data from 1st pass |
830 | #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2] |
831 | #define OF_DELAY_OP (1 << 0) |
832 | |
e05b81fc |
833 | static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) |
679af8a3 |
834 | { |
18b94127 |
835 | // XXX: maybe use structs instead? |
836 | void *branch_target_ptr[MAX_LOCAL_BRANCHES]; |
837 | u32 branch_target_pc[MAX_LOCAL_BRANCHES]; |
838 | int branch_target_count = 0; |
839 | void *branch_patch_ptr[MAX_LOCAL_BRANCHES]; |
840 | u32 branch_patch_pc[MAX_LOCAL_BRANCHES]; |
841 | int branch_patch_count = 0; |
44e6452e |
842 | int pending_branch_cond = -1; |
843 | int pending_branch_pc = 0; |
18b94127 |
844 | u8 op_flags[BLOCK_CYCLE_LIMIT + 1]; |
845 | struct { |
846 | u32 delayed_op:2; |
847 | u32 test_irq:1; |
848 | u32 use_saved_t:1; // delayed op modifies T |
849 | } drcf = { 0, }; |
850 | |
44e6452e |
851 | // PC of current, first, last, last_target_blk SH2 insn |
852 | u32 pc, base_pc, end_pc, out_pc; |
f4bb5d6b |
853 | void *block_entry; |
679af8a3 |
854 | block_desc *this_block; |
18b94127 |
855 | int blkid_main = 0; |
856 | u32 tmp, tmp2; |
857 | int cycles; |
858 | int op; |
859 | int i; |
860 | |
861 | base_pc = sh2->pc; |
679af8a3 |
862 | |
f4bb5d6b |
863 | // validate PC |
18b94127 |
864 | tmp = base_pc >> 29; |
865 | if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) { |
866 | printf("invalid PC, aborting: %08x\n", base_pc); |
f4bb5d6b |
867 | // FIXME: be less destructive |
868 | exit(1); |
869 | } |
870 | |
f4bb5d6b |
871 | tcache_ptr = tcache_ptrs[tcache_id]; |
18b94127 |
872 | this_block = dr_add_block(base_pc, tcache_id, &blkid_main); |
44e6452e |
873 | if (this_block == NULL) |
874 | return NULL; |
f4bb5d6b |
875 | |
18b94127 |
876 | // predict tcache overflow |
f4bb5d6b |
877 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
44e6452e |
878 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) { |
879 | printf("tcache %d overflow\n", tcache_id); |
18b94127 |
880 | return NULL; |
44e6452e |
881 | } |
18b94127 |
882 | |
883 | block_entry = tcache_ptr; |
884 | dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', |
885 | tcache_id, blkid_main, base_pc, block_entry); |
886 | |
44e6452e |
887 | dr_link_blocks(tcache_ptr, base_pc, tcache_id); |
888 | |
18b94127 |
889 | // 1st pass: scan forward for local branches |
890 | memset(op_flags, 0, sizeof(op_flags)); |
891 | for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) { |
892 | op = p32x_sh2_read16(pc, sh2); |
893 | if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR |
44e6452e |
894 | signed int offs = ((signed int)(op << 20) >> 19); |
18b94127 |
895 | pc += 2; |
896 | OP_FLAGS(pc) |= OF_DELAY_OP; |
44e6452e |
897 | ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,); |
18b94127 |
898 | break; |
899 | } |
900 | if ((op & 0xf000) == 0) { |
901 | op &= 0xff; |
44e6452e |
902 | if (op == 0x1b) // SLEEP |
903 | break; |
904 | if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE |
18b94127 |
905 | pc += 2; |
906 | OP_FLAGS(pc) |= OF_DELAY_OP; |
907 | break; |
908 | } |
909 | continue; |
910 | } |
911 | if ((op & 0xf0df) == 0x400b) { // JMP, JSR |
912 | pc += 2; |
913 | OP_FLAGS(pc) |= OF_DELAY_OP; |
914 | break; |
915 | } |
916 | if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) |
917 | signed int offs = ((signed int)(op << 24) >> 23); |
918 | if (op & 0x0400) |
919 | OP_FLAGS(pc + 2) |= OF_DELAY_OP; |
44e6452e |
920 | ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break); |
18b94127 |
921 | } |
44e6452e |
922 | if ((op & 0xff00) == 0xc300) // TRAPA |
923 | break; |
f4bb5d6b |
924 | } |
e898de13 |
925 | |
18b94127 |
926 | end_pc = pc; |
679af8a3 |
927 | |
18b94127 |
928 | // clean branch_targets that are not really local, |
929 | // and that land on delay slots |
930 | for (i = 0, tmp = 0; i < branch_target_count; i++) { |
931 | pc = branch_target_pc[i]; |
932 | if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP)) |
933 | branch_target_pc[tmp++] = branch_target_pc[i]; |
e898de13 |
934 | } |
18b94127 |
935 | branch_target_count = tmp; |
936 | memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); |
679af8a3 |
937 | |
18b94127 |
938 | // ------------------------------------------------- |
939 | // 2nd pass: actual compilation |
44e6452e |
940 | out_pc = 0; |
18b94127 |
941 | pc = base_pc; |
942 | for (cycles = 0; pc <= end_pc || drcf.delayed_op; ) |
679af8a3 |
943 | { |
18b94127 |
944 | u32 tmp3, tmp4, sr; |
945 | |
946 | if (drcf.delayed_op > 0) |
947 | drcf.delayed_op--; |
948 | |
949 | i = find_in_array(branch_target_pc, branch_target_count, pc); |
950 | if (i >= 0) |
951 | { |
952 | if (pc != sh2->pc) |
953 | { |
954 | /* make "subblock" - just a mid-block entry */ |
955 | block_desc *subblock; |
956 | u16 *drcblk; |
957 | int blkid; |
958 | |
959 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
e05b81fc |
960 | FLUSH_CYCLES(sr); |
18b94127 |
961 | rcache_flush(); |
962 | do_host_disasm(tcache_id); |
963 | |
964 | subblock = dr_add_block(pc, tcache_id, &blkid); |
965 | if (subblock == NULL) |
966 | return NULL; |
967 | subblock->end_addr = pc; |
968 | |
969 | if (tcache_id != 0) { // data array, BIOS |
970 | drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
971 | drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT; |
972 | *drcblk = (blkid << 1) | 1; |
973 | } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
974 | drcblk = Pico32xMem->drcblk_ram; |
975 | drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
976 | *drcblk = (blkid << 1) | 1; |
977 | } |
978 | |
44e6452e |
979 | dbg(1, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', |
18b94127 |
980 | tcache_id, blkid, pc, tcache_ptr); |
44e6452e |
981 | |
982 | // since we made a block entry, link any other blocks that jump to current pc |
983 | dr_link_blocks(tcache_ptr, pc, tcache_id); |
18b94127 |
984 | } |
985 | branch_target_ptr[i] = tcache_ptr; |
986 | |
987 | // must update PC |
988 | emit_move_r_imm32(SHR_PC, pc); |
989 | rcache_clean(); |
990 | |
991 | // check cycles |
992 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
993 | emith_cmp_r_imm(sr, 0); |
994 | emith_jump_cond(DCOND_LE, sh2_drc_exit); |
995 | } |
e898de13 |
996 | |
2b2b46b0 |
997 | op = p32x_sh2_read16(pc, sh2); |
e898de13 |
998 | |
999 | #if (DRC_DEBUG & 3) |
1000 | insns_compiled++; |
1001 | #if (DRC_DEBUG & 2) |
1002 | DasmSH2(sh2dasm_buff, pc, op); |
1003 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
1004 | #endif |
679af8a3 |
1005 | #endif |
679af8a3 |
1006 | |
1007 | pc += 2; |
1008 | cycles++; |
1009 | |
1010 | switch ((op >> 12) & 0x0f) |
1011 | { |
3863edbd |
1012 | ///////////////////////////////////////////// |
679af8a3 |
1013 | case 0x00: |
80599a42 |
1014 | switch (op & 0x0f) |
1015 | { |
1016 | case 0x02: |
1017 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1018 | switch (GET_Fx()) |
1019 | { |
1020 | case 0: // STC SR,Rn 0000nnnn00000010 |
1021 | tmp2 = SHR_SR; |
1022 | break; |
1023 | case 1: // STC GBR,Rn 0000nnnn00010010 |
1024 | tmp2 = SHR_GBR; |
1025 | break; |
1026 | case 2: // STC VBR,Rn 0000nnnn00100010 |
1027 | tmp2 = SHR_VBR; |
1028 | break; |
1029 | default: |
1030 | goto default_; |
1031 | } |
ed8cf79b |
1032 | tmp3 = rcache_get_reg(tmp2, RC_GR_READ); |
1033 | emith_move_r_r(tmp, tmp3); |
1034 | if (tmp2 == SHR_SR) |
18b94127 |
1035 | emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0 |
80599a42 |
1036 | goto end_op; |
e898de13 |
1037 | case 0x03: |
1038 | CHECK_UNHANDLED_BITS(0xd0); |
1039 | // BRAF Rm 0000mmmm00100011 |
1040 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
1041 | DELAYED_OP; |
18b94127 |
1042 | tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
80599a42 |
1043 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
c18edb34 |
1044 | emith_move_r_r(tmp, tmp2); |
18b94127 |
1045 | if (op & 0x20) |
1046 | emith_add_r_imm(tmp, pc + 2); |
1047 | else { // BSRF |
1048 | tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE); |
1049 | emith_move_r_imm(tmp3, pc + 2); |
1050 | emith_add_r_r(tmp, tmp3); |
1051 | } |
44e6452e |
1052 | out_pc = (u32)-1; |
679af8a3 |
1053 | cycles++; |
e898de13 |
1054 | goto end_op; |
80599a42 |
1055 | case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 |
1056 | case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 |
1057 | case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 |
e05b81fc |
1058 | rcache_clean(); |
1059 | tmp = rcache_get_reg_arg(1, GET_Rm()); |
1060 | tmp2 = rcache_get_reg_arg(0, SHR_R0); |
1061 | tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1062 | emith_add_r_r(tmp2, tmp3); |
1063 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1064 | goto end_op; |
1065 | case 0x07: |
1066 | // MUL.L Rm,Rn 0000nnnnmmmm0111 |
1067 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1068 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1069 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1070 | emith_mul(tmp3, tmp2, tmp); |
1071 | cycles++; |
1072 | goto end_op; |
1073 | case 0x08: |
1074 | CHECK_UNHANDLED_BITS(0xf00); |
1075 | switch (GET_Fx()) |
1076 | { |
1077 | case 0: // CLRT 0000000000001000 |
8796b7ee |
1078 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1079 | if (drcf.delayed_op) |
1080 | DELAY_SAVE_T(sr); |
8796b7ee |
1081 | emith_bic_r_imm(sr, T); |
80599a42 |
1082 | break; |
1083 | case 1: // SETT 0000000000011000 |
8796b7ee |
1084 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1085 | if (drcf.delayed_op) |
1086 | DELAY_SAVE_T(sr); |
8796b7ee |
1087 | emith_or_r_imm(sr, T); |
80599a42 |
1088 | break; |
1089 | case 2: // CLRMAC 0000000000101000 |
1090 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1091 | emith_move_r_imm(tmp, 0); |
1092 | tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1093 | emith_move_r_imm(tmp, 0); |
1094 | break; |
1095 | default: |
1096 | goto default_; |
1097 | } |
1098 | goto end_op; |
e898de13 |
1099 | case 0x09: |
80599a42 |
1100 | switch (GET_Fx()) |
1101 | { |
1102 | case 0: // NOP 0000000000001001 |
1103 | CHECK_UNHANDLED_BITS(0xf00); |
1104 | break; |
1105 | case 1: // DIV0U 0000000000011001 |
1106 | CHECK_UNHANDLED_BITS(0xf00); |
8796b7ee |
1107 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1108 | if (drcf.delayed_op) |
1109 | DELAY_SAVE_T(sr); |
8796b7ee |
1110 | emith_bic_r_imm(sr, M|Q|T); |
80599a42 |
1111 | break; |
1112 | case 2: // MOVT Rn 0000nnnn00101001 |
8796b7ee |
1113 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
80599a42 |
1114 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
8796b7ee |
1115 | emith_clear_msb(tmp2, sr, 31); |
80599a42 |
1116 | break; |
1117 | default: |
1118 | goto default_; |
1119 | } |
1120 | goto end_op; |
1121 | case 0x0a: |
1122 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1123 | switch (GET_Fx()) |
1124 | { |
1125 | case 0: // STS MACH,Rn 0000nnnn00001010 |
ed8cf79b |
1126 | tmp2 = SHR_MACH; |
80599a42 |
1127 | break; |
1128 | case 1: // STS MACL,Rn 0000nnnn00011010 |
ed8cf79b |
1129 | tmp2 = SHR_MACL; |
80599a42 |
1130 | break; |
1131 | case 2: // STS PR,Rn 0000nnnn00101010 |
ed8cf79b |
1132 | tmp2 = SHR_PR; |
80599a42 |
1133 | break; |
1134 | default: |
1135 | goto default_; |
1136 | } |
ed8cf79b |
1137 | tmp2 = rcache_get_reg(tmp2, RC_GR_READ); |
80599a42 |
1138 | emith_move_r_r(tmp, tmp2); |
e898de13 |
1139 | goto end_op; |
1140 | case 0x0b: |
80599a42 |
1141 | CHECK_UNHANDLED_BITS(0xf00); |
1142 | switch (GET_Fx()) |
1143 | { |
1144 | case 0: // RTS 0000000000001011 |
1145 | DELAYED_OP; |
18b94127 |
1146 | emit_move_r_r(SHR_PC, SHR_PR); |
44e6452e |
1147 | out_pc = (u32)-1; |
e898de13 |
1148 | cycles++; |
80599a42 |
1149 | break; |
1150 | case 1: // SLEEP 0000000000011011 |
80599a42 |
1151 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1152 | emith_clear_msb(tmp, tmp, 20); // clear cycles |
44e6452e |
1153 | out_pc = out_pc - 2; |
80599a42 |
1154 | cycles = 1; |
e05b81fc |
1155 | goto end_op; |
80599a42 |
1156 | case 2: // RTE 0000000000101011 |
52d759c3 |
1157 | DELAYED_OP; |
1158 | rcache_clean(); |
1159 | // pop PC |
1160 | rcache_get_reg_arg(0, SHR_SP); |
1161 | tmp = emit_memhandler_read(2); |
18b94127 |
1162 | tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
52d759c3 |
1163 | emith_move_r_r(tmp2, tmp); |
1164 | rcache_free_tmp(tmp); |
1165 | rcache_clean(); |
1166 | // pop SR |
1167 | tmp = rcache_get_reg_arg(0, SHR_SP); |
1168 | emith_add_r_imm(tmp, 4); |
1169 | tmp = emit_memhandler_read(2); |
18b94127 |
1170 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1171 | emith_write_sr(sr, tmp); |
52d759c3 |
1172 | rcache_free_tmp(tmp); |
1173 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
1174 | emith_add_r_imm(tmp, 4*2); |
18b94127 |
1175 | drcf.test_irq = 1; |
44e6452e |
1176 | out_pc = (u32)-1; |
e898de13 |
1177 | cycles += 3; |
80599a42 |
1178 | break; |
1179 | default: |
1180 | goto default_; |
e898de13 |
1181 | } |
1182 | goto end_op; |
80599a42 |
1183 | case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 |
1184 | case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 |
1185 | case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 |
52d759c3 |
1186 | tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3); |
80599a42 |
1187 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
80599a42 |
1188 | if ((op & 3) != 2) { |
1189 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
1190 | } else |
1191 | emith_move_r_r(tmp2, tmp); |
52d759c3 |
1192 | rcache_free_tmp(tmp); |
80599a42 |
1193 | goto end_op; |
1194 | case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 |
f0d7b1fa |
1195 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2); |
8796b7ee |
1196 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
f0d7b1fa |
1197 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
1198 | /* MS 16 MAC bits unused if saturated */ |
8796b7ee |
1199 | emith_tst_r_imm(sr, S); |
f0d7b1fa |
1200 | EMITH_SJMP_START(DCOND_EQ); |
1201 | emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16); |
1202 | EMITH_SJMP_END(DCOND_EQ); |
1203 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR |
1204 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
f0d7b1fa |
1205 | rcache_free_tmp(tmp2); |
8796b7ee |
1206 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case |
1207 | emith_tst_r_imm(sr, S); |
1208 | |
1209 | EMITH_JMP_START(DCOND_EQ); |
1210 | emith_asr(tmp, tmp4, 15); |
1211 | emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff) |
1212 | EMITH_SJMP_START(DCOND_GE); |
1213 | emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000); |
1214 | emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000); |
1215 | EMITH_SJMP_END(DCOND_GE); |
1216 | emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff) |
1217 | EMITH_SJMP_START(DCOND_LE); |
1218 | emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff); |
1219 | emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff); |
1220 | EMITH_SJMP_END(DCOND_LE); |
1221 | EMITH_JMP_END(DCOND_EQ); |
1222 | |
1223 | rcache_free_tmp(tmp); |
f0d7b1fa |
1224 | cycles += 3; |
1225 | goto end_op; |
80599a42 |
1226 | } |
1227 | goto default_; |
1228 | |
3863edbd |
1229 | ///////////////////////////////////////////// |
80599a42 |
1230 | case 0x01: |
1231 | // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd |
1232 | rcache_clean(); |
1233 | tmp = rcache_get_reg_arg(0, GET_Rn()); |
1234 | tmp2 = rcache_get_reg_arg(1, GET_Rm()); |
1235 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
e05b81fc |
1236 | emit_memhandler_write(2, pc, drcf.delayed_op); |
80599a42 |
1237 | goto end_op; |
1238 | |
1239 | case 0x02: |
1240 | switch (op & 0x0f) |
1241 | { |
1242 | case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000 |
1243 | case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001 |
1244 | case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010 |
1245 | rcache_clean(); |
1246 | rcache_get_reg_arg(0, GET_Rn()); |
1247 | rcache_get_reg_arg(1, GET_Rm()); |
e05b81fc |
1248 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1249 | goto end_op; |
1250 | case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 |
1251 | case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 |
1252 | case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110 |
1253 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1254 | emith_sub_r_imm(tmp, (1 << (op & 3))); |
1255 | rcache_clean(); |
1256 | rcache_get_reg_arg(0, GET_Rn()); |
1257 | rcache_get_reg_arg(1, GET_Rm()); |
e05b81fc |
1258 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1259 | goto end_op; |
1260 | case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 |
8796b7ee |
1261 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
80599a42 |
1262 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1263 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1264 | if (drcf.delayed_op) |
1265 | DELAY_SAVE_T(sr); |
8796b7ee |
1266 | emith_bic_r_imm(sr, M|Q|T); |
80599a42 |
1267 | emith_tst_r_imm(tmp2, (1<<31)); |
1268 | EMITH_SJMP_START(DCOND_EQ); |
8796b7ee |
1269 | emith_or_r_imm_c(DCOND_NE, sr, Q); |
80599a42 |
1270 | EMITH_SJMP_END(DCOND_EQ); |
1271 | emith_tst_r_imm(tmp3, (1<<31)); |
1272 | EMITH_SJMP_START(DCOND_EQ); |
8796b7ee |
1273 | emith_or_r_imm_c(DCOND_NE, sr, M); |
80599a42 |
1274 | EMITH_SJMP_END(DCOND_EQ); |
1275 | emith_teq_r_r(tmp2, tmp3); |
1276 | EMITH_SJMP_START(DCOND_PL); |
8796b7ee |
1277 | emith_or_r_imm_c(DCOND_MI, sr, T); |
80599a42 |
1278 | EMITH_SJMP_END(DCOND_PL); |
1279 | goto end_op; |
3863edbd |
1280 | case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 |
8796b7ee |
1281 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1282 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1283 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1284 | if (drcf.delayed_op) |
1285 | DELAY_SAVE_T(sr); |
8796b7ee |
1286 | emith_bic_r_imm(sr, T); |
3863edbd |
1287 | emith_tst_r_r(tmp2, tmp3); |
8796b7ee |
1288 | emit_or_t_if_eq(sr); |
3863edbd |
1289 | goto end_op; |
1290 | case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 |
1291 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1292 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1293 | emith_and_r_r(tmp, tmp2); |
1294 | goto end_op; |
1295 | case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010 |
1296 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1297 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1298 | emith_eor_r_r(tmp, tmp2); |
1299 | goto end_op; |
1300 | case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011 |
1301 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1302 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1303 | emith_or_r_r(tmp, tmp2); |
1304 | goto end_op; |
1305 | case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100 |
1306 | tmp = rcache_get_tmp(); |
1307 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1308 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1309 | emith_eor_r_r_r(tmp, tmp2, tmp3); |
8796b7ee |
1310 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1311 | if (drcf.delayed_op) |
1312 | DELAY_SAVE_T(sr); |
8796b7ee |
1313 | emith_bic_r_imm(sr, T); |
3863edbd |
1314 | emith_tst_r_imm(tmp, 0x000000ff); |
52d759c3 |
1315 | emit_or_t_if_eq(tmp); |
3863edbd |
1316 | emith_tst_r_imm(tmp, 0x0000ff00); |
52d759c3 |
1317 | emit_or_t_if_eq(tmp); |
3863edbd |
1318 | emith_tst_r_imm(tmp, 0x00ff0000); |
52d759c3 |
1319 | emit_or_t_if_eq(tmp); |
3863edbd |
1320 | emith_tst_r_imm(tmp, 0xff000000); |
52d759c3 |
1321 | emit_or_t_if_eq(tmp); |
3863edbd |
1322 | rcache_free_tmp(tmp); |
1323 | goto end_op; |
1324 | case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101 |
1325 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1326 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1327 | emith_lsr(tmp, tmp, 16); |
f0d7b1fa |
1328 | emith_or_r_r_lsl(tmp, tmp2, 16); |
3863edbd |
1329 | goto end_op; |
1330 | case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110 |
1331 | case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111 |
1332 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1333 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1334 | if (op & 1) { |
1335 | emith_sext(tmp, tmp2, 16); |
1336 | } else |
1337 | emith_clear_msb(tmp, tmp2, 16); |
1338 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1339 | tmp2 = rcache_get_tmp(); |
1340 | if (op & 1) { |
1341 | emith_sext(tmp2, tmp3, 16); |
1342 | } else |
1343 | emith_clear_msb(tmp2, tmp3, 16); |
1344 | emith_mul(tmp, tmp, tmp2); |
1345 | rcache_free_tmp(tmp2); |
1346 | // FIXME: causes timing issues in Doom? |
1347 | // cycles++; |
1348 | goto end_op; |
679af8a3 |
1349 | } |
1350 | goto default_; |
1351 | |
3863edbd |
1352 | ///////////////////////////////////////////// |
1353 | case 0x03: |
1354 | switch (op & 0x0f) |
1355 | { |
1356 | case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000 |
1357 | case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010 |
1358 | case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 |
1359 | case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 |
1360 | case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 |
8796b7ee |
1361 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1362 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1363 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1364 | if (drcf.delayed_op) |
1365 | DELAY_SAVE_T(sr); |
8796b7ee |
1366 | emith_bic_r_imm(sr, T); |
3863edbd |
1367 | emith_cmp_r_r(tmp2, tmp3); |
1368 | switch (op & 0x07) |
1369 | { |
1370 | case 0x00: // CMP/EQ |
8796b7ee |
1371 | emit_or_t_if_eq(sr); |
3863edbd |
1372 | break; |
1373 | case 0x02: // CMP/HS |
1374 | EMITH_SJMP_START(DCOND_LO); |
8796b7ee |
1375 | emith_or_r_imm_c(DCOND_HS, sr, T); |
3863edbd |
1376 | EMITH_SJMP_END(DCOND_LO); |
1377 | break; |
1378 | case 0x03: // CMP/GE |
1379 | EMITH_SJMP_START(DCOND_LT); |
8796b7ee |
1380 | emith_or_r_imm_c(DCOND_GE, sr, T); |
3863edbd |
1381 | EMITH_SJMP_END(DCOND_LT); |
1382 | break; |
1383 | case 0x06: // CMP/HI |
1384 | EMITH_SJMP_START(DCOND_LS); |
8796b7ee |
1385 | emith_or_r_imm_c(DCOND_HI, sr, T); |
3863edbd |
1386 | EMITH_SJMP_END(DCOND_LS); |
1387 | break; |
1388 | case 0x07: // CMP/GT |
1389 | EMITH_SJMP_START(DCOND_LE); |
8796b7ee |
1390 | emith_or_r_imm_c(DCOND_GT, sr, T); |
3863edbd |
1391 | EMITH_SJMP_END(DCOND_LE); |
1392 | break; |
1393 | } |
1394 | goto end_op; |
1395 | case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100 |
f0d7b1fa |
1396 | // Q1 = carry(Rn = (Rn << 1) | T) |
1397 | // if Q ^ M |
1398 | // Q2 = carry(Rn += Rm) |
1399 | // else |
1400 | // Q2 = carry(Rn -= Rm) |
1401 | // Q = M ^ Q1 ^ Q2 |
1402 | // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2) |
1403 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1404 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1405 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1406 | if (drcf.delayed_op) |
1407 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1408 | emith_tpop_carry(sr, 0); |
f0d7b1fa |
1409 | emith_adcf_r_r(tmp2, tmp2); |
8b4f38f4 |
1410 | emith_tpush_carry(sr, 0); // keep Q1 in T for now |
f0d7b1fa |
1411 | tmp4 = rcache_get_tmp(); |
1412 | emith_and_r_r_imm(tmp4, sr, M); |
1413 | emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M |
1414 | rcache_free_tmp(tmp4); |
1415 | // add or sub, invert T if carry to get Q1 ^ Q2 |
1416 | // in: (Q ^ M) passed in Q, Q1 in T |
1417 | emith_sh2_div1_step(tmp2, tmp3, sr); |
18b94127 |
1418 | emith_bic_r_imm(sr, Q); |
1419 | emith_tst_r_imm(sr, M); |
1420 | EMITH_SJMP_START(DCOND_EQ); |
1421 | emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M |
1422 | EMITH_SJMP_END(DCOND_EQ); |
1423 | emith_tst_r_imm(sr, T); |
1424 | EMITH_SJMP_START(DCOND_EQ); |
1425 | emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 |
1426 | EMITH_SJMP_END(DCOND_EQ); |
1427 | emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) |
f0d7b1fa |
1428 | goto end_op; |
3863edbd |
1429 | case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 |
1430 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1431 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1432 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1433 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1434 | emith_mul_u64(tmp3, tmp4, tmp, tmp2); |
1435 | goto end_op; |
1436 | case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 |
1437 | case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 |
1438 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1439 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1440 | if (op & 4) { |
1441 | emith_add_r_r(tmp, tmp2); |
1442 | } else |
1443 | emith_sub_r_r(tmp, tmp2); |
1444 | goto end_op; |
1445 | case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010 |
1446 | case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 |
1447 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1448 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
8796b7ee |
1449 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1450 | if (drcf.delayed_op) |
1451 | DELAY_SAVE_T(sr); |
3863edbd |
1452 | if (op & 4) { // adc |
8b4f38f4 |
1453 | emith_tpop_carry(sr, 0); |
3863edbd |
1454 | emith_adcf_r_r(tmp, tmp2); |
8b4f38f4 |
1455 | emith_tpush_carry(sr, 0); |
3863edbd |
1456 | } else { |
8b4f38f4 |
1457 | emith_tpop_carry(sr, 1); |
3863edbd |
1458 | emith_sbcf_r_r(tmp, tmp2); |
8b4f38f4 |
1459 | emith_tpush_carry(sr, 1); |
3863edbd |
1460 | } |
3863edbd |
1461 | goto end_op; |
1462 | case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 |
1463 | case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 |
1464 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1465 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
8796b7ee |
1466 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1467 | if (drcf.delayed_op) |
1468 | DELAY_SAVE_T(sr); |
8796b7ee |
1469 | emith_bic_r_imm(sr, T); |
3863edbd |
1470 | if (op & 4) { |
1471 | emith_addf_r_r(tmp, tmp2); |
1472 | } else |
1473 | emith_subf_r_r(tmp, tmp2); |
1474 | EMITH_SJMP_START(DCOND_VC); |
8796b7ee |
1475 | emith_or_r_imm_c(DCOND_VS, sr, T); |
3863edbd |
1476 | EMITH_SJMP_END(DCOND_VC); |
1477 | goto end_op; |
1478 | case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 |
1479 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1480 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1481 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1482 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1483 | emith_mul_s64(tmp3, tmp4, tmp, tmp2); |
1484 | goto end_op; |
1485 | } |
1486 | goto default_; |
1487 | |
1488 | ///////////////////////////////////////////// |
679af8a3 |
1489 | case 0x04: |
3863edbd |
1490 | switch (op & 0x0f) |
1491 | { |
c18edb34 |
1492 | case 0x00: |
3863edbd |
1493 | switch (GET_Fx()) |
1494 | { |
1495 | case 0: // SHLL Rn 0100nnnn00000000 |
1496 | case 2: // SHAL Rn 0100nnnn00100000 |
8796b7ee |
1497 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1498 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1499 | if (drcf.delayed_op) |
1500 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1501 | emith_tpop_carry(sr, 0); // dummy |
3863edbd |
1502 | emith_lslf(tmp, tmp, 1); |
8b4f38f4 |
1503 | emith_tpush_carry(sr, 0); |
3863edbd |
1504 | goto end_op; |
1505 | case 1: // DT Rn 0100nnnn00010000 |
1506 | if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 |
1507 | emith_sh2_dtbf_loop(); |
1508 | goto end_op; |
1509 | } |
1510 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
8796b7ee |
1511 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1512 | if (drcf.delayed_op) |
1513 | DELAY_SAVE_T(sr); |
8796b7ee |
1514 | emith_bic_r_imm(sr, T); |
3863edbd |
1515 | emith_subf_r_imm(tmp, 1); |
8796b7ee |
1516 | emit_or_t_if_eq(sr); |
80599a42 |
1517 | goto end_op; |
1518 | } |
3863edbd |
1519 | goto default_; |
ed8cf79b |
1520 | case 0x01: |
1521 | switch (GET_Fx()) |
1522 | { |
1523 | case 0: // SHLR Rn 0100nnnn00000001 |
1524 | case 2: // SHAR Rn 0100nnnn00100001 |
8796b7ee |
1525 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1526 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1527 | if (drcf.delayed_op) |
1528 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1529 | emith_tpop_carry(sr, 0); // dummy |
ed8cf79b |
1530 | if (op & 0x20) { |
1531 | emith_asrf(tmp, tmp, 1); |
1532 | } else |
1533 | emith_lsrf(tmp, tmp, 1); |
8b4f38f4 |
1534 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1535 | goto end_op; |
1536 | case 1: // CMP/PZ Rn 0100nnnn00010001 |
8796b7ee |
1537 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1538 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1539 | if (drcf.delayed_op) |
1540 | DELAY_SAVE_T(sr); |
8796b7ee |
1541 | emith_bic_r_imm(sr, T); |
ed8cf79b |
1542 | emith_cmp_r_imm(tmp, 0); |
1543 | EMITH_SJMP_START(DCOND_LT); |
8796b7ee |
1544 | emith_or_r_imm_c(DCOND_GE, sr, T); |
ed8cf79b |
1545 | EMITH_SJMP_END(DCOND_LT); |
1546 | goto end_op; |
1547 | } |
1548 | goto default_; |
1549 | case 0x02: |
1550 | case 0x03: |
1551 | switch (op & 0x3f) |
1552 | { |
1553 | case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010 |
1554 | tmp = SHR_MACH; |
1555 | break; |
1556 | case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010 |
1557 | tmp = SHR_MACL; |
1558 | break; |
1559 | case 0x22: // STS.L PR,@–Rn 0100nnnn00100010 |
1560 | tmp = SHR_PR; |
1561 | break; |
1562 | case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 |
1563 | tmp = SHR_SR; |
1564 | break; |
1565 | case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 |
1566 | tmp = SHR_GBR; |
1567 | break; |
1568 | case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 |
1569 | tmp = SHR_VBR; |
1570 | break; |
1571 | default: |
e898de13 |
1572 | goto default_; |
ed8cf79b |
1573 | } |
1574 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1575 | emith_sub_r_imm(tmp2, 4); |
1576 | rcache_clean(); |
1577 | rcache_get_reg_arg(0, GET_Rn()); |
1578 | tmp3 = rcache_get_reg_arg(1, tmp); |
1579 | if (tmp == SHR_SR) |
e05b81fc |
1580 | emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0 |
1581 | emit_memhandler_write(2, pc, drcf.delayed_op); |
ed8cf79b |
1582 | goto end_op; |
1583 | case 0x04: |
1584 | case 0x05: |
1585 | switch (op & 0x3f) |
1586 | { |
1587 | case 0x04: // ROTL Rn 0100nnnn00000100 |
1588 | case 0x05: // ROTR Rn 0100nnnn00000101 |
8796b7ee |
1589 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1590 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1591 | if (drcf.delayed_op) |
1592 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1593 | emith_tpop_carry(sr, 0); // dummy |
ed8cf79b |
1594 | if (op & 1) { |
1595 | emith_rorf(tmp, tmp, 1); |
1596 | } else |
1597 | emith_rolf(tmp, tmp, 1); |
8b4f38f4 |
1598 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1599 | goto end_op; |
1600 | case 0x24: // ROTCL Rn 0100nnnn00100100 |
1601 | case 0x25: // ROTCR Rn 0100nnnn00100101 |
8796b7ee |
1602 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1603 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1604 | if (drcf.delayed_op) |
1605 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1606 | emith_tpop_carry(sr, 0); |
ed8cf79b |
1607 | if (op & 1) { |
1608 | emith_rorcf(tmp); |
1609 | } else |
1610 | emith_rolcf(tmp); |
8b4f38f4 |
1611 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1612 | goto end_op; |
1613 | case 0x15: // CMP/PL Rn 0100nnnn00010101 |
8796b7ee |
1614 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1615 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1616 | if (drcf.delayed_op) |
1617 | DELAY_SAVE_T(sr); |
8796b7ee |
1618 | emith_bic_r_imm(sr, T); |
ed8cf79b |
1619 | emith_cmp_r_imm(tmp, 0); |
1620 | EMITH_SJMP_START(DCOND_LE); |
8796b7ee |
1621 | emith_or_r_imm_c(DCOND_GT, sr, T); |
ed8cf79b |
1622 | EMITH_SJMP_END(DCOND_LE); |
1623 | goto end_op; |
1624 | } |
e898de13 |
1625 | goto default_; |
ed8cf79b |
1626 | case 0x06: |
1627 | case 0x07: |
1628 | switch (op & 0x3f) |
1629 | { |
1630 | case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110 |
1631 | tmp = SHR_MACH; |
1632 | break; |
1633 | case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110 |
1634 | tmp = SHR_MACL; |
1635 | break; |
1636 | case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110 |
1637 | tmp = SHR_PR; |
1638 | break; |
1639 | case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 |
1640 | tmp = SHR_SR; |
1641 | break; |
1642 | case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 |
1643 | tmp = SHR_GBR; |
1644 | break; |
1645 | case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 |
1646 | tmp = SHR_VBR; |
1647 | break; |
1648 | default: |
1649 | goto default_; |
1650 | } |
1651 | rcache_clean(); |
1652 | rcache_get_reg_arg(0, GET_Rn()); |
1653 | tmp2 = emit_memhandler_read(2); |
1654 | if (tmp == SHR_SR) { |
18b94127 |
1655 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1656 | if (drcf.delayed_op) |
1657 | DELAY_SAVE_T(sr); |
1658 | emith_write_sr(sr, tmp2); |
1659 | drcf.test_irq = 1; |
ed8cf79b |
1660 | } else { |
1661 | tmp = rcache_get_reg(tmp, RC_GR_WRITE); |
1662 | emith_move_r_r(tmp, tmp2); |
1663 | } |
1664 | rcache_free_tmp(tmp2); |
1665 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1666 | emith_add_r_imm(tmp, 4); |
1667 | goto end_op; |
52d759c3 |
1668 | case 0x08: |
1669 | case 0x09: |
1670 | switch (GET_Fx()) |
1671 | { |
1672 | case 0: |
1673 | // SHLL2 Rn 0100nnnn00001000 |
1674 | // SHLR2 Rn 0100nnnn00001001 |
1675 | tmp = 2; |
1676 | break; |
1677 | case 1: |
1678 | // SHLL8 Rn 0100nnnn00011000 |
1679 | // SHLR8 Rn 0100nnnn00011001 |
1680 | tmp = 8; |
1681 | break; |
1682 | case 2: |
1683 | // SHLL16 Rn 0100nnnn00101000 |
1684 | // SHLR16 Rn 0100nnnn00101001 |
1685 | tmp = 16; |
1686 | break; |
1687 | default: |
1688 | goto default_; |
1689 | } |
1690 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1691 | if (op & 1) { |
1692 | emith_lsr(tmp2, tmp2, tmp); |
1693 | } else |
1694 | emith_lsl(tmp2, tmp2, tmp); |
1695 | goto end_op; |
1696 | case 0x0a: |
1697 | switch (GET_Fx()) |
1698 | { |
1699 | case 0: // LDS Rm,MACH 0100mmmm00001010 |
1700 | tmp2 = SHR_MACH; |
1701 | break; |
1702 | case 1: // LDS Rm,MACL 0100mmmm00011010 |
1703 | tmp2 = SHR_MACL; |
1704 | break; |
1705 | case 2: // LDS Rm,PR 0100mmmm00101010 |
1706 | tmp2 = SHR_PR; |
1707 | break; |
1708 | default: |
1709 | goto default_; |
1710 | } |
1711 | emit_move_r_r(tmp2, GET_Rn()); |
1712 | goto end_op; |
e898de13 |
1713 | case 0x0b: |
52d759c3 |
1714 | switch (GET_Fx()) |
1715 | { |
1716 | case 0: // JSR @Rm 0100mmmm00001011 |
1717 | case 2: // JMP @Rm 0100mmmm00101011 |
1718 | DELAYED_OP; |
1719 | if (!(op & 0x20)) |
1720 | emit_move_r_imm32(SHR_PR, pc + 2); |
18b94127 |
1721 | emit_move_r_r(SHR_PC, (op >> 8) & 0x0f); |
44e6452e |
1722 | out_pc = (u32)-1; |
52d759c3 |
1723 | cycles++; |
1724 | break; |
1725 | case 1: // TAS.B @Rn 0100nnnn00011011 |
1726 | // XXX: is TAS working on 32X? |
1727 | rcache_clean(); |
1728 | rcache_get_reg_arg(0, GET_Rn()); |
8796b7ee |
1729 | tmp = emit_memhandler_read(0); |
1730 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1731 | if (drcf.delayed_op) |
1732 | DELAY_SAVE_T(sr); |
8796b7ee |
1733 | emith_bic_r_imm(sr, T); |
52d759c3 |
1734 | emith_cmp_r_imm(tmp, 0); |
8796b7ee |
1735 | emit_or_t_if_eq(sr); |
52d759c3 |
1736 | rcache_clean(); |
1737 | emith_or_r_imm(tmp, 0x80); |
1738 | tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp |
1739 | emith_move_r_r(tmp2, tmp); |
1740 | rcache_free_tmp(tmp); |
1741 | rcache_get_reg_arg(0, GET_Rn()); |
e05b81fc |
1742 | emit_memhandler_write(0, pc, drcf.delayed_op); |
52d759c3 |
1743 | cycles += 3; |
1744 | break; |
1745 | default: |
e898de13 |
1746 | goto default_; |
52d759c3 |
1747 | } |
e898de13 |
1748 | goto end_op; |
1749 | case 0x0e: |
52d759c3 |
1750 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1751 | switch (GET_Fx()) |
1752 | { |
1753 | case 0: // LDC Rm,SR 0100mmmm00001110 |
1754 | tmp2 = SHR_SR; |
1755 | break; |
1756 | case 1: // LDC Rm,GBR 0100mmmm00011110 |
1757 | tmp2 = SHR_GBR; |
1758 | break; |
1759 | case 2: // LDC Rm,VBR 0100mmmm00101110 |
1760 | tmp2 = SHR_VBR; |
1761 | break; |
1762 | default: |
e898de13 |
1763 | goto default_; |
52d759c3 |
1764 | } |
1765 | if (tmp2 == SHR_SR) { |
18b94127 |
1766 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1767 | if (drcf.delayed_op) |
1768 | DELAY_SAVE_T(sr); |
1769 | emith_write_sr(sr, tmp); |
1770 | drcf.test_irq = 1; |
52d759c3 |
1771 | } else { |
1772 | tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE); |
1773 | emith_move_r_r(tmp2, tmp); |
1774 | } |
1775 | goto end_op; |
1776 | case 0x0f: |
1777 | // MAC @Rm+,@Rn+ 0100nnnnmmmm1111 |
f0d7b1fa |
1778 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1); |
1779 | emith_sext(tmp, tmp, 16); |
1780 | emith_sext(tmp2, tmp2, 16); |
1781 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); |
1782 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
1783 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
f0d7b1fa |
1784 | rcache_free_tmp(tmp2); |
f0d7b1fa |
1785 | // XXX: MACH should be untouched when S is set? |
8796b7ee |
1786 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
1787 | emith_tst_r_imm(sr, S); |
1788 | EMITH_JMP_START(DCOND_EQ); |
1789 | |
1790 | emith_asr(tmp, tmp3, 31); |
1791 | emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach |
1792 | EMITH_JMP_START(DCOND_EQ); |
1793 | emith_move_r_imm(tmp3, 0x80000000); |
1794 | emith_tst_r_r(tmp4, tmp4); |
1795 | EMITH_SJMP_START(DCOND_MI); |
1796 | emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive |
1797 | EMITH_SJMP_END(DCOND_MI); |
1798 | EMITH_JMP_END(DCOND_EQ); |
1799 | |
1800 | EMITH_JMP_END(DCOND_EQ); |
1801 | rcache_free_tmp(tmp); |
f0d7b1fa |
1802 | cycles += 2; |
1803 | goto end_op; |
679af8a3 |
1804 | } |
1805 | goto default_; |
1806 | |
52d759c3 |
1807 | ///////////////////////////////////////////// |
1808 | case 0x05: |
1809 | // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd |
1810 | rcache_clean(); |
1811 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1812 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
1813 | tmp = emit_memhandler_read(2); |
1814 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1815 | emith_move_r_r(tmp2, tmp); |
1816 | rcache_free_tmp(tmp); |
1817 | goto end_op; |
1818 | |
1819 | ///////////////////////////////////////////// |
1820 | case 0x06: |
1821 | switch (op & 0x0f) |
1822 | { |
1823 | case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000 |
1824 | case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001 |
1825 | case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010 |
1826 | case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100 |
1827 | case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101 |
1828 | case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110 |
1829 | rcache_clean(); |
1830 | rcache_get_reg_arg(0, GET_Rm()); |
1831 | tmp = emit_memhandler_read(op & 3); |
1832 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1833 | if ((op & 3) != 2) { |
1834 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
1835 | } else |
1836 | emith_move_r_r(tmp2, tmp); |
1837 | rcache_free_tmp(tmp); |
1838 | if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) { |
1839 | tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW); |
1840 | emith_add_r_imm(tmp, (1 << (op & 3))); |
1841 | } |
1842 | goto end_op; |
1843 | case 0x03: |
1844 | case 0x07 ... 0x0f: |
1845 | tmp = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1846 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1847 | switch (op & 0x0f) |
1848 | { |
1849 | case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011 |
1850 | emith_move_r_r(tmp2, tmp); |
1851 | break; |
1852 | case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111 |
1853 | emith_mvn_r_r(tmp2, tmp); |
1854 | break; |
1855 | case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000 |
1856 | tmp3 = tmp2; |
1857 | if (tmp == tmp2) |
1858 | tmp3 = rcache_get_tmp(); |
1859 | tmp4 = rcache_get_tmp(); |
1860 | emith_lsr(tmp3, tmp, 16); |
f0d7b1fa |
1861 | emith_or_r_r_lsl(tmp3, tmp, 24); |
52d759c3 |
1862 | emith_and_r_r_imm(tmp4, tmp, 0xff00); |
f0d7b1fa |
1863 | emith_or_r_r_lsl(tmp3, tmp4, 8); |
52d759c3 |
1864 | emith_rol(tmp2, tmp3, 16); |
1865 | rcache_free_tmp(tmp4); |
1866 | if (tmp == tmp2) |
1867 | rcache_free_tmp(tmp3); |
1868 | break; |
1869 | case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001 |
1870 | emith_rol(tmp2, tmp, 16); |
1871 | break; |
1872 | case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 |
8796b7ee |
1873 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1874 | if (drcf.delayed_op) |
1875 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1876 | emith_tpop_carry(sr, 1); |
52d759c3 |
1877 | emith_negcf_r_r(tmp2, tmp); |
8b4f38f4 |
1878 | emith_tpush_carry(sr, 1); |
52d759c3 |
1879 | break; |
1880 | case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011 |
1881 | emith_neg_r_r(tmp2, tmp); |
1882 | break; |
1883 | case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100 |
1884 | emith_clear_msb(tmp2, tmp, 24); |
1885 | break; |
1886 | case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101 |
1887 | emith_clear_msb(tmp2, tmp, 16); |
1888 | break; |
1889 | case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110 |
1890 | emith_sext(tmp2, tmp, 8); |
1891 | break; |
1892 | case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111 |
1893 | emith_sext(tmp2, tmp, 16); |
1894 | break; |
1895 | } |
1896 | goto end_op; |
1897 | } |
1898 | goto default_; |
1899 | |
1900 | ///////////////////////////////////////////// |
1901 | case 0x07: |
1902 | // ADD #imm,Rn 0111nnnniiiiiiii |
1903 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1904 | if (op & 0x80) { // adding negative |
1905 | emith_sub_r_imm(tmp, -op & 0xff); |
1906 | } else |
1907 | emith_add_r_imm(tmp, op & 0xff); |
1908 | goto end_op; |
1909 | |
3863edbd |
1910 | ///////////////////////////////////////////// |
e898de13 |
1911 | case 0x08: |
52d759c3 |
1912 | switch (op & 0x0f00) |
1913 | { |
1914 | case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd |
1915 | case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd |
1916 | rcache_clean(); |
1917 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1918 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
1919 | tmp3 = (op & 0x100) >> 8; |
1920 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
e05b81fc |
1921 | emit_memhandler_write(tmp3, pc, drcf.delayed_op); |
52d759c3 |
1922 | goto end_op; |
1923 | case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd |
1924 | case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd |
1925 | rcache_clean(); |
1926 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1927 | tmp3 = (op & 0x100) >> 8; |
1928 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
1929 | tmp = emit_memhandler_read(tmp3); |
1930 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
1931 | emith_sext(tmp2, tmp, 8 << tmp3); |
1932 | rcache_free_tmp(tmp); |
1933 | goto end_op; |
1934 | case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii |
1935 | // XXX: could use cmn |
1936 | tmp = rcache_get_tmp(); |
1937 | tmp2 = rcache_get_reg(0, RC_GR_READ); |
8796b7ee |
1938 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1939 | if (drcf.delayed_op) |
1940 | DELAY_SAVE_T(sr); |
52d759c3 |
1941 | emith_move_r_imm_s8(tmp, op & 0xff); |
8796b7ee |
1942 | emith_bic_r_imm(sr, T); |
52d759c3 |
1943 | emith_cmp_r_r(tmp2, tmp); |
8796b7ee |
1944 | emit_or_t_if_eq(sr); |
52d759c3 |
1945 | rcache_free_tmp(tmp); |
1946 | goto end_op; |
1947 | case 0x0d00: // BT/S label 10001101dddddddd |
1948 | case 0x0f00: // BF/S label 10001111dddddddd |
679af8a3 |
1949 | DELAYED_OP; |
1950 | cycles--; |
679af8a3 |
1951 | // fallthrough |
44e6452e |
1952 | case 0x0900: // BT label 10001001dddddddd |
1953 | case 0x0b00: // BF label 10001011dddddddd |
1954 | // will handle conditional branches later |
1955 | pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; |
1956 | i = ((signed int)(op << 24) >> 23); |
1957 | pending_branch_pc = pc + i + 2; |
e898de13 |
1958 | cycles += 2; |
e898de13 |
1959 | goto end_op; |
44e6452e |
1960 | } |
679af8a3 |
1961 | goto default_; |
679af8a3 |
1962 | |
52d759c3 |
1963 | ///////////////////////////////////////////// |
1964 | case 0x09: |
1965 | // MOV.W @(disp,PC),Rn 1001nnnndddddddd |
f0d7b1fa |
1966 | rcache_clean(); |
1967 | tmp = rcache_get_tmp_arg(0); |
1968 | emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2); |
1969 | tmp = emit_memhandler_read(1); |
1970 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1971 | emith_sext(tmp2, tmp, 16); |
1972 | rcache_free_tmp(tmp); |
1973 | goto end_op; |
52d759c3 |
1974 | |
3863edbd |
1975 | ///////////////////////////////////////////// |
679af8a3 |
1976 | case 0x0a: |
1977 | // BRA label 1010dddddddddddd |
1978 | DELAYED_OP; |
44e6452e |
1979 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
679af8a3 |
1980 | tmp = ((signed int)(op << 20) >> 19); |
44e6452e |
1981 | out_pc = pc + tmp + 2; |
1982 | if (tmp == (u32)-4) |
1983 | emith_clear_msb(sr, sr, 20); // burn cycles |
679af8a3 |
1984 | cycles++; |
e898de13 |
1985 | break; |
679af8a3 |
1986 | |
3863edbd |
1987 | ///////////////////////////////////////////// |
679af8a3 |
1988 | case 0x0b: |
1989 | // BSR label 1011dddddddddddd |
1990 | DELAYED_OP; |
e898de13 |
1991 | emit_move_r_imm32(SHR_PR, pc + 2); |
44e6452e |
1992 | tmp = ((signed int)(op << 20) >> 19); |
1993 | out_pc = pc + tmp + 2; |
1994 | cycles++; |
1995 | break; |
679af8a3 |
1996 | |
52d759c3 |
1997 | ///////////////////////////////////////////// |
1998 | case 0x0c: |
1999 | switch (op & 0x0f00) |
2000 | { |
2001 | case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd |
2002 | case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd |
2003 | case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd |
2004 | rcache_clean(); |
2005 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
2006 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
2007 | tmp3 = (op & 0x300) >> 8; |
2008 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
e05b81fc |
2009 | emit_memhandler_write(tmp3, pc, drcf.delayed_op); |
52d759c3 |
2010 | goto end_op; |
2011 | case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd |
2012 | case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd |
2013 | case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd |
2014 | rcache_clean(); |
2015 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
2016 | tmp3 = (op & 0x300) >> 8; |
2017 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
2018 | tmp = emit_memhandler_read(tmp3); |
2019 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
2020 | if (tmp3 != 2) { |
2021 | emith_sext(tmp2, tmp, 8 << tmp3); |
2022 | } else |
2023 | emith_move_r_r(tmp2, tmp); |
2024 | rcache_free_tmp(tmp); |
2025 | goto end_op; |
2026 | case 0x0300: // TRAPA #imm 11000011iiiiiiii |
2027 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
2028 | emith_sub_r_imm(tmp, 4*2); |
2029 | rcache_clean(); |
2030 | // push SR |
2031 | tmp = rcache_get_reg_arg(0, SHR_SP); |
2032 | emith_add_r_imm(tmp, 4); |
2033 | tmp = rcache_get_reg_arg(1, SHR_SR); |
18b94127 |
2034 | emith_clear_msb(tmp, tmp, 22); |
e05b81fc |
2035 | emit_memhandler_write(2, pc, drcf.delayed_op); |
52d759c3 |
2036 | // push PC |
2037 | rcache_get_reg_arg(0, SHR_SP); |
2038 | tmp = rcache_get_tmp_arg(1); |
2039 | emith_move_r_imm(tmp, pc); |
e05b81fc |
2040 | emit_memhandler_write(2, pc, drcf.delayed_op); |
52d759c3 |
2041 | // obtain new PC |
2042 | tmp = rcache_get_reg_arg(0, SHR_VBR); |
2043 | emith_add_r_imm(tmp, (op & 0xff) * 4); |
2044 | tmp = emit_memhandler_read(2); |
2045 | tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
2046 | emith_move_r_r(tmp2, tmp); |
2047 | rcache_free_tmp(tmp); |
44e6452e |
2048 | out_pc = (u32)-1; |
52d759c3 |
2049 | cycles += 7; |
44e6452e |
2050 | goto end_op; |
52d759c3 |
2051 | case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd |
2052 | emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3); |
2053 | goto end_op; |
2054 | case 0x0800: // TST #imm,R0 11001000iiiiiiii |
8796b7ee |
2055 | tmp = rcache_get_reg(SHR_R0, RC_GR_READ); |
2056 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2057 | if (drcf.delayed_op) |
2058 | DELAY_SAVE_T(sr); |
8796b7ee |
2059 | emith_bic_r_imm(sr, T); |
52d759c3 |
2060 | emith_tst_r_imm(tmp, op & 0xff); |
8796b7ee |
2061 | emit_or_t_if_eq(sr); |
52d759c3 |
2062 | goto end_op; |
2063 | case 0x0900: // AND #imm,R0 11001001iiiiiiii |
2064 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2065 | emith_and_r_imm(tmp, op & 0xff); |
2066 | goto end_op; |
2067 | case 0x0a00: // XOR #imm,R0 11001010iiiiiiii |
2068 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2069 | emith_eor_r_imm(tmp, op & 0xff); |
2070 | goto end_op; |
2071 | case 0x0b00: // OR #imm,R0 11001011iiiiiiii |
2072 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2073 | emith_or_r_imm(tmp, op & 0xff); |
2074 | goto end_op; |
2075 | case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii |
8796b7ee |
2076 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2077 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2078 | if (drcf.delayed_op) |
2079 | DELAY_SAVE_T(sr); |
8796b7ee |
2080 | emith_bic_r_imm(sr, T); |
52d759c3 |
2081 | emith_tst_r_imm(tmp, op & 0xff); |
8796b7ee |
2082 | emit_or_t_if_eq(sr); |
52d759c3 |
2083 | rcache_free_tmp(tmp); |
2084 | cycles += 2; |
2085 | goto end_op; |
2086 | case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii |
2087 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2088 | emith_and_r_imm(tmp, op & 0xff); |
8796b7ee |
2089 | goto end_rmw_op; |
52d759c3 |
2090 | case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii |
2091 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2092 | emith_eor_r_imm(tmp, op & 0xff); |
8796b7ee |
2093 | goto end_rmw_op; |
52d759c3 |
2094 | case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii |
2095 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2096 | emith_or_r_imm(tmp, op & 0xff); |
8796b7ee |
2097 | end_rmw_op: |
2098 | tmp2 = rcache_get_tmp_arg(1); |
2099 | emith_move_r_r(tmp2, tmp); |
2100 | rcache_free_tmp(tmp); |
2101 | tmp3 = rcache_get_reg_arg(0, SHR_GBR); |
2102 | tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ); |
2103 | emith_add_r_r(tmp3, tmp4); |
e05b81fc |
2104 | emit_memhandler_write(0, pc, drcf.delayed_op); |
52d759c3 |
2105 | cycles += 2; |
2106 | goto end_op; |
2107 | } |
2108 | goto default_; |
2109 | |
2110 | ///////////////////////////////////////////// |
2111 | case 0x0d: |
2112 | // MOV.L @(disp,PC),Rn 1101nnnndddddddd |
f0d7b1fa |
2113 | rcache_clean(); |
2114 | tmp = rcache_get_tmp_arg(0); |
2115 | emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3); |
2116 | tmp = emit_memhandler_read(2); |
2117 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
2118 | emith_move_r_r(tmp2, tmp); |
2119 | rcache_free_tmp(tmp); |
2120 | goto end_op; |
52d759c3 |
2121 | |
2122 | ///////////////////////////////////////////// |
2123 | case 0x0e: |
2124 | // MOV #imm,Rn 1110nnnniiiiiiii |
2125 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
2126 | emith_move_r_imm_s8(tmp, op & 0xff); |
2127 | goto end_op; |
2128 | |
679af8a3 |
2129 | default: |
2130 | default_: |
f0d7b1fa |
2131 | elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", |
2132 | sh2->is_slave ? 's' : 'm', op, pc - 2); |
2133 | #ifdef DRC_DEBUG_INTERP |
679af8a3 |
2134 | emit_move_r_imm32(SHR_PC, pc - 2); |
c18edb34 |
2135 | rcache_flush(); |
f4bb5d6b |
2136 | emith_pass_arg_r(0, CONTEXT_REG); |
2137 | emith_pass_arg_imm(1, op); |
679af8a3 |
2138 | emith_call(sh2_do_op); |
f0d7b1fa |
2139 | #endif |
679af8a3 |
2140 | break; |
2141 | } |
2142 | |
e898de13 |
2143 | end_op: |
44e6452e |
2144 | // conditional branch handling (with/without delay) |
2145 | if (pending_branch_cond != -1 && drcf.delayed_op != 2) |
2146 | { |
2147 | u32 target_pc = pending_branch_pc; |
2148 | void *target; |
2149 | |
18b94127 |
2150 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2151 | // handle cycles |
e05b81fc |
2152 | FLUSH_CYCLES(sr); |
18b94127 |
2153 | rcache_clean(); |
18b94127 |
2154 | if (drcf.use_saved_t) |
2155 | emith_tst_r_imm(sr, T_save); |
2156 | else |
2157 | emith_tst_r_imm(sr, T); |
18b94127 |
2158 | |
44e6452e |
2159 | if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) { |
2160 | // local branch |
2161 | // XXX: jumps back can be linked already |
2162 | branch_patch_pc[branch_patch_count] = target_pc; |
2163 | branch_patch_ptr[branch_patch_count] = tcache_ptr; |
2164 | emith_jump_cond_patchable(pending_branch_cond, tcache_ptr); |
2165 | |
2166 | branch_patch_count++; |
2167 | if (branch_patch_count == MAX_LOCAL_BRANCHES) { |
2168 | printf("warning: too many local branches\n"); |
2169 | break; |
2170 | } |
2171 | } |
2172 | else { |
2173 | // can't resolve branch locally, make a block exit |
2174 | emit_move_r_imm32(SHR_PC, target_pc); |
2175 | rcache_clean(); |
2176 | |
2177 | target = dr_prepare_ext_branch(target_pc, sh2, tcache_id); |
2178 | if (target == NULL) |
2179 | return NULL; |
2180 | emith_jump_cond_patchable(pending_branch_cond, target); |
18b94127 |
2181 | } |
44e6452e |
2182 | |
2183 | drcf.use_saved_t = 0; |
2184 | pending_branch_cond = -1; |
e898de13 |
2185 | } |
44e6452e |
2186 | |
18b94127 |
2187 | // test irq? |
e05b81fc |
2188 | // XXX: delay slots.. |
2189 | if (drcf.test_irq && drcf.delayed_op != 2) { |
2190 | if (!drcf.delayed_op) |
2191 | emit_move_r_imm32(SHR_PC, pc); |
2192 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2193 | FLUSH_CYCLES(sr); |
2194 | rcache_flush(); |
2195 | emith_call(sh2_drc_test_irq); |
2196 | drcf.test_irq = 0; |
2197 | } |
e898de13 |
2198 | |
f4bb5d6b |
2199 | do_host_disasm(tcache_id); |
52d759c3 |
2200 | |
44e6452e |
2201 | if (out_pc != 0 && drcf.delayed_op != 2) |
2202 | break; |
2203 | } |
f4bb5d6b |
2204 | |
18b94127 |
2205 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
e05b81fc |
2206 | FLUSH_CYCLES(tmp); |
18b94127 |
2207 | rcache_flush(); |
44e6452e |
2208 | |
2209 | if (out_pc == (u32)-1) { |
2210 | // indirect jump -> back to dispatcher |
2211 | emith_jump(sh2_drc_dispatcher); |
2212 | } else { |
2213 | void *target; |
2214 | if (out_pc == 0) |
2215 | out_pc = pc; |
2216 | emit_move_r_imm32(SHR_PC, out_pc); |
2217 | rcache_flush(); |
2218 | |
2219 | target = dr_prepare_ext_branch(out_pc, sh2, tcache_id); |
2220 | if (target == NULL) |
2221 | return NULL; |
2222 | emith_jump_patchable(target); |
2223 | } |
18b94127 |
2224 | |
2225 | // link local branches |
2226 | for (i = 0; i < branch_patch_count; i++) { |
2227 | void *target; |
2228 | int t; |
18b94127 |
2229 | t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]); |
44e6452e |
2230 | target = branch_target_ptr[t]; |
2231 | if (target == NULL) { |
2232 | // flush pc and go back to dispatcher (should no longer happen) |
18b94127 |
2233 | printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr); |
2234 | target = tcache_ptr; |
2235 | emit_move_r_imm32(SHR_PC, branch_patch_pc[i]); |
2236 | rcache_flush(); |
e05b81fc |
2237 | emith_jump(sh2_drc_dispatcher); |
18b94127 |
2238 | } |
2239 | emith_jump_patch(branch_patch_ptr[i], target); |
2240 | } |
2241 | |
44e6452e |
2242 | this_block->end_addr = pc; |
2243 | |
f4bb5d6b |
2244 | // mark memory blocks as containing compiled code |
18b94127 |
2245 | if (tcache_id != 0) { |
f4bb5d6b |
2246 | // data array, BIOS |
2247 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
18b94127 |
2248 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
f4bb5d6b |
2249 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
18b94127 |
2250 | drcblk[tmp] = (blkid_main << 1) | 1; |
f4bb5d6b |
2251 | for (++tmp; tmp < tmp2; tmp++) { |
2252 | if (drcblk[tmp]) |
18b94127 |
2253 | continue; // dont overwrite overlay block(s) |
2254 | drcblk[tmp] = blkid_main << 1; |
f4bb5d6b |
2255 | } |
2256 | } |
2257 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
18b94127 |
2258 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
f4bb5d6b |
2259 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
18b94127 |
2260 | Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1; |
f4bb5d6b |
2261 | for (++tmp; tmp < tmp2; tmp++) { |
2262 | if (Pico32xMem->drcblk_ram[tmp]) |
18b94127 |
2263 | continue; |
2264 | Pico32xMem->drcblk_ram[tmp] = blkid_main << 1; |
f4bb5d6b |
2265 | } |
679af8a3 |
2266 | } |
2267 | |
f4bb5d6b |
2268 | tcache_ptrs[tcache_id] = tcache_ptr; |
2269 | |
553c3eaa |
2270 | #ifdef ARM |
2271 | cache_flush_d_inval_i(block_entry, tcache_ptr); |
2272 | #endif |
2273 | |
f4bb5d6b |
2274 | do_host_disasm(tcache_id); |
2275 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
2276 | tcache_id, block_counts[tcache_id], |
2277 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
2278 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
2279 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
2280 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
18b94127 |
2281 | /* |
2282 | printf("~~~\n"); |
2283 | tcache_dsm_ptrs[tcache_id] = block_entry; |
2284 | do_host_disasm(tcache_id); |
2285 | printf("~~~\n"); |
2286 | */ |
2287 | |
553c3eaa |
2288 | #if (DRC_DEBUG & 2) |
2289 | fflush(stdout); |
2290 | #endif |
2291 | |
679af8a3 |
2292 | return block_entry; |
679af8a3 |
2293 | } |
2294 | |
e05b81fc |
2295 | static void sh2_generate_utils(void) |
679af8a3 |
2296 | { |
e05b81fc |
2297 | int arg0, arg1, arg2, sr, tmp; |
2298 | void *sh2_drc_write_end, *sh2_drc_write_slot_end; |
52d759c3 |
2299 | |
e05b81fc |
2300 | host_arg2reg(arg0, 0); |
2301 | host_arg2reg(arg1, 1); |
2302 | host_arg2reg(arg2, 2); |
2303 | emith_move_r_r(arg0, arg0); // nop |
679af8a3 |
2304 | |
e05b81fc |
2305 | // sh2_drc_exit(void) |
2306 | sh2_drc_exit = (void *)tcache_ptr; |
2307 | emit_do_static_regs(1, arg2); |
2308 | emith_sh2_drc_exit(); |
679af8a3 |
2309 | |
e05b81fc |
2310 | // sh2_drc_dispatcher(void) |
2311 | sh2_drc_dispatcher = (void *)tcache_ptr; |
2312 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
2313 | emith_cmp_r_imm(sr, 0); |
2314 | emith_jump_cond(DCOND_LT, sh2_drc_exit); |
2315 | rcache_invalidate(); |
2316 | emith_ctx_read(arg0, SHR_PC * 4); |
2317 | emith_ctx_read(arg1, offsetof(SH2, is_slave)); |
2318 | emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp)); |
2319 | emith_call(lookup_block); |
2320 | emit_block_entry(); |
2321 | // lookup failed, call sh2_translate() |
2322 | emith_move_r_r(arg0, CONTEXT_REG); |
2323 | emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id |
2324 | emith_call(sh2_translate); |
2325 | emit_block_entry(); |
2326 | // sh2_translate() failed, flush cache and retry |
2327 | emith_ctx_read(arg0, offsetof(SH2, drc_tmp)); |
2328 | emith_call(flush_tcache); |
2329 | emith_move_r_r(arg0, CONTEXT_REG); |
2330 | emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); |
2331 | emith_call(sh2_translate); |
2332 | emit_block_entry(); |
2333 | // XXX: can't translate, fail |
2334 | emith_call(exit); |
2335 | |
2336 | // sh2_drc_test_irq(void) |
2337 | // assumes it's called from main function (may jump to dispatcher) |
2338 | sh2_drc_test_irq = (void *)tcache_ptr; |
2339 | emith_ctx_read(arg1, offsetof(SH2, pending_level)); |
2340 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
2341 | emith_lsr(arg0, sr, I_SHIFT); |
2342 | emith_and_r_imm(arg0, 0x0f); |
2343 | emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)? |
2344 | EMITH_SJMP_START(DCOND_GT); |
2345 | emith_ret_c(DCOND_LE); // nope, return |
2346 | EMITH_SJMP_END(DCOND_GT); |
2347 | // adjust SP |
2348 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
2349 | emith_sub_r_imm(tmp, 4*2); |
2350 | rcache_clean(); |
2351 | // push SR |
2352 | tmp = rcache_get_reg_arg(0, SHR_SP); |
2353 | emith_add_r_imm(tmp, 4); |
2354 | tmp = rcache_get_reg_arg(1, SHR_SR); |
2355 | emith_clear_msb(tmp, tmp, 22); |
2356 | emith_move_r_r(arg2, CONTEXT_REG); |
2357 | emith_call(p32x_sh2_write32); |
2358 | rcache_invalidate(); |
2359 | // push PC |
2360 | rcache_get_reg_arg(0, SHR_SP); |
2361 | emith_ctx_read(arg1, SHR_PC * 4); |
2362 | emith_move_r_r(arg2, CONTEXT_REG); |
2363 | emith_call(p32x_sh2_write32); |
2364 | rcache_invalidate(); |
2365 | // update I, cycles, do callback |
2366 | emith_ctx_read(arg1, offsetof(SH2, pending_level)); |
2367 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2368 | emith_bic_r_imm(sr, I); |
2369 | emith_or_r_r_lsl(sr, arg1, I_SHIFT); |
2370 | emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles |
2371 | rcache_flush(); |
2372 | emith_move_r_r(arg0, CONTEXT_REG); |
2373 | emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level); |
2374 | // obtain new PC |
2375 | emith_lsl(arg0, arg0, 2); |
2376 | emith_ctx_read(arg1, SHR_VBR * 4); |
2377 | emith_add_r_r(arg0, arg1); |
2378 | emit_memhandler_read(2); |
2379 | emith_ctx_write(arg0, SHR_PC * 4); |
2380 | #ifdef __i386__ |
2381 | emith_add_r_imm(xSP, 4); // fix stack |
2382 | #endif |
2383 | emith_jump(sh2_drc_dispatcher); |
2384 | rcache_invalidate(); |
2385 | |
2386 | // sh2_drc_entry(SH2 *sh2) |
2387 | sh2_drc_entry = (void *)tcache_ptr; |
2388 | emith_sh2_drc_entry(); |
2389 | emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0 |
2390 | emit_do_static_regs(0, arg2); |
2391 | emith_call(sh2_drc_test_irq); |
2392 | emith_jump(sh2_drc_dispatcher); |
2393 | |
2394 | // write-caused irq detection |
2395 | sh2_drc_write_end = tcache_ptr; |
2396 | emith_tst_r_r(arg0, arg0); |
2397 | EMITH_SJMP_START(DCOND_NE); |
2398 | emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return |
2399 | EMITH_SJMP_END(DCOND_NE); |
2400 | // since PC is up to date, jump to it's block instead of returning |
2401 | emith_call(sh2_drc_test_irq); |
2402 | emith_jump_ctx(offsetof(SH2, drc_tmp)); |
2403 | |
2404 | // write-caused irq detection for writes in delay slot |
2405 | sh2_drc_write_slot_end = tcache_ptr; |
2406 | emith_tst_r_r(arg0, arg0); |
2407 | EMITH_SJMP_START(DCOND_NE); |
2408 | emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); |
2409 | EMITH_SJMP_END(DCOND_NE); |
2410 | // just burn cycles to get back to dispatcher after branch is handled |
2411 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2412 | emith_ctx_write(sr, offsetof(SH2, irq_cycles)); |
2413 | emith_clear_msb(sr, sr, 20); // clear cycles |
2414 | rcache_flush(); |
2415 | emith_jump_ctx(offsetof(SH2, drc_tmp)); |
2416 | |
2417 | // sh2_drc_write8(u32 a, u32 d) |
2418 | sh2_drc_write8 = (void *)tcache_ptr; |
2419 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2420 | emith_ctx_read(arg2, offsetof(SH2, write8_tab)); |
2421 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); |
2422 | |
2423 | // sh2_drc_write16(u32 a, u32 d) |
2424 | sh2_drc_write16 = (void *)tcache_ptr; |
2425 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2426 | emith_ctx_read(arg2, offsetof(SH2, write16_tab)); |
2427 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); |
2428 | |
2429 | // sh2_drc_write8_slot(u32 a, u32 d) |
2430 | sh2_drc_write8_slot = (void *)tcache_ptr; |
2431 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2432 | emith_ctx_read(arg2, offsetof(SH2, write8_tab)); |
2433 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); |
2434 | |
2435 | // sh2_drc_write16_slot(u32 a, u32 d) |
2436 | sh2_drc_write16_slot = (void *)tcache_ptr; |
2437 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2438 | emith_ctx_read(arg2, offsetof(SH2, write16_tab)); |
2439 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); |
2440 | |
2441 | rcache_invalidate(); |
2442 | #if (DRC_DEBUG & 2) |
2443 | host_dasm_new_symbol(sh2_drc_entry); |
2444 | host_dasm_new_symbol(sh2_drc_dispatcher); |
2445 | host_dasm_new_symbol(sh2_drc_exit); |
2446 | host_dasm_new_symbol(sh2_drc_test_irq); |
2447 | host_dasm_new_symbol(sh2_drc_write_end); |
2448 | host_dasm_new_symbol(sh2_drc_write_slot_end); |
2449 | host_dasm_new_symbol(sh2_drc_write8); |
2450 | host_dasm_new_symbol(sh2_drc_write8_slot); |
2451 | host_dasm_new_symbol(sh2_drc_write16); |
2452 | host_dasm_new_symbol(sh2_drc_write16_slot); |
679af8a3 |
2453 | #endif |
679af8a3 |
2454 | } |
2455 | |
f4bb5d6b |
2456 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
2457 | { |
2458 | u16 id = *p >> 1; |
2459 | block_desc *bd = btab + id; |
2460 | |
18b94127 |
2461 | // FIXME: skip subblocks; do both directions |
44e6452e |
2462 | // FIXME: collect all branches |
f4bb5d6b |
2463 | dbg(1, " killing block %08x", bd->addr); |
2464 | bd->addr = bd->end_addr = 0; |
2465 | |
2466 | while (p > drcblk && (p[-1] >> 1) == id) |
2467 | p--; |
2468 | |
2469 | // check for possible overlay block |
2470 | if (p > 0 && p[-1] != 0) { |
2471 | bd = btab + (p[-1] >> 1); |
2472 | if (bd->addr <= a && a < bd->end_addr) |
2473 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
2474 | } |
2475 | |
2476 | do { |
2477 | *p++ = 0; |
2478 | } |
2479 | while ((*p >> 1) == id); |
2480 | } |
2481 | |
2482 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
2483 | { |
2484 | u16 *drcblk = Pico32xMem->drcblk_ram; |
2485 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
2486 | |
2487 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
2488 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
2489 | } |
2490 | |
2491 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
2492 | { |
2493 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
2494 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
2495 | |
2496 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
2497 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
2498 | } |
2499 | |
52d759c3 |
2500 | void sh2_execute(SH2 *sh2c, int cycles) |
679af8a3 |
2501 | { |
e05b81fc |
2502 | int ret_cycles; |
52d759c3 |
2503 | sh2 = sh2c; // XXX |
2504 | |
2505 | sh2c->cycles_aim += cycles; |
2506 | cycles = sh2c->cycles_aim - sh2c->cycles_done; |
679af8a3 |
2507 | |
2508 | // cycles are kept in SHR_SR unused bits (upper 20) |
18b94127 |
2509 | // bit19 contains T saved for delay slot |
2510 | // others are usual SH2 flags |
52d759c3 |
2511 | sh2c->sr &= 0x3f3; |
2512 | sh2c->sr |= cycles << 12; |
e05b81fc |
2513 | sh2_drc_entry(sh2c); |
679af8a3 |
2514 | |
e05b81fc |
2515 | // TODO: irq cycles |
2516 | ret_cycles = (signed int)sh2c->sr >> 12; |
2517 | if (ret_cycles > 0) |
2518 | printf("warning: drc returned with cycles: %d\n", ret_cycles); |
679af8a3 |
2519 | |
e05b81fc |
2520 | sh2c->cycles_done += cycles - ret_cycles; |
679af8a3 |
2521 | } |
2522 | |
f4bb5d6b |
2523 | #if (DRC_DEBUG & 1) |
2524 | static void block_stats(void) |
2525 | { |
2526 | int c, b, i, total = 0; |
2527 | |
2528 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
2529 | for (i = 0; i < block_counts[b]; i++) |
2530 | if (block_tables[b][i].addr != 0) |
2531 | total += block_tables[b][i].refcount; |
2532 | |
2533 | for (c = 0; c < 10; c++) { |
2534 | block_desc *blk, *maxb = NULL; |
2535 | int max = 0; |
2536 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
2537 | for (i = 0; i < block_counts[b]; i++) { |
2538 | blk = &block_tables[b][i]; |
2539 | if (blk->addr != 0 && blk->refcount > max) { |
2540 | max = blk->refcount; |
2541 | maxb = blk; |
2542 | } |
2543 | } |
2544 | } |
2545 | if (maxb == NULL) |
2546 | break; |
2547 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
2548 | (double)maxb->refcount / total * 100.0); |
2549 | maxb->refcount = 0; |
2550 | } |
553c3eaa |
2551 | |
2552 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
2553 | for (i = 0; i < block_counts[b]; i++) |
2554 | block_tables[b][i].refcount = 0; |
f4bb5d6b |
2555 | } |
553c3eaa |
2556 | #else |
2557 | #define block_stats() |
f4bb5d6b |
2558 | #endif |
2559 | |
553c3eaa |
2560 | void sh2_drc_flush_all(void) |
2561 | { |
2562 | block_stats(); |
2563 | flush_tcache(0); |
2564 | flush_tcache(1); |
2565 | flush_tcache(2); |
2566 | } |
2567 | |
679af8a3 |
2568 | int sh2_drc_init(SH2 *sh2) |
2569 | { |
44e6452e |
2570 | int i; |
7f5a3fc1 |
2571 | |
44e6452e |
2572 | if (block_tables[0] == NULL) |
2573 | { |
2574 | for (i = 0; i < TCACHE_BUFFERS; i++) { |
2575 | block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0])); |
2576 | if (block_tables[i] == NULL) |
2577 | goto fail; |
2578 | // max 2 block links (exits) per block |
2579 | block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0])); |
2580 | if (block_links[i] == NULL) |
2581 | goto fail; |
2582 | } |
2583 | memset(block_counts, 0, sizeof(block_counts)); |
2584 | memset(block_link_counts, 0, sizeof(block_link_counts)); |
e898de13 |
2585 | |
44e6452e |
2586 | drc_cmn_init(); |
8796b7ee |
2587 | tcache_ptr = tcache; |
2588 | sh2_generate_utils(); |
8b4f38f4 |
2589 | #ifdef ARM |
2590 | cache_flush_d_inval_i(tcache, tcache_ptr); |
2591 | #endif |
8796b7ee |
2592 | |
8796b7ee |
2593 | tcache_bases[0] = tcache_ptrs[0] = tcache_ptr; |
44e6452e |
2594 | for (i = 1; i < ARRAY_SIZE(tcache_bases); i++) |
f4bb5d6b |
2595 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
f4bb5d6b |
2596 | |
553c3eaa |
2597 | // tmp |
2598 | PicoOpt |= POPT_DIS_VDP_FIFO; |
2599 | |
f4bb5d6b |
2600 | #if (DRC_DEBUG & 2) |
2601 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
2602 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
8796b7ee |
2603 | // disasm the utils |
2604 | tcache_dsm_ptrs[0] = tcache; |
2605 | do_host_disasm(0); |
f4bb5d6b |
2606 | #endif |
e898de13 |
2607 | #if (DRC_DEBUG & 1) |
2608 | hash_collisions = 0; |
2609 | #endif |
679af8a3 |
2610 | } |
2611 | |
f4bb5d6b |
2612 | if (hash_table == NULL) { |
2613 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
2614 | if (hash_table == NULL) |
44e6452e |
2615 | goto fail; |
f4bb5d6b |
2616 | } |
41397701 |
2617 | |
679af8a3 |
2618 | return 0; |
44e6452e |
2619 | |
2620 | fail: |
2621 | sh2_drc_finish(sh2); |
2622 | return -1; |
41397701 |
2623 | } |
2624 | |
e898de13 |
2625 | void sh2_drc_finish(SH2 *sh2) |
2626 | { |
44e6452e |
2627 | int i; |
2628 | |
f4bb5d6b |
2629 | if (block_tables[0] != NULL) { |
f4bb5d6b |
2630 | block_stats(); |
44e6452e |
2631 | |
2632 | for (i = 0; i < TCACHE_BUFFERS; i++) { |
2633 | #if (DRC_DEBUG & 2) |
2634 | printf("~~~ tcache %d\n", i); |
2635 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
2636 | tcache_ptr = tcache_ptrs[i]; |
2637 | do_host_disasm(i); |
2638 | #endif |
2639 | |
2640 | if (block_tables[i] != NULL) |
2641 | free(block_tables[i]); |
2642 | block_tables[i] = NULL; |
2643 | if (block_links[i] == NULL) |
2644 | free(block_links[i]); |
2645 | block_links[i] = NULL; |
2646 | } |
7f5a3fc1 |
2647 | |
2648 | drc_cmn_cleanup(); |
e898de13 |
2649 | } |
2650 | |
f4bb5d6b |
2651 | if (hash_table != NULL) { |
2652 | free(hash_table); |
2653 | hash_table = NULL; |
2654 | } |
e898de13 |
2655 | } |