1 #include "../pico_int.h"
7 #define ash2_end_run(x)
11 static const char str_mars[] = "MARS";
13 struct Pico32xMem *Pico32xMem;
15 static void bank_switch(int b);
18 #define POLL_THRESHOLD 6
21 u32 addr, cycles, cyc_max;
24 static struct poll_det m68k_poll, sh2_poll[2];
26 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
28 int ret = 0, flag = pd->flag;
33 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
35 if (pd->cnt > POLL_THRESHOLD) {
36 if (!(Pico32x.emu_flags & flag)) {
37 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
38 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
39 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
42 Pico32x.emu_flags |= flag;
54 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
56 int ret = 0, flag = pd->flag;
58 flag <<= 3; // VDP only
60 flag |= flag << 3; // both
61 if (Pico32x.emu_flags & flag) {
62 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
65 Pico32x.emu_flags &= ~flag;
66 pd->addr = pd->cnt = 0;
70 void p32x_poll_event(int cpu_mask, int is_vdp)
73 p32x_poll_undetect(&sh2_poll[0], is_vdp);
75 p32x_poll_undetect(&sh2_poll[1], is_vdp);
82 static const u16 comm_fakevals[] = {
83 0x4d5f, 0x4f4b, // M_OK
84 0x535f, 0x4f4b, // S_OK
85 0x4D41, 0x5346, // MASF - Brutal Unleashed
86 0x5331, 0x4d31, // Darxide
89 0x0000, 0x0000, // eq for doom
90 0x0002, // Mortal Kombat
94 static u32 sh2_comm_faker(u32 a)
97 if (a == 0x28 && !p32x_csum_faked) {
99 return *(unsigned short *)(Pico.rom + 0x18e);
101 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
103 return comm_fakevals[f++];
109 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
110 unsigned int chcr0; // chan ctl
111 unsigned int sar1, dar1, tcr1; // same for chan 1
117 static void dma_68k2sh2_do(void)
119 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
122 if (dmac0->tcr0 != *dreqlen)
123 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
125 // HACK: assume bus is busy and SH2 is halted
126 // XXX: use different mechanism for this, not poll det
127 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
129 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
130 extern void p32x_sh2_write16(u32 a, u32 d, int id);
131 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
132 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
138 Pico32x.dmac_ptr = 0; // HACK
139 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
141 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
142 if (dmac0->tcr0 == 0) {
143 dmac0->chcr0 |= 2; // DMA has ended normally
144 p32x_poll_undetect(&sh2_poll[0], 0);
148 // ------------------------------------------------------------------
151 static u32 p32x_reg_read16(u32 a)
155 if (a == 2) // INTM, INTS
156 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
158 if ((a & 0x30) == 0x20)
159 return sh2_comm_faker(a);
161 if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
166 if ((a & 0x30) == 0x30)
167 return p32x_pwm_read16(a);
169 return Pico32x.regs[a / 2];
172 static void p32x_reg_write8(u32 a, u32 d)
174 u16 *r = Pico32x.regs;
177 // for things like bset on comm port
180 if (a == 1 && !(r[0] & 1)) {
190 case 0: // adapter ctl
191 r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM);
194 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
195 Pico32x.sh2irqi[0] |= P32XI_CMD;
199 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
200 Pico32x.sh2irqi[1] |= P32XI_CMD;
213 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
220 if ((a & 0x30) == 0x20) {
223 p32x_poll_undetect(&sh2_poll[0], 0);
224 p32x_poll_undetect(&sh2_poll[1], 0);
225 // if some SH2 is busy waiting, it needs to see the result ASAP
226 if (SekCyclesLeftNoMCD > 32)
232 static void p32x_reg_write16(u32 a, u32 d)
234 u16 *r = Pico32x.regs;
237 // for things like bset on comm port
241 case 0x00: // adapter ctl
242 r[0] = (r[0] & 0x83) | (d & P32XS_FM);
244 case 0x10: // DREQ len
247 case 0x12: // FIFO reg
248 if (!(r[6 / 2] & P32XS_68S)) {
249 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
252 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
253 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
254 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
256 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
257 r[6 / 2] |= P32XS_FULL;
263 if ((a & 0x38) == 0x08) {
268 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
270 p32x_poll_undetect(&sh2_poll[0], 0);
271 p32x_poll_undetect(&sh2_poll[1], 0);
273 if (SekCyclesLeftNoMCD > 32)
278 else if ((a & 0x30) == 0x30) {
279 p32x_pwm_write16(a, d);
283 p32x_reg_write8(a + 1, d);
286 // ------------------------------------------------------------------
288 static u32 p32x_vdp_read16(u32 a)
292 return Pico32x.vdp_regs[a / 2];
295 static void p32x_vdp_write8(u32 a, u32 d)
297 u16 *r = Pico32x.vdp_regs;
300 // for FEN checks between writes
303 // TODO: verify what's writeable
306 // priority inversion is handled in palette
307 if ((r[0] ^ d) & P32XV_PRI)
308 Pico32x.dirty_pal = 1;
309 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
311 case 0x05: // fill len
316 Pico32x.pending_fb = d;
317 // if we are blanking and FS bit is changing
318 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
320 Pico32xSwapDRAM(d ^ 1);
321 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
327 static void p32x_vdp_write16(u32 a, u32 d)
330 if (a == 6) { // fill start
331 Pico32x.vdp_regs[6 / 2] = d;
334 if (a == 8) { // fill data
335 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
336 int len = Pico32x.vdp_regs[4 / 2] + 1;
337 a = Pico32x.vdp_regs[6 / 2];
340 a = (a & 0xff00) | ((a + 1) & 0xff);
342 Pico32x.vdp_regs[6 / 2] = a;
343 Pico32x.vdp_regs[8 / 2] = d;
347 p32x_vdp_write8(a | 1, d);
350 // ------------------------------------------------------------------
353 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
355 u16 *r = Pico32x.regs;
359 case 0x00: // adapter/irq ctl
360 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
361 case 0x04: // H count (often as comm too)
362 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
364 return Pico32x.sh2_regs[4 / 2];
365 case 0x10: // DREQ len
370 if ((a & 0x38) == 0x08)
373 if ((a & 0x30) == 0x20) {
374 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
378 if ((a & 0x30) == 0x30) {
379 sh2_poll[cpuid].cnt = 0;
380 return p32x_pwm_read16(a);
386 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
391 Pico32x.regs[0] &= ~P32XS_FM;
392 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
395 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
396 Pico32x.sh2_regs[0] &= ~0x80;
397 Pico32x.sh2_regs[0] |= d & 0x80;
401 Pico32x.sh2_regs[4 / 2] = d & 0xff;
402 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
406 if ((a & 0x30) == 0x20) {
407 u8 *r8 = (u8 *)Pico32x.regs;
409 p32x_poll_undetect(&m68k_poll, 0);
410 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
415 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
420 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
421 Pico32x.regs[a / 2] = d;
422 p32x_poll_undetect(&m68k_poll, 0);
423 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
427 else if ((a & 0x30) == 0x30) {
428 p32x_pwm_write16(a, d);
434 Pico32x.regs[0] &= ~P32XS_FM;
435 Pico32x.regs[0] |= d & P32XS_FM;
437 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
438 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
439 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
440 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
442 Pico32x.sh2irqs &= ~P32XI_PWM;
447 p32x_sh2reg_write8(a | 1, d, cpuid);
454 // ------------------------------------------------------------------
455 // SH2 internal peripherals
456 // we keep them in little endian format
457 static u32 sh2_peripheral_read8(u32 a, int id)
459 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
465 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
469 static u32 sh2_peripheral_read16(u32 a, int id)
471 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
477 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
481 static u32 sh2_peripheral_read32(u32 a, int id)
485 d = Pico32xMem->sh2_peri_regs[id][a / 4];
487 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
491 static void sh2_peripheral_write8(u32 a, u32 d, int id)
493 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
494 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
500 if ((a == 2 && (d & 0x20)) || // transmiter enabled
501 (a == 4 && !(d & 0x80))) { // valid data in TDR
502 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
503 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
504 int level = PREG8(oregs, 0x60) >> 4;
505 int vector = PREG8(oregs, 0x63) & 0x7f;
506 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
507 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
512 static void sh2_peripheral_write16(u32 a, u32 d, int id)
514 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
515 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
521 if ((d & 0xff00) == 0xa500) { // WTCSR
523 p32x_timers_recalc();
525 if ((d & 0xff00) == 0x5a00) // WTCNT
533 static void sh2_peripheral_write32(u32 a, u32 d, int id)
535 u32 *r = Pico32xMem->sh2_peri_regs[id];
536 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
542 // division unit (TODO: verify):
543 case 0x104: // DVDNT: divident L, starts divide
544 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
546 signed int divisor = r[0x100 / 4];
547 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
548 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
552 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
553 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
555 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
556 signed int divisor = r[0x100 / 4];
557 // XXX: undocumented mirroring to 0x118,0x11c?
558 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
559 r[0x11c / 4] = r[0x114 / 4] = divident / divisor;
564 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
565 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
566 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
567 dmac0->tcr0 &= 0xffffff;
569 // HACK: assume 68k starts writing soon and end the timeslice
572 // DREQ is only sent after first 4 words are written.
573 // we do multiple of 4 words to avoid messing up alignment
574 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
575 elprintf(EL_32X, "68k -> sh2 DMA");
581 // ------------------------------------------------------------------
582 // default 32x handlers
583 u32 PicoRead8_32x(u32 a)
586 if ((a & 0xffc0) == 0x5100) { // a15100
587 d = p32x_reg_read16(a);
591 if (!(Pico32x.regs[0] & 1))
594 if ((a & 0xfff0) == 0x5180) { // a15180
595 d = p32x_vdp_read16(a);
599 if ((a & 0xfe00) == 0x5200) { // a15200
600 d = Pico32xMem->pal[(a & 0x1ff) / 2];
605 if ((a & 0xfffc) == 0x30ec) { // a130ec
610 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
620 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
624 u32 PicoRead16_32x(u32 a)
627 if ((a & 0xffc0) == 0x5100) { // a15100
628 d = p32x_reg_read16(a);
632 if (!(Pico32x.regs[0] & 1))
635 if ((a & 0xfff0) == 0x5180) { // a15180
636 d = p32x_vdp_read16(a);
640 if ((a & 0xfe00) == 0x5200) { // a15200
641 d = Pico32xMem->pal[(a & 0x1ff) / 2];
646 if ((a & 0xfffc) == 0x30ec) { // a130ec
647 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
651 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
655 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
659 void PicoWrite8_32x(u32 a, u32 d)
661 if ((a & 0xfc00) == 0x5000)
662 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
664 if ((a & 0xffc0) == 0x5100) { // a15100
665 p32x_reg_write8(a, d);
669 if (!(Pico32x.regs[0] & 1))
672 if ((a & 0xfff0) == 0x5180) { // a15180
673 p32x_vdp_write8(a, d);
678 if ((a & 0xfe00) == 0x5200) { // a15200
679 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
680 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
681 Pico32x.dirty_pal = 1;
686 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
689 void PicoWrite16_32x(u32 a, u32 d)
691 if ((a & 0xfc00) == 0x5000)
692 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
694 if ((a & 0xffc0) == 0x5100) { // a15100
695 p32x_reg_write16(a, d);
699 if (!(Pico32x.regs[0] & 1))
702 if ((a & 0xfff0) == 0x5180) { // a15180
703 p32x_vdp_write16(a, d);
707 if ((a & 0xfe00) == 0x5200) { // a15200
708 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
709 Pico32x.dirty_pal = 1;
714 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
717 // hint vector is writeable
718 static void PicoWrite8_hint(u32 a, u32 d)
720 if ((a & 0xfffc) == 0x0070) {
721 Pico32xMem->m68k_rom[a ^ 1] = d;
725 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
728 static void PicoWrite16_hint(u32 a, u32 d)
730 if ((a & 0xfffc) == 0x0070) {
731 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
735 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
738 void Pico32xSwapDRAM(int b)
740 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
741 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
742 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
743 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
746 static void bank_switch(int b)
748 unsigned int rs, bank;
751 if (bank >= Pico.romsize) {
752 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
756 // 32X ROM (unbanked, XXX: consider mirroring?)
757 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
761 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
762 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
764 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
767 // -----------------------------------------------------------------
769 // -----------------------------------------------------------------
771 u32 p32x_sh2_read8(u32 a, int id)
775 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
776 return Pico32xMem->sh2_rom_m[a ^ 1];
777 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
778 return Pico32xMem->sh2_rom_s[a ^ 1];
780 if ((a & 0xdffc0000) == 0x06000000)
781 return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
783 if ((a & 0xdfc00000) == 0x02000000)
784 if ((a & 0x003fffff) < Pico.romsize)
785 return Pico.rom[(a & 0x3fffff) ^ 1];
787 if ((a & ~0xfff) == 0xc0000000)
788 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
790 if ((a & 0xdffc0000) == 0x04000000) {
791 /* XXX: overwrite readable as normal? */
792 u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
793 return dram[(a & 0x1ffff) ^ 1];
796 if ((a & 0xdfffff00) == 0x4000) {
797 d = p32x_sh2reg_read16(a, id);
801 if ((a & 0xdfffff00) == 0x4100) {
802 d = p32x_vdp_read16(a);
803 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
808 if ((a & 0xdfffff00) == 0x4200) {
809 d = Pico32xMem->pal[(a & 0x1ff) / 2];
813 if ((a & 0xfffffe00) == 0xfffffe00)
814 return sh2_peripheral_read8(a, id);
816 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
817 id ? 's' : 'm', a, d, sh2_pc(id));
826 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
827 id ? 's' : 'm', a, d, sh2_pc(id));
831 u32 p32x_sh2_read16(u32 a, int id)
835 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
836 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
837 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
838 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
840 if ((a & 0xdffc0000) == 0x06000000)
841 return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
843 if ((a & 0xdfc00000) == 0x02000000)
844 if ((a & 0x003fffff) < Pico.romsize)
845 return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
847 if ((a & ~0xfff) == 0xc0000000)
848 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
850 if ((a & 0xdffe0000) == 0x04000000)
851 return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
853 if ((a & 0xdfffff00) == 0x4000) {
854 d = p32x_sh2reg_read16(a, id);
855 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
860 if ((a & 0xdfffff00) == 0x4100) {
861 d = p32x_vdp_read16(a);
862 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
867 if ((a & 0xdfffff00) == 0x4200) {
868 d = Pico32xMem->pal[(a & 0x1ff) / 2];
872 if ((a & 0xfffffe00) == 0xfffffe00)
873 return sh2_peripheral_read16(a, id);
875 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
876 id ? 's' : 'm', a, d, sh2_pc(id));
880 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
881 id ? 's' : 'm', a, d, sh2_pc(id));
885 u32 p32x_sh2_read32(u32 a, int id)
887 if ((a & 0xfffffe00) == 0xfffffe00)
888 return sh2_peripheral_read32(a, id);
890 // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
891 return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
894 void p32x_sh2_write8(u32 a, u32 d, int id)
896 if ((a & 0xdffffc00) == 0x4000)
897 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
898 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
900 if ((a & 0xdffc0000) == 0x06000000) {
901 Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
905 if ((a & 0xdffc0000) == 0x04000000) {
907 if (!(a & 0x20000) || d) {
908 dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
909 dram[(a & 0x1ffff) ^ 1] = d;
914 if ((a & ~0xfff) == 0xc0000000) {
915 Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
919 if ((a & 0xdfffff00) == 0x4100) {
920 p32x_vdp_write8(a, d);
924 if ((a & 0xdfffff00) == 0x4000) {
925 p32x_sh2reg_write8(a, d, id);
929 if ((a & 0xfffffe00) == 0xfffffe00) {
930 sh2_peripheral_write8(a, d, id);
934 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
935 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
938 void p32x_sh2_write16(u32 a, u32 d, int id)
940 if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
941 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
942 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
944 // ignore "Associative purge space"
945 if ((a & 0xf8000000) == 0x40000000)
948 if ((a & 0xdffc0000) == 0x06000000) {
949 ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
953 if ((a & ~0xfff) == 0xc0000000) {
954 ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
958 if ((a & 0xdffc0000) == 0x04000000) {
959 u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
960 if (!(a & 0x20000)) {
965 if (!(d & 0xff00)) d |= *pd & 0xff00;
966 if (!(d & 0x00ff)) d |= *pd & 0x00ff;
971 if ((a & 0xdfffff00) == 0x4100) {
972 sh2_poll[id].cnt = 0; // for poll before VDP accesses
973 p32x_vdp_write16(a, d);
977 if ((a & 0xdffffe00) == 0x4200) {
978 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
979 Pico32x.dirty_pal = 1;
983 if ((a & 0xdfffff00) == 0x4000) {
984 p32x_sh2reg_write16(a, d, id);
988 if ((a & 0xfffffe00) == 0xfffffe00) {
989 sh2_peripheral_write16(a, d, id);
993 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
994 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
997 void p32x_sh2_write32(u32 a, u32 d, int id)
999 if ((a & 0xfffffe00) == 0xfffffe00) {
1000 sh2_peripheral_write32(a, d, id);
1004 p32x_sh2_write16(a, d >> 16, id);
1005 p32x_sh2_write16(a + 2, d, id);
1008 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1009 void PicoMemSetup32x(void)
1016 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
1017 if (Pico32xMem == NULL) {
1018 elprintf(EL_STATUS, "OOM");
1022 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1025 ps = (unsigned short *)Pico32xMem->m68k_rom;
1026 pl = (unsigned int *)Pico32xMem->m68k_rom;
1027 for (i = 1; i < 0xc0/4; i++)
1028 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1031 for (i = 0xc0/2; i < 0x100/2; i++)
1035 ps[0xc0/2] = 0x46fc;
1036 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1037 ps[0xfe/2] = 0x60fe; // jump to self
1039 ps[0xfe/2] = 0x4e75; // rts
1042 // fill remaining mem with ROM
1043 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
1048 FILE *f = fopen("32X_M_BIOS.BIN", "rb");
1051 printf("missing 32X_M_BIOS.BIN\n");
1054 fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f);
1056 f = fopen("32X_S_BIOS.BIN", "rb");
1058 printf("missing 32X_S_BIOS.BIN\n");
1061 fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f);
1064 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) {
1065 int t = Pico32xMem->sh2_rom_m[i];
1066 Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1];
1067 Pico32xMem->sh2_rom_m[i + 1] = t;
1069 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) {
1070 int t = Pico32xMem->sh2_rom_s[i];
1071 Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1];
1072 Pico32xMem->sh2_rom_s[i + 1] = t;
1076 // cartridge area becomes unmapped
1077 // XXX: we take the easy way and don't unmap ROM,
1078 // so that we can avoid handling the RV bit.
1079 // m68k_map_unmap(0x000000, 0x3fffff);
1082 rs = sizeof(Pico32xMem->m68k_rom);
1083 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1084 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1085 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1086 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1091 // 32X ROM (unbanked, XXX: consider mirroring?)
1092 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1095 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1096 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1101 // setup poll detector
1102 m68k_poll.flag = P32XF_68KPOLL;
1103 m68k_poll.cyc_max = 64;
1104 sh2_poll[0].flag = P32XF_MSH2POLL;
1105 sh2_poll[0].cyc_max = 21;
1106 sh2_poll[1].flag = P32XF_SSH2POLL;
1107 sh2_poll[1].cyc_max = 16;