{
case 0xa000:setmirror((V&1)^1);break;
case 0x8000:// DumpMem("out",0x0000,0xFFFF);
- cmd=V;DoPRG();DoCHR();break;
+ cmd=V;DoPRG();DoCHR();
+ X6502_Rebase();break;
case 0x8001:regs[cmd&7]=V;
- if((cmd&7)==4 || (cmd&7)==5)
+ if((cmd&7)==4 || (cmd&7)==5) {
DoPRG();
- else
+ X6502_Rebase();
+ } else
DoCHR();
break;
}
{
setprg32(0x8000,GameMemBlock[0]&3);
setchr8(GameMemBlock[0]&7);
+ X6502_Rebase();
}
static DECLFW(NovelWrite)
static void NovelReset(void)
{
SetWriteHandler(0x8000,0xFFFF,NovelWrite);
- SetReadHandler(0x8000,0xFFFF,CartBR);
+ SetReadHandler(0x8000,0xFFFF,CartBR);
setprg32(0x8000,0);
setchr8(0);
}
static void S74LS374NSynco(void)
{
setprg32(0x8000,latch[0]);
+ X6502_Rebase();
setchr8(latch[1]);
setmirror(latch[2]&1);
// setchr8(6);
A&=0x4101;
if(A==0x4100)
cmd=V&7;
- else
+ else
{
switch(cmd)
{
int x;
setprg32(0x8000,latch[5]&7);
+ X6502_Rebase();
if(!UNIFchrrama) // No CHR RAM? Then BS'ing is ok.
{
{
A&=0x4101;
if(A==0x4100) cmd=V;
- else
+ else
{
latch[cmd&7]=V;
S8259Synco();
static void SA0161MSynco()
{
- setprg32(0x8000,(latch[0]>>3)&1);
+ setprg32(0x8000,(latch[0]>>3)&1);
+ X6502_Rebase();
setchr8(latch[0]&7);
}
static void SA72007Synco()
{
setprg32(0x8000,0);
+ X6502_Rebase();
setchr8(latch[0]>>7);
}
static void SA72008Synco()
{
setprg32(0x8000,(latch[0]>>2)&1);
+ X6502_Rebase();
setchr8(latch[0]&3);
}
static void SA0036Synco()
{
setprg32(0x8000,0);
+ X6502_Rebase();
setchr8(latch[0]>>7);
}
static void SA0037Synco()
{
setprg32(0x8000,(latch[0]>>3)&1);
+ X6502_Rebase();
setchr8(latch[0]&7);
}
static void TCU01Synco()
{
setprg32(0x8000,(latch[0]>>2)&1);
+ X6502_Rebase();
setchr8((latch[0]>>3)&0xF);
}
setprg32(0x8000,V>>4);
setchr8(V);
latche=V;
+ X6502_Rebase();
}
static void MHROMReset(void)
}
void MHROM_Init(void)
-{
+{
BoardPower=MHROMReset;
AddExState(&latche, 1, 0,"LATC");
PRGmask32[0]&=1;
{
setprg16(0x8000,V);
latche=V;
+ X6502_Rebase();
}
static void UNROMReset(void)
else
{
//V&=masko1[sizer&7]>>1;
- V|=bigbank2*4;
+ V|=bigbank2*4;
setchr2r((V/256)&15,A,V);
}
}
swsetprg8(0x8000,DRegBuf[6]);
swsetprg8(0xC000,~1);
}
+ X6502_Rebase();
}
static INLINE void FixMMC3CHR(int V)
case 5: swsetchr1(cbase^0x1C00,V); break;
case 6: if (MMC3_cmd&0x40) swsetprg8(0xC000,V);
else swsetprg8(0x8000,V);
+ X6502_Rebase();
break;
case 7: swsetprg8(0xA000,V);
+ X6502_Rebase();
break;
}
}
setprg32r(4,0x8000,0);
setmirror(((GameMemBlock[0]&0x20)>>5)^1);
+ X6502_Rebase();
}
static DECLFW(SuperWrite)
static DECLFW(SuperHi)
{
- GameMemBlock[1]=V;
+ GameMemBlock[1]=V;
DoSuper();
}
{
SetWriteHandler(0x6000,0x7FFF,SuperWrite);
SetWriteHandler(0x8000,0xFFFF,SuperHi);
- SetReadHandler(0x6000,0xFFFF,CartBR);
+ SetReadHandler(0x6000,0xFFFF,CartBR);
GameMemBlock[0]=GameMemBlock[1]=0;
setprg32r(4,0x8000,0);
setvram8(CHRRAM);
swi #0x9f0002
mov pc, lr
+
+/* buggy and slow, probably because function call overhead
+@ renderer helper, based on bitbank's method
+.global draw8pix @ uint8 *P, uint8 *C, uint8 *PALRAM @ dest, src, pal
+
+draw8pix:
+ stmfd sp!, {r4,r5}
+
+ ldrb r3, [r1] @ get bit 0 pixels
+ mov r12,#1
+ orr r12,r12,r12,lsl #8
+ orr r12,r12,r12,lsl #16
+ ldrb r1, [r1, #8] @ get bit 1 pixels
+ orr r3, r3, r3, lsl #9 @ shift them over 1 byte + 1 bit
+ orr r3, r3, r3, lsl #18 @ now 4 pixels take up 4 bytes
+ and r4, r12,r3, lsr #7 @ mask off the upper nibble pixels we want
+ and r5, r12,r3, lsr #3 @ mask off the lower nibble pixels we want
+ ldr r2, [r2]
+
+ orr r1, r1, r1, lsl #9 @ process the bit 1 pixels
+ orr r1, r1, r1, lsl #18
+ and r3, r12,r1, lsr #7 @ mask off the upper nibble pixels we want
+ and r1, r12,r1, lsr #3 @ mask off the lower nibble
+ orr r4, r4, r3, lsl #1
+ orr r5, r5, r1, lsl #5
+
+ @ can this be avoided?
+ mov r4, r4, lsl #3 @ *8
+ mov r3, r2, ror r4
+ strb r3, [r0], #1
+ mov r4, r4, lsr #8
+ mov r3, r2, ror r4
+ strb r3, [r0], #1
+ mov r4, r4, lsr #8
+ mov r3, r2, ror r4
+ strb r3, [r0], #1
+ mov r4, r4, lsr #8
+ mov r3, r2, ror r4
+ strb r3, [r0], #1
+
+ mov r5, r5, lsl #3 @ *8
+ mov r3, r2, ror r5
+ strb r3, [r0], #1
+ mov r5, r5, lsr #8
+ mov r3, r2, ror r5
+ strb r3, [r0], #1
+ mov r5, r5, lsr #8
+ mov r3, r2, ror r5
+ strb r3, [r0], #1
+ mov r5, r5, lsr #8
+ mov r3, r2, ror r5
+ strb r3, [r0], #1
+
+ ldmfd sp!, {r4,r5}
+ bx lr
+*/
+
nes_registers[2] = X.Y;
pc_base = 0;
nes_registers[3] = X.PC;
- X6502_rebase_a();
+ X6502_Rebase_a();
nes_registers[4] = X.S << 24;
nes_registers[4]|= X.IRQlow << 8;
nes_registers[7] = (uint32)X.count;
vtoggle=0;
PPU_status&=0x7F;
#ifdef DEBUG_ASM_6502
- cpu_lastval=ret|(PPUGenLatch&0x1F);
+// cpu_lastval=ret|(PPUGenLatch&0x1F);
#endif
return ret|(PPUGenLatch&0x1F);
}
else RefreshAddr++;
if(PPU_hook) PPU_hook(RefreshAddr&0x3fff);
#ifdef DEBUG_ASM_6502
- cpu_lastval=ret;
+// cpu_lastval=ret;
#endif
return ret;
}
{
uint32 t=V<<8;
int x;
-#ifdef DEBUG_ASM_6502
- if (cpu_repeat) { X6502_AddCycles_a(512); return; }
- for(x=0;x<256;x++)
- B2004(0x2004,X.DB=ARead[t+x](t+x));
- X6502_AddCycles_c(512);
-#else
for(x=0;x<256;x++)
B2004(0x2004,X.DB=ARead[t+x](t+x));
X6502_AddCycles(512);
-#endif
}
void BGRender(uint8 *target)
#include "input.h"
#include "movie.h"
+#ifdef DEBUG_ASM_6502
+extern int cpu_repeat;
+extern int cpu_lastval;
+#endif
+
extern INPUTC *FCEU_InitZapper(int w);
extern INPUTC *FCEU_InitPowerpad(int w);
extern INPUTC *FCEU_InitArkanoid(int w);
{
uint8 ret=0;
+#ifdef DEBUG_ASM_6502
+ if (cpu_repeat) return cpu_lastval;
+#endif
if(JPorts[A&1]->Read)
ret|=JPorts[A&1]->Read(A&1);
ret=FCExp->Read(A&1,ret);
ret|=X.DB&0xC0;
+#ifdef DEBUG_ASM_6502
+// cpu_lastval=ret;
+#endif
return(ret);
}
static void MMC1PRG(void)
{
if(MMC1_reg[1]&8)
- {
+ {
switch(MMC1_reg[0]&0xC)
- {
+ {
case 0xC: ROM_BANK16(0x8000,8+(MMC1_reg[3]&7));
ROM_BANK16(0xC000,15);
break;
{
ROM_BANK32((MMC1_reg[1]>>1)&3);
}
+ X6502_Rebase();
}
DECLFW(Mapper105_write)
//MMC1_reg[n]&=~((1)<<(MMC1_sft));
MMC1_buf|=(V&1)<<(MMC1_sft++);
- if (MMC1_sft==5)
+ if (MMC1_sft==5)
{
if(n==3) V&=0xF;
else V&=0x1F;
case 6:VROM_BANK1(0x1800,V);break;
case 7:VROM_BANK1(0x1c00,V);break;
}
+ X6502_Rebase();
break;
}
}
/* I'm getting the feeling this is another "jam two different bank
switching hardwares into one mapper".
-*/
+*/
/* HES 4-in-1 */
DECLFW(Mapper113_write)
{
ROM_BANK32((V>>3)&7);
VROM_BANK8(V&7);
+ X6502_Rebase();
}
-
+
/* Deathbots */
DECLFW(Mapper113_writeh)
{
ROM_BANK32(V&0xF);
+ X6502_Rebase();
}
case 0xa005:VROM_BANK1(0x1400,V);break;
case 0xa006:VROM_BANK1(0x1800,V);break;
case 0xa007:VROM_BANK1(0x1c00,V);break;
- case 0x8000:ROM_BANK8(0x8000,V);break;
- case 0x8001:ROM_BANK8(0xa000,V);break;
- case 0x8002:ROM_BANK8(0xc000,V);break;
- case 0x8003:ROM_BANK8(0xe000,V);break;
+ case 0x8000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0x8001:ROM_BANK8(0xa000,V);
+ X6502_Rebase();break;
+ case 0x8002:ROM_BANK8(0xc000,V);
+ X6502_Rebase();break;
+ case 0x8003:ROM_BANK8(0xe000,V);
+ X6502_Rebase();break;
}
}
ROM_BANK16(0xC000,V+1);
}
MIRROR_SET((V>>6)&1);
+ X6502_Rebase();
break;
case 0x8001:
MIRROR_SET(0);
ROM_BANK16(0x8000,V);
ROM_BANK16(0xc000,~0);
+ X6502_Rebase();
break;
case 0x8002:
if(V&0x80)
ROM_BANK8(0xC000,(V<<1));
ROM_BANK8(0xE000,(V<<1));
}
+ X6502_Rebase();
break;
case 0x8003:
MIRROR_SET((V>>6)&1);
{
ROM_BANK16(0xC000,V);
}
+ X6502_Rebase();
break;
}
}
{
switch(A&0xF000)
{
- case 0x8000:ROM_BANK8(0x8000,V);break;
- case 0xA000:ROM_BANK8(0xA000,V);break;
- case 0xC000:ROM_BANK8(0xC000,V);break;
+ case 0x8000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0xA000:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
+ case 0xC000:ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
case 0xe000:VROM_BANK4(0x0000,V);break;
case 0xf000:VROM_BANK4(0x1000,V);break;
}
if(A<=0x7)
VROM_BANK1(A<<10,V);
else if(A==0x8)
+ {
ROM_BANK16(0x8000,V);
+ X6502_Rebase();
+ }
else switch(A) {
case 0x9: switch(V&3) {
case 0x00:MIRROR_SET2(1);break;
uint32 base=(mapbyte1[0]&1)<<4;
ROM_BANK16(0x8000,(mapbyte2[0]&0xF)|base);
ROM_BANK16(0xC000,base|0xF);
+ X6502_Rebase();
}
static DECLFW(Mapper153_write)
{
A&=0xF;
- if(A<=0x7)
+ if(A<=0x7)
{
mapbyte1[A&7]=V;
PRGO();
}
- else if(A==0x8)
+ else if(A==0x8)
{
mapbyte2[0]=V;
PRGO();
case 0x4501:IRQa=V&1;break;
case 0x4502:IRQCount&=0xFF00;IRQCount|=V;break;
case 0x4503:IRQCount&=0x00FF;IRQCount|=V<<8;IRQa=1;break;
- case 0x4504: ROM_BANK8(0x8000,V);break;
- case 0x4505: ROM_BANK8(0xA000,V);break;
- case 0x4506: ROM_BANK8(0xC000,V);break;
- case 0x4507: ROM_BANK8(0xE000,V);break;
+ case 0x4504: ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0x4505: ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
+ case 0x4506: ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
+ case 0x4507: ROM_BANK8(0xE000,V);
+ X6502_Rebase();break;
case 0x4510: VROM_BANK1(0x0000,V);break;
case 0x4511: VROM_BANK1(0x0400,V);break;
case 0x4512: VROM_BANK1(0x0800,V);break;
K4buf2[x]&=(0xF0)>>((A&1)<<2);
K4buf2[x]|=(V&0xF)<<((A&1)<<2);
ROM_BANK8(0x8000+(x<<13),K4buf2[x]);
+ X6502_Rebase();
}
else if(A>=0xa000 && A<=0xd003)
{
DECLFW(Mapper180_write)
{
-ROM_BANK16(0xC000,V);
+ ROM_BANK16(0xC000,V);
+ X6502_Rebase();
}
void Mapper180_init(void)
case 1:VROM_BANK1(0x1400,V);break;
case 2:VROM_BANK2(0x0800,V>>1);break;
case 3:VROM_BANK1(0x1c00,V);break;
- case 4:ROM_BANK8(0x8000,V);break;
- case 5:ROM_BANK8(0xA000,V);break;
+ case 4:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 5:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
case 6:VROM_BANK1(0x1000,V);break;
case 7:VROM_BANK1(0x1800,V);break;
}
#define cmd mapbyte1[0]
static DECLFW(Mapper189_write)
{
- if(A==0x4120) ROM_BANK32(V>>4);
+ if(A==0x4120)
+ {
+ ROM_BANK32(V>>4);
+ X6502_Rebase();
+ }
else switch(A&0xE001)
{
case 0xa000:MIRROR_SET(V&1);break;
- case 0x8000:cmd=V;break;
+ case 0x8000:cmd=V;break;
case 0x8001:switch(cmd&7)
{
case 0:VROM_BANK2(0x0000,V>>1);break;
// setntamem(NTARAM+((V&1)<<10), 1, w);
if((V>=0xE0)) // || ((gorko>>(6+(w>>1)))&1) )
setntamem(NTARAM+((V&1)<<10), 1, w);
- else
+ else
{
V&=CHRmask1[0];
setntamem(VROM+(V<<10), 0, w);
case 0xE000:gorko=V&0xC0;
//FixNTAR();
ROM_BANK8(0x8000,V);
+ X6502_Rebase();
break;
case 0xE800:gorfus=V&0xC0;
FixCRR();
ROM_BANK8(0xA000,V);
+ X6502_Rebase();
break;
case 0xF000:
ROM_BANK8(0xC000,V);
+ X6502_Rebase();
break;
}
}
{
int32 z,a;
- z=((timestamp<<16)/soundtsinc)>>4;
+ z=((timestamp<<16)/soundtsinc)>>4;
a=z-dwave;
if(a)
DoNamcoSound(&Wave[dwave], a);
duff>>=4;
duff&=0xF;
duff2=(duff*envelope)>>14;
-
+
lengo=((8-((MapperExRAM[0x44+(P<<3)]>>2)&7)))<<2;
for(V=0;V<Count OVERSAMPLE;V++)
{
A|=((A>>5)&0xF);
if((A&0xF000)==0xA000)
+ {
ROM_BANK8(0xA000,V);
+ X6502_Rebase();
+ }
else if((A&0xF000)==0x8000)
{
if(K4sel&2)
ROM_BANK8(0xC000,V);
else
ROM_BANK8(0x8000,V);
+ X6502_Rebase();
}
else if(A>=0xb000 && A<=0xefff)
{
K4buf[x]|=(V&0xF)<<((A&2)<<1);
VROM_BANK1(x<<10,K4buf[x]);
}
-
+
}
else switch(A&0xF006)
{
swa=PRGBankList[0];
ROM_BANK8(0x8000,PRGBankList[2]);
ROM_BANK8(0xc000,swa);
+ X6502_Rebase();
}
K4sel=V;
break;
{
switch(A&0xF000)
{
- case 0x8000:ROM_BANK8(0x8000,V);break;
- case 0xa000:ROM_BANK8(0xA000,V);break;
+ case 0x8000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0xa000:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
case 0x9000:switch(V&3)
{
case 0x00:MIRROR_SET2(1);break;
{
ROM_BANK32(((((A>>7)&0x1F)+(banks<<5))));
}
+ X6502_Rebase();
}
void Mapper225_init(void)
}
else
ROM_BANK32(b);
+ X6502_Rebase();
}
static DECLFW(Mapper226_write)
else
ROM_BANK16(0xC000,(p<<1)&(~7));
}
+ X6502_Rebase();
}
static DECLFW(Mapper227_write)
page=(A>>7)&0x3F;
if((page&0x30)==0x30)
page-=0x10;
-
+
pagel=pageh=(page<<1) + (((A>>6)&1)&((A>>5)&1));
pageh+=((A>>5)&1)^1;
ROM_BANK16(0x8000,pagel);
ROM_BANK16(0xC000,pageh);
VROM_BANK8( (V&0x3) | ((A&0xF)<<2) );
+ X6502_Rebase();
}
static void A52Reset(void)
ROM_BANK16(0xC000,A&0x1f);
}
VROM_BANK8(A);
+ X6502_Rebase();
}
}
ROM_BANK8(0xC000,V);
else
ROM_BANK8(0x8000,V);
- }
- else if((A&0xF000)==0xA000)
+ X6502_Rebase();
+ }
+ else if((A&0xF000)==0xA000)
+ {
ROM_BANK8(0xA000,V);
+ X6502_Rebase();
+ }
else
{
A|=((A>>2)&0x3)|((A>>4)&0x3)|((A>>6)&0x3);
K4buf[x]|=(V&0xF)<<((A&1)<<2);
VROM_BANK1(x<<10,K4buf[x]);
}
- else
+ else
switch(A)
{
case 0xf000:X6502_IRQEnd(FCEU_IQEXT);IRQLatch&=0xF0;IRQLatch|=V&0xF;break;
swa=PRGBankList[0];
ROM_BANK8(0x8000,PRGBankList[2]);
ROM_BANK8(0xc000,swa);
+ X6502_Rebase();
}
K4sel=V;
break;
{
ROM_BANK16(0x8000,(mapbyte1[1]&3) | ((mapbyte1[0]&0x18)>>1));
ROM_BANK16(0xc000,3|(((mapbyte1[0])&0x18)>>1));
+ X6502_Rebase();
}
DECLFW(Mapper232_write)
ROM_BANK32(r1&0xF);
VROM_BANK8( ((r1&0xF)<<2) | ((r2>>4)&3) );
}
+ X6502_Rebase();
}
static void R1Set(uint8 V)
SetWriteHandler(0x6000,0x7FFF,0);
M15Reset();
-
+
GameStateRestore=M15Restore;
MapperReset=M15Reset;
}
{
ROM_BANK32(V>>4);
VROM_BANK8(V&0xF);
+ X6502_Rebase();
}
}
DECLFW(Mapper242_write)
{
ROM_BANK32((A>>3)&0xF);
+ X6502_Rebase();
switch(V&3)
{
case 0:MIRROR_SET(0);break;
case 1:MIRROR_SET(1);break;
- case 2:onemir(0);break;
+ case 2:onemir(0);break;
case 3:onemir(1);break;
}
}
ROM_BANK8(0xA000,mapbyte2[1]);
ROM_BANK8(0xc000,0x3e);
ROM_BANK8(0xe000,0x3f);
+ X6502_Rebase();
}
static DECLFW(Mapper245_write)
{
{
switch(A&0xF007)
{
- case 0x6000:ROM_BANK8(0x8000,V);break;
- case 0x6001:ROM_BANK8(0xA000,V);break;
- case 0x6002:ROM_BANK8(0xC000,V);break;
- case 0x6003:ROM_BANK8(0xE000,V);break;
+ case 0x6000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0x6001:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
+ case 0x6002:ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
+ case 0x6003:ROM_BANK8(0xE000,V);
+ X6502_Rebase();break;
case 0x6004:VROM_BANK2(0x0000,V);break;
case 0x6005:VROM_BANK2(0x0800,V);break;
case 0x6006:VROM_BANK2(0x1000,V);break;
ROM_BANK8(0x8000,prgl[0]&0x1F);
ROM_BANK8(0xa000,prgl[1]&0x1F);
}
+ X6502_Rebase();
}
static DECLFW(Mapper248_writelow)
switch(A&0xF003)
{
- case 0x8000:ROM_BANK16(0x8000,V);break;
+ case 0x8000:ROM_BANK16(0x8000,V);
+ X6502_Rebase();break;
case 0xB003:
switch(V&0xF)
{
case 0xC:onemir(1);break;
}
break;
- case 0xC000:ROM_BANK8(0xC000,V);break;
+ case 0xC000:ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
case 0xD000:VROM_BANK1(0x0000,V);break;
case 0xD001:VROM_BANK1(0x0400,V);break;
case 0xD002:VROM_BANK1(0x0800,V);break;
int V;
int32 start,end;
- start=CVBC[0];
+ start=CVBC[0];
end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
CVBC[0]=end;
}
else
{
- unsigned long dcycs;
+ unsigned long dcycs;
freq=(((VPSG[0x2]|((VPSG[0x3]&15)<<8))+1));
inc=(long double)((unsigned long)((FSettings.SndRate OVERSAMPLE)<<12))/((long double)PSG_base/freq);
switch(VPSG[0]&0x70)
int32 start,end;
start=CVBC[1];
- end=(timestamp<<16)/soundtsinc;
+ end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
CVBC[1]=end;
int32 start,end;
start=CVBC[2];
- end=(timestamp<<16)/soundtsinc;
+ end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
CVBC[2]=end;
b3=0;
phaseacc=0;
}
- if(saw1phaseacc<=0)
+ if(saw1phaseacc<=0)
goto rea;
duff=(((phaseacc>>3)&0x1f)<<4);
}
{
for(x=000;x<0x1000;x+=4)
{
- SetWriteHandler(0x9000+x,0x9002+x,0);
- SetWriteHandler(0xa000+x,0xa002+x,0);
- SetWriteHandler(0xb000+x,0xb002+x,0);
+ SetWriteHandler(0x9000+x,0x9002+x,0);
+ SetWriteHandler(0xa000+x,0xa002+x,0);
+ SetWriteHandler(0xb000+x,0xb002+x,0);
}
}
}
A=(A&0xF003)|((A&0xC)>>2);
if((A&0xF000)==0xA000)
+ {
ROM_BANK8(0xA000,V);
+ X6502_Rebase();
+ }
else if(A>=0xB000 && A<=0xEFFF)
{
int x=(A&1)|((A-0xB000)>>11);
ROM_BANK8(0xC000,V);
else
ROM_BANK8(0x8000,V);
+ X6502_Rebase();
}
else switch(A)
{
swa=PRGBankList[0];
ROM_BANK8(0x8000,PRGBankList[2]);
ROM_BANK8(0xc000,swa);
+ X6502_Rebase();
}
K4sel=V;
break;
mapbyte1[1]=V;
if(IREMCon) {ROM_BANK8(0xc000,V);ROM_BANK8(0x8000,~1);}
else {ROM_BANK8(0x8000,V);ROM_BANK8(0xc000,~1);}
+ X6502_Rebase();
break;
case 0x9:MIRROR_SET2(V&1);
IREMCon=(V>>1)&1;
if(IREMCon) {ROM_BANK8(0xc000,mapbyte1[1]);ROM_BANK8(0x8000,~1);}
else {ROM_BANK8(0x8000,mapbyte1[1]); ROM_BANK8(0xc000,~1);}
MIRROR_SET(V&1);
+ X6502_Rebase();
break;
case 0xa:ROM_BANK8(0xA000,V);
+ X6502_Rebase();
break;
}
else switch(A){
case 0x8000:if(!mapbyte1[0])
MIRROR_SET((V>>6)&1);
- ROM_BANK8(0x8000,V);
+ ROM_BANK8(0x8000,V);
+ X6502_Rebase();
break;
- case 0x8001:ROM_BANK8(0xA000,V); break;
+ case 0x8001:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
case 0x8002:VROM_BANK2(0x0000,V);break;
case 0x8003:VROM_BANK2(0x0800,V);break;
case 0xc000:IRQLatch=V;break;
if(IRQa)
{
IRQCount++;
- if(IRQCount==0x100)
+ if(IRQCount==0x100)
{
TriggerIRQ();
IRQa=0;
{
case 0x8000:IRQa=0;IRQCount=0;break;
case 0xa000:IRQa=1;break;
- case 0xe000:ROM_BANK8(0xc000,V&7);break;
+ case 0xe000:ROM_BANK8(0xc000,V&7);
+ X6502_Rebase();break;
}
}
{
if(IRQa)
{
- if(IRQCount<4096)
+ if(IRQCount<4096)
IRQCount+=a;
else
{
if(A<0x8000)
{
ROM_BANK32(A&7);
+ X6502_Rebase();
MIRROR_SET((A>>5)&1);
calreg=A;
calchr&=0x3;
{
switch(A&0xe003)
{
- case 0xe000:mapbyte1[0]=V;ROM_BANK8(0x6000,V&0xF);break;
+ case 0xe000:mapbyte1[0]=V;ROM_BANK8(0x6000,V&0xF);
+ X6502_Rebase();break;
case 0xe001:MIRROR_SET((V>>3)&1);break;
case 0xe002:IRQa=V&2;if(!IRQa) IRQCount=0;break;
}
}
else
ROM_BANK32(m);
+ X6502_Rebase();
}
void Mapper43_init(void)
A64reg=V;
ROM_BANK32((A64wr&1)+((A64reg&0xF)<<1));
VROM_BANK8(((A64wr>>4)&7)+((A64reg&0xF0)>>1));
+ X6502_Rebase();
}
DECLFW(Mapper46_write)
A64wr=V;
ROM_BANK32((V&1)+((A64reg&0xF)<<1));
VROM_BANK8(((V>>4)&7)+((A64reg&0xF0)>>1));
+ X6502_Rebase();
}
void Mapper46_init(void)
static uint32 Get8K(uint32 A)
{
uint32 bank;
-
+
bank=(page<<2)|((A>>13)&1);
if(A&0x4000 && !(mode&1)) bank|=0xC;
MIRROR_SET2(0);
for(x=0x6000;x<0x10000;x+=8192)
ROM_BANK8(x,Get8K(x));
+ X6502_Rebase();
}
static DECLFW(Write)
} else {
ROM_BANK16(0x8000,V>>2);
FVRAM_BANK8(0x0000,V&3);
+ X6502_Rebase();
}
}
void Mapper6_StateRestore(int version)
setprg8(0xA000,regsl[7]);
setprg8(0xC000,regsh[7]);
+ X6502_Rebase();
}
if(rmode==1)
{IRQCount=IRQLatch;}
break;
- }
+ }
}
static void RAMBO1_Restore(int version)
{
switch(A)
{
-case 0x8000:ROM_BANK8(0x8000,V);break;
+case 0x8000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
case 0x9000:MIRROR_SET2((V>>6)&1);break;
case 0x9003:IRQa=V&0x80;break;
case 0x9004:IRQCount=IRQLatch;break;
case 0xB005:VROM_BANK1(0x1400,V);break;
case 0xB006:VROM_BANK1(0x1800,V);break;
case 0xB007:VROM_BANK1(0x1C00,V);break;
-case 0xa000:ROM_BANK8(0xA000,V);break;
-case 0xC000:ROM_BANK8(0xC000,V);break;
+case 0xa000:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
+case 0xC000:ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
}
}
case 3:onemir(1);break;
}
break;
- case 0xf800:ROM_BANK16(0x8000,V);break;
+ case 0xf800:ROM_BANK16(0x8000,V);
+ X6502_Rebase();break;
}
}
static void FP_FASTAPASS(1) SunIRQHook(int a)
PPUNTARAM=0;
}
break;
- case 0xf000: ROM_BANK16(0x8000,V);break;
+ case 0xf000: ROM_BANK16(0x8000,V);
+ X6502_Rebase();break;
}
}
DECLFR(SUN5AWRAM)
{
if((sungah&0xC0)==0x40)
- return X.DB;
+ return X.DB;
return CartBR(A);
}
DoAYSQ(1);
DoAYSQ(2);break;
}
- MapperExRAM[sunindex]=V;
+ MapperExRAM[sunindex]=V;
}
DECLFW(Mapper69_write)
}
else
setprg8(0x6000,V);
+ X6502_Rebase();
break;
- case 9:ROM_BANK8(0x8000,V);break;
- case 0xa:ROM_BANK8(0xa000,V);break;
- case 0xb:ROM_BANK8(0xc000,V);break;
+ case 9:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0xa:ROM_BANK8(0xa000,V);
+ X6502_Rebase();break;
+ case 0xb:ROM_BANK8(0xc000,V);
+ X6502_Rebase();break;
case 0xc:
switch(V&3)
{
unsigned char amp;
int32 start,end;
- start=CAYBC[x];
+ start=CAYBC[x];
end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
CAYBC[x]=end;
unsigned char amp;
int32 start,end;
- start=CAYBC[3];
+ start=CAYBC[3];
end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
CAYBC[3]=end;
{
if(FSettings.SndRate)
Mapper69_ESI();
- else
+ else
SetWriteHandler(0xc000,0xffff,(writefunc)0);
}
void Mapper69_ESI(void)
{
- GameExpSound.RChange=M69SC;
+ GameExpSound.RChange=M69SC;
if(FSettings.SndRate)
{
SetWriteHandler(0xc000,0xdfff,Mapper69_SWL);
case 0xF000:
case 0xE000:
case 0xD000:
- case 0xC000:ROM_BANK16(0x8000,V);break;
+ case 0xC000:ROM_BANK16(0x8000,V);
+ X6502_Rebase();break;
case 0x9000:onemir((V>>3)&2);break;
}
}
{
mapbyte1[0]=V;
if(V&0x80)
+ {
ROM_BANK16(0x8000,V&0xF);
+ X6502_Rebase();
+ }
if(V&0x40)
VROM_BANK8(V&0xF);
}
case 0xa000:IRQCount&=0xF0FF;IRQCount|=(V&0xF)<<8;break;
case 0xb000:IRQCount&=0x0FFF;IRQCount|=(V&0xF)<<12;break;
case 0xc000:IRQa=V&2;break;
- case 0xf000:ROM_BANK16(0x8000,V);break;
+ case 0xf000:ROM_BANK16(0x8000,V);
+ X6502_Rebase();break;
}
}
{
switch(A&0xF000)
{
- case 0x8000:ROM_BANK8(0x8000,V);break;
+ case 0x8000:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
case 0x9000:
VROM_BANK4(0x0000,map75ar[0]|((V&2)<<3));
VROM_BANK4(0x1000,map75ar[1]|((V&4)<<2));
map75sel=V;MIRROR_SET(V&1);break;
- case 0xa000:ROM_BANK8(0xa000,V);break;
- case 0xc000:ROM_BANK8(0xc000,V);break;
+ case 0xa000:ROM_BANK8(0xa000,V);
+ X6502_Rebase();break;
+ case 0xc000:ROM_BANK8(0xc000,V);
+ X6502_Rebase();break;
case 0xe000:V&=0xF;map75ar[0]=V;V|=(map75sel&2)<<3;VROM_BANK4(0x0000,V);break;
case 0xf000:V&=0xF;map75ar[1]=V;V|=(map75sel&4)<<2;VROM_BANK4(0x1000,V);break;
}
case 6:
if (MMC3_cmd&0x40) ROM_BANK8(0xC000,V);
else ROM_BANK8(0x8000,V);
+ X6502_Rebase();
break;
case 7: ROM_BANK8(0xA000,V);
+ X6502_Rebase();
break;
}
break;
mapbyte1[0]=V;
ROM_BANK32(V&0x7);
VROM_BANK2(0x0000, (V&0xf0)>>4);
+ X6502_Rebase();
}
static void Mapper77_StateRestore(int version)
{
int x;
-
+
if(version>=72)
{
ROM_BANK32(mapbyte1[0]&0x7);
VROM_BANK2(0x0000, (mapbyte1[0]&0xf0)>>4);
+ X6502_Rebase();
}
for(x=2;x<8;x++)
VRAM_BANK1(x*0x400,x);
if(A<0x8000 && ((A^0x4100)==0))
{
ROM_BANK32((V>>3)&1);
+ X6502_Rebase();
}
VROM_BANK8(V);
}
{
ROM_BANK16(0x8000,V>>3);
VROM_BANK8(V&7);
+ X6502_Rebase();
}
void Mapper8_init(void)
case 0x7ef4: VROM_BANK1(0x1800,V);break;
case 0x7ef5: VROM_BANK1(0x1c00,V);break;
case 0x7efa:
- case 0x7efb: ROM_BANK8(0x8000,V);break;
+ case 0x7efb: ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
case 0x7efd:
- case 0x7efc: ROM_BANK8(0xA000,V);break;
+ case 0x7efc: ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
case 0x7efe:
- case 0x7eff: ROM_BANK8(0xC000,V);break;
+ case 0x7eff: ROM_BANK8(0xC000,V);
+ X6502_Rebase();break;
}
}
MIRROR_SET2(V&1);
DoCHR();
break;
- case 0x7efa:V>>=2;mapbyte2[0]=V;ROM_BANK8(0x8000,V);break;
- case 0x7efb:V>>=2;mapbyte2[1]=V;ROM_BANK8(0xa000,V);break;
- case 0x7efc:V>>=2;mapbyte2[2]=V;ROM_BANK8(0xc000,V);break;
+ case 0x7efa:V>>=2;mapbyte2[0]=V;ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 0x7efb:V>>=2;mapbyte2[1]=V;ROM_BANK8(0xa000,V);
+ X6502_Rebase();break;
+ case 0x7efc:V>>=2;mapbyte2[2]=V;ROM_BANK8(0xc000,V);
+ X6502_Rebase();break;
}
}
{
ROM_BANK16(0x8000,mapbyte1[0]&0x3F);
ROM_BANK16(0xC000,(mapbyte1[0]&0x30)|0xF);
+ X6502_Rebase();
}
static void m83chr(void)
case 0x8317:mapbyte2[7]=V;m83chr();break;
}
// printf("$%04x:$%02x, $%04x\n",A,V,X.PC.W);
-
+
}
void Mapper83_init(void)
}
else switch(A&0xF010)
{
- case 0x8000:mapbyte2[0]=V;setprg8(0x8000,V);break;
- case 0x8010:mapbyte2[1]=V;setprg8(0xa000,V);break;
- case 0x9000:mapbyte2[2]=V;setprg8(0xc000,V);break;
+ case 0x8000:mapbyte2[0]=V;setprg8(0x8000,V);
+ X6502_Rebase();break;
+ case 0x8010:mapbyte2[1]=V;setprg8(0xa000,V);
+ X6502_Rebase();break;
+ case 0x9000:mapbyte2[2]=V;setprg8(0xc000,V);
+ X6502_Rebase();break;
case 0x9010:indox=V;break;
case 0xe000:mapbyte2[3]=V;DaMirror(V);break;
case 0xE010:IRQLatch=V;
{
VROM_BANK8((V&3)|((V>>4)&4));
ROM_BANK32((V>>4)&3);
+ X6502_Rebase();
}
void Mapper86_init(void)
case 3:VROM_BANK1(0x1400,V|0x40);break;
case 4:VROM_BANK1(0x1800,V|0x40);break;
case 5:VROM_BANK1(0x1c00,V|0x40);break;
- case 6:ROM_BANK8(0x8000,V);break;
- case 7:ROM_BANK8(0xA000,V);break;
+ case 6:ROM_BANK8(0x8000,V);
+ X6502_Rebase();break;
+ case 7:ROM_BANK8(0xA000,V);
+ X6502_Rebase();break;
}
break;
VROM_BANK8((V&7)|((V>>4)&8));
ROM_BANK16(0x8000,(V>>4)&7);
onemir((V>>3)&1);
+ X6502_Rebase();
}
void Mapper89_init(void)
ROM_BANK8(0xe000,prgb[3]);
break;
}
+ X6502_Rebase();
}
static void tekvrom(void)
{
if(IRQa)
{
- if(IRQCount)
+ if(IRQCount)
{
IRQCount--;
if(!IRQCount)
if(A>=0x9000)
{
- if(reg==0xD) ROM_BANK16(0xc000,bank);
+ if(reg==0xD) { ROM_BANK16(0xc000,bank); X6502_Rebase(); }
else if(reg==0xE) VROM_BANK8(bank);
}
else
{
- if(reg==0xB) ROM_BANK16(0xc000,bank);
+ if(reg==0xB) { ROM_BANK16(0xc000,bank); X6502_Rebase(); }
else if(reg==0x7) VROM_BANK8(bank);
}
}
case 5: dbarray[7]=(V&0x20)>>4;onemir((V&0x20)>>4);VROM_BANK1(0x1C00,V); break;
case 6:
ROM_BANK8(0x8000,V);
+ X6502_Rebase();
break;
case 7:
ROM_BANK8(0xA000,V);
+ X6502_Rebase();
break;
}
break;
DECLFW(Mapper97_write)
{
ROM_BANK16(0xC000,V&15);
+X6502_Rebase();
switch(V>>6)
{
case 0:break;
h=VAddr>>8;
- if(h>=0x20 || ((h&0xF)!=0xF))
+ if(h>=0x20 || ((h&0xF)!=0xF))
return;
l=VAddr&0xF0;
DECLFW(Mapper9_write) // $Axxx
{
ROM_BANK8(0x8000,V);
+ X6502_Rebase();
}
DECLFW(Mapper10_write)
{
ROM_BANK16(0x8000,V);
+ X6502_Rebase();
}
DECLFW(Mapper9and10_write)
{
latche=V;
ROM_BANK16(0x8000,V);
+ X6502_Rebase();
}
void Mapper2_init(void)
ROM_BANK32(V&0xF);
onemir((V>>4)&1);
latche=V;
+ X6502_Rebase();
}
void Mapper7_init(void)
ROM_BANK32(V);
VROM_BANK8(V>>4);
latche=V;
+ X6502_Rebase();
}
void Mapper11_init(void)
setchr4r(0x10,0x1000,V&3);
setprg32(0x8000,(V>>4)&3);
latche=V;
+ X6502_Rebase();
}
static void Mapper13_StateRestore(int version)
setchr4r(0x10,0x0000,0);
setchr4r(0x10,0x1000,latche&3);
setprg32(0x8000,(latche>>4)&3);
+ X6502_Rebase();
}
void Mapper13_init(void)
{
switch(A)
{
- case 0x7FFD:ROM_BANK32(V);break;
+ case 0x7FFD:ROM_BANK32(V);
+ X6502_Rebase();break;
case 0x7FFE:VROM_BANK4(0x0000,V);break;
case 0x7fff:VROM_BANK4(0x1000,V);break;
}
-if(A>=0x8000)
- ROM_BANK32(V);
+ if(A>=0x8000)
+ {
+ ROM_BANK32(V);
+ X6502_Rebase();
+ }
}
void Mapper34_init(void)
VROM_BANK8(V&0xF);
ROM_BANK32((V>>4));
latche=V;
+ X6502_Rebase();
}
void Mapper66_init(void)
VROM_BANK8(V&0xF);
onemir((V>>7)&1); /* Saint Seiya...hmm. */
latche=V;
+ X6502_Rebase();
}
void Mapper152_init(void)
ROM_BANK16(0x8000,V>>4);
VROM_BANK8(V&0xF);
latche=V;
+ X6502_Rebase();
}
void Mapper70_init(void)
VROM_BANK8(V>>4);
onemir((V>>3)&1);
latche=V;
+ X6502_Rebase();
}
void Mapper78_init(void)
ROM_BANK16(0x8000,V>>4);
MIRROR_SET(V&1);
latche=V;
+ X6502_Rebase();
}
void Mapper93_init(void)
{
ROM_BANK16(0x8000,V>>2);
latche=V;
+ X6502_Rebase();
}
void Mapper94_init(void)
setprg32(0x8000,V&3);
setchr4r(0x10,0x0000,(latche&4)|M96LA);
setchr4r(0x10,0x1000,(latche&4)|3);
+ X6502_Rebase();
}
static void FP_FASTAPASS(1) M96Hook(uint32 A)
setprg32(0x8000,latche&3);
setchr4r(0x10,0x0000,(latche&4)|M96LA);
setchr4r(0x10,0x1000,(latche&4)|3);
+ X6502_Rebase();
}
void Mapper96_init(void)
{
VROM_BANK8(V&0xF);
ROM_BANK32((V>>4)&0xF);
+ X6502_Rebase();
}
void Mapper140_init(void)
static DECLFR(MAWRAM)
{
- if(MMC1_reg[3]&0x10)
+ if(MMC1_reg[3]&0x10)
return X.DB; // WRAM is disabled
return(Page[A>>11][A]);
}
setprg8r(0x10,0x6000,(MMC1_reg[1]>>4)&1);
else
setprg8r(0x10,0x6000,(MMC1_reg[1]>>3)&1);
+ X6502_Rebase();
}
if(MMC1_reg[0]&0x10)
setprg16(0xc000,((MMC1_reg[3]&~1)+offs+1));
break;
}
+ X6502_Rebase();
}
static void MMC1MIRROR(void)
{
{
lreset=0;
mmc1opts=0;
- MMC1CMReset();
+ MMC1CMReset();
SetWriteHandler(0x8000,0xFFFF,MMC1_write);
MapStateRestore=MMC1_Restore;
AddExState(&lreset, 8, 1, "LRST");
CHRmask4[0]&=(chr>>12)-1;
CHRmask8[0]&=(chr>>13)-1;
- if(wram)
- {
+ if(wram)
+ {
mmc1opts|=1;
if(wram>8) mmc1opts|=4;
SetupCartPRGMapping(0x10,WRAM,wram*1024,1);
//static void GenMMC1Init(int prg, int chr, int wram, int battery)
void SAROM_Init(void)
{
- GenMMC1Init(128, 64, 8, 1);
+ GenMMC1Init(128, 64, 8, 1);
}
void SBROM_Init(void)
GenMMC1Init(128, 64, 0, 0);
}
-void SCROM_Init(void)
+void SCROM_Init(void)
{
GenMMC1Init(128, 128, 0, 0);
}
resetmode=1;
break;
case 0xE001:IRQa=1;
- if(latched)
+ if(latched)
IRQCount=IRQLatch;
break;
}
}
pwrap(0xA000,DRegBuf[7]);
pwrap(0xE000,~0);
+ X6502_Rebase();
}
static INLINE void FixMMC3CHR(int V)
case 5: cwrap(cbase^0x1C00,V); break;
case 6: if (MMC3_cmd&0x40) pwrap(0xC000,V);
else pwrap(0x8000,V);
+ X6502_Rebase();
break;
case 7: pwrap(0xA000,V);
+ X6502_Rebase();
break;
}
}
A000B=V;
}
-static void genmmc3ii(void (*PW)(uint32 A, uint8 V),
- void (*CW)(uint32 A, uint8 V),
+static void genmmc3ii(void (*PW)(uint32 A, uint8 V),
+ void (*CW)(uint32 A, uint8 V),
void (*MW)(uint8 V))
{
pwrap=GENPWRAP;
{
PIRREGS[0]=V&1;
FixMMC3PRG(MMC3_cmd);
- FixMMC3CHR(MMC3_cmd);
+ FixMMC3CHR(MMC3_cmd);
}
void Mapper47_init(void)
static DECLFW(Mapper52_write)
{
- if(PIRREGS[1])
+ if(PIRREGS[1])
{
(WRAM-0x6000)[A]=V;
return;
static void M52Reset(void)
{
PIRREGS[0]=PIRREGS[1]=0;
- MMC3RegReset();
+ MMC3RegReset();
}
void Mapper52_init(void)
setprg8(A,V);
}
else
+ {
setprg32(0x8000,(PIRREGS[0]>>4)&3);
+ X6502_Rebase();
+ }
}
static void M49CW(uint32 A, uint8 V)
//if(scanline>=140 && scanline<=200) {setmirror(MI_1);return;}
//if(scanline>=140 && scanline<=200)
// if(scanline>=190 && scanline<=200) {setmirror(MI_1);return;}
- // setmirror(MI_1);
+ // setmirror(MI_1);
//printf("$%04x\n",A);
A>>=10;
void MMC5Sound(int Count);
void Do5SQ(int P);
-static INLINE void MMC5SPRVROM_BANK1(uint32 A,uint32 V)
+static INLINE void MMC5SPRVROM_BANK1(uint32 A,uint32 V)
{
if(CHRptr[0])
{
static INLINE void MMC5BGVROM_BANK8(uint32 V) {if(CHRptr[0]){V&=CHRmask8[0];MMC5BGVPage[0]=MMC5BGVPage[1]=MMC5BGVPage[2]=MMC5BGVPage[3]=MMC5BGVPage[4]=MMC5BGVPage[5]=MMC5BGVPage[6]=MMC5BGVPage[7]=&CHRptr[0][(V)<<13];}}
static int32 inc;
-uint8 MMC5fill[0x400];
+uint8 MMC5fill[0x400] __attribute__ ((aligned (4)));
#define MMC5IRQR mapbyte3[4]
#define MMC5LineCounter mapbyte3[5]
MMC5ROMWrProtect[0]=MMC5ROMWrProtect[1]=
MMC5ROMWrProtect[2]=MMC5ROMWrProtect[3]=1;
setprg32(0x8000,((mapbyte1[5]&0x7F)>>2));
+ X6502_Rebase();
for(x=0;x<4;x++)
MMC5MemIn[1+x]=1;
break;
mapbyte4[3]=V;
break;
- case 0x5113:mapbyte4[6]=V;MMC5WRAM(0x6000,V&7);break;
- case 0x5100:mapbyte1[0]=V;MMC5PRG();break;
+ case 0x5113:mapbyte4[6]=V;MMC5WRAM(0x6000,V&7);
+ X6502_Rebase();break;
+ case 0x5100:mapbyte1[0]=V;MMC5PRG();
+ X6502_Rebase();break;
case 0x5101:mapbyte1[1]=V;
if(!mapbyte4[7])
{MMC5CHRB();MMC5CHRA();}
case 0x5115:
case 0x5116:
case 0x5117:
- mapbyte1[A&7]=V;MMC5PRG();break;
+ mapbyte1[A&7]=V;MMC5PRG();
+ X6502_Rebase();break;
case 0x5120:
case 0x5121:
}
X6502_IRQEnd(FCEU_IQEXT);
MMC5HackCHRMode=mapbyte4[2]&3;
+ X6502_Rebase();
}
void MMC5_hbo(void)
if(MMC5LineCounter<240)
{
MMC5LineCounter++;
- if(MMC5LineCounter==IRQCount)
+ if(MMC5LineCounter==IRQCount)
{
MMC5IRQR|=0x80;
if(IRQa&0x80)
end=(timestamp<<16)/soundtsinc;
if(end<=start) return;
C5BC[2]=end;
-
+
if(!(MMC5PSG[0x10]&0x40) && MMC5PSG[0x11])
for(V=start;V<end;V++)
Wave[V>>4]+=MMC5PSG[0x11]<<2;
if(FSettings.SndRate)
Mapper5_ESI();
else
- SetWriteHandler(0x5000,0x5015,0);
+ SetWriteHandler(0x5000,0x5015,0);
}
void Mapper5_ESI(void)
AddExState(&MMC5HackSPScroll, 1, 0, "SPLS");
AddExState(&MMC5HackSPPage, 1, 0, "SPLP");
- MMC5WRAMsize=wsize/8;
+ MMC5WRAMsize=wsize/8;
BuildWRAMSizeTable();
GameStateRestore=Mapper5_StateRestore;
BoardPower=GenMMC5Reset;
#define OTOFFS_NES_REGS (nes_registers - cpu_exec_table)
#define OTOFFS_PC_BASE (pc_base - cpu_exec_table)
#define OTOFFS_IRQ_HOOK (MapIRQHook - cpu_exec_table)
-#define OTOFFS_X (X - cpu_exec_table)
+#define OTOFFS_X (X_ - cpu_exec_table)
@ fceu
#define FCEU_IQNMI 0x08
SECTION_TEXT
ALIGN
+bbbb:
+.ascii "rebase: %04x"
+.byte 0x0a,0
+.align 4
@@@
@@@
.macro REBASE_PC
@ FIXME: do something with mem not in Page[].
+@ stmfd sp!, {r0-r3,r12,lr}
+@ mov r1, r0
+@ ldr r0, =bbbb
+@ bl printf
+@ ldmfd sp!, {r0-r3,r12,lr}
+
cmp r0, #0x2000
ldrge r1, =Page
movge r2, r0, lsr #11
mov REG_PC, lr @ r7
mov REG_P_REST, r3 @ r8
+#ifndef DEBUG_ASM_6502
ldr r2, =ARead
bic r0, REG_ADDR, #0x00ff0000
mov lr, pc
ldr pc, [r2, r0, lsl #2]
+#else
+ ldr r1, =cpu_lastval
+ ldr r0, [r1]
+ tst r0, #0x20000
+ orreq r0, r0, #0x20000
+ streq r0, [r1]
+ movne r0, r0, lsr #8
+ and r0, r0, #0xff
+#endif
ldr REG_OP_TABLE, =cpu_exec_table @ got trashed because was in r12
mov lr, REG_PC
write_high_reg:
write_save_ram:
write_rom_byte:
+#ifndef DEBUG_ASM_6502
@ must preserve r3 for the callers too
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
ldr REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
ldr REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
ldr REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
+#endif
bx lr
@@@
nes_registers:
.fill 0x40, 1, 0
-#ifndef DEBUG_ASM_6502
RAM:
-#endif
nes_internal_ram:
.fill 0x100, 1, 0
nes_stack:
@ TODO: write code which keeps it up-to-date
pc_base:
.long 0
-#ifndef DEBUG_ASM_6502
MapIRQHook:
.long 0
timestamp:
.long 0
-X: .fill 0x20, 1, 0
+#ifndef DEBUG_ASM_6502
+X:
#endif
+X_: .fill 0x20, 1, 0
.pool
.globl RAM
.globl timestamp
.globl MapIRQHook @ (int a)
+#else
+ .globl nes_internal_ram
#endif
.globl X6502_Reset_a @ (void);
.globl X6502_Power_a @ (void);
.globl X6502_AddCycles_a @ (int x);
.globl X6502_IRQBegin_a @ (int w);
.globl X6502_IRQEnd_a @ (int w);
- .globl X6502_rebase_a @ (void);
+ .globl X6502_Rebase_a @ (void);
SECTION_TEXT
ALIGN
@ rebase PC when not executing or in memhandlers
-X6502_rebase_a:
+X6502_Rebase_a:
stmfd sp!,{REG_PC,REG_OP_TABLE}
ldr REG_OP_TABLE, =cpu_exec_table
ldr r0, [REG_OP_TABLE, #(OTOFFS_NES_REGS+0x0c)] @ PC
// asm core state
extern uint32 nes_registers[0x10];
extern uint32 pc_base;
-uint32 PC_prev = 0, g_cnt = 0;
+extern uint8 nes_internal_ram[0x800];
+uint32 PC_prev = 0xcccccc, OP_prev = 0xcccccc;
+int32 g_cnt = 0;
int cpu_repeat;
int cpu_lastval;
+static int pending_add_cycles = 0, pending_rebase = 0;
static void leave(void)
{
printf("\nA: %02x, X: %02x, Y: %02x, S: %02x\n", X.A, X.X, X.Y, X.S);
- printf("PC = %04lx, OP=%02X\n", PC_prev, (PC_prev < 0x2000) ? RAM[PC_prev&0x7ff] : ARead[PC_prev](PC_prev));
+ printf("PC = %04lx, OP=%02lX\n", PC_prev, OP_prev);
+ printf("cpu_lastval = %02x\n", cpu_lastval);
exit(1);
}
if (fail) leave();
}
+#if 1
+static void compare_ram(void)
+{
+ int i, fail = 0;
+ for (i = 0; i < 0x800/4; i++)
+ {
+ if (((int *)nes_internal_ram)[i] != ((int32 *)RAM)[i]) {
+ int u;
+ fail = 1;
+ for (u = i*4; u < i*4+4; u++)
+ if (nes_internal_ram[u] != RAM[u])
+ printf("RAM[%03x]: %02x vs %02x\n", u, nes_internal_ram[u], RAM[u]);
+ }
+ }
+
+ if (fail) leave();
+}
+#endif
void TriggerIRQ_d(void)
{
void X6502_Run_d(int32 c)
{
- int32 cycles = c << 4; /* *16 */ \
- if (PAL) cycles -= c; /* *15 */ \
+ int32 cycles = c << 4; /* *16 */
+ if (PAL) cycles -= c; /* *15 */
//printf("-- %06i: run(%i)\n", (int)g_cnt, (int)c);
- g_cnt += c;
+ g_cnt += cycles;
- while (cycles > 0)
+ if (c > 200)
+ compare_ram();
+
+ while (g_cnt > 0)
{
- PC_prev = X.PC;
nes_registers[7]=1;
X.count=1;
+ cpu_lastval = 0;
cpu_repeat = 0;
X6502_Run_c();
X6502_Run_a();
compare_state();
- cycles -= 1 - X.count;
+ g_cnt -= 1 - X.count;
+ if (pending_add_cycles) {
+ //X6502_AddCycles_c(pending_add_cycles);
+ //X6502_AddCycles_a(pending_add_cycles);
+ g_cnt -= pending_add_cycles*48;
+ pending_add_cycles = 0;
+ }
+ if (pending_rebase) {
+ X6502_Rebase_a();
+ pending_rebase = 0;
+ }
}
//printf("-- run_end\n");
void X6502_Power_d(void)
{
printf("-- power\n");
+ if (nes_internal_ram == RAM) printf("nes_internal_ram == RAM!!\n");
X6502_Power_c();
X6502_Power_a();
{
printf("-- AddCycles(%i|%i)\n", x, x*48);
- printf("can't use this in debug\n");
- exit(1);
+ pending_add_cycles = x; // *48;
+// printf("can't use this in debug\n");
+// exit(1);
//X6502_AddCycles_c(x);
//X6502_AddCycles_a(x);
//compare_state();
}
+void X6502_Rebase_d(void)
+{
+ pending_rebase = 1;
+}
+
bank&=NSFMaxBank;
if(NSFHeader.SoundChip&4)
memcpy(FDSMEM+(A-0x6000),NSFDATA+(bank<<12),4096);
- else
+ else
setprg4(A,bank);
}
FCEU_fseek(fp,0x80,SEEK_SET);
memset(NSFDATA,0x00,NSFMaxBank*4096);
FCEU_fread(NSFDATA+(LoadAddr&0xfff),1,NSFSize,fp);
-
+
NSFMaxBank--;
BSon=0;
for(x=0;x<32;x++)
{
double ta,no;
-
+
ta=sin(fruit)*7;
ta+=modf(ta,&no);
sinetable[x]=ta;
SetReadHandler(0x4020,0x5fff,NSF_read);
- if(NSFHeader.SoundChip&1) {
+ if(NSFHeader.SoundChip&1) {
VRC6_ESI(0);
} else if (NSFHeader.SoundChip&2) {
VRC7_ESI();
switch(A)
{
case 0x5FF2:if((X.PC&0xF000)==0x3000) DoUpdateStuff=V;break;
-
+
case 0x5FF6:
case 0x5FF7:if(!(NSFHeader.SoundChip&4)) return;
case 0x5FF8:
case 0x5FFF:if(!BSon) return;
A&=0xF;
BANKSET((A*4096),V);
+ X6502_Rebase();
break;
}
}
BWrite[0x4011](0x4011,0x40);
BWrite[0x4015](0x4015,0xF);
BWrite[0x4017](0x4017,0x40);
- if(NSFHeader.SoundChip&4)
+ if(NSFHeader.SoundChip&4)
BWrite[0x4089](0x4089,0x80);
if(BSon)
{
for(x=0;x<8;x++)
BANKSET(0x8000+x*4096,NSFHeader.BankSwitch[x]);
+ X6502_Rebase();
}
return (CurrentSong-1);
}
}
void NSFControl(int z)
-{
+{
if(z==1)
{
if(CurrentSong<NSFHeader.TotalSongs) CurrentSong++;
_PC=POP();
_PC|=POP()<<8;
break;
-
+
case 0x60: /* RTS */
_PC=POP();
_PC|=POP()<<8;
_PC=npc;
}
break; /* JMP ABSOLUTE */
-case 0x6C:
+case 0x6C:
{
uint32 tmp;
GetAB(tmp);
case 0x83: ST_IX(_A&_X);
/* ARR - ARGH, MATEY! */
-case 0x6B: {
- uint8 arrtmp;
+case 0x6B: {
+ uint8 arrtmp;
LD_IM(AND;_P&=~V_FLAG;_P|=(_A^(_A>>1))&0x40;arrtmp=_A>>7;_A>>=1;_A|=(_P&C_FLAG)<<7;_P&=~C_FLAG;_P|=arrtmp;X_ZN(_A));
}
/* ASR */
/* ATX(OAL) Is this(OR with $EE) correct? */
case 0xAB: LD_IM(_A|=0xEE;AND;_X=_A);
-/* AXS */
+/* AXS */
case 0xCB: LD_IM(AXS);
/* DCP */
/* TOP */
case 0x0C: LD_AB(;);
-case 0x1C:
-case 0x3C:
-case 0x5C:
-case 0x7C:
-case 0xDC:
+case 0x1C:
+case 0x3C:
+case 0x5C:
+case 0x7C:
+case 0xDC:
case 0xFC: LD_ABX(;);
/* XAA - BIG QUESTION MARK HERE */
--------------------------------------------------------------------\r
\r
\r
+ver 0.4 (by notaz)\r
+\r
+ - Compatibility fixes for the asm core.\r
+ - Fixed an anligment problem in MMC5 mapper.\r
+\r
+\r
ver 0.3 (by notaz)\r
\r
- Major improvement: added ARM asm CPU core from LJGP32,\r
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <stdio.h>
+
void SaveState(void);
void LoadState(void);
int FCEUSS_LoadFP(FILE *st, int make_backup);
#include "sound.h"
#include "cart.h"
+#ifdef DEBUG_ASM_6502
+extern uint32 PC_prev, OP_prev;
+extern int cpu_lastval;
+#endif
+
X6502 X;
uint32 timestamp;
void FP_FASTAPASS(1) (*MapIRQHook)(int a);
return (_DB=RAM[A&0x7FF]);
}
#endif
- return((_DB=ARead[A](A)));
+ _DB=ARead[A](A);
+#ifdef DEBUG_ASM_6502
+ // TODO: read counter, not 0x10000..
+ if (cpu_lastval)
+ cpu_lastval|=_DB<<8;
+ else
+ cpu_lastval=_DB|0x10000;
+ printf("read [%04x] %02x, cpu_lastval=%02x\n", A, _DB, cpu_lastval);
+#endif
+ return _DB;
}
static INLINE void WrMem(unsigned int A, uint8 V)
//#define X_ZN(zort) _P&=~(Z_FLAG|N_FLAG);_P|=ZNTable[zort]
//#define X_ZNT(zort) _P|=ZNTable[zort]
#define X_ZN(zort) _P&=~(Z_FLAG|N_FLAG);if(!zort) _P|=Z_FLAG;else _P|=zort&N_FLAG
-#define X_ZNT(zort) if(!zort) _P|=Z_FLAG;else _P|=zort&N_FLAG
+#define X_ZNT(zort) if(!zort) _P|=Z_FLAG;else _P|=(zort&N_FLAG)
/* Care must be taken if you want to turn this into a macro. Use { and }. */
#define JR(); \
ADDCYC(7);
PUSH(_PC>>8);
PUSH(_PC);
- PUSH((_P&~B_FLAG)|(U_FLAG));
+ _P&=~B_FLAG;
+ PUSH(_P|U_FLAG);
_PC=RdMem(0xFFFA);
_PC|=RdMem(0xFFFB)<<8;
+#ifdef DEBUG_ASM_6502
+ PC_prev = _PC;
+ OP_prev = 0x100;
+#endif
}
}
ADDCYC(7);
PUSH(_PC>>8);
PUSH(_PC);
- PUSH((_P&~B_FLAG)|(U_FLAG));
+ _P&=~B_FLAG;
+ PUSH(_P|U_FLAG);
_P|=I_FLAG;
_PC=RdMem(0xFFFE);
_PC|=RdMem(0xFFFF)<<8;
+#ifdef DEBUG_ASM_6502
+ PC_prev = _PC;
+ OP_prev = 0x101;
+#endif
}
}
//int asdc = 0;
-
void X6502_Run_c(void/*int32 cycles*/)
{
/*
}
}
+#ifdef DEBUG_ASM_6502
+ PC_prev = _PC;
+ OP_prev = b1;
+ cpu_lastval = 0;
+#endif
//printf("$%04x:$%02x\n",_PC,b1);
//_PC++;
//printf("$%02x\n",b1);
#define X6502_AddCycles X6502_AddCycles_d
#define X6502_IRQBegin X6502_IRQBegin_d
#define X6502_IRQEnd X6502_IRQEnd_d
+#define X6502_Rebase X6502_Rebase_d
#define X6502_C
#define X6502_A
#define X6502_D
#define X6502_AddCycles X6502_AddCycles_a
#define X6502_IRQBegin X6502_IRQBegin_a
#define X6502_IRQEnd X6502_IRQEnd_a
+#define X6502_Rebase X6502_Rebase_a
#define X6502_A
#define X6502_Run(c) \
#define X6502_AddCycles X6502_AddCycles_c
#define X6502_IRQBegin X6502_IRQBegin_c
#define X6502_IRQEnd X6502_IRQEnd_c
+#define X6502_Rebase(...)
#define X6502_C
#define X6502_Run(c) \
void X6502_AddCycles_a(int x);
void X6502_IRQBegin_a(int w);
void X6502_IRQEnd_a(int w);
-void X6502_rebase_a(void);
+void X6502_Rebase_a(void);
#endif
// debug
void X6502_AddCycles_d(int x);
void X6502_IRQBegin_d(int w);
void X6502_IRQEnd_d(int w);
+void X6502_Rebase_d(void);
#endif