drc: fix JALR with non-r31 return register
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
57871462 182
183 /* stubs */
184#define CC_STUB 1
185#define FP_STUB 2
186#define LOADB_STUB 3
187#define LOADH_STUB 4
188#define LOADW_STUB 5
189#define LOADD_STUB 6
190#define LOADBU_STUB 7
191#define LOADHU_STUB 8
192#define STOREB_STUB 9
193#define STOREH_STUB 10
194#define STOREW_STUB 11
195#define STORED_STUB 12
196#define STORELR_STUB 13
197#define INVCODE_STUB 14
198
199 /* branch codes */
200#define TAKEN 1
201#define NOTTAKEN 2
202#define NULLDS 3
203
204// asm linkage
205int new_recompile_block(int addr);
206void *get_addr_ht(u_int vaddr);
207void invalidate_block(u_int block);
208void invalidate_addr(u_int addr);
209void remove_hash(int vaddr);
210void jump_vaddr();
211void dyna_linker();
212void dyna_linker_ds();
213void verify_code();
214void verify_code_vm();
215void verify_code_ds();
216void cc_interrupt();
217void fp_exception();
218void fp_exception_ds();
219void jump_syscall();
7139f3c8 220void jump_syscall_hle();
57871462 221void jump_eret();
7139f3c8 222void jump_hlecall();
223void new_dyna_leave();
57871462 224
225// TLB
226void TLBWI_new();
227void TLBWR_new();
228void read_nomem_new();
229void read_nomemb_new();
230void read_nomemh_new();
231void read_nomemd_new();
232void write_nomem_new();
233void write_nomemb_new();
234void write_nomemh_new();
235void write_nomemd_new();
236void write_rdram_new();
237void write_rdramb_new();
238void write_rdramh_new();
239void write_rdramd_new();
240extern u_int memory_map[1048576];
241
242// Needed by assembler
243void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246void load_all_regs(signed char i_regmap[]);
247void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248void load_regs_entry(int t);
249void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
250
251int tracedebug=0;
252
253//#define DEBUG_CYCLE_COUNT 1
254
255void nullf() {}
256//#define assem_debug printf
257//#define inv_debug printf
258#define assem_debug nullf
259#define inv_debug nullf
260
94d23bb9 261static void tlb_hacks()
57871462 262{
94d23bb9 263#ifndef DISABLE_TLB
57871462 264 // Goldeneye hack
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
266 {
267 u_int addr;
268 int n;
269 switch (ROM_HEADER->Country_code&0xFF)
270 {
271 case 0x45: // U
272 addr=0x34b30;
273 break;
274 case 0x4A: // J
275 addr=0x34b70;
276 break;
277 case 0x50: // E
278 addr=0x329f0;
279 break;
280 default:
281 // Unknown country code
282 addr=0;
283 break;
284 }
285 u_int rom_addr=(u_int)rom;
286 #ifdef ROM_COPY
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
297 }
298 #endif
299 if(addr) {
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
302 }
303 }
304 }
94d23bb9 305#endif
57871462 306}
307
94d23bb9 308static u_int get_page(u_int vaddr)
57871462 309{
310 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 311#ifndef DISABLE_TLB
57871462 312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 313#endif
57871462 314 if(page>2048) page=2048+(page&2047);
94d23bb9 315 return page;
316}
317
318static u_int get_vpage(u_int vaddr)
319{
320 u_int vpage=(vaddr^0x80000000)>>12;
321#ifndef DISABLE_TLB
57871462 322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 323#endif
57871462 324 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 325 return vpage;
326}
327
328// Get address from virtual address
329// This is called from the recompiled JR/JALR instructions
330void *get_addr(u_int vaddr)
331{
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
57871462 334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
336 head=jump_in[page];
337 while(head!=NULL) {
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
341 ht_bin[3]=ht_bin[1];
342 ht_bin[2]=ht_bin[0];
343 ht_bin[1]=(int)head->addr;
344 ht_bin[0]=vaddr;
345 return head->addr;
346 }
347 head=head->next;
348 }
349 head=jump_dirty[vpage];
350 while(head!=NULL) {
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
359 if(vpage<2048) {
94d23bb9 360#ifndef DISABLE_TLB
57871462 361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
364 }
94d23bb9 365#endif
57871462 366 restore_candidate[vpage>>3]|=1<<(vpage&7);
367 }
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
372 }
373 else
374 {
375 ht_bin[3]=ht_bin[1];
376 ht_bin[2]=ht_bin[0];
377 ht_bin[1]=(int)head->addr;
378 ht_bin[0]=vaddr;
379 }
380 return head->addr;
381 }
382 }
383 head=head->next;
384 }
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
389 Status|=2;
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
392 BadVAddr=(vaddr&~1);
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
396}
397// Look up address in hash table first
398void *get_addr_ht(u_int vaddr)
399{
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
405}
406
407void *get_addr_32(u_int vaddr,u_int flags)
408{
7139f3c8 409#ifdef FORCE32
410 return get_addr(vaddr);
411#endif
57871462 412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
57871462 418 struct ll_entry *head;
419 head=jump_in[page];
420 while(head!=NULL) {
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
423 if(head->reg32==0) {
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==-1) {
426 ht_bin[1]=(int)head->addr;
427 ht_bin[0]=vaddr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
430 ht_bin[2]=vaddr;
431 }
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
435 //ht_bin[0]=vaddr;
436 }
437 return head->addr;
438 }
439 head=head->next;
440 }
441 head=jump_dirty[vpage];
442 while(head!=NULL) {
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
451 if(vpage<2048) {
94d23bb9 452#ifndef DISABLE_TLB
57871462 453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
456 }
94d23bb9 457#endif
57871462 458 restore_candidate[vpage>>3]|=1<<(vpage&7);
459 }
460 else restore_candidate[page>>3]|=1<<(page&7);
461 if(head->reg32==0) {
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
463 if(ht_bin[0]==-1) {
464 ht_bin[1]=(int)head->addr;
465 ht_bin[0]=vaddr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
468 ht_bin[2]=vaddr;
469 }
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
473 //ht_bin[0]=vaddr;
474 }
475 return head->addr;
476 }
477 }
478 head=head->next;
479 }
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
484 Status|=2;
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
487 BadVAddr=(vaddr&~1);
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
491}
492
493void clear_all_regs(signed char regmap[])
494{
495 int hr;
496 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
497}
498
499signed char get_reg(signed char regmap[],int r)
500{
501 int hr;
502 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
503 return -1;
504}
505
506// Find a register that is available for two consecutive cycles
507signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
508{
509 int hr;
510 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
511 return -1;
512}
513
514int count_free_regs(signed char regmap[])
515{
516 int count=0;
517 int hr;
518 for(hr=0;hr<HOST_REGS;hr++)
519 {
520 if(hr!=EXCLUDE_REG) {
521 if(regmap[hr]<0) count++;
522 }
523 }
524 return count;
525}
526
527void dirty_reg(struct regstat *cur,signed char reg)
528{
529 int hr;
530 if(!reg) return;
531 for (hr=0;hr<HOST_REGS;hr++) {
532 if((cur->regmap[hr]&63)==reg) {
533 cur->dirty|=1<<hr;
534 }
535 }
536}
537
538// If we dirty the lower half of a 64 bit register which is now being
539// sign-extended, we need to dump the upper half.
540// Note: Do this only after completion of the instruction, because
541// some instructions may need to read the full 64-bit value even if
542// overwriting it (eg SLTI, DSRA32).
543static void flush_dirty_uppers(struct regstat *cur)
544{
545 int hr,reg;
546 for (hr=0;hr<HOST_REGS;hr++) {
547 if((cur->dirty>>hr)&1) {
548 reg=cur->regmap[hr];
549 if(reg>=64)
550 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
551 }
552 }
553}
554
555void set_const(struct regstat *cur,signed char reg,uint64_t value)
556{
557 int hr;
558 if(!reg) return;
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if(cur->regmap[hr]==reg) {
561 cur->isconst|=1<<hr;
562 cur->constmap[hr]=value;
563 }
564 else if((cur->regmap[hr]^64)==reg) {
565 cur->isconst|=1<<hr;
566 cur->constmap[hr]=value>>32;
567 }
568 }
569}
570
571void clear_const(struct regstat *cur,signed char reg)
572{
573 int hr;
574 if(!reg) return;
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->isconst&=~(1<<hr);
578 }
579 }
580}
581
582int is_const(struct regstat *cur,signed char reg)
583{
584 int hr;
585 if(!reg) return 1;
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
588 return (cur->isconst>>hr)&1;
589 }
590 }
591 return 0;
592}
593uint64_t get_const(struct regstat *cur,signed char reg)
594{
595 int hr;
596 if(!reg) return 0;
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if(cur->regmap[hr]==reg) {
599 return cur->constmap[hr];
600 }
601 }
602 printf("Unknown constant in r%d\n",reg);
603 exit(1);
604}
605
606// Least soon needed registers
607// Look at the next ten instructions and see which registers
608// will be used. Try not to reallocate these.
609void lsn(u_char hsn[], int i, int *preferred_reg)
610{
611 int j;
612 int b=-1;
613 for(j=0;j<9;j++)
614 {
615 if(i+j>=slen) {
616 j=slen-i-1;
617 break;
618 }
619 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
620 {
621 // Don't go past an unconditonal jump
622 j++;
623 break;
624 }
625 }
626 for(;j>=0;j--)
627 {
628 if(rs1[i+j]) hsn[rs1[i+j]]=j;
629 if(rs2[i+j]) hsn[rs2[i+j]]=j;
630 if(rt1[i+j]) hsn[rt1[i+j]]=j;
631 if(rt2[i+j]) hsn[rt2[i+j]]=j;
632 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
633 // Stores can allocate zero
634 hsn[rs1[i+j]]=j;
635 hsn[rs2[i+j]]=j;
636 }
637 // On some architectures stores need invc_ptr
638 #if defined(HOST_IMM8)
b9b61529 639 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 640 hsn[INVCP]=j;
641 }
642 #endif
643 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
644 {
645 hsn[CCREG]=j;
646 b=j;
647 }
648 }
649 if(b>=0)
650 {
651 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
652 {
653 // Follow first branch
654 int t=(ba[i+b]-start)>>2;
655 j=7-b;if(t+j>=slen) j=slen-t-1;
656 for(;j>=0;j--)
657 {
658 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
659 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
660 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
661 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
662 }
663 }
664 // TODO: preferred register based on backward branch
665 }
666 // Delay slot should preferably not overwrite branch conditions or cycle count
667 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
668 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
669 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
670 hsn[CCREG]=1;
671 // ...or hash tables
672 hsn[RHASH]=1;
673 hsn[RHTBL]=1;
674 }
675 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 676 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 677 hsn[FTEMP]=0;
678 }
679 // Load L/R also uses FTEMP as a temporary register
680 if(itype[i]==LOADLR) {
681 hsn[FTEMP]=0;
682 }
683 // Also 64-bit SDL/SDR
684 if(opcode[i]==0x2c||opcode[i]==0x2d) {
685 hsn[FTEMP]=0;
686 }
687 // Don't remove the TLB registers either
b9b61529 688 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 689 hsn[TLREG]=0;
690 }
691 // Don't remove the miniht registers
692 if(itype[i]==UJUMP||itype[i]==RJUMP)
693 {
694 hsn[RHASH]=0;
695 hsn[RHTBL]=0;
696 }
697}
698
699// We only want to allocate registers if we're going to use them again soon
700int needed_again(int r, int i)
701{
702 int j;
703 int b=-1;
704 int rn=10;
705 int hr;
706 u_char hsn[MAXREG+1];
707 int preferred_reg;
708
709 memset(hsn,10,sizeof(hsn));
710 lsn(hsn,i,&preferred_reg);
711
712 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
713 {
714 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
715 return 0; // Don't need any registers if exiting the block
716 }
717 for(j=0;j<9;j++)
718 {
719 if(i+j>=slen) {
720 j=slen-i-1;
721 break;
722 }
723 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
724 {
725 // Don't go past an unconditonal jump
726 j++;
727 break;
728 }
7139f3c8 729 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 730 {
731 break;
732 }
733 }
734 for(;j>=1;j--)
735 {
736 if(rs1[i+j]==r) rn=j;
737 if(rs2[i+j]==r) rn=j;
738 if((unneeded_reg[i+j]>>r)&1) rn=10;
739 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
740 {
741 b=j;
742 }
743 }
744 /*
745 if(b>=0)
746 {
747 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
748 {
749 // Follow first branch
750 int o=rn;
751 int t=(ba[i+b]-start)>>2;
752 j=7-b;if(t+j>=slen) j=slen-t-1;
753 for(;j>=0;j--)
754 {
755 if(!((unneeded_reg[t+j]>>r)&1)) {
756 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
757 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
758 }
759 else rn=o;
760 }
761 }
762 }*/
763 for(hr=0;hr<HOST_REGS;hr++) {
764 if(hr!=EXCLUDE_REG) {
765 if(rn<hsn[hr]) return 1;
766 }
767 }
768 return 0;
769}
770
771// Try to match register allocations at the end of a loop with those
772// at the beginning
773int loop_reg(int i, int r, int hr)
774{
775 int j,k;
776 for(j=0;j<9;j++)
777 {
778 if(i+j>=slen) {
779 j=slen-i-1;
780 break;
781 }
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
783 {
784 // Don't go past an unconditonal jump
785 j++;
786 break;
787 }
788 }
789 k=0;
790 if(i>0){
791 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
792 k--;
793 }
794 for(;k<j;k++)
795 {
796 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
797 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
798 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
799 {
800 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
801 {
802 int t=(ba[i+k]-start)>>2;
803 int reg=get_reg(regs[t].regmap_entry,r);
804 if(reg>=0) return reg;
805 //reg=get_reg(regs[t+1].regmap_entry,r);
806 //if(reg>=0) return reg;
807 }
808 }
809 }
810 return hr;
811}
812
813
814// Allocate every register, preserving source/target regs
815void alloc_all(struct regstat *cur,int i)
816{
817 int hr;
818
819 for(hr=0;hr<HOST_REGS;hr++) {
820 if(hr!=EXCLUDE_REG) {
821 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
822 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
823 {
824 cur->regmap[hr]=-1;
825 cur->dirty&=~(1<<hr);
826 }
827 // Don't need zeros
828 if((cur->regmap[hr]&63)==0)
829 {
830 cur->regmap[hr]=-1;
831 cur->dirty&=~(1<<hr);
832 }
833 }
834 }
835}
836
837
838void div64(int64_t dividend,int64_t divisor)
839{
840 lo=dividend/divisor;
841 hi=dividend%divisor;
842 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
843 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
844}
845void divu64(uint64_t dividend,uint64_t divisor)
846{
847 lo=dividend/divisor;
848 hi=dividend%divisor;
849 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
850 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
851}
852
853void mult64(uint64_t m1,uint64_t m2)
854{
855 unsigned long long int op1, op2, op3, op4;
856 unsigned long long int result1, result2, result3, result4;
857 unsigned long long int temp1, temp2, temp3, temp4;
858 int sign = 0;
859
860 if (m1 < 0)
861 {
862 op2 = -m1;
863 sign = 1 - sign;
864 }
865 else op2 = m1;
866 if (m2 < 0)
867 {
868 op4 = -m2;
869 sign = 1 - sign;
870 }
871 else op4 = m2;
872
873 op1 = op2 & 0xFFFFFFFF;
874 op2 = (op2 >> 32) & 0xFFFFFFFF;
875 op3 = op4 & 0xFFFFFFFF;
876 op4 = (op4 >> 32) & 0xFFFFFFFF;
877
878 temp1 = op1 * op3;
879 temp2 = (temp1 >> 32) + op1 * op4;
880 temp3 = op2 * op3;
881 temp4 = (temp3 >> 32) + op2 * op4;
882
883 result1 = temp1 & 0xFFFFFFFF;
884 result2 = temp2 + (temp3 & 0xFFFFFFFF);
885 result3 = (result2 >> 32) + temp4;
886 result4 = (result3 >> 32);
887
888 lo = result1 | (result2 << 32);
889 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
890 if (sign)
891 {
892 hi = ~hi;
893 if (!lo) hi++;
894 else lo = ~lo + 1;
895 }
896}
897
898void multu64(uint64_t m1,uint64_t m2)
899{
900 unsigned long long int op1, op2, op3, op4;
901 unsigned long long int result1, result2, result3, result4;
902 unsigned long long int temp1, temp2, temp3, temp4;
903
904 op1 = m1 & 0xFFFFFFFF;
905 op2 = (m1 >> 32) & 0xFFFFFFFF;
906 op3 = m2 & 0xFFFFFFFF;
907 op4 = (m2 >> 32) & 0xFFFFFFFF;
908
909 temp1 = op1 * op3;
910 temp2 = (temp1 >> 32) + op1 * op4;
911 temp3 = op2 * op3;
912 temp4 = (temp3 >> 32) + op2 * op4;
913
914 result1 = temp1 & 0xFFFFFFFF;
915 result2 = temp2 + (temp3 & 0xFFFFFFFF);
916 result3 = (result2 >> 32) + temp4;
917 result4 = (result3 >> 32);
918
919 lo = result1 | (result2 << 32);
920 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
921
922 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
923 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
924}
925
926uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
927{
928 if(bits) {
929 original<<=64-bits;
930 original>>=64-bits;
931 loaded<<=bits;
932 original|=loaded;
933 }
934 else original=loaded;
935 return original;
936}
937uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
938{
939 if(bits^56) {
940 original>>=64-(bits^56);
941 original<<=64-(bits^56);
942 loaded>>=bits^56;
943 original|=loaded;
944 }
945 else original=loaded;
946 return original;
947}
948
949#ifdef __i386__
950#include "assem_x86.c"
951#endif
952#ifdef __x86_64__
953#include "assem_x64.c"
954#endif
955#ifdef __arm__
956#include "assem_arm.c"
957#endif
958
959// Add virtual address mapping to linked list
960void ll_add(struct ll_entry **head,int vaddr,void *addr)
961{
962 struct ll_entry *new_entry;
963 new_entry=malloc(sizeof(struct ll_entry));
964 assert(new_entry!=NULL);
965 new_entry->vaddr=vaddr;
966 new_entry->reg32=0;
967 new_entry->addr=addr;
968 new_entry->next=*head;
969 *head=new_entry;
970}
971
972// Add virtual address mapping for 32-bit compiled block
973void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
974{
7139f3c8 975 ll_add(head,vaddr,addr);
976#ifndef FORCE32
977 (*head)->reg32=reg32;
978#endif
57871462 979}
980
981// Check if an address is already compiled
982// but don't return addresses which are about to expire from the cache
983void *check_addr(u_int vaddr)
984{
985 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
986 if(ht_bin[0]==vaddr) {
987 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
988 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
989 }
990 if(ht_bin[2]==vaddr) {
991 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
992 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
993 }
94d23bb9 994 u_int page=get_page(vaddr);
57871462 995 struct ll_entry *head;
996 head=jump_in[page];
997 while(head!=NULL) {
998 if(head->vaddr==vaddr&&head->reg32==0) {
999 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000 // Update existing entry with current address
1001 if(ht_bin[0]==vaddr) {
1002 ht_bin[1]=(int)head->addr;
1003 return head->addr;
1004 }
1005 if(ht_bin[2]==vaddr) {
1006 ht_bin[3]=(int)head->addr;
1007 return head->addr;
1008 }
1009 // Insert into hash table with low priority.
1010 // Don't evict existing entries, as they are probably
1011 // addresses that are being accessed frequently.
1012 if(ht_bin[0]==-1) {
1013 ht_bin[1]=(int)head->addr;
1014 ht_bin[0]=vaddr;
1015 }else if(ht_bin[2]==-1) {
1016 ht_bin[3]=(int)head->addr;
1017 ht_bin[2]=vaddr;
1018 }
1019 return head->addr;
1020 }
1021 }
1022 head=head->next;
1023 }
1024 return 0;
1025}
1026
1027void remove_hash(int vaddr)
1028{
1029 //printf("remove hash: %x\n",vaddr);
1030 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031 if(ht_bin[2]==vaddr) {
1032 ht_bin[2]=ht_bin[3]=-1;
1033 }
1034 if(ht_bin[0]==vaddr) {
1035 ht_bin[0]=ht_bin[2];
1036 ht_bin[1]=ht_bin[3];
1037 ht_bin[2]=ht_bin[3]=-1;
1038 }
1039}
1040
1041void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1042{
1043 struct ll_entry *next;
1044 while(*head) {
1045 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1047 {
1048 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049 remove_hash((*head)->vaddr);
1050 next=(*head)->next;
1051 free(*head);
1052 *head=next;
1053 }
1054 else
1055 {
1056 head=&((*head)->next);
1057 }
1058 }
1059}
1060
1061// Remove all entries from linked list
1062void ll_clear(struct ll_entry **head)
1063{
1064 struct ll_entry *cur;
1065 struct ll_entry *next;
1066 if(cur=*head) {
1067 *head=0;
1068 while(cur) {
1069 next=cur->next;
1070 free(cur);
1071 cur=next;
1072 }
1073 }
1074}
1075
1076// Dereference the pointers and remove if it matches
1077void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1078{
1079 while(head) {
1080 int ptr=get_pointer(head->addr);
1081 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082 if(((ptr>>shift)==(addr>>shift)) ||
1083 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1084 {
1085 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086 kill_pointer(head->addr);
1087 }
1088 head=head->next;
1089 }
1090}
1091
1092// This is called when we write to a compiled block (see do_invstub)
1093int invalidate_page(u_int page)
1094{
1095 int modified=0;
1096 struct ll_entry *head;
1097 struct ll_entry *next;
1098 head=jump_in[page];
1099 jump_in[page]=0;
1100 while(head!=NULL) {
1101 inv_debug("INVALIDATE: %x\n",head->vaddr);
1102 remove_hash(head->vaddr);
1103 next=head->next;
1104 free(head);
1105 head=next;
1106 }
1107 head=jump_out[page];
1108 jump_out[page]=0;
1109 while(head!=NULL) {
1110 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111 kill_pointer(head->addr);
1112 modified=1;
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 return modified;
1118}
1119void invalidate_block(u_int block)
1120{
1121 int modified;
94d23bb9 1122 u_int page=get_page(block<<12);
1123 u_int vpage=get_vpage(block<<12);
57871462 1124 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1126 u_int first,last;
1127 first=last=page;
1128 struct ll_entry *head;
1129 head=jump_dirty[vpage];
1130 //printf("page=%d vpage=%d\n",page,vpage);
1131 while(head!=NULL) {
1132 u_int start,end;
1133 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134 get_bounds((int)head->addr,&start,&end);
1135 //printf("start: %x end: %x\n",start,end);
1136 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1140 }
1141 }
90ae6d4e 1142#ifndef DISABLE_TLB
57871462 1143 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1147 }
1148 }
90ae6d4e 1149#endif
57871462 1150 }
1151 head=head->next;
1152 }
1153 //printf("first=%d last=%d\n",first,last);
1154 modified=invalidate_page(page);
1155 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156 assert(last<page+5);
1157 // Invalidate the adjacent pages if a block crosses a 4K boundary
1158 while(first<page) {
1159 invalidate_page(first);
1160 first++;
1161 }
1162 for(first=page+1;first<last;first++) {
1163 invalidate_page(first);
1164 }
1165
1166 // Don't trap writes
1167 invalid_code[block]=1;
94d23bb9 1168#ifndef DISABLE_TLB
57871462 1169 // If there is a valid TLB entry for this page, remove write protect
1170 if(tlb_LUT_w[block]) {
1171 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172 // CHECK: Is this right?
1173 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174 u_int real_block=tlb_LUT_w[block]>>12;
1175 invalid_code[real_block]=1;
1176 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177 }
1178 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1179#endif
57871462 1180 #ifdef __arm__
1181 if(modified)
1182 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1183 #endif
1184 #ifdef USE_MINI_HT
1185 memset(mini_ht,-1,sizeof(mini_ht));
1186 #endif
1187}
1188void invalidate_addr(u_int addr)
1189{
1190 invalidate_block(addr>>12);
1191}
1192void invalidate_all_pages()
1193{
1194 u_int page,n;
1195 for(page=0;page<4096;page++)
1196 invalidate_page(page);
1197 for(page=0;page<1048576;page++)
1198 if(!invalid_code[page]) {
1199 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1201 }
1202 #ifdef __arm__
1203 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1204 #endif
1205 #ifdef USE_MINI_HT
1206 memset(mini_ht,-1,sizeof(mini_ht));
1207 #endif
94d23bb9 1208 #ifndef DISABLE_TLB
57871462 1209 // TLB
1210 for(page=0;page<0x100000;page++) {
1211 if(tlb_LUT_r[page]) {
1212 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213 if(!tlb_LUT_w[page]||!invalid_code[page])
1214 memory_map[page]|=0x40000000; // Write protect
1215 }
1216 else memory_map[page]=-1;
1217 if(page==0x80000) page=0xC0000;
1218 }
1219 tlb_hacks();
94d23bb9 1220 #endif
57871462 1221}
1222
1223// Add an entry to jump_out after making a link
1224void add_link(u_int vaddr,void *src)
1225{
94d23bb9 1226 u_int page=get_page(vaddr);
57871462 1227 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228 ll_add(jump_out+page,vaddr,src);
1229 //int ptr=get_pointer(src);
1230 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1231}
1232
1233// If a code block was found to be unmodified (bit was set in
1234// restore_candidate) and it remains unmodified (bit is clear
1235// in invalid_code) then move the entries for that 4K page from
1236// the dirty list to the clean list.
1237void clean_blocks(u_int page)
1238{
1239 struct ll_entry *head;
1240 inv_debug("INV: clean_blocks page=%d\n",page);
1241 head=jump_dirty[page];
1242 while(head!=NULL) {
1243 if(!invalid_code[head->vaddr>>12]) {
1244 // Don't restore blocks which are about to expire from the cache
1245 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1246 u_int start,end;
1247 if(verify_dirty((int)head->addr)) {
1248 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1249 u_int i;
1250 u_int inv=0;
1251 get_bounds((int)head->addr,&start,&end);
1252 if(start-(u_int)rdram<0x800000) {
1253 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254 inv|=invalid_code[i];
1255 }
1256 }
1257 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260 if(addr<start||addr>=end) inv=1;
1261 }
1262 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1263 inv=1;
1264 }
1265 if(!inv) {
1266 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1268 u_int ppage=page;
94d23bb9 1269#ifndef DISABLE_TLB
57871462 1270 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1271#endif
57871462 1272 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273 //printf("page=%x, addr=%x\n",page,head->vaddr);
1274 //assert(head->vaddr>>12==(page|0x80000));
1275 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1277 if(!head->reg32) {
1278 if(ht_bin[0]==head->vaddr) {
1279 ht_bin[1]=(int)clean_addr; // Replace existing entry
1280 }
1281 if(ht_bin[2]==head->vaddr) {
1282 ht_bin[3]=(int)clean_addr; // Replace existing entry
1283 }
1284 }
1285 }
1286 }
1287 }
1288 }
1289 }
1290 head=head->next;
1291 }
1292}
1293
1294
1295void mov_alloc(struct regstat *current,int i)
1296{
1297 // Note: Don't need to actually alloc the source registers
1298 if((~current->is32>>rs1[i])&1) {
1299 //alloc_reg64(current,i,rs1[i]);
1300 alloc_reg64(current,i,rt1[i]);
1301 current->is32&=~(1LL<<rt1[i]);
1302 } else {
1303 //alloc_reg(current,i,rs1[i]);
1304 alloc_reg(current,i,rt1[i]);
1305 current->is32|=(1LL<<rt1[i]);
1306 }
1307 clear_const(current,rs1[i]);
1308 clear_const(current,rt1[i]);
1309 dirty_reg(current,rt1[i]);
1310}
1311
1312void shiftimm_alloc(struct regstat *current,int i)
1313{
1314 clear_const(current,rs1[i]);
1315 clear_const(current,rt1[i]);
1316 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1317 {
1318 if(rt1[i]) {
1319 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1320 else lt1[i]=rs1[i];
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=1LL<<rt1[i];
1323 dirty_reg(current,rt1[i]);
1324 }
1325 }
1326 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1327 {
1328 if(rt1[i]) {
1329 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330 alloc_reg64(current,i,rt1[i]);
1331 current->is32&=~(1LL<<rt1[i]);
1332 dirty_reg(current,rt1[i]);
1333 }
1334 }
1335 if(opcode2[i]==0x3c) // DSLL32
1336 {
1337 if(rt1[i]) {
1338 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339 alloc_reg64(current,i,rt1[i]);
1340 current->is32&=~(1LL<<rt1[i]);
1341 dirty_reg(current,rt1[i]);
1342 }
1343 }
1344 if(opcode2[i]==0x3e) // DSRL32
1345 {
1346 if(rt1[i]) {
1347 alloc_reg64(current,i,rs1[i]);
1348 if(imm[i]==32) {
1349 alloc_reg64(current,i,rt1[i]);
1350 current->is32&=~(1LL<<rt1[i]);
1351 } else {
1352 alloc_reg(current,i,rt1[i]);
1353 current->is32|=1LL<<rt1[i];
1354 }
1355 dirty_reg(current,rt1[i]);
1356 }
1357 }
1358 if(opcode2[i]==0x3f) // DSRA32
1359 {
1360 if(rt1[i]) {
1361 alloc_reg64(current,i,rs1[i]);
1362 alloc_reg(current,i,rt1[i]);
1363 current->is32|=1LL<<rt1[i];
1364 dirty_reg(current,rt1[i]);
1365 }
1366 }
1367}
1368
1369void shift_alloc(struct regstat *current,int i)
1370{
1371 if(rt1[i]) {
1372 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1373 {
1374 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378 current->is32|=1LL<<rt1[i];
1379 } else { // DSLLV/DSRLV/DSRAV
1380 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382 alloc_reg64(current,i,rt1[i]);
1383 current->is32&=~(1LL<<rt1[i]);
1384 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385 alloc_reg_temp(current,i,-1);
1386 }
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rs2[i]);
1389 clear_const(current,rt1[i]);
1390 dirty_reg(current,rt1[i]);
1391 }
1392}
1393
1394void alu_alloc(struct regstat *current,int i)
1395{
1396 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1397 if(rt1[i]) {
1398 if(rs1[i]&&rs2[i]) {
1399 alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rs2[i]);
1401 }
1402 else {
1403 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1405 }
1406 alloc_reg(current,i,rt1[i]);
1407 }
1408 current->is32|=1LL<<rt1[i];
1409 }
1410 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1411 if(rt1[i]) {
1412 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1413 {
1414 alloc_reg64(current,i,rs1[i]);
1415 alloc_reg64(current,i,rs2[i]);
1416 alloc_reg(current,i,rt1[i]);
1417 } else {
1418 alloc_reg(current,i,rs1[i]);
1419 alloc_reg(current,i,rs2[i]);
1420 alloc_reg(current,i,rt1[i]);
1421 }
1422 }
1423 current->is32|=1LL<<rt1[i];
1424 }
1425 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1426 if(rt1[i]) {
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1430 }
1431 else
1432 {
1433 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1435 }
1436 alloc_reg(current,i,rt1[i]);
1437 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438 {
1439 if(!((current->uu>>rt1[i])&1)) {
1440 alloc_reg64(current,i,rt1[i]);
1441 }
1442 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443 if(rs1[i]&&rs2[i]) {
1444 alloc_reg64(current,i,rs1[i]);
1445 alloc_reg64(current,i,rs2[i]);
1446 }
1447 else
1448 {
1449 // Is is really worth it to keep 64-bit values in registers?
1450 #ifdef NATIVE_64BIT
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1453 #endif
1454 }
1455 }
1456 current->is32&=~(1LL<<rt1[i]);
1457 } else {
1458 current->is32|=1LL<<rt1[i];
1459 }
1460 }
1461 }
1462 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1463 if(rt1[i]) {
1464 if(rs1[i]&&rs2[i]) {
1465 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 alloc_reg64(current,i,rt1[i]);
1469 } else {
1470 alloc_reg(current,i,rs1[i]);
1471 alloc_reg(current,i,rs2[i]);
1472 alloc_reg(current,i,rt1[i]);
1473 }
1474 }
1475 else {
1476 alloc_reg(current,i,rt1[i]);
1477 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478 // DADD used as move, or zeroing
1479 // If we have a 64-bit source, then make the target 64 bits too
1480 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482 alloc_reg64(current,i,rt1[i]);
1483 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1486 }
1487 if(opcode2[i]>=0x2e&&rs2[i]) {
1488 // DSUB used as negation - 64-bit result
1489 // If we have a 32-bit register, extend it to 64 bits
1490 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491 alloc_reg64(current,i,rt1[i]);
1492 }
1493 }
1494 }
1495 if(rs1[i]&&rs2[i]) {
1496 current->is32&=~(1LL<<rt1[i]);
1497 } else if(rs1[i]) {
1498 current->is32&=~(1LL<<rt1[i]);
1499 if((current->is32>>rs1[i])&1)
1500 current->is32|=1LL<<rt1[i];
1501 } else if(rs2[i]) {
1502 current->is32&=~(1LL<<rt1[i]);
1503 if((current->is32>>rs2[i])&1)
1504 current->is32|=1LL<<rt1[i];
1505 } else {
1506 current->is32|=1LL<<rt1[i];
1507 }
1508 }
1509 }
1510 clear_const(current,rs1[i]);
1511 clear_const(current,rs2[i]);
1512 clear_const(current,rt1[i]);
1513 dirty_reg(current,rt1[i]);
1514}
1515
1516void imm16_alloc(struct regstat *current,int i)
1517{
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 else lt1[i]=rs1[i];
1520 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522 current->is32&=~(1LL<<rt1[i]);
1523 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524 // TODO: Could preserve the 32-bit flag if the immediate is zero
1525 alloc_reg64(current,i,rt1[i]);
1526 alloc_reg64(current,i,rs1[i]);
1527 }
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1530 }
1531 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533 current->is32|=1LL<<rt1[i];
1534 clear_const(current,rs1[i]);
1535 clear_const(current,rt1[i]);
1536 }
1537 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539 if(rs1[i]!=rt1[i]) {
1540 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541 alloc_reg64(current,i,rt1[i]);
1542 current->is32&=~(1LL<<rt1[i]);
1543 }
1544 }
1545 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546 if(is_const(current,rs1[i])) {
1547 int v=get_const(current,rs1[i]);
1548 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1551 }
1552 else clear_const(current,rt1[i]);
1553 }
1554 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555 if(is_const(current,rs1[i])) {
1556 int v=get_const(current,rs1[i]);
1557 set_const(current,rt1[i],v+imm[i]);
1558 }
1559 else clear_const(current,rt1[i]);
1560 current->is32|=1LL<<rt1[i];
1561 }
1562 else {
1563 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564 current->is32|=1LL<<rt1[i];
1565 }
1566 dirty_reg(current,rt1[i]);
1567}
1568
1569void load_alloc(struct regstat *current,int i)
1570{
1571 clear_const(current,rt1[i]);
1572 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1575 if(rt1[i]) {
1576 alloc_reg(current,i,rt1[i]);
1577 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1578 {
1579 current->is32&=~(1LL<<rt1[i]);
1580 alloc_reg64(current,i,rt1[i]);
1581 }
1582 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1583 {
1584 current->is32&=~(1LL<<rt1[i]);
1585 alloc_reg64(current,i,rt1[i]);
1586 alloc_all(current,i);
1587 alloc_reg64(current,i,FTEMP);
1588 }
1589 else current->is32|=1LL<<rt1[i];
1590 dirty_reg(current,rt1[i]);
1591 // If using TLB, need a register for pointer to the mapping table
1592 if(using_tlb) alloc_reg(current,i,TLREG);
1593 // LWL/LWR need a temporary register for the old value
1594 if(opcode[i]==0x22||opcode[i]==0x26)
1595 {
1596 alloc_reg(current,i,FTEMP);
1597 alloc_reg_temp(current,i,-1);
1598 }
1599 }
1600 else
1601 {
1602 // Load to r0 (dummy load)
1603 // but we still need a register to calculate the address
1604 alloc_reg_temp(current,i,-1);
1605 }
1606}
1607
1608void store_alloc(struct regstat *current,int i)
1609{
1610 clear_const(current,rs2[i]);
1611 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613 alloc_reg(current,i,rs2[i]);
1614 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615 alloc_reg64(current,i,rs2[i]);
1616 if(rs2[i]) alloc_reg(current,i,FTEMP);
1617 }
1618 // If using TLB, need a register for pointer to the mapping table
1619 if(using_tlb) alloc_reg(current,i,TLREG);
1620 #if defined(HOST_IMM8)
1621 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622 else alloc_reg(current,i,INVCP);
1623 #endif
1624 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625 alloc_reg(current,i,FTEMP);
1626 }
1627 // We need a temporary register for address generation
1628 alloc_reg_temp(current,i,-1);
1629}
1630
1631void c1ls_alloc(struct regstat *current,int i)
1632{
1633 //clear_const(current,rs1[i]); // FIXME
1634 clear_const(current,rt1[i]);
1635 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636 alloc_reg(current,i,CSREG); // Status
1637 alloc_reg(current,i,FTEMP);
1638 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639 alloc_reg64(current,i,FTEMP);
1640 }
1641 // If using TLB, need a register for pointer to the mapping table
1642 if(using_tlb) alloc_reg(current,i,TLREG);
1643 #if defined(HOST_IMM8)
1644 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646 alloc_reg(current,i,INVCP);
1647 #endif
1648 // We need a temporary register for address generation
1649 alloc_reg_temp(current,i,-1);
1650}
1651
b9b61529 1652void c2ls_alloc(struct regstat *current,int i)
1653{
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,FTEMP);
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662 alloc_reg(current,i,INVCP);
1663 #endif
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
1666}
1667
57871462 1668#ifndef multdiv_alloc
1669void multdiv_alloc(struct regstat *current,int i)
1670{
1671 // case 0x18: MULT
1672 // case 0x19: MULTU
1673 // case 0x1A: DIV
1674 // case 0x1B: DIVU
1675 // case 0x1C: DMULT
1676 // case 0x1D: DMULTU
1677 // case 0x1E: DDIV
1678 // case 0x1F: DDIVU
1679 clear_const(current,rs1[i]);
1680 clear_const(current,rs2[i]);
1681 if(rs1[i]&&rs2[i])
1682 {
1683 if((opcode2[i]&4)==0) // 32-bit
1684 {
1685 current->u&=~(1LL<<HIREG);
1686 current->u&=~(1LL<<LOREG);
1687 alloc_reg(current,i,HIREG);
1688 alloc_reg(current,i,LOREG);
1689 alloc_reg(current,i,rs1[i]);
1690 alloc_reg(current,i,rs2[i]);
1691 current->is32|=1LL<<HIREG;
1692 current->is32|=1LL<<LOREG;
1693 dirty_reg(current,HIREG);
1694 dirty_reg(current,LOREG);
1695 }
1696 else // 64-bit
1697 {
1698 current->u&=~(1LL<<HIREG);
1699 current->u&=~(1LL<<LOREG);
1700 current->uu&=~(1LL<<HIREG);
1701 current->uu&=~(1LL<<LOREG);
1702 alloc_reg64(current,i,HIREG);
1703 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704 alloc_reg64(current,i,rs1[i]);
1705 alloc_reg64(current,i,rs2[i]);
1706 alloc_all(current,i);
1707 current->is32&=~(1LL<<HIREG);
1708 current->is32&=~(1LL<<LOREG);
1709 dirty_reg(current,HIREG);
1710 dirty_reg(current,LOREG);
1711 }
1712 }
1713 else
1714 {
1715 // Multiply by zero is zero.
1716 // MIPS does not have a divide by zero exception.
1717 // The result is undefined, we return zero.
1718 alloc_reg(current,i,HIREG);
1719 alloc_reg(current,i,LOREG);
1720 current->is32|=1LL<<HIREG;
1721 current->is32|=1LL<<LOREG;
1722 dirty_reg(current,HIREG);
1723 dirty_reg(current,LOREG);
1724 }
1725}
1726#endif
1727
1728void cop0_alloc(struct regstat *current,int i)
1729{
1730 if(opcode2[i]==0) // MFC0
1731 {
1732 if(rt1[i]) {
1733 clear_const(current,rt1[i]);
1734 alloc_all(current,i);
1735 alloc_reg(current,i,rt1[i]);
1736 current->is32|=1LL<<rt1[i];
1737 dirty_reg(current,rt1[i]);
1738 }
1739 }
1740 else if(opcode2[i]==4) // MTC0
1741 {
1742 if(rs1[i]){
1743 clear_const(current,rs1[i]);
1744 alloc_reg(current,i,rs1[i]);
1745 alloc_all(current,i);
1746 }
1747 else {
1748 alloc_all(current,i); // FIXME: Keep r0
1749 current->u&=~1LL;
1750 alloc_reg(current,i,0);
1751 }
1752 }
1753 else
1754 {
1755 // TLBR/TLBWI/TLBWR/TLBP/ERET
1756 assert(opcode2[i]==0x10);
1757 alloc_all(current,i);
1758 }
1759}
1760
1761void cop1_alloc(struct regstat *current,int i)
1762{
1763 alloc_reg(current,i,CSREG); // Load status
1764 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1765 {
1766 assert(rt1[i]);
1767 clear_const(current,rt1[i]);
1768 if(opcode2[i]==1) {
1769 alloc_reg64(current,i,rt1[i]); // DMFC1
1770 current->is32&=~(1LL<<rt1[i]);
1771 }else{
1772 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773 current->is32|=1LL<<rt1[i];
1774 }
1775 dirty_reg(current,rt1[i]);
1776 alloc_reg_temp(current,i,-1);
1777 }
1778 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1779 {
1780 if(rs1[i]){
1781 clear_const(current,rs1[i]);
1782 if(opcode2[i]==5)
1783 alloc_reg64(current,i,rs1[i]); // DMTC1
1784 else
1785 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786 alloc_reg_temp(current,i,-1);
1787 }
1788 else {
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 alloc_reg_temp(current,i,-1);
1792 }
1793 }
1794}
1795void fconv_alloc(struct regstat *current,int i)
1796{
1797 alloc_reg(current,i,CSREG); // Load status
1798 alloc_reg_temp(current,i,-1);
1799}
1800void float_alloc(struct regstat *current,int i)
1801{
1802 alloc_reg(current,i,CSREG); // Load status
1803 alloc_reg_temp(current,i,-1);
1804}
b9b61529 1805void c2op_alloc(struct regstat *current,int i)
1806{
1807 alloc_reg_temp(current,i,-1);
1808}
57871462 1809void fcomp_alloc(struct regstat *current,int i)
1810{
1811 alloc_reg(current,i,CSREG); // Load status
1812 alloc_reg(current,i,FSREG); // Load flags
1813 dirty_reg(current,FSREG); // Flag will be modified
1814 alloc_reg_temp(current,i,-1);
1815}
1816
1817void syscall_alloc(struct regstat *current,int i)
1818{
1819 alloc_cc(current,i);
1820 dirty_reg(current,CCREG);
1821 alloc_all(current,i);
1822 current->isconst=0;
1823}
1824
1825void delayslot_alloc(struct regstat *current,int i)
1826{
1827 switch(itype[i]) {
1828 case UJUMP:
1829 case CJUMP:
1830 case SJUMP:
1831 case RJUMP:
1832 case FJUMP:
1833 case SYSCALL:
7139f3c8 1834 case HLECALL:
57871462 1835 case SPAN:
1836 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1837 printf("Disabled speculative precompilation\n");
1838 stop_after_jal=1;
1839 break;
1840 case IMM16:
1841 imm16_alloc(current,i);
1842 break;
1843 case LOAD:
1844 case LOADLR:
1845 load_alloc(current,i);
1846 break;
1847 case STORE:
1848 case STORELR:
1849 store_alloc(current,i);
1850 break;
1851 case ALU:
1852 alu_alloc(current,i);
1853 break;
1854 case SHIFT:
1855 shift_alloc(current,i);
1856 break;
1857 case MULTDIV:
1858 multdiv_alloc(current,i);
1859 break;
1860 case SHIFTIMM:
1861 shiftimm_alloc(current,i);
1862 break;
1863 case MOV:
1864 mov_alloc(current,i);
1865 break;
1866 case COP0:
1867 cop0_alloc(current,i);
1868 break;
1869 case COP1:
b9b61529 1870 case COP2:
57871462 1871 cop1_alloc(current,i);
1872 break;
1873 case C1LS:
1874 c1ls_alloc(current,i);
1875 break;
b9b61529 1876 case C2LS:
1877 c2ls_alloc(current,i);
1878 break;
57871462 1879 case FCONV:
1880 fconv_alloc(current,i);
1881 break;
1882 case FLOAT:
1883 float_alloc(current,i);
1884 break;
1885 case FCOMP:
1886 fcomp_alloc(current,i);
1887 break;
b9b61529 1888 case C2OP:
1889 c2op_alloc(current,i);
1890 break;
57871462 1891 }
1892}
1893
1894// Special case where a branch and delay slot span two pages in virtual memory
1895static void pagespan_alloc(struct regstat *current,int i)
1896{
1897 current->isconst=0;
1898 current->wasconst=0;
1899 regs[i].wasconst=0;
1900 alloc_all(current,i);
1901 alloc_cc(current,i);
1902 dirty_reg(current,CCREG);
1903 if(opcode[i]==3) // JAL
1904 {
1905 alloc_reg(current,i,31);
1906 dirty_reg(current,31);
1907 }
1908 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1909 {
1910 alloc_reg(current,i,rs1[i]);
5067f341 1911 if (rt1[i]!=0) {
1912 alloc_reg(current,i,rt1[i]);
1913 dirty_reg(current,rt1[i]);
57871462 1914 }
1915 }
1916 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1917 {
1918 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1921 {
1922 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1924 }
1925 }
1926 else
1927 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1928 {
1929 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930 if(!((current->is32>>rs1[i])&1))
1931 {
1932 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1933 }
1934 }
1935 else
1936 if(opcode[i]==0x11) // BC1
1937 {
1938 alloc_reg(current,i,FSREG);
1939 alloc_reg(current,i,CSREG);
1940 }
1941 //else ...
1942}
1943
1944add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1945{
1946 stubs[stubcount][0]=type;
1947 stubs[stubcount][1]=addr;
1948 stubs[stubcount][2]=retaddr;
1949 stubs[stubcount][3]=a;
1950 stubs[stubcount][4]=b;
1951 stubs[stubcount][5]=c;
1952 stubs[stubcount][6]=d;
1953 stubs[stubcount][7]=e;
1954 stubcount++;
1955}
1956
1957// Write out a single register
1958void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1959{
1960 int hr;
1961 for(hr=0;hr<HOST_REGS;hr++) {
1962 if(hr!=EXCLUDE_REG) {
1963 if((regmap[hr]&63)==r) {
1964 if((dirty>>hr)&1) {
1965 if(regmap[hr]<64) {
1966 emit_storereg(r,hr);
24385cae 1967#ifndef FORCE32
57871462 1968 if((is32>>regmap[hr])&1) {
1969 emit_sarimm(hr,31,hr);
1970 emit_storereg(r|64,hr);
1971 }
24385cae 1972#endif
57871462 1973 }else{
1974 emit_storereg(r|64,hr);
1975 }
1976 }
1977 }
1978 }
1979 }
1980}
1981
1982int mchecksum()
1983{
1984 //if(!tracedebug) return 0;
1985 int i;
1986 int sum=0;
1987 for(i=0;i<2097152;i++) {
1988 unsigned int temp=sum;
1989 sum<<=1;
1990 sum|=(~temp)>>31;
1991 sum^=((u_int *)rdram)[i];
1992 }
1993 return sum;
1994}
1995int rchecksum()
1996{
1997 int i;
1998 int sum=0;
1999 for(i=0;i<64;i++)
2000 sum^=((u_int *)reg)[i];
2001 return sum;
2002}
57871462 2003void rlist()
2004{
2005 int i;
2006 printf("TRACE: ");
2007 for(i=0;i<32;i++)
2008 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2009 printf("\n");
3d624f89 2010#ifndef DISABLE_COP1
57871462 2011 printf("TRACE: ");
2012 for(i=0;i<32;i++)
2013 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2014 printf("\n");
3d624f89 2015#endif
57871462 2016}
2017
2018void enabletrace()
2019{
2020 tracedebug=1;
2021}
2022
2023void memdebug(int i)
2024{
2025 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2027 //rlist();
2028 //if(tracedebug) {
2029 //if(Count>=-2084597794) {
2030 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2031 //if(0) {
2032 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2035 rlist();
2036 #ifdef __i386__
2037 printf("TRACE: %x\n",(&i)[-1]);
2038 #endif
2039 #ifdef __arm__
2040 int j;
2041 printf("TRACE: %x \n",(&j)[10]);
2042 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2043 #endif
2044 //fflush(stdout);
2045 }
2046 //printf("TRACE: %x\n",(&i)[-1]);
2047}
2048
2049void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2050{
2051 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2052}
2053
2054void alu_assemble(int i,struct regstat *i_regs)
2055{
2056 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2057 if(rt1[i]) {
2058 signed char s1,s2,t;
2059 t=get_reg(i_regs->regmap,rt1[i]);
2060 if(t>=0) {
2061 s1=get_reg(i_regs->regmap,rs1[i]);
2062 s2=get_reg(i_regs->regmap,rs2[i]);
2063 if(rs1[i]&&rs2[i]) {
2064 assert(s1>=0);
2065 assert(s2>=0);
2066 if(opcode2[i]&2) emit_sub(s1,s2,t);
2067 else emit_add(s1,s2,t);
2068 }
2069 else if(rs1[i]) {
2070 if(s1>=0) emit_mov(s1,t);
2071 else emit_loadreg(rs1[i],t);
2072 }
2073 else if(rs2[i]) {
2074 if(s2>=0) {
2075 if(opcode2[i]&2) emit_neg(s2,t);
2076 else emit_mov(s2,t);
2077 }
2078 else {
2079 emit_loadreg(rs2[i],t);
2080 if(opcode2[i]&2) emit_neg(t,t);
2081 }
2082 }
2083 else emit_zeroreg(t);
2084 }
2085 }
2086 }
2087 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2088 if(rt1[i]) {
2089 signed char s1l,s2l,s1h,s2h,tl,th;
2090 tl=get_reg(i_regs->regmap,rt1[i]);
2091 th=get_reg(i_regs->regmap,rt1[i]|64);
2092 if(tl>=0) {
2093 s1l=get_reg(i_regs->regmap,rs1[i]);
2094 s2l=get_reg(i_regs->regmap,rs2[i]);
2095 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097 if(rs1[i]&&rs2[i]) {
2098 assert(s1l>=0);
2099 assert(s2l>=0);
2100 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101 else emit_adds(s1l,s2l,tl);
2102 if(th>=0) {
2103 #ifdef INVERTED_CARRY
2104 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2105 #else
2106 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2107 #endif
2108 else emit_add(s1h,s2h,th);
2109 }
2110 }
2111 else if(rs1[i]) {
2112 if(s1l>=0) emit_mov(s1l,tl);
2113 else emit_loadreg(rs1[i],tl);
2114 if(th>=0) {
2115 if(s1h>=0) emit_mov(s1h,th);
2116 else emit_loadreg(rs1[i]|64,th);
2117 }
2118 }
2119 else if(rs2[i]) {
2120 if(s2l>=0) {
2121 if(opcode2[i]&2) emit_negs(s2l,tl);
2122 else emit_mov(s2l,tl);
2123 }
2124 else {
2125 emit_loadreg(rs2[i],tl);
2126 if(opcode2[i]&2) emit_negs(tl,tl);
2127 }
2128 if(th>=0) {
2129 #ifdef INVERTED_CARRY
2130 if(s2h>=0) emit_mov(s2h,th);
2131 else emit_loadreg(rs2[i]|64,th);
2132 if(opcode2[i]&2) {
2133 emit_adcimm(-1,th); // x86 has inverted carry flag
2134 emit_not(th,th);
2135 }
2136 #else
2137 if(opcode2[i]&2) {
2138 if(s2h>=0) emit_rscimm(s2h,0,th);
2139 else {
2140 emit_loadreg(rs2[i]|64,th);
2141 emit_rscimm(th,0,th);
2142 }
2143 }else{
2144 if(s2h>=0) emit_mov(s2h,th);
2145 else emit_loadreg(rs2[i]|64,th);
2146 }
2147 #endif
2148 }
2149 }
2150 else {
2151 emit_zeroreg(tl);
2152 if(th>=0) emit_zeroreg(th);
2153 }
2154 }
2155 }
2156 }
2157 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2158 if(rt1[i]) {
2159 signed char s1l,s1h,s2l,s2h,t;
2160 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2161 {
2162 t=get_reg(i_regs->regmap,rt1[i]);
2163 //assert(t>=0);
2164 if(t>=0) {
2165 s1l=get_reg(i_regs->regmap,rs1[i]);
2166 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167 s2l=get_reg(i_regs->regmap,rs2[i]);
2168 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169 if(rs2[i]==0) // rx<r0
2170 {
2171 assert(s1h>=0);
2172 if(opcode2[i]==0x2a) // SLT
2173 emit_shrimm(s1h,31,t);
2174 else // SLTU (unsigned can not be less than zero)
2175 emit_zeroreg(t);
2176 }
2177 else if(rs1[i]==0) // r0<rx
2178 {
2179 assert(s2h>=0);
2180 if(opcode2[i]==0x2a) // SLT
2181 emit_set_gz64_32(s2h,s2l,t);
2182 else // SLTU (set if not zero)
2183 emit_set_nz64_32(s2h,s2l,t);
2184 }
2185 else {
2186 assert(s1l>=0);assert(s1h>=0);
2187 assert(s2l>=0);assert(s2h>=0);
2188 if(opcode2[i]==0x2a) // SLT
2189 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2190 else // SLTU
2191 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2192 }
2193 }
2194 } else {
2195 t=get_reg(i_regs->regmap,rt1[i]);
2196 //assert(t>=0);
2197 if(t>=0) {
2198 s1l=get_reg(i_regs->regmap,rs1[i]);
2199 s2l=get_reg(i_regs->regmap,rs2[i]);
2200 if(rs2[i]==0) // rx<r0
2201 {
2202 assert(s1l>=0);
2203 if(opcode2[i]==0x2a) // SLT
2204 emit_shrimm(s1l,31,t);
2205 else // SLTU (unsigned can not be less than zero)
2206 emit_zeroreg(t);
2207 }
2208 else if(rs1[i]==0) // r0<rx
2209 {
2210 assert(s2l>=0);
2211 if(opcode2[i]==0x2a) // SLT
2212 emit_set_gz32(s2l,t);
2213 else // SLTU (set if not zero)
2214 emit_set_nz32(s2l,t);
2215 }
2216 else{
2217 assert(s1l>=0);assert(s2l>=0);
2218 if(opcode2[i]==0x2a) // SLT
2219 emit_set_if_less32(s1l,s2l,t);
2220 else // SLTU
2221 emit_set_if_carry32(s1l,s2l,t);
2222 }
2223 }
2224 }
2225 }
2226 }
2227 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2228 if(rt1[i]) {
2229 signed char s1l,s1h,s2l,s2h,th,tl;
2230 tl=get_reg(i_regs->regmap,rt1[i]);
2231 th=get_reg(i_regs->regmap,rt1[i]|64);
2232 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2233 {
2234 assert(tl>=0);
2235 if(tl>=0) {
2236 s1l=get_reg(i_regs->regmap,rs1[i]);
2237 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238 s2l=get_reg(i_regs->regmap,rs2[i]);
2239 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240 if(rs1[i]&&rs2[i]) {
2241 assert(s1l>=0);assert(s1h>=0);
2242 assert(s2l>=0);assert(s2h>=0);
2243 if(opcode2[i]==0x24) { // AND
2244 emit_and(s1l,s2l,tl);
2245 emit_and(s1h,s2h,th);
2246 } else
2247 if(opcode2[i]==0x25) { // OR
2248 emit_or(s1l,s2l,tl);
2249 emit_or(s1h,s2h,th);
2250 } else
2251 if(opcode2[i]==0x26) { // XOR
2252 emit_xor(s1l,s2l,tl);
2253 emit_xor(s1h,s2h,th);
2254 } else
2255 if(opcode2[i]==0x27) { // NOR
2256 emit_or(s1l,s2l,tl);
2257 emit_or(s1h,s2h,th);
2258 emit_not(tl,tl);
2259 emit_not(th,th);
2260 }
2261 }
2262 else
2263 {
2264 if(opcode2[i]==0x24) { // AND
2265 emit_zeroreg(tl);
2266 emit_zeroreg(th);
2267 } else
2268 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2269 if(rs1[i]){
2270 if(s1l>=0) emit_mov(s1l,tl);
2271 else emit_loadreg(rs1[i],tl);
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2274 }
2275 else
2276 if(rs2[i]){
2277 if(s2l>=0) emit_mov(s2l,tl);
2278 else emit_loadreg(rs2[i],tl);
2279 if(s2h>=0) emit_mov(s2h,th);
2280 else emit_loadreg(rs2[i]|64,th);
2281 }
2282 else{
2283 emit_zeroreg(tl);
2284 emit_zeroreg(th);
2285 }
2286 } else
2287 if(opcode2[i]==0x27) { // NOR
2288 if(rs1[i]){
2289 if(s1l>=0) emit_not(s1l,tl);
2290 else{
2291 emit_loadreg(rs1[i],tl);
2292 emit_not(tl,tl);
2293 }
2294 if(s1h>=0) emit_not(s1h,th);
2295 else{
2296 emit_loadreg(rs1[i]|64,th);
2297 emit_not(th,th);
2298 }
2299 }
2300 else
2301 if(rs2[i]){
2302 if(s2l>=0) emit_not(s2l,tl);
2303 else{
2304 emit_loadreg(rs2[i],tl);
2305 emit_not(tl,tl);
2306 }
2307 if(s2h>=0) emit_not(s2h,th);
2308 else{
2309 emit_loadreg(rs2[i]|64,th);
2310 emit_not(th,th);
2311 }
2312 }
2313 else {
2314 emit_movimm(-1,tl);
2315 emit_movimm(-1,th);
2316 }
2317 }
2318 }
2319 }
2320 }
2321 else
2322 {
2323 // 32 bit
2324 if(tl>=0) {
2325 s1l=get_reg(i_regs->regmap,rs1[i]);
2326 s2l=get_reg(i_regs->regmap,rs2[i]);
2327 if(rs1[i]&&rs2[i]) {
2328 assert(s1l>=0);
2329 assert(s2l>=0);
2330 if(opcode2[i]==0x24) { // AND
2331 emit_and(s1l,s2l,tl);
2332 } else
2333 if(opcode2[i]==0x25) { // OR
2334 emit_or(s1l,s2l,tl);
2335 } else
2336 if(opcode2[i]==0x26) { // XOR
2337 emit_xor(s1l,s2l,tl);
2338 } else
2339 if(opcode2[i]==0x27) { // NOR
2340 emit_or(s1l,s2l,tl);
2341 emit_not(tl,tl);
2342 }
2343 }
2344 else
2345 {
2346 if(opcode2[i]==0x24) { // AND
2347 emit_zeroreg(tl);
2348 } else
2349 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2350 if(rs1[i]){
2351 if(s1l>=0) emit_mov(s1l,tl);
2352 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2353 }
2354 else
2355 if(rs2[i]){
2356 if(s2l>=0) emit_mov(s2l,tl);
2357 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2358 }
2359 else emit_zeroreg(tl);
2360 } else
2361 if(opcode2[i]==0x27) { // NOR
2362 if(rs1[i]){
2363 if(s1l>=0) emit_not(s1l,tl);
2364 else {
2365 emit_loadreg(rs1[i],tl);
2366 emit_not(tl,tl);
2367 }
2368 }
2369 else
2370 if(rs2[i]){
2371 if(s2l>=0) emit_not(s2l,tl);
2372 else {
2373 emit_loadreg(rs2[i],tl);
2374 emit_not(tl,tl);
2375 }
2376 }
2377 else emit_movimm(-1,tl);
2378 }
2379 }
2380 }
2381 }
2382 }
2383 }
2384}
2385
2386void imm16_assemble(int i,struct regstat *i_regs)
2387{
2388 if (opcode[i]==0x0f) { // LUI
2389 if(rt1[i]) {
2390 signed char t;
2391 t=get_reg(i_regs->regmap,rt1[i]);
2392 //assert(t>=0);
2393 if(t>=0) {
2394 if(!((i_regs->isconst>>t)&1))
2395 emit_movimm(imm[i]<<16,t);
2396 }
2397 }
2398 }
2399 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2400 if(rt1[i]) {
2401 signed char s,t;
2402 t=get_reg(i_regs->regmap,rt1[i]);
2403 s=get_reg(i_regs->regmap,rs1[i]);
2404 if(rs1[i]) {
2405 //assert(t>=0);
2406 //assert(s>=0);
2407 if(t>=0) {
2408 if(!((i_regs->isconst>>t)&1)) {
2409 if(s<0) {
2410 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411 emit_addimm(t,imm[i],t);
2412 }else{
2413 if(!((i_regs->wasconst>>s)&1))
2414 emit_addimm(s,imm[i],t);
2415 else
2416 emit_movimm(constmap[i][s]+imm[i],t);
2417 }
2418 }
2419 }
2420 } else {
2421 if(t>=0) {
2422 if(!((i_regs->isconst>>t)&1))
2423 emit_movimm(imm[i],t);
2424 }
2425 }
2426 }
2427 }
2428 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2429 if(rt1[i]) {
2430 signed char sh,sl,th,tl;
2431 th=get_reg(i_regs->regmap,rt1[i]|64);
2432 tl=get_reg(i_regs->regmap,rt1[i]);
2433 sh=get_reg(i_regs->regmap,rs1[i]|64);
2434 sl=get_reg(i_regs->regmap,rs1[i]);
2435 if(tl>=0) {
2436 if(rs1[i]) {
2437 assert(sh>=0);
2438 assert(sl>=0);
2439 if(th>=0) {
2440 emit_addimm64_32(sh,sl,imm[i],th,tl);
2441 }
2442 else {
2443 emit_addimm(sl,imm[i],tl);
2444 }
2445 } else {
2446 emit_movimm(imm[i],tl);
2447 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2448 }
2449 }
2450 }
2451 }
2452 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2453 if(rt1[i]) {
2454 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455 signed char sh,sl,t;
2456 t=get_reg(i_regs->regmap,rt1[i]);
2457 sh=get_reg(i_regs->regmap,rs1[i]|64);
2458 sl=get_reg(i_regs->regmap,rs1[i]);
2459 //assert(t>=0);
2460 if(t>=0) {
2461 if(rs1[i]>0) {
2462 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464 if(opcode[i]==0x0a) { // SLTI
2465 if(sl<0) {
2466 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467 emit_slti32(t,imm[i],t);
2468 }else{
2469 emit_slti32(sl,imm[i],t);
2470 }
2471 }
2472 else { // SLTIU
2473 if(sl<0) {
2474 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475 emit_sltiu32(t,imm[i],t);
2476 }else{
2477 emit_sltiu32(sl,imm[i],t);
2478 }
2479 }
2480 }else{ // 64-bit
2481 assert(sl>=0);
2482 if(opcode[i]==0x0a) // SLTI
2483 emit_slti64_32(sh,sl,imm[i],t);
2484 else // SLTIU
2485 emit_sltiu64_32(sh,sl,imm[i],t);
2486 }
2487 }else{
2488 // SLTI(U) with r0 is just stupid,
2489 // nonetheless examples can be found
2490 if(opcode[i]==0x0a) // SLTI
2491 if(0<imm[i]) emit_movimm(1,t);
2492 else emit_zeroreg(t);
2493 else // SLTIU
2494 {
2495 if(imm[i]) emit_movimm(1,t);
2496 else emit_zeroreg(t);
2497 }
2498 }
2499 }
2500 }
2501 }
2502 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2503 if(rt1[i]) {
2504 signed char sh,sl,th,tl;
2505 th=get_reg(i_regs->regmap,rt1[i]|64);
2506 tl=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510 if(opcode[i]==0x0c) //ANDI
2511 {
2512 if(rs1[i]) {
2513 if(sl<0) {
2514 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515 emit_andimm(tl,imm[i],tl);
2516 }else{
2517 if(!((i_regs->wasconst>>sl)&1))
2518 emit_andimm(sl,imm[i],tl);
2519 else
2520 emit_movimm(constmap[i][sl]&imm[i],tl);
2521 }
2522 }
2523 else
2524 emit_zeroreg(tl);
2525 if(th>=0) emit_zeroreg(th);
2526 }
2527 else
2528 {
2529 if(rs1[i]) {
2530 if(sl<0) {
2531 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2532 }
2533 if(th>=0) {
2534 if(sh<0) {
2535 emit_loadreg(rs1[i]|64,th);
2536 }else{
2537 emit_mov(sh,th);
2538 }
2539 }
2540 if(opcode[i]==0x0d) //ORI
2541 if(sl<0) {
2542 emit_orimm(tl,imm[i],tl);
2543 }else{
2544 if(!((i_regs->wasconst>>sl)&1))
2545 emit_orimm(sl,imm[i],tl);
2546 else
2547 emit_movimm(constmap[i][sl]|imm[i],tl);
2548 }
2549 if(opcode[i]==0x0e) //XORI
2550 if(sl<0) {
2551 emit_xorimm(tl,imm[i],tl);
2552 }else{
2553 if(!((i_regs->wasconst>>sl)&1))
2554 emit_xorimm(sl,imm[i],tl);
2555 else
2556 emit_movimm(constmap[i][sl]^imm[i],tl);
2557 }
2558 }
2559 else {
2560 emit_movimm(imm[i],tl);
2561 if(th>=0) emit_zeroreg(th);
2562 }
2563 }
2564 }
2565 }
2566 }
2567}
2568
2569void shiftimm_assemble(int i,struct regstat *i_regs)
2570{
2571 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2572 {
2573 if(rt1[i]) {
2574 signed char s,t;
2575 t=get_reg(i_regs->regmap,rt1[i]);
2576 s=get_reg(i_regs->regmap,rs1[i]);
2577 //assert(t>=0);
2578 if(t>=0){
2579 if(rs1[i]==0)
2580 {
2581 emit_zeroreg(t);
2582 }
2583 else
2584 {
2585 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2586 if(imm[i]) {
2587 if(opcode2[i]==0) // SLL
2588 {
2589 emit_shlimm(s<0?t:s,imm[i],t);
2590 }
2591 if(opcode2[i]==2) // SRL
2592 {
2593 emit_shrimm(s<0?t:s,imm[i],t);
2594 }
2595 if(opcode2[i]==3) // SRA
2596 {
2597 emit_sarimm(s<0?t:s,imm[i],t);
2598 }
2599 }else{
2600 // Shift by zero
2601 if(s>=0 && s!=t) emit_mov(s,t);
2602 }
2603 }
2604 }
2605 //emit_storereg(rt1[i],t); //DEBUG
2606 }
2607 }
2608 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2609 {
2610 if(rt1[i]) {
2611 signed char sh,sl,th,tl;
2612 th=get_reg(i_regs->regmap,rt1[i]|64);
2613 tl=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2616 if(tl>=0) {
2617 if(rs1[i]==0)
2618 {
2619 emit_zeroreg(tl);
2620 if(th>=0) emit_zeroreg(th);
2621 }
2622 else
2623 {
2624 assert(sl>=0);
2625 assert(sh>=0);
2626 if(imm[i]) {
2627 if(opcode2[i]==0x38) // DSLL
2628 {
2629 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630 emit_shlimm(sl,imm[i],tl);
2631 }
2632 if(opcode2[i]==0x3a) // DSRL
2633 {
2634 emit_shrdimm(sl,sh,imm[i],tl);
2635 if(th>=0) emit_shrimm(sh,imm[i],th);
2636 }
2637 if(opcode2[i]==0x3b) // DSRA
2638 {
2639 emit_shrdimm(sl,sh,imm[i],tl);
2640 if(th>=0) emit_sarimm(sh,imm[i],th);
2641 }
2642 }else{
2643 // Shift by zero
2644 if(sl!=tl) emit_mov(sl,tl);
2645 if(th>=0&&sh!=th) emit_mov(sh,th);
2646 }
2647 }
2648 }
2649 }
2650 }
2651 if(opcode2[i]==0x3c) // DSLL32
2652 {
2653 if(rt1[i]) {
2654 signed char sl,tl,th;
2655 tl=get_reg(i_regs->regmap,rt1[i]);
2656 th=get_reg(i_regs->regmap,rt1[i]|64);
2657 sl=get_reg(i_regs->regmap,rs1[i]);
2658 if(th>=0||tl>=0){
2659 assert(tl>=0);
2660 assert(th>=0);
2661 assert(sl>=0);
2662 emit_mov(sl,th);
2663 emit_zeroreg(tl);
2664 if(imm[i]>32)
2665 {
2666 emit_shlimm(th,imm[i]&31,th);
2667 }
2668 }
2669 }
2670 }
2671 if(opcode2[i]==0x3e) // DSRL32
2672 {
2673 if(rt1[i]) {
2674 signed char sh,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sh=get_reg(i_regs->regmap,rs1[i]|64);
2678 if(tl>=0){
2679 assert(sh>=0);
2680 emit_mov(sh,tl);
2681 if(th>=0) emit_zeroreg(th);
2682 if(imm[i]>32)
2683 {
2684 emit_shrimm(tl,imm[i]&31,tl);
2685 }
2686 }
2687 }
2688 }
2689 if(opcode2[i]==0x3f) // DSRA32
2690 {
2691 if(rt1[i]) {
2692 signed char sh,tl;
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 sh=get_reg(i_regs->regmap,rs1[i]|64);
2695 if(tl>=0){
2696 assert(sh>=0);
2697 emit_mov(sh,tl);
2698 if(imm[i]>32)
2699 {
2700 emit_sarimm(tl,imm[i]&31,tl);
2701 }
2702 }
2703 }
2704 }
2705}
2706
2707#ifndef shift_assemble
2708void shift_assemble(int i,struct regstat *i_regs)
2709{
2710 printf("Need shift_assemble for this architecture.\n");
2711 exit(1);
2712}
2713#endif
2714
2715void load_assemble(int i,struct regstat *i_regs)
2716{
2717 int s,th,tl,addr,map=-1;
2718 int offset;
2719 int jaddr=0;
2720 int memtarget,c=0;
2721 u_int hr,reglist=0;
2722 th=get_reg(i_regs->regmap,rt1[i]|64);
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 s=get_reg(i_regs->regmap,rs1[i]);
2725 offset=imm[i];
2726 for(hr=0;hr<HOST_REGS;hr++) {
2727 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2728 }
2729 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2730 if(s>=0) {
2731 c=(i_regs->wasconst>>s)&1;
2732 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2734 }
2735 if(offset||s<0||c) addr=tl;
2736 else addr=s;
2737 //printf("load_assemble: c=%d\n",c);
2738 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2739 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2740 if(tl>=0) {
2741 //assert(tl>=0);
2742 //assert(rt1[i]);
2743 reglist&=~(1<<tl);
2744 if(th>=0) reglist&=~(1<<th);
2745 if(!using_tlb) {
2746 if(!c) {
2747//#define R29_HACK 1
2748 #ifdef R29_HACK
2749 // Strmnnrmn's speed hack
2750 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2751 #endif
2752 {
2753 emit_cmpimm(addr,0x800000);
2754 jaddr=(int)out;
2755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2756 // Hint to branch predictor that the branch is unlikely to be taken
2757 if(rs1[i]>=28)
2758 emit_jno_unlikely(0);
2759 else
2760 #endif
2761 emit_jno(0);
2762 }
2763 }
2764 }else{ // using tlb
2765 int x=0;
2766 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2767 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2768 map=get_reg(i_regs->regmap,TLREG);
2769 assert(map>=0);
2770 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2771 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2772 }
2773 if (opcode[i]==0x20) { // LB
2774 if(!c||memtarget) {
2775 #ifdef HOST_IMM_ADDR32
2776 if(c)
2777 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2778 else
2779 #endif
2780 {
2781 //emit_xorimm(addr,3,tl);
2782 //gen_tlb_addr_r(tl,map);
2783 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2784 int x=0;
2002a1db 2785#ifdef BIG_ENDIAN_MIPS
57871462 2786 if(!c) emit_xorimm(addr,3,tl);
2787 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2788#else
2789 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2790 else if (tl!=addr) emit_mov(addr,tl);
2791#endif
57871462 2792 emit_movsbl_indexed_tlb(x,tl,map,tl);
2793 }
2794 if(jaddr)
2795 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2796 }
2797 else
2798 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2799 }
2800 if (opcode[i]==0x21) { // LH
2801 if(!c||memtarget) {
2802 #ifdef HOST_IMM_ADDR32
2803 if(c)
2804 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2805 else
2806 #endif
2807 {
2808 int x=0;
2002a1db 2809#ifdef BIG_ENDIAN_MIPS
57871462 2810 if(!c) emit_xorimm(addr,2,tl);
2811 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2812#else
2813 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2814 else if (tl!=addr) emit_mov(addr,tl);
2815#endif
57871462 2816 //#ifdef
2817 //emit_movswl_indexed_tlb(x,tl,map,tl);
2818 //else
2819 if(map>=0) {
2820 gen_tlb_addr_r(tl,map);
2821 emit_movswl_indexed(x,tl,tl);
2822 }else
2823 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2824 }
2825 if(jaddr)
2826 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2827 }
2828 else
2829 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830 }
2831 if (opcode[i]==0x23) { // LW
2832 if(!c||memtarget) {
2833 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2834 #ifdef HOST_IMM_ADDR32
2835 if(c)
2836 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2837 else
2838 #endif
2839 emit_readword_indexed_tlb(0,addr,map,tl);
2840 if(jaddr)
2841 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2842 }
2843 else
2844 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845 }
2846 if (opcode[i]==0x24) { // LBU
2847 if(!c||memtarget) {
2848 #ifdef HOST_IMM_ADDR32
2849 if(c)
2850 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2851 else
2852 #endif
2853 {
2854 //emit_xorimm(addr,3,tl);
2855 //gen_tlb_addr_r(tl,map);
2856 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2857 int x=0;
2002a1db 2858#ifdef BIG_ENDIAN_MIPS
57871462 2859 if(!c) emit_xorimm(addr,3,tl);
2860 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2861#else
2862 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2863 else if (tl!=addr) emit_mov(addr,tl);
2864#endif
57871462 2865 emit_movzbl_indexed_tlb(x,tl,map,tl);
2866 }
2867 if(jaddr)
2868 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2869 }
2870 else
2871 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2872 }
2873 if (opcode[i]==0x25) { // LHU
2874 if(!c||memtarget) {
2875 #ifdef HOST_IMM_ADDR32
2876 if(c)
2877 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2878 else
2879 #endif
2880 {
2881 int x=0;
2002a1db 2882#ifdef BIG_ENDIAN_MIPS
57871462 2883 if(!c) emit_xorimm(addr,2,tl);
2884 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2885#else
2886 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2887 else if (tl!=addr) emit_mov(addr,tl);
2888#endif
57871462 2889 //#ifdef
2890 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2891 //#else
2892 if(map>=0) {
2893 gen_tlb_addr_r(tl,map);
2894 emit_movzwl_indexed(x,tl,tl);
2895 }else
2896 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2897 if(jaddr)
2898 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899 }
2900 }
2901 else
2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903 }
2904 if (opcode[i]==0x27) { // LWU
2905 assert(th>=0);
2906 if(!c||memtarget) {
2907 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908 #ifdef HOST_IMM_ADDR32
2909 if(c)
2910 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911 else
2912 #endif
2913 emit_readword_indexed_tlb(0,addr,map,tl);
2914 if(jaddr)
2915 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2916 }
2917 else {
2918 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919 }
2920 emit_zeroreg(th);
2921 }
2922 if (opcode[i]==0x37) { // LD
2923 if(!c||memtarget) {
2924 //gen_tlb_addr_r(tl,map);
2925 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2926 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2927 #ifdef HOST_IMM_ADDR32
2928 if(c)
2929 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2930 else
2931 #endif
2932 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2933 if(jaddr)
2934 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2935 }
2936 else
2937 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938 }
2939 //emit_storereg(rt1[i],tl); // DEBUG
2940 }
2941 //if(opcode[i]==0x23)
2942 //if(opcode[i]==0x24)
2943 //if(opcode[i]==0x23||opcode[i]==0x24)
2944 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2945 {
2946 //emit_pusha();
2947 save_regs(0x100f);
2948 emit_readword((int)&last_count,ECX);
2949 #ifdef __i386__
2950 if(get_reg(i_regs->regmap,CCREG)<0)
2951 emit_loadreg(CCREG,HOST_CCREG);
2952 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2953 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2954 emit_writeword(HOST_CCREG,(int)&Count);
2955 #endif
2956 #ifdef __arm__
2957 if(get_reg(i_regs->regmap,CCREG)<0)
2958 emit_loadreg(CCREG,0);
2959 else
2960 emit_mov(HOST_CCREG,0);
2961 emit_add(0,ECX,0);
2962 emit_addimm(0,2*ccadj[i],0);
2963 emit_writeword(0,(int)&Count);
2964 #endif
2965 emit_call((int)memdebug);
2966 //emit_popa();
2967 restore_regs(0x100f);
2968 }/**/
2969}
2970
2971#ifndef loadlr_assemble
2972void loadlr_assemble(int i,struct regstat *i_regs)
2973{
2974 printf("Need loadlr_assemble for this architecture.\n");
2975 exit(1);
2976}
2977#endif
2978
2979void store_assemble(int i,struct regstat *i_regs)
2980{
2981 int s,th,tl,map=-1;
2982 int addr,temp;
2983 int offset;
2984 int jaddr=0,jaddr2,type;
666a299d 2985 int memtarget=0,c=0;
57871462 2986 int agr=AGEN1+(i&1);
2987 u_int hr,reglist=0;
2988 th=get_reg(i_regs->regmap,rs2[i]|64);
2989 tl=get_reg(i_regs->regmap,rs2[i]);
2990 s=get_reg(i_regs->regmap,rs1[i]);
2991 temp=get_reg(i_regs->regmap,agr);
2992 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2993 offset=imm[i];
2994 if(s>=0) {
2995 c=(i_regs->wasconst>>s)&1;
2996 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2997 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2998 }
2999 assert(tl>=0);
3000 assert(temp>=0);
3001 for(hr=0;hr<HOST_REGS;hr++) {
3002 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3003 }
3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(offset||s<0||c) addr=temp;
3006 else addr=s;
3007 if(!using_tlb) {
3008 if(!c) {
3009 #ifdef R29_HACK
3010 // Strmnnrmn's speed hack
3011 memtarget=1;
3012 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3013 #endif
3014 emit_cmpimm(addr,0x800000);
3015 #ifdef DESTRUCTIVE_SHIFT
3016 if(s==addr) emit_mov(s,temp);
3017 #endif
3018 #ifdef R29_HACK
3019 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3020 #endif
3021 {
3022 jaddr=(int)out;
3023 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3024 // Hint to branch predictor that the branch is unlikely to be taken
3025 if(rs1[i]>=28)
3026 emit_jno_unlikely(0);
3027 else
3028 #endif
3029 emit_jno(0);
3030 }
3031 }
3032 }else{ // using tlb
3033 int x=0;
3034 if (opcode[i]==0x28) x=3; // SB
3035 if (opcode[i]==0x29) x=2; // SH
3036 map=get_reg(i_regs->regmap,TLREG);
3037 assert(map>=0);
3038 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3039 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3040 }
3041
3042 if (opcode[i]==0x28) { // SB
3043 if(!c||memtarget) {
3044 int x=0;
2002a1db 3045#ifdef BIG_ENDIAN_MIPS
57871462 3046 if(!c) emit_xorimm(addr,3,temp);
3047 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3048#else
3049 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3050 else if (addr!=temp) emit_mov(addr,temp);
3051#endif
57871462 3052 //gen_tlb_addr_w(temp,map);
3053 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3054 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3055 }
3056 type=STOREB_STUB;
3057 }
3058 if (opcode[i]==0x29) { // SH
3059 if(!c||memtarget) {
3060 int x=0;
2002a1db 3061#ifdef BIG_ENDIAN_MIPS
57871462 3062 if(!c) emit_xorimm(addr,2,temp);
3063 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3064#else
3065 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3066 else if (addr!=temp) emit_mov(addr,temp);
3067#endif
57871462 3068 //#ifdef
3069 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3070 //#else
3071 if(map>=0) {
3072 gen_tlb_addr_w(temp,map);
3073 emit_writehword_indexed(tl,x,temp);
3074 }else
3075 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3076 }
3077 type=STOREH_STUB;
3078 }
3079 if (opcode[i]==0x2B) { // SW
3080 if(!c||memtarget)
3081 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3082 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3083 type=STOREW_STUB;
3084 }
3085 if (opcode[i]==0x3F) { // SD
3086 if(!c||memtarget) {
3087 if(rs2[i]) {
3088 assert(th>=0);
3089 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3090 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3091 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3092 }else{
3093 // Store zero
3094 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3095 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3096 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3097 }
3098 }
3099 type=STORED_STUB;
3100 }
666a299d 3101 if(!using_tlb&&(!c||memtarget))
3102 // addr could be a temp, make sure it survives STORE*_STUB
3103 reglist|=1<<addr;
57871462 3104 if(jaddr) {
3105 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 } else if(!memtarget) {
3107 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3108 }
3109 if(!using_tlb) {
3110 if(!c||memtarget) {
3111 #ifdef DESTRUCTIVE_SHIFT
3112 // The x86 shift operation is 'destructive'; it overwrites the
3113 // source register, so we need to make a copy first and use that.
3114 addr=temp;
3115 #endif
3116 #if defined(HOST_IMM8)
3117 int ir=get_reg(i_regs->regmap,INVCP);
3118 assert(ir>=0);
3119 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3120 #else
3121 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3122 #endif
3123 jaddr2=(int)out;
3124 emit_jne(0);
3125 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3126 }
3127 }
3128 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3129 //if(opcode[i]==0x2B || opcode[i]==0x28)
3130 //if(opcode[i]==0x2B || opcode[i]==0x29)
3131 //if(opcode[i]==0x2B)
3132 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3133 {
3134 //emit_pusha();
3135 save_regs(0x100f);
3136 emit_readword((int)&last_count,ECX);
3137 #ifdef __i386__
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,HOST_CCREG);
3140 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3141 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3142 emit_writeword(HOST_CCREG,(int)&Count);
3143 #endif
3144 #ifdef __arm__
3145 if(get_reg(i_regs->regmap,CCREG)<0)
3146 emit_loadreg(CCREG,0);
3147 else
3148 emit_mov(HOST_CCREG,0);
3149 emit_add(0,ECX,0);
3150 emit_addimm(0,2*ccadj[i],0);
3151 emit_writeword(0,(int)&Count);
3152 #endif
3153 emit_call((int)memdebug);
3154 //emit_popa();
3155 restore_regs(0x100f);
3156 }/**/
3157}
3158
3159void storelr_assemble(int i,struct regstat *i_regs)
3160{
3161 int s,th,tl;
3162 int temp;
3163 int temp2;
3164 int offset;
3165 int jaddr=0,jaddr2;
3166 int case1,case2,case3;
3167 int done0,done1,done2;
3168 int memtarget,c=0;
3169 u_int hr,reglist=0;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,-1);
3174 offset=imm[i];
3175 if(s>=0) {
3176 c=(i_regs->isconst>>s)&1;
3177 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3178 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3179 }
3180 assert(tl>=0);
3181 for(hr=0;hr<HOST_REGS;hr++) {
3182 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3183 }
3184 if(tl>=0) {
3185 assert(temp>=0);
3186 if(!using_tlb) {
3187 if(!c) {
3188 emit_cmpimm(s<0||offset?temp:s,0x800000);
3189 if(!offset&&s!=temp) emit_mov(s,temp);
3190 jaddr=(int)out;
3191 emit_jno(0);
3192 }
3193 else
3194 {
3195 if(!memtarget||!rs1[i]) {
3196 jaddr=(int)out;
3197 emit_jmp(0);
3198 }
3199 }
3200 if((u_int)rdram!=0x80000000)
3201 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3202 }else{ // using tlb
3203 int map=get_reg(i_regs->regmap,TLREG);
3204 assert(map>=0);
3205 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3206 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3207 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3208 if(!jaddr&&!memtarget) {
3209 jaddr=(int)out;
3210 emit_jmp(0);
3211 }
3212 gen_tlb_addr_w(temp,map);
3213 }
3214
3215 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3216 temp2=get_reg(i_regs->regmap,FTEMP);
3217 if(!rs2[i]) temp2=th=tl;
3218 }
3219
2002a1db 3220#ifndef BIG_ENDIAN_MIPS
3221 emit_xorimm(temp,3,temp);
3222#endif
57871462 3223 emit_testimm(temp,2);
3224 case2=(int)out;
3225 emit_jne(0);
3226 emit_testimm(temp,1);
3227 case1=(int)out;
3228 emit_jne(0);
3229 // 0
3230 if (opcode[i]==0x2A) { // SWL
3231 emit_writeword_indexed(tl,0,temp);
3232 }
3233 if (opcode[i]==0x2E) { // SWR
3234 emit_writebyte_indexed(tl,3,temp);
3235 }
3236 if (opcode[i]==0x2C) { // SDL
3237 emit_writeword_indexed(th,0,temp);
3238 if(rs2[i]) emit_mov(tl,temp2);
3239 }
3240 if (opcode[i]==0x2D) { // SDR
3241 emit_writebyte_indexed(tl,3,temp);
3242 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3243 }
3244 done0=(int)out;
3245 emit_jmp(0);
3246 // 1
3247 set_jump_target(case1,(int)out);
3248 if (opcode[i]==0x2A) { // SWL
3249 // Write 3 msb into three least significant bytes
3250 if(rs2[i]) emit_rorimm(tl,8,tl);
3251 emit_writehword_indexed(tl,-1,temp);
3252 if(rs2[i]) emit_rorimm(tl,16,tl);
3253 emit_writebyte_indexed(tl,1,temp);
3254 if(rs2[i]) emit_rorimm(tl,8,tl);
3255 }
3256 if (opcode[i]==0x2E) { // SWR
3257 // Write two lsb into two most significant bytes
3258 emit_writehword_indexed(tl,1,temp);
3259 }
3260 if (opcode[i]==0x2C) { // SDL
3261 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3262 // Write 3 msb into three least significant bytes
3263 if(rs2[i]) emit_rorimm(th,8,th);
3264 emit_writehword_indexed(th,-1,temp);
3265 if(rs2[i]) emit_rorimm(th,16,th);
3266 emit_writebyte_indexed(th,1,temp);
3267 if(rs2[i]) emit_rorimm(th,8,th);
3268 }
3269 if (opcode[i]==0x2D) { // SDR
3270 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3271 // Write two lsb into two most significant bytes
3272 emit_writehword_indexed(tl,1,temp);
3273 }
3274 done1=(int)out;
3275 emit_jmp(0);
3276 // 2
3277 set_jump_target(case2,(int)out);
3278 emit_testimm(temp,1);
3279 case3=(int)out;
3280 emit_jne(0);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write two msb into two least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,16,tl);
3284 emit_writehword_indexed(tl,-2,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3286 }
3287 if (opcode[i]==0x2E) { // SWR
3288 // Write 3 lsb into three most significant bytes
3289 emit_writebyte_indexed(tl,-1,temp);
3290 if(rs2[i]) emit_rorimm(tl,8,tl);
3291 emit_writehword_indexed(tl,0,temp);
3292 if(rs2[i]) emit_rorimm(tl,24,tl);
3293 }
3294 if (opcode[i]==0x2C) { // SDL
3295 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3296 // Write two msb into two least significant bytes
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writehword_indexed(th,-2,temp);
3299 if(rs2[i]) emit_rorimm(th,16,th);
3300 }
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3303 // Write 3 lsb into three most significant bytes
3304 emit_writebyte_indexed(tl,-1,temp);
3305 if(rs2[i]) emit_rorimm(tl,8,tl);
3306 emit_writehword_indexed(tl,0,temp);
3307 if(rs2[i]) emit_rorimm(tl,24,tl);
3308 }
3309 done2=(int)out;
3310 emit_jmp(0);
3311 // 3
3312 set_jump_target(case3,(int)out);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write msb into least significant byte
3315 if(rs2[i]) emit_rorimm(tl,24,tl);
3316 emit_writebyte_indexed(tl,-3,temp);
3317 if(rs2[i]) emit_rorimm(tl,8,tl);
3318 }
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write entire word
3321 emit_writeword_indexed(tl,-3,temp);
3322 }
3323 if (opcode[i]==0x2C) { // SDL
3324 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3325 // Write msb into least significant byte
3326 if(rs2[i]) emit_rorimm(th,24,th);
3327 emit_writebyte_indexed(th,-3,temp);
3328 if(rs2[i]) emit_rorimm(th,8,th);
3329 }
3330 if (opcode[i]==0x2D) { // SDR
3331 if(rs2[i]) emit_mov(th,temp2);
3332 // Write entire word
3333 emit_writeword_indexed(tl,-3,temp);
3334 }
3335 set_jump_target(done0,(int)out);
3336 set_jump_target(done1,(int)out);
3337 set_jump_target(done2,(int)out);
3338 if (opcode[i]==0x2C) { // SDL
3339 emit_testimm(temp,4);
3340 done0=(int)out;
3341 emit_jne(0);
3342 emit_andimm(temp,~3,temp);
3343 emit_writeword_indexed(temp2,4,temp);
3344 set_jump_target(done0,(int)out);
3345 }
3346 if (opcode[i]==0x2D) { // SDR
3347 emit_testimm(temp,4);
3348 done0=(int)out;
3349 emit_jeq(0);
3350 emit_andimm(temp,~3,temp);
3351 emit_writeword_indexed(temp2,-4,temp);
3352 set_jump_target(done0,(int)out);
3353 }
3354 if(!c||!memtarget)
3355 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3356 }
3357 if(!using_tlb) {
3358 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3359 #if defined(HOST_IMM8)
3360 int ir=get_reg(i_regs->regmap,INVCP);
3361 assert(ir>=0);
3362 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3363 #else
3364 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3365 #endif
3366 jaddr2=(int)out;
3367 emit_jne(0);
3368 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3369 }
3370 /*
3371 emit_pusha();
3372 //save_regs(0x100f);
3373 emit_readword((int)&last_count,ECX);
3374 if(get_reg(i_regs->regmap,CCREG)<0)
3375 emit_loadreg(CCREG,HOST_CCREG);
3376 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3377 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3378 emit_writeword(HOST_CCREG,(int)&Count);
3379 emit_call((int)memdebug);
3380 emit_popa();
3381 //restore_regs(0x100f);
3382 /**/
3383}
3384
3385void c1ls_assemble(int i,struct regstat *i_regs)
3386{
3d624f89 3387#ifndef DISABLE_COP1
57871462 3388 int s,th,tl;
3389 int temp,ar;
3390 int map=-1;
3391 int offset;
3392 int c=0;
3393 int jaddr,jaddr2=0,jaddr3,type;
3394 int agr=AGEN1+(i&1);
3395 u_int hr,reglist=0;
3396 th=get_reg(i_regs->regmap,FTEMP|64);
3397 tl=get_reg(i_regs->regmap,FTEMP);
3398 s=get_reg(i_regs->regmap,rs1[i]);
3399 temp=get_reg(i_regs->regmap,agr);
3400 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3401 offset=imm[i];
3402 assert(tl>=0);
3403 assert(rs1[i]>0);
3404 assert(temp>=0);
3405 for(hr=0;hr<HOST_REGS;hr++) {
3406 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3407 }
3408 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3409 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3410 {
3411 // Loads use a temporary register which we need to save
3412 reglist|=1<<temp;
3413 }
3414 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3415 ar=temp;
3416 else // LWC1/LDC1
3417 ar=tl;
3418 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3419 //else c=(i_regs->wasconst>>s)&1;
3420 if(s>=0) c=(i_regs->wasconst>>s)&1;
3421 // Check cop1 unusable
3422 if(!cop1_usable) {
3423 signed char rs=get_reg(i_regs->regmap,CSREG);
3424 assert(rs>=0);
3425 emit_testimm(rs,0x20000000);
3426 jaddr=(int)out;
3427 emit_jeq(0);
3428 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3429 cop1_usable=1;
3430 }
3431 if (opcode[i]==0x39) { // SWC1 (get float address)
3432 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3433 }
3434 if (opcode[i]==0x3D) { // SDC1 (get double address)
3435 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3436 }
3437 // Generate address + offset
3438 if(!using_tlb) {
3439 if(!c)
3440 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3441 }
3442 else
3443 {
3444 map=get_reg(i_regs->regmap,TLREG);
3445 assert(map>=0);
3446 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3447 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3448 }
3449 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3450 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3451 }
3452 }
3453 if (opcode[i]==0x39) { // SWC1 (read float)
3454 emit_readword_indexed(0,tl,tl);
3455 }
3456 if (opcode[i]==0x3D) { // SDC1 (read double)
3457 emit_readword_indexed(4,tl,th);
3458 emit_readword_indexed(0,tl,tl);
3459 }
3460 if (opcode[i]==0x31) { // LWC1 (get target address)
3461 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3462 }
3463 if (opcode[i]==0x35) { // LDC1 (get target address)
3464 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3465 }
3466 if(!using_tlb) {
3467 if(!c) {
3468 jaddr2=(int)out;
3469 emit_jno(0);
3470 }
3471 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3472 jaddr2=(int)out;
3473 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3474 }
3475 #ifdef DESTRUCTIVE_SHIFT