drc: hacks for psx bios on PCSX
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
57871462 182
183 /* stubs */
184#define CC_STUB 1
185#define FP_STUB 2
186#define LOADB_STUB 3
187#define LOADH_STUB 4
188#define LOADW_STUB 5
189#define LOADD_STUB 6
190#define LOADBU_STUB 7
191#define LOADHU_STUB 8
192#define STOREB_STUB 9
193#define STOREH_STUB 10
194#define STOREW_STUB 11
195#define STORED_STUB 12
196#define STORELR_STUB 13
197#define INVCODE_STUB 14
198
199 /* branch codes */
200#define TAKEN 1
201#define NOTTAKEN 2
202#define NULLDS 3
203
204// asm linkage
205int new_recompile_block(int addr);
206void *get_addr_ht(u_int vaddr);
207void invalidate_block(u_int block);
208void invalidate_addr(u_int addr);
209void remove_hash(int vaddr);
210void jump_vaddr();
211void dyna_linker();
212void dyna_linker_ds();
213void verify_code();
214void verify_code_vm();
215void verify_code_ds();
216void cc_interrupt();
217void fp_exception();
218void fp_exception_ds();
219void jump_syscall();
7139f3c8 220void jump_syscall_hle();
57871462 221void jump_eret();
7139f3c8 222void jump_hlecall();
223void new_dyna_leave();
57871462 224
225// TLB
226void TLBWI_new();
227void TLBWR_new();
228void read_nomem_new();
229void read_nomemb_new();
230void read_nomemh_new();
231void read_nomemd_new();
232void write_nomem_new();
233void write_nomemb_new();
234void write_nomemh_new();
235void write_nomemd_new();
236void write_rdram_new();
237void write_rdramb_new();
238void write_rdramh_new();
239void write_rdramd_new();
240extern u_int memory_map[1048576];
241
242// Needed by assembler
243void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246void load_all_regs(signed char i_regmap[]);
247void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248void load_regs_entry(int t);
249void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
250
251int tracedebug=0;
252
253//#define DEBUG_CYCLE_COUNT 1
254
255void nullf() {}
256//#define assem_debug printf
257//#define inv_debug printf
258#define assem_debug nullf
259#define inv_debug nullf
260
94d23bb9 261static void tlb_hacks()
57871462 262{
94d23bb9 263#ifndef DISABLE_TLB
57871462 264 // Goldeneye hack
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
266 {
267 u_int addr;
268 int n;
269 switch (ROM_HEADER->Country_code&0xFF)
270 {
271 case 0x45: // U
272 addr=0x34b30;
273 break;
274 case 0x4A: // J
275 addr=0x34b70;
276 break;
277 case 0x50: // E
278 addr=0x329f0;
279 break;
280 default:
281 // Unknown country code
282 addr=0;
283 break;
284 }
285 u_int rom_addr=(u_int)rom;
286 #ifdef ROM_COPY
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
297 }
298 #endif
299 if(addr) {
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
302 }
303 }
304 }
94d23bb9 305#endif
57871462 306}
307
94d23bb9 308static u_int get_page(u_int vaddr)
57871462 309{
310 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 311#ifndef DISABLE_TLB
57871462 312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 313#endif
57871462 314 if(page>2048) page=2048+(page&2047);
94d23bb9 315 return page;
316}
317
318static u_int get_vpage(u_int vaddr)
319{
320 u_int vpage=(vaddr^0x80000000)>>12;
321#ifndef DISABLE_TLB
57871462 322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 323#endif
57871462 324 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 325 return vpage;
326}
327
328// Get address from virtual address
329// This is called from the recompiled JR/JALR instructions
330void *get_addr(u_int vaddr)
331{
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
57871462 334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
336 head=jump_in[page];
337 while(head!=NULL) {
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
341 ht_bin[3]=ht_bin[1];
342 ht_bin[2]=ht_bin[0];
343 ht_bin[1]=(int)head->addr;
344 ht_bin[0]=vaddr;
345 return head->addr;
346 }
347 head=head->next;
348 }
349 head=jump_dirty[vpage];
350 while(head!=NULL) {
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
359 if(vpage<2048) {
94d23bb9 360#ifndef DISABLE_TLB
57871462 361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
364 }
94d23bb9 365#endif
57871462 366 restore_candidate[vpage>>3]|=1<<(vpage&7);
367 }
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
372 }
373 else
374 {
375 ht_bin[3]=ht_bin[1];
376 ht_bin[2]=ht_bin[0];
377 ht_bin[1]=(int)head->addr;
378 ht_bin[0]=vaddr;
379 }
380 return head->addr;
381 }
382 }
383 head=head->next;
384 }
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
560e4a12 388#ifdef PCSX
389 return (void *)r;
390#else
57871462 391 // Execute in unmapped page, generate pagefault execption
392 Status|=2;
393 Cause=(vaddr<<31)|0x8;
394 EPC=(vaddr&1)?vaddr-5:vaddr;
395 BadVAddr=(vaddr&~1);
396 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
397 EntryHi=BadVAddr&0xFFFFE000;
398 return get_addr_ht(0x80000000);
560e4a12 399#endif
57871462 400}
401// Look up address in hash table first
402void *get_addr_ht(u_int vaddr)
403{
404 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
405 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
406 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
407 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
408 return get_addr(vaddr);
409}
410
411void *get_addr_32(u_int vaddr,u_int flags)
412{
7139f3c8 413#ifdef FORCE32
414 return get_addr(vaddr);
560e4a12 415#else
57871462 416 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 420 u_int page=get_page(vaddr);
421 u_int vpage=get_vpage(vaddr);
57871462 422 struct ll_entry *head;
423 head=jump_in[page];
424 while(head!=NULL) {
425 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
426 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
427 if(head->reg32==0) {
428 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
429 if(ht_bin[0]==-1) {
430 ht_bin[1]=(int)head->addr;
431 ht_bin[0]=vaddr;
432 }else if(ht_bin[2]==-1) {
433 ht_bin[3]=(int)head->addr;
434 ht_bin[2]=vaddr;
435 }
436 //ht_bin[3]=ht_bin[1];
437 //ht_bin[2]=ht_bin[0];
438 //ht_bin[1]=(int)head->addr;
439 //ht_bin[0]=vaddr;
440 }
441 return head->addr;
442 }
443 head=head->next;
444 }
445 head=jump_dirty[vpage];
446 while(head!=NULL) {
447 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
448 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
449 // Don't restore blocks which are about to expire from the cache
450 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
451 if(verify_dirty(head->addr)) {
452 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
453 invalid_code[vaddr>>12]=0;
454 memory_map[vaddr>>12]|=0x40000000;
455 if(vpage<2048) {
94d23bb9 456#ifndef DISABLE_TLB
57871462 457 if(tlb_LUT_r[vaddr>>12]) {
458 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
459 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
460 }
94d23bb9 461#endif
57871462 462 restore_candidate[vpage>>3]|=1<<(vpage&7);
463 }
464 else restore_candidate[page>>3]|=1<<(page&7);
465 if(head->reg32==0) {
466 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
467 if(ht_bin[0]==-1) {
468 ht_bin[1]=(int)head->addr;
469 ht_bin[0]=vaddr;
470 }else if(ht_bin[2]==-1) {
471 ht_bin[3]=(int)head->addr;
472 ht_bin[2]=vaddr;
473 }
474 //ht_bin[3]=ht_bin[1];
475 //ht_bin[2]=ht_bin[0];
476 //ht_bin[1]=(int)head->addr;
477 //ht_bin[0]=vaddr;
478 }
479 return head->addr;
480 }
481 }
482 head=head->next;
483 }
484 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
485 int r=new_recompile_block(vaddr);
486 if(r==0) return get_addr(vaddr);
487 // Execute in unmapped page, generate pagefault execption
488 Status|=2;
489 Cause=(vaddr<<31)|0x8;
490 EPC=(vaddr&1)?vaddr-5:vaddr;
491 BadVAddr=(vaddr&~1);
492 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
493 EntryHi=BadVAddr&0xFFFFE000;
494 return get_addr_ht(0x80000000);
560e4a12 495#endif
57871462 496}
497
498void clear_all_regs(signed char regmap[])
499{
500 int hr;
501 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
502}
503
504signed char get_reg(signed char regmap[],int r)
505{
506 int hr;
507 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
508 return -1;
509}
510
511// Find a register that is available for two consecutive cycles
512signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
513{
514 int hr;
515 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
516 return -1;
517}
518
519int count_free_regs(signed char regmap[])
520{
521 int count=0;
522 int hr;
523 for(hr=0;hr<HOST_REGS;hr++)
524 {
525 if(hr!=EXCLUDE_REG) {
526 if(regmap[hr]<0) count++;
527 }
528 }
529 return count;
530}
531
532void dirty_reg(struct regstat *cur,signed char reg)
533{
534 int hr;
535 if(!reg) return;
536 for (hr=0;hr<HOST_REGS;hr++) {
537 if((cur->regmap[hr]&63)==reg) {
538 cur->dirty|=1<<hr;
539 }
540 }
541}
542
543// If we dirty the lower half of a 64 bit register which is now being
544// sign-extended, we need to dump the upper half.
545// Note: Do this only after completion of the instruction, because
546// some instructions may need to read the full 64-bit value even if
547// overwriting it (eg SLTI, DSRA32).
548static void flush_dirty_uppers(struct regstat *cur)
549{
550 int hr,reg;
551 for (hr=0;hr<HOST_REGS;hr++) {
552 if((cur->dirty>>hr)&1) {
553 reg=cur->regmap[hr];
554 if(reg>=64)
555 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
556 }
557 }
558}
559
560void set_const(struct regstat *cur,signed char reg,uint64_t value)
561{
562 int hr;
563 if(!reg) return;
564 for (hr=0;hr<HOST_REGS;hr++) {
565 if(cur->regmap[hr]==reg) {
566 cur->isconst|=1<<hr;
567 cur->constmap[hr]=value;
568 }
569 else if((cur->regmap[hr]^64)==reg) {
570 cur->isconst|=1<<hr;
571 cur->constmap[hr]=value>>32;
572 }
573 }
574}
575
576void clear_const(struct regstat *cur,signed char reg)
577{
578 int hr;
579 if(!reg) return;
580 for (hr=0;hr<HOST_REGS;hr++) {
581 if((cur->regmap[hr]&63)==reg) {
582 cur->isconst&=~(1<<hr);
583 }
584 }
585}
586
587int is_const(struct regstat *cur,signed char reg)
588{
589 int hr;
590 if(!reg) return 1;
591 for (hr=0;hr<HOST_REGS;hr++) {
592 if((cur->regmap[hr]&63)==reg) {
593 return (cur->isconst>>hr)&1;
594 }
595 }
596 return 0;
597}
598uint64_t get_const(struct regstat *cur,signed char reg)
599{
600 int hr;
601 if(!reg) return 0;
602 for (hr=0;hr<HOST_REGS;hr++) {
603 if(cur->regmap[hr]==reg) {
604 return cur->constmap[hr];
605 }
606 }
607 printf("Unknown constant in r%d\n",reg);
608 exit(1);
609}
610
611// Least soon needed registers
612// Look at the next ten instructions and see which registers
613// will be used. Try not to reallocate these.
614void lsn(u_char hsn[], int i, int *preferred_reg)
615{
616 int j;
617 int b=-1;
618 for(j=0;j<9;j++)
619 {
620 if(i+j>=slen) {
621 j=slen-i-1;
622 break;
623 }
624 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
625 {
626 // Don't go past an unconditonal jump
627 j++;
628 break;
629 }
630 }
631 for(;j>=0;j--)
632 {
633 if(rs1[i+j]) hsn[rs1[i+j]]=j;
634 if(rs2[i+j]) hsn[rs2[i+j]]=j;
635 if(rt1[i+j]) hsn[rt1[i+j]]=j;
636 if(rt2[i+j]) hsn[rt2[i+j]]=j;
637 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
638 // Stores can allocate zero
639 hsn[rs1[i+j]]=j;
640 hsn[rs2[i+j]]=j;
641 }
642 // On some architectures stores need invc_ptr
643 #if defined(HOST_IMM8)
b9b61529 644 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 645 hsn[INVCP]=j;
646 }
647 #endif
648 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
649 {
650 hsn[CCREG]=j;
651 b=j;
652 }
653 }
654 if(b>=0)
655 {
656 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
657 {
658 // Follow first branch
659 int t=(ba[i+b]-start)>>2;
660 j=7-b;if(t+j>=slen) j=slen-t-1;
661 for(;j>=0;j--)
662 {
663 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
664 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
665 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
666 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
667 }
668 }
669 // TODO: preferred register based on backward branch
670 }
671 // Delay slot should preferably not overwrite branch conditions or cycle count
672 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
673 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
674 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
675 hsn[CCREG]=1;
676 // ...or hash tables
677 hsn[RHASH]=1;
678 hsn[RHTBL]=1;
679 }
680 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 681 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 682 hsn[FTEMP]=0;
683 }
684 // Load L/R also uses FTEMP as a temporary register
685 if(itype[i]==LOADLR) {
686 hsn[FTEMP]=0;
687 }
b7918751 688 // Also SWL/SWR/SDL/SDR
689 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 690 hsn[FTEMP]=0;
691 }
692 // Don't remove the TLB registers either
b9b61529 693 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 694 hsn[TLREG]=0;
695 }
696 // Don't remove the miniht registers
697 if(itype[i]==UJUMP||itype[i]==RJUMP)
698 {
699 hsn[RHASH]=0;
700 hsn[RHTBL]=0;
701 }
702}
703
704// We only want to allocate registers if we're going to use them again soon
705int needed_again(int r, int i)
706{
707 int j;
708 int b=-1;
709 int rn=10;
710 int hr;
711 u_char hsn[MAXREG+1];
712 int preferred_reg;
713
714 memset(hsn,10,sizeof(hsn));
715 lsn(hsn,i,&preferred_reg);
716
717 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
718 {
719 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
720 return 0; // Don't need any registers if exiting the block
721 }
722 for(j=0;j<9;j++)
723 {
724 if(i+j>=slen) {
725 j=slen-i-1;
726 break;
727 }
728 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
729 {
730 // Don't go past an unconditonal jump
731 j++;
732 break;
733 }
7139f3c8 734 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 735 {
736 break;
737 }
738 }
739 for(;j>=1;j--)
740 {
741 if(rs1[i+j]==r) rn=j;
742 if(rs2[i+j]==r) rn=j;
743 if((unneeded_reg[i+j]>>r)&1) rn=10;
744 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
745 {
746 b=j;
747 }
748 }
749 /*
750 if(b>=0)
751 {
752 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
753 {
754 // Follow first branch
755 int o=rn;
756 int t=(ba[i+b]-start)>>2;
757 j=7-b;if(t+j>=slen) j=slen-t-1;
758 for(;j>=0;j--)
759 {
760 if(!((unneeded_reg[t+j]>>r)&1)) {
761 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
762 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
763 }
764 else rn=o;
765 }
766 }
767 }*/
768 for(hr=0;hr<HOST_REGS;hr++) {
769 if(hr!=EXCLUDE_REG) {
770 if(rn<hsn[hr]) return 1;
771 }
772 }
773 return 0;
774}
775
776// Try to match register allocations at the end of a loop with those
777// at the beginning
778int loop_reg(int i, int r, int hr)
779{
780 int j,k;
781 for(j=0;j<9;j++)
782 {
783 if(i+j>=slen) {
784 j=slen-i-1;
785 break;
786 }
787 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
788 {
789 // Don't go past an unconditonal jump
790 j++;
791 break;
792 }
793 }
794 k=0;
795 if(i>0){
796 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
797 k--;
798 }
799 for(;k<j;k++)
800 {
801 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
802 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
803 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
804 {
805 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
806 {
807 int t=(ba[i+k]-start)>>2;
808 int reg=get_reg(regs[t].regmap_entry,r);
809 if(reg>=0) return reg;
810 //reg=get_reg(regs[t+1].regmap_entry,r);
811 //if(reg>=0) return reg;
812 }
813 }
814 }
815 return hr;
816}
817
818
819// Allocate every register, preserving source/target regs
820void alloc_all(struct regstat *cur,int i)
821{
822 int hr;
823
824 for(hr=0;hr<HOST_REGS;hr++) {
825 if(hr!=EXCLUDE_REG) {
826 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
827 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
828 {
829 cur->regmap[hr]=-1;
830 cur->dirty&=~(1<<hr);
831 }
832 // Don't need zeros
833 if((cur->regmap[hr]&63)==0)
834 {
835 cur->regmap[hr]=-1;
836 cur->dirty&=~(1<<hr);
837 }
838 }
839 }
840}
841
842
843void div64(int64_t dividend,int64_t divisor)
844{
845 lo=dividend/divisor;
846 hi=dividend%divisor;
847 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
848 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
849}
850void divu64(uint64_t dividend,uint64_t divisor)
851{
852 lo=dividend/divisor;
853 hi=dividend%divisor;
854 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
855 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856}
857
858void mult64(uint64_t m1,uint64_t m2)
859{
860 unsigned long long int op1, op2, op3, op4;
861 unsigned long long int result1, result2, result3, result4;
862 unsigned long long int temp1, temp2, temp3, temp4;
863 int sign = 0;
864
865 if (m1 < 0)
866 {
867 op2 = -m1;
868 sign = 1 - sign;
869 }
870 else op2 = m1;
871 if (m2 < 0)
872 {
873 op4 = -m2;
874 sign = 1 - sign;
875 }
876 else op4 = m2;
877
878 op1 = op2 & 0xFFFFFFFF;
879 op2 = (op2 >> 32) & 0xFFFFFFFF;
880 op3 = op4 & 0xFFFFFFFF;
881 op4 = (op4 >> 32) & 0xFFFFFFFF;
882
883 temp1 = op1 * op3;
884 temp2 = (temp1 >> 32) + op1 * op4;
885 temp3 = op2 * op3;
886 temp4 = (temp3 >> 32) + op2 * op4;
887
888 result1 = temp1 & 0xFFFFFFFF;
889 result2 = temp2 + (temp3 & 0xFFFFFFFF);
890 result3 = (result2 >> 32) + temp4;
891 result4 = (result3 >> 32);
892
893 lo = result1 | (result2 << 32);
894 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
895 if (sign)
896 {
897 hi = ~hi;
898 if (!lo) hi++;
899 else lo = ~lo + 1;
900 }
901}
902
903void multu64(uint64_t m1,uint64_t m2)
904{
905 unsigned long long int op1, op2, op3, op4;
906 unsigned long long int result1, result2, result3, result4;
907 unsigned long long int temp1, temp2, temp3, temp4;
908
909 op1 = m1 & 0xFFFFFFFF;
910 op2 = (m1 >> 32) & 0xFFFFFFFF;
911 op3 = m2 & 0xFFFFFFFF;
912 op4 = (m2 >> 32) & 0xFFFFFFFF;
913
914 temp1 = op1 * op3;
915 temp2 = (temp1 >> 32) + op1 * op4;
916 temp3 = op2 * op3;
917 temp4 = (temp3 >> 32) + op2 * op4;
918
919 result1 = temp1 & 0xFFFFFFFF;
920 result2 = temp2 + (temp3 & 0xFFFFFFFF);
921 result3 = (result2 >> 32) + temp4;
922 result4 = (result3 >> 32);
923
924 lo = result1 | (result2 << 32);
925 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
926
927 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
928 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
929}
930
931uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
932{
933 if(bits) {
934 original<<=64-bits;
935 original>>=64-bits;
936 loaded<<=bits;
937 original|=loaded;
938 }
939 else original=loaded;
940 return original;
941}
942uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
943{
944 if(bits^56) {
945 original>>=64-(bits^56);
946 original<<=64-(bits^56);
947 loaded>>=bits^56;
948 original|=loaded;
949 }
950 else original=loaded;
951 return original;
952}
953
954#ifdef __i386__
955#include "assem_x86.c"
956#endif
957#ifdef __x86_64__
958#include "assem_x64.c"
959#endif
960#ifdef __arm__
961#include "assem_arm.c"
962#endif
963
964// Add virtual address mapping to linked list
965void ll_add(struct ll_entry **head,int vaddr,void *addr)
966{
967 struct ll_entry *new_entry;
968 new_entry=malloc(sizeof(struct ll_entry));
969 assert(new_entry!=NULL);
970 new_entry->vaddr=vaddr;
971 new_entry->reg32=0;
972 new_entry->addr=addr;
973 new_entry->next=*head;
974 *head=new_entry;
975}
976
977// Add virtual address mapping for 32-bit compiled block
978void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
979{
7139f3c8 980 ll_add(head,vaddr,addr);
981#ifndef FORCE32
982 (*head)->reg32=reg32;
983#endif
57871462 984}
985
986// Check if an address is already compiled
987// but don't return addresses which are about to expire from the cache
988void *check_addr(u_int vaddr)
989{
990 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
991 if(ht_bin[0]==vaddr) {
992 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
993 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
994 }
995 if(ht_bin[2]==vaddr) {
996 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
997 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
998 }
94d23bb9 999 u_int page=get_page(vaddr);
57871462 1000 struct ll_entry *head;
1001 head=jump_in[page];
1002 while(head!=NULL) {
1003 if(head->vaddr==vaddr&&head->reg32==0) {
1004 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1005 // Update existing entry with current address
1006 if(ht_bin[0]==vaddr) {
1007 ht_bin[1]=(int)head->addr;
1008 return head->addr;
1009 }
1010 if(ht_bin[2]==vaddr) {
1011 ht_bin[3]=(int)head->addr;
1012 return head->addr;
1013 }
1014 // Insert into hash table with low priority.
1015 // Don't evict existing entries, as they are probably
1016 // addresses that are being accessed frequently.
1017 if(ht_bin[0]==-1) {
1018 ht_bin[1]=(int)head->addr;
1019 ht_bin[0]=vaddr;
1020 }else if(ht_bin[2]==-1) {
1021 ht_bin[3]=(int)head->addr;
1022 ht_bin[2]=vaddr;
1023 }
1024 return head->addr;
1025 }
1026 }
1027 head=head->next;
1028 }
1029 return 0;
1030}
1031
1032void remove_hash(int vaddr)
1033{
1034 //printf("remove hash: %x\n",vaddr);
1035 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1036 if(ht_bin[2]==vaddr) {
1037 ht_bin[2]=ht_bin[3]=-1;
1038 }
1039 if(ht_bin[0]==vaddr) {
1040 ht_bin[0]=ht_bin[2];
1041 ht_bin[1]=ht_bin[3];
1042 ht_bin[2]=ht_bin[3]=-1;
1043 }
1044}
1045
1046void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1047{
1048 struct ll_entry *next;
1049 while(*head) {
1050 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1051 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1052 {
1053 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1054 remove_hash((*head)->vaddr);
1055 next=(*head)->next;
1056 free(*head);
1057 *head=next;
1058 }
1059 else
1060 {
1061 head=&((*head)->next);
1062 }
1063 }
1064}
1065
1066// Remove all entries from linked list
1067void ll_clear(struct ll_entry **head)
1068{
1069 struct ll_entry *cur;
1070 struct ll_entry *next;
1071 if(cur=*head) {
1072 *head=0;
1073 while(cur) {
1074 next=cur->next;
1075 free(cur);
1076 cur=next;
1077 }
1078 }
1079}
1080
1081// Dereference the pointers and remove if it matches
1082void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1083{
f76eeef9 1084 u_int old_host_addr=0;
57871462 1085 while(head) {
1086 int ptr=get_pointer(head->addr);
1087 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1088 if(((ptr>>shift)==(addr>>shift)) ||
1089 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1090 {
f76eeef9 1091 printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1092 u_int host_addr=(u_int)kill_pointer(head->addr);
1093
1094 if((host_addr>>12)!=(old_host_addr>>12)) {
1095 #ifdef __arm__
1096 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1097 #endif
1098 old_host_addr=host_addr;
1099 }
57871462 1100 }
1101 head=head->next;
1102 }
f76eeef9 1103 #ifdef __arm__
1104 if (old_host_addr)
1105 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1106 #endif
57871462 1107}
1108
1109// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1110void invalidate_page(u_int page)
57871462 1111{
57871462 1112 struct ll_entry *head;
1113 struct ll_entry *next;
f76eeef9 1114 u_int old_host_addr=0;
57871462 1115 head=jump_in[page];
1116 jump_in[page]=0;
1117 while(head!=NULL) {
1118 inv_debug("INVALIDATE: %x\n",head->vaddr);
1119 remove_hash(head->vaddr);
1120 next=head->next;
1121 free(head);
1122 head=next;
1123 }
1124 head=jump_out[page];
1125 jump_out[page]=0;
1126 while(head!=NULL) {
1127 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1128 u_int host_addr=(u_int)kill_pointer(head->addr);
1129
1130 if((host_addr>>12)!=(old_host_addr>>12)) {
1131 #ifdef __arm__
1132 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1133 #endif
1134 old_host_addr=host_addr;
1135 }
57871462 1136 next=head->next;
1137 free(head);
1138 head=next;
1139 }
f76eeef9 1140 #ifdef __arm__
1141 if (old_host_addr)
1142 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1143 #endif
57871462 1144}
1145void invalidate_block(u_int block)
1146{
94d23bb9 1147 u_int page=get_page(block<<12);
1148 u_int vpage=get_vpage(block<<12);
57871462 1149 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1150 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1151 u_int first,last;
1152 first=last=page;
1153 struct ll_entry *head;
1154 head=jump_dirty[vpage];
1155 //printf("page=%d vpage=%d\n",page,vpage);
1156 while(head!=NULL) {
1157 u_int start,end;
1158 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1159 get_bounds((int)head->addr,&start,&end);
1160 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1161 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1162 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1163 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1164 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1165 }
1166 }
90ae6d4e 1167#ifndef DISABLE_TLB
57871462 1168 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1169 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1170 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1171 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1172 }
1173 }
90ae6d4e 1174#endif
57871462 1175 }
1176 head=head->next;
1177 }
1178 //printf("first=%d last=%d\n",first,last);
f76eeef9 1179 invalidate_page(page);
57871462 1180 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1181 assert(last<page+5);
1182 // Invalidate the adjacent pages if a block crosses a 4K boundary
1183 while(first<page) {
1184 invalidate_page(first);
1185 first++;
1186 }
1187 for(first=page+1;first<last;first++) {
1188 invalidate_page(first);
1189 }
1190
1191 // Don't trap writes
1192 invalid_code[block]=1;
94d23bb9 1193#ifndef DISABLE_TLB
57871462 1194 // If there is a valid TLB entry for this page, remove write protect
1195 if(tlb_LUT_w[block]) {
1196 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1197 // CHECK: Is this right?
1198 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1199 u_int real_block=tlb_LUT_w[block]>>12;
1200 invalid_code[real_block]=1;
1201 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1202 }
1203 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1204#endif
f76eeef9 1205
57871462 1206 #ifdef USE_MINI_HT
1207 memset(mini_ht,-1,sizeof(mini_ht));
1208 #endif
1209}
1210void invalidate_addr(u_int addr)
1211{
1212 invalidate_block(addr>>12);
1213}
1214void invalidate_all_pages()
1215{
1216 u_int page,n;
1217 for(page=0;page<4096;page++)
1218 invalidate_page(page);
1219 for(page=0;page<1048576;page++)
1220 if(!invalid_code[page]) {
1221 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1222 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1223 }
1224 #ifdef __arm__
1225 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1226 #endif
1227 #ifdef USE_MINI_HT
1228 memset(mini_ht,-1,sizeof(mini_ht));
1229 #endif
94d23bb9 1230 #ifndef DISABLE_TLB
57871462 1231 // TLB
1232 for(page=0;page<0x100000;page++) {
1233 if(tlb_LUT_r[page]) {
1234 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1235 if(!tlb_LUT_w[page]||!invalid_code[page])
1236 memory_map[page]|=0x40000000; // Write protect
1237 }
1238 else memory_map[page]=-1;
1239 if(page==0x80000) page=0xC0000;
1240 }
1241 tlb_hacks();
94d23bb9 1242 #endif
57871462 1243}
1244
1245// Add an entry to jump_out after making a link
1246void add_link(u_int vaddr,void *src)
1247{
94d23bb9 1248 u_int page=get_page(vaddr);
57871462 1249 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1250 ll_add(jump_out+page,vaddr,src);
1251 //int ptr=get_pointer(src);
1252 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1253}
1254
1255// If a code block was found to be unmodified (bit was set in
1256// restore_candidate) and it remains unmodified (bit is clear
1257// in invalid_code) then move the entries for that 4K page from
1258// the dirty list to the clean list.
1259void clean_blocks(u_int page)
1260{
1261 struct ll_entry *head;
1262 inv_debug("INV: clean_blocks page=%d\n",page);
1263 head=jump_dirty[page];
1264 while(head!=NULL) {
1265 if(!invalid_code[head->vaddr>>12]) {
1266 // Don't restore blocks which are about to expire from the cache
1267 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1268 u_int start,end;
1269 if(verify_dirty((int)head->addr)) {
1270 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1271 u_int i;
1272 u_int inv=0;
1273 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1274 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1275 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1276 inv|=invalid_code[i];
1277 }
1278 }
1279 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1280 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1281 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1282 if(addr<start||addr>=end) inv=1;
1283 }
4cb76aa4 1284 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1285 inv=1;
1286 }
1287 if(!inv) {
1288 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1289 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1290 u_int ppage=page;
94d23bb9 1291#ifndef DISABLE_TLB
57871462 1292 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1293#endif
57871462 1294 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1295 //printf("page=%x, addr=%x\n",page,head->vaddr);
1296 //assert(head->vaddr>>12==(page|0x80000));
1297 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1298 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1299 if(!head->reg32) {
1300 if(ht_bin[0]==head->vaddr) {
1301 ht_bin[1]=(int)clean_addr; // Replace existing entry
1302 }
1303 if(ht_bin[2]==head->vaddr) {
1304 ht_bin[3]=(int)clean_addr; // Replace existing entry
1305 }
1306 }
1307 }
1308 }
1309 }
1310 }
1311 }
1312 head=head->next;
1313 }
1314}
1315
1316
1317void mov_alloc(struct regstat *current,int i)
1318{
1319 // Note: Don't need to actually alloc the source registers
1320 if((~current->is32>>rs1[i])&1) {
1321 //alloc_reg64(current,i,rs1[i]);
1322 alloc_reg64(current,i,rt1[i]);
1323 current->is32&=~(1LL<<rt1[i]);
1324 } else {
1325 //alloc_reg(current,i,rs1[i]);
1326 alloc_reg(current,i,rt1[i]);
1327 current->is32|=(1LL<<rt1[i]);
1328 }
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 dirty_reg(current,rt1[i]);
1332}
1333
1334void shiftimm_alloc(struct regstat *current,int i)
1335{
1336 clear_const(current,rs1[i]);
1337 clear_const(current,rt1[i]);
1338 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1339 {
1340 if(rt1[i]) {
1341 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1342 else lt1[i]=rs1[i];
1343 alloc_reg(current,i,rt1[i]);
1344 current->is32|=1LL<<rt1[i];
1345 dirty_reg(current,rt1[i]);
1346 }
1347 }
1348 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1349 {
1350 if(rt1[i]) {
1351 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1352 alloc_reg64(current,i,rt1[i]);
1353 current->is32&=~(1LL<<rt1[i]);
1354 dirty_reg(current,rt1[i]);
1355 }
1356 }
1357 if(opcode2[i]==0x3c) // DSLL32
1358 {
1359 if(rt1[i]) {
1360 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1361 alloc_reg64(current,i,rt1[i]);
1362 current->is32&=~(1LL<<rt1[i]);
1363 dirty_reg(current,rt1[i]);
1364 }
1365 }
1366 if(opcode2[i]==0x3e) // DSRL32
1367 {
1368 if(rt1[i]) {
1369 alloc_reg64(current,i,rs1[i]);
1370 if(imm[i]==32) {
1371 alloc_reg64(current,i,rt1[i]);
1372 current->is32&=~(1LL<<rt1[i]);
1373 } else {
1374 alloc_reg(current,i,rt1[i]);
1375 current->is32|=1LL<<rt1[i];
1376 }
1377 dirty_reg(current,rt1[i]);
1378 }
1379 }
1380 if(opcode2[i]==0x3f) // DSRA32
1381 {
1382 if(rt1[i]) {
1383 alloc_reg64(current,i,rs1[i]);
1384 alloc_reg(current,i,rt1[i]);
1385 current->is32|=1LL<<rt1[i];
1386 dirty_reg(current,rt1[i]);
1387 }
1388 }
1389}
1390
1391void shift_alloc(struct regstat *current,int i)
1392{
1393 if(rt1[i]) {
1394 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1395 {
1396 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1397 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1398 alloc_reg(current,i,rt1[i]);
1399 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1400 current->is32|=1LL<<rt1[i];
1401 } else { // DSLLV/DSRLV/DSRAV
1402 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1403 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1404 alloc_reg64(current,i,rt1[i]);
1405 current->is32&=~(1LL<<rt1[i]);
1406 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1407 alloc_reg_temp(current,i,-1);
1408 }
1409 clear_const(current,rs1[i]);
1410 clear_const(current,rs2[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1413 }
1414}
1415
1416void alu_alloc(struct regstat *current,int i)
1417{
1418 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1419 if(rt1[i]) {
1420 if(rs1[i]&&rs2[i]) {
1421 alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rs2[i]);
1423 }
1424 else {
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427 }
1428 alloc_reg(current,i,rt1[i]);
1429 }
1430 current->is32|=1LL<<rt1[i];
1431 }
1432 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1433 if(rt1[i]) {
1434 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1435 {
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1439 } else {
1440 alloc_reg(current,i,rs1[i]);
1441 alloc_reg(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1443 }
1444 }
1445 current->is32|=1LL<<rt1[i];
1446 }
1447 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1448 if(rt1[i]) {
1449 if(rs1[i]&&rs2[i]) {
1450 alloc_reg(current,i,rs1[i]);
1451 alloc_reg(current,i,rs2[i]);
1452 }
1453 else
1454 {
1455 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1456 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1457 }
1458 alloc_reg(current,i,rt1[i]);
1459 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1460 {
1461 if(!((current->uu>>rt1[i])&1)) {
1462 alloc_reg64(current,i,rt1[i]);
1463 }
1464 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1465 if(rs1[i]&&rs2[i]) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 }
1469 else
1470 {
1471 // Is is really worth it to keep 64-bit values in registers?
1472 #ifdef NATIVE_64BIT
1473 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1474 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1475 #endif
1476 }
1477 }
1478 current->is32&=~(1LL<<rt1[i]);
1479 } else {
1480 current->is32|=1LL<<rt1[i];
1481 }
1482 }
1483 }
1484 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1485 if(rt1[i]) {
1486 if(rs1[i]&&rs2[i]) {
1487 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1488 alloc_reg64(current,i,rs1[i]);
1489 alloc_reg64(current,i,rs2[i]);
1490 alloc_reg64(current,i,rt1[i]);
1491 } else {
1492 alloc_reg(current,i,rs1[i]);
1493 alloc_reg(current,i,rs2[i]);
1494 alloc_reg(current,i,rt1[i]);
1495 }
1496 }
1497 else {
1498 alloc_reg(current,i,rt1[i]);
1499 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1500 // DADD used as move, or zeroing
1501 // If we have a 64-bit source, then make the target 64 bits too
1502 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1503 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1504 alloc_reg64(current,i,rt1[i]);
1505 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1506 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1507 alloc_reg64(current,i,rt1[i]);
1508 }
1509 if(opcode2[i]>=0x2e&&rs2[i]) {
1510 // DSUB used as negation - 64-bit result
1511 // If we have a 32-bit register, extend it to 64 bits
1512 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1513 alloc_reg64(current,i,rt1[i]);
1514 }
1515 }
1516 }
1517 if(rs1[i]&&rs2[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1519 } else if(rs1[i]) {
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs1[i])&1)
1522 current->is32|=1LL<<rt1[i];
1523 } else if(rs2[i]) {
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs2[i])&1)
1526 current->is32|=1LL<<rt1[i];
1527 } else {
1528 current->is32|=1LL<<rt1[i];
1529 }
1530 }
1531 }
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1536}
1537
1538void imm16_alloc(struct regstat *current,int i)
1539{
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 else lt1[i]=rs1[i];
1542 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1543 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1544 current->is32&=~(1LL<<rt1[i]);
1545 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1546 // TODO: Could preserve the 32-bit flag if the immediate is zero
1547 alloc_reg64(current,i,rt1[i]);
1548 alloc_reg64(current,i,rs1[i]);
1549 }
1550 clear_const(current,rs1[i]);
1551 clear_const(current,rt1[i]);
1552 }
1553 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1554 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1555 current->is32|=1LL<<rt1[i];
1556 clear_const(current,rs1[i]);
1557 clear_const(current,rt1[i]);
1558 }
1559 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1560 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1561 if(rs1[i]!=rt1[i]) {
1562 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1565 }
1566 }
1567 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1568 if(is_const(current,rs1[i])) {
1569 int v=get_const(current,rs1[i]);
1570 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1571 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1572 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1573 }
1574 else clear_const(current,rt1[i]);
1575 }
1576 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1577 if(is_const(current,rs1[i])) {
1578 int v=get_const(current,rs1[i]);
1579 set_const(current,rt1[i],v+imm[i]);
1580 }
1581 else clear_const(current,rt1[i]);
1582 current->is32|=1LL<<rt1[i];
1583 }
1584 else {
1585 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1586 current->is32|=1LL<<rt1[i];
1587 }
1588 dirty_reg(current,rt1[i]);
1589}
1590
1591void load_alloc(struct regstat *current,int i)
1592{
1593 clear_const(current,rt1[i]);
1594 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1595 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1596 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1597 if(rt1[i]) {
1598 alloc_reg(current,i,rt1[i]);
1599 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1600 {
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 }
1604 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 alloc_all(current,i);
1609 alloc_reg64(current,i,FTEMP);
1610 }
1611 else current->is32|=1LL<<rt1[i];
1612 dirty_reg(current,rt1[i]);
1613 // If using TLB, need a register for pointer to the mapping table
1614 if(using_tlb) alloc_reg(current,i,TLREG);
1615 // LWL/LWR need a temporary register for the old value
1616 if(opcode[i]==0x22||opcode[i]==0x26)
1617 {
1618 alloc_reg(current,i,FTEMP);
1619 alloc_reg_temp(current,i,-1);
1620 }
1621 }
1622 else
1623 {
1624 // Load to r0 (dummy load)
1625 // but we still need a register to calculate the address
1626 alloc_reg_temp(current,i,-1);
1627 }
1628}
1629
1630void store_alloc(struct regstat *current,int i)
1631{
1632 clear_const(current,rs2[i]);
1633 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1634 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1635 alloc_reg(current,i,rs2[i]);
1636 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1637 alloc_reg64(current,i,rs2[i]);
1638 if(rs2[i]) alloc_reg(current,i,FTEMP);
1639 }
1640 // If using TLB, need a register for pointer to the mapping table
1641 if(using_tlb) alloc_reg(current,i,TLREG);
1642 #if defined(HOST_IMM8)
1643 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1644 else alloc_reg(current,i,INVCP);
1645 #endif
b7918751 1646 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1647 alloc_reg(current,i,FTEMP);
1648 }
1649 // We need a temporary register for address generation
1650 alloc_reg_temp(current,i,-1);
1651}
1652
1653void c1ls_alloc(struct regstat *current,int i)
1654{
1655 //clear_const(current,rs1[i]); // FIXME
1656 clear_const(current,rt1[i]);
1657 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1658 alloc_reg(current,i,CSREG); // Status
1659 alloc_reg(current,i,FTEMP);
1660 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1661 alloc_reg64(current,i,FTEMP);
1662 }
1663 // If using TLB, need a register for pointer to the mapping table
1664 if(using_tlb) alloc_reg(current,i,TLREG);
1665 #if defined(HOST_IMM8)
1666 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1667 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1668 alloc_reg(current,i,INVCP);
1669 #endif
1670 // We need a temporary register for address generation
1671 alloc_reg_temp(current,i,-1);
1672}
1673
b9b61529 1674void c2ls_alloc(struct regstat *current,int i)
1675{
1676 clear_const(current,rt1[i]);
1677 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1678 alloc_reg(current,i,FTEMP);
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 #if defined(HOST_IMM8)
1682 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1684 alloc_reg(current,i,INVCP);
1685 #endif
1686 // We need a temporary register for address generation
1687 alloc_reg_temp(current,i,-1);
1688}
1689
57871462 1690#ifndef multdiv_alloc
1691void multdiv_alloc(struct regstat *current,int i)
1692{
1693 // case 0x18: MULT
1694 // case 0x19: MULTU
1695 // case 0x1A: DIV
1696 // case 0x1B: DIVU
1697 // case 0x1C: DMULT
1698 // case 0x1D: DMULTU
1699 // case 0x1E: DDIV
1700 // case 0x1F: DDIVU
1701 clear_const(current,rs1[i]);
1702 clear_const(current,rs2[i]);
1703 if(rs1[i]&&rs2[i])
1704 {
1705 if((opcode2[i]&4)==0) // 32-bit
1706 {
1707 current->u&=~(1LL<<HIREG);
1708 current->u&=~(1LL<<LOREG);
1709 alloc_reg(current,i,HIREG);
1710 alloc_reg(current,i,LOREG);
1711 alloc_reg(current,i,rs1[i]);
1712 alloc_reg(current,i,rs2[i]);
1713 current->is32|=1LL<<HIREG;
1714 current->is32|=1LL<<LOREG;
1715 dirty_reg(current,HIREG);
1716 dirty_reg(current,LOREG);
1717 }
1718 else // 64-bit
1719 {
1720 current->u&=~(1LL<<HIREG);
1721 current->u&=~(1LL<<LOREG);
1722 current->uu&=~(1LL<<HIREG);
1723 current->uu&=~(1LL<<LOREG);
1724 alloc_reg64(current,i,HIREG);
1725 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1726 alloc_reg64(current,i,rs1[i]);
1727 alloc_reg64(current,i,rs2[i]);
1728 alloc_all(current,i);
1729 current->is32&=~(1LL<<HIREG);
1730 current->is32&=~(1LL<<LOREG);
1731 dirty_reg(current,HIREG);
1732 dirty_reg(current,LOREG);
1733 }
1734 }
1735 else
1736 {
1737 // Multiply by zero is zero.
1738 // MIPS does not have a divide by zero exception.
1739 // The result is undefined, we return zero.
1740 alloc_reg(current,i,HIREG);
1741 alloc_reg(current,i,LOREG);
1742 current->is32|=1LL<<HIREG;
1743 current->is32|=1LL<<LOREG;
1744 dirty_reg(current,HIREG);
1745 dirty_reg(current,LOREG);
1746 }
1747}
1748#endif
1749
1750void cop0_alloc(struct regstat *current,int i)
1751{
1752 if(opcode2[i]==0) // MFC0
1753 {
1754 if(rt1[i]) {
1755 clear_const(current,rt1[i]);
1756 alloc_all(current,i);
1757 alloc_reg(current,i,rt1[i]);
1758 current->is32|=1LL<<rt1[i];
1759 dirty_reg(current,rt1[i]);
1760 }
1761 }
1762 else if(opcode2[i]==4) // MTC0
1763 {
1764 if(rs1[i]){
1765 clear_const(current,rs1[i]);
1766 alloc_reg(current,i,rs1[i]);
1767 alloc_all(current,i);
1768 }
1769 else {
1770 alloc_all(current,i); // FIXME: Keep r0
1771 current->u&=~1LL;
1772 alloc_reg(current,i,0);
1773 }
1774 }
1775 else
1776 {
1777 // TLBR/TLBWI/TLBWR/TLBP/ERET
1778 assert(opcode2[i]==0x10);
1779 alloc_all(current,i);
1780 }
1781}
1782
1783void cop1_alloc(struct regstat *current,int i)
1784{
1785 alloc_reg(current,i,CSREG); // Load status
1786 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1787 {
1788 assert(rt1[i]);
1789 clear_const(current,rt1[i]);
1790 if(opcode2[i]==1) {
1791 alloc_reg64(current,i,rt1[i]); // DMFC1
1792 current->is32&=~(1LL<<rt1[i]);
1793 }else{
1794 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1795 current->is32|=1LL<<rt1[i];
1796 }
1797 dirty_reg(current,rt1[i]);
1798 alloc_reg_temp(current,i,-1);
1799 }
1800 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1801 {
1802 if(rs1[i]){
1803 clear_const(current,rs1[i]);
1804 if(opcode2[i]==5)
1805 alloc_reg64(current,i,rs1[i]); // DMTC1
1806 else
1807 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1808 alloc_reg_temp(current,i,-1);
1809 }
1810 else {
1811 current->u&=~1LL;
1812 alloc_reg(current,i,0);
1813 alloc_reg_temp(current,i,-1);
1814 }
1815 }
1816}
1817void fconv_alloc(struct regstat *current,int i)
1818{
1819 alloc_reg(current,i,CSREG); // Load status
1820 alloc_reg_temp(current,i,-1);
1821}
1822void float_alloc(struct regstat *current,int i)
1823{
1824 alloc_reg(current,i,CSREG); // Load status
1825 alloc_reg_temp(current,i,-1);
1826}
b9b61529 1827void c2op_alloc(struct regstat *current,int i)
1828{
1829 alloc_reg_temp(current,i,-1);
1830}
57871462 1831void fcomp_alloc(struct regstat *current,int i)
1832{
1833 alloc_reg(current,i,CSREG); // Load status
1834 alloc_reg(current,i,FSREG); // Load flags
1835 dirty_reg(current,FSREG); // Flag will be modified
1836 alloc_reg_temp(current,i,-1);
1837}
1838
1839void syscall_alloc(struct regstat *current,int i)
1840{
1841 alloc_cc(current,i);
1842 dirty_reg(current,CCREG);
1843 alloc_all(current,i);
1844 current->isconst=0;
1845}
1846
1847void delayslot_alloc(struct regstat *current,int i)
1848{
1849 switch(itype[i]) {
1850 case UJUMP:
1851 case CJUMP:
1852 case SJUMP:
1853 case RJUMP:
1854 case FJUMP:
1855 case SYSCALL:
7139f3c8 1856 case HLECALL:
57871462 1857 case SPAN:
1858 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1859 printf("Disabled speculative precompilation\n");
1860 stop_after_jal=1;
1861 break;
1862 case IMM16:
1863 imm16_alloc(current,i);
1864 break;
1865 case LOAD:
1866 case LOADLR:
1867 load_alloc(current,i);
1868 break;
1869 case STORE:
1870 case STORELR:
1871 store_alloc(current,i);
1872 break;
1873 case ALU:
1874 alu_alloc(current,i);
1875 break;
1876 case SHIFT:
1877 shift_alloc(current,i);
1878 break;
1879 case MULTDIV:
1880 multdiv_alloc(current,i);
1881 break;
1882 case SHIFTIMM:
1883 shiftimm_alloc(current,i);
1884 break;
1885 case MOV:
1886 mov_alloc(current,i);
1887 break;
1888 case COP0:
1889 cop0_alloc(current,i);
1890 break;
1891 case COP1:
b9b61529 1892 case COP2:
57871462 1893 cop1_alloc(current,i);
1894 break;
1895 case C1LS:
1896 c1ls_alloc(current,i);
1897 break;
b9b61529 1898 case C2LS:
1899 c2ls_alloc(current,i);
1900 break;
57871462 1901 case FCONV:
1902 fconv_alloc(current,i);
1903 break;
1904 case FLOAT:
1905 float_alloc(current,i);
1906 break;
1907 case FCOMP:
1908 fcomp_alloc(current,i);
1909 break;
b9b61529 1910 case C2OP:
1911 c2op_alloc(current,i);
1912 break;
57871462 1913 }
1914}
1915
1916// Special case where a branch and delay slot span two pages in virtual memory
1917static void pagespan_alloc(struct regstat *current,int i)
1918{
1919 current->isconst=0;
1920 current->wasconst=0;
1921 regs[i].wasconst=0;
1922 alloc_all(current,i);
1923 alloc_cc(current,i);
1924 dirty_reg(current,CCREG);
1925 if(opcode[i]==3) // JAL
1926 {
1927 alloc_reg(current,i,31);
1928 dirty_reg(current,31);
1929 }
1930 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1931 {
1932 alloc_reg(current,i,rs1[i]);
5067f341 1933 if (rt1[i]!=0) {
1934 alloc_reg(current,i,rt1[i]);
1935 dirty_reg(current,rt1[i]);
57871462 1936 }
1937 }
1938 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1939 {
1940 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1941 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1942 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1943 {
1944 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1945 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1946 }
1947 }
1948 else
1949 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1950 {
1951 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1952 if(!((current->is32>>rs1[i])&1))
1953 {
1954 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1955 }
1956 }
1957 else
1958 if(opcode[i]==0x11) // BC1
1959 {
1960 alloc_reg(current,i,FSREG);
1961 alloc_reg(current,i,CSREG);
1962 }
1963 //else ...
1964}
1965
1966add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1967{
1968 stubs[stubcount][0]=type;
1969 stubs[stubcount][1]=addr;
1970 stubs[stubcount][2]=retaddr;
1971 stubs[stubcount][3]=a;
1972 stubs[stubcount][4]=b;
1973 stubs[stubcount][5]=c;
1974 stubs[stubcount][6]=d;
1975 stubs[stubcount][7]=e;
1976 stubcount++;
1977}
1978
1979// Write out a single register
1980void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1981{
1982 int hr;
1983 for(hr=0;hr<HOST_REGS;hr++) {
1984 if(hr!=EXCLUDE_REG) {
1985 if((regmap[hr]&63)==r) {
1986 if((dirty>>hr)&1) {
1987 if(regmap[hr]<64) {
1988 emit_storereg(r,hr);
24385cae 1989#ifndef FORCE32
57871462 1990 if((is32>>regmap[hr])&1) {
1991 emit_sarimm(hr,31,hr);
1992 emit_storereg(r|64,hr);
1993 }
24385cae 1994#endif
57871462 1995 }else{
1996 emit_storereg(r|64,hr);
1997 }
1998 }
1999 }
2000 }
2001 }
2002}
2003
2004int mchecksum()
2005{
2006 //if(!tracedebug) return 0;
2007 int i;
2008 int sum=0;
2009 for(i=0;i<2097152;i++) {
2010 unsigned int temp=sum;
2011 sum<<=1;
2012 sum|=(~temp)>>31;
2013 sum^=((u_int *)rdram)[i];
2014 }
2015 return sum;
2016}
2017int rchecksum()
2018{
2019 int i;
2020 int sum=0;
2021 for(i=0;i<64;i++)
2022 sum^=((u_int *)reg)[i];
2023 return sum;
2024}
57871462 2025void rlist()
2026{
2027 int i;
2028 printf("TRACE: ");
2029 for(i=0;i<32;i++)
2030 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2031 printf("\n");
3d624f89 2032#ifndef DISABLE_COP1
57871462 2033 printf("TRACE: ");
2034 for(i=0;i<32;i++)
2035 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2036 printf("\n");
3d624f89 2037#endif
57871462 2038}
2039
2040void enabletrace()
2041{
2042 tracedebug=1;
2043}
2044
2045void memdebug(int i)
2046{
2047 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2048 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2049 //rlist();
2050 //if(tracedebug) {
2051 //if(Count>=-2084597794) {
2052 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2053 //if(0) {
2054 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2055 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2056 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2057 rlist();
2058 #ifdef __i386__
2059 printf("TRACE: %x\n",(&i)[-1]);
2060 #endif
2061 #ifdef __arm__
2062 int j;
2063 printf("TRACE: %x \n",(&j)[10]);
2064 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2065 #endif
2066 //fflush(stdout);
2067 }
2068 //printf("TRACE: %x\n",(&i)[-1]);
2069}
2070
2071void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2072{
2073 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2074}
2075
2076void alu_assemble(int i,struct regstat *i_regs)
2077{
2078 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2079 if(rt1[i]) {
2080 signed char s1,s2,t;
2081 t=get_reg(i_regs->regmap,rt1[i]);
2082 if(t>=0) {
2083 s1=get_reg(i_regs->regmap,rs1[i]);
2084 s2=get_reg(i_regs->regmap,rs2[i]);
2085 if(rs1[i]&&rs2[i]) {
2086 assert(s1>=0);
2087 assert(s2>=0);
2088 if(opcode2[i]&2) emit_sub(s1,s2,t);
2089 else emit_add(s1,s2,t);
2090 }
2091 else if(rs1[i]) {
2092 if(s1>=0) emit_mov(s1,t);
2093 else emit_loadreg(rs1[i],t);
2094 }
2095 else if(rs2[i]) {
2096 if(s2>=0) {
2097 if(opcode2[i]&2) emit_neg(s2,t);
2098 else emit_mov(s2,t);
2099 }
2100 else {
2101 emit_loadreg(rs2[i],t);
2102 if(opcode2[i]&2) emit_neg(t,t);
2103 }
2104 }
2105 else emit_zeroreg(t);
2106 }
2107 }
2108 }
2109 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2110 if(rt1[i]) {
2111 signed char s1l,s2l,s1h,s2h,tl,th;
2112 tl=get_reg(i_regs->regmap,rt1[i]);
2113 th=get_reg(i_regs->regmap,rt1[i]|64);
2114 if(tl>=0) {
2115 s1l=get_reg(i_regs->regmap,rs1[i]);
2116 s2l=get_reg(i_regs->regmap,rs2[i]);
2117 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2118 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2119 if(rs1[i]&&rs2[i]) {
2120 assert(s1l>=0);
2121 assert(s2l>=0);
2122 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2123 else emit_adds(s1l,s2l,tl);
2124 if(th>=0) {
2125 #ifdef INVERTED_CARRY
2126 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2127 #else
2128 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2129 #endif
2130 else emit_add(s1h,s2h,th);
2131 }
2132 }
2133 else if(rs1[i]) {
2134 if(s1l>=0) emit_mov(s1l,tl);
2135 else emit_loadreg(rs1[i],tl);
2136 if(th>=0) {
2137 if(s1h>=0) emit_mov(s1h,th);
2138 else emit_loadreg(rs1[i]|64,th);
2139 }
2140 }
2141 else if(rs2[i]) {
2142 if(s2l>=0) {
2143 if(opcode2[i]&2) emit_negs(s2l,tl);
2144 else emit_mov(s2l,tl);
2145 }
2146 else {
2147 emit_loadreg(rs2[i],tl);
2148 if(opcode2[i]&2) emit_negs(tl,tl);
2149 }
2150 if(th>=0) {
2151 #ifdef INVERTED_CARRY
2152 if(s2h>=0) emit_mov(s2h,th);
2153 else emit_loadreg(rs2[i]|64,th);
2154 if(opcode2[i]&2) {
2155 emit_adcimm(-1,th); // x86 has inverted carry flag
2156 emit_not(th,th);
2157 }
2158 #else
2159 if(opcode2[i]&2) {
2160 if(s2h>=0) emit_rscimm(s2h,0,th);
2161 else {
2162 emit_loadreg(rs2[i]|64,th);
2163 emit_rscimm(th,0,th);
2164 }
2165 }else{
2166 if(s2h>=0) emit_mov(s2h,th);
2167 else emit_loadreg(rs2[i]|64,th);
2168 }
2169 #endif
2170 }
2171 }
2172 else {
2173 emit_zeroreg(tl);
2174 if(th>=0) emit_zeroreg(th);
2175 }
2176 }
2177 }
2178 }
2179 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2180 if(rt1[i]) {
2181 signed char s1l,s1h,s2l,s2h,t;
2182 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2183 {
2184 t=get_reg(i_regs->regmap,rt1[i]);
2185 //assert(t>=0);
2186 if(t>=0) {
2187 s1l=get_reg(i_regs->regmap,rs1[i]);
2188 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2189 s2l=get_reg(i_regs->regmap,rs2[i]);
2190 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2191 if(rs2[i]==0) // rx<r0
2192 {
2193 assert(s1h>=0);
2194 if(opcode2[i]==0x2a) // SLT
2195 emit_shrimm(s1h,31,t);
2196 else // SLTU (unsigned can not be less than zero)
2197 emit_zeroreg(t);
2198 }
2199 else if(rs1[i]==0) // r0<rx
2200 {
2201 assert(s2h>=0);
2202 if(opcode2[i]==0x2a) // SLT
2203 emit_set_gz64_32(s2h,s2l,t);
2204 else // SLTU (set if not zero)
2205 emit_set_nz64_32(s2h,s2l,t);
2206 }
2207 else {
2208 assert(s1l>=0);assert(s1h>=0);
2209 assert(s2l>=0);assert(s2h>=0);
2210 if(opcode2[i]==0x2a) // SLT
2211 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2212 else // SLTU
2213 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2214 }
2215 }
2216 } else {
2217 t=get_reg(i_regs->regmap,rt1[i]);
2218 //assert(t>=0);
2219 if(t>=0) {
2220 s1l=get_reg(i_regs->regmap,rs1[i]);
2221 s2l=get_reg(i_regs->regmap,rs2[i]);
2222 if(rs2[i]==0) // rx<r0
2223 {
2224 assert(s1l>=0);
2225 if(opcode2[i]==0x2a) // SLT
2226 emit_shrimm(s1l,31,t);
2227 else // SLTU (unsigned can not be less than zero)
2228 emit_zeroreg(t);
2229 }
2230 else if(rs1[i]==0) // r0<rx
2231 {
2232 assert(s2l>=0);
2233 if(opcode2[i]==0x2a) // SLT
2234 emit_set_gz32(s2l,t);
2235 else // SLTU (set if not zero)
2236 emit_set_nz32(s2l,t);
2237 }
2238 else{
2239 assert(s1l>=0);assert(s2l>=0);
2240 if(opcode2[i]==0x2a) // SLT
2241 emit_set_if_less32(s1l,s2l,t);
2242 else // SLTU
2243 emit_set_if_carry32(s1l,s2l,t);
2244 }
2245 }
2246 }
2247 }
2248 }
2249 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2250 if(rt1[i]) {
2251 signed char s1l,s1h,s2l,s2h,th,tl;
2252 tl=get_reg(i_regs->regmap,rt1[i]);
2253 th=get_reg(i_regs->regmap,rt1[i]|64);
2254 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2255 {
2256 assert(tl>=0);
2257 if(tl>=0) {
2258 s1l=get_reg(i_regs->regmap,rs1[i]);
2259 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2260 s2l=get_reg(i_regs->regmap,rs2[i]);
2261 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2262 if(rs1[i]&&rs2[i]) {
2263 assert(s1l>=0);assert(s1h>=0);
2264 assert(s2l>=0);assert(s2h>=0);
2265 if(opcode2[i]==0x24) { // AND
2266 emit_and(s1l,s2l,tl);
2267 emit_and(s1h,s2h,th);
2268 } else
2269 if(opcode2[i]==0x25) { // OR
2270 emit_or(s1l,s2l,tl);
2271 emit_or(s1h,s2h,th);
2272 } else
2273 if(opcode2[i]==0x26) { // XOR
2274 emit_xor(s1l,s2l,tl);
2275 emit_xor(s1h,s2h,th);
2276 } else
2277 if(opcode2[i]==0x27) { // NOR
2278 emit_or(s1l,s2l,tl);
2279 emit_or(s1h,s2h,th);
2280 emit_not(tl,tl);
2281 emit_not(th,th);
2282 }
2283 }
2284 else
2285 {
2286 if(opcode2[i]==0x24) { // AND
2287 emit_zeroreg(tl);
2288 emit_zeroreg(th);
2289 } else
2290 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2291 if(rs1[i]){
2292 if(s1l>=0) emit_mov(s1l,tl);
2293 else emit_loadreg(rs1[i],tl);
2294 if(s1h>=0) emit_mov(s1h,th);
2295 else emit_loadreg(rs1[i]|64,th);
2296 }
2297 else
2298 if(rs2[i]){
2299 if(s2l>=0) emit_mov(s2l,tl);
2300 else emit_loadreg(rs2[i],tl);
2301 if(s2h>=0) emit_mov(s2h,th);
2302 else emit_loadreg(rs2[i]|64,th);
2303 }
2304 else{
2305 emit_zeroreg(tl);
2306 emit_zeroreg(th);
2307 }
2308 } else
2309 if(opcode2[i]==0x27) { // NOR
2310 if(rs1[i]){
2311 if(s1l>=0) emit_not(s1l,tl);
2312 else{
2313 emit_loadreg(rs1[i],tl);
2314 emit_not(tl,tl);
2315 }
2316 if(s1h>=0) emit_not(s1h,th);
2317 else{
2318 emit_loadreg(rs1[i]|64,th);
2319 emit_not(th,th);
2320 }
2321 }
2322 else
2323 if(rs2[i]){
2324 if(s2l>=0) emit_not(s2l,tl);
2325 else{
2326 emit_loadreg(rs2[i],tl);
2327 emit_not(tl,tl);
2328 }
2329 if(s2h>=0) emit_not(s2h,th);
2330 else{
2331 emit_loadreg(rs2[i]|64,th);
2332 emit_not(th,th);
2333 }
2334 }
2335 else {
2336 emit_movimm(-1,tl);
2337 emit_movimm(-1,th);
2338 }
2339 }
2340 }
2341 }
2342 }
2343 else
2344 {
2345 // 32 bit
2346 if(tl>=0) {
2347 s1l=get_reg(i_regs->regmap,rs1[i]);
2348 s2l=get_reg(i_regs->regmap,rs2[i]);
2349 if(rs1[i]&&rs2[i]) {
2350 assert(s1l>=0);
2351 assert(s2l>=0);
2352 if(opcode2[i]==0x24) { // AND
2353 emit_and(s1l,s2l,tl);
2354 } else
2355 if(opcode2[i]==0x25) { // OR
2356 emit_or(s1l,s2l,tl);
2357 } else
2358 if(opcode2[i]==0x26) { // XOR
2359 emit_xor(s1l,s2l,tl);
2360 } else
2361 if(opcode2[i]==0x27) { // NOR
2362 emit_or(s1l,s2l,tl);
2363 emit_not(tl,tl);
2364 }
2365 }
2366 else
2367 {
2368 if(opcode2[i]==0x24) { // AND
2369 emit_zeroreg(tl);
2370 } else
2371 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2372 if(rs1[i]){
2373 if(s1l>=0) emit_mov(s1l,tl);
2374 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2375 }
2376 else
2377 if(rs2[i]){
2378 if(s2l>=0) emit_mov(s2l,tl);
2379 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2380 }
2381 else emit_zeroreg(tl);
2382 } else
2383 if(opcode2[i]==0x27) { // NOR
2384 if(rs1[i]){
2385 if(s1l>=0) emit_not(s1l,tl);
2386 else {
2387 emit_loadreg(rs1[i],tl);
2388 emit_not(tl,tl);
2389 }
2390 }
2391 else
2392 if(rs2[i]){
2393 if(s2l>=0) emit_not(s2l,tl);
2394 else {
2395 emit_loadreg(rs2[i],tl);
2396 emit_not(tl,tl);
2397 }
2398 }
2399 else emit_movimm(-1,tl);
2400 }
2401 }
2402 }
2403 }
2404 }
2405 }
2406}
2407
2408void imm16_assemble(int i,struct regstat *i_regs)
2409{
2410 if (opcode[i]==0x0f) { // LUI
2411 if(rt1[i]) {
2412 signed char t;
2413 t=get_reg(i_regs->regmap,rt1[i]);
2414 //assert(t>=0);
2415 if(t>=0) {
2416 if(!((i_regs->isconst>>t)&1))
2417 emit_movimm(imm[i]<<16,t);
2418 }
2419 }
2420 }
2421 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2422 if(rt1[i]) {
2423 signed char s,t;
2424 t=get_reg(i_regs->regmap,rt1[i]);
2425 s=get_reg(i_regs->regmap,rs1[i]);
2426 if(rs1[i]) {
2427 //assert(t>=0);
2428 //assert(s>=0);
2429 if(t>=0) {
2430 if(!((i_regs->isconst>>t)&1)) {
2431 if(s<0) {
2432 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2433 emit_addimm(t,imm[i],t);
2434 }else{
2435 if(!((i_regs->wasconst>>s)&1))
2436 emit_addimm(s,imm[i],t);
2437 else
2438 emit_movimm(constmap[i][s]+imm[i],t);
2439 }
2440 }
2441 }
2442 } else {
2443 if(t>=0) {
2444 if(!((i_regs->isconst>>t)&1))
2445 emit_movimm(imm[i],t);
2446 }
2447 }
2448 }
2449 }
2450 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2451 if(rt1[i]) {
2452 signed char sh,sl,th,tl;
2453 th=get_reg(i_regs->regmap,rt1[i]|64);
2454 tl=get_reg(i_regs->regmap,rt1[i]);
2455 sh=get_reg(i_regs->regmap,rs1[i]|64);
2456 sl=get_reg(i_regs->regmap,rs1[i]);
2457 if(tl>=0) {
2458 if(rs1[i]) {
2459 assert(sh>=0);
2460 assert(sl>=0);
2461 if(th>=0) {
2462 emit_addimm64_32(sh,sl,imm[i],th,tl);
2463 }
2464 else {
2465 emit_addimm(sl,imm[i],tl);
2466 }
2467 } else {
2468 emit_movimm(imm[i],tl);
2469 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2470 }
2471 }
2472 }
2473 }
2474 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2475 if(rt1[i]) {
2476 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2477 signed char sh,sl,t;
2478 t=get_reg(i_regs->regmap,rt1[i]);
2479 sh=get_reg(i_regs->regmap,rs1[i]|64);
2480 sl=get_reg(i_regs->regmap,rs1[i]);
2481 //assert(t>=0);
2482 if(t>=0) {
2483 if(rs1[i]>0) {
2484 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2485 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2486 if(opcode[i]==0x0a) { // SLTI
2487 if(sl<0) {
2488 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2489 emit_slti32(t,imm[i],t);
2490 }else{
2491 emit_slti32(sl,imm[i],t);
2492 }
2493 }
2494 else { // SLTIU
2495 if(sl<0) {
2496 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2497 emit_sltiu32(t,imm[i],t);
2498 }else{
2499 emit_sltiu32(sl,imm[i],t);
2500 }
2501 }
2502 }else{ // 64-bit
2503 assert(sl>=0);
2504 if(opcode[i]==0x0a) // SLTI
2505 emit_slti64_32(sh,sl,imm[i],t);
2506 else // SLTIU
2507 emit_sltiu64_32(sh,sl,imm[i],t);
2508 }
2509 }else{
2510 // SLTI(U) with r0 is just stupid,
2511 // nonetheless examples can be found
2512 if(opcode[i]==0x0a) // SLTI
2513 if(0<imm[i]) emit_movimm(1,t);
2514 else emit_zeroreg(t);
2515 else // SLTIU
2516 {
2517 if(imm[i]) emit_movimm(1,t);
2518 else emit_zeroreg(t);
2519 }
2520 }
2521 }
2522 }
2523 }
2524 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2525 if(rt1[i]) {
2526 signed char sh,sl,th,tl;
2527 th=get_reg(i_regs->regmap,rt1[i]|64);
2528 tl=get_reg(i_regs->regmap,rt1[i]);
2529 sh=get_reg(i_regs->regmap,rs1[i]|64);
2530 sl=get_reg(i_regs->regmap,rs1[i]);
2531 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2532 if(opcode[i]==0x0c) //ANDI
2533 {
2534 if(rs1[i]) {
2535 if(sl<0) {
2536 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2537 emit_andimm(tl,imm[i],tl);
2538 }else{
2539 if(!((i_regs->wasconst>>sl)&1))
2540 emit_andimm(sl,imm[i],tl);
2541 else
2542 emit_movimm(constmap[i][sl]&imm[i],tl);
2543 }
2544 }
2545 else
2546 emit_zeroreg(tl);
2547 if(th>=0) emit_zeroreg(th);
2548 }
2549 else
2550 {
2551 if(rs1[i]) {
2552 if(sl<0) {
2553 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2554 }
2555 if(th>=0) {
2556 if(sh<0) {
2557 emit_loadreg(rs1[i]|64,th);
2558 }else{
2559 emit_mov(sh,th);
2560 }
2561 }
2562 if(opcode[i]==0x0d) //ORI
2563 if(sl<0) {
2564 emit_orimm(tl,imm[i],tl);
2565 }else{
2566 if(!((i_regs->wasconst>>sl)&1))
2567 emit_orimm(sl,imm[i],tl);
2568 else
2569 emit_movimm(constmap[i][sl]|imm[i],tl);
2570 }
2571 if(opcode[i]==0x0e) //XORI
2572 if(sl<0) {
2573 emit_xorimm(tl,imm[i],tl);
2574 }else{
2575 if(!((i_regs->wasconst>>sl)&1))
2576 emit_xorimm(sl,imm[i],tl);
2577 else
2578 emit_movimm(constmap[i][sl]^imm[i],tl);
2579 }
2580 }
2581 else {
2582 emit_movimm(imm[i],tl);
2583 if(th>=0) emit_zeroreg(th);
2584 }
2585 }
2586 }
2587 }
2588 }
2589}
2590
2591void shiftimm_assemble(int i,struct regstat *i_regs)
2592{
2593 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2594 {
2595 if(rt1[i]) {
2596 signed char s,t;
2597 t=get_reg(i_regs->regmap,rt1[i]);
2598 s=get_reg(i_regs->regmap,rs1[i]);
2599 //assert(t>=0);
2600 if(t>=0){
2601 if(rs1[i]==0)
2602 {
2603 emit_zeroreg(t);
2604 }
2605 else
2606 {
2607 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2608 if(imm[i]) {
2609 if(opcode2[i]==0) // SLL
2610 {
2611 emit_shlimm(s<0?t:s,imm[i],t);
2612 }
2613 if(opcode2[i]==2) // SRL
2614 {
2615 emit_shrimm(s<0?t:s,imm[i],t);
2616 }
2617 if(opcode2[i]==3) // SRA
2618 {
2619 emit_sarimm(s<0?t:s,imm[i],t);
2620 }
2621 }else{
2622 // Shift by zero
2623 if(s>=0 && s!=t) emit_mov(s,t);
2624 }
2625 }
2626 }
2627 //emit_storereg(rt1[i],t); //DEBUG
2628 }
2629 }
2630 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2631 {
2632 if(rt1[i]) {
2633 signed char sh,sl,th,tl;
2634 th=get_reg(i_regs->regmap,rt1[i]|64);
2635 tl=get_reg(i_regs->regmap,rt1[i]);
2636 sh=get_reg(i_regs->regmap,rs1[i]|64);
2637 sl=get_reg(i_regs->regmap,rs1[i]);
2638 if(tl>=0) {
2639 if(rs1[i]==0)
2640 {
2641 emit_zeroreg(tl);
2642 if(th>=0) emit_zeroreg(th);
2643 }
2644 else
2645 {
2646 assert(sl>=0);
2647 assert(sh>=0);
2648 if(imm[i]) {
2649 if(opcode2[i]==0x38) // DSLL
2650 {
2651 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2652 emit_shlimm(sl,imm[i],tl);
2653 }
2654 if(opcode2[i]==0x3a) // DSRL
2655 {
2656 emit_shrdimm(sl,sh,imm[i],tl);
2657 if(th>=0) emit_shrimm(sh,imm[i],th);
2658 }
2659 if(opcode2[i]==0x3b) // DSRA
2660 {
2661 emit_shrdimm(sl,sh,imm[i],tl);
2662 if(th>=0) emit_sarimm(sh,imm[i],th);
2663 }
2664 }else{
2665 // Shift by zero
2666 if(sl!=tl) emit_mov(sl,tl);
2667 if(th>=0&&sh!=th) emit_mov(sh,th);
2668 }
2669 }
2670 }
2671 }
2672 }
2673 if(opcode2[i]==0x3c) // DSLL32
2674 {
2675 if(rt1[i]) {
2676 signed char sl,tl,th;
2677 tl=get_reg(i_regs->regmap,rt1[i]);
2678 th=get_reg(i_regs->regmap,rt1[i]|64);
2679 sl=get_reg(i_regs->regmap,rs1[i]);
2680 if(th>=0||tl>=0){
2681 assert(tl>=0);
2682 assert(th>=0);
2683 assert(sl>=0);
2684 emit_mov(sl,th);
2685 emit_zeroreg(tl);
2686 if(imm[i]>32)
2687 {
2688 emit_shlimm(th,imm[i]&31,th);
2689 }
2690 }
2691 }
2692 }
2693 if(opcode2[i]==0x3e) // DSRL32
2694 {
2695 if(rt1[i]) {
2696 signed char sh,tl,th;
2697 tl=get_reg(i_regs->regmap,rt1[i]);
2698 th=get_reg(i_regs->regmap,rt1[i]|64);
2699 sh=get_reg(i_regs->regmap,rs1[i]|64);
2700 if(tl>=0){
2701 assert(sh>=0);
2702 emit_mov(sh,tl);
2703 if(th>=0) emit_zeroreg(th);
2704 if(imm[i]>32)
2705 {
2706 emit_shrimm(tl,imm[i]&31,tl);
2707 }
2708 }
2709 }
2710 }
2711 if(opcode2[i]==0x3f) // DSRA32
2712 {
2713 if(rt1[i]) {
2714 signed char sh,tl;
2715 tl=get_reg(i_regs->regmap,rt1[i]);
2716 sh=get_reg(i_regs->regmap,rs1[i]|64);
2717 if(tl>=0){
2718 assert(sh>=0);
2719 emit_mov(sh,tl);
2720 if(imm[i]>32)
2721 {
2722 emit_sarimm(tl,imm[i]&31,tl);
2723 }
2724 }
2725 }
2726 }
2727}
2728
2729#ifndef shift_assemble
2730void shift_assemble(int i,struct regstat *i_regs)
2731{
2732 printf("Need shift_assemble for this architecture.\n");
2733 exit(1);
2734}
2735#endif
2736
2737void load_assemble(int i,struct regstat *i_regs)
2738{
2739 int s,th,tl,addr,map=-1;
2740 int offset;
2741 int jaddr=0;
5bf843dc 2742 int memtarget=0,c=0;
57871462 2743 u_int hr,reglist=0;
2744 th=get_reg(i_regs->regmap,rt1[i]|64);
2745 tl=get_reg(i_regs->regmap,rt1[i]);
2746 s=get_reg(i_regs->regmap,rs1[i]);
2747 offset=imm[i];
2748 for(hr=0;hr<HOST_REGS;hr++) {
2749 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2750 }
2751 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2752 if(s>=0) {
2753 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2754 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2755 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2756 }
57871462 2757 //printf("load_assemble: c=%d\n",c);
2758 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2759 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2760#ifdef PCSX
f18c0f46 2761 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2762 ||rt1[i]==0) {
5bf843dc 2763 // could be FIFO, must perform the read
f18c0f46 2764 // ||dummy read
5bf843dc 2765 assem_debug("(forced read)\n");
2766 tl=get_reg(i_regs->regmap,-1);
2767 assert(tl>=0);
5bf843dc 2768 }
f18c0f46 2769#endif
5bf843dc 2770 if(offset||s<0||c) addr=tl;
2771 else addr=s;
57871462 2772 if(tl>=0) {
2773 //assert(tl>=0);
2774 //assert(rt1[i]);
2775 reglist&=~(1<<tl);
2776 if(th>=0) reglist&=~(1<<th);
2777 if(!using_tlb) {
2778 if(!c) {
2779//#define R29_HACK 1
2780 #ifdef R29_HACK
2781 // Strmnnrmn's speed hack
4cb76aa4 2782 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 2783 #endif
2784 {
4cb76aa4 2785 emit_cmpimm(addr,RAM_SIZE);
57871462 2786 jaddr=(int)out;
2787 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2788 // Hint to branch predictor that the branch is unlikely to be taken
2789 if(rs1[i]>=28)
2790 emit_jno_unlikely(0);
2791 else
2792 #endif
2793 emit_jno(0);
2794 }
2795 }
2796 }else{ // using tlb
2797 int x=0;
2798 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2799 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2800 map=get_reg(i_regs->regmap,TLREG);
2801 assert(map>=0);
2802 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2803 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2804 }
2805 if (opcode[i]==0x20) { // LB
2806 if(!c||memtarget) {
2807 #ifdef HOST_IMM_ADDR32
2808 if(c)
2809 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2810 else
2811 #endif
2812 {
2813 //emit_xorimm(addr,3,tl);
2814 //gen_tlb_addr_r(tl,map);
2815 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2816 int x=0;
2002a1db 2817#ifdef BIG_ENDIAN_MIPS
57871462 2818 if(!c) emit_xorimm(addr,3,tl);
2819 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2820#else
2821 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2822 else if (tl!=addr) emit_mov(addr,tl);
2823#endif
57871462 2824 emit_movsbl_indexed_tlb(x,tl,map,tl);
2825 }
2826 if(jaddr)
2827 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2828 }
2829 else
2830 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2831 }
2832 if (opcode[i]==0x21) { // LH
2833 if(!c||memtarget) {
2834 #ifdef HOST_IMM_ADDR32
2835 if(c)
2836 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2837 else
2838 #endif
2839 {
2840 int x=0;
2002a1db 2841#ifdef BIG_ENDIAN_MIPS
57871462 2842 if(!c) emit_xorimm(addr,2,tl);
2843 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2844#else
2845 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2846 else if (tl!=addr) emit_mov(addr,tl);
2847#endif
57871462 2848 //#ifdef
2849 //emit_movswl_indexed_tlb(x,tl,map,tl);
2850 //else
2851 if(map>=0) {
2852 gen_tlb_addr_r(tl,map);
2853 emit_movswl_indexed(x,tl,tl);
2854 }else
2855 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2856 }
2857 if(jaddr)
2858 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2859 }
2860 else
2861 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2862 }
2863 if (opcode[i]==0x23) { // LW
2864 if(!c||memtarget) {
2865 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2866 #ifdef HOST_IMM_ADDR32
2867 if(c)
2868 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2869 else
2870 #endif
2871 emit_readword_indexed_tlb(0,addr,map,tl);
2872 if(jaddr)
2873 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2874 }
2875 else
2876 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877 }
2878 if (opcode[i]==0x24) { // LBU
2879 if(!c||memtarget) {
2880 #ifdef HOST_IMM_ADDR32
2881 if(c)
2882 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2883 else
2884 #endif
2885 {
2886 //emit_xorimm(addr,3,tl);
2887 //gen_tlb_addr_r(tl,map);
2888 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2889 int x=0;
2002a1db 2890#ifdef BIG_ENDIAN_MIPS
57871462 2891 if(!c) emit_xorimm(addr,3,tl);
2892 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2893#else
2894 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2895 else if (tl!=addr) emit_mov(addr,tl);
2896#endif
57871462 2897 emit_movzbl_indexed_tlb(x,tl,map,tl);
2898 }
2899 if(jaddr)
2900 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2901 }
2902 else
2903 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 }
2905 if (opcode[i]==0x25) { // LHU
2906 if(!c||memtarget) {
2907 #ifdef HOST_IMM_ADDR32
2908 if(c)
2909 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2910 else
2911 #endif
2912 {
2913 int x=0;
2002a1db 2914#ifdef BIG_ENDIAN_MIPS
57871462 2915 if(!c) emit_xorimm(addr,2,tl);
2916 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2917#else
2918 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2919 else if (tl!=addr) emit_mov(addr,tl);
2920#endif
57871462 2921 //#ifdef
2922 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2923 //#else
2924 if(map>=0) {
2925 gen_tlb_addr_r(tl,map);
2926 emit_movzwl_indexed(x,tl,tl);
2927 }else
2928 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2929 if(jaddr)
2930 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2931 }
2932 }
2933 else
2934 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2935 }
2936 if (opcode[i]==0x27) { // LWU
2937 assert(th>=0);
2938 if(!c||memtarget) {
2939 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2940 #ifdef HOST_IMM_ADDR32
2941 if(c)
2942 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2943 else
2944 #endif
2945 emit_readword_indexed_tlb(0,addr,map,tl);
2946 if(jaddr)
2947 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948 }
2949 else {
2950 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951 }
2952 emit_zeroreg(th);
2953 }
2954 if (opcode[i]==0x37) { // LD
2955 if(!c||memtarget) {
2956 //gen_tlb_addr_r(tl,map);
2957 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2958 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2959 #ifdef HOST_IMM_ADDR32
2960 if(c)
2961 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2962 else
2963 #endif
2964 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2965 if(jaddr)
2966 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2967 }
2968 else
2969 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2970 }
2971 //emit_storereg(rt1[i],tl); // DEBUG
2972 }
2973 //if(opcode[i]==0x23)
2974 //if(opcode[i]==0x24)
2975 //if(opcode[i]==0x23||opcode[i]==0x24)
2976 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2977 {
2978 //emit_pusha();
2979 save_regs(0x100f);
2980 emit_readword((int)&last_count,ECX);
2981 #ifdef __i386__
2982 if(get_reg(i_regs->regmap,CCREG)<0)
2983 emit_loadreg(CCREG,HOST_CCREG);
2984 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2985 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2986 emit_writeword(HOST_CCREG,(int)&Count);
2987 #endif
2988 #ifdef __arm__
2989 if(get_reg(i_regs->regmap,CCREG)<0)
2990 emit_loadreg(CCREG,0);
2991 else
2992 emit_mov(HOST_CCREG,0);
2993 emit_add(0,ECX,0);
2994 emit_addimm(0,2*ccadj[i],0);
2995 emit_writeword(0,(int)&Count);
2996 #endif
2997 emit_call((int)memdebug);
2998 //emit_popa();
2999 restore_regs(0x100f);
3000 }/**/
3001}
3002
3003#ifndef loadlr_assemble
3004void loadlr_assemble(int i,struct regstat *i_regs)
3005{
3006 printf("Need loadlr_assemble for this architecture.\n");
3007 exit(1);
3008}
3009#endif
3010
3011void store_assemble(int i,struct regstat *i_regs)
3012{
3013 int s,th,tl,map=-1;
3014 int addr,temp;
3015 int offset;
3016 int jaddr=0,jaddr2,type;
666a299d 3017 int memtarget=0,c=0;
57871462 3018 int agr=AGEN1+(i&1);
3019 u_int hr,reglist=0;
3020 th=get_reg(i_regs->regmap,rs2[i]|64);
3021 tl=get_reg(i_regs->regmap,rs2[i]);
3022 s=get_reg(i_regs->regmap,rs1[i]);
3023 temp=get_reg(i_regs->regmap,agr);
3024 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3025 offset=imm[i];
3026 if(s>=0) {
3027 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3028 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3029 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3030 }
3031 assert(tl>=0);
3032 assert(temp>=0);
3033 for(hr=0;hr<HOST_REGS;hr++) {
3034 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3035 }
3036 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3037 if(offset||s<0||c) addr=temp;
3038 else addr=s;
3039 if(!using_tlb) {
3040 if(!c) {
3041 #ifdef R29_HACK
3042 // Strmnnrmn's speed hack
3043 memtarget=1;
4cb76aa4 3044 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3045 #endif
4cb76aa4 3046 emit_cmpimm(addr,RAM_SIZE);
57871462 3047 #ifdef DESTRUCTIVE_SHIFT
3048 if(s==addr) emit_mov(s,temp);
3049 #endif
3050 #ifdef R29_HACK
4cb76aa4 3051 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3052 #endif
3053 {
3054 jaddr=(int)out;
3055 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3056 // Hint to branch predictor that the branch is unlikely to be taken
3057 if(rs1[i]>=28)
3058 emit_jno_unlikely(0);
3059 else
3060 #endif
3061 emit_jno(0);
3062 }
3063 }
3064 }else{ // using tlb
3065 int x=0;
3066 if (opcode[i]==0x28) x=3; // SB
3067 if (opcode[i]==0x29) x=2; // SH
3068 map=get_reg(i_regs->regmap,TLREG);
3069 assert(map>=0);
3070 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3071 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3072 }
3073
3074 if (opcode[i]==0x28) { // SB
3075 if(!c||memtarget) {
3076 int x=0;
2002a1db 3077#ifdef BIG_ENDIAN_MIPS
57871462 3078 if(!c) emit_xorimm(addr,3,temp);
3079 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3080#else
3081 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3082 else if (addr!=temp) emit_mov(addr,temp);
3083#endif
57871462 3084 //gen_tlb_addr_w(temp,map);
3085 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3086 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3087 }
3088 type=STOREB_STUB;
3089 }
3090 if (opcode[i]==0x29) { // SH
3091 if(!c||memtarget) {
3092 int x=0;
2002a1db 3093#ifdef BIG_ENDIAN_MIPS
57871462 3094 if(!c) emit_xorimm(addr,2,temp);
3095 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3096#else
3097 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3098 else if (addr!=temp) emit_mov(addr,temp);
3099#endif
57871462 3100 //#ifdef
3101 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3102 //#else
3103 if(map>=0) {
3104 gen_tlb_addr_w(temp,map);
3105 emit_writehword_indexed(tl,x,temp);
3106 }else
3107 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3108 }
3109 type=STOREH_STUB;
3110 }
3111 if (opcode[i]==0x2B) { // SW
3112 if(!c||memtarget)
3113 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3114 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3115 type=STOREW_STUB;
3116 }
3117 if (opcode[i]==0x3F) { // SD
3118 if(!c||memtarget) {
3119 if(rs2[i]) {
3120 assert(th>=0);
3121 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3122 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3123 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3124 }else{
3125 // Store zero
3126 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3127 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3128 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3129 }
3130 }
3131 type=STORED_STUB;
3132 }
666a299d 3133 if(!using_tlb&&(!c||memtarget))
3134 // addr could be a temp, make sure it survives STORE*_STUB
3135 reglist|=1<<addr;
57871462 3136 if(jaddr) {
3137 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3138 } else if(!memtarget) {
3139 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3140 }
3141 if(!using_tlb) {
3142 if(!c||memtarget) {
3143 #ifdef DESTRUCTIVE_SHIFT
3144 // The x86 shift operation is 'destructive'; it overwrites the
3145 // source register, so we need to make a copy first and use that.
3146 addr=temp;
3147 #endif
3148 #if defined(HOST_IMM8)
3149 int ir=get_reg(i_regs->regmap,INVCP);
3150 assert(ir>=0);
3151 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3152 #else
3153 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3154 #endif
3155 jaddr2=(int)out;
3156 emit_jne(0);
3157 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3158 }
3159 }
3160 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3161 //if(opcode[i]==0x2B || opcode[i]==0x28)
3162 //if(opcode[i]==0x2B || opcode[i]==0x29)
3163 //if(opcode[i]==0x2B)
3164 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3165 {
3166 //emit_pusha();
3167 save_regs(0x100f);
3168 emit_readword((int)&last_count,ECX);
3169 #ifdef __i386__
3170 if(get_reg(i_regs->regmap,CCREG)<0)
3171 emit_loadreg(CCREG,HOST_CCREG);
3172 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3173 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3174 emit_writeword(HOST_CCREG,(int)&Count);
3175 #endif
3176 #ifdef __arm__
3177 if(get_reg(i_regs->regmap,CCREG)<0)
3178 emit_loadreg(CCREG,0);
3179 else
3180 emit_mov(HOST_CCREG,0);
3181 emit_add(0,ECX,0);
3182 emit_addimm(0,2*ccadj[i],0);
3183 emit_writeword(0,(int)&Count);
3184 #endif
3185 emit_call((int)memdebug);
3186 //emit_popa();
3187 restore_regs(0x100f);
3188 }/**/
3189}
3190
3191void storelr_assemble(int i,struct regstat *i_regs)
3192{
3193 int s,th,tl;
3194 int temp;
3195 int temp2;
3196 int offset;
3197 int jaddr=0,jaddr2;
3198 int case1,case2,case3;
3199 int done0,done1,done2;
3200 int memtarget,c=0;
fab5d06d 3201 int agr=AGEN1+(i&1);
57871462 3202 u_int hr,reglist=0;
3203 th=get_reg(i_regs->regmap,rs2[i]|64);
3204 tl=get_reg(i_regs->regmap,rs2[i]);
3205 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3206 temp=get_reg(i_regs->regmap,agr);
3207 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3208 offset=imm[i];
3209 if(s>=0) {
3210 c=(i_regs->isconst>>s)&1;
4cb76aa4 3211 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3212 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3213 }
3214 assert(tl>=0);
3215 for(hr=0;hr<HOST_REGS;hr++) {
3216 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3217 }
3218 if(tl>=0) {
3219 assert(temp>=0);
3220 if(!using_tlb) {
3221 if(!c) {
4cb76aa4 3222 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
57871462 3223 if(!offset&&s!=temp) emit_mov(s,temp);
3224 jaddr=(int)out;
3225 emit_jno(0);
3226 }
3227 else
3228 {
3229 if(!memtarget||!rs1[i]) {
3230 jaddr=(int)out;
3231 emit_jmp(0);
3232 }
3233 }
3234 if((u_int)rdram!=0x80000000)
3235 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3236 }else{ // using tlb
3237 int map=get_reg(i_regs->regmap,TLREG);
3238 assert(map>=0);
3239 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3240 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3241 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3242 if(!jaddr&&!memtarget) {
3243 jaddr=(int)out;
3244 emit_jmp(0);
3245 }
3246 gen_tlb_addr_w(temp,map);
3247 }
3248
3249 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3250 temp2=get_reg(i_regs->regmap,FTEMP);
3251 if(!rs2[i]) temp2=th=tl;
3252 }
3253
2002a1db 3254#ifndef BIG_ENDIAN_MIPS
3255 emit_xorimm(temp,3,temp);
3256#endif
57871462 3257 emit_testimm(temp,2);
3258 case2=(int)out;
3259 emit_jne(0);
3260 emit_testimm(temp,1);
3261 case1=(int)out;
3262 emit_jne(0);
3263 // 0
3264 if (opcode[i]==0x2A) { // SWL
3265 emit_writeword_indexed(tl,0,temp);
3266 }
3267 if (opcode[i]==0x2E) { // SWR
3268 emit_writebyte_indexed(tl,3,temp);
3269 }
3270 if (opcode[i]==0x2C) { // SDL
3271 emit_writeword_indexed(th,0,temp);
3272 if(rs2[i]) emit_mov(tl,temp2);
3273 }
3274 if (opcode[i]==0x2D) { // SDR
3275 emit_writebyte_indexed(tl,3,temp);
3276 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3277 }
3278 done0=(int)out;
3279 emit_jmp(0);
3280 // 1
3281 set_jump_target(case1,(int)out);
3282 if (opcode[i]==0x2A) { // SWL
3283 // Write 3 msb into three least significant bytes
3284 if(rs2[i]) emit_rorimm(tl,8,tl);
3285 emit_writehword_indexed(tl,-1,temp);
3286 if(rs2[i]) emit_rorimm(tl,16,tl);
3287 emit_writebyte_indexed(tl,1,temp);
3288 if(rs2[i]) emit_rorimm(tl,8,tl);
3289 }
3290 if (opcode[i]==0x2E) { // SWR
3291 // Write two lsb into two most significant bytes
3292 emit_writehword_indexed(tl,1,temp);
3293 }
3294 if (opcode[i]==0x2C) { // SDL
3295 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3296 // Write 3 msb into three least significant bytes
3297 if(rs2[i]) emit_rorimm(th,8,th);
3298 emit_writehword_indexed(th,-1,temp);
3299 if(rs2[i]) emit_rorimm(th,16,th);
3300 emit_writebyte_indexed(th,1,temp);
3301 if(rs2[i]) emit_rorimm(th,8,th);
3302 }
3303 if (opcode[i]==0x2D) { // SDR
3304 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3305 // Write two lsb into two most significant bytes
3306 emit_writehword_indexed(tl,1,temp);
3307 }
3308 done1=(int)out;
3309 emit_jmp(0);
3310 // 2
3311 set_jump_target(case2,(int)out);
3312 emit_testimm(temp,1);
3313 case3=(int)out;
3314 emit_jne(0);
3315 if (opcode[i]==0x2A) { // SWL
3316 // Write two msb into two least significant bytes
3317 if(rs2[i]) emit_rorimm(tl,16,tl);
3318 emit_writehword_indexed(tl,-2,temp);
3319 if(rs2[i]) emit_rorimm(tl,16,tl);
3320 }
3321 if (opcode[i]==0x2E) { // SWR
3322 // Write 3 lsb into three most significant bytes
3323 emit_writebyte_indexed(tl,-1,temp);
3324 if(rs2[i]) emit_rorimm(tl,8,tl);
3325 emit_writehword_indexed(tl,0,temp);
3326 if(rs2[i]) emit_rorimm(tl,24,tl);
3327 }
3328 if (opcode[i]==0x2C) { // SDL
3329 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3330 // Write two msb into two least significant bytes
3331 if(rs2[i]) emit_rorimm(th,16,th);
3332 emit_writehword_indexed(th,-2,temp);
3333 if(rs2[i]) emit_rorimm(th,16,th);
3334 }
3335 if (opcode[i]==0x2D) { // SDR
3336 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3337 // Write 3 lsb into three most significant bytes
3338 emit_writebyte_indexed(tl,-1,temp);
3339 if(rs2[i]) emit_rorimm(tl,8,tl);
3340 emit_writehword_indexed(tl,0,temp);
3341 if(rs2[i]) emit_rorimm(tl,24,tl);
3342 }
3343 done2=(int)out;
3344 emit_jmp(0);
3345 // 3
3346 set_jump_target(case3,(int)out);
3347 if (opcode[i]==0x2A) { // SWL
3348 // Write msb into least significant byte
3349 if(rs2[i]) emit_rorimm(tl,24,tl);
3350 emit_writebyte_indexed(tl,-3,temp);
3351 if(rs2[i]) emit_rorimm(tl,8,tl);
3352 }
3353 if (opcode[i]==0x2E) { // SWR
3354 // Write entire word
3355 emit_writeword_indexed(tl,-3,temp);
3356 }
3357 if (opcode[i]==0x2C) { // SDL
3358 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3359 // Write msb into least significant byte
3360 if(rs2[i]) emit_rorimm(th,24,th);
3361 emit_writebyte_indexed(th,-3,temp);
3362 if(rs2[i]) emit_rorimm(th,8,th);
3363 }
3364 if (opcode[i]==0x2D) { // SDR
3365 if(rs2[i]) emit_mov(th,temp2);
3366 // Write entire word
3367 emit_writeword_indexed(tl,-3,temp);
3368 }
3369 set_jump_target(done0,(int)out);
3370 set_jump_target(done1,(int)out);
3371 set_jump_target(done2,(int)out);
3372 if (opcode[i]==0x2C) { // SDL
3373 emit_testimm(temp,4);
3374 done0=(int)out;
3375 emit_jne(0);
3376 emit_andimm(temp,~3,temp);
3377 emit_writeword_indexed(temp2,4,temp);
3378 set_jump_target(done0,(int)out);
3379 }
3380 if (opcode[i]==0x2D) { // SDR
3381 emit_testimm(temp,4);
3382 done0=(int)out;
3383 emit_jeq(0);
3384 emit_andimm(temp,~3,temp);
3385 emit_writeword_indexed(temp2,-4,temp);
3386 set_jump_target(done0,(int)out);
3387 }
3388 if(!c||!memtarget)
b7918751 3389 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3390 }
3391 if(!using_tlb) {
3392 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3393 #if defined(HOST_IMM8)
3394 int ir=get_reg(i_regs->regmap,INVCP);
3395 assert(ir>=0);
3396 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3397 #else
3398 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3399 #endif
3400 jaddr2=(int)out;
3401 emit_jne(0);
3402 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3403 }
3404 /*
3405 emit_pusha();
3406 //save_regs(0x100f);
3407 emit_readword((int)&last_count,ECX);
3408 if(get_reg(i_regs->regmap,CCREG)<0)
3409 emit_loadreg(CCREG,HOST_CCREG);
3410 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3411 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3412 emit_writeword(HOST_CCREG,(int)&Count);
3413 emit_call((int)memdebug);
3414 emit_popa();
3415 //restore_regs(0x100f);
3416 /**/
3417}
3418
3419void c1ls_assemble(int i,struct regstat *i_regs)
3420{
3d624f89 3421#ifndef DISABLE_COP1
57871462 3422 int s,th,tl;
3423 int temp,ar;
3424 int map=-1;