57871462 |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * |
3 | * Copyright (C) 2009-2010 Ari64 * |
4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * |
6 | * it under the terms of the GNU General Public License as published by * |
7 | * the Free Software Foundation; either version 2 of the License, or * |
8 | * (at your option) any later version. * |
9 | * * |
10 | * This program is distributed in the hope that it will be useful, * |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
13 | * GNU General Public License for more details. * |
14 | * * |
15 | * You should have received a copy of the GNU General Public License * |
16 | * along with this program; if not, write to the * |
17 | * Free Software Foundation, Inc., * |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
20 | |
21 | #include <stdlib.h> |
22 | #include <stdint.h> //include for uint64_t |
23 | #include <assert.h> |
24 | |
3d624f89 |
25 | #include "emu_if.h" //emulator interface |
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26 | |
27 | #include <sys/mman.h> |
28 | |
29 | #ifdef __i386__ |
30 | #include "assem_x86.h" |
31 | #endif |
32 | #ifdef __x86_64__ |
33 | #include "assem_x64.h" |
34 | #endif |
35 | #ifdef __arm__ |
36 | #include "assem_arm.h" |
37 | #endif |
38 | |
39 | #define MAXBLOCK 4096 |
40 | #define MAX_OUTPUT_BLOCK_SIZE 262144 |
41 | #define CLOCK_DIVIDER 2 |
42 | |
43 | struct regstat |
44 | { |
45 | signed char regmap_entry[HOST_REGS]; |
46 | signed char regmap[HOST_REGS]; |
47 | uint64_t was32; |
48 | uint64_t is32; |
49 | uint64_t wasdirty; |
50 | uint64_t dirty; |
51 | uint64_t u; |
52 | uint64_t uu; |
53 | u_int wasconst; |
54 | u_int isconst; |
55 | uint64_t constmap[HOST_REGS]; |
56 | }; |
57 | |
58 | struct ll_entry |
59 | { |
60 | u_int vaddr; |
61 | u_int reg32; |
62 | void *addr; |
63 | struct ll_entry *next; |
64 | }; |
65 | |
66 | u_int start; |
67 | u_int *source; |
68 | u_int pagelimit; |
69 | char insn[MAXBLOCK][10]; |
70 | u_char itype[MAXBLOCK]; |
71 | u_char opcode[MAXBLOCK]; |
72 | u_char opcode2[MAXBLOCK]; |
73 | u_char bt[MAXBLOCK]; |
74 | u_char rs1[MAXBLOCK]; |
75 | u_char rs2[MAXBLOCK]; |
76 | u_char rt1[MAXBLOCK]; |
77 | u_char rt2[MAXBLOCK]; |
78 | u_char us1[MAXBLOCK]; |
79 | u_char us2[MAXBLOCK]; |
80 | u_char dep1[MAXBLOCK]; |
81 | u_char dep2[MAXBLOCK]; |
82 | u_char lt1[MAXBLOCK]; |
83 | int imm[MAXBLOCK]; |
84 | u_int ba[MAXBLOCK]; |
85 | char likely[MAXBLOCK]; |
86 | char is_ds[MAXBLOCK]; |
87 | uint64_t unneeded_reg[MAXBLOCK]; |
88 | uint64_t unneeded_reg_upper[MAXBLOCK]; |
89 | uint64_t branch_unneeded_reg[MAXBLOCK]; |
90 | uint64_t branch_unneeded_reg_upper[MAXBLOCK]; |
91 | uint64_t p32[MAXBLOCK]; |
92 | uint64_t pr32[MAXBLOCK]; |
93 | signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
94 | signed char regmap[MAXBLOCK][HOST_REGS]; |
95 | signed char regmap_entry[MAXBLOCK][HOST_REGS]; |
96 | uint64_t constmap[MAXBLOCK][HOST_REGS]; |
97 | uint64_t known_value[HOST_REGS]; |
98 | u_int known_reg; |
99 | struct regstat regs[MAXBLOCK]; |
100 | struct regstat branch_regs[MAXBLOCK]; |
101 | u_int needed_reg[MAXBLOCK]; |
102 | uint64_t requires_32bit[MAXBLOCK]; |
103 | u_int wont_dirty[MAXBLOCK]; |
104 | u_int will_dirty[MAXBLOCK]; |
105 | int ccadj[MAXBLOCK]; |
106 | int slen; |
107 | u_int instr_addr[MAXBLOCK]; |
108 | u_int link_addr[MAXBLOCK][3]; |
109 | int linkcount; |
110 | u_int stubs[MAXBLOCK*3][8]; |
111 | int stubcount; |
112 | u_int literals[1024][2]; |
113 | int literalcount; |
114 | int is_delayslot; |
115 | int cop1_usable; |
116 | u_char *out; |
117 | struct ll_entry *jump_in[4096]; |
118 | struct ll_entry *jump_out[4096]; |
119 | struct ll_entry *jump_dirty[4096]; |
120 | u_int hash_table[65536][4] __attribute__((aligned(16))); |
121 | char shadow[1048576] __attribute__((aligned(16))); |
122 | void *copy; |
123 | int expirep; |
124 | u_int using_tlb; |
125 | u_int stop_after_jal; |
126 | extern u_char restore_candidate[512]; |
127 | extern int cycle_count; |
128 | |
129 | /* registers that may be allocated */ |
130 | /* 1-31 gpr */ |
131 | #define HIREG 32 // hi |
132 | #define LOREG 33 // lo |
133 | #define FSREG 34 // FPU status (FCSR) |
134 | #define CSREG 35 // Coprocessor status |
135 | #define CCREG 36 // Cycle count |
136 | #define INVCP 37 // Pointer to invalid_code |
137 | #define TEMPREG 38 |
b9b61529 |
138 | #define FTEMP 38 // FPU/LDL/LDR temporary register |
57871462 |
139 | #define PTEMP 39 // Prefetch temporary register |
140 | #define TLREG 40 // TLB mapping offset |
141 | #define RHASH 41 // Return address hash |
142 | #define RHTBL 42 // Return address hash table address |
143 | #define RTEMP 43 // JR/JALR address register |
144 | #define MAXREG 43 |
145 | #define AGEN1 44 // Address generation temporary register |
146 | #define AGEN2 45 // Address generation temporary register |
147 | #define MGEN1 46 // Maptable address generation temporary register |
148 | #define MGEN2 47 // Maptable address generation temporary register |
149 | #define BTREG 48 // Branch target temporary register |
150 | |
151 | /* instruction types */ |
152 | #define NOP 0 // No operation |
153 | #define LOAD 1 // Load |
154 | #define STORE 2 // Store |
155 | #define LOADLR 3 // Unaligned load |
156 | #define STORELR 4 // Unaligned store |
157 | #define MOV 5 // Move |
158 | #define ALU 6 // Arithmetic/logic |
159 | #define MULTDIV 7 // Multiply/divide |
160 | #define SHIFT 8 // Shift by register |
161 | #define SHIFTIMM 9// Shift by immediate |
162 | #define IMM16 10 // 16-bit immediate |
163 | #define RJUMP 11 // Unconditional jump to register |
164 | #define UJUMP 12 // Unconditional jump |
165 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) |
166 | #define SJUMP 14 // Conditional branch (regimm format) |
167 | #define COP0 15 // Coprocessor 0 |
168 | #define COP1 16 // Coprocessor 1 |
169 | #define C1LS 17 // Coprocessor 1 load/store |
170 | #define FJUMP 18 // Conditional branch (floating point) |
171 | #define FLOAT 19 // Floating point unit |
172 | #define FCONV 20 // Convert integer to float |
173 | #define FCOMP 21 // Floating point compare (sets FSREG) |
174 | #define SYSCALL 22// SYSCALL |
175 | #define OTHER 23 // Other |
176 | #define SPAN 24 // Branch/delay slot spans 2 pages |
177 | #define NI 25 // Not implemented |
7139f3c8 |
178 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 |
179 | #define COP2 27 // Coprocessor 2 move |
180 | #define C2LS 28 // Coprocessor 2 load/store |
181 | #define C2OP 29 // Coprocessor 2 operation |
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182 | |
183 | /* stubs */ |
184 | #define CC_STUB 1 |
185 | #define FP_STUB 2 |
186 | #define LOADB_STUB 3 |
187 | #define LOADH_STUB 4 |
188 | #define LOADW_STUB 5 |
189 | #define LOADD_STUB 6 |
190 | #define LOADBU_STUB 7 |
191 | #define LOADHU_STUB 8 |
192 | #define STOREB_STUB 9 |
193 | #define STOREH_STUB 10 |
194 | #define STOREW_STUB 11 |
195 | #define STORED_STUB 12 |
196 | #define STORELR_STUB 13 |
197 | #define INVCODE_STUB 14 |
198 | |
199 | /* branch codes */ |
200 | #define TAKEN 1 |
201 | #define NOTTAKEN 2 |
202 | #define NULLDS 3 |
203 | |
204 | // asm linkage |
205 | int new_recompile_block(int addr); |
206 | void *get_addr_ht(u_int vaddr); |
207 | void invalidate_block(u_int block); |
208 | void invalidate_addr(u_int addr); |
209 | void remove_hash(int vaddr); |
210 | void jump_vaddr(); |
211 | void dyna_linker(); |
212 | void dyna_linker_ds(); |
213 | void verify_code(); |
214 | void verify_code_vm(); |
215 | void verify_code_ds(); |
216 | void cc_interrupt(); |
217 | void fp_exception(); |
218 | void fp_exception_ds(); |
219 | void jump_syscall(); |
7139f3c8 |
220 | void jump_syscall_hle(); |
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221 | void jump_eret(); |
7139f3c8 |
222 | void jump_hlecall(); |
223 | void new_dyna_leave(); |
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224 | |
225 | // TLB |
226 | void TLBWI_new(); |
227 | void TLBWR_new(); |
228 | void read_nomem_new(); |
229 | void read_nomemb_new(); |
230 | void read_nomemh_new(); |
231 | void read_nomemd_new(); |
232 | void write_nomem_new(); |
233 | void write_nomemb_new(); |
234 | void write_nomemh_new(); |
235 | void write_nomemd_new(); |
236 | void write_rdram_new(); |
237 | void write_rdramb_new(); |
238 | void write_rdramh_new(); |
239 | void write_rdramd_new(); |
240 | extern u_int memory_map[1048576]; |
241 | |
242 | // Needed by assembler |
243 | void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32); |
244 | void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty); |
245 | void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr); |
246 | void load_all_regs(signed char i_regmap[]); |
247 | void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); |
248 | void load_regs_entry(int t); |
249 | void load_all_consts(signed char regmap[],int is32,u_int dirty,int i); |
250 | |
251 | int tracedebug=0; |
252 | |
253 | //#define DEBUG_CYCLE_COUNT 1 |
254 | |
255 | void nullf() {} |
256 | //#define assem_debug printf |
257 | //#define inv_debug printf |
258 | #define assem_debug nullf |
259 | #define inv_debug nullf |
260 | |
94d23bb9 |
261 | static void tlb_hacks() |
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262 | { |
94d23bb9 |
263 | #ifndef DISABLE_TLB |
57871462 |
264 | // Goldeneye hack |
265 | if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0) |
266 | { |
267 | u_int addr; |
268 | int n; |
269 | switch (ROM_HEADER->Country_code&0xFF) |
270 | { |
271 | case 0x45: // U |
272 | addr=0x34b30; |
273 | break; |
274 | case 0x4A: // J |
275 | addr=0x34b70; |
276 | break; |
277 | case 0x50: // E |
278 | addr=0x329f0; |
279 | break; |
280 | default: |
281 | // Unknown country code |
282 | addr=0; |
283 | break; |
284 | } |
285 | u_int rom_addr=(u_int)rom; |
286 | #ifdef ROM_COPY |
287 | // Since memory_map is 32-bit, on 64-bit systems the rom needs to be |
288 | // in the lower 4G of memory to use this hack. Copy it if necessary. |
289 | if((void *)rom>(void *)0xffffffff) { |
290 | munmap(ROM_COPY, 67108864); |
291 | if(mmap(ROM_COPY, 12582912, |
292 | PROT_READ | PROT_WRITE, |
293 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, |
294 | -1, 0) <= 0) {printf("mmap() failed\n");} |
295 | memcpy(ROM_COPY,rom,12582912); |
296 | rom_addr=(u_int)ROM_COPY; |
297 | } |
298 | #endif |
299 | if(addr) { |
300 | for(n=0x7F000;n<0x80000;n++) { |
301 | memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000; |
302 | } |
303 | } |
304 | } |
94d23bb9 |
305 | #endif |
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306 | } |
307 | |
94d23bb9 |
308 | static u_int get_page(u_int vaddr) |
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309 | { |
310 | u_int page=(vaddr^0x80000000)>>12; |
94d23bb9 |
311 | #ifndef DISABLE_TLB |
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312 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
94d23bb9 |
313 | #endif |
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314 | if(page>2048) page=2048+(page&2047); |
94d23bb9 |
315 | return page; |
316 | } |
317 | |
318 | static u_int get_vpage(u_int vaddr) |
319 | { |
320 | u_int vpage=(vaddr^0x80000000)>>12; |
321 | #ifndef DISABLE_TLB |
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322 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
94d23bb9 |
323 | #endif |
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324 | if(vpage>2048) vpage=2048+(vpage&2047); |
94d23bb9 |
325 | return vpage; |
326 | } |
327 | |
328 | // Get address from virtual address |
329 | // This is called from the recompiled JR/JALR instructions |
330 | void *get_addr(u_int vaddr) |
331 | { |
332 | u_int page=get_page(vaddr); |
333 | u_int vpage=get_vpage(vaddr); |
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334 | struct ll_entry *head; |
335 | //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); |
336 | head=jump_in[page]; |
337 | while(head!=NULL) { |
338 | if(head->vaddr==vaddr&&head->reg32==0) { |
339 | //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
340 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
341 | ht_bin[3]=ht_bin[1]; |
342 | ht_bin[2]=ht_bin[0]; |
343 | ht_bin[1]=(int)head->addr; |
344 | ht_bin[0]=vaddr; |
345 | return head->addr; |
346 | } |
347 | head=head->next; |
348 | } |
349 | head=jump_dirty[vpage]; |
350 | while(head!=NULL) { |
351 | if(head->vaddr==vaddr&&head->reg32==0) { |
352 | //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
353 | // Don't restore blocks which are about to expire from the cache |
354 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
355 | if(verify_dirty(head->addr)) { |
356 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); |
357 | invalid_code[vaddr>>12]=0; |
358 | memory_map[vaddr>>12]|=0x40000000; |
359 | if(vpage<2048) { |
94d23bb9 |
360 | #ifndef DISABLE_TLB |
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361 | if(tlb_LUT_r[vaddr>>12]) { |
362 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
363 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
364 | } |
94d23bb9 |
365 | #endif |
57871462 |
366 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
367 | } |
368 | else restore_candidate[page>>3]|=1<<(page&7); |
369 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
370 | if(ht_bin[0]==vaddr) { |
371 | ht_bin[1]=(int)head->addr; // Replace existing entry |
372 | } |
373 | else |
374 | { |
375 | ht_bin[3]=ht_bin[1]; |
376 | ht_bin[2]=ht_bin[0]; |
377 | ht_bin[1]=(int)head->addr; |
378 | ht_bin[0]=vaddr; |
379 | } |
380 | return head->addr; |
381 | } |
382 | } |
383 | head=head->next; |
384 | } |
385 | //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); |
386 | int r=new_recompile_block(vaddr); |
387 | if(r==0) return get_addr(vaddr); |
388 | // Execute in unmapped page, generate pagefault execption |
389 | Status|=2; |
390 | Cause=(vaddr<<31)|0x8; |
391 | EPC=(vaddr&1)?vaddr-5:vaddr; |
392 | BadVAddr=(vaddr&~1); |
393 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
394 | EntryHi=BadVAddr&0xFFFFE000; |
395 | return get_addr_ht(0x80000000); |
396 | } |
397 | // Look up address in hash table first |
398 | void *get_addr_ht(u_int vaddr) |
399 | { |
400 | //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); |
401 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
402 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
403 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
404 | return get_addr(vaddr); |
405 | } |
406 | |
407 | void *get_addr_32(u_int vaddr,u_int flags) |
408 | { |
7139f3c8 |
409 | #ifdef FORCE32 |
410 | return get_addr(vaddr); |
411 | #endif |
57871462 |
412 | //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags); |
413 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
414 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
415 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
94d23bb9 |
416 | u_int page=get_page(vaddr); |
417 | u_int vpage=get_vpage(vaddr); |
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418 | struct ll_entry *head; |
419 | head=jump_in[page]; |
420 | while(head!=NULL) { |
421 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
422 | //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
423 | if(head->reg32==0) { |
424 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
425 | if(ht_bin[0]==-1) { |
426 | ht_bin[1]=(int)head->addr; |
427 | ht_bin[0]=vaddr; |
428 | }else if(ht_bin[2]==-1) { |
429 | ht_bin[3]=(int)head->addr; |
430 | ht_bin[2]=vaddr; |
431 | } |
432 | //ht_bin[3]=ht_bin[1]; |
433 | //ht_bin[2]=ht_bin[0]; |
434 | //ht_bin[1]=(int)head->addr; |
435 | //ht_bin[0]=vaddr; |
436 | } |
437 | return head->addr; |
438 | } |
439 | head=head->next; |
440 | } |
441 | head=jump_dirty[vpage]; |
442 | while(head!=NULL) { |
443 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
444 | //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
445 | // Don't restore blocks which are about to expire from the cache |
446 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
447 | if(verify_dirty(head->addr)) { |
448 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); |
449 | invalid_code[vaddr>>12]=0; |
450 | memory_map[vaddr>>12]|=0x40000000; |
451 | if(vpage<2048) { |
94d23bb9 |
452 | #ifndef DISABLE_TLB |
57871462 |
453 | if(tlb_LUT_r[vaddr>>12]) { |
454 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
455 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
456 | } |
94d23bb9 |
457 | #endif |
57871462 |
458 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
459 | } |
460 | else restore_candidate[page>>3]|=1<<(page&7); |
461 | if(head->reg32==0) { |
462 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
463 | if(ht_bin[0]==-1) { |
464 | ht_bin[1]=(int)head->addr; |
465 | ht_bin[0]=vaddr; |
466 | }else if(ht_bin[2]==-1) { |
467 | ht_bin[3]=(int)head->addr; |
468 | ht_bin[2]=vaddr; |
469 | } |
470 | //ht_bin[3]=ht_bin[1]; |
471 | //ht_bin[2]=ht_bin[0]; |
472 | //ht_bin[1]=(int)head->addr; |
473 | //ht_bin[0]=vaddr; |
474 | } |
475 | return head->addr; |
476 | } |
477 | } |
478 | head=head->next; |
479 | } |
480 | //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags); |
481 | int r=new_recompile_block(vaddr); |
482 | if(r==0) return get_addr(vaddr); |
483 | // Execute in unmapped page, generate pagefault execption |
484 | Status|=2; |
485 | Cause=(vaddr<<31)|0x8; |
486 | EPC=(vaddr&1)?vaddr-5:vaddr; |
487 | BadVAddr=(vaddr&~1); |
488 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
489 | EntryHi=BadVAddr&0xFFFFE000; |
490 | return get_addr_ht(0x80000000); |
491 | } |
492 | |
493 | void clear_all_regs(signed char regmap[]) |
494 | { |
495 | int hr; |
496 | for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1; |
497 | } |
498 | |
499 | signed char get_reg(signed char regmap[],int r) |
500 | { |
501 | int hr; |
502 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr; |
503 | return -1; |
504 | } |
505 | |
506 | // Find a register that is available for two consecutive cycles |
507 | signed char get_reg2(signed char regmap1[],signed char regmap2[],int r) |
508 | { |
509 | int hr; |
510 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; |
511 | return -1; |
512 | } |
513 | |
514 | int count_free_regs(signed char regmap[]) |
515 | { |
516 | int count=0; |
517 | int hr; |
518 | for(hr=0;hr<HOST_REGS;hr++) |
519 | { |
520 | if(hr!=EXCLUDE_REG) { |
521 | if(regmap[hr]<0) count++; |
522 | } |
523 | } |
524 | return count; |
525 | } |
526 | |
527 | void dirty_reg(struct regstat *cur,signed char reg) |
528 | { |
529 | int hr; |
530 | if(!reg) return; |
531 | for (hr=0;hr<HOST_REGS;hr++) { |
532 | if((cur->regmap[hr]&63)==reg) { |
533 | cur->dirty|=1<<hr; |
534 | } |
535 | } |
536 | } |
537 | |
538 | // If we dirty the lower half of a 64 bit register which is now being |
539 | // sign-extended, we need to dump the upper half. |
540 | // Note: Do this only after completion of the instruction, because |
541 | // some instructions may need to read the full 64-bit value even if |
542 | // overwriting it (eg SLTI, DSRA32). |
543 | static void flush_dirty_uppers(struct regstat *cur) |
544 | { |
545 | int hr,reg; |
546 | for (hr=0;hr<HOST_REGS;hr++) { |
547 | if((cur->dirty>>hr)&1) { |
548 | reg=cur->regmap[hr]; |
549 | if(reg>=64) |
550 | if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; |
551 | } |
552 | } |
553 | } |
554 | |
555 | void set_const(struct regstat *cur,signed char reg,uint64_t value) |
556 | { |
557 | int hr; |
558 | if(!reg) return; |
559 | for (hr=0;hr<HOST_REGS;hr++) { |
560 | if(cur->regmap[hr]==reg) { |
561 | cur->isconst|=1<<hr; |
562 | cur->constmap[hr]=value; |
563 | } |
564 | else if((cur->regmap[hr]^64)==reg) { |
565 | cur->isconst|=1<<hr; |
566 | cur->constmap[hr]=value>>32; |
567 | } |
568 | } |
569 | } |
570 | |
571 | void clear_const(struct regstat *cur,signed char reg) |
572 | { |
573 | int hr; |
574 | if(!reg) return; |
575 | for (hr=0;hr<HOST_REGS;hr++) { |
576 | if((cur->regmap[hr]&63)==reg) { |
577 | cur->isconst&=~(1<<hr); |
578 | } |
579 | } |
580 | } |
581 | |
582 | int is_const(struct regstat *cur,signed char reg) |
583 | { |
584 | int hr; |
585 | if(!reg) return 1; |
586 | for (hr=0;hr<HOST_REGS;hr++) { |
587 | if((cur->regmap[hr]&63)==reg) { |
588 | return (cur->isconst>>hr)&1; |
589 | } |
590 | } |
591 | return 0; |
592 | } |
593 | uint64_t get_const(struct regstat *cur,signed char reg) |
594 | { |
595 | int hr; |
596 | if(!reg) return 0; |
597 | for (hr=0;hr<HOST_REGS;hr++) { |
598 | if(cur->regmap[hr]==reg) { |
599 | return cur->constmap[hr]; |
600 | } |
601 | } |
602 | printf("Unknown constant in r%d\n",reg); |
603 | exit(1); |
604 | } |
605 | |
606 | // Least soon needed registers |
607 | // Look at the next ten instructions and see which registers |
608 | // will be used. Try not to reallocate these. |
609 | void lsn(u_char hsn[], int i, int *preferred_reg) |
610 | { |
611 | int j; |
612 | int b=-1; |
613 | for(j=0;j<9;j++) |
614 | { |
615 | if(i+j>=slen) { |
616 | j=slen-i-1; |
617 | break; |
618 | } |
619 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
620 | { |
621 | // Don't go past an unconditonal jump |
622 | j++; |
623 | break; |
624 | } |
625 | } |
626 | for(;j>=0;j--) |
627 | { |
628 | if(rs1[i+j]) hsn[rs1[i+j]]=j; |
629 | if(rs2[i+j]) hsn[rs2[i+j]]=j; |
630 | if(rt1[i+j]) hsn[rt1[i+j]]=j; |
631 | if(rt2[i+j]) hsn[rt2[i+j]]=j; |
632 | if(itype[i+j]==STORE || itype[i+j]==STORELR) { |
633 | // Stores can allocate zero |
634 | hsn[rs1[i+j]]=j; |
635 | hsn[rs2[i+j]]=j; |
636 | } |
637 | // On some architectures stores need invc_ptr |
638 | #if defined(HOST_IMM8) |
b9b61529 |
639 | if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) { |
57871462 |
640 | hsn[INVCP]=j; |
641 | } |
642 | #endif |
643 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
644 | { |
645 | hsn[CCREG]=j; |
646 | b=j; |
647 | } |
648 | } |
649 | if(b>=0) |
650 | { |
651 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
652 | { |
653 | // Follow first branch |
654 | int t=(ba[i+b]-start)>>2; |
655 | j=7-b;if(t+j>=slen) j=slen-t-1; |
656 | for(;j>=0;j--) |
657 | { |
658 | if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2; |
659 | if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2; |
660 | //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2; |
661 | //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2; |
662 | } |
663 | } |
664 | // TODO: preferred register based on backward branch |
665 | } |
666 | // Delay slot should preferably not overwrite branch conditions or cycle count |
667 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { |
668 | if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; |
669 | if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; |
670 | hsn[CCREG]=1; |
671 | // ...or hash tables |
672 | hsn[RHASH]=1; |
673 | hsn[RHTBL]=1; |
674 | } |
675 | // Coprocessor load/store needs FTEMP, even if not declared |
b9b61529 |
676 | if(itype[i]==C1LS||itype[i]==C2LS) { |
57871462 |
677 | hsn[FTEMP]=0; |
678 | } |
679 | // Load L/R also uses FTEMP as a temporary register |
680 | if(itype[i]==LOADLR) { |
681 | hsn[FTEMP]=0; |
682 | } |
b7918751 |
683 | // Also SWL/SWR/SDL/SDR |
684 | if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { |
57871462 |
685 | hsn[FTEMP]=0; |
686 | } |
687 | // Don't remove the TLB registers either |
b9b61529 |
688 | if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) { |
57871462 |
689 | hsn[TLREG]=0; |
690 | } |
691 | // Don't remove the miniht registers |
692 | if(itype[i]==UJUMP||itype[i]==RJUMP) |
693 | { |
694 | hsn[RHASH]=0; |
695 | hsn[RHTBL]=0; |
696 | } |
697 | } |
698 | |
699 | // We only want to allocate registers if we're going to use them again soon |
700 | int needed_again(int r, int i) |
701 | { |
702 | int j; |
703 | int b=-1; |
704 | int rn=10; |
705 | int hr; |
706 | u_char hsn[MAXREG+1]; |
707 | int preferred_reg; |
708 | |
709 | memset(hsn,10,sizeof(hsn)); |
710 | lsn(hsn,i,&preferred_reg); |
711 | |
712 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) |
713 | { |
714 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) |
715 | return 0; // Don't need any registers if exiting the block |
716 | } |
717 | for(j=0;j<9;j++) |
718 | { |
719 | if(i+j>=slen) { |
720 | j=slen-i-1; |
721 | break; |
722 | } |
723 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
724 | { |
725 | // Don't go past an unconditonal jump |
726 | j++; |
727 | break; |
728 | } |
7139f3c8 |
729 | if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d)) |
57871462 |
730 | { |
731 | break; |
732 | } |
733 | } |
734 | for(;j>=1;j--) |
735 | { |
736 | if(rs1[i+j]==r) rn=j; |
737 | if(rs2[i+j]==r) rn=j; |
738 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
739 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
740 | { |
741 | b=j; |
742 | } |
743 | } |
744 | /* |
745 | if(b>=0) |
746 | { |
747 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
748 | { |
749 | // Follow first branch |
750 | int o=rn; |
751 | int t=(ba[i+b]-start)>>2; |
752 | j=7-b;if(t+j>=slen) j=slen-t-1; |
753 | for(;j>=0;j--) |
754 | { |
755 | if(!((unneeded_reg[t+j]>>r)&1)) { |
756 | if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
757 | if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
758 | } |
759 | else rn=o; |
760 | } |
761 | } |
762 | }*/ |
763 | for(hr=0;hr<HOST_REGS;hr++) { |
764 | if(hr!=EXCLUDE_REG) { |
765 | if(rn<hsn[hr]) return 1; |
766 | } |
767 | } |
768 | return 0; |
769 | } |
770 | |
771 | // Try to match register allocations at the end of a loop with those |
772 | // at the beginning |
773 | int loop_reg(int i, int r, int hr) |
774 | { |
775 | int j,k; |
776 | for(j=0;j<9;j++) |
777 | { |
778 | if(i+j>=slen) { |
779 | j=slen-i-1; |
780 | break; |
781 | } |
782 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
783 | { |
784 | // Don't go past an unconditonal jump |
785 | j++; |
786 | break; |
787 | } |
788 | } |
789 | k=0; |
790 | if(i>0){ |
791 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) |
792 | k--; |
793 | } |
794 | for(;k<j;k++) |
795 | { |
796 | if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr; |
797 | if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr; |
798 | if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP)) |
799 | { |
800 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) |
801 | { |
802 | int t=(ba[i+k]-start)>>2; |
803 | int reg=get_reg(regs[t].regmap_entry,r); |
804 | if(reg>=0) return reg; |
805 | //reg=get_reg(regs[t+1].regmap_entry,r); |
806 | //if(reg>=0) return reg; |
807 | } |
808 | } |
809 | } |
810 | return hr; |
811 | } |
812 | |
813 | |
814 | // Allocate every register, preserving source/target regs |
815 | void alloc_all(struct regstat *cur,int i) |
816 | { |
817 | int hr; |
818 | |
819 | for(hr=0;hr<HOST_REGS;hr++) { |
820 | if(hr!=EXCLUDE_REG) { |
821 | if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& |
822 | ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i])) |
823 | { |
824 | cur->regmap[hr]=-1; |
825 | cur->dirty&=~(1<<hr); |
826 | } |
827 | // Don't need zeros |
828 | if((cur->regmap[hr]&63)==0) |
829 | { |
830 | cur->regmap[hr]=-1; |
831 | cur->dirty&=~(1<<hr); |
832 | } |
833 | } |
834 | } |
835 | } |
836 | |
837 | |
838 | void div64(int64_t dividend,int64_t divisor) |
839 | { |
840 | lo=dividend/divisor; |
841 | hi=dividend%divisor; |
842 | //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32) |
843 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
844 | } |
845 | void divu64(uint64_t dividend,uint64_t divisor) |
846 | { |
847 | lo=dividend/divisor; |
848 | hi=dividend%divisor; |
849 | //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
850 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
851 | } |
852 | |
853 | void mult64(uint64_t m1,uint64_t m2) |
854 | { |
855 | unsigned long long int op1, op2, op3, op4; |
856 | unsigned long long int result1, result2, result3, result4; |
857 | unsigned long long int temp1, temp2, temp3, temp4; |
858 | int sign = 0; |
859 | |
860 | if (m1 < 0) |
861 | { |
862 | op2 = -m1; |
863 | sign = 1 - sign; |
864 | } |
865 | else op2 = m1; |
866 | if (m2 < 0) |
867 | { |
868 | op4 = -m2; |
869 | sign = 1 - sign; |
870 | } |
871 | else op4 = m2; |
872 | |
873 | op1 = op2 & 0xFFFFFFFF; |
874 | op2 = (op2 >> 32) & 0xFFFFFFFF; |
875 | op3 = op4 & 0xFFFFFFFF; |
876 | op4 = (op4 >> 32) & 0xFFFFFFFF; |
877 | |
878 | temp1 = op1 * op3; |
879 | temp2 = (temp1 >> 32) + op1 * op4; |
880 | temp3 = op2 * op3; |
881 | temp4 = (temp3 >> 32) + op2 * op4; |
882 | |
883 | result1 = temp1 & 0xFFFFFFFF; |
884 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
885 | result3 = (result2 >> 32) + temp4; |
886 | result4 = (result3 >> 32); |
887 | |
888 | lo = result1 | (result2 << 32); |
889 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
890 | if (sign) |
891 | { |
892 | hi = ~hi; |
893 | if (!lo) hi++; |
894 | else lo = ~lo + 1; |
895 | } |
896 | } |
897 | |
898 | void multu64(uint64_t m1,uint64_t m2) |
899 | { |
900 | unsigned long long int op1, op2, op3, op4; |
901 | unsigned long long int result1, result2, result3, result4; |
902 | unsigned long long int temp1, temp2, temp3, temp4; |
903 | |
904 | op1 = m1 & 0xFFFFFFFF; |
905 | op2 = (m1 >> 32) & 0xFFFFFFFF; |
906 | op3 = m2 & 0xFFFFFFFF; |
907 | op4 = (m2 >> 32) & 0xFFFFFFFF; |
908 | |
909 | temp1 = op1 * op3; |
910 | temp2 = (temp1 >> 32) + op1 * op4; |
911 | temp3 = op2 * op3; |
912 | temp4 = (temp3 >> 32) + op2 * op4; |
913 | |
914 | result1 = temp1 & 0xFFFFFFFF; |
915 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
916 | result3 = (result2 >> 32) + temp4; |
917 | result4 = (result3 >> 32); |
918 | |
919 | lo = result1 | (result2 << 32); |
920 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
921 | |
922 | //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
923 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
924 | } |
925 | |
926 | uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits) |
927 | { |
928 | if(bits) { |
929 | original<<=64-bits; |
930 | original>>=64-bits; |
931 | loaded<<=bits; |
932 | original|=loaded; |
933 | } |
934 | else original=loaded; |
935 | return original; |
936 | } |
937 | uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits) |
938 | { |
939 | if(bits^56) { |
940 | original>>=64-(bits^56); |
941 | original<<=64-(bits^56); |
942 | loaded>>=bits^56; |
943 | original|=loaded; |
944 | } |
945 | else original=loaded; |
946 | return original; |
947 | } |
948 | |
949 | #ifdef __i386__ |
950 | #include "assem_x86.c" |
951 | #endif |
952 | #ifdef __x86_64__ |
953 | #include "assem_x64.c" |
954 | #endif |
955 | #ifdef __arm__ |
956 | #include "assem_arm.c" |
957 | #endif |
958 | |
959 | // Add virtual address mapping to linked list |
960 | void ll_add(struct ll_entry **head,int vaddr,void *addr) |
961 | { |
962 | struct ll_entry *new_entry; |
963 | new_entry=malloc(sizeof(struct ll_entry)); |
964 | assert(new_entry!=NULL); |
965 | new_entry->vaddr=vaddr; |
966 | new_entry->reg32=0; |
967 | new_entry->addr=addr; |
968 | new_entry->next=*head; |
969 | *head=new_entry; |
970 | } |
971 | |
972 | // Add virtual address mapping for 32-bit compiled block |
973 | void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr) |
974 | { |
7139f3c8 |
975 | ll_add(head,vaddr,addr); |
976 | #ifndef FORCE32 |
977 | (*head)->reg32=reg32; |
978 | #endif |
57871462 |
979 | } |
980 | |
981 | // Check if an address is already compiled |
982 | // but don't return addresses which are about to expire from the cache |
983 | void *check_addr(u_int vaddr) |
984 | { |
985 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
986 | if(ht_bin[0]==vaddr) { |
987 | if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
988 | if(isclean(ht_bin[1])) return (void *)ht_bin[1]; |
989 | } |
990 | if(ht_bin[2]==vaddr) { |
991 | if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
992 | if(isclean(ht_bin[3])) return (void *)ht_bin[3]; |
993 | } |
94d23bb9 |
994 | u_int page=get_page(vaddr); |
57871462 |
995 | struct ll_entry *head; |
996 | head=jump_in[page]; |
997 | while(head!=NULL) { |
998 | if(head->vaddr==vaddr&&head->reg32==0) { |
999 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1000 | // Update existing entry with current address |
1001 | if(ht_bin[0]==vaddr) { |
1002 | ht_bin[1]=(int)head->addr; |
1003 | return head->addr; |
1004 | } |
1005 | if(ht_bin[2]==vaddr) { |
1006 | ht_bin[3]=(int)head->addr; |
1007 | return head->addr; |
1008 | } |
1009 | // Insert into hash table with low priority. |
1010 | // Don't evict existing entries, as they are probably |
1011 | // addresses that are being accessed frequently. |
1012 | if(ht_bin[0]==-1) { |
1013 | ht_bin[1]=(int)head->addr; |
1014 | ht_bin[0]=vaddr; |
1015 | }else if(ht_bin[2]==-1) { |
1016 | ht_bin[3]=(int)head->addr; |
1017 | ht_bin[2]=vaddr; |
1018 | } |
1019 | return head->addr; |
1020 | } |
1021 | } |
1022 | head=head->next; |
1023 | } |
1024 | return 0; |
1025 | } |
1026 | |
1027 | void remove_hash(int vaddr) |
1028 | { |
1029 | //printf("remove hash: %x\n",vaddr); |
1030 | int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF]; |
1031 | if(ht_bin[2]==vaddr) { |
1032 | ht_bin[2]=ht_bin[3]=-1; |
1033 | } |
1034 | if(ht_bin[0]==vaddr) { |
1035 | ht_bin[0]=ht_bin[2]; |
1036 | ht_bin[1]=ht_bin[3]; |
1037 | ht_bin[2]=ht_bin[3]=-1; |
1038 | } |
1039 | } |
1040 | |
1041 | void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) |
1042 | { |
1043 | struct ll_entry *next; |
1044 | while(*head) { |
1045 | if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || |
1046 | ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) |
1047 | { |
1048 | inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); |
1049 | remove_hash((*head)->vaddr); |
1050 | next=(*head)->next; |
1051 | free(*head); |
1052 | *head=next; |
1053 | } |
1054 | else |
1055 | { |
1056 | head=&((*head)->next); |
1057 | } |
1058 | } |
1059 | } |
1060 | |
1061 | // Remove all entries from linked list |
1062 | void ll_clear(struct ll_entry **head) |
1063 | { |
1064 | struct ll_entry *cur; |
1065 | struct ll_entry *next; |
1066 | if(cur=*head) { |
1067 | *head=0; |
1068 | while(cur) { |
1069 | next=cur->next; |
1070 | free(cur); |
1071 | cur=next; |
1072 | } |
1073 | } |
1074 | } |
1075 | |
1076 | // Dereference the pointers and remove if it matches |
1077 | void ll_kill_pointers(struct ll_entry *head,int addr,int shift) |
1078 | { |
f76eeef9 |
1079 | u_int old_host_addr=0; |
57871462 |
1080 | while(head) { |
1081 | int ptr=get_pointer(head->addr); |
1082 | inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr); |
1083 | if(((ptr>>shift)==(addr>>shift)) || |
1084 | (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))) |
1085 | { |
f76eeef9 |
1086 | printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr); |
1087 | u_int host_addr=(u_int)kill_pointer(head->addr); |
1088 | |
1089 | if((host_addr>>12)!=(old_host_addr>>12)) { |
1090 | #ifdef __arm__ |
1091 | __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff)); |
1092 | #endif |
1093 | old_host_addr=host_addr; |
1094 | } |
57871462 |
1095 | } |
1096 | head=head->next; |
1097 | } |
f76eeef9 |
1098 | #ifdef __arm__ |
1099 | if (old_host_addr) |
1100 | __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff)); |
1101 | #endif |
57871462 |
1102 | } |
1103 | |
1104 | // This is called when we write to a compiled block (see do_invstub) |
f76eeef9 |
1105 | void invalidate_page(u_int page) |
57871462 |
1106 | { |
57871462 |
1107 | struct ll_entry *head; |
1108 | struct ll_entry *next; |
f76eeef9 |
1109 | u_int old_host_addr=0; |
57871462 |
1110 | head=jump_in[page]; |
1111 | jump_in[page]=0; |
1112 | while(head!=NULL) { |
1113 | inv_debug("INVALIDATE: %x\n",head->vaddr); |
1114 | remove_hash(head->vaddr); |
1115 | next=head->next; |
1116 | free(head); |
1117 | head=next; |
1118 | } |
1119 | head=jump_out[page]; |
1120 | jump_out[page]=0; |
1121 | while(head!=NULL) { |
1122 | inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr); |
f76eeef9 |
1123 | u_int host_addr=(u_int)kill_pointer(head->addr); |
1124 | |
1125 | if((host_addr>>12)!=(old_host_addr>>12)) { |
1126 | #ifdef __arm__ |
1127 | __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff)); |
1128 | #endif |
1129 | old_host_addr=host_addr; |
1130 | } |
57871462 |
1131 | next=head->next; |
1132 | free(head); |
1133 | head=next; |
1134 | } |
f76eeef9 |
1135 | #ifdef __arm__ |
1136 | if (old_host_addr) |
1137 | __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff)); |
1138 | #endif |
57871462 |
1139 | } |
1140 | void invalidate_block(u_int block) |
1141 | { |
94d23bb9 |
1142 | u_int page=get_page(block<<12); |
1143 | u_int vpage=get_vpage(block<<12); |
57871462 |
1144 | inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); |
1145 | //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); |
1146 | u_int first,last; |
1147 | first=last=page; |
1148 | struct ll_entry *head; |
1149 | head=jump_dirty[vpage]; |
1150 | //printf("page=%d vpage=%d\n",page,vpage); |
1151 | while(head!=NULL) { |
1152 | u_int start,end; |
1153 | if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision |
1154 | get_bounds((int)head->addr,&start,&end); |
1155 | //printf("start: %x end: %x\n",start,end); |
4cb76aa4 |
1156 | if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) { |
57871462 |
1157 | if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) { |
1158 | if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047; |
1159 | if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047; |
1160 | } |
1161 | } |
90ae6d4e |
1162 | #ifndef DISABLE_TLB |
57871462 |
1163 | if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) { |
1164 | if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) { |
1165 | if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047; |
1166 | if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047; |
1167 | } |
1168 | } |
90ae6d4e |
1169 | #endif |
57871462 |
1170 | } |
1171 | head=head->next; |
1172 | } |
1173 | //printf("first=%d last=%d\n",first,last); |
f76eeef9 |
1174 | invalidate_page(page); |
57871462 |
1175 | assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) |
1176 | assert(last<page+5); |
1177 | // Invalidate the adjacent pages if a block crosses a 4K boundary |
1178 | while(first<page) { |
1179 | invalidate_page(first); |
1180 | first++; |
1181 | } |
1182 | for(first=page+1;first<last;first++) { |
1183 | invalidate_page(first); |
1184 | } |
1185 | |
1186 | // Don't trap writes |
1187 | invalid_code[block]=1; |
94d23bb9 |
1188 | #ifndef DISABLE_TLB |
57871462 |
1189 | // If there is a valid TLB entry for this page, remove write protect |
1190 | if(tlb_LUT_w[block]) { |
1191 | assert(tlb_LUT_r[block]==tlb_LUT_w[block]); |
1192 | // CHECK: Is this right? |
1193 | memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2; |
1194 | u_int real_block=tlb_LUT_w[block]>>12; |
1195 | invalid_code[real_block]=1; |
1196 | if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2; |
1197 | } |
1198 | else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2; |
94d23bb9 |
1199 | #endif |
f76eeef9 |
1200 | |
57871462 |
1201 | #ifdef USE_MINI_HT |
1202 | memset(mini_ht,-1,sizeof(mini_ht)); |
1203 | #endif |
1204 | } |
1205 | void invalidate_addr(u_int addr) |
1206 | { |
1207 | invalidate_block(addr>>12); |
1208 | } |
1209 | void invalidate_all_pages() |
1210 | { |
1211 | u_int page,n; |
1212 | for(page=0;page<4096;page++) |
1213 | invalidate_page(page); |
1214 | for(page=0;page<1048576;page++) |
1215 | if(!invalid_code[page]) { |
1216 | restore_candidate[(page&2047)>>3]|=1<<(page&7); |
1217 | restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); |
1218 | } |
1219 | #ifdef __arm__ |
1220 | __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2)); |
1221 | #endif |
1222 | #ifdef USE_MINI_HT |
1223 | memset(mini_ht,-1,sizeof(mini_ht)); |
1224 | #endif |
94d23bb9 |
1225 | #ifndef DISABLE_TLB |
57871462 |
1226 | // TLB |
1227 | for(page=0;page<0x100000;page++) { |
1228 | if(tlb_LUT_r[page]) { |
1229 | memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2; |
1230 | if(!tlb_LUT_w[page]||!invalid_code[page]) |
1231 | memory_map[page]|=0x40000000; // Write protect |
1232 | } |
1233 | else memory_map[page]=-1; |
1234 | if(page==0x80000) page=0xC0000; |
1235 | } |
1236 | tlb_hacks(); |
94d23bb9 |
1237 | #endif |
57871462 |
1238 | } |
1239 | |
1240 | // Add an entry to jump_out after making a link |
1241 | void add_link(u_int vaddr,void *src) |
1242 | { |
94d23bb9 |
1243 | u_int page=get_page(vaddr); |
57871462 |
1244 | inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page); |
1245 | ll_add(jump_out+page,vaddr,src); |
1246 | //int ptr=get_pointer(src); |
1247 | //inv_debug("add_link: Pointer is to %x\n",(int)ptr); |
1248 | } |
1249 | |
1250 | // If a code block was found to be unmodified (bit was set in |
1251 | // restore_candidate) and it remains unmodified (bit is clear |
1252 | // in invalid_code) then move the entries for that 4K page from |
1253 | // the dirty list to the clean list. |
1254 | void clean_blocks(u_int page) |
1255 | { |
1256 | struct ll_entry *head; |
1257 | inv_debug("INV: clean_blocks page=%d\n",page); |
1258 | head=jump_dirty[page]; |
1259 | while(head!=NULL) { |
1260 | if(!invalid_code[head->vaddr>>12]) { |
1261 | // Don't restore blocks which are about to expire from the cache |
1262 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1263 | u_int start,end; |
1264 | if(verify_dirty((int)head->addr)) { |
1265 | //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr); |
1266 | u_int i; |
1267 | u_int inv=0; |
1268 | get_bounds((int)head->addr,&start,&end); |
4cb76aa4 |
1269 | if(start-(u_int)rdram<RAM_SIZE) { |
57871462 |
1270 | for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) { |
1271 | inv|=invalid_code[i]; |
1272 | } |
1273 | } |
1274 | if((signed int)head->vaddr>=(signed int)0xC0000000) { |
1275 | u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2)); |
1276 | //printf("addr=%x start=%x end=%x\n",addr,start,end); |
1277 | if(addr<start||addr>=end) inv=1; |
1278 | } |
4cb76aa4 |
1279 | else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { |
57871462 |
1280 | inv=1; |
1281 | } |
1282 | if(!inv) { |
1283 | void * clean_addr=(void *)get_clean_addr((int)head->addr); |
1284 | if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1285 | u_int ppage=page; |
94d23bb9 |
1286 | #ifndef DISABLE_TLB |
57871462 |
1287 | if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12; |
94d23bb9 |
1288 | #endif |
57871462 |
1289 | inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr); |
1290 | //printf("page=%x, addr=%x\n",page,head->vaddr); |
1291 | //assert(head->vaddr>>12==(page|0x80000)); |
1292 | ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr); |
1293 | int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF]; |
1294 | if(!head->reg32) { |
1295 | if(ht_bin[0]==head->vaddr) { |
1296 | ht_bin[1]=(int)clean_addr; // Replace existing entry |
1297 | } |
1298 | if(ht_bin[2]==head->vaddr) { |
1299 | ht_bin[3]=(int)clean_addr; // Replace existing entry |
1300 | } |
1301 | } |
1302 | } |
1303 | } |
1304 | } |
1305 | } |
1306 | } |
1307 | head=head->next; |
1308 | } |
1309 | } |
1310 | |
1311 | |
1312 | void mov_alloc(struct regstat *current,int i) |
1313 | { |
1314 | // Note: Don't need to actually alloc the source registers |
1315 | if((~current->is32>>rs1[i])&1) { |
1316 | //alloc_reg64(current,i,rs1[i]); |
1317 | alloc_reg64(current,i,rt1[i]); |
1318 | current->is32&=~(1LL<<rt1[i]); |
1319 | } else { |
1320 | //alloc_reg(current,i,rs1[i]); |
1321 | alloc_reg(current,i,rt1[i]); |
1322 | current->is32|=(1LL<<rt1[i]); |
1323 | } |
1324 | clear_const(current,rs1[i]); |
1325 | clear_const(current,rt1[i]); |
1326 | dirty_reg(current,rt1[i]); |
1327 | } |
1328 | |
1329 | void shiftimm_alloc(struct regstat *current,int i) |
1330 | { |
1331 | clear_const(current,rs1[i]); |
1332 | clear_const(current,rt1[i]); |
1333 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
1334 | { |
1335 | if(rt1[i]) { |
1336 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1337 | else lt1[i]=rs1[i]; |
1338 | alloc_reg(current,i,rt1[i]); |
1339 | current->is32|=1LL<<rt1[i]; |
1340 | dirty_reg(current,rt1[i]); |
1341 | } |
1342 | } |
1343 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
1344 | { |
1345 | if(rt1[i]) { |
1346 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1347 | alloc_reg64(current,i,rt1[i]); |
1348 | current->is32&=~(1LL<<rt1[i]); |
1349 | dirty_reg(current,rt1[i]); |
1350 | } |
1351 | } |
1352 | if(opcode2[i]==0x3c) // DSLL32 |
1353 | { |
1354 | if(rt1[i]) { |
1355 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1356 | alloc_reg64(current,i,rt1[i]); |
1357 | current->is32&=~(1LL<<rt1[i]); |
1358 | dirty_reg(current,rt1[i]); |
1359 | } |
1360 | } |
1361 | if(opcode2[i]==0x3e) // DSRL32 |
1362 | { |
1363 | if(rt1[i]) { |
1364 | alloc_reg64(current,i,rs1[i]); |
1365 | if(imm[i]==32) { |
1366 | alloc_reg64(current,i,rt1[i]); |
1367 | current->is32&=~(1LL<<rt1[i]); |
1368 | } else { |
1369 | alloc_reg(current,i,rt1[i]); |
1370 | current->is32|=1LL<<rt1[i]; |
1371 | } |
1372 | dirty_reg(current,rt1[i]); |
1373 | } |
1374 | } |
1375 | if(opcode2[i]==0x3f) // DSRA32 |
1376 | { |
1377 | if(rt1[i]) { |
1378 | alloc_reg64(current,i,rs1[i]); |
1379 | alloc_reg(current,i,rt1[i]); |
1380 | current->is32|=1LL<<rt1[i]; |
1381 | dirty_reg(current,rt1[i]); |
1382 | } |
1383 | } |
1384 | } |
1385 | |
1386 | void shift_alloc(struct regstat *current,int i) |
1387 | { |
1388 | if(rt1[i]) { |
1389 | if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV |
1390 | { |
1391 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1392 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1393 | alloc_reg(current,i,rt1[i]); |
1394 | if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1); |
1395 | current->is32|=1LL<<rt1[i]; |
1396 | } else { // DSLLV/DSRLV/DSRAV |
1397 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1398 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1399 | alloc_reg64(current,i,rt1[i]); |
1400 | current->is32&=~(1LL<<rt1[i]); |
1401 | if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register |
1402 | alloc_reg_temp(current,i,-1); |
1403 | } |
1404 | clear_const(current,rs1[i]); |
1405 | clear_const(current,rs2[i]); |
1406 | clear_const(current,rt1[i]); |
1407 | dirty_reg(current,rt1[i]); |
1408 | } |
1409 | } |
1410 | |
1411 | void alu_alloc(struct regstat *current,int i) |
1412 | { |
1413 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
1414 | if(rt1[i]) { |
1415 | if(rs1[i]&&rs2[i]) { |
1416 | alloc_reg(current,i,rs1[i]); |
1417 | alloc_reg(current,i,rs2[i]); |
1418 | } |
1419 | else { |
1420 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1421 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1422 | } |
1423 | alloc_reg(current,i,rt1[i]); |
1424 | } |
1425 | current->is32|=1LL<<rt1[i]; |
1426 | } |
1427 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
1428 | if(rt1[i]) { |
1429 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1430 | { |
1431 | alloc_reg64(current,i,rs1[i]); |
1432 | alloc_reg64(current,i,rs2[i]); |
1433 | alloc_reg(current,i,rt1[i]); |
1434 | } else { |
1435 | alloc_reg(current,i,rs1[i]); |
1436 | alloc_reg(current,i,rs2[i]); |
1437 | alloc_reg(current,i,rt1[i]); |
1438 | } |
1439 | } |
1440 | current->is32|=1LL<<rt1[i]; |
1441 | } |
1442 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
1443 | if(rt1[i]) { |
1444 | if(rs1[i]&&rs2[i]) { |
1445 | alloc_reg(current,i,rs1[i]); |
1446 | alloc_reg(current,i,rs2[i]); |
1447 | } |
1448 | else |
1449 | { |
1450 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1451 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1452 | } |
1453 | alloc_reg(current,i,rt1[i]); |
1454 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1455 | { |
1456 | if(!((current->uu>>rt1[i])&1)) { |
1457 | alloc_reg64(current,i,rt1[i]); |
1458 | } |
1459 | if(get_reg(current->regmap,rt1[i]|64)>=0) { |
1460 | if(rs1[i]&&rs2[i]) { |
1461 | alloc_reg64(current,i,rs1[i]); |
1462 | alloc_reg64(current,i,rs2[i]); |
1463 | } |
1464 | else |
1465 | { |
1466 | // Is is really worth it to keep 64-bit values in registers? |
1467 | #ifdef NATIVE_64BIT |
1468 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1469 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]); |
1470 | #endif |
1471 | } |
1472 | } |
1473 | current->is32&=~(1LL<<rt1[i]); |
1474 | } else { |
1475 | current->is32|=1LL<<rt1[i]; |
1476 | } |
1477 | } |
1478 | } |
1479 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
1480 | if(rt1[i]) { |
1481 | if(rs1[i]&&rs2[i]) { |
1482 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1483 | alloc_reg64(current,i,rs1[i]); |
1484 | alloc_reg64(current,i,rs2[i]); |
1485 | alloc_reg64(current,i,rt1[i]); |
1486 | } else { |
1487 | alloc_reg(current,i,rs1[i]); |
1488 | alloc_reg(current,i,rs2[i]); |
1489 | alloc_reg(current,i,rt1[i]); |
1490 | } |
1491 | } |
1492 | else { |
1493 | alloc_reg(current,i,rt1[i]); |
1494 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1495 | // DADD used as move, or zeroing |
1496 | // If we have a 64-bit source, then make the target 64 bits too |
1497 | if(rs1[i]&&!((current->is32>>rs1[i])&1)) { |
1498 | if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]); |
1499 | alloc_reg64(current,i,rt1[i]); |
1500 | } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) { |
1501 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1502 | alloc_reg64(current,i,rt1[i]); |
1503 | } |
1504 | if(opcode2[i]>=0x2e&&rs2[i]) { |
1505 | // DSUB used as negation - 64-bit result |
1506 | // If we have a 32-bit register, extend it to 64 bits |
1507 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1508 | alloc_reg64(current,i,rt1[i]); |
1509 | } |
1510 | } |
1511 | } |
1512 | if(rs1[i]&&rs2[i]) { |
1513 | current->is32&=~(1LL<<rt1[i]); |
1514 | } else if(rs1[i]) { |
1515 | current->is32&=~(1LL<<rt1[i]); |
1516 | if((current->is32>>rs1[i])&1) |
1517 | current->is32|=1LL<<rt1[i]; |
1518 | } else if(rs2[i]) { |
1519 | current->is32&=~(1LL<<rt1[i]); |
1520 | if((current->is32>>rs2[i])&1) |
1521 | current->is32|=1LL<<rt1[i]; |
1522 | } else { |
1523 | current->is32|=1LL<<rt1[i]; |
1524 | } |
1525 | } |
1526 | } |
1527 | clear_const(current,rs1[i]); |
1528 | clear_const(current,rs2[i]); |
1529 | clear_const(current,rt1[i]); |
1530 | dirty_reg(current,rt1[i]); |
1531 | } |
1532 | |
1533 | void imm16_alloc(struct regstat *current,int i) |
1534 | { |
1535 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1536 | else lt1[i]=rs1[i]; |
1537 | if(rt1[i]) alloc_reg(current,i,rt1[i]); |
1538 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
1539 | current->is32&=~(1LL<<rt1[i]); |
1540 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1541 | // TODO: Could preserve the 32-bit flag if the immediate is zero |
1542 | alloc_reg64(current,i,rt1[i]); |
1543 | alloc_reg64(current,i,rs1[i]); |
1544 | } |
1545 | clear_const(current,rs1[i]); |
1546 | clear_const(current,rt1[i]); |
1547 | } |
1548 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
1549 | if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]); |
1550 | current->is32|=1LL<<rt1[i]; |
1551 | clear_const(current,rs1[i]); |
1552 | clear_const(current,rt1[i]); |
1553 | } |
1554 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
1555 | if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) { |
1556 | if(rs1[i]!=rt1[i]) { |
1557 | if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1558 | alloc_reg64(current,i,rt1[i]); |
1559 | current->is32&=~(1LL<<rt1[i]); |
1560 | } |
1561 | } |
1562 | else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits |
1563 | if(is_const(current,rs1[i])) { |
1564 | int v=get_const(current,rs1[i]); |
1565 | if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]); |
1566 | if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]); |
1567 | if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]); |
1568 | } |
1569 | else clear_const(current,rt1[i]); |
1570 | } |
1571 | else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
1572 | if(is_const(current,rs1[i])) { |
1573 | int v=get_const(current,rs1[i]); |
1574 | set_const(current,rt1[i],v+imm[i]); |
1575 | } |
1576 | else clear_const(current,rt1[i]); |
1577 | current->is32|=1LL<<rt1[i]; |
1578 | } |
1579 | else { |
1580 | set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI |
1581 | current->is32|=1LL<<rt1[i]; |
1582 | } |
1583 | dirty_reg(current,rt1[i]); |
1584 | } |
1585 | |
1586 | void load_alloc(struct regstat *current,int i) |
1587 | { |
1588 | clear_const(current,rt1[i]); |
1589 | //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt? |
1590 | if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register |
1591 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1592 | if(rt1[i]) { |
1593 | alloc_reg(current,i,rt1[i]); |
1594 | if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD |
1595 | { |
1596 | current->is32&=~(1LL<<rt1[i]); |
1597 | alloc_reg64(current,i,rt1[i]); |
1598 | } |
1599 | else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
1600 | { |
1601 | current->is32&=~(1LL<<rt1[i]); |
1602 | alloc_reg64(current,i,rt1[i]); |
1603 | alloc_all(current,i); |
1604 | alloc_reg64(current,i,FTEMP); |
1605 | } |
1606 | else current->is32|=1LL<<rt1[i]; |
1607 | dirty_reg(current,rt1[i]); |
1608 | // If using TLB, need a register for pointer to the mapping table |
1609 | if(using_tlb) alloc_reg(current,i,TLREG); |
1610 | // LWL/LWR need a temporary register for the old value |
1611 | if(opcode[i]==0x22||opcode[i]==0x26) |
1612 | { |
1613 | alloc_reg(current,i,FTEMP); |
1614 | alloc_reg_temp(current,i,-1); |
1615 | } |
1616 | } |
1617 | else |
1618 | { |
1619 | // Load to r0 (dummy load) |
1620 | // but we still need a register to calculate the address |
1621 | alloc_reg_temp(current,i,-1); |
1622 | } |
1623 | } |
1624 | |
1625 | void store_alloc(struct regstat *current,int i) |
1626 | { |
1627 | clear_const(current,rs2[i]); |
1628 | if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary |
1629 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1630 | alloc_reg(current,i,rs2[i]); |
1631 | if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD |
1632 | alloc_reg64(current,i,rs2[i]); |
1633 | if(rs2[i]) alloc_reg(current,i,FTEMP); |
1634 | } |
1635 | // If using TLB, need a register for pointer to the mapping table |
1636 | if(using_tlb) alloc_reg(current,i,TLREG); |
1637 | #if defined(HOST_IMM8) |
1638 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1639 | else alloc_reg(current,i,INVCP); |
1640 | #endif |
b7918751 |
1641 | if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR |
57871462 |
1642 | alloc_reg(current,i,FTEMP); |
1643 | } |
1644 | // We need a temporary register for address generation |
1645 | alloc_reg_temp(current,i,-1); |
1646 | } |
1647 | |
1648 | void c1ls_alloc(struct regstat *current,int i) |
1649 | { |
1650 | //clear_const(current,rs1[i]); // FIXME |
1651 | clear_const(current,rt1[i]); |
1652 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1653 | alloc_reg(current,i,CSREG); // Status |
1654 | alloc_reg(current,i,FTEMP); |
1655 | if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1 |
1656 | alloc_reg64(current,i,FTEMP); |
1657 | } |
1658 | // If using TLB, need a register for pointer to the mapping table |
1659 | if(using_tlb) alloc_reg(current,i,TLREG); |
1660 | #if defined(HOST_IMM8) |
1661 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1662 | else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1 |
1663 | alloc_reg(current,i,INVCP); |
1664 | #endif |
1665 | // We need a temporary register for address generation |
1666 | alloc_reg_temp(current,i,-1); |
1667 | } |
1668 | |
b9b61529 |
1669 | void c2ls_alloc(struct regstat *current,int i) |
1670 | { |
1671 | clear_const(current,rt1[i]); |
1672 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1673 | alloc_reg(current,i,FTEMP); |
1674 | // If using TLB, need a register for pointer to the mapping table |
1675 | if(using_tlb) alloc_reg(current,i,TLREG); |
1676 | #if defined(HOST_IMM8) |
1677 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1678 | else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2 |
1679 | alloc_reg(current,i,INVCP); |
1680 | #endif |
1681 | // We need a temporary register for address generation |
1682 | alloc_reg_temp(current,i,-1); |
1683 | } |
1684 | |
57871462 |
1685 | #ifndef multdiv_alloc |
1686 | void multdiv_alloc(struct regstat *current,int i) |
1687 | { |
1688 | // case 0x18: MULT |
1689 | // case 0x19: MULTU |
1690 | // case 0x1A: DIV |
1691 | // case 0x1B: DIVU |
1692 | // case 0x1C: DMULT |
1693 | // case 0x1D: DMULTU |
1694 | // case 0x1E: DDIV |
1695 | // case 0x1F: DDIVU |
1696 | clear_const(current,rs1[i]); |
1697 | clear_const(current,rs2[i]); |
1698 | if(rs1[i]&&rs2[i]) |
1699 | { |
1700 | if((opcode2[i]&4)==0) // 32-bit |
1701 | { |
1702 | current->u&=~(1LL<<HIREG); |
1703 | current->u&=~(1LL<<LOREG); |
1704 | alloc_reg(current,i,HIREG); |
1705 | alloc_reg(current,i,LOREG); |
1706 | alloc_reg(current,i,rs1[i]); |
1707 | alloc_reg(current,i,rs2[i]); |
1708 | current->is32|=1LL<<HIREG; |
1709 | current->is32|=1LL<<LOREG; |
1710 | dirty_reg(current,HIREG); |
1711 | dirty_reg(current,LOREG); |
1712 | } |
1713 | else // 64-bit |
1714 | { |
1715 | current->u&=~(1LL<<HIREG); |
1716 | current->u&=~(1LL<<LOREG); |
1717 | current->uu&=~(1LL<<HIREG); |
1718 | current->uu&=~(1LL<<LOREG); |
1719 | alloc_reg64(current,i,HIREG); |
1720 | //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); |
1721 | alloc_reg64(current,i,rs1[i]); |
1722 | alloc_reg64(current,i,rs2[i]); |
1723 | alloc_all(current,i); |
1724 | current->is32&=~(1LL<<HIREG); |
1725 | current->is32&=~(1LL<<LOREG); |
1726 | dirty_reg(current,HIREG); |
1727 | dirty_reg(current,LOREG); |
1728 | } |
1729 | } |
1730 | else |
1731 | { |
1732 | // Multiply by zero is zero. |
1733 | // MIPS does not have a divide by zero exception. |
1734 | // The result is undefined, we return zero. |
1735 | alloc_reg(current,i,HIREG); |
1736 | alloc_reg(current,i,LOREG); |
1737 | current->is32|=1LL<<HIREG; |
1738 | current->is32|=1LL<<LOREG; |
1739 | dirty_reg(current,HIREG); |
1740 | dirty_reg(current,LOREG); |
1741 | } |
1742 | } |
1743 | #endif |
1744 | |
1745 | void cop0_alloc(struct regstat *current,int i) |
1746 | { |
1747 | if(opcode2[i]==0) // MFC0 |
1748 | { |
1749 | if(rt1[i]) { |
1750 | clear_const(current,rt1[i]); |
1751 | alloc_all(current,i); |
1752 | alloc_reg(current,i,rt1[i]); |
1753 | current->is32|=1LL<<rt1[i]; |
1754 | dirty_reg(current,rt1[i]); |
1755 | } |
1756 | } |
1757 | else if(opcode2[i]==4) // MTC0 |
1758 | { |
1759 | if(rs1[i]){ |
1760 | clear_const(current,rs1[i]); |
1761 | alloc_reg(current,i,rs1[i]); |
1762 | alloc_all(current,i); |
1763 | } |
1764 | else { |
1765 | alloc_all(current,i); // FIXME: Keep r0 |
1766 | current->u&=~1LL; |
1767 | alloc_reg(current,i,0); |
1768 | } |
1769 | } |
1770 | else |
1771 | { |
1772 | // TLBR/TLBWI/TLBWR/TLBP/ERET |
1773 | assert(opcode2[i]==0x10); |
1774 | alloc_all(current,i); |
1775 | } |
1776 | } |
1777 | |
1778 | void cop1_alloc(struct regstat *current,int i) |
1779 | { |
1780 | alloc_reg(current,i,CSREG); // Load status |
1781 | if(opcode2[i]<3) // MFC1/DMFC1/CFC1 |
1782 | { |
1783 | assert(rt1[i]); |
1784 | clear_const(current,rt1[i]); |
1785 | if(opcode2[i]==1) { |
1786 | alloc_reg64(current,i,rt1[i]); // DMFC1 |
1787 | current->is32&=~(1LL<<rt1[i]); |
1788 | }else{ |
1789 | alloc_reg(current,i,rt1[i]); // MFC1/CFC1 |
1790 | current->is32|=1LL<<rt1[i]; |
1791 | } |
1792 | dirty_reg(current,rt1[i]); |
1793 | alloc_reg_temp(current,i,-1); |
1794 | } |
1795 | else if(opcode2[i]>3) // MTC1/DMTC1/CTC1 |
1796 | { |
1797 | if(rs1[i]){ |
1798 | clear_const(current,rs1[i]); |
1799 | if(opcode2[i]==5) |
1800 | alloc_reg64(current,i,rs1[i]); // DMTC1 |
1801 | else |
1802 | alloc_reg(current,i,rs1[i]); // MTC1/CTC1 |
1803 | alloc_reg_temp(current,i,-1); |
1804 | } |
1805 | else { |
1806 | current->u&=~1LL; |
1807 | alloc_reg(current,i,0); |
1808 | alloc_reg_temp(current,i,-1); |
1809 | } |
1810 | } |
1811 | } |
1812 | void fconv_alloc(struct regstat *current,int i) |
1813 | { |
1814 | alloc_reg(current,i,CSREG); // Load status |
1815 | alloc_reg_temp(current,i,-1); |
1816 | } |
1817 | void float_alloc(struct regstat *current,int i) |
1818 | { |
1819 | alloc_reg(current,i,CSREG); // Load status |
1820 | alloc_reg_temp(current,i,-1); |
1821 | } |
b9b61529 |
1822 | void c2op_alloc(struct regstat *current,int i) |
1823 | { |
1824 | alloc_reg_temp(current,i,-1); |
1825 | } |
57871462 |
1826 | void fcomp_alloc(struct regstat *current,int i) |
1827 | { |
1828 | alloc_reg(current,i,CSREG); // Load status |
1829 | alloc_reg(current,i,FSREG); // Load flags |
1830 | dirty_reg(current,FSREG); // Flag will be modified |
1831 | alloc_reg_temp(current,i,-1); |
1832 | } |
1833 | |
1834 | void syscall_alloc(struct regstat *current,int i) |
1835 | { |
1836 | alloc_cc(current,i); |
1837 | dirty_reg(current,CCREG); |
1838 | alloc_all(current,i); |
1839 | current->isconst=0; |
1840 | } |
1841 | |
1842 | void delayslot_alloc(struct regstat *current,int i) |
1843 | { |
1844 | switch(itype[i]) { |
1845 | case UJUMP: |
1846 | case CJUMP: |
1847 | case SJUMP: |
1848 | case RJUMP: |
1849 | case FJUMP: |
1850 | case SYSCALL: |
7139f3c8 |
1851 | case HLECALL: |
57871462 |
1852 | case SPAN: |
1853 | assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1); |
1854 | printf("Disabled speculative precompilation\n"); |
1855 | stop_after_jal=1; |
1856 | break; |
1857 | case IMM16: |
1858 | imm16_alloc(current,i); |
1859 | break; |
1860 | case LOAD: |
1861 | case LOADLR: |
1862 | load_alloc(current,i); |
1863 | break; |
1864 | case STORE: |
1865 | case STORELR: |
1866 | store_alloc(current,i); |
1867 | break; |
1868 | case ALU: |
1869 | alu_alloc(current,i); |
1870 | break; |
1871 | case SHIFT: |
1872 | shift_alloc(current,i); |
1873 | break; |
1874 | case MULTDIV: |
1875 | multdiv_alloc(current,i); |
1876 | break; |
1877 | case SHIFTIMM: |
1878 | shiftimm_alloc(current,i); |
1879 | break; |
1880 | case MOV: |
1881 | mov_alloc(current,i); |
1882 | break; |
1883 | case COP0: |
1884 | cop0_alloc(current,i); |
1885 | break; |
1886 | case COP1: |
b9b61529 |
1887 | case COP2: |
57871462 |
1888 | cop1_alloc(current,i); |
1889 | break; |
1890 | case C1LS: |
1891 | c1ls_alloc(current,i); |
1892 | break; |
b9b61529 |
1893 | case C2LS: |
1894 | c2ls_alloc(current,i); |
1895 | break; |
57871462 |
1896 | case FCONV: |
1897 | fconv_alloc(current,i); |
1898 | break; |
1899 | case FLOAT: |
1900 | float_alloc(current,i); |
1901 | break; |
1902 | case FCOMP: |
1903 | fcomp_alloc(current,i); |
1904 | break; |
b9b61529 |
1905 | case C2OP: |
1906 | c2op_alloc(current,i); |
1907 | break; |
57871462 |
1908 | } |
1909 | } |
1910 | |
1911 | // Special case where a branch and delay slot span two pages in virtual memory |
1912 | static void pagespan_alloc(struct regstat *current,int i) |
1913 | { |
1914 | current->isconst=0; |
1915 | current->wasconst=0; |
1916 | regs[i].wasconst=0; |
1917 | alloc_all(current,i); |
1918 | alloc_cc(current,i); |
1919 | dirty_reg(current,CCREG); |
1920 | if(opcode[i]==3) // JAL |
1921 | { |
1922 | alloc_reg(current,i,31); |
1923 | dirty_reg(current,31); |
1924 | } |
1925 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR |
1926 | { |
1927 | alloc_reg(current,i,rs1[i]); |
5067f341 |
1928 | if (rt1[i]!=0) { |
1929 | alloc_reg(current,i,rt1[i]); |
1930 | dirty_reg(current,rt1[i]); |
57871462 |
1931 | } |
1932 | } |
1933 | if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL |
1934 | { |
1935 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1936 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1937 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1938 | { |
1939 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1940 | if(rs2[i]) alloc_reg64(current,i,rs2[i]); |
1941 | } |
1942 | } |
1943 | else |
1944 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL |
1945 | { |
1946 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1947 | if(!((current->is32>>rs1[i])&1)) |
1948 | { |
1949 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1950 | } |
1951 | } |
1952 | else |
1953 | if(opcode[i]==0x11) // BC1 |
1954 | { |
1955 | alloc_reg(current,i,FSREG); |
1956 | alloc_reg(current,i,CSREG); |
1957 | } |
1958 | //else ... |
1959 | } |
1960 | |
1961 | add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e) |
1962 | { |
1963 | stubs[stubcount][0]=type; |
1964 | stubs[stubcount][1]=addr; |
1965 | stubs[stubcount][2]=retaddr; |
1966 | stubs[stubcount][3]=a; |
1967 | stubs[stubcount][4]=b; |
1968 | stubs[stubcount][5]=c; |
1969 | stubs[stubcount][6]=d; |
1970 | stubs[stubcount][7]=e; |
1971 | stubcount++; |
1972 | } |
1973 | |
1974 | // Write out a single register |
1975 | void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32) |
1976 | { |
1977 | int hr; |
1978 | for(hr=0;hr<HOST_REGS;hr++) { |
1979 | if(hr!=EXCLUDE_REG) { |
1980 | if((regmap[hr]&63)==r) { |
1981 | if((dirty>>hr)&1) { |
1982 | if(regmap[hr]<64) { |
1983 | emit_storereg(r,hr); |
24385cae |
1984 | #ifndef FORCE32 |
57871462 |
1985 | if((is32>>regmap[hr])&1) { |
1986 | emit_sarimm(hr,31,hr); |
1987 | emit_storereg(r|64,hr); |
1988 | } |
24385cae |
1989 | #endif |
57871462 |
1990 | }else{ |
1991 | emit_storereg(r|64,hr); |
1992 | } |
1993 | } |
1994 | } |
1995 | } |
1996 | } |
1997 | } |
1998 | |
1999 | int mchecksum() |
2000 | { |
2001 | //if(!tracedebug) return 0; |
2002 | int i; |
2003 | int sum=0; |
2004 | for(i=0;i<2097152;i++) { |
2005 | unsigned int temp=sum; |
2006 | sum<<=1; |
2007 | sum|=(~temp)>>31; |
2008 | sum^=((u_int *)rdram)[i]; |
2009 | } |
2010 | return sum; |
2011 | } |
2012 | int rchecksum() |
2013 | { |
2014 | int i; |
2015 | int sum=0; |
2016 | for(i=0;i<64;i++) |
2017 | sum^=((u_int *)reg)[i]; |
2018 | return sum; |
2019 | } |
57871462 |
2020 | void rlist() |
2021 | { |
2022 | int i; |
2023 | printf("TRACE: "); |
2024 | for(i=0;i<32;i++) |
2025 | printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]); |
2026 | printf("\n"); |
3d624f89 |
2027 | #ifndef DISABLE_COP1 |
57871462 |
2028 | printf("TRACE: "); |
2029 | for(i=0;i<32;i++) |
2030 | printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i])); |
2031 | printf("\n"); |
3d624f89 |
2032 | #endif |
57871462 |
2033 | } |
2034 | |
2035 | void enabletrace() |
2036 | { |
2037 | tracedebug=1; |
2038 | } |
2039 | |
2040 | void memdebug(int i) |
2041 | { |
2042 | //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]); |
2043 | //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum()); |
2044 | //rlist(); |
2045 | //if(tracedebug) { |
2046 | //if(Count>=-2084597794) { |
2047 | if((signed int)Count>=-2084597794&&(signed int)Count<0) { |
2048 | //if(0) { |
2049 | printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); |
2050 | //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status); |
2051 | //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]); |
2052 | rlist(); |
2053 | #ifdef __i386__ |
2054 | printf("TRACE: %x\n",(&i)[-1]); |
2055 | #endif |
2056 | #ifdef __arm__ |
2057 | int j; |
2058 | printf("TRACE: %x \n",(&j)[10]); |
2059 | printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]); |
2060 | #endif |
2061 | //fflush(stdout); |
2062 | } |
2063 | //printf("TRACE: %x\n",(&i)[-1]); |
2064 | } |
2065 | |
2066 | void tlb_debug(u_int cause, u_int addr, u_int iaddr) |
2067 | { |
2068 | printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause); |
2069 | } |
2070 | |
2071 | void alu_assemble(int i,struct regstat *i_regs) |
2072 | { |
2073 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
2074 | if(rt1[i]) { |
2075 | signed char s1,s2,t; |
2076 | t=get_reg(i_regs->regmap,rt1[i]); |
2077 | if(t>=0) { |
2078 | s1=get_reg(i_regs->regmap,rs1[i]); |
2079 | s2=get_reg(i_regs->regmap,rs2[i]); |
2080 | if(rs1[i]&&rs2[i]) { |
2081 | assert(s1>=0); |
2082 | assert(s2>=0); |
2083 | if(opcode2[i]&2) emit_sub(s1,s2,t); |
2084 | else emit_add(s1,s2,t); |
2085 | } |
2086 | else if(rs1[i]) { |
2087 | if(s1>=0) emit_mov(s1,t); |
2088 | else emit_loadreg(rs1[i],t); |
2089 | } |
2090 | else if(rs2[i]) { |
2091 | if(s2>=0) { |
2092 | if(opcode2[i]&2) emit_neg(s2,t); |
2093 | else emit_mov(s2,t); |
2094 | } |
2095 | else { |
2096 | emit_loadreg(rs2[i],t); |
2097 | if(opcode2[i]&2) emit_neg(t,t); |
2098 | } |
2099 | } |
2100 | else emit_zeroreg(t); |
2101 | } |
2102 | } |
2103 | } |
2104 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
2105 | if(rt1[i]) { |
2106 | signed char s1l,s2l,s1h,s2h,tl,th; |
2107 | tl=get_reg(i_regs->regmap,rt1[i]); |
2108 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2109 | if(tl>=0) { |
2110 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2111 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2112 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2113 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2114 | if(rs1[i]&&rs2[i]) { |
2115 | assert(s1l>=0); |
2116 | assert(s2l>=0); |
2117 | if(opcode2[i]&2) emit_subs(s1l,s2l,tl); |
2118 | else emit_adds(s1l,s2l,tl); |
2119 | if(th>=0) { |
2120 | #ifdef INVERTED_CARRY |
2121 | if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);} |
2122 | #else |
2123 | if(opcode2[i]&2) emit_sbc(s1h,s2h,th); |
2124 | #endif |
2125 | else emit_add(s1h,s2h,th); |
2126 | } |
2127 | } |
2128 | else if(rs1[i]) { |
2129 | if(s1l>=0) emit_mov(s1l,tl); |
2130 | else emit_loadreg(rs1[i],tl); |
2131 | if(th>=0) { |
2132 | if(s1h>=0) emit_mov(s1h,th); |
2133 | else emit_loadreg(rs1[i]|64,th); |
2134 | } |
2135 | } |
2136 | else if(rs2[i]) { |
2137 | if(s2l>=0) { |
2138 | if(opcode2[i]&2) emit_negs(s2l,tl); |
2139 | else emit_mov(s2l,tl); |
2140 | } |
2141 | else { |
2142 | emit_loadreg(rs2[i],tl); |
2143 | if(opcode2[i]&2) emit_negs(tl,tl); |
2144 | } |
2145 | if(th>=0) { |
2146 | #ifdef INVERTED_CARRY |
2147 | if(s2h>=0) emit_mov(s2h,th); |
2148 | else emit_loadreg(rs2[i]|64,th); |
2149 | if(opcode2[i]&2) { |
2150 | emit_adcimm(-1,th); // x86 has inverted carry flag |
2151 | emit_not(th,th); |
2152 | } |
2153 | #else |
2154 | if(opcode2[i]&2) { |
2155 | if(s2h>=0) emit_rscimm(s2h,0,th); |
2156 | else { |
2157 | emit_loadreg(rs2[i]|64,th); |
2158 | emit_rscimm(th,0,th); |
2159 | } |
2160 | }else{ |
2161 | if(s2h>=0) emit_mov(s2h,th); |
2162 | else emit_loadreg(rs2[i]|64,th); |
2163 | } |
2164 | #endif |
2165 | } |
2166 | } |
2167 | else { |
2168 | emit_zeroreg(tl); |
2169 | if(th>=0) emit_zeroreg(th); |
2170 | } |
2171 | } |
2172 | } |
2173 | } |
2174 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
2175 | if(rt1[i]) { |
2176 | signed char s1l,s1h,s2l,s2h,t; |
2177 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)) |
2178 | { |
2179 | t=get_reg(i_regs->regmap,rt1[i]); |
2180 | //assert(t>=0); |
2181 | if(t>=0) { |
2182 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2183 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2184 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2185 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2186 | if(rs2[i]==0) // rx<r0 |
2187 | { |
2188 | assert(s1h>=0); |
2189 | if(opcode2[i]==0x2a) // SLT |
2190 | emit_shrimm(s1h,31,t); |
2191 | else // SLTU (unsigned can not be less than zero) |
2192 | emit_zeroreg(t); |
2193 | } |
2194 | else if(rs1[i]==0) // r0<rx |
2195 | { |
2196 | assert(s2h>=0); |
2197 | if(opcode2[i]==0x2a) // SLT |
2198 | emit_set_gz64_32(s2h,s2l,t); |
2199 | else // SLTU (set if not zero) |
2200 | emit_set_nz64_32(s2h,s2l,t); |
2201 | } |
2202 | else { |
2203 | assert(s1l>=0);assert(s1h>=0); |
2204 | assert(s2l>=0);assert(s2h>=0); |
2205 | if(opcode2[i]==0x2a) // SLT |
2206 | emit_set_if_less64_32(s1h,s1l,s2h,s2l,t); |
2207 | else // SLTU |
2208 | emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t); |
2209 | } |
2210 | } |
2211 | } else { |
2212 | t=get_reg(i_regs->regmap,rt1[i]); |
2213 | //assert(t>=0); |
2214 | if(t>=0) { |
2215 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2216 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2217 | if(rs2[i]==0) // rx<r0 |
2218 | { |
2219 | assert(s1l>=0); |
2220 | if(opcode2[i]==0x2a) // SLT |
2221 | emit_shrimm(s1l,31,t); |
2222 | else // SLTU (unsigned can not be less than zero) |
2223 | emit_zeroreg(t); |
2224 | } |
2225 | else if(rs1[i]==0) // r0<rx |
2226 | { |
2227 | assert(s2l>=0); |
2228 | if(opcode2[i]==0x2a) // SLT |
2229 | emit_set_gz32(s2l,t); |
2230 | else // SLTU (set if not zero) |
2231 | emit_set_nz32(s2l,t); |
2232 | } |
2233 | else{ |
2234 | assert(s1l>=0);assert(s2l>=0); |
2235 | if(opcode2[i]==0x2a) // SLT |
2236 | emit_set_if_less32(s1l,s2l,t); |
2237 | else // SLTU |
2238 | emit_set_if_carry32(s1l,s2l,t); |
2239 | } |
2240 | } |
2241 | } |
2242 | } |
2243 | } |
2244 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
2245 | if(rt1[i]) { |
2246 | signed char s1l,s1h,s2l,s2h,th,tl; |
2247 | tl=get_reg(i_regs->regmap,rt1[i]); |
2248 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2249 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0) |
2250 | { |
2251 | assert(tl>=0); |
2252 | if(tl>=0) { |
2253 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2254 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2255 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2256 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2257 | if(rs1[i]&&rs2[i]) { |
2258 | assert(s1l>=0);assert(s1h>=0); |
2259 | assert(s2l>=0);assert(s2h>=0); |
2260 | if(opcode2[i]==0x24) { // AND |
2261 | emit_and(s1l,s2l,tl); |
2262 | emit_and(s1h,s2h,th); |
2263 | } else |
2264 | if(opcode2[i]==0x25) { // OR |
2265 | emit_or(s1l,s2l,tl); |
2266 | emit_or(s1h,s2h,th); |
2267 | } else |
2268 | if(opcode2[i]==0x26) { // XOR |
2269 | emit_xor(s1l,s2l,tl); |
2270 | emit_xor(s1h,s2h,th); |
2271 | } else |
2272 | if(opcode2[i]==0x27) { // NOR |
2273 | emit_or(s1l,s2l,tl); |
2274 | emit_or(s1h,s2h,th); |
2275 | emit_not(tl,tl); |
2276 | emit_not(th,th); |
2277 | } |
2278 | } |
2279 | else |
2280 | { |
2281 | if(opcode2[i]==0x24) { // AND |
2282 | emit_zeroreg(tl); |
2283 | emit_zeroreg(th); |
2284 | } else |
2285 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2286 | if(rs1[i]){ |
2287 | if(s1l>=0) emit_mov(s1l,tl); |
2288 | else emit_loadreg(rs1[i],tl); |
2289 | if(s1h>=0) emit_mov(s1h,th); |
2290 | else emit_loadreg(rs1[i]|64,th); |
2291 | } |
2292 | else |
2293 | if(rs2[i]){ |
2294 | if(s2l>=0) emit_mov(s2l,tl); |
2295 | else emit_loadreg(rs2[i],tl); |
2296 | if(s2h>=0) emit_mov(s2h,th); |
2297 | else emit_loadreg(rs2[i]|64,th); |
2298 | } |
2299 | else{ |
2300 | emit_zeroreg(tl); |
2301 | emit_zeroreg(th); |
2302 | } |
2303 | } else |
2304 | if(opcode2[i]==0x27) { // NOR |
2305 | if(rs1[i]){ |
2306 | if(s1l>=0) emit_not(s1l,tl); |
2307 | else{ |
2308 | emit_loadreg(rs1[i],tl); |
2309 | emit_not(tl,tl); |
2310 | } |
2311 | if(s1h>=0) emit_not(s1h,th); |
2312 | else{ |
2313 | emit_loadreg(rs1[i]|64,th); |
2314 | emit_not(th,th); |
2315 | } |
2316 | } |
2317 | else |
2318 | if(rs2[i]){ |
2319 | if(s2l>=0) emit_not(s2l,tl); |
2320 | else{ |
2321 | emit_loadreg(rs2[i],tl); |
2322 | emit_not(tl,tl); |
2323 | } |
2324 | if(s2h>=0) emit_not(s2h,th); |
2325 | else{ |
2326 | emit_loadreg(rs2[i]|64,th); |
2327 | emit_not(th,th); |
2328 | } |
2329 | } |
2330 | else { |
2331 | emit_movimm(-1,tl); |
2332 | emit_movimm(-1,th); |
2333 | } |
2334 | } |
2335 | } |
2336 | } |
2337 | } |
2338 | else |
2339 | { |
2340 | // 32 bit |
2341 | if(tl>=0) { |
2342 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2343 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2344 | if(rs1[i]&&rs2[i]) { |
2345 | assert(s1l>=0); |
2346 | assert(s2l>=0); |
2347 | if(opcode2[i]==0x24) { // AND |
2348 | emit_and(s1l,s2l,tl); |
2349 | } else |
2350 | if(opcode2[i]==0x25) { // OR |
2351 | emit_or(s1l,s2l,tl); |
2352 | } else |
2353 | if(opcode2[i]==0x26) { // XOR |
2354 | emit_xor(s1l,s2l,tl); |
2355 | } else |
2356 | if(opcode2[i]==0x27) { // NOR |
2357 | emit_or(s1l,s2l,tl); |
2358 | emit_not(tl,tl); |
2359 | } |
2360 | } |
2361 | else |
2362 | { |
2363 | if(opcode2[i]==0x24) { // AND |
2364 | emit_zeroreg(tl); |
2365 | } else |
2366 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2367 | if(rs1[i]){ |
2368 | if(s1l>=0) emit_mov(s1l,tl); |
2369 | else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry? |
2370 | } |
2371 | else |
2372 | if(rs2[i]){ |
2373 | if(s2l>=0) emit_mov(s2l,tl); |
2374 | else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry? |
2375 | } |
2376 | else emit_zeroreg(tl); |
2377 | } else |
2378 | if(opcode2[i]==0x27) { // NOR |
2379 | if(rs1[i]){ |
2380 | if(s1l>=0) emit_not(s1l,tl); |
2381 | else { |
2382 | emit_loadreg(rs1[i],tl); |
2383 | emit_not(tl,tl); |
2384 | } |
2385 | } |
2386 | else |
2387 | if(rs2[i]){ |
2388 | if(s2l>=0) emit_not(s2l,tl); |
2389 | else { |
2390 | emit_loadreg(rs2[i],tl); |
2391 | emit_not(tl,tl); |
2392 | } |
2393 | } |
2394 | else emit_movimm(-1,tl); |
2395 | } |
2396 | } |
2397 | } |
2398 | } |
2399 | } |
2400 | } |
2401 | } |
2402 | |
2403 | void imm16_assemble(int i,struct regstat *i_regs) |
2404 | { |
2405 | if (opcode[i]==0x0f) { // LUI |
2406 | if(rt1[i]) { |
2407 | signed char t; |
2408 | t=get_reg(i_regs->regmap,rt1[i]); |
2409 | //assert(t>=0); |
2410 | if(t>=0) { |
2411 | if(!((i_regs->isconst>>t)&1)) |
2412 | emit_movimm(imm[i]<<16,t); |
2413 | } |
2414 | } |
2415 | } |
2416 | if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
2417 | if(rt1[i]) { |
2418 | signed char s,t; |
2419 | t=get_reg(i_regs->regmap,rt1[i]); |
2420 | s=get_reg(i_regs->regmap,rs1[i]); |
2421 | if(rs1[i]) { |
2422 | //assert(t>=0); |
2423 | //assert(s>=0); |
2424 | if(t>=0) { |
2425 | if(!((i_regs->isconst>>t)&1)) { |
2426 | if(s<0) { |
2427 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2428 | emit_addimm(t,imm[i],t); |
2429 | }else{ |
2430 | if(!((i_regs->wasconst>>s)&1)) |
2431 | emit_addimm(s,imm[i],t); |
2432 | else |
2433 | emit_movimm(constmap[i][s]+imm[i],t); |
2434 | } |
2435 | } |
2436 | } |
2437 | } else { |
2438 | if(t>=0) { |
2439 | if(!((i_regs->isconst>>t)&1)) |
2440 | emit_movimm(imm[i],t); |
2441 | } |
2442 | } |
2443 | } |
2444 | } |
2445 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
2446 | if(rt1[i]) { |
2447 | signed char sh,sl,th,tl; |
2448 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2449 | tl=get_reg(i_regs->regmap,rt1[i]); |
2450 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2451 | sl=get_reg(i_regs->regmap,rs1[i]); |
2452 | if(tl>=0) { |
2453 | if(rs1[i]) { |
2454 | assert(sh>=0); |
2455 | assert(sl>=0); |
2456 | if(th>=0) { |
2457 | emit_addimm64_32(sh,sl,imm[i],th,tl); |
2458 | } |
2459 | else { |
2460 | emit_addimm(sl,imm[i],tl); |
2461 | } |
2462 | } else { |
2463 | emit_movimm(imm[i],tl); |
2464 | if(th>=0) emit_movimm(((signed int)imm[i])>>31,th); |
2465 | } |
2466 | } |
2467 | } |
2468 | } |
2469 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
2470 | if(rt1[i]) { |
2471 | //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug |
2472 | signed char sh,sl,t; |
2473 | t=get_reg(i_regs->regmap,rt1[i]); |
2474 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2475 | sl=get_reg(i_regs->regmap,rs1[i]); |
2476 | //assert(t>=0); |
2477 | if(t>=0) { |
2478 | if(rs1[i]>0) { |
2479 | if(sh<0) assert((i_regs->was32>>rs1[i])&1); |
2480 | if(sh<0||((i_regs->was32>>rs1[i])&1)) { |
2481 | if(opcode[i]==0x0a) { // SLTI |
2482 | if(sl<0) { |
2483 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2484 | emit_slti32(t,imm[i],t); |
2485 | }else{ |
2486 | emit_slti32(sl,imm[i],t); |
2487 | } |
2488 | } |
2489 | else { // SLTIU |
2490 | if(sl<0) { |
2491 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2492 | emit_sltiu32(t,imm[i],t); |
2493 | }else{ |
2494 | emit_sltiu32(sl,imm[i],t); |
2495 | } |
2496 | } |
2497 | }else{ // 64-bit |
2498 | assert(sl>=0); |
2499 | if(opcode[i]==0x0a) // SLTI |
2500 | emit_slti64_32(sh,sl,imm[i],t); |
2501 | else // SLTIU |
2502 | emit_sltiu64_32(sh,sl,imm[i],t); |
2503 | } |
2504 | }else{ |
2505 | // SLTI(U) with r0 is just stupid, |
2506 | // nonetheless examples can be found |
2507 | if(opcode[i]==0x0a) // SLTI |
2508 | if(0<imm[i]) emit_movimm(1,t); |
2509 | else emit_zeroreg(t); |
2510 | else // SLTIU |
2511 | { |
2512 | if(imm[i]) emit_movimm(1,t); |
2513 | else emit_zeroreg(t); |
2514 | } |
2515 | } |
2516 | } |
2517 | } |
2518 | } |
2519 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
2520 | if(rt1[i]) { |
2521 | signed char sh,sl,th,tl; |
2522 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2523 | tl=get_reg(i_regs->regmap,rt1[i]); |
2524 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2525 | sl=get_reg(i_regs->regmap,rs1[i]); |
2526 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
2527 | if(opcode[i]==0x0c) //ANDI |
2528 | { |
2529 | if(rs1[i]) { |
2530 | if(sl<0) { |
2531 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2532 | emit_andimm(tl,imm[i],tl); |
2533 | }else{ |
2534 | if(!((i_regs->wasconst>>sl)&1)) |
2535 | emit_andimm(sl,imm[i],tl); |
2536 | else |
2537 | emit_movimm(constmap[i][sl]&imm[i],tl); |
2538 | } |
2539 | } |
2540 | else |
2541 | emit_zeroreg(tl); |
2542 | if(th>=0) emit_zeroreg(th); |
2543 | } |
2544 | else |
2545 | { |
2546 | if(rs1[i]) { |
2547 | if(sl<0) { |
2548 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2549 | } |
2550 | if(th>=0) { |
2551 | if(sh<0) { |
2552 | emit_loadreg(rs1[i]|64,th); |
2553 | }else{ |
2554 | emit_mov(sh,th); |
2555 | } |
2556 | } |
2557 | if(opcode[i]==0x0d) //ORI |
2558 | if(sl<0) { |
2559 | emit_orimm(tl,imm[i],tl); |
2560 | }else{ |
2561 | if(!((i_regs->wasconst>>sl)&1)) |
2562 | emit_orimm(sl,imm[i],tl); |
2563 | else |
2564 | emit_movimm(constmap[i][sl]|imm[i],tl); |
2565 | } |
2566 | if(opcode[i]==0x0e) //XORI |
2567 | if(sl<0) { |
2568 | emit_xorimm(tl,imm[i],tl); |
2569 | }else{ |
2570 | if(!((i_regs->wasconst>>sl)&1)) |
2571 | emit_xorimm(sl,imm[i],tl); |
2572 | else |
2573 | emit_movimm(constmap[i][sl]^imm[i],tl); |
2574 | } |
2575 | } |
2576 | else { |
2577 | emit_movimm(imm[i],tl); |
2578 | if(th>=0) emit_zeroreg(th); |
2579 | } |
2580 | } |
2581 | } |
2582 | } |
2583 | } |
2584 | } |
2585 | |
2586 | void shiftimm_assemble(int i,struct regstat *i_regs) |
2587 | { |
2588 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
2589 | { |
2590 | if(rt1[i]) { |
2591 | signed char s,t; |
2592 | t=get_reg(i_regs->regmap,rt1[i]); |
2593 | s=get_reg(i_regs->regmap,rs1[i]); |
2594 | //assert(t>=0); |
2595 | if(t>=0){ |
2596 | if(rs1[i]==0) |
2597 | { |
2598 | emit_zeroreg(t); |
2599 | } |
2600 | else |
2601 | { |
2602 | if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2603 | if(imm[i]) { |
2604 | if(opcode2[i]==0) // SLL |
2605 | { |
2606 | emit_shlimm(s<0?t:s,imm[i],t); |
2607 | } |
2608 | if(opcode2[i]==2) // SRL |
2609 | { |
2610 | emit_shrimm(s<0?t:s,imm[i],t); |
2611 | } |
2612 | if(opcode2[i]==3) // SRA |
2613 | { |
2614 | emit_sarimm(s<0?t:s,imm[i],t); |
2615 | } |
2616 | }else{ |
2617 | // Shift by zero |
2618 | if(s>=0 && s!=t) emit_mov(s,t); |
2619 | } |
2620 | } |
2621 | } |
2622 | //emit_storereg(rt1[i],t); //DEBUG |
2623 | } |
2624 | } |
2625 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
2626 | { |
2627 | if(rt1[i]) { |
2628 | signed char sh,sl,th,tl; |
2629 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2630 | tl=get_reg(i_regs->regmap,rt1[i]); |
2631 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2632 | sl=get_reg(i_regs->regmap,rs1[i]); |
2633 | if(tl>=0) { |
2634 | if(rs1[i]==0) |
2635 | { |
2636 | emit_zeroreg(tl); |
2637 | if(th>=0) emit_zeroreg(th); |
2638 | } |
2639 | else |
2640 | { |
2641 | assert(sl>=0); |
2642 | assert(sh>=0); |
2643 | if(imm[i]) { |
2644 | if(opcode2[i]==0x38) // DSLL |
2645 | { |
2646 | if(th>=0) emit_shldimm(sh,sl,imm[i],th); |
2647 | emit_shlimm(sl,imm[i],tl); |
2648 | } |
2649 | if(opcode2[i]==0x3a) // DSRL |
2650 | { |
2651 | emit_shrdimm(sl,sh,imm[i],tl); |
2652 | if(th>=0) emit_shrimm(sh,imm[i],th); |
2653 | } |
2654 | if(opcode2[i]==0x3b) // DSRA |
2655 | { |
2656 | emit_shrdimm(sl,sh,imm[i],tl); |
2657 | if(th>=0) emit_sarimm(sh,imm[i],th); |
2658 | } |
2659 | }else{ |
2660 | // Shift by zero |
2661 | if(sl!=tl) emit_mov(sl,tl); |
2662 | if(th>=0&&sh!=th) emit_mov(sh,th); |
2663 | } |
2664 | } |
2665 | } |
2666 | } |
2667 | } |
2668 | if(opcode2[i]==0x3c) // DSLL32 |
2669 | { |
2670 | if(rt1[i]) { |
2671 | signed char sl,tl,th; |
2672 | tl=get_reg(i_regs->regmap,rt1[i]); |
2673 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2674 | sl=get_reg(i_regs->regmap,rs1[i]); |
2675 | if(th>=0||tl>=0){ |
2676 | assert(tl>=0); |
2677 | assert(th>=0); |
2678 | assert(sl>=0); |
2679 | emit_mov(sl,th); |
2680 | emit_zeroreg(tl); |
2681 | if(imm[i]>32) |
2682 | { |
2683 | emit_shlimm(th,imm[i]&31,th); |
2684 | } |
2685 | } |
2686 | } |
2687 | } |
2688 | if(opcode2[i]==0x3e) // DSRL32 |
2689 | { |
2690 | if(rt1[i]) { |
2691 | signed char sh,tl,th; |
2692 | tl=get_reg(i_regs->regmap,rt1[i]); |
2693 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2694 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2695 | if(tl>=0){ |
2696 | assert(sh>=0); |
2697 | emit_mov(sh,tl); |
2698 | if(th>=0) emit_zeroreg(th); |
2699 | if(imm[i]>32) |
2700 | { |
2701 | emit_shrimm(tl,imm[i]&31,tl); |
2702 | } |
2703 | } |
2704 | } |
2705 | } |
2706 | if(opcode2[i]==0x3f) // DSRA32 |
2707 | { |
2708 | if(rt1[i]) { |
2709 | signed char sh,tl; |
2710 | tl=get_reg(i_regs->regmap,rt1[i]); |
2711 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2712 | if(tl>=0){ |
2713 | assert(sh>=0); |
2714 | emit_mov(sh,tl); |
2715 | if(imm[i]>32) |
2716 | { |
2717 | emit_sarimm(tl,imm[i]&31,tl); |
2718 | } |
2719 | } |
2720 | } |
2721 | } |
2722 | } |
2723 | |
2724 | #ifndef shift_assemble |
2725 | void shift_assemble(int i,struct regstat *i_regs) |
2726 | { |
2727 | printf("Need shift_assemble for this architecture.\n"); |
2728 | exit(1); |
2729 | } |
2730 | #endif |
2731 | |
2732 | void load_assemble(int i,struct regstat *i_regs) |
2733 | { |
2734 | int s,th,tl,addr,map=-1; |
2735 | int offset; |
2736 | int jaddr=0; |
5bf843dc |
2737 | int memtarget=0,c=0; |
57871462 |
2738 | u_int hr,reglist=0; |
2739 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2740 | tl=get_reg(i_regs->regmap,rt1[i]); |
2741 | s=get_reg(i_regs->regmap,rs1[i]); |
2742 | offset=imm[i]; |
2743 | for(hr=0;hr<HOST_REGS;hr++) { |
2744 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
2745 | } |
2746 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2747 | if(s>=0) { |
2748 | c=(i_regs->wasconst>>s)&1; |
4cb76aa4 |
2749 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
57871462 |
2750 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
2751 | } |
57871462 |
2752 | //printf("load_assemble: c=%d\n",c); |
2753 | //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); |
2754 | // FIXME: Even if the load is a NOP, we should check for pagefaults... |
5bf843dc |
2755 | #ifdef PCSX |
2756 | if(tl<0) { |
2757 | if(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) { |
2758 | // could be FIFO, must perform the read |
2759 | assem_debug("(forced read)\n"); |
2760 | tl=get_reg(i_regs->regmap,-1); |
2761 | assert(tl>=0); |
2762 | } |
2763 | } |
2764 | if(offset||s<0||c) addr=tl; |
2765 | else addr=s; |
2766 | #endif |
57871462 |
2767 | if(tl>=0) { |
2768 | //assert(tl>=0); |
2769 | //assert(rt1[i]); |
2770 | reglist&=~(1<<tl); |
2771 | if(th>=0) reglist&=~(1<<th); |
2772 | if(!using_tlb) { |
2773 | if(!c) { |
2774 | //#define R29_HACK 1 |
2775 | #ifdef R29_HACK |
2776 | // Strmnnrmn's speed hack |
4cb76aa4 |
2777 | if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
57871462 |
2778 | #endif |
2779 | { |
4cb76aa4 |
2780 | emit_cmpimm(addr,RAM_SIZE); |
57871462 |
2781 | jaddr=(int)out; |
2782 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
2783 | // Hint to branch predictor that the branch is unlikely to be taken |
2784 | if(rs1[i]>=28) |
2785 | emit_jno_unlikely(0); |
2786 | else |
2787 | #endif |
2788 | emit_jno(0); |
2789 | } |
2790 | } |
2791 | }else{ // using tlb |
2792 | int x=0; |
2793 | if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU |
2794 | if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU |
2795 | map=get_reg(i_regs->regmap,TLREG); |
2796 | assert(map>=0); |
2797 | map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset); |
2798 | do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr); |
2799 | } |
2800 | if (opcode[i]==0x20) { // LB |
2801 | if(!c||memtarget) { |
2802 | #ifdef HOST_IMM_ADDR32 |
2803 | if(c) |
2804 | emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2805 | else |
2806 | #endif |
2807 | { |
2808 | //emit_xorimm(addr,3,tl); |
2809 | //gen_tlb_addr_r(tl,map); |
2810 | //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl); |
2811 | int x=0; |
2002a1db |
2812 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
2813 | if(!c) emit_xorimm(addr,3,tl); |
2814 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2002a1db |
2815 | #else |
2816 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
2817 | else if (tl!=addr) emit_mov(addr,tl); |
2818 | #endif |
57871462 |
2819 | emit_movsbl_indexed_tlb(x,tl,map,tl); |
2820 | } |
2821 | if(jaddr) |
2822 | add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2823 | } |
2824 | else |
2825 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2826 | } |
2827 | if (opcode[i]==0x21) { // LH |
2828 | if(!c||memtarget) { |
2829 | #ifdef HOST_IMM_ADDR32 |
2830 | if(c) |
2831 | emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl); |
2832 | else |
2833 | #endif |
2834 | { |
2835 | int x=0; |
2002a1db |
2836 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
2837 | if(!c) emit_xorimm(addr,2,tl); |
2838 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2002a1db |
2839 | #else |
2840 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
2841 | else if (tl!=addr) emit_mov(addr,tl); |
2842 | #endif |
57871462 |
2843 | //#ifdef |
2844 | //emit_movswl_indexed_tlb(x,tl,map,tl); |
2845 | //else |
2846 | if(map>=0) { |
2847 | gen_tlb_addr_r(tl,map); |
2848 | emit_movswl_indexed(x,tl,tl); |
2849 | }else |
2850 | emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl); |
2851 | } |
2852 | if(jaddr) |
2853 | add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2854 | } |
2855 | else |
2856 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2857 | } |
2858 | if (opcode[i]==0x23) { // LW |
2859 | if(!c||memtarget) { |
2860 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2861 | #ifdef HOST_IMM_ADDR32 |
2862 | if(c) |
2863 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2864 | else |
2865 | #endif |
2866 | emit_readword_indexed_tlb(0,addr,map,tl); |
2867 | if(jaddr) |
2868 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2869 | } |
2870 | else |
2871 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2872 | } |
2873 | if (opcode[i]==0x24) { // LBU |
2874 | if(!c||memtarget) { |
2875 | #ifdef HOST_IMM_ADDR32 |
2876 | if(c) |
2877 | emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2878 | else |
2879 | #endif |
2880 | { |
2881 | //emit_xorimm(addr,3,tl); |
2882 | //gen_tlb_addr_r(tl,map); |
2883 | //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl); |
2884 | int x=0; |
2002a1db |
2885 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
2886 | if(!c) emit_xorimm(addr,3,tl); |
2887 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2002a1db |
2888 | #else |
2889 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
2890 | else if (tl!=addr) emit_mov(addr,tl); |
2891 | #endif |
57871462 |
2892 | emit_movzbl_indexed_tlb(x,tl,map,tl); |
2893 | } |
2894 | if(jaddr) |
2895 | add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2896 | } |
2897 | else |
2898 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2899 | } |
2900 | if (opcode[i]==0x25) { // LHU |
2901 | if(!c||memtarget) { |
2902 | #ifdef HOST_IMM_ADDR32 |
2903 | if(c) |
2904 | emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl); |
2905 | else |
2906 | #endif |
2907 | { |
2908 | int x=0; |
2002a1db |
2909 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
2910 | if(!c) emit_xorimm(addr,2,tl); |
2911 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2002a1db |
2912 | #else |
2913 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
2914 | else if (tl!=addr) emit_mov(addr,tl); |
2915 | #endif |
57871462 |
2916 | //#ifdef |
2917 | //emit_movzwl_indexed_tlb(x,tl,map,tl); |
2918 | //#else |
2919 | if(map>=0) { |
2920 | gen_tlb_addr_r(tl,map); |
2921 | emit_movzwl_indexed(x,tl,tl); |
2922 | }else |
2923 | emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl); |
2924 | if(jaddr) |
2925 | add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2926 | } |
2927 | } |
2928 | else |
2929 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2930 | } |
2931 | if (opcode[i]==0x27) { // LWU |
2932 | assert(th>=0); |
2933 | if(!c||memtarget) { |
2934 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2935 | #ifdef HOST_IMM_ADDR32 |
2936 | if(c) |
2937 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2938 | else |
2939 | #endif |
2940 | emit_readword_indexed_tlb(0,addr,map,tl); |
2941 | if(jaddr) |
2942 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2943 | } |
2944 | else { |
2945 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2946 | } |
2947 | emit_zeroreg(th); |
2948 | } |
2949 | if (opcode[i]==0x37) { // LD |
2950 | if(!c||memtarget) { |
2951 | //gen_tlb_addr_r(tl,map); |
2952 | //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th); |
2953 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl); |
2954 | #ifdef HOST_IMM_ADDR32 |
2955 | if(c) |
2956 | emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); |
2957 | else |
2958 | #endif |
2959 | emit_readdword_indexed_tlb(0,addr,map,th,tl); |
2960 | if(jaddr) |
2961 | add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2962 | } |
2963 | else |
2964 | inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2965 | } |
2966 | //emit_storereg(rt1[i],tl); // DEBUG |
2967 | } |
2968 | //if(opcode[i]==0x23) |
2969 | //if(opcode[i]==0x24) |
2970 | //if(opcode[i]==0x23||opcode[i]==0x24) |
2971 | /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24) |
2972 | { |
2973 | //emit_pusha(); |
2974 | save_regs(0x100f); |
2975 | emit_readword((int)&last_count,ECX); |
2976 | #ifdef __i386__ |
2977 | if(get_reg(i_regs->regmap,CCREG)<0) |
2978 | emit_loadreg(CCREG,HOST_CCREG); |
2979 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
2980 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
2981 | emit_writeword(HOST_CCREG,(int)&Count); |
2982 | #endif |
2983 | #ifdef __arm__ |
2984 | if(get_reg(i_regs->regmap,CCREG)<0) |
2985 | emit_loadreg(CCREG,0); |
2986 | else |
2987 | emit_mov(HOST_CCREG,0); |
2988 | emit_add(0,ECX,0); |
2989 | emit_addimm(0,2*ccadj[i],0); |
2990 | emit_writeword(0,(int)&Count); |
2991 | #endif |
2992 | emit_call((int)memdebug); |
2993 | //emit_popa(); |
2994 | restore_regs(0x100f); |
2995 | }/**/ |
2996 | } |
2997 | |
2998 | #ifndef loadlr_assemble |
2999 | void loadlr_assemble(int i,struct regstat *i_regs) |
3000 | { |
3001 | printf("Need loadlr_assemble for this architecture.\n"); |
3002 | exit(1); |
3003 | } |
3004 | #endif |
3005 | |
3006 | void store_assemble(int i,struct regstat *i_regs) |
3007 | { |
3008 | int s,th,tl,map=-1; |
3009 | int addr,temp; |
3010 | int offset; |
3011 | int jaddr=0,jaddr2,type; |
666a299d |
3012 | int memtarget=0,c=0; |
57871462 |
3013 | int agr=AGEN1+(i&1); |
3014 | u_int hr,reglist=0; |
3015 | th=get_reg(i_regs->regmap,rs2[i]|64); |
3016 | tl=get_reg(i_regs->regmap,rs2[i]); |
3017 | s=get_reg(i_regs->regmap,rs1[i]); |
3018 | temp=get_reg(i_regs->regmap,agr); |
3019 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3020 | offset=imm[i]; |
3021 | if(s>=0) { |
3022 | c=(i_regs->wasconst>>s)&1; |
4cb76aa4 |
3023 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
57871462 |
3024 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
3025 | } |
3026 | assert(tl>=0); |
3027 | assert(temp>=0); |
3028 | for(hr=0;hr<HOST_REGS;hr++) { |
3029 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3030 | } |
3031 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3032 | if(offset||s<0||c) addr=temp; |
3033 | else addr=s; |
3034 | if(!using_tlb) { |
3035 | if(!c) { |
3036 | #ifdef R29_HACK |
3037 | // Strmnnrmn's speed hack |
3038 | memtarget=1; |
4cb76aa4 |
3039 | if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
57871462 |
3040 | #endif |
4cb76aa4 |
3041 | emit_cmpimm(addr,RAM_SIZE); |
57871462 |
3042 | #ifdef DESTRUCTIVE_SHIFT |
3043 | if(s==addr) emit_mov(s,temp); |
3044 | #endif |
3045 | #ifdef R29_HACK |
4cb76aa4 |
3046 | if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
57871462 |
3047 | #endif |
3048 | { |
3049 | jaddr=(int)out; |
3050 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
3051 | // Hint to branch predictor that the branch is unlikely to be taken |
3052 | if(rs1[i]>=28) |
3053 | emit_jno_unlikely(0); |
3054 | else |
3055 | #endif |
3056 | emit_jno(0); |
3057 | } |
3058 | } |
3059 | }else{ // using tlb |
3060 | int x=0; |
3061 | if (opcode[i]==0x28) x=3; // SB |
3062 | if (opcode[i]==0x29) x=2; // SH |
3063 | map=get_reg(i_regs->regmap,TLREG); |
3064 | assert(map>=0); |
3065 | map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset); |
3066 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
3067 | } |
3068 | |
3069 | if (opcode[i]==0x28) { // SB |
3070 | if(!c||memtarget) { |
3071 | int x=0; |
2002a1db |
3072 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
3073 | if(!c) emit_xorimm(addr,3,temp); |
3074 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2002a1db |
3075 | #else |
3076 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
3077 | else if (addr!=temp) emit_mov(addr,temp); |
3078 | #endif |
57871462 |
3079 | //gen_tlb_addr_w(temp,map); |
3080 | //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp); |
3081 | emit_writebyte_indexed_tlb(tl,x,temp,map,temp); |
3082 | } |
3083 | type=STOREB_STUB; |
3084 | } |
3085 | if (opcode[i]==0x29) { // SH |
3086 | if(!c||memtarget) { |
3087 | int x=0; |
2002a1db |
3088 | #ifdef BIG_ENDIAN_MIPS |
57871462 |
3089 | if(!c) emit_xorimm(addr,2,temp); |
3090 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2002a1db |
3091 | #else |
3092 | if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset); |
3093 | else if (addr!=temp) emit_mov(addr,temp); |
3094 | #endif |
57871462 |
3095 | //#ifdef |
3096 | //emit_writehword_indexed_tlb(tl,x,temp,map,temp); |
3097 | //#else |
3098 | if(map>=0) { |
3099 | gen_tlb_addr_w(temp,map); |
3100 | emit_writehword_indexed(tl,x,temp); |
3101 | }else |
3102 | emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp); |
3103 | } |
3104 | type=STOREH_STUB; |
3105 | } |
3106 | if (opcode[i]==0x2B) { // SW |
3107 | if(!c||memtarget) |
3108 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr); |
3109 | emit_writeword_indexed_tlb(tl,0,addr,map,temp); |
3110 | type=STOREW_STUB; |
3111 | } |
3112 | if (opcode[i]==0x3F) { // SD |
3113 | if(!c||memtarget) { |
3114 | if(rs2[i]) { |
3115 | assert(th>=0); |
3116 | //emit_writeword_indexed(th,(int)rdram-0x80000000,addr); |
3117 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr); |
3118 | emit_writedword_indexed_tlb(th,tl,0,addr,map,temp); |
3119 | }else{ |
3120 | // Store zero |
3121 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); |
3122 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); |
3123 | emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp); |
3124 | } |
3125 | } |
3126 | type=STORED_STUB; |
3127 | } |
666a299d |
3128 | if(!using_tlb&&(!c||memtarget)) |
3129 | // addr could be a temp, make sure it survives STORE*_STUB |
3130 | reglist|=1<<addr; |
57871462 |
3131 | if(jaddr) { |
3132 | add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
3133 | } else if(!memtarget) { |
3134 | inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist); |
3135 | } |
3136 | if(!using_tlb) { |
3137 | if(!c||memtarget) { |
3138 | #ifdef DESTRUCTIVE_SHIFT |
3139 | // The x86 shift operation is 'destructive'; it overwrites the |
3140 | // source register, so we need to make a copy first and use that. |
3141 | addr=temp; |
3142 | #endif |
3143 | #if defined(HOST_IMM8) |
3144 | int ir=get_reg(i_regs->regmap,INVCP); |
3145 | assert(ir>=0); |
3146 | emit_cmpmem_indexedsr12_reg(ir,addr,1); |
3147 | #else |
3148 | emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1); |
3149 | #endif |
3150 | jaddr2=(int)out; |
3151 | emit_jne(0); |
3152 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0); |
3153 | } |
3154 | } |
3155 | //if(opcode[i]==0x2B || opcode[i]==0x3F) |
3156 | //if(opcode[i]==0x2B || opcode[i]==0x28) |
3157 | //if(opcode[i]==0x2B || opcode[i]==0x29) |
3158 | //if(opcode[i]==0x2B) |
3159 | /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F) |
3160 | { |
3161 | //emit_pusha(); |
3162 | save_regs(0x100f); |
3163 | emit_readword((int)&last_count,ECX); |
3164 | #ifdef __i386__ |
3165 | if(get_reg(i_regs->regmap,CCREG)<0) |
3166 | emit_loadreg(CCREG,HOST_CCREG); |
3167 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3168 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3169 | emit_writeword(HOST_CCREG,(int)&Count); |
3170 | #endif |
3171 | #ifdef __arm__ |
3172 | if(get_reg(i_regs->regmap,CCREG)<0) |
3173 | emit_loadreg(CCREG,0); |
3174 | else |
3175 | emit_mov(HOST_CCREG,0); |
3176 | emit_add(0,ECX,0); |
3177 | emit_addimm(0,2*ccadj[i],0); |
3178 | emit_writeword(0,(int)&Count); |
3179 | #endif |
3180 | emit_call((int)memdebug); |
3181 | //emit_popa(); |
3182 | restore_regs(0x100f); |
3183 | }/**/ |
3184 | } |
3185 | |
3186 | void storelr_assemble(int i,struct regstat *i_regs) |
3187 | { |
3188 | int s,th,tl; |
3189 | int temp; |
3190 | int temp2; |
3191 | int offset; |
3192 | int jaddr=0,jaddr2; |
3193 | int case1,case2,case3; |
3194 | int done0,done1,done2; |
3195 | int memtarget,c=0; |
fab5d06d |
3196 | int agr=AGEN1+(i&1); |
57871462 |
3197 | u_int hr,reglist=0; |
3198 | th=get_reg(i_regs->regmap,rs2[i]|64); |
3199 | tl=get_reg(i_regs->regmap,rs2[i]); |
3200 | s=get_reg(i_regs->regmap,rs1[i]); |
fab5d06d |
3201 | temp=get_reg(i_regs->regmap,agr); |
3202 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
57871462 |
3203 | offset=imm[i]; |
3204 | if(s>=0) { |
3205 | c=(i_regs->isconst>>s)&1; |
4cb76aa4 |
3206 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; |
57871462 |
3207 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
3208 | } |
3209 | assert(tl>=0); |
3210 | for(hr=0;hr<HOST_REGS;hr++) { |
3211 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3212 | } |
3213 | if(tl>=0) { |
3214 | assert(temp>=0); |
3215 | if(!using_tlb) { |
3216 | if(!c) { |
4cb76aa4 |
3217 | emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); |
57871462 |
3218 | if(!offset&&s!=temp) emit_mov(s,temp); |
3219 | jaddr=(int)out; |
3220 | emit_jno(0); |
3221 | } |
3222 | else |
3223 | { |
3224 | if(!memtarget||!rs1[i]) { |
3225 | jaddr=(int)out; |
3226 | emit_jmp(0); |
3227 | } |
3228 | } |
3229 | if((u_int)rdram!=0x80000000) |
3230 | emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); |
3231 | }else{ // using tlb |
3232 | int map=get_reg(i_regs->regmap,TLREG); |
3233 | assert(map>=0); |
3234 | map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset); |
3235 | if(!c&&!offset&&s>=0) emit_mov(s,temp); |
3236 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
3237 | if(!jaddr&&!memtarget) { |
3238 | jaddr=(int)out; |
3239 | emit_jmp(0); |
3240 | } |
3241 | gen_tlb_addr_w(temp,map); |
3242 | } |
3243 | |
3244 | if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR |
3245 | temp2=get_reg(i_regs->regmap,FTEMP); |
3246 | if(!rs2[i]) temp2=th=tl; |
3247 | } |
3248 | |
2002a1db |
3249 | #ifndef BIG_ENDIAN_MIPS |
3250 | emit_xorimm(temp,3,temp); |
3251 | #endif |
57871462 |
3252 | emit_testimm(temp,2); |
3253 | case2=(int)out; |
3254 | emit_jne(0); |
3255 | emit_testimm(temp,1); |
3256 | case1=(int)out; |
3257 | emit_jne(0); |
3258 | // 0 |
3259 | if (opcode[i]==0x2A) { // SWL |
3260 | emit_writeword_indexed(tl,0,temp); |
3261 | } |
3262 | if (opcode[i]==0x2E) { // SWR |
3263 | emit_writebyte_indexed(tl,3,temp); |
3264 | } |
3265 | if (opcode[i]==0x2C) { // SDL |
3266 | emit_writeword_indexed(th,0,temp); |
3267 | if(rs2[i]) emit_mov(tl,temp2); |
3268 | } |
3269 | if (opcode[i]==0x2D) { // SDR |
3270 | emit_writebyte_indexed(tl,3,temp); |
3271 | if(rs2[i]) emit_shldimm(th,tl,24,temp2); |
3272 | } |
3273 | done0=(int)out; |
3274 | emit_jmp(0); |
3275 | // 1 |
3276 | set_jump_target(case1,(int)out); |
3277 | if (opcode[i]==0x2A) { // SWL |
3278 | // Write 3 msb into three least significant bytes |
3279 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3280 | emit_writehword_indexed(tl,-1,temp); |
3281 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3282 | emit_writebyte_indexed(tl,1,temp); |
3283 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3284 | } |
3285 | if (opcode[i]==0x2E) { // SWR |
3286 | // Write two lsb into two most significant bytes |
3287 | emit_writehword_indexed(tl,1,temp); |
3288 | } |
3289 | if (opcode[i]==0x2C) { // SDL |
3290 | if(rs2[i]) emit_shrdimm(tl,th,8,temp2); |
3291 | // Write 3 msb into three least significant bytes |
3292 | if(rs2[i]) emit_rorimm(th,8,th); |
3293 | emit_writehword_indexed(th,-1,temp); |
3294 | if(rs2[i]) emit_rorimm(th,16,th); |
3295 | emit_writebyte_indexed(th,1,temp); |
3296 | if(rs2[i]) emit_rorimm(th,8,th); |
3297 | } |
3298 | if (opcode[i]==0x2D) { // SDR |
3299 | if(rs2[i]) emit_shldimm(th,tl,16,temp2); |
3300 | // Write two lsb into two most significant bytes |
3301 | emit_writehword_indexed(tl,1,temp); |
3302 | } |
3303 | done1=(int)out; |
3304 | emit_jmp(0); |
3305 | // 2 |
3306 | set_jump_target(case2,(int)out); |
3307 | emit_testimm(temp,1); |
3308 | case3=(int)out; |
3309 | emit_jne(0); |
3310 | if (opcode[i]==0x2A) { // SWL |
3311 | // Write two msb into two least significant bytes |
3312 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3313 | emit_writehword_indexed(tl,-2,temp); |
3314 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3315 | } |
3316 | if (opcode[i]==0x2E) { // SWR |
3317 | // Write 3 lsb into three most significant bytes |
3318 | emit_writebyte_indexed(tl,-1,temp); |
3319 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3320 | emit_writehword_indexed(tl,0,temp); |
3321 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3322 | } |
3323 | if (opcode[i]==0x2C) { // SDL |
3324 | if(rs2[i]) emit_shrdimm(tl,th,16,temp2); |
3325 | // Write two msb into two least significant bytes |
3326 | if(rs2[i]) emit_rorimm(th,16,th); |
3327 | emit_writehword_indexed(th,-2,temp); |
3328 | if(rs2[i]) emit_rorimm(th,16,th); |
3329 | } |
3330 | if (opcode[i]==0x2D) { // SDR |
3331 | if(rs2[i]) emit_shldimm(th,tl,8,temp2); |
3332 | // Write 3 lsb into three most significant bytes |
3333 | emit_writebyte_indexed(tl,-1,temp); |
3334 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3335 | emit_writehword_indexed(tl,0,temp); |
3336 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3337 | } |
3338 | done2=(int)out; |
3339 | emit_jmp(0); |
3340 | // 3 |
3341 | set_jump_target(case3,(int)out); |
3342 | if (opcode[i]==0x2A) { // SWL |
3343 | // Write msb into least significant byte |
3344 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3345 | emit_writebyte_indexed(tl,-3,temp); |
3346 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3347 | } |
3348 | if (opcode[i]==0x2E) { // SWR |
3349 | // Write entire word |
3350 | emit_writeword_indexed(tl,-3,temp); |
3351 | } |
3352 | if (opcode[i]==0x2C) { // SDL |
3353 | if(rs2[i]) emit_shrdimm(tl,th,24,temp2); |
3354 | // Write msb into least significant byte |
3355 | if(rs2[i]) emit_rorimm(th,24,th); |
3356 | emit_writebyte_indexed(th,-3,temp); |
3357 | if(rs2[i]) emit_rorimm(th,8,th); |
3358 | } |
3359 | if (opcode[i]==0x2D) { // SDR |
3360 | if(rs2[i]) emit_mov(th,temp2); |
3361 | // Write entire word |
3362 | emit_writeword_indexed(tl,-3,temp); |
3363 | } |
3364 | set_jump_target(done0,(int)out); |
3365 | set_jump_target(done1,(int)out); |
3366 | set_jump_target(done2,(int)out); |
3367 | if (opcode[i]==0x2C) { // SDL |
3368 | emit_testimm(temp,4); |
3369 | done0=(int)out; |
3370 | emit_jne(0); |
3371 | emit_andimm(temp,~3,temp); |
3372 | emit_writeword_indexed(temp2,4,temp); |
3373 | set_jump_target(done0,(int)out); |
3374 | } |
3375 | if (opcode[i]==0x2D) { // SDR |
3376 | emit_testimm(temp,4); |
3377 | done0=(int)out; |
3378 | emit_jeq(0); |
3379 | emit_andimm(temp,~3,temp); |
3380 | emit_writeword_indexed(temp2,-4,temp); |
3381 | set_jump_target(done0,(int)out); |
3382 | } |
3383 | if(!c||!memtarget) |
b7918751 |
3384 | add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist); |
57871462 |
3385 | } |
3386 | if(!using_tlb) { |
3387 | emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp); |
3388 | #if defined(HOST_IMM8) |
3389 | int ir=get_reg(i_regs->regmap,INVCP); |
3390 | assert(ir>=0); |
3391 | emit_cmpmem_indexedsr12_reg(ir,temp,1); |
3392 | #else |
3393 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); |
3394 | #endif |
3395 | jaddr2=(int)out; |
3396 | emit_jne(0); |
3397 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
3398 | } |
3399 | /* |
3400 | emit_pusha(); |
3401 | //save_regs(0x100f); |
3402 | emit_readword((int)&last_count,ECX); |
3403 | if(get_reg(i_regs->regmap,CCREG)<0) |
3404 | emit_loadreg(CCREG,HOST_CCREG); |
3405 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3406 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3407 | emit_writeword(HOST_CCREG,(int)&Count); |
3408 | emit_call((int)memdebug); |
3409 | emit_popa(); |
3410 | //restore_regs(0x100f); |
3411 | /**/ |
3412 | } |
3413 | |
3414 | void c1ls_assemble(int i,struct regstat *i_regs) |
3415 | { |
3d624f89 |
3416 | #ifndef DISABLE_COP1 |
57871462 |
3417 | int s,th,tl; |
3418 | int temp,ar; |
3419 | int map=-1; |
3420 | int offset; |
3421 | int c=0; |
3422 | int jaddr,jaddr2=0,jaddr3,type; |
3423 | int agr=AGEN1+(i&1); |
3424 | u_int hr,reglist=0; |
3425 | th=get_reg(i_regs->regmap,FTEMP|64); |
3426 | tl=get_reg(i_regs->regmap,FTEMP); |
3427 | s=get_reg(i_regs->regmap,rs1[i]); |
3428 | temp=get_reg(i_regs->regmap,agr); |
3429 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3430 | offset=imm[i]; |
3431 | assert(tl>=0); |
3432 | assert(rs1[i]>0); |
|