drc: allow move-to-r0 condition
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
57871462 182
183 /* stubs */
184#define CC_STUB 1
185#define FP_STUB 2
186#define LOADB_STUB 3
187#define LOADH_STUB 4
188#define LOADW_STUB 5
189#define LOADD_STUB 6
190#define LOADBU_STUB 7
191#define LOADHU_STUB 8
192#define STOREB_STUB 9
193#define STOREH_STUB 10
194#define STOREW_STUB 11
195#define STORED_STUB 12
196#define STORELR_STUB 13
197#define INVCODE_STUB 14
198
199 /* branch codes */
200#define TAKEN 1
201#define NOTTAKEN 2
202#define NULLDS 3
203
204// asm linkage
205int new_recompile_block(int addr);
206void *get_addr_ht(u_int vaddr);
207void invalidate_block(u_int block);
208void invalidate_addr(u_int addr);
209void remove_hash(int vaddr);
210void jump_vaddr();
211void dyna_linker();
212void dyna_linker_ds();
213void verify_code();
214void verify_code_vm();
215void verify_code_ds();
216void cc_interrupt();
217void fp_exception();
218void fp_exception_ds();
219void jump_syscall();
7139f3c8 220void jump_syscall_hle();
57871462 221void jump_eret();
7139f3c8 222void jump_hlecall();
223void new_dyna_leave();
57871462 224
225// TLB
226void TLBWI_new();
227void TLBWR_new();
228void read_nomem_new();
229void read_nomemb_new();
230void read_nomemh_new();
231void read_nomemd_new();
232void write_nomem_new();
233void write_nomemb_new();
234void write_nomemh_new();
235void write_nomemd_new();
236void write_rdram_new();
237void write_rdramb_new();
238void write_rdramh_new();
239void write_rdramd_new();
240extern u_int memory_map[1048576];
241
242// Needed by assembler
243void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246void load_all_regs(signed char i_regmap[]);
247void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248void load_regs_entry(int t);
249void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
250
251int tracedebug=0;
252
253//#define DEBUG_CYCLE_COUNT 1
254
255void nullf() {}
256//#define assem_debug printf
257//#define inv_debug printf
258#define assem_debug nullf
259#define inv_debug nullf
260
94d23bb9 261static void tlb_hacks()
57871462 262{
94d23bb9 263#ifndef DISABLE_TLB
57871462 264 // Goldeneye hack
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
266 {
267 u_int addr;
268 int n;
269 switch (ROM_HEADER->Country_code&0xFF)
270 {
271 case 0x45: // U
272 addr=0x34b30;
273 break;
274 case 0x4A: // J
275 addr=0x34b70;
276 break;
277 case 0x50: // E
278 addr=0x329f0;
279 break;
280 default:
281 // Unknown country code
282 addr=0;
283 break;
284 }
285 u_int rom_addr=(u_int)rom;
286 #ifdef ROM_COPY
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
297 }
298 #endif
299 if(addr) {
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
302 }
303 }
304 }
94d23bb9 305#endif
57871462 306}
307
94d23bb9 308static u_int get_page(u_int vaddr)
57871462 309{
310 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 311#ifndef DISABLE_TLB
57871462 312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 313#endif
57871462 314 if(page>2048) page=2048+(page&2047);
94d23bb9 315 return page;
316}
317
318static u_int get_vpage(u_int vaddr)
319{
320 u_int vpage=(vaddr^0x80000000)>>12;
321#ifndef DISABLE_TLB
57871462 322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 323#endif
57871462 324 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 325 return vpage;
326}
327
328// Get address from virtual address
329// This is called from the recompiled JR/JALR instructions
330void *get_addr(u_int vaddr)
331{
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
57871462 334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
336 head=jump_in[page];
337 while(head!=NULL) {
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
341 ht_bin[3]=ht_bin[1];
342 ht_bin[2]=ht_bin[0];
343 ht_bin[1]=(int)head->addr;
344 ht_bin[0]=vaddr;
345 return head->addr;
346 }
347 head=head->next;
348 }
349 head=jump_dirty[vpage];
350 while(head!=NULL) {
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
359 if(vpage<2048) {
94d23bb9 360#ifndef DISABLE_TLB
57871462 361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
364 }
94d23bb9 365#endif
57871462 366 restore_candidate[vpage>>3]|=1<<(vpage&7);
367 }
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
372 }
373 else
374 {
375 ht_bin[3]=ht_bin[1];
376 ht_bin[2]=ht_bin[0];
377 ht_bin[1]=(int)head->addr;
378 ht_bin[0]=vaddr;
379 }
380 return head->addr;
381 }
382 }
383 head=head->next;
384 }
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
389 Status|=2;
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
392 BadVAddr=(vaddr&~1);
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
396}
397// Look up address in hash table first
398void *get_addr_ht(u_int vaddr)
399{
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
405}
406
407void *get_addr_32(u_int vaddr,u_int flags)
408{
7139f3c8 409#ifdef FORCE32
410 return get_addr(vaddr);
560e4a12 411#else
57871462 412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
57871462 418 struct ll_entry *head;
419 head=jump_in[page];
420 while(head!=NULL) {
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
423 if(head->reg32==0) {
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==-1) {
426 ht_bin[1]=(int)head->addr;
427 ht_bin[0]=vaddr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
430 ht_bin[2]=vaddr;
431 }
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
435 //ht_bin[0]=vaddr;
436 }
437 return head->addr;
438 }
439 head=head->next;
440 }
441 head=jump_dirty[vpage];
442 while(head!=NULL) {
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
451 if(vpage<2048) {
94d23bb9 452#ifndef DISABLE_TLB
57871462 453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
456 }
94d23bb9 457#endif
57871462 458 restore_candidate[vpage>>3]|=1<<(vpage&7);
459 }
460 else restore_candidate[page>>3]|=1<<(page&7);
461 if(head->reg32==0) {
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
463 if(ht_bin[0]==-1) {
464 ht_bin[1]=(int)head->addr;
465 ht_bin[0]=vaddr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
468 ht_bin[2]=vaddr;
469 }
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
473 //ht_bin[0]=vaddr;
474 }
475 return head->addr;
476 }
477 }
478 head=head->next;
479 }
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
484 Status|=2;
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
487 BadVAddr=(vaddr&~1);
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
560e4a12 491#endif
57871462 492}
493
494void clear_all_regs(signed char regmap[])
495{
496 int hr;
497 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
498}
499
500signed char get_reg(signed char regmap[],int r)
501{
502 int hr;
503 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
504 return -1;
505}
506
507// Find a register that is available for two consecutive cycles
508signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
509{
510 int hr;
511 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
512 return -1;
513}
514
515int count_free_regs(signed char regmap[])
516{
517 int count=0;
518 int hr;
519 for(hr=0;hr<HOST_REGS;hr++)
520 {
521 if(hr!=EXCLUDE_REG) {
522 if(regmap[hr]<0) count++;
523 }
524 }
525 return count;
526}
527
528void dirty_reg(struct regstat *cur,signed char reg)
529{
530 int hr;
531 if(!reg) return;
532 for (hr=0;hr<HOST_REGS;hr++) {
533 if((cur->regmap[hr]&63)==reg) {
534 cur->dirty|=1<<hr;
535 }
536 }
537}
538
539// If we dirty the lower half of a 64 bit register which is now being
540// sign-extended, we need to dump the upper half.
541// Note: Do this only after completion of the instruction, because
542// some instructions may need to read the full 64-bit value even if
543// overwriting it (eg SLTI, DSRA32).
544static void flush_dirty_uppers(struct regstat *cur)
545{
546 int hr,reg;
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->dirty>>hr)&1) {
549 reg=cur->regmap[hr];
550 if(reg>=64)
551 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
552 }
553 }
554}
555
556void set_const(struct regstat *cur,signed char reg,uint64_t value)
557{
558 int hr;
559 if(!reg) return;
560 for (hr=0;hr<HOST_REGS;hr++) {
561 if(cur->regmap[hr]==reg) {
562 cur->isconst|=1<<hr;
563 cur->constmap[hr]=value;
564 }
565 else if((cur->regmap[hr]^64)==reg) {
566 cur->isconst|=1<<hr;
567 cur->constmap[hr]=value>>32;
568 }
569 }
570}
571
572void clear_const(struct regstat *cur,signed char reg)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if((cur->regmap[hr]&63)==reg) {
578 cur->isconst&=~(1<<hr);
579 }
580 }
581}
582
583int is_const(struct regstat *cur,signed char reg)
584{
585 int hr;
586 if(!reg) return 1;
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 return (cur->isconst>>hr)&1;
590 }
591 }
592 return 0;
593}
594uint64_t get_const(struct regstat *cur,signed char reg)
595{
596 int hr;
597 if(!reg) return 0;
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if(cur->regmap[hr]==reg) {
600 return cur->constmap[hr];
601 }
602 }
603 printf("Unknown constant in r%d\n",reg);
604 exit(1);
605}
606
607// Least soon needed registers
608// Look at the next ten instructions and see which registers
609// will be used. Try not to reallocate these.
610void lsn(u_char hsn[], int i, int *preferred_reg)
611{
612 int j;
613 int b=-1;
614 for(j=0;j<9;j++)
615 {
616 if(i+j>=slen) {
617 j=slen-i-1;
618 break;
619 }
620 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
621 {
622 // Don't go past an unconditonal jump
623 j++;
624 break;
625 }
626 }
627 for(;j>=0;j--)
628 {
629 if(rs1[i+j]) hsn[rs1[i+j]]=j;
630 if(rs2[i+j]) hsn[rs2[i+j]]=j;
631 if(rt1[i+j]) hsn[rt1[i+j]]=j;
632 if(rt2[i+j]) hsn[rt2[i+j]]=j;
633 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
634 // Stores can allocate zero
635 hsn[rs1[i+j]]=j;
636 hsn[rs2[i+j]]=j;
637 }
638 // On some architectures stores need invc_ptr
639 #if defined(HOST_IMM8)
b9b61529 640 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 641 hsn[INVCP]=j;
642 }
643 #endif
644 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
645 {
646 hsn[CCREG]=j;
647 b=j;
648 }
649 }
650 if(b>=0)
651 {
652 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
653 {
654 // Follow first branch
655 int t=(ba[i+b]-start)>>2;
656 j=7-b;if(t+j>=slen) j=slen-t-1;
657 for(;j>=0;j--)
658 {
659 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
660 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
661 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
662 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
663 }
664 }
665 // TODO: preferred register based on backward branch
666 }
667 // Delay slot should preferably not overwrite branch conditions or cycle count
668 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
669 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
670 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
671 hsn[CCREG]=1;
672 // ...or hash tables
673 hsn[RHASH]=1;
674 hsn[RHTBL]=1;
675 }
676 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 677 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 678 hsn[FTEMP]=0;
679 }
680 // Load L/R also uses FTEMP as a temporary register
681 if(itype[i]==LOADLR) {
682 hsn[FTEMP]=0;
683 }
b7918751 684 // Also SWL/SWR/SDL/SDR
685 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 686 hsn[FTEMP]=0;
687 }
688 // Don't remove the TLB registers either
b9b61529 689 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 690 hsn[TLREG]=0;
691 }
692 // Don't remove the miniht registers
693 if(itype[i]==UJUMP||itype[i]==RJUMP)
694 {
695 hsn[RHASH]=0;
696 hsn[RHTBL]=0;
697 }
698}
699
700// We only want to allocate registers if we're going to use them again soon
701int needed_again(int r, int i)
702{
703 int j;
704 int b=-1;
705 int rn=10;
706 int hr;
707 u_char hsn[MAXREG+1];
708 int preferred_reg;
709
710 memset(hsn,10,sizeof(hsn));
711 lsn(hsn,i,&preferred_reg);
712
713 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
714 {
715 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
716 return 0; // Don't need any registers if exiting the block
717 }
718 for(j=0;j<9;j++)
719 {
720 if(i+j>=slen) {
721 j=slen-i-1;
722 break;
723 }
724 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
725 {
726 // Don't go past an unconditonal jump
727 j++;
728 break;
729 }
7139f3c8 730 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 731 {
732 break;
733 }
734 }
735 for(;j>=1;j--)
736 {
737 if(rs1[i+j]==r) rn=j;
738 if(rs2[i+j]==r) rn=j;
739 if((unneeded_reg[i+j]>>r)&1) rn=10;
740 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
741 {
742 b=j;
743 }
744 }
745 /*
746 if(b>=0)
747 {
748 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
749 {
750 // Follow first branch
751 int o=rn;
752 int t=(ba[i+b]-start)>>2;
753 j=7-b;if(t+j>=slen) j=slen-t-1;
754 for(;j>=0;j--)
755 {
756 if(!((unneeded_reg[t+j]>>r)&1)) {
757 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
758 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
759 }
760 else rn=o;
761 }
762 }
763 }*/
764 for(hr=0;hr<HOST_REGS;hr++) {
765 if(hr!=EXCLUDE_REG) {
766 if(rn<hsn[hr]) return 1;
767 }
768 }
769 return 0;
770}
771
772// Try to match register allocations at the end of a loop with those
773// at the beginning
774int loop_reg(int i, int r, int hr)
775{
776 int j,k;
777 for(j=0;j<9;j++)
778 {
779 if(i+j>=slen) {
780 j=slen-i-1;
781 break;
782 }
783 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784 {
785 // Don't go past an unconditonal jump
786 j++;
787 break;
788 }
789 }
790 k=0;
791 if(i>0){
792 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
793 k--;
794 }
795 for(;k<j;k++)
796 {
797 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
798 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
799 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
800 {
801 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
802 {
803 int t=(ba[i+k]-start)>>2;
804 int reg=get_reg(regs[t].regmap_entry,r);
805 if(reg>=0) return reg;
806 //reg=get_reg(regs[t+1].regmap_entry,r);
807 //if(reg>=0) return reg;
808 }
809 }
810 }
811 return hr;
812}
813
814
815// Allocate every register, preserving source/target regs
816void alloc_all(struct regstat *cur,int i)
817{
818 int hr;
819
820 for(hr=0;hr<HOST_REGS;hr++) {
821 if(hr!=EXCLUDE_REG) {
822 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
823 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
824 {
825 cur->regmap[hr]=-1;
826 cur->dirty&=~(1<<hr);
827 }
828 // Don't need zeros
829 if((cur->regmap[hr]&63)==0)
830 {
831 cur->regmap[hr]=-1;
832 cur->dirty&=~(1<<hr);
833 }
834 }
835 }
836}
837
838
839void div64(int64_t dividend,int64_t divisor)
840{
841 lo=dividend/divisor;
842 hi=dividend%divisor;
843 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
844 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
845}
846void divu64(uint64_t dividend,uint64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853
854void mult64(uint64_t m1,uint64_t m2)
855{
856 unsigned long long int op1, op2, op3, op4;
857 unsigned long long int result1, result2, result3, result4;
858 unsigned long long int temp1, temp2, temp3, temp4;
859 int sign = 0;
860
861 if (m1 < 0)
862 {
863 op2 = -m1;
864 sign = 1 - sign;
865 }
866 else op2 = m1;
867 if (m2 < 0)
868 {
869 op4 = -m2;
870 sign = 1 - sign;
871 }
872 else op4 = m2;
873
874 op1 = op2 & 0xFFFFFFFF;
875 op2 = (op2 >> 32) & 0xFFFFFFFF;
876 op3 = op4 & 0xFFFFFFFF;
877 op4 = (op4 >> 32) & 0xFFFFFFFF;
878
879 temp1 = op1 * op3;
880 temp2 = (temp1 >> 32) + op1 * op4;
881 temp3 = op2 * op3;
882 temp4 = (temp3 >> 32) + op2 * op4;
883
884 result1 = temp1 & 0xFFFFFFFF;
885 result2 = temp2 + (temp3 & 0xFFFFFFFF);
886 result3 = (result2 >> 32) + temp4;
887 result4 = (result3 >> 32);
888
889 lo = result1 | (result2 << 32);
890 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
891 if (sign)
892 {
893 hi = ~hi;
894 if (!lo) hi++;
895 else lo = ~lo + 1;
896 }
897}
898
899void multu64(uint64_t m1,uint64_t m2)
900{
901 unsigned long long int op1, op2, op3, op4;
902 unsigned long long int result1, result2, result3, result4;
903 unsigned long long int temp1, temp2, temp3, temp4;
904
905 op1 = m1 & 0xFFFFFFFF;
906 op2 = (m1 >> 32) & 0xFFFFFFFF;
907 op3 = m2 & 0xFFFFFFFF;
908 op4 = (m2 >> 32) & 0xFFFFFFFF;
909
910 temp1 = op1 * op3;
911 temp2 = (temp1 >> 32) + op1 * op4;
912 temp3 = op2 * op3;
913 temp4 = (temp3 >> 32) + op2 * op4;
914
915 result1 = temp1 & 0xFFFFFFFF;
916 result2 = temp2 + (temp3 & 0xFFFFFFFF);
917 result3 = (result2 >> 32) + temp4;
918 result4 = (result3 >> 32);
919
920 lo = result1 | (result2 << 32);
921 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
922
923 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
924 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
925}
926
927uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
928{
929 if(bits) {
930 original<<=64-bits;
931 original>>=64-bits;
932 loaded<<=bits;
933 original|=loaded;
934 }
935 else original=loaded;
936 return original;
937}
938uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
939{
940 if(bits^56) {
941 original>>=64-(bits^56);
942 original<<=64-(bits^56);
943 loaded>>=bits^56;
944 original|=loaded;
945 }
946 else original=loaded;
947 return original;
948}
949
950#ifdef __i386__
951#include "assem_x86.c"
952#endif
953#ifdef __x86_64__
954#include "assem_x64.c"
955#endif
956#ifdef __arm__
957#include "assem_arm.c"
958#endif
959
960// Add virtual address mapping to linked list
961void ll_add(struct ll_entry **head,int vaddr,void *addr)
962{
963 struct ll_entry *new_entry;
964 new_entry=malloc(sizeof(struct ll_entry));
965 assert(new_entry!=NULL);
966 new_entry->vaddr=vaddr;
967 new_entry->reg32=0;
968 new_entry->addr=addr;
969 new_entry->next=*head;
970 *head=new_entry;
971}
972
973// Add virtual address mapping for 32-bit compiled block
974void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
975{
7139f3c8 976 ll_add(head,vaddr,addr);
977#ifndef FORCE32
978 (*head)->reg32=reg32;
979#endif
57871462 980}
981
982// Check if an address is already compiled
983// but don't return addresses which are about to expire from the cache
984void *check_addr(u_int vaddr)
985{
986 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
987 if(ht_bin[0]==vaddr) {
988 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
989 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
990 }
991 if(ht_bin[2]==vaddr) {
992 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
993 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
994 }
94d23bb9 995 u_int page=get_page(vaddr);
57871462 996 struct ll_entry *head;
997 head=jump_in[page];
998 while(head!=NULL) {
999 if(head->vaddr==vaddr&&head->reg32==0) {
1000 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1001 // Update existing entry with current address
1002 if(ht_bin[0]==vaddr) {
1003 ht_bin[1]=(int)head->addr;
1004 return head->addr;
1005 }
1006 if(ht_bin[2]==vaddr) {
1007 ht_bin[3]=(int)head->addr;
1008 return head->addr;
1009 }
1010 // Insert into hash table with low priority.
1011 // Don't evict existing entries, as they are probably
1012 // addresses that are being accessed frequently.
1013 if(ht_bin[0]==-1) {
1014 ht_bin[1]=(int)head->addr;
1015 ht_bin[0]=vaddr;
1016 }else if(ht_bin[2]==-1) {
1017 ht_bin[3]=(int)head->addr;
1018 ht_bin[2]=vaddr;
1019 }
1020 return head->addr;
1021 }
1022 }
1023 head=head->next;
1024 }
1025 return 0;
1026}
1027
1028void remove_hash(int vaddr)
1029{
1030 //printf("remove hash: %x\n",vaddr);
1031 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1032 if(ht_bin[2]==vaddr) {
1033 ht_bin[2]=ht_bin[3]=-1;
1034 }
1035 if(ht_bin[0]==vaddr) {
1036 ht_bin[0]=ht_bin[2];
1037 ht_bin[1]=ht_bin[3];
1038 ht_bin[2]=ht_bin[3]=-1;
1039 }
1040}
1041
1042void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1043{
1044 struct ll_entry *next;
1045 while(*head) {
1046 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1047 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1048 {
1049 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1050 remove_hash((*head)->vaddr);
1051 next=(*head)->next;
1052 free(*head);
1053 *head=next;
1054 }
1055 else
1056 {
1057 head=&((*head)->next);
1058 }
1059 }
1060}
1061
1062// Remove all entries from linked list
1063void ll_clear(struct ll_entry **head)
1064{
1065 struct ll_entry *cur;
1066 struct ll_entry *next;
1067 if(cur=*head) {
1068 *head=0;
1069 while(cur) {
1070 next=cur->next;
1071 free(cur);
1072 cur=next;
1073 }
1074 }
1075}
1076
1077// Dereference the pointers and remove if it matches
1078void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1079{
f76eeef9 1080 u_int old_host_addr=0;
57871462 1081 while(head) {
1082 int ptr=get_pointer(head->addr);
1083 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1084 if(((ptr>>shift)==(addr>>shift)) ||
1085 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1086 {
f76eeef9 1087 printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1088 u_int host_addr=(u_int)kill_pointer(head->addr);
1089
1090 if((host_addr>>12)!=(old_host_addr>>12)) {
1091 #ifdef __arm__
1092 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1093 #endif
1094 old_host_addr=host_addr;
1095 }
57871462 1096 }
1097 head=head->next;
1098 }
f76eeef9 1099 #ifdef __arm__
1100 if (old_host_addr)
1101 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1102 #endif
57871462 1103}
1104
1105// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1106void invalidate_page(u_int page)
57871462 1107{
57871462 1108 struct ll_entry *head;
1109 struct ll_entry *next;
f76eeef9 1110 u_int old_host_addr=0;
57871462 1111 head=jump_in[page];
1112 jump_in[page]=0;
1113 while(head!=NULL) {
1114 inv_debug("INVALIDATE: %x\n",head->vaddr);
1115 remove_hash(head->vaddr);
1116 next=head->next;
1117 free(head);
1118 head=next;
1119 }
1120 head=jump_out[page];
1121 jump_out[page]=0;
1122 while(head!=NULL) {
1123 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1124 u_int host_addr=(u_int)kill_pointer(head->addr);
1125
1126 if((host_addr>>12)!=(old_host_addr>>12)) {
1127 #ifdef __arm__
1128 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1129 #endif
1130 old_host_addr=host_addr;
1131 }
57871462 1132 next=head->next;
1133 free(head);
1134 head=next;
1135 }
f76eeef9 1136 #ifdef __arm__
1137 if (old_host_addr)
1138 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1139 #endif
57871462 1140}
1141void invalidate_block(u_int block)
1142{
94d23bb9 1143 u_int page=get_page(block<<12);
1144 u_int vpage=get_vpage(block<<12);
57871462 1145 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1146 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1147 u_int first,last;
1148 first=last=page;
1149 struct ll_entry *head;
1150 head=jump_dirty[vpage];
1151 //printf("page=%d vpage=%d\n",page,vpage);
1152 while(head!=NULL) {
1153 u_int start,end;
1154 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1155 get_bounds((int)head->addr,&start,&end);
1156 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1157 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1158 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1159 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1160 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1161 }
1162 }
90ae6d4e 1163#ifndef DISABLE_TLB
57871462 1164 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1165 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1166 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1167 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1168 }
1169 }
90ae6d4e 1170#endif
57871462 1171 }
1172 head=head->next;
1173 }
1174 //printf("first=%d last=%d\n",first,last);
f76eeef9 1175 invalidate_page(page);
57871462 1176 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1177 assert(last<page+5);
1178 // Invalidate the adjacent pages if a block crosses a 4K boundary
1179 while(first<page) {
1180 invalidate_page(first);
1181 first++;
1182 }
1183 for(first=page+1;first<last;first++) {
1184 invalidate_page(first);
1185 }
1186
1187 // Don't trap writes
1188 invalid_code[block]=1;
94d23bb9 1189#ifndef DISABLE_TLB
57871462 1190 // If there is a valid TLB entry for this page, remove write protect
1191 if(tlb_LUT_w[block]) {
1192 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1193 // CHECK: Is this right?
1194 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1195 u_int real_block=tlb_LUT_w[block]>>12;
1196 invalid_code[real_block]=1;
1197 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1198 }
1199 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1200#endif
f76eeef9 1201
57871462 1202 #ifdef USE_MINI_HT
1203 memset(mini_ht,-1,sizeof(mini_ht));
1204 #endif
1205}
1206void invalidate_addr(u_int addr)
1207{
1208 invalidate_block(addr>>12);
1209}
1210void invalidate_all_pages()
1211{
1212 u_int page,n;
1213 for(page=0;page<4096;page++)
1214 invalidate_page(page);
1215 for(page=0;page<1048576;page++)
1216 if(!invalid_code[page]) {
1217 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1218 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1219 }
1220 #ifdef __arm__
1221 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1222 #endif
1223 #ifdef USE_MINI_HT
1224 memset(mini_ht,-1,sizeof(mini_ht));
1225 #endif
94d23bb9 1226 #ifndef DISABLE_TLB
57871462 1227 // TLB
1228 for(page=0;page<0x100000;page++) {
1229 if(tlb_LUT_r[page]) {
1230 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1231 if(!tlb_LUT_w[page]||!invalid_code[page])
1232 memory_map[page]|=0x40000000; // Write protect
1233 }
1234 else memory_map[page]=-1;
1235 if(page==0x80000) page=0xC0000;
1236 }
1237 tlb_hacks();
94d23bb9 1238 #endif
57871462 1239}
1240
1241// Add an entry to jump_out after making a link
1242void add_link(u_int vaddr,void *src)
1243{
94d23bb9 1244 u_int page=get_page(vaddr);
57871462 1245 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1246 ll_add(jump_out+page,vaddr,src);
1247 //int ptr=get_pointer(src);
1248 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1249}
1250
1251// If a code block was found to be unmodified (bit was set in
1252// restore_candidate) and it remains unmodified (bit is clear
1253// in invalid_code) then move the entries for that 4K page from
1254// the dirty list to the clean list.
1255void clean_blocks(u_int page)
1256{
1257 struct ll_entry *head;
1258 inv_debug("INV: clean_blocks page=%d\n",page);
1259 head=jump_dirty[page];
1260 while(head!=NULL) {
1261 if(!invalid_code[head->vaddr>>12]) {
1262 // Don't restore blocks which are about to expire from the cache
1263 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1264 u_int start,end;
1265 if(verify_dirty((int)head->addr)) {
1266 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1267 u_int i;
1268 u_int inv=0;
1269 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1270 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1271 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1272 inv|=invalid_code[i];
1273 }
1274 }
1275 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1276 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1277 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1278 if(addr<start||addr>=end) inv=1;
1279 }
4cb76aa4 1280 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1281 inv=1;
1282 }
1283 if(!inv) {
1284 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1285 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1286 u_int ppage=page;
94d23bb9 1287#ifndef DISABLE_TLB
57871462 1288 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1289#endif
57871462 1290 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1291 //printf("page=%x, addr=%x\n",page,head->vaddr);
1292 //assert(head->vaddr>>12==(page|0x80000));
1293 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1294 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1295 if(!head->reg32) {
1296 if(ht_bin[0]==head->vaddr) {
1297 ht_bin[1]=(int)clean_addr; // Replace existing entry
1298 }
1299 if(ht_bin[2]==head->vaddr) {
1300 ht_bin[3]=(int)clean_addr; // Replace existing entry
1301 }
1302 }
1303 }
1304 }
1305 }
1306 }
1307 }
1308 head=head->next;
1309 }
1310}
1311
1312
1313void mov_alloc(struct regstat *current,int i)
1314{
1315 // Note: Don't need to actually alloc the source registers
1316 if((~current->is32>>rs1[i])&1) {
1317 //alloc_reg64(current,i,rs1[i]);
1318 alloc_reg64(current,i,rt1[i]);
1319 current->is32&=~(1LL<<rt1[i]);
1320 } else {
1321 //alloc_reg(current,i,rs1[i]);
1322 alloc_reg(current,i,rt1[i]);
1323 current->is32|=(1LL<<rt1[i]);
1324 }
1325 clear_const(current,rs1[i]);
1326 clear_const(current,rt1[i]);
1327 dirty_reg(current,rt1[i]);
1328}
1329
1330void shiftimm_alloc(struct regstat *current,int i)
1331{
1332 clear_const(current,rs1[i]);
1333 clear_const(current,rt1[i]);
1334 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1335 {
1336 if(rt1[i]) {
1337 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1338 else lt1[i]=rs1[i];
1339 alloc_reg(current,i,rt1[i]);
1340 current->is32|=1LL<<rt1[i];
1341 dirty_reg(current,rt1[i]);
1342 }
1343 }
1344 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1345 {
1346 if(rt1[i]) {
1347 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1348 alloc_reg64(current,i,rt1[i]);
1349 current->is32&=~(1LL<<rt1[i]);
1350 dirty_reg(current,rt1[i]);
1351 }
1352 }
1353 if(opcode2[i]==0x3c) // DSLL32
1354 {
1355 if(rt1[i]) {
1356 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1357 alloc_reg64(current,i,rt1[i]);
1358 current->is32&=~(1LL<<rt1[i]);
1359 dirty_reg(current,rt1[i]);
1360 }
1361 }
1362 if(opcode2[i]==0x3e) // DSRL32
1363 {
1364 if(rt1[i]) {
1365 alloc_reg64(current,i,rs1[i]);
1366 if(imm[i]==32) {
1367 alloc_reg64(current,i,rt1[i]);
1368 current->is32&=~(1LL<<rt1[i]);
1369 } else {
1370 alloc_reg(current,i,rt1[i]);
1371 current->is32|=1LL<<rt1[i];
1372 }
1373 dirty_reg(current,rt1[i]);
1374 }
1375 }
1376 if(opcode2[i]==0x3f) // DSRA32
1377 {
1378 if(rt1[i]) {
1379 alloc_reg64(current,i,rs1[i]);
1380 alloc_reg(current,i,rt1[i]);
1381 current->is32|=1LL<<rt1[i];
1382 dirty_reg(current,rt1[i]);
1383 }
1384 }
1385}
1386
1387void shift_alloc(struct regstat *current,int i)
1388{
1389 if(rt1[i]) {
1390 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1391 {
1392 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1393 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1394 alloc_reg(current,i,rt1[i]);
1395 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1403 alloc_reg_temp(current,i,-1);
1404 }
1405 clear_const(current,rs1[i]);
1406 clear_const(current,rs2[i]);
1407 clear_const(current,rt1[i]);
1408 dirty_reg(current,rt1[i]);
1409 }
1410}
1411
1412void alu_alloc(struct regstat *current,int i)
1413{
1414 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1415 if(rt1[i]) {
1416 if(rs1[i]&&rs2[i]) {
1417 alloc_reg(current,i,rs1[i]);
1418 alloc_reg(current,i,rs2[i]);
1419 }
1420 else {
1421 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1422 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1423 }
1424 alloc_reg(current,i,rt1[i]);
1425 }
1426 current->is32|=1LL<<rt1[i];
1427 }
1428 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1429 if(rt1[i]) {
1430 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1431 {
1432 alloc_reg64(current,i,rs1[i]);
1433 alloc_reg64(current,i,rs2[i]);
1434 alloc_reg(current,i,rt1[i]);
1435 } else {
1436 alloc_reg(current,i,rs1[i]);
1437 alloc_reg(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1439 }
1440 }
1441 current->is32|=1LL<<rt1[i];
1442 }
1443 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1444 if(rt1[i]) {
1445 if(rs1[i]&&rs2[i]) {
1446 alloc_reg(current,i,rs1[i]);
1447 alloc_reg(current,i,rs2[i]);
1448 }
1449 else
1450 {
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1453 }
1454 alloc_reg(current,i,rt1[i]);
1455 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1456 {
1457 if(!((current->uu>>rt1[i])&1)) {
1458 alloc_reg64(current,i,rt1[i]);
1459 }
1460 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1461 if(rs1[i]&&rs2[i]) {
1462 alloc_reg64(current,i,rs1[i]);
1463 alloc_reg64(current,i,rs2[i]);
1464 }
1465 else
1466 {
1467 // Is is really worth it to keep 64-bit values in registers?
1468 #ifdef NATIVE_64BIT
1469 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1470 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1471 #endif
1472 }
1473 }
1474 current->is32&=~(1LL<<rt1[i]);
1475 } else {
1476 current->is32|=1LL<<rt1[i];
1477 }
1478 }
1479 }
1480 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1481 if(rt1[i]) {
1482 if(rs1[i]&&rs2[i]) {
1483 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1484 alloc_reg64(current,i,rs1[i]);
1485 alloc_reg64(current,i,rs2[i]);
1486 alloc_reg64(current,i,rt1[i]);
1487 } else {
1488 alloc_reg(current,i,rs1[i]);
1489 alloc_reg(current,i,rs2[i]);
1490 alloc_reg(current,i,rt1[i]);
1491 }
1492 }
1493 else {
1494 alloc_reg(current,i,rt1[i]);
1495 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1496 // DADD used as move, or zeroing
1497 // If we have a 64-bit source, then make the target 64 bits too
1498 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1499 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rt1[i]);
1501 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1502 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 }
1505 if(opcode2[i]>=0x2e&&rs2[i]) {
1506 // DSUB used as negation - 64-bit result
1507 // If we have a 32-bit register, extend it to 64 bits
1508 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1509 alloc_reg64(current,i,rt1[i]);
1510 }
1511 }
1512 }
1513 if(rs1[i]&&rs2[i]) {
1514 current->is32&=~(1LL<<rt1[i]);
1515 } else if(rs1[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1517 if((current->is32>>rs1[i])&1)
1518 current->is32|=1LL<<rt1[i];
1519 } else if(rs2[i]) {
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs2[i])&1)
1522 current->is32|=1LL<<rt1[i];
1523 } else {
1524 current->is32|=1LL<<rt1[i];
1525 }
1526 }
1527 }
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rs2[i]);
1530 clear_const(current,rt1[i]);
1531 dirty_reg(current,rt1[i]);
1532}
1533
1534void imm16_alloc(struct regstat *current,int i)
1535{
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1537 else lt1[i]=rs1[i];
1538 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1539 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1540 current->is32&=~(1LL<<rt1[i]);
1541 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1542 // TODO: Could preserve the 32-bit flag if the immediate is zero
1543 alloc_reg64(current,i,rt1[i]);
1544 alloc_reg64(current,i,rs1[i]);
1545 }
1546 clear_const(current,rs1[i]);
1547 clear_const(current,rt1[i]);
1548 }
1549 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1550 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1551 current->is32|=1LL<<rt1[i];
1552 clear_const(current,rs1[i]);
1553 clear_const(current,rt1[i]);
1554 }
1555 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1556 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1557 if(rs1[i]!=rt1[i]) {
1558 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1559 alloc_reg64(current,i,rt1[i]);
1560 current->is32&=~(1LL<<rt1[i]);
1561 }
1562 }
1563 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1564 if(is_const(current,rs1[i])) {
1565 int v=get_const(current,rs1[i]);
1566 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1567 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1568 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1569 }
1570 else clear_const(current,rt1[i]);
1571 }
1572 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1573 if(is_const(current,rs1[i])) {
1574 int v=get_const(current,rs1[i]);
1575 set_const(current,rt1[i],v+imm[i]);
1576 }
1577 else clear_const(current,rt1[i]);
1578 current->is32|=1LL<<rt1[i];
1579 }
1580 else {
1581 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1582 current->is32|=1LL<<rt1[i];
1583 }
1584 dirty_reg(current,rt1[i]);
1585}
1586
1587void load_alloc(struct regstat *current,int i)
1588{
1589 clear_const(current,rt1[i]);
1590 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1591 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1592 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1593 if(rt1[i]) {
1594 alloc_reg(current,i,rt1[i]);
1595 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1596 {
1597 current->is32&=~(1LL<<rt1[i]);
1598 alloc_reg64(current,i,rt1[i]);
1599 }
1600 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1601 {
1602 current->is32&=~(1LL<<rt1[i]);
1603 alloc_reg64(current,i,rt1[i]);
1604 alloc_all(current,i);
1605 alloc_reg64(current,i,FTEMP);
1606 }
1607 else current->is32|=1LL<<rt1[i];
1608 dirty_reg(current,rt1[i]);
1609 // If using TLB, need a register for pointer to the mapping table
1610 if(using_tlb) alloc_reg(current,i,TLREG);
1611 // LWL/LWR need a temporary register for the old value
1612 if(opcode[i]==0x22||opcode[i]==0x26)
1613 {
1614 alloc_reg(current,i,FTEMP);
1615 alloc_reg_temp(current,i,-1);
1616 }
1617 }
1618 else
1619 {
1620 // Load to r0 (dummy load)
1621 // but we still need a register to calculate the address
1622 alloc_reg_temp(current,i,-1);
1623 }
1624}
1625
1626void store_alloc(struct regstat *current,int i)
1627{
1628 clear_const(current,rs2[i]);
1629 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1630 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1631 alloc_reg(current,i,rs2[i]);
1632 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1633 alloc_reg64(current,i,rs2[i]);
1634 if(rs2[i]) alloc_reg(current,i,FTEMP);
1635 }
1636 // If using TLB, need a register for pointer to the mapping table
1637 if(using_tlb) alloc_reg(current,i,TLREG);
1638 #if defined(HOST_IMM8)
1639 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1640 else alloc_reg(current,i,INVCP);
1641 #endif
b7918751 1642 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1643 alloc_reg(current,i,FTEMP);
1644 }
1645 // We need a temporary register for address generation
1646 alloc_reg_temp(current,i,-1);
1647}
1648
1649void c1ls_alloc(struct regstat *current,int i)
1650{
1651 //clear_const(current,rs1[i]); // FIXME
1652 clear_const(current,rt1[i]);
1653 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1654 alloc_reg(current,i,CSREG); // Status
1655 alloc_reg(current,i,FTEMP);
1656 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1657 alloc_reg64(current,i,FTEMP);
1658 }
1659 // If using TLB, need a register for pointer to the mapping table
1660 if(using_tlb) alloc_reg(current,i,TLREG);
1661 #if defined(HOST_IMM8)
1662 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1663 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1664 alloc_reg(current,i,INVCP);
1665 #endif
1666 // We need a temporary register for address generation
1667 alloc_reg_temp(current,i,-1);
1668}
1669
b9b61529 1670void c2ls_alloc(struct regstat *current,int i)
1671{
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,FTEMP);
1675 // If using TLB, need a register for pointer to the mapping table
1676 if(using_tlb) alloc_reg(current,i,TLREG);
1677 #if defined(HOST_IMM8)
1678 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1679 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1680 alloc_reg(current,i,INVCP);
1681 #endif
1682 // We need a temporary register for address generation
1683 alloc_reg_temp(current,i,-1);
1684}
1685
57871462 1686#ifndef multdiv_alloc
1687void multdiv_alloc(struct regstat *current,int i)
1688{
1689 // case 0x18: MULT
1690 // case 0x19: MULTU
1691 // case 0x1A: DIV
1692 // case 0x1B: DIVU
1693 // case 0x1C: DMULT
1694 // case 0x1D: DMULTU
1695 // case 0x1E: DDIV
1696 // case 0x1F: DDIVU
1697 clear_const(current,rs1[i]);
1698 clear_const(current,rs2[i]);
1699 if(rs1[i]&&rs2[i])
1700 {
1701 if((opcode2[i]&4)==0) // 32-bit
1702 {
1703 current->u&=~(1LL<<HIREG);
1704 current->u&=~(1LL<<LOREG);
1705 alloc_reg(current,i,HIREG);
1706 alloc_reg(current,i,LOREG);
1707 alloc_reg(current,i,rs1[i]);
1708 alloc_reg(current,i,rs2[i]);
1709 current->is32|=1LL<<HIREG;
1710 current->is32|=1LL<<LOREG;
1711 dirty_reg(current,HIREG);
1712 dirty_reg(current,LOREG);
1713 }
1714 else // 64-bit
1715 {
1716 current->u&=~(1LL<<HIREG);
1717 current->u&=~(1LL<<LOREG);
1718 current->uu&=~(1LL<<HIREG);
1719 current->uu&=~(1LL<<LOREG);
1720 alloc_reg64(current,i,HIREG);
1721 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1722 alloc_reg64(current,i,rs1[i]);
1723 alloc_reg64(current,i,rs2[i]);
1724 alloc_all(current,i);
1725 current->is32&=~(1LL<<HIREG);
1726 current->is32&=~(1LL<<LOREG);
1727 dirty_reg(current,HIREG);
1728 dirty_reg(current,LOREG);
1729 }
1730 }
1731 else
1732 {
1733 // Multiply by zero is zero.
1734 // MIPS does not have a divide by zero exception.
1735 // The result is undefined, we return zero.
1736 alloc_reg(current,i,HIREG);
1737 alloc_reg(current,i,LOREG);
1738 current->is32|=1LL<<HIREG;
1739 current->is32|=1LL<<LOREG;
1740 dirty_reg(current,HIREG);
1741 dirty_reg(current,LOREG);
1742 }
1743}
1744#endif
1745
1746void cop0_alloc(struct regstat *current,int i)
1747{
1748 if(opcode2[i]==0) // MFC0
1749 {
1750 if(rt1[i]) {
1751 clear_const(current,rt1[i]);
1752 alloc_all(current,i);
1753 alloc_reg(current,i,rt1[i]);
1754 current->is32|=1LL<<rt1[i];
1755 dirty_reg(current,rt1[i]);
1756 }
1757 }
1758 else if(opcode2[i]==4) // MTC0
1759 {
1760 if(rs1[i]){
1761 clear_const(current,rs1[i]);
1762 alloc_reg(current,i,rs1[i]);
1763 alloc_all(current,i);
1764 }
1765 else {
1766 alloc_all(current,i); // FIXME: Keep r0
1767 current->u&=~1LL;
1768 alloc_reg(current,i,0);
1769 }
1770 }
1771 else
1772 {
1773 // TLBR/TLBWI/TLBWR/TLBP/ERET
1774 assert(opcode2[i]==0x10);
1775 alloc_all(current,i);
1776 }
1777}
1778
1779void cop1_alloc(struct regstat *current,int i)
1780{
1781 alloc_reg(current,i,CSREG); // Load status
1782 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1783 {
1784 assert(rt1[i]);
1785 clear_const(current,rt1[i]);
1786 if(opcode2[i]==1) {
1787 alloc_reg64(current,i,rt1[i]); // DMFC1
1788 current->is32&=~(1LL<<rt1[i]);
1789 }else{
1790 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1791 current->is32|=1LL<<rt1[i];
1792 }
1793 dirty_reg(current,rt1[i]);
1794 alloc_reg_temp(current,i,-1);
1795 }
1796 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1797 {
1798 if(rs1[i]){
1799 clear_const(current,rs1[i]);
1800 if(opcode2[i]==5)
1801 alloc_reg64(current,i,rs1[i]); // DMTC1
1802 else
1803 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1804 alloc_reg_temp(current,i,-1);
1805 }
1806 else {
1807 current->u&=~1LL;
1808 alloc_reg(current,i,0);
1809 alloc_reg_temp(current,i,-1);
1810 }
1811 }
1812}
1813void fconv_alloc(struct regstat *current,int i)
1814{
1815 alloc_reg(current,i,CSREG); // Load status
1816 alloc_reg_temp(current,i,-1);
1817}
1818void float_alloc(struct regstat *current,int i)
1819{
1820 alloc_reg(current,i,CSREG); // Load status
1821 alloc_reg_temp(current,i,-1);
1822}
b9b61529 1823void c2op_alloc(struct regstat *current,int i)
1824{
1825 alloc_reg_temp(current,i,-1);
1826}
57871462 1827void fcomp_alloc(struct regstat *current,int i)
1828{
1829 alloc_reg(current,i,CSREG); // Load status
1830 alloc_reg(current,i,FSREG); // Load flags
1831 dirty_reg(current,FSREG); // Flag will be modified
1832 alloc_reg_temp(current,i,-1);
1833}
1834
1835void syscall_alloc(struct regstat *current,int i)
1836{
1837 alloc_cc(current,i);
1838 dirty_reg(current,CCREG);
1839 alloc_all(current,i);
1840 current->isconst=0;
1841}
1842
1843void delayslot_alloc(struct regstat *current,int i)
1844{
1845 switch(itype[i]) {
1846 case UJUMP:
1847 case CJUMP:
1848 case SJUMP:
1849 case RJUMP:
1850 case FJUMP:
1851 case SYSCALL:
7139f3c8 1852 case HLECALL:
57871462 1853 case SPAN:
1854 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1855 printf("Disabled speculative precompilation\n");
1856 stop_after_jal=1;
1857 break;
1858 case IMM16:
1859 imm16_alloc(current,i);
1860 break;
1861 case LOAD:
1862 case LOADLR:
1863 load_alloc(current,i);
1864 break;
1865 case STORE:
1866 case STORELR:
1867 store_alloc(current,i);
1868 break;
1869 case ALU:
1870 alu_alloc(current,i);
1871 break;
1872 case SHIFT:
1873 shift_alloc(current,i);
1874 break;
1875 case MULTDIV:
1876 multdiv_alloc(current,i);
1877 break;
1878 case SHIFTIMM:
1879 shiftimm_alloc(current,i);
1880 break;
1881 case MOV:
1882 mov_alloc(current,i);
1883 break;
1884 case COP0:
1885 cop0_alloc(current,i);
1886 break;
1887 case COP1:
b9b61529 1888 case COP2:
57871462 1889 cop1_alloc(current,i);
1890 break;
1891 case C1LS:
1892 c1ls_alloc(current,i);
1893 break;
b9b61529 1894 case C2LS:
1895 c2ls_alloc(current,i);
1896 break;
57871462 1897 case FCONV:
1898 fconv_alloc(current,i);
1899 break;
1900 case FLOAT:
1901 float_alloc(current,i);
1902 break;
1903 case FCOMP:
1904 fcomp_alloc(current,i);
1905 break;
b9b61529 1906 case C2OP:
1907 c2op_alloc(current,i);
1908 break;
57871462 1909 }
1910}
1911
1912// Special case where a branch and delay slot span two pages in virtual memory
1913static void pagespan_alloc(struct regstat *current,int i)
1914{
1915 current->isconst=0;
1916 current->wasconst=0;
1917 regs[i].wasconst=0;
1918 alloc_all(current,i);
1919 alloc_cc(current,i);
1920 dirty_reg(current,CCREG);
1921 if(opcode[i]==3) // JAL
1922 {
1923 alloc_reg(current,i,31);
1924 dirty_reg(current,31);
1925 }
1926 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1927 {
1928 alloc_reg(current,i,rs1[i]);
5067f341 1929 if (rt1[i]!=0) {
1930 alloc_reg(current,i,rt1[i]);
1931 dirty_reg(current,rt1[i]);
57871462 1932 }
1933 }
1934 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1935 {
1936 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1937 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1938 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1939 {
1940 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1941 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1942 }
1943 }
1944 else
1945 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1946 {
1947 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1948 if(!((current->is32>>rs1[i])&1))
1949 {
1950 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1951 }
1952 }
1953 else
1954 if(opcode[i]==0x11) // BC1
1955 {
1956 alloc_reg(current,i,FSREG);
1957 alloc_reg(current,i,CSREG);
1958 }
1959 //else ...
1960}
1961
1962add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1963{
1964 stubs[stubcount][0]=type;
1965 stubs[stubcount][1]=addr;
1966 stubs[stubcount][2]=retaddr;
1967 stubs[stubcount][3]=a;
1968 stubs[stubcount][4]=b;
1969 stubs[stubcount][5]=c;
1970 stubs[stubcount][6]=d;
1971 stubs[stubcount][7]=e;
1972 stubcount++;
1973}
1974
1975// Write out a single register
1976void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1977{
1978 int hr;
1979 for(hr=0;hr<HOST_REGS;hr++) {
1980 if(hr!=EXCLUDE_REG) {
1981 if((regmap[hr]&63)==r) {
1982 if((dirty>>hr)&1) {
1983 if(regmap[hr]<64) {
1984 emit_storereg(r,hr);
24385cae 1985#ifndef FORCE32
57871462 1986 if((is32>>regmap[hr])&1) {
1987 emit_sarimm(hr,31,hr);
1988 emit_storereg(r|64,hr);
1989 }
24385cae 1990#endif
57871462 1991 }else{
1992 emit_storereg(r|64,hr);
1993 }
1994 }
1995 }
1996 }
1997 }
1998}
1999
2000int mchecksum()
2001{
2002 //if(!tracedebug) return 0;
2003 int i;
2004 int sum=0;
2005 for(i=0;i<2097152;i++) {
2006 unsigned int temp=sum;
2007 sum<<=1;
2008 sum|=(~temp)>>31;
2009 sum^=((u_int *)rdram)[i];
2010 }
2011 return sum;
2012}
2013int rchecksum()
2014{
2015 int i;
2016 int sum=0;
2017 for(i=0;i<64;i++)
2018 sum^=((u_int *)reg)[i];
2019 return sum;
2020}
57871462 2021void rlist()
2022{
2023 int i;
2024 printf("TRACE: ");
2025 for(i=0;i<32;i++)
2026 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2027 printf("\n");
3d624f89 2028#ifndef DISABLE_COP1
57871462 2029 printf("TRACE: ");
2030 for(i=0;i<32;i++)
2031 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2032 printf("\n");
3d624f89 2033#endif
57871462 2034}
2035
2036void enabletrace()
2037{
2038 tracedebug=1;
2039}
2040
2041void memdebug(int i)
2042{
2043 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2044 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2045 //rlist();
2046 //if(tracedebug) {
2047 //if(Count>=-2084597794) {
2048 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2049 //if(0) {
2050 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2051 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2052 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2053 rlist();
2054 #ifdef __i386__
2055 printf("TRACE: %x\n",(&i)[-1]);
2056 #endif
2057 #ifdef __arm__
2058 int j;
2059 printf("TRACE: %x \n",(&j)[10]);
2060 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2061 #endif
2062 //fflush(stdout);
2063 }
2064 //printf("TRACE: %x\n",(&i)[-1]);
2065}
2066
2067void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2068{
2069 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2070}
2071
2072void alu_assemble(int i,struct regstat *i_regs)
2073{
2074 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2075 if(rt1[i]) {
2076 signed char s1,s2,t;
2077 t=get_reg(i_regs->regmap,rt1[i]);
2078 if(t>=0) {
2079 s1=get_reg(i_regs->regmap,rs1[i]);
2080 s2=get_reg(i_regs->regmap,rs2[i]);
2081 if(rs1[i]&&rs2[i]) {
2082 assert(s1>=0);
2083 assert(s2>=0);
2084 if(opcode2[i]&2) emit_sub(s1,s2,t);
2085 else emit_add(s1,s2,t);
2086 }
2087 else if(rs1[i]) {
2088 if(s1>=0) emit_mov(s1,t);
2089 else emit_loadreg(rs1[i],t);
2090 }
2091 else if(rs2[i]) {
2092 if(s2>=0) {
2093 if(opcode2[i]&2) emit_neg(s2,t);
2094 else emit_mov(s2,t);
2095 }
2096 else {
2097 emit_loadreg(rs2[i],t);
2098 if(opcode2[i]&2) emit_neg(t,t);
2099 }
2100 }
2101 else emit_zeroreg(t);
2102 }
2103 }
2104 }
2105 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2106 if(rt1[i]) {
2107 signed char s1l,s2l,s1h,s2h,tl,th;
2108 tl=get_reg(i_regs->regmap,rt1[i]);
2109 th=get_reg(i_regs->regmap,rt1[i]|64);
2110 if(tl>=0) {
2111 s1l=get_reg(i_regs->regmap,rs1[i]);
2112 s2l=get_reg(i_regs->regmap,rs2[i]);
2113 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2114 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2115 if(rs1[i]&&rs2[i]) {
2116 assert(s1l>=0);
2117 assert(s2l>=0);
2118 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2119 else emit_adds(s1l,s2l,tl);
2120 if(th>=0) {
2121 #ifdef INVERTED_CARRY
2122 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2123 #else
2124 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2125 #endif
2126 else emit_add(s1h,s2h,th);
2127 }
2128 }
2129 else if(rs1[i]) {
2130 if(s1l>=0) emit_mov(s1l,tl);
2131 else emit_loadreg(rs1[i],tl);
2132 if(th>=0) {
2133 if(s1h>=0) emit_mov(s1h,th);
2134 else emit_loadreg(rs1[i]|64,th);
2135 }
2136 }
2137 else if(rs2[i]) {
2138 if(s2l>=0) {
2139 if(opcode2[i]&2) emit_negs(s2l,tl);
2140 else emit_mov(s2l,tl);
2141 }
2142 else {
2143 emit_loadreg(rs2[i],tl);
2144 if(opcode2[i]&2) emit_negs(tl,tl);
2145 }
2146 if(th>=0) {
2147 #ifdef INVERTED_CARRY
2148 if(s2h>=0) emit_mov(s2h,th);
2149 else emit_loadreg(rs2[i]|64,th);
2150 if(opcode2[i]&2) {
2151 emit_adcimm(-1,th); // x86 has inverted carry flag
2152 emit_not(th,th);
2153 }
2154 #else
2155 if(opcode2[i]&2) {
2156 if(s2h>=0) emit_rscimm(s2h,0,th);
2157 else {
2158 emit_loadreg(rs2[i]|64,th);
2159 emit_rscimm(th,0,th);
2160 }
2161 }else{
2162 if(s2h>=0) emit_mov(s2h,th);
2163 else emit_loadreg(rs2[i]|64,th);
2164 }
2165 #endif
2166 }
2167 }
2168 else {
2169 emit_zeroreg(tl);
2170 if(th>=0) emit_zeroreg(th);
2171 }
2172 }
2173 }
2174 }
2175 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2176 if(rt1[i]) {
2177 signed char s1l,s1h,s2l,s2h,t;
2178 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2179 {
2180 t=get_reg(i_regs->regmap,rt1[i]);
2181 //assert(t>=0);
2182 if(t>=0) {
2183 s1l=get_reg(i_regs->regmap,rs1[i]);
2184 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2185 s2l=get_reg(i_regs->regmap,rs2[i]);
2186 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2187 if(rs2[i]==0) // rx<r0
2188 {
2189 assert(s1h>=0);
2190 if(opcode2[i]==0x2a) // SLT
2191 emit_shrimm(s1h,31,t);
2192 else // SLTU (unsigned can not be less than zero)
2193 emit_zeroreg(t);
2194 }
2195 else if(rs1[i]==0) // r0<rx
2196 {
2197 assert(s2h>=0);
2198 if(opcode2[i]==0x2a) // SLT
2199 emit_set_gz64_32(s2h,s2l,t);
2200 else // SLTU (set if not zero)
2201 emit_set_nz64_32(s2h,s2l,t);
2202 }
2203 else {
2204 assert(s1l>=0);assert(s1h>=0);
2205 assert(s2l>=0);assert(s2h>=0);
2206 if(opcode2[i]==0x2a) // SLT
2207 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2208 else // SLTU
2209 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2210 }
2211 }
2212 } else {
2213 t=get_reg(i_regs->regmap,rt1[i]);
2214 //assert(t>=0);
2215 if(t>=0) {
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s2l=get_reg(i_regs->regmap,rs2[i]);
2218 if(rs2[i]==0) // rx<r0
2219 {
2220 assert(s1l>=0);
2221 if(opcode2[i]==0x2a) // SLT
2222 emit_shrimm(s1l,31,t);
2223 else // SLTU (unsigned can not be less than zero)
2224 emit_zeroreg(t);
2225 }
2226 else if(rs1[i]==0) // r0<rx
2227 {
2228 assert(s2l>=0);
2229 if(opcode2[i]==0x2a) // SLT
2230 emit_set_gz32(s2l,t);
2231 else // SLTU (set if not zero)
2232 emit_set_nz32(s2l,t);
2233 }
2234 else{
2235 assert(s1l>=0);assert(s2l>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less32(s1l,s2l,t);
2238 else // SLTU
2239 emit_set_if_carry32(s1l,s2l,t);
2240 }
2241 }
2242 }
2243 }
2244 }
2245 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2246 if(rt1[i]) {
2247 signed char s1l,s1h,s2l,s2h,th,tl;
2248 tl=get_reg(i_regs->regmap,rt1[i]);
2249 th=get_reg(i_regs->regmap,rt1[i]|64);
2250 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2251 {
2252 assert(tl>=0);
2253 if(tl>=0) {
2254 s1l=get_reg(i_regs->regmap,rs1[i]);
2255 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2256 s2l=get_reg(i_regs->regmap,rs2[i]);
2257 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2258 if(rs1[i]&&rs2[i]) {
2259 assert(s1l>=0);assert(s1h>=0);
2260 assert(s2l>=0);assert(s2h>=0);
2261 if(opcode2[i]==0x24) { // AND
2262 emit_and(s1l,s2l,tl);
2263 emit_and(s1h,s2h,th);
2264 } else
2265 if(opcode2[i]==0x25) { // OR
2266 emit_or(s1l,s2l,tl);
2267 emit_or(s1h,s2h,th);
2268 } else
2269 if(opcode2[i]==0x26) { // XOR
2270 emit_xor(s1l,s2l,tl);
2271 emit_xor(s1h,s2h,th);
2272 } else
2273 if(opcode2[i]==0x27) { // NOR
2274 emit_or(s1l,s2l,tl);
2275 emit_or(s1h,s2h,th);
2276 emit_not(tl,tl);
2277 emit_not(th,th);
2278 }
2279 }
2280 else
2281 {
2282 if(opcode2[i]==0x24) { // AND
2283 emit_zeroreg(tl);
2284 emit_zeroreg(th);
2285 } else
2286 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2287 if(rs1[i]){
2288 if(s1l>=0) emit_mov(s1l,tl);
2289 else emit_loadreg(rs1[i],tl);
2290 if(s1h>=0) emit_mov(s1h,th);
2291 else emit_loadreg(rs1[i]|64,th);
2292 }
2293 else
2294 if(rs2[i]){
2295 if(s2l>=0) emit_mov(s2l,tl);
2296 else emit_loadreg(rs2[i],tl);
2297 if(s2h>=0) emit_mov(s2h,th);
2298 else emit_loadreg(rs2[i]|64,th);
2299 }
2300 else{
2301 emit_zeroreg(tl);
2302 emit_zeroreg(th);
2303 }
2304 } else
2305 if(opcode2[i]==0x27) { // NOR
2306 if(rs1[i]){
2307 if(s1l>=0) emit_not(s1l,tl);
2308 else{
2309 emit_loadreg(rs1[i],tl);
2310 emit_not(tl,tl);
2311 }
2312 if(s1h>=0) emit_not(s1h,th);
2313 else{
2314 emit_loadreg(rs1[i]|64,th);
2315 emit_not(th,th);
2316 }
2317 }
2318 else
2319 if(rs2[i]){
2320 if(s2l>=0) emit_not(s2l,tl);
2321 else{
2322 emit_loadreg(rs2[i],tl);
2323 emit_not(tl,tl);
2324 }
2325 if(s2h>=0) emit_not(s2h,th);
2326 else{
2327 emit_loadreg(rs2[i]|64,th);
2328 emit_not(th,th);
2329 }
2330 }
2331 else {
2332 emit_movimm(-1,tl);
2333 emit_movimm(-1,th);
2334 }
2335 }
2336 }
2337 }
2338 }
2339 else
2340 {
2341 // 32 bit
2342 if(tl>=0) {
2343 s1l=get_reg(i_regs->regmap,rs1[i]);
2344 s2l=get_reg(i_regs->regmap,rs2[i]);
2345 if(rs1[i]&&rs2[i]) {
2346 assert(s1l>=0);
2347 assert(s2l>=0);
2348 if(opcode2[i]==0x24) { // AND
2349 emit_and(s1l,s2l,tl);
2350 } else
2351 if(opcode2[i]==0x25) { // OR
2352 emit_or(s1l,s2l,tl);
2353 } else
2354 if(opcode2[i]==0x26) { // XOR
2355 emit_xor(s1l,s2l,tl);
2356 } else
2357 if(opcode2[i]==0x27) { // NOR
2358 emit_or(s1l,s2l,tl);
2359 emit_not(tl,tl);
2360 }
2361 }
2362 else
2363 {
2364 if(opcode2[i]==0x24) { // AND
2365 emit_zeroreg(tl);
2366 } else
2367 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2368 if(rs1[i]){
2369 if(s1l>=0) emit_mov(s1l,tl);
2370 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2371 }
2372 else
2373 if(rs2[i]){
2374 if(s2l>=0) emit_mov(s2l,tl);
2375 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2376 }
2377 else emit_zeroreg(tl);
2378 } else
2379 if(opcode2[i]==0x27) { // NOR
2380 if(rs1[i]){
2381 if(s1l>=0) emit_not(s1l,tl);
2382 else {
2383 emit_loadreg(rs1[i],tl);
2384 emit_not(tl,tl);
2385 }
2386 }
2387 else
2388 if(rs2[i]){
2389 if(s2l>=0) emit_not(s2l,tl);
2390 else {
2391 emit_loadreg(rs2[i],tl);
2392 emit_not(tl,tl);
2393 }
2394 }
2395 else emit_movimm(-1,tl);
2396 }
2397 }
2398 }
2399 }
2400 }
2401 }
2402}
2403
2404void imm16_assemble(int i,struct regstat *i_regs)
2405{
2406 if (opcode[i]==0x0f) { // LUI
2407 if(rt1[i]) {
2408 signed char t;
2409 t=get_reg(i_regs->regmap,rt1[i]);
2410 //assert(t>=0);
2411 if(t>=0) {
2412 if(!((i_regs->isconst>>t)&1))
2413 emit_movimm(imm[i]<<16,t);
2414 }
2415 }
2416 }
2417 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2418 if(rt1[i]) {
2419 signed char s,t;
2420 t=get_reg(i_regs->regmap,rt1[i]);
2421 s=get_reg(i_regs->regmap,rs1[i]);
2422 if(rs1[i]) {
2423 //assert(t>=0);
2424 //assert(s>=0);
2425 if(t>=0) {
2426 if(!((i_regs->isconst>>t)&1)) {
2427 if(s<0) {
2428 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2429 emit_addimm(t,imm[i],t);
2430 }else{
2431 if(!((i_regs->wasconst>>s)&1))
2432 emit_addimm(s,imm[i],t);
2433 else
2434 emit_movimm(constmap[i][s]+imm[i],t);
2435 }
2436 }
2437 }
2438 } else {
2439 if(t>=0) {
2440 if(!((i_regs->isconst>>t)&1))
2441 emit_movimm(imm[i],t);
2442 }
2443 }
2444 }
2445 }
2446 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2447 if(rt1[i]) {
2448 signed char sh,sl,th,tl;
2449 th=get_reg(i_regs->regmap,rt1[i]|64);
2450 tl=get_reg(i_regs->regmap,rt1[i]);
2451 sh=get_reg(i_regs->regmap,rs1[i]|64);
2452 sl=get_reg(i_regs->regmap,rs1[i]);
2453 if(tl>=0) {
2454 if(rs1[i]) {
2455 assert(sh>=0);
2456 assert(sl>=0);
2457 if(th>=0) {
2458 emit_addimm64_32(sh,sl,imm[i],th,tl);
2459 }
2460 else {
2461 emit_addimm(sl,imm[i],tl);
2462 }
2463 } else {
2464 emit_movimm(imm[i],tl);
2465 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2466 }
2467 }
2468 }
2469 }
2470 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2471 if(rt1[i]) {
2472 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2473 signed char sh,sl,t;
2474 t=get_reg(i_regs->regmap,rt1[i]);
2475 sh=get_reg(i_regs->regmap,rs1[i]|64);
2476 sl=get_reg(i_regs->regmap,rs1[i]);
2477 //assert(t>=0);
2478 if(t>=0) {
2479 if(rs1[i]>0) {
2480 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2481 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2482 if(opcode[i]==0x0a) { // SLTI
2483 if(sl<0) {
2484 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2485 emit_slti32(t,imm[i],t);
2486 }else{
2487 emit_slti32(sl,imm[i],t);
2488 }
2489 }
2490 else { // SLTIU
2491 if(sl<0) {
2492 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2493 emit_sltiu32(t,imm[i],t);
2494 }else{
2495 emit_sltiu32(sl,imm[i],t);
2496 }
2497 }
2498 }else{ // 64-bit
2499 assert(sl>=0);
2500 if(opcode[i]==0x0a) // SLTI
2501 emit_slti64_32(sh,sl,imm[i],t);
2502 else // SLTIU
2503 emit_sltiu64_32(sh,sl,imm[i],t);
2504 }
2505 }else{
2506 // SLTI(U) with r0 is just stupid,
2507 // nonetheless examples can be found
2508 if(opcode[i]==0x0a) // SLTI
2509 if(0<imm[i]) emit_movimm(1,t);
2510 else emit_zeroreg(t);
2511 else // SLTIU
2512 {
2513 if(imm[i]) emit_movimm(1,t);
2514 else emit_zeroreg(t);
2515 }
2516 }
2517 }
2518 }
2519 }
2520 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2521 if(rt1[i]) {
2522 signed char sh,sl,th,tl;
2523 th=get_reg(i_regs->regmap,rt1[i]|64);
2524 tl=get_reg(i_regs->regmap,rt1[i]);
2525 sh=get_reg(i_regs->regmap,rs1[i]|64);
2526 sl=get_reg(i_regs->regmap,rs1[i]);
2527 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2528 if(opcode[i]==0x0c) //ANDI
2529 {
2530 if(rs1[i]) {
2531 if(sl<0) {
2532 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2533 emit_andimm(tl,imm[i],tl);
2534 }else{
2535 if(!((i_regs->wasconst>>sl)&1))
2536 emit_andimm(sl,imm[i],tl);
2537 else
2538 emit_movimm(constmap[i][sl]&imm[i],tl);
2539 }
2540 }
2541 else
2542 emit_zeroreg(tl);
2543 if(th>=0) emit_zeroreg(th);
2544 }
2545 else
2546 {
2547 if(rs1[i]) {
2548 if(sl<0) {
2549 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2550 }
2551 if(th>=0) {
2552 if(sh<0) {
2553 emit_loadreg(rs1[i]|64,th);
2554 }else{
2555 emit_mov(sh,th);
2556 }
2557 }
2558 if(opcode[i]==0x0d) //ORI
2559 if(sl<0) {
2560 emit_orimm(tl,imm[i],tl);
2561 }else{
2562 if(!((i_regs->wasconst>>sl)&1))
2563 emit_orimm(sl,imm[i],tl);
2564 else
2565 emit_movimm(constmap[i][sl]|imm[i],tl);
2566 }
2567 if(opcode[i]==0x0e) //XORI
2568 if(sl<0) {
2569 emit_xorimm(tl,imm[i],tl);
2570 }else{
2571 if(!((i_regs->wasconst>>sl)&1))
2572 emit_xorimm(sl,imm[i],tl);
2573 else
2574 emit_movimm(constmap[i][sl]^imm[i],tl);
2575 }
2576 }
2577 else {
2578 emit_movimm(imm[i],tl);
2579 if(th>=0) emit_zeroreg(th);
2580 }
2581 }
2582 }
2583 }
2584 }
2585}
2586
2587void shiftimm_assemble(int i,struct regstat *i_regs)
2588{
2589 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2590 {
2591 if(rt1[i]) {
2592 signed char s,t;
2593 t=get_reg(i_regs->regmap,rt1[i]);
2594 s=get_reg(i_regs->regmap,rs1[i]);
2595 //assert(t>=0);
2596 if(t>=0){
2597 if(rs1[i]==0)
2598 {
2599 emit_zeroreg(t);
2600 }
2601 else
2602 {
2603 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2604 if(imm[i]) {
2605 if(opcode2[i]==0) // SLL
2606 {
2607 emit_shlimm(s<0?t:s,imm[i],t);
2608 }
2609 if(opcode2[i]==2) // SRL
2610 {
2611 emit_shrimm(s<0?t:s,imm[i],t);
2612 }
2613 if(opcode2[i]==3) // SRA
2614 {
2615 emit_sarimm(s<0?t:s,imm[i],t);
2616 }
2617 }else{
2618 // Shift by zero
2619 if(s>=0 && s!=t) emit_mov(s,t);
2620 }
2621 }
2622 }
2623 //emit_storereg(rt1[i],t); //DEBUG
2624 }
2625 }
2626 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2627 {
2628 if(rt1[i]) {
2629 signed char sh,sl,th,tl;
2630 th=get_reg(i_regs->regmap,rt1[i]|64);
2631 tl=get_reg(i_regs->regmap,rt1[i]);
2632 sh=get_reg(i_regs->regmap,rs1[i]|64);
2633 sl=get_reg(i_regs->regmap,rs1[i]);
2634 if(tl>=0) {
2635 if(rs1[i]==0)
2636 {
2637 emit_zeroreg(tl);
2638 if(th>=0) emit_zeroreg(th);
2639 }
2640 else
2641 {
2642 assert(sl>=0);
2643 assert(sh>=0);
2644 if(imm[i]) {
2645 if(opcode2[i]==0x38) // DSLL
2646 {
2647 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2648 emit_shlimm(sl,imm[i],tl);
2649 }
2650 if(opcode2[i]==0x3a) // DSRL
2651 {
2652 emit_shrdimm(sl,sh,imm[i],tl);
2653 if(th>=0) emit_shrimm(sh,imm[i],th);
2654 }
2655 if(opcode2[i]==0x3b) // DSRA
2656 {
2657 emit_shrdimm(sl,sh,imm[i],tl);
2658 if(th>=0) emit_sarimm(sh,imm[i],th);
2659 }
2660 }else{
2661 // Shift by zero
2662 if(sl!=tl) emit_mov(sl,tl);
2663 if(th>=0&&sh!=th) emit_mov(sh,th);
2664 }
2665 }
2666 }
2667 }
2668 }
2669 if(opcode2[i]==0x3c) // DSLL32
2670 {
2671 if(rt1[i]) {
2672 signed char sl,tl,th;
2673 tl=get_reg(i_regs->regmap,rt1[i]);
2674 th=get_reg(i_regs->regmap,rt1[i]|64);
2675 sl=get_reg(i_regs->regmap,rs1[i]);
2676 if(th>=0||tl>=0){
2677 assert(tl>=0);
2678 assert(th>=0);
2679 assert(sl>=0);
2680 emit_mov(sl,th);
2681 emit_zeroreg(tl);
2682 if(imm[i]>32)
2683 {
2684 emit_shlimm(th,imm[i]&31,th);
2685 }
2686 }
2687 }
2688 }
2689 if(opcode2[i]==0x3e) // DSRL32
2690 {
2691 if(rt1[i]) {
2692 signed char sh,tl,th;
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 th=get_reg(i_regs->regmap,rt1[i]|64);
2695 sh=get_reg(i_regs->regmap,rs1[i]|64);
2696 if(tl>=0){
2697 assert(sh>=0);
2698 emit_mov(sh,tl);
2699 if(th>=0) emit_zeroreg(th);
2700 if(imm[i]>32)
2701 {
2702 emit_shrimm(tl,imm[i]&31,tl);
2703 }
2704 }
2705 }
2706 }
2707 if(opcode2[i]==0x3f) // DSRA32
2708 {
2709 if(rt1[i]) {
2710 signed char sh,tl;
2711 tl=get_reg(i_regs->regmap,rt1[i]);
2712 sh=get_reg(i_regs->regmap,rs1[i]|64);
2713 if(tl>=0){
2714 assert(sh>=0);
2715 emit_mov(sh,tl);
2716 if(imm[i]>32)
2717 {
2718 emit_sarimm(tl,imm[i]&31,tl);
2719 }
2720 }
2721 }
2722 }
2723}
2724
2725#ifndef shift_assemble
2726void shift_assemble(int i,struct regstat *i_regs)
2727{
2728 printf("Need shift_assemble for this architecture.\n");
2729 exit(1);
2730}
2731#endif
2732
2733void load_assemble(int i,struct regstat *i_regs)
2734{
2735 int s,th,tl,addr,map=-1;
2736 int offset;
2737 int jaddr=0;
5bf843dc 2738 int memtarget=0,c=0;
57871462 2739 u_int hr,reglist=0;
2740 th=get_reg(i_regs->regmap,rt1[i]|64);
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 s=get_reg(i_regs->regmap,rs1[i]);
2743 offset=imm[i];
2744 for(hr=0;hr<HOST_REGS;hr++) {
2745 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2746 }
2747 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2748 if(s>=0) {
2749 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2750 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2751 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2752 }
57871462 2753 //printf("load_assemble: c=%d\n",c);
2754 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2755 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2756#ifdef PCSX
f18c0f46 2757 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2758 ||rt1[i]==0) {
5bf843dc 2759 // could be FIFO, must perform the read
f18c0f46 2760 // ||dummy read
5bf843dc 2761 assem_debug("(forced read)\n");
2762 tl=get_reg(i_regs->regmap,-1);
2763 assert(tl>=0);
5bf843dc 2764 }
f18c0f46 2765#endif
5bf843dc 2766 if(offset||s<0||c) addr=tl;
2767 else addr=s;
57871462 2768 if(tl>=0) {
2769 //assert(tl>=0);
2770 //assert(rt1[i]);
2771 reglist&=~(1<<tl);
2772 if(th>=0) reglist&=~(1<<th);
2773 if(!using_tlb) {
2774 if(!c) {
2775//#define R29_HACK 1
2776 #ifdef R29_HACK
2777 // Strmnnrmn's speed hack
4cb76aa4 2778 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 2779 #endif
2780 {
4cb76aa4 2781 emit_cmpimm(addr,RAM_SIZE);
57871462 2782 jaddr=(int)out;
2783 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2784 // Hint to branch predictor that the branch is unlikely to be taken
2785 if(rs1[i]>=28)
2786 emit_jno_unlikely(0);
2787 else
2788 #endif
2789 emit_jno(0);
2790 }
2791 }
2792 }else{ // using tlb
2793 int x=0;
2794 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2795 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2796 map=get_reg(i_regs->regmap,TLREG);
2797 assert(map>=0);
2798 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2799 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2800 }
2801 if (opcode[i]==0x20) { // LB
2802 if(!c||memtarget) {
2803 #ifdef HOST_IMM_ADDR32
2804 if(c)
2805 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2806 else
2807 #endif
2808 {
2809 //emit_xorimm(addr,3,tl);
2810 //gen_tlb_addr_r(tl,map);
2811 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2812 int x=0;
2002a1db 2813#ifdef BIG_ENDIAN_MIPS
57871462 2814 if(!c) emit_xorimm(addr,3,tl);
2815 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2816#else
2817 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2818 else if (tl!=addr) emit_mov(addr,tl);
2819#endif
57871462 2820 emit_movsbl_indexed_tlb(x,tl,map,tl);
2821 }
2822 if(jaddr)
2823 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2824 }
2825 else
2826 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2827 }
2828 if (opcode[i]==0x21) { // LH
2829 if(!c||memtarget) {
2830 #ifdef HOST_IMM_ADDR32
2831 if(c)
2832 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2833 else
2834 #endif
2835 {
2836 int x=0;
2002a1db 2837#ifdef BIG_ENDIAN_MIPS
57871462 2838 if(!c) emit_xorimm(addr,2,tl);
2839 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2840#else
2841 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2842 else if (tl!=addr) emit_mov(addr,tl);
2843#endif
57871462 2844 //#ifdef
2845 //emit_movswl_indexed_tlb(x,tl,map,tl);
2846 //else
2847 if(map>=0) {
2848 gen_tlb_addr_r(tl,map);
2849 emit_movswl_indexed(x,tl,tl);
2850 }else
2851 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2852 }
2853 if(jaddr)
2854 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2855 }
2856 else
2857 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2858 }
2859 if (opcode[i]==0x23) { // LW
2860 if(!c||memtarget) {
2861 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2862 #ifdef HOST_IMM_ADDR32
2863 if(c)
2864 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2865 else
2866 #endif
2867 emit_readword_indexed_tlb(0,addr,map,tl);
2868 if(jaddr)
2869 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2870 }
2871 else
2872 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2873 }
2874 if (opcode[i]==0x24) { // LBU
2875 if(!c||memtarget) {
2876 #ifdef HOST_IMM_ADDR32
2877 if(c)
2878 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2879 else
2880 #endif
2881 {
2882 //emit_xorimm(addr,3,tl);
2883 //gen_tlb_addr_r(tl,map);
2884 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2885 int x=0;
2002a1db 2886#ifdef BIG_ENDIAN_MIPS
57871462 2887 if(!c) emit_xorimm(addr,3,tl);
2888 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2889#else
2890 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2891 else if (tl!=addr) emit_mov(addr,tl);
2892#endif
57871462 2893 emit_movzbl_indexed_tlb(x,tl,map,tl);
2894 }
2895 if(jaddr)
2896 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2897 }
2898 else
2899 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2900 }
2901 if (opcode[i]==0x25) { // LHU
2902 if(!c||memtarget) {
2903 #ifdef HOST_IMM_ADDR32
2904 if(c)
2905 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2906 else
2907 #endif
2908 {
2909 int x=0;
2002a1db 2910#ifdef BIG_ENDIAN_MIPS
57871462 2911 if(!c) emit_xorimm(addr,2,tl);
2912 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2913#else
2914 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2915 else if (tl!=addr) emit_mov(addr,tl);
2916#endif
57871462 2917 //#ifdef
2918 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2919 //#else
2920 if(map>=0) {
2921 gen_tlb_addr_r(tl,map);
2922 emit_movzwl_indexed(x,tl,tl);
2923 }else
2924 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2925 if(jaddr)
2926 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2927 }
2928 }
2929 else
2930 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2931 }
2932 if (opcode[i]==0x27) { // LWU
2933 assert(th>=0);
2934 if(!c||memtarget) {
2935 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2936 #ifdef HOST_IMM_ADDR32
2937 if(c)
2938 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2939 else
2940 #endif
2941 emit_readword_indexed_tlb(0,addr,map,tl);
2942 if(jaddr)
2943 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2944 }
2945 else {
2946 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2947 }
2948 emit_zeroreg(th);
2949 }
2950 if (opcode[i]==0x37) { // LD
2951 if(!c||memtarget) {
2952 //gen_tlb_addr_r(tl,map);
2953 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2954 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2955 #ifdef HOST_IMM_ADDR32
2956 if(c)
2957 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2958 else
2959 #endif
2960 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2961 if(jaddr)
2962 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2963 }
2964 else
2965 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2966 }
2967 //emit_storereg(rt1[i],tl); // DEBUG
2968 }
2969 //if(opcode[i]==0x23)
2970 //if(opcode[i]==0x24)
2971 //if(opcode[i]==0x23||opcode[i]==0x24)
2972 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2973 {
2974 //emit_pusha();
2975 save_regs(0x100f);
2976 emit_readword((int)&last_count,ECX);
2977 #ifdef __i386__
2978 if(get_reg(i_regs->regmap,CCREG)<0)
2979 emit_loadreg(CCREG,HOST_CCREG);
2980 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2981 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2982 emit_writeword(HOST_CCREG,(int)&Count);
2983 #endif
2984 #ifdef __arm__
2985 if(get_reg(i_regs->regmap,CCREG)<0)
2986 emit_loadreg(CCREG,0);
2987 else
2988 emit_mov(HOST_CCREG,0);
2989 emit_add(0,ECX,0);
2990 emit_addimm(0,2*ccadj[i],0);
2991 emit_writeword(0,(int)&Count);
2992 #endif
2993 emit_call((int)memdebug);
2994 //emit_popa();
2995 restore_regs(0x100f);
2996 }/**/
2997}
2998
2999#ifndef loadlr_assemble
3000void loadlr_assemble(int i,struct regstat *i_regs)
3001{
3002 printf("Need loadlr_assemble for this architecture.\n");
3003 exit(1);
3004}
3005#endif
3006
3007void store_assemble(int i,struct regstat *i_regs)
3008{
3009 int s,th,tl,map=-1;
3010 int addr,temp;
3011 int offset;
3012 int jaddr=0,jaddr2,type;
666a299d 3013 int memtarget=0,c=0;
57871462 3014 int agr=AGEN1+(i&1);
3015 u_int hr,reglist=0;
3016 th=get_reg(i_regs->regmap,rs2[i]|64);
3017 tl=get_reg(i_regs->regmap,rs2[i]);
3018 s=get_reg(i_regs->regmap,rs1[i]);
3019 temp=get_reg(i_regs->regmap,agr);
3020 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3021 offset=imm[i];
3022 if(s>=0) {
3023 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3024 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3025 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3026 }
3027 assert(tl>=0);
3028 assert(temp>=0);
3029 for(hr=0;hr<HOST_REGS;hr++) {
3030 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3031 }
3032 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3033 if(offset||s<0||c) addr=temp;
3034 else addr=s;
3035 if(!using_tlb) {
3036 if(!c) {
3037 #ifdef R29_HACK
3038 // Strmnnrmn's speed hack
3039 memtarget=1;
4cb76aa4 3040 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3041 #endif
4cb76aa4 3042 emit_cmpimm(addr,RAM_SIZE);
57871462 3043 #ifdef DESTRUCTIVE_SHIFT
3044 if(s==addr) emit_mov(s,temp);
3045 #endif
3046 #ifdef R29_HACK
4cb76aa4 3047 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3048 #endif
3049 {
3050 jaddr=(int)out;
3051 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3052 // Hint to branch predictor that the branch is unlikely to be taken
3053 if(rs1[i]>=28)
3054 emit_jno_unlikely(0);
3055 else
3056 #endif
3057 emit_jno(0);
3058 }
3059 }
3060 }else{ // using tlb
3061 int x=0;
3062 if (opcode[i]==0x28) x=3; // SB
3063 if (opcode[i]==0x29) x=2; // SH
3064 map=get_reg(i_regs->regmap,TLREG);
3065 assert(map>=0);
3066 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3067 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3068 }
3069
3070 if (opcode[i]==0x28) { // SB
3071 if(!c||memtarget) {
3072 int x=0;
2002a1db 3073#ifdef BIG_ENDIAN_MIPS
57871462 3074 if(!c) emit_xorimm(addr,3,temp);
3075 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3076#else
3077 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3078 else if (addr!=temp) emit_mov(addr,temp);
3079#endif
57871462 3080 //gen_tlb_addr_w(temp,map);
3081 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3082 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3083 }
3084 type=STOREB_STUB;
3085 }
3086 if (opcode[i]==0x29) { // SH
3087 if(!c||memtarget) {
3088 int x=0;
2002a1db 3089#ifdef BIG_ENDIAN_MIPS
57871462 3090 if(!c) emit_xorimm(addr,2,temp);
3091 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3092#else
3093 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3094 else if (addr!=temp) emit_mov(addr,temp);
3095#endif
57871462 3096 //#ifdef
3097 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3098 //#else
3099 if(map>=0) {
3100 gen_tlb_addr_w(temp,map);
3101 emit_writehword_indexed(tl,x,temp);
3102 }else
3103 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3104 }
3105 type=STOREH_STUB;
3106 }
3107 if (opcode[i]==0x2B) { // SW
3108 if(!c||memtarget)
3109 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3110 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3111 type=STOREW_STUB;
3112 }
3113 if (opcode[i]==0x3F) { // SD
3114 if(!c||memtarget) {
3115 if(rs2[i]) {
3116 assert(th>=0);
3117 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3118 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3119 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3120 }else{
3121 // Store zero
3122 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3123 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3124 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3125 }
3126 }
3127 type=STORED_STUB;
3128 }
666a299d 3129 if(!using_tlb&&(!c||memtarget))
3130 // addr could be a temp, make sure it survives STORE*_STUB
3131 reglist|=1<<addr;
57871462 3132 if(jaddr) {
3133 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3134 } else if(!memtarget) {
3135 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3136 }
3137 if(!using_tlb) {
3138 if(!c||memtarget) {
3139 #ifdef DESTRUCTIVE_SHIFT
3140 // The x86 shift operation is 'destructive'; it overwrites the
3141 // source register, so we need to make a copy first and use that.
3142 addr=temp;
3143 #endif
3144 #if defined(HOST_IMM8)
3145 int ir=get_reg(i_regs->regmap,INVCP);
3146 assert(ir>=0);
3147 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3148 #else
3149 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3150 #endif
3151 jaddr2=(int)out;
3152 emit_jne(0);
3153 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3154 }
3155 }
3156 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3157 //if(opcode[i]==0x2B || opcode[i]==0x28)
3158 //if(opcode[i]==0x2B || opcode[i]==0x29)
3159 //if(opcode[i]==0x2B)
3160 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3161 {
3162 //emit_pusha();
3163 save_regs(0x100f);
3164 emit_readword((int)&last_count,ECX);
3165 #ifdef __i386__
3166 if(get_reg(i_regs->regmap,CCREG)<0)
3167 emit_loadreg(CCREG,HOST_CCREG);
3168 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3169 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3170 emit_writeword(HOST_CCREG,(int)&Count);
3171 #endif
3172 #ifdef __arm__
3173 if(get_reg(i_regs->regmap,CCREG)<0)
3174 emit_loadreg(CCREG,0);
3175 else
3176 emit_mov(HOST_CCREG,0);
3177 emit_add(0,ECX,0);
3178 emit_addimm(0,2*ccadj[i],0);
3179 emit_writeword(0,(int)&Count);
3180 #endif
3181 emit_call((int)memdebug);
3182 //emit_popa();
3183 restore_regs(0x100f);
3184 }/**/
3185}
3186
3187void storelr_assemble(int i,struct regstat *i_regs)
3188{
3189 int s,th,tl;
3190 int temp;
3191 int temp2;
3192 int offset;
3193 int jaddr=0,jaddr2;
3194 int case1,case2,case3;
3195 int done0,done1,done2;
3196 int memtarget,c=0;
fab5d06d 3197 int agr=AGEN1+(i&1);
57871462 3198 u_int hr,reglist=0;
3199 th=get_reg(i_regs->regmap,rs2[i]|64);
3200 tl=get_reg(i_regs->regmap,rs2[i]);
3201 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3202 temp=get_reg(i_regs->regmap,agr);
3203 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3204 offset=imm[i];
3205 if(s>=0) {
3206 c=(i_regs->isconst>>s)&1;
4cb76aa4 3207 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3208 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3209 }
3210 assert(tl>=0);
3211 for(hr=0;hr<HOST_REGS;hr++) {
3212 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3213 }
3214 if(tl>=0) {
3215 assert(temp>=0);
3216 if(!using_tlb) {
3217 if(!c) {
4cb76aa4 3218 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
57871462 3219 if(!offset&&s!=temp) emit_mov(s,temp);
3220 jaddr=(int)out;
3221 emit_jno(0);
3222 }
3223 else
3224 {
3225 if(!memtarget||!rs1[i]) {
3226 jaddr=(int)out;
3227 emit_jmp(0);
3228 }
3229 }
3230 if((u_int)rdram!=0x80000000)
3231 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3232 }else{ // using tlb
3233 int map=get_reg(i_regs->regmap,TLREG);
3234 assert(map>=0);
3235 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3236 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3237 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3238 if(!jaddr&&!memtarget) {
3239 jaddr=(int)out;
3240 emit_jmp(0);
3241 }
3242 gen_tlb_addr_w(temp,map);
3243 }
3244
3245 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3246 temp2=get_reg(i_regs->regmap,FTEMP);
3247 if(!rs2[i]) temp2=th=tl;
3248 }
3249
2002a1db 3250#ifndef BIG_ENDIAN_MIPS
3251 emit_xorimm(temp,3,temp);
3252#endif
57871462 3253 emit_testimm(temp,2);
3254 case2=(int)out;
3255 emit_jne(0);
3256 emit_testimm(temp,1);
3257 case1=(int)out;
3258 emit_jne(0);
3259 // 0
3260 if (opcode[i]==0x2A) { // SWL
3261 emit_writeword_indexed(tl,0,temp);
3262 }
3263 if (opcode[i]==0x2E) { // SWR
3264 emit_writebyte_indexed(tl,3,temp);
3265 }
3266 if (opcode[i]==0x2C) { // SDL
3267 emit_writeword_indexed(th,0,temp);
3268 if(rs2[i]) emit_mov(tl,temp2);
3269 }
3270 if (opcode[i]==0x2D) { // SDR
3271 emit_writebyte_indexed(tl,3,temp);
3272 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3273 }
3274 done0=(int)out;
3275 emit_jmp(0);
3276 // 1
3277 set_jump_target(case1,(int)out);
3278 if (opcode[i]==0x2A) { // SWL
3279 // Write 3 msb into three least significant bytes
3280 if(rs2[i]) emit_rorimm(tl,8,tl);
3281 emit_writehword_indexed(tl,-1,temp);
3282 if(rs2[i]) emit_rorimm(tl,16,tl);
3283 emit_writebyte_indexed(tl,1,temp);
3284 if(rs2[i]) emit_rorimm(tl,8,tl);
3285 }
3286 if (opcode[i]==0x2E) { // SWR
3287 // Write two lsb into two most significant bytes
3288 emit_writehword_indexed(tl,1,temp);
3289 }
3290 if (opcode[i]==0x2C) { // SDL
3291 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3292 // Write 3 msb into three least significant bytes
3293 if(rs2[i]) emit_rorimm(th,8,th);
3294 emit_writehword_indexed(th,-1,temp);
3295 if(rs2[i]) emit_rorimm(th,16,th);
3296 emit_writebyte_indexed(th,1,temp);
3297 if(rs2[i]) emit_rorimm(th,8,th);
3298 }
3299 if (opcode[i]==0x2D) { // SDR
3300 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3301 // Write two lsb into two most significant bytes
3302 emit_writehword_indexed(tl,1,temp);
3303 }
3304 done1=(int)out;
3305 emit_jmp(0);
3306 // 2
3307 set_jump_target(case2,(int)out);
3308 emit_testimm(temp,1);
3309 case3=(int)out;
3310 emit_jne(0);
3311 if (opcode[i]==0x2A) { // SWL
3312 // Write two msb into two least significant bytes
3313 if(rs2[i]) emit_rorimm(tl,16,tl);
3314 emit_writehword_indexed(tl,-2,temp);
3315 if(rs2[i]) emit_rorimm(tl,16,tl);
3316 }
3317 if (opcode[i]==0x2E) { // SWR
3318 // Write 3 lsb into three most significant bytes
3319 emit_writebyte_indexed(tl,-1,temp);
3320 if(rs2[i]) emit_rorimm(tl,8,tl);
3321 emit_writehword_indexed(tl,0,temp);
3322 if(rs2[i]) emit_rorimm(tl,24,tl);
3323 }
3324 if (opcode[i]==0x2C) { // SDL
3325 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3326 // Write two msb into two least significant bytes
3327 if(rs2[i]) emit_rorimm(th,16,th);
3328 emit_writehword_indexed(th,-2,temp);
3329 if(rs2[i]) emit_rorimm(th,16,th);
3330 }
3331 if (opcode[i]==0x2D) { // SDR
3332 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3333 // Write 3 lsb into three most significant bytes
3334 emit_writebyte_indexed(tl,-1,temp);
3335 if(rs2[i]) emit_rorimm(tl,8,tl);
3336 emit_writehword_indexed(tl,0,temp);
3337 if(rs2[i]) emit_rorimm(tl,24,tl);
3338 }
3339 done2=(int)out;
3340 emit_jmp(0);
3341 // 3
3342 set_jump_target(case3,(int)out);
3343 if (opcode[i]==0x2A) { // SWL
3344 // Write msb into least significant byte
3345 if(rs2[i]) emit_rorimm(tl,24,tl);
3346 emit_writebyte_indexed(tl,-3,temp);
3347 if(rs2[i]) emit_rorimm(tl,8,tl);
3348 }
3349 if (opcode[i]==0x2E) { // SWR
3350 // Write entire word
3351 emit_writeword_indexed(tl,-3,temp);
3352 }
3353 if (opcode[i]==0x2C) { // SDL
3354 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3355 // Write msb into least significant byte
3356 if(rs2[i]) emit_rorimm(th,24,th);
3357 emit_writebyte_indexed(th,-3,temp);
3358 if(rs2[i]) emit_rorimm(th,8,th);
3359 }
3360 if (opcode[i]==0x2D) { // SDR
3361 if(rs2[i]) emit_mov(th,temp2);
3362 // Write entire word
3363 emit_writeword_indexed(tl,-3,temp);
3364 }
3365 set_jump_target(done0,(int)out);
3366 set_jump_target(done1,(int)out);
3367 set_jump_target(done2,(int)out);
3368 if (opcode[i]==0x2C) { // SDL
3369 emit_testimm(temp,4);
3370 done0=(int)out;
3371 emit_jne(0);
3372 emit_andimm(temp,~3,temp);
3373 emit_writeword_indexed(temp2,4,temp);
3374 set_jump_target(done0,(int)out);
3375 }
3376 if (opcode[i]==0x2D) { // SDR
3377 emit_testimm(temp,4);
3378 done0=(int)out;
3379 emit_jeq(0);
3380 emit_andimm(temp,~3,temp);
3381 emit_writeword_indexed(temp2,-4,temp);
3382 set_jump_target(done0,(int)out);
3383 }
3384 if(!c||!memtarget)
b7918751 3385 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3386 }
3387 if(!using_tlb) {
3388 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3389 #if defined(HOST_IMM8)
3390 int ir=get_reg(i_regs->regmap,INVCP);
3391 assert(ir>=0);
3392 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3393 #else
3394 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3395 #endif
3396 jaddr2=(int)out;
3397 emit_jne(0);
3398 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3399 }
3400 /*
3401 emit_pusha();
3402 //save_regs(0x100f);
3403 emit_readword((int)&last_count,ECX);
3404 if(get_reg(i_regs->regmap,CCREG)<0)
3405 emit_loadreg(CCREG,HOST_CCREG);
3406 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3407 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3408 emit_writeword(HOST_CCREG,(int)&Count);
3409 emit_call((int)memdebug);
3410 emit_popa();
3411 //restore_regs(0x100f);
3412 /**/
3413}
3414
3415void c1ls_assemble(int i,struct regstat *i_regs)
3416{
3d624f89 3417#ifndef DISABLE_COP1
57871462 3418 int s,th,tl;
3419 int temp,ar;
3420 int map=-1;
3421 int offset;
3422 int c=0;
3423 int jaddr,jaddr2=0,jaddr3,type;
3424 int agr=AGEN1+(i&1);
3425 u_int hr,reglist=0;
3426 th=get_reg(i_regs->regmap,FTEMP|64);
3427 tl=get_reg(i_regs->regma