notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
some skin adjustments
[picodrive.git] / Pico / PicoInt.h
CommitLineData
cc68a136 1// Pico Library - Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9\r
10#include <stdio.h>\r
11#include <stdlib.h>\r
12#include <string.h>\r
13#include "Pico.h"\r
14\r
89fa852d 15//\r
16#define USE_POLL_DETECT\r
17\r
cc68a136 18\r
ab0607f7 19// to select core, define EMU_C68K, EMU_M68K or EMU_A68K in your makefile or project\r
cc68a136 20\r
21#ifdef __cplusplus\r
22extern "C" {\r
23#endif\r
24\r
25\r
26// ----------------------- 68000 CPU -----------------------\r
27#ifdef EMU_C68K\r
28#include "../cpu/Cyclone/Cyclone.h"\r
b837b69b 29extern struct Cyclone PicoCpu, PicoCpuS68k;\r
7336a99a 30#define SekCyclesLeftNoMCD PicoCpu.cycles // cycles left for this run\r
31#define SekCyclesLeft \\r
32 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 33#define SekCyclesLeftS68k \\r
34 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuS68k.cycles)\r
7336a99a 35#define SekSetCyclesLeftNoMCD(c) PicoCpu.cycles=c\r
36#define SekSetCyclesLeft(c) { \\r
37 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
38}\r
cc68a136 39#define SekPc (PicoCpu.pc-PicoCpu.membase)\r
b837b69b 40#define SekPcS68k (PicoCpuS68k.pc-PicoCpuS68k.membase)\r
0af33fe0 41#define SekSetStop(x) { PicoCpu.state_flags&=~1; if (x) { PicoCpu.state_flags|=1; PicoCpu.cycles=0; } }\r
42#define SekSetStopS68k(x) { PicoCpuS68k.state_flags&=~1; if (x) { PicoCpuS68k.state_flags|=1; PicoCpuS68k.cycles=0; } }\r
cc68a136 43#endif\r
44\r
45#ifdef EMU_A68K\r
46void __cdecl M68000_RUN();\r
47// The format of the data in a68k.asm (at the _M68000_regs location)\r
48struct A68KContext\r
49{\r
50 unsigned int d[8],a[8];\r
51 unsigned int isp,srh,ccr,xc,pc,irq,sr;\r
52 int (*IrqCallback) (int nIrq);\r
53 unsigned int ppc;\r
54 void *pResetCallback;\r
55 unsigned int sfc,dfc,usp,vbr;\r
56 unsigned int AsmBank,CpuVersion;\r
57};\r
58struct A68KContext M68000_regs;\r
59extern int m68k_ICount;\r
60#define SekCyclesLeft m68k_ICount\r
61#define SekSetCyclesLeft(c) m68k_ICount=c\r
62#define SekPc M68000_regs.pc\r
63#endif\r
64\r
65#ifdef EMU_M68K\r
66#include "../cpu/musashi/m68kcpu.h"\r
67extern m68ki_cpu_core PicoM68kCPU; // MD's CPU\r
68extern m68ki_cpu_core PicoS68kCPU; // Mega CD's CPU\r
69#ifndef SekCyclesLeft\r
7a1f6e45 70#define SekCyclesLeftNoMCD PicoM68kCPU.cyc_remaining_cycles\r
7336a99a 71#define SekCyclesLeft \\r
72 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 73#define SekCyclesLeftS68k \\r
74 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoS68kCPU.cyc_remaining_cycles)\r
7336a99a 75#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
76#define SekSetCyclesLeft(c) { \\r
77 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
78}\r
cc68a136 79#define SekPc m68k_get_reg(&PicoM68kCPU, M68K_REG_PC)\r
80#define SekPcS68k m68k_get_reg(&PicoS68kCPU, M68K_REG_PC)\r
7a1f6e45 81#define SekSetStop(x) { \\r
82 if(x) { SET_CYCLES(0); PicoM68kCPU.stopped=STOP_LEVEL_STOP; } \\r
83 else PicoM68kCPU.stopped=0; \\r
84}\r
85#define SekSetStopS68k(x) { \\r
86 if(x) { SET_CYCLES(0); PicoS68kCPU.stopped=STOP_LEVEL_STOP; } \\r
87 else PicoS68kCPU.stopped=0; \\r
88}\r
cc68a136 89#endif\r
90#endif\r
91\r
92extern int SekCycleCnt; // cycles done in this frame\r
93extern int SekCycleAim; // cycle aim\r
94extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
95\r
96#define SekCyclesReset() {SekCycleCntT+=SekCycleCnt;SekCycleCnt=SekCycleAim=0;}\r
97#define SekCyclesBurn(c) SekCycleCnt+=c\r
98#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
99#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
100\r
101#define SekEndRun(after) { \\r
102 SekCycleCnt -= SekCyclesLeft - after; \\r
103 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
104 SekSetCyclesLeft(after); \\r
105}\r
106\r
107extern int SekCycleCntS68k;\r
108extern int SekCycleAimS68k;\r
109\r
110#define SekCyclesResetS68k() {SekCycleCntS68k=SekCycleAimS68k=0;}\r
7a1f6e45 111#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 112\r
2d0b15bb 113// debug cyclone\r
114#if defined(EMU_C68K) && defined(EMU_M68K)\r
115#undef SekSetCyclesLeftNoMCD\r
116#undef SekSetCyclesLeft\r
117#undef SekCyclesBurn\r
118#undef SekEndRun\r
119#define SekSetCyclesLeftNoMCD(c)\r
120#define SekSetCyclesLeft(c)\r
2270612a 121#define SekCyclesBurn(c) c\r
2d0b15bb 122#define SekEndRun(c)\r
123#endif\r
cc68a136 124\r
125extern int PicoMCD;\r
126\r
127// ---------------------------------------------------------\r
128\r
129// main oscillator clock which controls timing\r
130#define OSC_NTSC 53693100\r
131#define OSC_PAL 53203424 // not accurate\r
132\r
133struct PicoVideo\r
134{\r
135 unsigned char reg[0x20];\r
136 unsigned int command; // 32-bit Command\r
137 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
138 unsigned char type; // Command type (v/c/vsram read/write)\r
139 unsigned short addr; // Read/Write address\r
140 int status; // Status bits\r
141 unsigned char pending_ints; // pending interrupts: ??VH????\r
142 unsigned char pad[0x13];\r
143};\r
144\r
145struct PicoMisc\r
146{\r
147 unsigned char rotate;\r
148 unsigned char z80Run;\r
149 unsigned char padTHPhase[2]; // phase of gamepad TH switches\r
150 short scanline; // 0 to 261||311; -1 in fast mode\r
151 char dirtyPal; // Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
152 unsigned char hardware; // Hardware value for country\r
153 unsigned char pal; // 1=PAL 0=NTSC\r
721cd396 154 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
cc68a136 155 unsigned short z80_bank68k;\r
156 unsigned short z80_lastaddr; // this is for Z80 faking\r
157 unsigned char z80_fakeval;\r
158 unsigned char pad0;\r
159 unsigned char padDelay[2]; // gamepad phase time outs, so we count a delay\r
160 unsigned short sram_addr; // EEPROM address register\r
161 unsigned char sram_cycle; // EEPROM SRAM cycle number\r
162 unsigned char sram_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 163 unsigned char prot_bytes[2]; // simple protection faking\r
4f672280 164 unsigned short dma_bytes; //\r
312e9ce1 165 unsigned char pad[2];\r
166 unsigned int frame_count; // mainly for movies\r
cc68a136 167};\r
168\r
169// some assembly stuff depend on these, do not touch!\r
170struct Pico\r
171{\r
172 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
173 unsigned short vram[0x8000]; // 0x10000\r
174 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
175 unsigned char ioports[0x10];\r
176 unsigned int pad[0x3c]; // unused\r
177 unsigned short cram[0x40]; // 0x22100\r
178 unsigned short vsram[0x40]; // 0x22180\r
179\r
180 unsigned char *rom; // 0x22200\r
181 unsigned int romsize; // 0x22204\r
182\r
183 struct PicoMisc m;\r
184 struct PicoVideo video;\r
185};\r
186\r
187// sram\r
188struct PicoSRAM\r
189{\r
4ff2d527 190 unsigned char *data; // actual data\r
191 unsigned int start; // start address in 68k address space\r
cc68a136 192 unsigned int end;\r
4ff2d527 193 unsigned char resize; // 0c: 1=SRAM size changed and needs to be reallocated on PicoReset\r
194 unsigned char reg_back; // copy of Pico.m.sram_reg to set after reset\r
cc68a136 195 unsigned char changed;\r
196 unsigned char pad;\r
197};\r
198\r
199// MCD\r
200#include "cd/cd_sys.h"\r
201#include "cd/LC89510.h"\r
d1df8786 202#include "cd/gfx_cd.h"\r
cc68a136 203\r
4f265db7 204struct mcd_pcm\r
205{\r
206 unsigned char control; // reg7\r
207 unsigned char enabled; // reg8\r
208 unsigned char cur_ch;\r
209 unsigned char bank;\r
210 int pad1;\r
211\r
4ff2d527 212 struct pcm_chan // 08, size 0x10\r
4f265db7 213 {\r
214 unsigned char regs[8];\r
4ff2d527 215 unsigned int addr; // .08: played sample address\r
4f265db7 216 int pad;\r
217 } ch[8];\r
218};\r
219\r
c459aefd 220struct mcd_misc\r
221{\r
222 unsigned short hint_vector;\r
223 unsigned char busreq;\r
51a902ae 224 unsigned char s68k_pend_ints;\r
89fa852d 225 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 226 unsigned int counter75hz;\r
4ff2d527 227 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 228 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 229 char pad1;\r
4ff2d527 230 int timer_int3; // 10\r
4f265db7 231 unsigned int timer_stopwatch;\r
6cadc2da 232 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
233 unsigned char pad2;\r
234 unsigned short pad3;\r
235 int pad[9];\r
c459aefd 236};\r
237\r
cc68a136 238typedef struct\r
239{\r
4ff2d527 240 unsigned char bios[0x20000]; // 000000: 128K\r
241 union { // 020000: 512K\r
fa1e5e29 242 unsigned char prg_ram[0x80000];\r
cc68a136 243 unsigned char prg_ram_b[4][0x20000];\r
244 };\r
4ff2d527 245 union { // 0a0000: 256K\r
fa1e5e29 246 struct {\r
247 unsigned char word_ram2M[0x40000];\r
248 unsigned char unused[0x20000];\r
249 };\r
250 struct {\r
251 unsigned char unused[0x20000];\r
252 unsigned char word_ram1M[2][0x20000];\r
253 };\r
254 };\r
4ff2d527 255 union { // 100000: 64K\r
fa1e5e29 256 unsigned char pcm_ram[0x10000];\r
4f265db7 257 unsigned char pcm_ram_b[0x10][0x1000];\r
258 };\r
4ff2d527 259 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
260 unsigned char bram[0x2000]; // 110200: 8K\r
261 struct mcd_misc m; // 112200: misc\r
262 struct mcd_pcm pcm; // 112240:\r
75736070 263 _scd_toc TOC; // not to be saved\r
cc68a136 264 CDD cdd;\r
265 CDC cdc;\r
266 _scd scd;\r
d1df8786 267 Rot_Comp rot_comp;\r
cc68a136 268} mcd_state;\r
269\r
270#define Pico_mcd ((mcd_state *)Pico.rom)\r
271\r
51a902ae 272// Area.c\r
273int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
274int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
275\r
276// cd/Area.c\r
277int PicoCdSaveState(void *file);\r
278int PicoCdLoadState(void *file);\r
860c6322 279int PicoCdLoadStateGfx(void *file);\r
cc68a136 280\r
281// Draw.c\r
282int PicoLine(int scan);\r
283void PicoFrameStart();\r
284\r
285// Draw2.c\r
286void PicoFrameFull();\r
287\r
288// Memory.c\r
289int PicoInitPc(unsigned int pc);\r
290unsigned int CPU_CALL PicoRead32(unsigned int a);\r
b837b69b 291void PicoMemSetup();\r
cc68a136 292void PicoMemReset();\r
b837b69b 293//void PicoDasm(int start,int len);\r
cc68a136 294unsigned char z80_read(unsigned short a);\r
295unsigned short z80_read16(unsigned short a);\r
296void z80_write(unsigned char data, unsigned short a);\r
297void z80_write16(unsigned short data, unsigned short a);\r
298\r
299// cd/Memory.c\r
83bd0b76 300void PicoMemSetupCD(void);\r
4ff2d527 301void PicoMemResetCD(int r3);\r
48e8482f 302void PicoMemResetCDdecode(int r3);\r
cc68a136 303unsigned char PicoReadCD8 (unsigned int a);\r
304unsigned short PicoReadCD16(unsigned int a);\r
305unsigned int PicoReadCD32(unsigned int a);\r
306void PicoWriteCD8 (unsigned int a, unsigned char d);\r
307void PicoWriteCD16(unsigned int a, unsigned short d);\r
308void PicoWriteCD32(unsigned int a, unsigned int d);\r
309\r
310// Pico.c\r
311extern struct Pico Pico;\r
312extern struct PicoSRAM SRam;\r
313extern int emustatus;\r
d9153729 314extern int z80startCycle, z80stopCycle; // in 68k cycles\r
312e9ce1 315int CheckDMA(void);\r
cc68a136 316\r
317// cd/Pico.c\r
318int PicoInitMCD(void);\r
319void PicoExitMCD(void);\r
320int PicoResetMCD(int hard);\r
321\r
322// Sek.c\r
323int SekInit(void);\r
324int SekReset(void);\r
325int SekInterrupt(int irq);\r
326void SekState(unsigned char *data);\r
2433f409 327void SekSetRealTAS(int use_real);\r
cc68a136 328\r
329// cd/Sek.c\r
330int SekInitS68k(void);\r
331int SekResetS68k(void);\r
332int SekInterruptS68k(int irq);\r
333\r
7a93adeb 334// sound/sound.c\r
335extern int PsndLen_exc_cnt;\r
336extern int PsndLen_exc_add;\r
337\r
cc68a136 338// VideoPort.c\r
339void PicoVideoWrite(unsigned int a,unsigned short d);\r
340unsigned int PicoVideoRead(unsigned int a);\r
341\r
342// Misc.c\r
343void SRAMWriteEEPROM(unsigned int d);\r
344unsigned int SRAMReadEEPROM();\r
345void SRAMUpdPending(unsigned int a, unsigned int d);\r
cea65903 346void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
0a051f55 347void memcpy16bswap(unsigned short *dest, void *src, int count);\r
6cadc2da 348void memcpy32(int *dest, int *src, int count); // 32bit word count\r
cea65903 349void memset32(int *dest, int c, int count);\r
cc68a136 350\r
fa1e5e29 351// cd/Misc.c\r
352void wram_2M_to_1M(unsigned char *m);\r
353void wram_1M_to_2M(unsigned char *m);\r
354\r
cc68a136 355\r
356#ifdef __cplusplus\r
357} // End of extern "C"\r
358#endif\r
fast MegaDrive/MegaCD/32X emulator