e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
44e6452e |
3 | * |
4 | * notes: |
5 | * - tcache, block descriptor, link buffer overflows result in sh2_translate() |
6 | * failure, followed by full tcache invalidation for that region |
9bb5d91c |
7 | * - jumps between blocks are tracked for SMC handling (in block_links[]), |
8 | * except jumps between different tcaches |
9 | * |
10 | * implemented: |
11 | * - static register allocation |
12 | * - remaining register caching and tracking in temporaries |
13 | * - block-local branch linking |
14 | * - block linking (except between tcaches) |
23686515 |
15 | * - some constant propagation |
9bb5d91c |
16 | * |
17 | * TODO: |
18 | * - proper SMC handling |
23686515 |
19 | * - better constant propagation |
9bb5d91c |
20 | * - stack caching? |
21 | * - bug fixing |
e898de13 |
22 | */ |
f0d7b1fa |
23 | #include <stddef.h> |
679af8a3 |
24 | #include <stdio.h> |
25 | #include <stdlib.h> |
26 | #include <assert.h> |
41397701 |
27 | |
f4bb5d6b |
28 | #include "../../pico/pico_int.h" |
679af8a3 |
29 | #include "sh2.h" |
30 | #include "compiler.h" |
31 | #include "../drc/cmn.h" |
5686d931 |
32 | #include "../debug.h" |
679af8a3 |
33 | |
23686515 |
34 | // features |
35 | #define PROPAGATE_CONSTANTS 1 |
36 | #define LINK_BRANCHES 1 |
37 | |
38 | // max literal offset from the block end |
39 | #define MAX_LITERAL_OFFSET 32*2 |
40 | |
8796b7ee |
41 | // debug stuff { |
e898de13 |
42 | #ifndef DRC_DEBUG |
43 | #define DRC_DEBUG 0 |
44 | #endif |
45 | |
553c3eaa |
46 | #if DRC_DEBUG |
f4bb5d6b |
47 | #define dbg(l,...) { \ |
48 | if ((l) & DRC_DEBUG) \ |
49 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
50 | } |
51 | |
e898de13 |
52 | #include "mame/sh2dasm.h" |
53 | #include <platform/linux/host_dasm.h> |
54 | static int insns_compiled, hash_collisions, host_insn_count; |
553c3eaa |
55 | #define COUNT_OP \ |
56 | host_insn_count++ |
57 | #else // !DRC_DEBUG |
58 | #define COUNT_OP |
59 | #define dbg(...) |
e898de13 |
60 | #endif |
553c3eaa |
61 | |
e898de13 |
62 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
63 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
64 | static char sh2dasm_buff[64]; |
f4bb5d6b |
65 | #define do_host_disasm(tcid) \ |
66 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
67 | tcache_dsm_ptrs[tcid] = tcache_ptr |
68 | #else |
69 | #define do_host_disasm(x) |
e898de13 |
70 | #endif |
e05b81fc |
71 | |
5686d931 |
72 | #if (DRC_DEBUG & 4) || defined(PDB) |
73 | static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr) |
e05b81fc |
74 | { |
5686d931 |
75 | if (block != NULL) { |
e05b81fc |
76 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
77 | sh2->pc, block, (signed int)sr >> 12); |
5686d931 |
78 | pdb_step(sh2, sh2->pc); |
79 | } |
e05b81fc |
80 | return block; |
81 | } |
82 | #endif |
8796b7ee |
83 | // } debug |
e898de13 |
84 | |
679af8a3 |
85 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
86 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
44e6452e |
87 | #define TCACHE_BUFFERS 3 |
f4bb5d6b |
88 | |
89 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
90 | // BIOS shares tcache with data array because it's only used for init |
91 | // and can be discarded early |
8796b7ee |
92 | // XXX: need to tune sizes |
44e6452e |
93 | static const int tcache_sizes[TCACHE_BUFFERS] = { |
f4bb5d6b |
94 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
95 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
96 | DRC_TCACHE_SIZE / 8, // ... slave |
97 | }; |
679af8a3 |
98 | |
44e6452e |
99 | static u8 *tcache_bases[TCACHE_BUFFERS]; |
100 | static u8 *tcache_ptrs[TCACHE_BUFFERS]; |
f4bb5d6b |
101 | |
102 | // ptr for code emiters |
103 | static u8 *tcache_ptr; |
e898de13 |
104 | |
44e6452e |
105 | typedef struct block_desc_ { |
106 | u32 addr; // SH2 PC address |
44e6452e |
107 | void *tcache_ptr; // translated block for above PC |
108 | struct block_desc_ *next; // next block with the same PC hash |
109 | #if (DRC_DEBUG & 1) |
110 | int refcount; |
111 | #endif |
112 | } block_desc; |
113 | |
114 | typedef struct block_link_ { |
115 | u32 target_pc; |
a2b8c5a5 |
116 | void *jump; // insn address |
44e6452e |
117 | // struct block_link_ *next; |
118 | } block_link; |
119 | |
120 | static const int block_max_counts[TCACHE_BUFFERS] = { |
121 | 4*1024, |
122 | 256, |
123 | 256, |
124 | }; |
125 | static block_desc *block_tables[TCACHE_BUFFERS]; |
126 | static block_link *block_links[TCACHE_BUFFERS]; |
127 | static int block_counts[TCACHE_BUFFERS]; |
128 | static int block_link_counts[TCACHE_BUFFERS]; |
129 | |
c18edb34 |
130 | // host register tracking |
131 | enum { |
132 | HR_FREE, |
133 | HR_CACHED, // 'val' has sh2_reg_e |
23686515 |
134 | // HR_CONST, // 'val' has a constant |
c18edb34 |
135 | HR_TEMP, // reg used for temp storage |
136 | }; |
137 | |
23686515 |
138 | enum { |
139 | HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx |
140 | HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted |
141 | }; |
142 | |
c18edb34 |
143 | typedef struct { |
23686515 |
144 | u32 hreg:5; // "host" reg |
145 | u32 greg:5; // "guest" reg |
146 | u32 type:3; |
147 | u32 flags:3; |
148 | u32 stamp:16; // kind of a timestamp |
c18edb34 |
149 | } temp_reg_t; |
150 | |
80599a42 |
151 | // note: reg_temp[] must have at least the amount of |
3863edbd |
152 | // registers used by handlers in worst case (currently 4) |
65c75cb0 |
153 | #ifdef ARM |
154 | #include "../drc/emit_arm.c" |
155 | |
156 | static const int reg_map_g2h[] = { |
8b4f38f4 |
157 | 4, 5, 6, 7, |
158 | 8, -1, -1, -1, |
c18edb34 |
159 | -1, -1, -1, -1, |
8b4f38f4 |
160 | -1, -1, -1, 9, |
161 | -1, -1, -1, 10, |
c18edb34 |
162 | -1, -1, -1, -1, |
163 | }; |
164 | |
165 | static temp_reg_t reg_temp[] = { |
166 | { 0, }, |
167 | { 1, }, |
168 | { 12, }, |
169 | { 14, }, |
170 | { 2, }, |
171 | { 3, }, |
65c75cb0 |
172 | }; |
173 | |
e05b81fc |
174 | #elif defined(__i386__) |
e898de13 |
175 | #include "../drc/emit_x86.c" |
176 | |
65c75cb0 |
177 | static const int reg_map_g2h[] = { |
8b4f38f4 |
178 | xSI,-1, -1, -1, |
c18edb34 |
179 | -1, -1, -1, -1, |
180 | -1, -1, -1, -1, |
181 | -1, -1, -1, -1, |
8b4f38f4 |
182 | -1, -1, -1, xDI, |
c18edb34 |
183 | -1, -1, -1, -1, |
184 | }; |
185 | |
3863edbd |
186 | // ax, cx, dx are usually temporaries by convention |
c18edb34 |
187 | static temp_reg_t reg_temp[] = { |
188 | { xAX, }, |
3863edbd |
189 | { xBX, }, |
c18edb34 |
190 | { xCX, }, |
191 | { xDX, }, |
65c75cb0 |
192 | }; |
193 | |
e05b81fc |
194 | #else |
195 | #error unsupported arch |
65c75cb0 |
196 | #endif |
197 | |
80599a42 |
198 | #define T 0x00000001 |
199 | #define S 0x00000002 |
200 | #define I 0x000000f0 |
201 | #define Q 0x00000100 |
202 | #define M 0x00000200 |
18b94127 |
203 | #define T_save 0x00000800 |
80599a42 |
204 | |
e05b81fc |
205 | #define I_SHIFT 4 |
f0d7b1fa |
206 | #define Q_SHIFT 8 |
207 | #define M_SHIFT 9 |
208 | |
f4bb5d6b |
209 | // ROM hash table |
679af8a3 |
210 | #define MAX_HASH_ENTRIES 1024 |
211 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
212 | static void **hash_table; |
679af8a3 |
213 | |
18b94127 |
214 | #define HASH_FUNC(hash_tab, addr) \ |
215 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
216 | |
e05b81fc |
217 | static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2); |
218 | static void (*sh2_drc_dispatcher)(void); |
219 | static void (*sh2_drc_exit)(void); |
220 | static void (*sh2_drc_test_irq)(void); |
5686d931 |
221 | |
222 | static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2); |
223 | static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2); |
224 | static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2); |
e05b81fc |
225 | static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d); |
226 | static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d); |
227 | static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); |
228 | static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d); |
5686d931 |
229 | static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2); |
679af8a3 |
230 | |
553c3eaa |
231 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
679af8a3 |
232 | |
a2b8c5a5 |
233 | // address space stuff |
234 | static void *dr_get_pc_base(u32 pc, int is_slave) |
235 | { |
236 | void *ret = NULL; |
237 | u32 mask = 0; |
238 | |
239 | if ((pc & ~0x7ff) == 0) { |
240 | // BIOS |
241 | ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; |
242 | mask = 0x7ff; |
243 | } |
244 | else if ((pc & 0xfffff000) == 0xc0000000) { |
245 | // data array |
246 | ret = Pico32xMem->data_array[is_slave]; |
247 | mask = 0xfff; |
248 | } |
249 | else if ((pc & 0xc6000000) == 0x06000000) { |
250 | // SDRAM |
251 | ret = Pico32xMem->sdram; |
252 | mask = 0x03ffff; |
253 | } |
254 | else if ((pc & 0xc6000000) == 0x02000000) { |
255 | // ROM |
256 | ret = Pico.rom; |
257 | mask = 0x3fffff; |
258 | } |
259 | |
260 | if (ret == NULL) |
261 | return (void *)-1; // NULL is valid value |
262 | |
263 | return (char *)ret - (pc & ~mask); |
264 | } |
265 | |
266 | static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) |
267 | { |
268 | int poffs = -1; |
269 | |
270 | if ((a & ~0x7ff) == 0) { |
271 | // BIOS |
272 | poffs = offsetof(SH2, p_bios); |
273 | *mask = 0x7ff; |
274 | } |
275 | else if ((a & 0xfffff000) == 0xc0000000) { |
276 | // data array |
277 | poffs = offsetof(SH2, p_da); |
278 | *mask = 0xfff; |
279 | } |
280 | else if ((a & 0xc6000000) == 0x06000000) { |
281 | // SDRAM |
282 | poffs = offsetof(SH2, p_sdram); |
283 | *mask = 0x03ffff; |
284 | } |
285 | else if ((a & 0xc6000000) == 0x02000000) { |
286 | // ROM |
287 | poffs = offsetof(SH2, p_rom); |
288 | *mask = 0x3fffff; |
289 | } |
290 | |
291 | return poffs; |
292 | } |
293 | |
294 | static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id) |
295 | { |
296 | *tcache_id = 0; |
297 | |
298 | // we have full block id tables for data_array and RAM |
299 | // BIOS goes to data_array table too |
300 | if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) { |
301 | int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
302 | *tcache_id = 1 + is_slave; |
303 | if (blkid & 1) |
304 | return &block_tables[*tcache_id][blkid >> 1]; |
305 | } |
306 | // RAM |
307 | else if ((pc & 0xc6000000) == 0x06000000) { |
308 | int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
309 | if (blkid & 1) |
310 | return &block_tables[0][blkid >> 1]; |
311 | } |
312 | // ROM |
313 | else if ((pc & 0xc6000000) == 0x02000000) { |
314 | block_desc *bd = HASH_FUNC(hash_table, pc); |
315 | |
316 | for (; bd != NULL; bd = bd->next) |
317 | if (bd->addr == pc) |
318 | return bd; |
319 | } |
320 | |
321 | return NULL; |
322 | } |
323 | |
324 | // --------------------------------------------------------------- |
325 | |
326 | // block management |
327 | static void REGPARM(1) flush_tcache(int tcid) |
f4bb5d6b |
328 | { |
553c3eaa |
329 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
f4bb5d6b |
330 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
331 | block_counts[tcid], block_max_counts[tcid]); |
332 | |
333 | block_counts[tcid] = 0; |
a2b8c5a5 |
334 | block_link_counts[tcid] = 0; |
f4bb5d6b |
335 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
336 | if (tcid == 0) { // ROM, RAM |
337 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
338 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
339 | } |
340 | else |
341 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
342 | #if (DRC_DEBUG & 2) |
343 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
344 | #endif |
345 | } |
346 | |
5686d931 |
347 | #if LINK_BRANCHES |
44e6452e |
348 | // add block links (tracked branches) |
349 | static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id) |
350 | { |
351 | block_link *bl = block_links[tcache_id]; |
352 | int cnt = block_link_counts[tcache_id]; |
353 | |
354 | if (cnt >= block_max_counts[tcache_id] * 2) { |
355 | printf("bl overflow for tcache %d\n", tcache_id); |
356 | return -1; |
357 | } |
358 | |
359 | bl[cnt].target_pc = target_pc; |
360 | bl[cnt].jump = jump; |
361 | block_link_counts[tcache_id]++; |
362 | |
363 | return 0; |
364 | } |
5686d931 |
365 | #endif |
44e6452e |
366 | |
a2b8c5a5 |
367 | static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id) |
679af8a3 |
368 | { |
369 | block_desc *bd; |
a2b8c5a5 |
370 | int tcache_id; |
371 | int *bcount; |
372 | |
373 | bd = dr_get_bd(addr, is_slave, &tcache_id); |
374 | if (bd != NULL) { |
375 | dbg(1, "block override for %08x", addr); |
376 | bd->tcache_ptr = tcache_ptr; |
377 | *blk_id = bd - block_tables[tcache_id]; |
378 | return bd; |
379 | } |
679af8a3 |
380 | |
a2b8c5a5 |
381 | bcount = &block_counts[tcache_id]; |
44e6452e |
382 | if (*bcount >= block_max_counts[tcache_id]) { |
383 | printf("bd overflow for tcache %d\n", tcache_id); |
f4bb5d6b |
384 | return NULL; |
44e6452e |
385 | } |
a2b8c5a5 |
386 | if (*bcount == 0) |
387 | (*bcount)++; // not using descriptor 0 |
679af8a3 |
388 | |
f4bb5d6b |
389 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
390 | bd->addr = addr; |
391 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
392 | *blk_id = *bcount; |
393 | (*bcount)++; |
679af8a3 |
394 | |
18b94127 |
395 | if ((addr & 0xc6000000) == 0x02000000) { // ROM |
396 | bd->next = HASH_FUNC(hash_table, addr); |
397 | HASH_FUNC(hash_table, addr) = bd; |
398 | #if (DRC_DEBUG & 1) |
399 | if (bd->next != NULL) { |
400 | printf(" hash collision with %08x\n", bd->next->addr); |
401 | hash_collisions++; |
402 | } |
403 | #endif |
404 | } |
405 | |
679af8a3 |
406 | return bd; |
407 | } |
408 | |
a2b8c5a5 |
409 | static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id) |
410 | { |
411 | block_desc *bd = NULL; |
412 | void *block = NULL; |
413 | |
414 | bd = dr_get_bd(pc, is_slave, tcache_id); |
415 | if (bd != NULL) |
416 | block = bd->tcache_ptr; |
417 | |
418 | #if (DRC_DEBUG & 1) |
419 | if (bd != NULL) |
420 | bd->refcount++; |
421 | #endif |
422 | return block; |
423 | } |
424 | |
425 | static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id) |
426 | { |
427 | #if LINK_BRANCHES |
428 | int target_tcache_id; |
429 | void *target; |
430 | int ret; |
431 | |
432 | target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id); |
433 | if (target_tcache_id == tcache_id) { |
434 | // allow linking blocks only from local cache |
435 | ret = dr_add_block_link(pc, tcache_ptr, tcache_id); |
436 | if (ret < 0) |
437 | return NULL; |
438 | } |
439 | if (target == NULL || target_tcache_id != tcache_id) |
440 | target = sh2_drc_dispatcher; |
441 | |
442 | return target; |
443 | #else |
444 | return sh2_drc_dispatcher; |
445 | #endif |
446 | } |
447 | |
448 | static void dr_link_blocks(void *target, u32 pc, int tcache_id) |
449 | { |
450 | #if LINK_BRANCHES |
451 | block_link *bl = block_links[tcache_id]; |
452 | int cnt = block_link_counts[tcache_id]; |
453 | int i; |
454 | |
455 | for (i = 0; i < cnt; i++) { |
456 | if (bl[i].target_pc == pc) { |
457 | dbg(1, "- link from %p", bl[i].jump); |
458 | emith_jump_patch(bl[i].jump, target); |
459 | // XXX: sync ARM caches (old jump should be fine)? |
460 | } |
461 | } |
462 | #endif |
463 | } |
464 | |
44e6452e |
465 | #define ADD_TO_ARRAY(array, count, item, failcode) \ |
466 | array[count++] = item; \ |
467 | if (count >= ARRAY_SIZE(array)) { \ |
468 | printf("warning: " #array " overflow\n"); \ |
469 | failcode; \ |
470 | } |
471 | |
a2b8c5a5 |
472 | static int find_in_array(u32 *array, size_t size, u32 what) |
18b94127 |
473 | { |
474 | size_t i; |
475 | for (i = 0; i < size; i++) |
476 | if (what == array[i]) |
477 | return i; |
478 | |
479 | return -1; |
480 | } |
679af8a3 |
481 | |
482 | // --------------------------------------------------------------- |
483 | |
a2b8c5a5 |
484 | // register cache / constant propagation stuff |
23686515 |
485 | typedef enum { |
486 | RC_GR_READ, |
487 | RC_GR_WRITE, |
488 | RC_GR_RMW, |
489 | } rc_gr_mode; |
490 | |
491 | static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking); |
492 | |
493 | // guest regs with constants |
494 | static u32 dr_gcregs[24]; |
495 | // a mask of constant/dirty regs |
496 | static u32 dr_gcregs_mask; |
497 | static u32 dr_gcregs_dirty; |
498 | |
a2b8c5a5 |
499 | #if PROPAGATE_CONSTANTS |
23686515 |
500 | static void gconst_new(sh2_reg_e r, u32 val) |
501 | { |
23686515 |
502 | int i; |
503 | |
504 | dr_gcregs_mask |= 1 << r; |
505 | dr_gcregs_dirty |= 1 << r; |
506 | dr_gcregs[r] = val; |
507 | |
508 | // throw away old r that we might have cached |
509 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
510 | if ((reg_temp[i].type == HR_CACHED) && |
511 | reg_temp[i].greg == r) { |
512 | reg_temp[i].type = HR_FREE; |
513 | reg_temp[i].flags = 0; |
514 | } |
515 | } |
23686515 |
516 | } |
a2b8c5a5 |
517 | #endif |
23686515 |
518 | |
519 | static int gconst_get(sh2_reg_e r, u32 *val) |
520 | { |
521 | if (dr_gcregs_mask & (1 << r)) { |
522 | *val = dr_gcregs[r]; |
523 | return 1; |
524 | } |
525 | return 0; |
526 | } |
527 | |
528 | static int gconst_check(sh2_reg_e r) |
529 | { |
530 | if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r)) |
531 | return 1; |
532 | return 0; |
533 | } |
534 | |
535 | // update hr if dirty, else do nothing |
536 | static int gconst_try_read(int hr, sh2_reg_e r) |
537 | { |
538 | if (dr_gcregs_dirty & (1 << r)) { |
539 | emith_move_r_imm(hr, dr_gcregs[r]); |
540 | dr_gcregs_dirty &= ~(1 << r); |
541 | return 1; |
542 | } |
543 | return 0; |
544 | } |
545 | |
546 | static void gconst_check_evict(sh2_reg_e r) |
547 | { |
548 | if (dr_gcregs_mask & (1 << r)) |
549 | // no longer cached in reg, make dirty again |
550 | dr_gcregs_dirty |= 1 << r; |
551 | } |
552 | |
553 | static void gconst_kill(sh2_reg_e r) |
554 | { |
555 | dr_gcregs_mask &= ~(1 << r); |
556 | dr_gcregs_dirty &= ~(1 << r); |
557 | } |
558 | |
559 | static void gconst_clean(void) |
560 | { |
561 | int i; |
562 | |
563 | for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++) |
564 | if (dr_gcregs_dirty & (1 << i)) { |
565 | // using RC_GR_READ here: it will call gconst_try_read, |
566 | // cache the reg and mark it dirty. |
567 | rcache_get_reg_(i, RC_GR_READ, 0); |
568 | } |
569 | } |
570 | |
571 | static void gconst_invalidate(void) |
572 | { |
573 | dr_gcregs_mask = dr_gcregs_dirty = 0; |
574 | } |
575 | |
c18edb34 |
576 | static u16 rcache_counter; |
577 | |
578 | static temp_reg_t *rcache_evict(void) |
41397701 |
579 | { |
c18edb34 |
580 | // evict reg with oldest stamp |
581 | int i, oldest = -1; |
582 | u16 min_stamp = (u16)-1; |
583 | |
584 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
23686515 |
585 | if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) && |
586 | reg_temp[i].stamp <= min_stamp) { |
587 | min_stamp = reg_temp[i].stamp; |
588 | oldest = i; |
589 | } |
c18edb34 |
590 | } |
591 | |
592 | if (oldest == -1) { |
80599a42 |
593 | printf("no registers to evict, aborting\n"); |
c18edb34 |
594 | exit(1); |
595 | } |
596 | |
597 | i = oldest; |
23686515 |
598 | if (reg_temp[i].type == HR_CACHED) { |
599 | if (reg_temp[i].flags & HRF_DIRTY) |
600 | // writeback |
601 | emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4); |
602 | gconst_check_evict(reg_temp[i].greg); |
c18edb34 |
603 | } |
604 | |
23686515 |
605 | reg_temp[i].type = HR_FREE; |
606 | reg_temp[i].flags = 0; |
c18edb34 |
607 | return ®_temp[i]; |
679af8a3 |
608 | } |
609 | |
23686515 |
610 | static int get_reg_static(sh2_reg_e r, rc_gr_mode mode) |
611 | { |
612 | int i = reg_map_g2h[r]; |
613 | if (i != -1) { |
614 | if (mode != RC_GR_WRITE) |
615 | gconst_try_read(i, r); |
616 | } |
617 | return i; |
618 | } |
c18edb34 |
619 | |
80599a42 |
620 | // note: must not be called when doing conditional code |
23686515 |
621 | static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking) |
679af8a3 |
622 | { |
c18edb34 |
623 | temp_reg_t *tr; |
23686515 |
624 | int i, ret; |
c18edb34 |
625 | |
23686515 |
626 | // maybe statically mapped? |
627 | ret = get_reg_static(r, mode); |
628 | if (ret != -1) |
629 | goto end; |
679af8a3 |
630 | |
c18edb34 |
631 | rcache_counter++; |
632 | |
633 | // maybe already cached? |
23686515 |
634 | // if so, prefer against gconst (they must be in sync) |
c18edb34 |
635 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
23686515 |
636 | if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) { |
c18edb34 |
637 | reg_temp[i].stamp = rcache_counter; |
638 | if (mode != RC_GR_READ) |
23686515 |
639 | reg_temp[i].flags |= HRF_DIRTY; |
640 | ret = reg_temp[i].hreg; |
641 | goto end; |
c18edb34 |
642 | } |
679af8a3 |
643 | } |
644 | |
c18edb34 |
645 | // use any free reg |
646 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
23686515 |
647 | if (reg_temp[i].type == HR_FREE) { |
c18edb34 |
648 | tr = ®_temp[i]; |
649 | goto do_alloc; |
650 | } |
651 | } |
652 | |
653 | tr = rcache_evict(); |
654 | |
655 | do_alloc: |
23686515 |
656 | tr->type = HR_CACHED; |
657 | if (do_locking) |
658 | tr->flags |= HRF_LOCKED; |
659 | if (mode != RC_GR_READ) |
660 | tr->flags |= HRF_DIRTY; |
661 | tr->greg = r; |
c18edb34 |
662 | tr->stamp = rcache_counter; |
23686515 |
663 | ret = tr->hreg; |
664 | |
665 | if (mode != RC_GR_WRITE) { |
666 | if (gconst_check(r)) { |
667 | if (gconst_try_read(ret, r)) |
668 | tr->flags |= HRF_DIRTY; |
669 | } |
670 | else |
671 | emith_ctx_read(tr->hreg, r * 4); |
672 | } |
673 | |
674 | end: |
675 | if (mode != RC_GR_READ) |
676 | gconst_kill(r); |
677 | |
678 | return ret; |
679 | } |
680 | |
681 | static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode) |
682 | { |
683 | return rcache_get_reg_(r, mode, 1); |
679af8a3 |
684 | } |
685 | |
c18edb34 |
686 | static int rcache_get_tmp(void) |
679af8a3 |
687 | { |
c18edb34 |
688 | temp_reg_t *tr; |
689 | int i; |
690 | |
691 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
23686515 |
692 | if (reg_temp[i].type == HR_FREE) { |
c18edb34 |
693 | tr = ®_temp[i]; |
694 | goto do_alloc; |
695 | } |
696 | |
697 | tr = rcache_evict(); |
698 | |
699 | do_alloc: |
700 | tr->type = HR_TEMP; |
23686515 |
701 | return tr->hreg; |
c18edb34 |
702 | } |
703 | |
80599a42 |
704 | static int rcache_get_arg_id(int arg) |
705 | { |
706 | int i, r = 0; |
707 | host_arg2reg(r, arg); |
708 | |
709 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
23686515 |
710 | if (reg_temp[i].hreg == r) |
80599a42 |
711 | break; |
712 | |
713 | if (i == ARRAY_SIZE(reg_temp)) |
714 | // let's just say it's untracked arg reg |
715 | return r; |
716 | |
23686515 |
717 | if (reg_temp[i].type == HR_CACHED) { |
80599a42 |
718 | // writeback |
23686515 |
719 | if (reg_temp[i].flags & HRF_DIRTY) |
720 | emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4); |
721 | gconst_check_evict(reg_temp[i].greg); |
80599a42 |
722 | } |
723 | else if (reg_temp[i].type == HR_TEMP) { |
724 | printf("arg %d reg %d already used, aborting\n", arg, r); |
725 | exit(1); |
726 | } |
727 | |
23686515 |
728 | reg_temp[i].type = HR_FREE; |
729 | reg_temp[i].flags = 0; |
730 | |
80599a42 |
731 | return i; |
732 | } |
733 | |
734 | // get a reg to be used as function arg |
80599a42 |
735 | static int rcache_get_tmp_arg(int arg) |
736 | { |
737 | int id = rcache_get_arg_id(arg); |
738 | reg_temp[id].type = HR_TEMP; |
739 | |
23686515 |
740 | return reg_temp[id].hreg; |
80599a42 |
741 | } |
742 | |
23686515 |
743 | // same but caches a reg. RC_GR_READ only. |
80599a42 |
744 | static int rcache_get_reg_arg(int arg, sh2_reg_e r) |
745 | { |
746 | int i, srcr, dstr, dstid; |
23686515 |
747 | int dirty = 0; |
80599a42 |
748 | |
749 | dstid = rcache_get_arg_id(arg); |
23686515 |
750 | dstr = reg_temp[dstid].hreg; |
80599a42 |
751 | |
752 | // maybe already statically mapped? |
23686515 |
753 | srcr = get_reg_static(r, RC_GR_READ); |
80599a42 |
754 | if (srcr != -1) |
755 | goto do_cache; |
756 | |
757 | // maybe already cached? |
758 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
23686515 |
759 | if ((reg_temp[i].type == HR_CACHED) && |
760 | reg_temp[i].greg == r) |
80599a42 |
761 | { |
23686515 |
762 | srcr = reg_temp[i].hreg; |
80599a42 |
763 | goto do_cache; |
764 | } |
765 | } |
766 | |
767 | // must read |
768 | srcr = dstr; |
23686515 |
769 | if (gconst_check(r)) { |
770 | if (gconst_try_read(srcr, r)) |
771 | dirty = 1; |
772 | } |
773 | else |
774 | emith_ctx_read(srcr, r * 4); |
80599a42 |
775 | |
776 | do_cache: |
23686515 |
777 | if (dstr != srcr) |
80599a42 |
778 | emith_move_r_r(dstr, srcr); |
779 | |
780 | reg_temp[dstid].stamp = ++rcache_counter; |
781 | reg_temp[dstid].type = HR_CACHED; |
23686515 |
782 | reg_temp[dstid].greg = r; |
783 | reg_temp[dstid].flags |= HRF_LOCKED; |
784 | if (dirty) |
785 | reg_temp[dstid].flags |= HRF_DIRTY; |
80599a42 |
786 | return dstr; |
787 | } |
788 | |
c18edb34 |
789 | static void rcache_free_tmp(int hr) |
790 | { |
791 | int i; |
792 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
23686515 |
793 | if (reg_temp[i].hreg == hr) |
c18edb34 |
794 | break; |
795 | |
80599a42 |
796 | if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) { |
c18edb34 |
797 | printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type); |
80599a42 |
798 | return; |
799 | } |
800 | |
801 | reg_temp[i].type = HR_FREE; |
23686515 |
802 | reg_temp[i].flags = 0; |
803 | } |
804 | |
805 | static void rcache_unlock(int hr) |
806 | { |
807 | int i; |
808 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
809 | if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr) |
810 | reg_temp[i].flags &= ~HRF_LOCKED; |
811 | } |
812 | |
813 | static void rcache_unlock_all(void) |
814 | { |
815 | int i; |
816 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
817 | reg_temp[i].flags &= ~HRF_LOCKED; |
c18edb34 |
818 | } |
819 | |
80599a42 |
820 | static void rcache_clean(void) |
c18edb34 |
821 | { |
822 | int i; |
23686515 |
823 | gconst_clean(); |
824 | |
80599a42 |
825 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
23686515 |
826 | if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) { |
c18edb34 |
827 | // writeback |
23686515 |
828 | emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4); |
829 | reg_temp[i].flags &= ~HRF_DIRTY; |
c18edb34 |
830 | } |
80599a42 |
831 | } |
832 | |
833 | static void rcache_invalidate(void) |
834 | { |
835 | int i; |
23686515 |
836 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
c18edb34 |
837 | reg_temp[i].type = HR_FREE; |
23686515 |
838 | reg_temp[i].flags = 0; |
839 | } |
c18edb34 |
840 | rcache_counter = 0; |
23686515 |
841 | |
842 | gconst_invalidate(); |
c18edb34 |
843 | } |
844 | |
80599a42 |
845 | static void rcache_flush(void) |
846 | { |
847 | rcache_clean(); |
848 | rcache_invalidate(); |
849 | } |
850 | |
c18edb34 |
851 | // --------------------------------------------------------------- |
852 | |
23686515 |
853 | static int emit_get_rbase_and_offs(u32 a, u32 *offs) |
854 | { |
23686515 |
855 | u32 mask = 0; |
a2b8c5a5 |
856 | int poffs; |
23686515 |
857 | int hr; |
858 | |
a2b8c5a5 |
859 | poffs = dr_ctx_get_mem_ptr(a, &mask); |
23686515 |
860 | if (poffs == -1) |
861 | return -1; |
862 | |
a2b8c5a5 |
863 | // XXX: could use some related reg |
23686515 |
864 | hr = rcache_get_tmp(); |
865 | emith_ctx_read(hr, poffs); |
866 | emith_add_r_imm(hr, a & mask & ~0xff); |
867 | *offs = a & 0xff; // XXX: ARM oriented.. |
868 | return hr; |
869 | } |
870 | |
c18edb34 |
871 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
872 | { |
23686515 |
873 | #if PROPAGATE_CONSTANTS |
874 | gconst_new(dst, imm); |
875 | #else |
c18edb34 |
876 | int hr = rcache_get_reg(dst, RC_GR_WRITE); |
877 | emith_move_r_imm(hr, imm); |
23686515 |
878 | #endif |
c18edb34 |
879 | } |
880 | |
881 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
882 | { |
883 | int hr_d = rcache_get_reg(dst, RC_GR_WRITE); |
884 | int hr_s = rcache_get_reg(src, RC_GR_READ); |
885 | |
886 | emith_move_r_r(hr_d, hr_s); |
679af8a3 |
887 | } |
888 | |
52d759c3 |
889 | // T must be clear, and comparison done just before this |
890 | static void emit_or_t_if_eq(int srr) |
891 | { |
892 | EMITH_SJMP_START(DCOND_NE); |
893 | emith_or_r_imm_c(DCOND_EQ, srr, T); |
894 | EMITH_SJMP_END(DCOND_NE); |
895 | } |
896 | |
80599a42 |
897 | // arguments must be ready |
898 | // reg cache must be clean before call |
23686515 |
899 | static int emit_memhandler_read_(int size, int ram_check) |
679af8a3 |
900 | { |
b081408f |
901 | int arg0, arg1; |
902 | host_arg2reg(arg0, 0); |
903 | |
23686515 |
904 | rcache_clean(); |
905 | |
b081408f |
906 | // must writeback cycles for poll detection stuff |
23686515 |
907 | // FIXME: rm |
b081408f |
908 | if (reg_map_g2h[SHR_SR] != -1) |
909 | emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4); |
23686515 |
910 | |
b081408f |
911 | arg1 = rcache_get_tmp_arg(1); |
912 | emith_move_r_r(arg1, CONTEXT_REG); |
913 | |
5686d931 |
914 | #ifndef PDB_NET |
23686515 |
915 | if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) { |
b081408f |
916 | int tmp = rcache_get_tmp(); |
917 | emith_and_r_r_imm(tmp, arg0, 0xfb000000); |
918 | emith_cmp_r_imm(tmp, 0x02000000); |
919 | switch (size) { |
920 | case 0: // 8 |
921 | EMITH_SJMP3_START(DCOND_NE); |
922 | emith_eor_r_imm_c(DCOND_EQ, arg0, 1); |
923 | emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
924 | EMITH_SJMP3_MID(DCOND_NE); |
5686d931 |
925 | emith_call_cond(DCOND_NE, sh2_drc_read8); |
b081408f |
926 | EMITH_SJMP3_END(); |
927 | break; |
928 | case 1: // 16 |
929 | EMITH_SJMP3_START(DCOND_NE); |
930 | emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
931 | EMITH_SJMP3_MID(DCOND_NE); |
5686d931 |
932 | emith_call_cond(DCOND_NE, sh2_drc_read16); |
b081408f |
933 | EMITH_SJMP3_END(); |
934 | break; |
935 | case 2: // 32 |
936 | EMITH_SJMP3_START(DCOND_NE); |
937 | emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0); |
938 | emith_ror_c(DCOND_EQ, arg0, arg0, 16); |
939 | EMITH_SJMP3_MID(DCOND_NE); |
5686d931 |
940 | emith_call_cond(DCOND_NE, sh2_drc_read32); |
b081408f |
941 | EMITH_SJMP3_END(); |
942 | break; |
943 | } |
944 | } |
945 | else |
946 | #endif |
947 | { |
948 | switch (size) { |
949 | case 0: // 8 |
5686d931 |
950 | emith_call(sh2_drc_read8); |
b081408f |
951 | break; |
952 | case 1: // 16 |
5686d931 |
953 | emith_call(sh2_drc_read16); |
b081408f |
954 | break; |
955 | case 2: // 32 |
5686d931 |
956 | emith_call(sh2_drc_read32); |
b081408f |
957 | break; |
958 | } |
679af8a3 |
959 | } |
80599a42 |
960 | rcache_invalidate(); |
961 | // assuming arg0 and retval reg matches |
962 | return rcache_get_tmp_arg(0); |
963 | } |
679af8a3 |
964 | |
23686515 |
965 | static int emit_memhandler_read(int size) |
966 | { |
967 | return emit_memhandler_read_(size, 1); |
968 | } |
969 | |
970 | static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size) |
971 | { |
972 | int hr, hr2, ram_check = 1; |
973 | u32 val, offs2; |
974 | |
975 | if (gconst_get(rs, &val)) { |
976 | hr = emit_get_rbase_and_offs(val + offs, &offs2); |
977 | if (hr != -1) { |
978 | hr2 = rcache_get_reg(rd, RC_GR_WRITE); |
979 | switch (size) { |
980 | case 0: // 8 |
981 | emith_read8_r_r_offs(hr2, hr, offs2 ^ 1); |
982 | emith_sext(hr2, hr2, 8); |
983 | break; |
984 | case 1: // 16 |
985 | emith_read16_r_r_offs(hr2, hr, offs2); |
986 | emith_sext(hr2, hr2, 16); |
987 | break; |
988 | case 2: // 32 |
989 | emith_read_r_r_offs(hr2, hr, offs2); |
990 | emith_ror(hr2, hr2, 16); |
991 | break; |
992 | } |
993 | rcache_free_tmp(hr); |
994 | return hr2; |
995 | } |
996 | |
997 | ram_check = 0; |
998 | } |
999 | |
1000 | hr = rcache_get_reg_arg(0, rs); |
1001 | if (offs != 0) |
1002 | emith_add_r_imm(hr, offs); |
1003 | hr = emit_memhandler_read_(size, ram_check); |
1004 | hr2 = rcache_get_reg(rd, RC_GR_WRITE); |
1005 | if (size != 2) { |
1006 | emith_sext(hr2, hr, (size == 1) ? 16 : 8); |
1007 | } else |
1008 | emith_move_r_r(hr2, hr); |
1009 | rcache_free_tmp(hr); |
1010 | |
1011 | return hr2; |
1012 | } |
1013 | |
e05b81fc |
1014 | static void emit_memhandler_write(int size, u32 pc, int delay) |
80599a42 |
1015 | { |
1016 | int ctxr; |
1017 | host_arg2reg(ctxr, 2); |
80599a42 |
1018 | switch (size) { |
1019 | case 0: // 8 |
e05b81fc |
1020 | // XXX: consider inlining sh2_drc_write8 |
1021 | if (delay) { |
1022 | emith_call(sh2_drc_write8_slot); |
1023 | } else { |
1024 | emit_move_r_imm32(SHR_PC, pc); |
1025 | rcache_clean(); |
1026 | emith_call(sh2_drc_write8); |
1027 | } |
80599a42 |
1028 | break; |
1029 | case 1: // 16 |
e05b81fc |
1030 | if (delay) { |
1031 | emith_call(sh2_drc_write16_slot); |
1032 | } else { |
1033 | emit_move_r_imm32(SHR_PC, pc); |
1034 | rcache_clean(); |
1035 | emith_call(sh2_drc_write16); |
1036 | } |
80599a42 |
1037 | break; |
1038 | case 2: // 32 |
e05b81fc |
1039 | emith_move_r_r(ctxr, CONTEXT_REG); |
5686d931 |
1040 | emith_call(sh2_drc_write32); |
80599a42 |
1041 | break; |
1042 | } |
1043 | rcache_invalidate(); |
679af8a3 |
1044 | } |
80599a42 |
1045 | |
52d759c3 |
1046 | // @(Rx,Ry) |
1047 | static int emit_indirect_indexed_read(int rx, int ry, int size) |
1048 | { |
1049 | int a0, t; |
52d759c3 |
1050 | a0 = rcache_get_reg_arg(0, rx); |
1051 | t = rcache_get_reg(ry, RC_GR_READ); |
1052 | emith_add_r_r(a0, t); |
1053 | return emit_memhandler_read(size); |
1054 | } |
1055 | |
f0d7b1fa |
1056 | // read @Rn, @rm |
1057 | static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size) |
1058 | { |
1059 | int tmp; |
1060 | |
f0d7b1fa |
1061 | rcache_get_reg_arg(0, rn); |
1062 | tmp = emit_memhandler_read(size); |
1063 | emith_ctx_write(tmp, offsetof(SH2, drc_tmp)); |
1064 | rcache_free_tmp(tmp); |
1065 | tmp = rcache_get_reg(rn, RC_GR_RMW); |
1066 | emith_add_r_imm(tmp, 1 << size); |
23686515 |
1067 | rcache_unlock(tmp); |
f0d7b1fa |
1068 | |
f0d7b1fa |
1069 | rcache_get_reg_arg(0, rm); |
1070 | *rmr = emit_memhandler_read(size); |
1071 | *rnr = rcache_get_tmp(); |
1072 | emith_ctx_read(*rnr, offsetof(SH2, drc_tmp)); |
1073 | tmp = rcache_get_reg(rm, RC_GR_RMW); |
1074 | emith_add_r_imm(tmp, 1 << size); |
23686515 |
1075 | rcache_unlock(tmp); |
f0d7b1fa |
1076 | } |
1077 | |
8796b7ee |
1078 | static void emit_do_static_regs(int is_write, int tmpr) |
f0d7b1fa |
1079 | { |
8796b7ee |
1080 | int i, r, count; |
1081 | |
1082 | for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) { |
1083 | r = reg_map_g2h[i]; |
1084 | if (r == -1) |
1085 | continue; |
1086 | |
1087 | for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) { |
1088 | if (reg_map_g2h[i + 1] != r + 1) |
1089 | break; |
1090 | count++; |
1091 | } |
1092 | |
1093 | if (count > 1) { |
1094 | // i, r point to last item |
1095 | if (is_write) |
1096 | emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr); |
1097 | else |
1098 | emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr); |
1099 | } else { |
1100 | if (is_write) |
1101 | emith_ctx_write(r, i * 4); |
1102 | else |
1103 | emith_ctx_read(r, i * 4); |
1104 | } |
f0d7b1fa |
1105 | } |
1106 | } |
1107 | |
e05b81fc |
1108 | static void emit_block_entry(void) |
f0d7b1fa |
1109 | { |
e05b81fc |
1110 | int arg0, arg1, arg2; |
8796b7ee |
1111 | |
e05b81fc |
1112 | host_arg2reg(arg0, 0); |
1113 | host_arg2reg(arg1, 1); |
1114 | host_arg2reg(arg2, 2); |
8796b7ee |
1115 | |
5686d931 |
1116 | #if (DRC_DEBUG & 4) || defined(PDB) |
1117 | emit_do_static_regs(1, arg2); |
e05b81fc |
1118 | emith_move_r_r(arg1, CONTEXT_REG); |
1119 | emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ)); |
5686d931 |
1120 | emith_call(sh2_drc_log_entry); |
e05b81fc |
1121 | rcache_invalidate(); |
1122 | #endif |
1123 | emith_tst_r_r(arg0, arg0); |
1124 | EMITH_SJMP_START(DCOND_EQ); |
1125 | emith_jump_reg_c(DCOND_NE, arg0); |
1126 | EMITH_SJMP_END(DCOND_EQ); |
1127 | } |
8796b7ee |
1128 | |
e898de13 |
1129 | #define DELAYED_OP \ |
18b94127 |
1130 | drcf.delayed_op = 2 |
1131 | |
1132 | #define DELAY_SAVE_T(sr) { \ |
1133 | emith_bic_r_imm(sr, T_save); \ |
1134 | emith_tst_r_imm(sr, T); \ |
1135 | EMITH_SJMP_START(DCOND_EQ); \ |
1136 | emith_or_r_imm_c(DCOND_NE, sr, T_save); \ |
1137 | EMITH_SJMP_END(DCOND_EQ); \ |
1138 | drcf.use_saved_t = 1; \ |
1139 | } |
e898de13 |
1140 | |
e05b81fc |
1141 | #define FLUSH_CYCLES(sr) \ |
1142 | if (cycles > 0) { \ |
1143 | emith_sub_r_imm(sr, cycles << 12); \ |
1144 | cycles = 0; \ |
1145 | } |
1146 | |
e898de13 |
1147 | #define CHECK_UNHANDLED_BITS(mask) { \ |
1148 | if ((op & (mask)) != 0) \ |
1149 | goto default_; \ |
1150 | } |
1151 | |
23686515 |
1152 | #define FETCH_OP(pc) \ |
1153 | dr_pc_base[(pc) / 2] |
1154 | |
1155 | #define FETCH32(a) \ |
1156 | ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1]) |
1157 | |
80599a42 |
1158 | #define GET_Fx() \ |
1159 | ((op >> 4) & 0x0f) |
1160 | |
1161 | #define GET_Rm GET_Fx |
1162 | |
1163 | #define GET_Rn() \ |
1164 | ((op >> 8) & 0x0f) |
1165 | |
ed8cf79b |
1166 | #define CHECK_FX_LT(n) \ |
52d759c3 |
1167 | if (GET_Fx() >= n) \ |
80599a42 |
1168 | goto default_ |
1169 | |
44e6452e |
1170 | #define MAX_LOCAL_BRANCHES 32 |
18b94127 |
1171 | |
1172 | // op_flags: data from 1st pass |
1173 | #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2] |
1174 | #define OF_DELAY_OP (1 << 0) |
1175 | |
e05b81fc |
1176 | static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) |
679af8a3 |
1177 | { |
18b94127 |
1178 | // XXX: maybe use structs instead? |
18b94127 |
1179 | u32 branch_target_pc[MAX_LOCAL_BRANCHES]; |
a2b8c5a5 |
1180 | void *branch_target_ptr[MAX_LOCAL_BRANCHES]; |
1181 | int branch_target_blkid[MAX_LOCAL_BRANCHES]; |
18b94127 |
1182 | int branch_target_count = 0; |
1183 | void *branch_patch_ptr[MAX_LOCAL_BRANCHES]; |
1184 | u32 branch_patch_pc[MAX_LOCAL_BRANCHES]; |
1185 | int branch_patch_count = 0; |
44e6452e |
1186 | int pending_branch_cond = -1; |
1187 | int pending_branch_pc = 0; |
18b94127 |
1188 | u8 op_flags[BLOCK_CYCLE_LIMIT + 1]; |
1189 | struct { |
1190 | u32 delayed_op:2; |
1191 | u32 test_irq:1; |
1192 | u32 use_saved_t:1; // delayed op modifies T |
1193 | } drcf = { 0, }; |
1194 | |
44e6452e |
1195 | // PC of current, first, last, last_target_blk SH2 insn |
1196 | u32 pc, base_pc, end_pc, out_pc; |
23686515 |
1197 | u32 last_inlined_literal = 0; |
f4bb5d6b |
1198 | void *block_entry; |
679af8a3 |
1199 | block_desc *this_block; |
23686515 |
1200 | u16 *dr_pc_base; |
18b94127 |
1201 | int blkid_main = 0; |
23686515 |
1202 | int skip_op = 0; |
18b94127 |
1203 | u32 tmp, tmp2; |
1204 | int cycles; |
1205 | int op; |
1206 | int i; |
1207 | |
1208 | base_pc = sh2->pc; |
679af8a3 |
1209 | |
23686515 |
1210 | // get base/validate PC |
1211 | dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave); |
1212 | if (dr_pc_base == (void *)-1) { |
18b94127 |
1213 | printf("invalid PC, aborting: %08x\n", base_pc); |
f4bb5d6b |
1214 | // FIXME: be less destructive |
1215 | exit(1); |
1216 | } |
1217 | |
f4bb5d6b |
1218 | tcache_ptr = tcache_ptrs[tcache_id]; |
a2b8c5a5 |
1219 | this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main); |
44e6452e |
1220 | if (this_block == NULL) |
1221 | return NULL; |
f4bb5d6b |
1222 | |
18b94127 |
1223 | // predict tcache overflow |
f4bb5d6b |
1224 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
44e6452e |
1225 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) { |
1226 | printf("tcache %d overflow\n", tcache_id); |
18b94127 |
1227 | return NULL; |
44e6452e |
1228 | } |
18b94127 |
1229 | |
1230 | block_entry = tcache_ptr; |
1231 | dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', |
1232 | tcache_id, blkid_main, base_pc, block_entry); |
1233 | |
44e6452e |
1234 | dr_link_blocks(tcache_ptr, base_pc, tcache_id); |
1235 | |
18b94127 |
1236 | // 1st pass: scan forward for local branches |
1237 | memset(op_flags, 0, sizeof(op_flags)); |
1238 | for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) { |
23686515 |
1239 | op = FETCH_OP(pc); |
18b94127 |
1240 | if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR |
44e6452e |
1241 | signed int offs = ((signed int)(op << 20) >> 19); |
18b94127 |
1242 | pc += 2; |
1243 | OP_FLAGS(pc) |= OF_DELAY_OP; |
44e6452e |
1244 | ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,); |
18b94127 |
1245 | break; |
1246 | } |
1247 | if ((op & 0xf000) == 0) { |
1248 | op &= 0xff; |
44e6452e |
1249 | if (op == 0x1b) // SLEEP |
1250 | break; |
1251 | if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE |
18b94127 |
1252 | pc += 2; |
1253 | OP_FLAGS(pc) |= OF_DELAY_OP; |
1254 | break; |
1255 | } |
1256 | continue; |
1257 | } |
1258 | if ((op & 0xf0df) == 0x400b) { // JMP, JSR |
1259 | pc += 2; |
1260 | OP_FLAGS(pc) |= OF_DELAY_OP; |
1261 | break; |
1262 | } |
1263 | if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) |
1264 | signed int offs = ((signed int)(op << 24) >> 23); |
1265 | if (op & 0x0400) |
1266 | OP_FLAGS(pc + 2) |= OF_DELAY_OP; |
44e6452e |
1267 | ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break); |
18b94127 |
1268 | } |
44e6452e |
1269 | if ((op & 0xff00) == 0xc300) // TRAPA |
1270 | break; |
f4bb5d6b |
1271 | } |
e898de13 |
1272 | |
18b94127 |
1273 | end_pc = pc; |
679af8a3 |
1274 | |
18b94127 |
1275 | // clean branch_targets that are not really local, |
1276 | // and that land on delay slots |
1277 | for (i = 0, tmp = 0; i < branch_target_count; i++) { |
1278 | pc = branch_target_pc[i]; |
1279 | if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP)) |
1280 | branch_target_pc[tmp++] = branch_target_pc[i]; |
e898de13 |
1281 | } |
18b94127 |
1282 | branch_target_count = tmp; |
1283 | memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); |
a2b8c5a5 |
1284 | memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count); |
679af8a3 |
1285 | |
18b94127 |
1286 | // ------------------------------------------------- |
1287 | // 2nd pass: actual compilation |
44e6452e |
1288 | out_pc = 0; |
18b94127 |
1289 | pc = base_pc; |
1290 | for (cycles = 0; pc <= end_pc || drcf.delayed_op; ) |
679af8a3 |
1291 | { |
18b94127 |
1292 | u32 tmp3, tmp4, sr; |
1293 | |
1294 | if (drcf.delayed_op > 0) |
1295 | drcf.delayed_op--; |
1296 | |
23686515 |
1297 | op = FETCH_OP(pc); |
1298 | |
18b94127 |
1299 | i = find_in_array(branch_target_pc, branch_target_count, pc); |
1300 | if (i >= 0) |
1301 | { |
a2b8c5a5 |
1302 | if (pc != base_pc) |
18b94127 |
1303 | { |
1304 | /* make "subblock" - just a mid-block entry */ |
1305 | block_desc *subblock; |
18b94127 |
1306 | |
1307 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
e05b81fc |
1308 | FLUSH_CYCLES(sr); |
23686515 |
1309 | // decide if to flush rcache |
1310 | if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2 |
1311 | rcache_clean(); |
1312 | else |
1313 | rcache_flush(); |
18b94127 |
1314 | do_host_disasm(tcache_id); |
1315 | |
a2b8c5a5 |
1316 | subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]); |
18b94127 |
1317 | if (subblock == NULL) |
1318 | return NULL; |
18b94127 |
1319 | |
44e6452e |
1320 | dbg(1, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', |
a2b8c5a5 |
1321 | tcache_id, branch_target_blkid[i], pc, tcache_ptr); |
44e6452e |
1322 | |
1323 | // since we made a block entry, link any other blocks that jump to current pc |
1324 | dr_link_blocks(tcache_ptr, pc, tcache_id); |
18b94127 |
1325 | } |
1326 | branch_target_ptr[i] = tcache_ptr; |
1327 | |
1328 | // must update PC |
1329 | emit_move_r_imm32(SHR_PC, pc); |
1330 | rcache_clean(); |
1331 | |
1332 | // check cycles |
1333 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
1334 | emith_cmp_r_imm(sr, 0); |
1335 | emith_jump_cond(DCOND_LE, sh2_drc_exit); |
23686515 |
1336 | do_host_disasm(tcache_id); |
18b94127 |
1337 | } |
e898de13 |
1338 | |
e898de13 |
1339 | #if (DRC_DEBUG & 3) |
1340 | insns_compiled++; |
1341 | #if (DRC_DEBUG & 2) |
1342 | DasmSH2(sh2dasm_buff, pc, op); |
1343 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
1344 | #endif |
679af8a3 |
1345 | #endif |
679af8a3 |
1346 | |
1347 | pc += 2; |
1348 | cycles++; |
1349 | |
23686515 |
1350 | if (skip_op > 0) { |
1351 | skip_op--; |
1352 | continue; |
1353 | } |
1354 | |
679af8a3 |
1355 | switch ((op >> 12) & 0x0f) |
1356 | { |
3863edbd |
1357 | ///////////////////////////////////////////// |
679af8a3 |
1358 | case 0x00: |
80599a42 |
1359 | switch (op & 0x0f) |
1360 | { |
1361 | case 0x02: |
1362 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1363 | switch (GET_Fx()) |
1364 | { |
1365 | case 0: // STC SR,Rn 0000nnnn00000010 |
1366 | tmp2 = SHR_SR; |
1367 | break; |
1368 | case 1: // STC GBR,Rn 0000nnnn00010010 |
1369 | tmp2 = SHR_GBR; |
1370 | break; |
1371 | case 2: // STC VBR,Rn 0000nnnn00100010 |
1372 | tmp2 = SHR_VBR; |
1373 | break; |
1374 | default: |
1375 | goto default_; |
1376 | } |
ed8cf79b |
1377 | tmp3 = rcache_get_reg(tmp2, RC_GR_READ); |
1378 | emith_move_r_r(tmp, tmp3); |
1379 | if (tmp2 == SHR_SR) |
18b94127 |
1380 | emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0 |
80599a42 |
1381 | goto end_op; |
e898de13 |
1382 | case 0x03: |
1383 | CHECK_UNHANDLED_BITS(0xd0); |
1384 | // BRAF Rm 0000mmmm00100011 |
1385 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
1386 | DELAYED_OP; |
18b94127 |
1387 | tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
80599a42 |
1388 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
c18edb34 |
1389 | emith_move_r_r(tmp, tmp2); |
18b94127 |
1390 | if (op & 0x20) |
1391 | emith_add_r_imm(tmp, pc + 2); |
1392 | else { // BSRF |
1393 | tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE); |
1394 | emith_move_r_imm(tmp3, pc + 2); |
1395 | emith_add_r_r(tmp, tmp3); |
1396 | } |
44e6452e |
1397 | out_pc = (u32)-1; |
679af8a3 |
1398 | cycles++; |
e898de13 |
1399 | goto end_op; |
80599a42 |
1400 | case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 |
1401 | case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 |
1402 | case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 |
e05b81fc |
1403 | rcache_clean(); |
1404 | tmp = rcache_get_reg_arg(1, GET_Rm()); |
1405 | tmp2 = rcache_get_reg_arg(0, SHR_R0); |
1406 | tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1407 | emith_add_r_r(tmp2, tmp3); |
1408 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1409 | goto end_op; |
1410 | case 0x07: |
1411 | // MUL.L Rm,Rn 0000nnnnmmmm0111 |
1412 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1413 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1414 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1415 | emith_mul(tmp3, tmp2, tmp); |
1416 | cycles++; |
1417 | goto end_op; |
1418 | case 0x08: |
1419 | CHECK_UNHANDLED_BITS(0xf00); |
1420 | switch (GET_Fx()) |
1421 | { |
1422 | case 0: // CLRT 0000000000001000 |
8796b7ee |
1423 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1424 | if (drcf.delayed_op) |
1425 | DELAY_SAVE_T(sr); |
8796b7ee |
1426 | emith_bic_r_imm(sr, T); |
80599a42 |
1427 | break; |
1428 | case 1: // SETT 0000000000011000 |
8796b7ee |
1429 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1430 | if (drcf.delayed_op) |
1431 | DELAY_SAVE_T(sr); |
8796b7ee |
1432 | emith_or_r_imm(sr, T); |
80599a42 |
1433 | break; |
1434 | case 2: // CLRMAC 0000000000101000 |
23686515 |
1435 | emit_move_r_imm32(SHR_MACL, 0); |
1436 | emit_move_r_imm32(SHR_MACH, 0); |
80599a42 |
1437 | break; |
1438 | default: |
1439 | goto default_; |
1440 | } |
1441 | goto end_op; |
e898de13 |
1442 | case 0x09: |
80599a42 |
1443 | switch (GET_Fx()) |
1444 | { |
1445 | case 0: // NOP 0000000000001001 |
1446 | CHECK_UNHANDLED_BITS(0xf00); |
1447 | break; |
1448 | case 1: // DIV0U 0000000000011001 |
1449 | CHECK_UNHANDLED_BITS(0xf00); |
8796b7ee |
1450 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1451 | if (drcf.delayed_op) |
1452 | DELAY_SAVE_T(sr); |
8796b7ee |
1453 | emith_bic_r_imm(sr, M|Q|T); |
80599a42 |
1454 | break; |
1455 | case 2: // MOVT Rn 0000nnnn00101001 |
8796b7ee |
1456 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
80599a42 |
1457 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
8796b7ee |
1458 | emith_clear_msb(tmp2, sr, 31); |
80599a42 |
1459 | break; |
1460 | default: |
1461 | goto default_; |
1462 | } |
1463 | goto end_op; |
1464 | case 0x0a: |
1465 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1466 | switch (GET_Fx()) |
1467 | { |
1468 | case 0: // STS MACH,Rn 0000nnnn00001010 |
ed8cf79b |
1469 | tmp2 = SHR_MACH; |
80599a42 |
1470 | break; |
1471 | case 1: // STS MACL,Rn 0000nnnn00011010 |
ed8cf79b |
1472 | tmp2 = SHR_MACL; |
80599a42 |
1473 | break; |
1474 | case 2: // STS PR,Rn 0000nnnn00101010 |
ed8cf79b |
1475 | tmp2 = SHR_PR; |
80599a42 |
1476 | break; |
1477 | default: |
1478 | goto default_; |
1479 | } |
ed8cf79b |
1480 | tmp2 = rcache_get_reg(tmp2, RC_GR_READ); |
80599a42 |
1481 | emith_move_r_r(tmp, tmp2); |
e898de13 |
1482 | goto end_op; |
1483 | case 0x0b: |
80599a42 |
1484 | CHECK_UNHANDLED_BITS(0xf00); |
1485 | switch (GET_Fx()) |
1486 | { |
1487 | case 0: // RTS 0000000000001011 |
1488 | DELAYED_OP; |
18b94127 |
1489 | emit_move_r_r(SHR_PC, SHR_PR); |
44e6452e |
1490 | out_pc = (u32)-1; |
e898de13 |
1491 | cycles++; |
80599a42 |
1492 | break; |
1493 | case 1: // SLEEP 0000000000011011 |
80599a42 |
1494 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1495 | emith_clear_msb(tmp, tmp, 20); // clear cycles |
44e6452e |
1496 | out_pc = out_pc - 2; |
80599a42 |
1497 | cycles = 1; |
e05b81fc |
1498 | goto end_op; |
80599a42 |
1499 | case 2: // RTE 0000000000101011 |
52d759c3 |
1500 | DELAYED_OP; |
52d759c3 |
1501 | // pop PC |
23686515 |
1502 | emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2); |
52d759c3 |
1503 | // pop SR |
1504 | tmp = rcache_get_reg_arg(0, SHR_SP); |
1505 | emith_add_r_imm(tmp, 4); |
1506 | tmp = emit_memhandler_read(2); |
18b94127 |
1507 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1508 | emith_write_sr(sr, tmp); |
52d759c3 |
1509 | rcache_free_tmp(tmp); |
1510 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
1511 | emith_add_r_imm(tmp, 4*2); |
18b94127 |
1512 | drcf.test_irq = 1; |
44e6452e |
1513 | out_pc = (u32)-1; |
e898de13 |
1514 | cycles += 3; |
80599a42 |
1515 | break; |
1516 | default: |
1517 | goto default_; |
e898de13 |
1518 | } |
1519 | goto end_op; |
80599a42 |
1520 | case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 |
1521 | case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 |
1522 | case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 |
52d759c3 |
1523 | tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3); |
80599a42 |
1524 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
80599a42 |
1525 | if ((op & 3) != 2) { |
1526 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
1527 | } else |
1528 | emith_move_r_r(tmp2, tmp); |
52d759c3 |
1529 | rcache_free_tmp(tmp); |
80599a42 |
1530 | goto end_op; |
1531 | case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 |
f0d7b1fa |
1532 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2); |
f0d7b1fa |
1533 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
1534 | /* MS 16 MAC bits unused if saturated */ |
23686515 |
1535 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
8796b7ee |
1536 | emith_tst_r_imm(sr, S); |
f0d7b1fa |
1537 | EMITH_SJMP_START(DCOND_EQ); |
1538 | emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16); |
1539 | EMITH_SJMP_END(DCOND_EQ); |
23686515 |
1540 | rcache_unlock(sr); |
f0d7b1fa |
1541 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR |
1542 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
f0d7b1fa |
1543 | rcache_free_tmp(tmp2); |
8796b7ee |
1544 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case |
1545 | emith_tst_r_imm(sr, S); |
1546 | |
1547 | EMITH_JMP_START(DCOND_EQ); |
1548 | emith_asr(tmp, tmp4, 15); |
1549 | emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff) |
1550 | EMITH_SJMP_START(DCOND_GE); |
1551 | emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000); |
1552 | emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000); |
1553 | EMITH_SJMP_END(DCOND_GE); |
1554 | emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff) |
1555 | EMITH_SJMP_START(DCOND_LE); |
1556 | emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff); |
1557 | emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff); |
1558 | EMITH_SJMP_END(DCOND_LE); |
1559 | EMITH_JMP_END(DCOND_EQ); |
1560 | |
1561 | rcache_free_tmp(tmp); |
f0d7b1fa |
1562 | cycles += 3; |
1563 | goto end_op; |
80599a42 |
1564 | } |
1565 | goto default_; |
1566 | |
3863edbd |
1567 | ///////////////////////////////////////////// |
80599a42 |
1568 | case 0x01: |
1569 | // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd |
1570 | rcache_clean(); |
1571 | tmp = rcache_get_reg_arg(0, GET_Rn()); |
1572 | tmp2 = rcache_get_reg_arg(1, GET_Rm()); |
23686515 |
1573 | if (op & 0x0f) |
1574 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
e05b81fc |
1575 | emit_memhandler_write(2, pc, drcf.delayed_op); |
80599a42 |
1576 | goto end_op; |
1577 | |
1578 | case 0x02: |
1579 | switch (op & 0x0f) |
1580 | { |
1581 | case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000 |
1582 | case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001 |
1583 | case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010 |
1584 | rcache_clean(); |
1585 | rcache_get_reg_arg(0, GET_Rn()); |
1586 | rcache_get_reg_arg(1, GET_Rm()); |
e05b81fc |
1587 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1588 | goto end_op; |
1589 | case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 |
1590 | case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 |
1591 | case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110 |
1592 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1593 | emith_sub_r_imm(tmp, (1 << (op & 3))); |
1594 | rcache_clean(); |
1595 | rcache_get_reg_arg(0, GET_Rn()); |
1596 | rcache_get_reg_arg(1, GET_Rm()); |
e05b81fc |
1597 | emit_memhandler_write(op & 3, pc, drcf.delayed_op); |
80599a42 |
1598 | goto end_op; |
1599 | case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 |
8796b7ee |
1600 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
80599a42 |
1601 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1602 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1603 | if (drcf.delayed_op) |
1604 | DELAY_SAVE_T(sr); |
8796b7ee |
1605 | emith_bic_r_imm(sr, M|Q|T); |
80599a42 |
1606 | emith_tst_r_imm(tmp2, (1<<31)); |
1607 | EMITH_SJMP_START(DCOND_EQ); |
8796b7ee |
1608 | emith_or_r_imm_c(DCOND_NE, sr, Q); |
80599a42 |
1609 | EMITH_SJMP_END(DCOND_EQ); |
1610 | emith_tst_r_imm(tmp3, (1<<31)); |
1611 | EMITH_SJMP_START(DCOND_EQ); |
8796b7ee |
1612 | emith_or_r_imm_c(DCOND_NE, sr, M); |
80599a42 |
1613 | EMITH_SJMP_END(DCOND_EQ); |
1614 | emith_teq_r_r(tmp2, tmp3); |
1615 | EMITH_SJMP_START(DCOND_PL); |
8796b7ee |
1616 | emith_or_r_imm_c(DCOND_MI, sr, T); |
80599a42 |
1617 | EMITH_SJMP_END(DCOND_PL); |
1618 | goto end_op; |
3863edbd |
1619 | case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 |
8796b7ee |
1620 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1621 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1622 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1623 | if (drcf.delayed_op) |
1624 | DELAY_SAVE_T(sr); |
8796b7ee |
1625 | emith_bic_r_imm(sr, T); |
3863edbd |
1626 | emith_tst_r_r(tmp2, tmp3); |
8796b7ee |
1627 | emit_or_t_if_eq(sr); |
3863edbd |
1628 | goto end_op; |
1629 | case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 |
1630 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1631 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1632 | emith_and_r_r(tmp, tmp2); |
1633 | goto end_op; |
1634 | case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010 |
1635 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1636 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1637 | emith_eor_r_r(tmp, tmp2); |
1638 | goto end_op; |
1639 | case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011 |
1640 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1641 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1642 | emith_or_r_r(tmp, tmp2); |
1643 | goto end_op; |
1644 | case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100 |
1645 | tmp = rcache_get_tmp(); |
1646 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1647 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1648 | emith_eor_r_r_r(tmp, tmp2, tmp3); |
8796b7ee |
1649 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1650 | if (drcf.delayed_op) |
1651 | DELAY_SAVE_T(sr); |
8796b7ee |
1652 | emith_bic_r_imm(sr, T); |
3863edbd |
1653 | emith_tst_r_imm(tmp, 0x000000ff); |
52d759c3 |
1654 | emit_or_t_if_eq(tmp); |
3863edbd |
1655 | emith_tst_r_imm(tmp, 0x0000ff00); |
52d759c3 |
1656 | emit_or_t_if_eq(tmp); |
3863edbd |
1657 | emith_tst_r_imm(tmp, 0x00ff0000); |
52d759c3 |
1658 | emit_or_t_if_eq(tmp); |
3863edbd |
1659 | emith_tst_r_imm(tmp, 0xff000000); |
52d759c3 |
1660 | emit_or_t_if_eq(tmp); |
3863edbd |
1661 | rcache_free_tmp(tmp); |
1662 | goto end_op; |
1663 | case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101 |
1664 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1665 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1666 | emith_lsr(tmp, tmp, 16); |
f0d7b1fa |
1667 | emith_or_r_r_lsl(tmp, tmp2, 16); |
3863edbd |
1668 | goto end_op; |
1669 | case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110 |
1670 | case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111 |
1671 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1672 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1673 | if (op & 1) { |
1674 | emith_sext(tmp, tmp2, 16); |
1675 | } else |
1676 | emith_clear_msb(tmp, tmp2, 16); |
1677 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1678 | tmp2 = rcache_get_tmp(); |
1679 | if (op & 1) { |
1680 | emith_sext(tmp2, tmp3, 16); |
1681 | } else |
1682 | emith_clear_msb(tmp2, tmp3, 16); |
1683 | emith_mul(tmp, tmp, tmp2); |
1684 | rcache_free_tmp(tmp2); |
1685 | // FIXME: causes timing issues in Doom? |
1686 | // cycles++; |
1687 | goto end_op; |
679af8a3 |
1688 | } |
1689 | goto default_; |
1690 | |
3863edbd |
1691 | ///////////////////////////////////////////// |
1692 | case 0x03: |
1693 | switch (op & 0x0f) |
1694 | { |
1695 | case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000 |
1696 | case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010 |
1697 | case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 |
1698 | case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 |
1699 | case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 |
8796b7ee |
1700 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1701 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1702 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
18b94127 |
1703 | if (drcf.delayed_op) |
1704 | DELAY_SAVE_T(sr); |
8796b7ee |
1705 | emith_bic_r_imm(sr, T); |
3863edbd |
1706 | emith_cmp_r_r(tmp2, tmp3); |
1707 | switch (op & 0x07) |
1708 | { |
1709 | case 0x00: // CMP/EQ |
8796b7ee |
1710 | emit_or_t_if_eq(sr); |
3863edbd |
1711 | break; |
1712 | case 0x02: // CMP/HS |
1713 | EMITH_SJMP_START(DCOND_LO); |
8796b7ee |
1714 | emith_or_r_imm_c(DCOND_HS, sr, T); |
3863edbd |
1715 | EMITH_SJMP_END(DCOND_LO); |
1716 | break; |
1717 | case 0x03: // CMP/GE |
1718 | EMITH_SJMP_START(DCOND_LT); |
8796b7ee |
1719 | emith_or_r_imm_c(DCOND_GE, sr, T); |
3863edbd |
1720 | EMITH_SJMP_END(DCOND_LT); |
1721 | break; |
1722 | case 0x06: // CMP/HI |
1723 | EMITH_SJMP_START(DCOND_LS); |
8796b7ee |
1724 | emith_or_r_imm_c(DCOND_HI, sr, T); |
3863edbd |
1725 | EMITH_SJMP_END(DCOND_LS); |
1726 | break; |
1727 | case 0x07: // CMP/GT |
1728 | EMITH_SJMP_START(DCOND_LE); |
8796b7ee |
1729 | emith_or_r_imm_c(DCOND_GT, sr, T); |
3863edbd |
1730 | EMITH_SJMP_END(DCOND_LE); |
1731 | break; |
1732 | } |
1733 | goto end_op; |
1734 | case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100 |
f0d7b1fa |
1735 | // Q1 = carry(Rn = (Rn << 1) | T) |
1736 | // if Q ^ M |
1737 | // Q2 = carry(Rn += Rm) |
1738 | // else |
1739 | // Q2 = carry(Rn -= Rm) |
1740 | // Q = M ^ Q1 ^ Q2 |
1741 | // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2) |
1742 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1743 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1744 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1745 | if (drcf.delayed_op) |
1746 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1747 | emith_tpop_carry(sr, 0); |
f0d7b1fa |
1748 | emith_adcf_r_r(tmp2, tmp2); |
8b4f38f4 |
1749 | emith_tpush_carry(sr, 0); // keep Q1 in T for now |
f0d7b1fa |
1750 | tmp4 = rcache_get_tmp(); |
1751 | emith_and_r_r_imm(tmp4, sr, M); |
1752 | emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M |
1753 | rcache_free_tmp(tmp4); |
1754 | // add or sub, invert T if carry to get Q1 ^ Q2 |
1755 | // in: (Q ^ M) passed in Q, Q1 in T |
1756 | emith_sh2_div1_step(tmp2, tmp3, sr); |
18b94127 |
1757 | emith_bic_r_imm(sr, Q); |
1758 | emith_tst_r_imm(sr, M); |
1759 | EMITH_SJMP_START(DCOND_EQ); |
1760 | emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M |
1761 | EMITH_SJMP_END(DCOND_EQ); |
1762 | emith_tst_r_imm(sr, T); |
1763 | EMITH_SJMP_START(DCOND_EQ); |
1764 | emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 |
1765 | EMITH_SJMP_END(DCOND_EQ); |
1766 | emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) |
f0d7b1fa |
1767 | goto end_op; |
3863edbd |
1768 | case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 |
1769 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1770 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1771 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1772 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1773 | emith_mul_u64(tmp3, tmp4, tmp, tmp2); |
1774 | goto end_op; |
1775 | case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 |
1776 | case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 |
1777 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1778 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1779 | if (op & 4) { |
1780 | emith_add_r_r(tmp, tmp2); |
1781 | } else |
1782 | emith_sub_r_r(tmp, tmp2); |
1783 | goto end_op; |
1784 | case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010 |
1785 | case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 |
1786 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1787 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
8796b7ee |
1788 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1789 | if (drcf.delayed_op) |
1790 | DELAY_SAVE_T(sr); |
3863edbd |
1791 | if (op & 4) { // adc |
8b4f38f4 |
1792 | emith_tpop_carry(sr, 0); |
3863edbd |
1793 | emith_adcf_r_r(tmp, tmp2); |
8b4f38f4 |
1794 | emith_tpush_carry(sr, 0); |
3863edbd |
1795 | } else { |
8b4f38f4 |
1796 | emith_tpop_carry(sr, 1); |
3863edbd |
1797 | emith_sbcf_r_r(tmp, tmp2); |
8b4f38f4 |
1798 | emith_tpush_carry(sr, 1); |
3863edbd |
1799 | } |
3863edbd |
1800 | goto end_op; |
1801 | case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 |
1802 | case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 |
1803 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1804 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
8796b7ee |
1805 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1806 | if (drcf.delayed_op) |
1807 | DELAY_SAVE_T(sr); |
8796b7ee |
1808 | emith_bic_r_imm(sr, T); |
3863edbd |
1809 | if (op & 4) { |
1810 | emith_addf_r_r(tmp, tmp2); |
1811 | } else |
1812 | emith_subf_r_r(tmp, tmp2); |
1813 | EMITH_SJMP_START(DCOND_VC); |
8796b7ee |
1814 | emith_or_r_imm_c(DCOND_VS, sr, T); |
3863edbd |
1815 | EMITH_SJMP_END(DCOND_VC); |
1816 | goto end_op; |
1817 | case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 |
1818 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1819 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1820 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1821 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1822 | emith_mul_s64(tmp3, tmp4, tmp, tmp2); |
1823 | goto end_op; |
1824 | } |
1825 | goto default_; |
1826 | |
1827 | ///////////////////////////////////////////// |
679af8a3 |
1828 | case 0x04: |
3863edbd |
1829 | switch (op & 0x0f) |
1830 | { |
c18edb34 |
1831 | case 0x00: |
3863edbd |
1832 | switch (GET_Fx()) |
1833 | { |
1834 | case 0: // SHLL Rn 0100nnnn00000000 |
1835 | case 2: // SHAL Rn 0100nnnn00100000 |
8796b7ee |
1836 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1837 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1838 | if (drcf.delayed_op) |
1839 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1840 | emith_tpop_carry(sr, 0); // dummy |
3863edbd |
1841 | emith_lslf(tmp, tmp, 1); |
8b4f38f4 |
1842 | emith_tpush_carry(sr, 0); |
3863edbd |
1843 | goto end_op; |
1844 | case 1: // DT Rn 0100nnnn00010000 |
8796b7ee |
1845 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1846 | if (drcf.delayed_op) |
1847 | DELAY_SAVE_T(sr); |
23686515 |
1848 | if (FETCH_OP(pc) == 0x8bfd) { // BF #-2 |
1849 | if (gconst_get(GET_Rn(), &tmp)) { |
1850 | // XXX: limit burned cycles |
1851 | emit_move_r_imm32(GET_Rn(), 0); |
1852 | emith_or_r_imm(sr, T); |
a2b8c5a5 |
1853 | cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why |
23686515 |
1854 | skip_op = 1; |
1855 | } |
1856 | else |
1857 | emith_sh2_dtbf_loop(); |
1858 | goto end_op; |
1859 | } |
1860 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
8796b7ee |
1861 | emith_bic_r_imm(sr, T); |
3863edbd |
1862 | emith_subf_r_imm(tmp, 1); |
8796b7ee |
1863 | emit_or_t_if_eq(sr); |
80599a42 |
1864 | goto end_op; |
1865 | } |
3863edbd |
1866 | goto default_; |
ed8cf79b |
1867 | case 0x01: |
1868 | switch (GET_Fx()) |
1869 | { |
1870 | case 0: // SHLR Rn 0100nnnn00000001 |
1871 | case 2: // SHAR Rn 0100nnnn00100001 |
8796b7ee |
1872 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1873 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1874 | if (drcf.delayed_op) |
1875 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1876 | emith_tpop_carry(sr, 0); // dummy |
ed8cf79b |
1877 | if (op & 0x20) { |
1878 | emith_asrf(tmp, tmp, 1); |
1879 | } else |
1880 | emith_lsrf(tmp, tmp, 1); |
8b4f38f4 |
1881 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1882 | goto end_op; |
1883 | case 1: // CMP/PZ Rn 0100nnnn00010001 |
8796b7ee |
1884 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1885 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1886 | if (drcf.delayed_op) |
1887 | DELAY_SAVE_T(sr); |
8796b7ee |
1888 | emith_bic_r_imm(sr, T); |
ed8cf79b |
1889 | emith_cmp_r_imm(tmp, 0); |
1890 | EMITH_SJMP_START(DCOND_LT); |
8796b7ee |
1891 | emith_or_r_imm_c(DCOND_GE, sr, T); |
ed8cf79b |
1892 | EMITH_SJMP_END(DCOND_LT); |
1893 | goto end_op; |
1894 | } |
1895 | goto default_; |
1896 | case 0x02: |
1897 | case 0x03: |
1898 | switch (op & 0x3f) |
1899 | { |
1900 | case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010 |
1901 | tmp = SHR_MACH; |
1902 | break; |
1903 | case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010 |
1904 | tmp = SHR_MACL; |
1905 | break; |
1906 | case 0x22: // STS.L PR,@–Rn 0100nnnn00100010 |
1907 | tmp = SHR_PR; |
1908 | break; |
1909 | case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 |
1910 | tmp = SHR_SR; |
1911 | break; |
1912 | case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 |
1913 | tmp = SHR_GBR; |
1914 | break; |
1915 | case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 |
1916 | tmp = SHR_VBR; |
1917 | break; |
1918 | default: |
e898de13 |
1919 | goto default_; |
ed8cf79b |
1920 | } |
1921 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1922 | emith_sub_r_imm(tmp2, 4); |
1923 | rcache_clean(); |
1924 | rcache_get_reg_arg(0, GET_Rn()); |
1925 | tmp3 = rcache_get_reg_arg(1, tmp); |
1926 | if (tmp == SHR_SR) |
e05b81fc |
1927 | emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0 |
1928 | emit_memhandler_write(2, pc, drcf.delayed_op); |
ed8cf79b |
1929 | goto end_op; |
1930 | case 0x04: |
1931 | case 0x05: |
1932 | switch (op & 0x3f) |
1933 | { |
1934 | case 0x04: // ROTL Rn 0100nnnn00000100 |
1935 | case 0x05: // ROTR Rn 0100nnnn00000101 |
8796b7ee |
1936 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1937 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1938 | if (drcf.delayed_op) |
1939 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1940 | emith_tpop_carry(sr, 0); // dummy |
ed8cf79b |
1941 | if (op & 1) { |
1942 | emith_rorf(tmp, tmp, 1); |
1943 | } else |
1944 | emith_rolf(tmp, tmp, 1); |
8b4f38f4 |
1945 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1946 | goto end_op; |
1947 | case 0x24: // ROTCL Rn 0100nnnn00100100 |
1948 | case 0x25: // ROTCR Rn 0100nnnn00100101 |
8796b7ee |
1949 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1950 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1951 | if (drcf.delayed_op) |
1952 | DELAY_SAVE_T(sr); |
8b4f38f4 |
1953 | emith_tpop_carry(sr, 0); |
ed8cf79b |
1954 | if (op & 1) { |
1955 | emith_rorcf(tmp); |
1956 | } else |
1957 | emith_rolcf(tmp); |
8b4f38f4 |
1958 | emith_tpush_carry(sr, 0); |
ed8cf79b |
1959 | goto end_op; |
1960 | case 0x15: // CMP/PL Rn 0100nnnn00010101 |
8796b7ee |
1961 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1962 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
1963 | if (drcf.delayed_op) |
1964 | DELAY_SAVE_T(sr); |
8796b7ee |
1965 | emith_bic_r_imm(sr, T); |
ed8cf79b |
1966 | emith_cmp_r_imm(tmp, 0); |
1967 | EMITH_SJMP_START(DCOND_LE); |
8796b7ee |
1968 | emith_or_r_imm_c(DCOND_GT, sr, T); |
ed8cf79b |
1969 | EMITH_SJMP_END(DCOND_LE); |
1970 | goto end_op; |
1971 | } |
e898de13 |
1972 | goto default_; |
ed8cf79b |
1973 | case 0x06: |
1974 | case 0x07: |
1975 | switch (op & 0x3f) |
1976 | { |
1977 | case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110 |
1978 | tmp = SHR_MACH; |
1979 | break; |
1980 | case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110 |
1981 | tmp = SHR_MACL; |
1982 | break; |
1983 | case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110 |
1984 | tmp = SHR_PR; |
1985 | break; |
1986 | case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 |
1987 | tmp = SHR_SR; |
1988 | break; |
1989 | case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 |
1990 | tmp = SHR_GBR; |
1991 | break; |
1992 | case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 |
1993 | tmp = SHR_VBR; |
1994 | break; |
1995 | default: |
1996 | goto default_; |
1997 | } |
ed8cf79b |
1998 | rcache_get_reg_arg(0, GET_Rn()); |
1999 | tmp2 = emit_memhandler_read(2); |
2000 | if (tmp == SHR_SR) { |
18b94127 |
2001 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2002 | if (drcf.delayed_op) |
2003 | DELAY_SAVE_T(sr); |
2004 | emith_write_sr(sr, tmp2); |
2005 | drcf.test_irq = 1; |
ed8cf79b |
2006 | } else { |
2007 | tmp = rcache_get_reg(tmp, RC_GR_WRITE); |
2008 | emith_move_r_r(tmp, tmp2); |
2009 | } |
2010 | rcache_free_tmp(tmp2); |
2011 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
2012 | emith_add_r_imm(tmp, 4); |
2013 | goto end_op; |
52d759c3 |
2014 | case 0x08: |
2015 | case 0x09: |
2016 | switch (GET_Fx()) |
2017 | { |
2018 | case 0: |
2019 | // SHLL2 Rn 0100nnnn00001000 |
2020 | // SHLR2 Rn 0100nnnn00001001 |
2021 | tmp = 2; |
2022 | break; |
2023 | case 1: |
2024 | // SHLL8 Rn 0100nnnn00011000 |
2025 | // SHLR8 Rn 0100nnnn00011001 |
2026 | tmp = 8; |
2027 | break; |
2028 | case 2: |
2029 | // SHLL16 Rn 0100nnnn00101000 |
2030 | // SHLR16 Rn 0100nnnn00101001 |
2031 | tmp = 16; |
2032 | break; |
2033 | default: |
2034 | goto default_; |
2035 | } |
2036 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
2037 | if (op & 1) { |
2038 | emith_lsr(tmp2, tmp2, tmp); |
2039 | } else |
2040 | emith_lsl(tmp2, tmp2, tmp); |
2041 | goto end_op; |
2042 | case 0x0a: |
2043 | switch (GET_Fx()) |
2044 | { |
2045 | case 0: // LDS Rm,MACH 0100mmmm00001010 |
2046 | tmp2 = SHR_MACH; |
2047 | break; |
2048 | case 1: // LDS Rm,MACL 0100mmmm00011010 |
2049 | tmp2 = SHR_MACL; |
2050 | break; |
2051 | case 2: // LDS Rm,PR 0100mmmm00101010 |
2052 | tmp2 = SHR_PR; |
2053 | break; |
2054 | default: |
2055 | goto default_; |
2056 | } |
2057 | emit_move_r_r(tmp2, GET_Rn()); |
2058 | goto end_op; |
e898de13 |
2059 | case 0x0b: |
52d759c3 |
2060 | switch (GET_Fx()) |
2061 | { |
2062 | case 0: // JSR @Rm 0100mmmm00001011 |
2063 | case 2: // JMP @Rm 0100mmmm00101011 |
2064 | DELAYED_OP; |
2065 | if (!(op & 0x20)) |
2066 | emit_move_r_imm32(SHR_PR, pc + 2); |
18b94127 |
2067 | emit_move_r_r(SHR_PC, (op >> 8) & 0x0f); |
44e6452e |
2068 | out_pc = (u32)-1; |
52d759c3 |
2069 | cycles++; |
2070 | break; |
2071 | case 1: // TAS.B @Rn 0100nnnn00011011 |
2072 | // XXX: is TAS working on 32X? |
52d759c3 |
2073 | rcache_get_reg_arg(0, GET_Rn()); |
8796b7ee |
2074 | tmp = emit_memhandler_read(0); |
2075 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2076 | if (drcf.delayed_op) |
2077 | DELAY_SAVE_T(sr); |
8796b7ee |
2078 | emith_bic_r_imm(sr, T); |
52d759c3 |
2079 | emith_cmp_r_imm(tmp, 0); |
8796b7ee |
2080 | emit_or_t_if_eq(sr); |
52d759c3 |
2081 | rcache_clean(); |
2082 | emith_or_r_imm(tmp, 0x80); |
2083 | tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp |
2084 | emith_move_r_r(tmp2, tmp); |
2085 | rcache_free_tmp(tmp); |
2086 | rcache_get_reg_arg(0, GET_Rn()); |
e05b81fc |
2087 | emit_memhandler_write(0, pc, drcf.delayed_op); |
52d759c3 |
2088 | cycles += 3; |
2089 | break; |
2090 | default: |
e898de13 |
2091 | goto default_; |
52d759c3 |
2092 | } |
e898de13 |
2093 | goto end_op; |
2094 | case 0x0e: |
52d759c3 |
2095 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
2096 | switch (GET_Fx()) |
2097 | { |
2098 | case 0: // LDC Rm,SR 0100mmmm00001110 |
2099 | tmp2 = SHR_SR; |
2100 | break; |
2101 | case 1: // LDC Rm,GBR 0100mmmm00011110 |
2102 | tmp2 = SHR_GBR; |
2103 | break; |
2104 | case 2: // LDC Rm,VBR 0100mmmm00101110 |
2105 | tmp2 = SHR_VBR; |
2106 | break; |
2107 | default: |
e898de13 |
2108 | goto default_; |
52d759c3 |
2109 | } |
2110 | if (tmp2 == SHR_SR) { |
18b94127 |
2111 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2112 | if (drcf.delayed_op) |
2113 | DELAY_SAVE_T(sr); |
2114 | emith_write_sr(sr, tmp); |
2115 | drcf.test_irq = 1; |
52d759c3 |
2116 | } else { |
2117 | tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE); |
2118 | emith_move_r_r(tmp2, tmp); |
2119 | } |
2120 | goto end_op; |
2121 | case 0x0f: |
23686515 |
2122 | // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 |
f0d7b1fa |
2123 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1); |
2124 | emith_sext(tmp, tmp, 16); |
2125 | emith_sext(tmp2, tmp2, 16); |
2126 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); |
2127 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
2128 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
f0d7b1fa |
2129 | rcache_free_tmp(tmp2); |
f0d7b1fa |
2130 | // XXX: MACH should be untouched when S is set? |
8796b7ee |
2131 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
2132 | emith_tst_r_imm(sr, S); |
2133 | EMITH_JMP_START(DCOND_EQ); |
2134 | |
2135 | emith_asr(tmp, tmp3, 31); |
2136 | emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach |
2137 | EMITH_JMP_START(DCOND_EQ); |
2138 | emith_move_r_imm(tmp3, 0x80000000); |
2139 | emith_tst_r_r(tmp4, tmp4); |
2140 | EMITH_SJMP_START(DCOND_MI); |
2141 | emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive |
2142 | EMITH_SJMP_END(DCOND_MI); |
2143 | EMITH_JMP_END(DCOND_EQ); |
2144 | |
2145 | EMITH_JMP_END(DCOND_EQ); |
2146 | rcache_free_tmp(tmp); |
f0d7b1fa |
2147 | cycles += 2; |
2148 | goto end_op; |
679af8a3 |
2149 | } |
2150 | goto default_; |
2151 | |
52d759c3 |
2152 | ///////////////////////////////////////////// |
2153 | case 0x05: |
2154 | // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd |
23686515 |
2155 | emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2); |
52d759c3 |
2156 | goto end_op; |
2157 | |
2158 | ///////////////////////////////////////////// |
2159 | case 0x06: |
2160 | switch (op & 0x0f) |
2161 | { |
2162 | case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000 |
2163 | case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001 |
2164 | case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010 |
2165 | case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100 |
2166 | case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101 |
2167 | case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110 |
23686515 |
2168 | emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3); |
52d759c3 |
2169 | if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) { |
2170 | tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW); |
2171 | emith_add_r_imm(tmp, (1 << (op & 3))); |
2172 | } |
2173 | goto end_op; |
2174 | case 0x03: |
2175 | case 0x07 ... 0x0f: |
2176 | tmp = rcache_get_reg(GET_Rm(), RC_GR_READ); |
2177 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
2178 | switch (op & 0x0f) |
2179 | { |
2180 | case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011 |
2181 | emith_move_r_r(tmp2, tmp); |
2182 | break; |
2183 | case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111 |
2184 | emith_mvn_r_r(tmp2, tmp); |
2185 | break; |
2186 | case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000 |
2187 | tmp3 = tmp2; |
2188 | if (tmp == tmp2) |
2189 | tmp3 = rcache_get_tmp(); |
2190 | tmp4 = rcache_get_tmp(); |
2191 | emith_lsr(tmp3, tmp, 16); |
f0d7b1fa |
2192 | emith_or_r_r_lsl(tmp3, tmp, 24); |
52d759c3 |
2193 | emith_and_r_r_imm(tmp4, tmp, 0xff00); |
f0d7b1fa |
2194 | emith_or_r_r_lsl(tmp3, tmp4, 8); |
52d759c3 |
2195 | emith_rol(tmp2, tmp3, 16); |
2196 | rcache_free_tmp(tmp4); |
2197 | if (tmp == tmp2) |
2198 | rcache_free_tmp(tmp3); |
2199 | break; |
2200 | case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001 |
2201 | emith_rol(tmp2, tmp, 16); |
2202 | break; |
2203 | case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 |
8796b7ee |
2204 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2205 | if (drcf.delayed_op) |
2206 | DELAY_SAVE_T(sr); |
8b4f38f4 |
2207 | emith_tpop_carry(sr, 1); |
52d759c3 |
2208 | emith_negcf_r_r(tmp2, tmp); |
8b4f38f4 |
2209 | emith_tpush_carry(sr, 1); |
52d759c3 |
2210 | break; |
2211 | case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011 |
2212 | emith_neg_r_r(tmp2, tmp); |
2213 | break; |
2214 | case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100 |
2215 | emith_clear_msb(tmp2, tmp, 24); |
2216 | break; |
2217 | case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101 |
2218 | emith_clear_msb(tmp2, tmp, 16); |
2219 | break; |
2220 | case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110 |
2221 | emith_sext(tmp2, tmp, 8); |
2222 | break; |
2223 | case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111 |
2224 | emith_sext(tmp2, tmp, 16); |
2225 | break; |
2226 | } |
2227 | goto end_op; |
2228 | } |
2229 | goto default_; |
2230 | |
2231 | ///////////////////////////////////////////// |
2232 | case 0x07: |
2233 | // ADD #imm,Rn 0111nnnniiiiiiii |
2234 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
2235 | if (op & 0x80) { // adding negative |
2236 | emith_sub_r_imm(tmp, -op & 0xff); |
2237 | } else |
2238 | emith_add_r_imm(tmp, op & 0xff); |
2239 | goto end_op; |
2240 | |
3863edbd |
2241 | ///////////////////////////////////////////// |
e898de13 |
2242 | case 0x08: |
52d759c3 |
2243 | switch (op & 0x0f00) |
2244 | { |
2245 | case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd |
2246 | case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd |
2247 | rcache_clean(); |
2248 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
2249 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
2250 | tmp3 = (op & 0x100) >> 8; |
23686515 |
2251 | if (op & 0x0f) |
2252 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
e05b81fc |
2253 | emit_memhandler_write(tmp3, pc, drcf.delayed_op); |
52d759c3 |
2254 | goto end_op; |
2255 | case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd |
2256 | case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd |
23686515 |
2257 | tmp = (op & 0x100) >> 8; |
2258 | emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp); |
52d759c3 |
2259 | goto end_op; |
2260 | case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii |
2261 | // XXX: could use cmn |
2262 | tmp = rcache_get_tmp(); |
2263 | tmp2 = rcache_get_reg(0, RC_GR_READ); |
8796b7ee |
2264 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2265 | if (drcf.delayed_op) |
2266 | DELAY_SAVE_T(sr); |
52d759c3 |
2267 | emith_move_r_imm_s8(tmp, op & 0xff); |
8796b7ee |
2268 | emith_bic_r_imm(sr, T); |
52d759c3 |
2269 | emith_cmp_r_r(tmp2, tmp); |
8796b7ee |
2270 | emit_or_t_if_eq(sr); |
52d759c3 |
2271 | rcache_free_tmp(tmp); |
2272 | goto end_op; |
2273 | case 0x0d00: // BT/S label 10001101dddddddd |
2274 | case 0x0f00: // BF/S label 10001111dddddddd |
679af8a3 |
2275 | DELAYED_OP; |
2276 | cycles--; |
679af8a3 |
2277 | // fallthrough |
44e6452e |
2278 | case 0x0900: // BT label 10001001dddddddd |
2279 | case 0x0b00: // BF label 10001011dddddddd |
2280 | // will handle conditional branches later |
2281 | pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; |
2282 | i = ((signed int)(op << 24) >> 23); |
2283 | pending_branch_pc = pc + i + 2; |
e898de13 |
2284 | cycles += 2; |
e898de13 |
2285 | goto end_op; |
44e6452e |
2286 | } |
679af8a3 |
2287 | goto default_; |
679af8a3 |
2288 | |
52d759c3 |
2289 | ///////////////////////////////////////////// |
2290 | case 0x09: |
2291 | // MOV.W @(disp,PC),Rn 1001nnnndddddddd |
23686515 |
2292 | tmp = pc + (op & 0xff) * 2 + 2; |
2293 | #if PROPAGATE_CONSTANTS |
2294 | if (tmp < end_pc + MAX_LITERAL_OFFSET) { |
2295 | gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp)); |
2296 | if (last_inlined_literal < tmp) |
2297 | last_inlined_literal = tmp; |
2298 | } |
2299 | else |
2300 | #endif |
2301 | { |
2302 | tmp2 = rcache_get_tmp_arg(0); |
2303 | emith_move_r_imm(tmp2, tmp); |
2304 | tmp2 = emit_memhandler_read(1); |
2305 | tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
2306 | emith_sext(tmp3, tmp2, 16); |
2307 | rcache_free_tmp(tmp2); |
2308 | } |
f0d7b1fa |
2309 | goto end_op; |
52d759c3 |
2310 | |
3863edbd |
2311 | ///////////////////////////////////////////// |
679af8a3 |
2312 | case 0x0a: |
2313 | // BRA label 1010dddddddddddd |
2314 | DELAYED_OP; |
44e6452e |
2315 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
679af8a3 |
2316 | tmp = ((signed int)(op << 20) >> 19); |
44e6452e |
2317 | out_pc = pc + tmp + 2; |
2318 | if (tmp == (u32)-4) |
2319 | emith_clear_msb(sr, sr, 20); // burn cycles |
679af8a3 |
2320 | cycles++; |
e898de13 |
2321 | break; |
679af8a3 |
2322 | |
3863edbd |
2323 | ///////////////////////////////////////////// |
679af8a3 |
2324 | case 0x0b: |
2325 | // BSR label 1011dddddddddddd |
2326 | DELAYED_OP; |
e898de13 |
2327 | emit_move_r_imm32(SHR_PR, pc + 2); |
44e6452e |
2328 | tmp = ((signed int)(op << 20) >> 19); |
2329 | out_pc = pc + tmp + 2; |
2330 | cycles++; |
2331 | break; |
679af8a3 |
2332 | |
52d759c3 |
2333 | ///////////////////////////////////////////// |
2334 | case 0x0c: |
2335 | switch (op & 0x0f00) |
2336 | { |
2337 | case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd |
2338 | case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd |
2339 | case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd |
2340 | rcache_clean(); |
2341 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
2342 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
2343 | tmp3 = (op & 0x300) >> 8; |
2344 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
e05b81fc |
2345 | emit_memhandler_write(tmp3, pc, drcf.delayed_op); |
52d759c3 |
2346 | goto end_op; |
2347 | case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd |
2348 | case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd |
2349 | case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd |
23686515 |
2350 | tmp = (op & 0x300) >> 8; |
2351 | emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp); |
52d759c3 |
2352 | goto end_op; |
2353 | case 0x0300: // TRAPA #imm 11000011iiiiiiii |
2354 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
2355 | emith_sub_r_imm(tmp, 4*2); |
52d759c3 |
2356 | // push SR |
2357 | tmp = rcache_get_reg_arg(0, SHR_SP); |
2358 | emith_add_r_imm(tmp, 4); |
2359 | tmp = rcache_get_reg_arg(1, SHR_SR); |
18b94127 |
2360 | emith_clear_msb(tmp, tmp, 22); |
e05b81fc |
2361 | emit_memhandler_write(2, pc, drcf.delayed_op); |
52d759c3 |
2362 | // push PC |
2363 | rcache_get_reg_arg(0, SHR_SP); |
2364 | tmp = rcache_get_tmp_arg(1); |
2365 | emith_move_r_imm(tmp, pc); |
e05b81fc |
2366 | emit_memhandler_write(2, pc, drcf.delayed_op); |
52d759c3 |
2367 | // obtain new PC |
23686515 |
2368 | emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2); |
44e6452e |
2369 | out_pc = (u32)-1; |
52d759c3 |
2370 | cycles += 7; |
44e6452e |
2371 | goto end_op; |
52d759c3 |
2372 | case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd |
2373 | emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3); |
2374 | goto end_op; |
2375 | case 0x0800: // TST #imm,R0 11001000iiiiiiii |
8796b7ee |
2376 | tmp = rcache_get_reg(SHR_R0, RC_GR_READ); |
2377 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2378 | if (drcf.delayed_op) |
2379 | DELAY_SAVE_T(sr); |
8796b7ee |
2380 | emith_bic_r_imm(sr, T); |
52d759c3 |
2381 | emith_tst_r_imm(tmp, op & 0xff); |
8796b7ee |
2382 | emit_or_t_if_eq(sr); |
52d759c3 |
2383 | goto end_op; |
2384 | case 0x0900: // AND #imm,R0 11001001iiiiiiii |
2385 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2386 | emith_and_r_imm(tmp, op & 0xff); |
2387 | goto end_op; |
2388 | case 0x0a00: // XOR #imm,R0 11001010iiiiiiii |
2389 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2390 | emith_eor_r_imm(tmp, op & 0xff); |
2391 | goto end_op; |
2392 | case 0x0b00: // OR #imm,R0 11001011iiiiiiii |
2393 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
2394 | emith_or_r_imm(tmp, op & 0xff); |
2395 | goto end_op; |
2396 | case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii |
8796b7ee |
2397 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2398 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
18b94127 |
2399 | if (drcf.delayed_op) |
2400 | DELAY_SAVE_T(sr); |
8796b7ee |
2401 | emith_bic_r_imm(sr, T); |
52d759c3 |
2402 | emith_tst_r_imm(tmp, op & 0xff); |
8796b7ee |
2403 | emit_or_t_if_eq(sr); |
52d759c3 |
2404 | rcache_free_tmp(tmp); |
2405 | cycles += 2; |
2406 | goto end_op; |
2407 | case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii |
2408 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2409 | emith_and_r_imm(tmp, op & 0xff); |
8796b7ee |
2410 | goto end_rmw_op; |
52d759c3 |
2411 | case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii |
2412 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2413 | emith_eor_r_imm(tmp, op & 0xff); |
8796b7ee |
2414 | goto end_rmw_op; |
52d759c3 |
2415 | case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii |
2416 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
2417 | emith_or_r_imm(tmp, op & 0xff); |
8796b7ee |
2418 | end_rmw_op: |
2419 | tmp2 = rcache_get_tmp_arg(1); |
2420 | emith_move_r_r(tmp2, tmp); |
2421 | rcache_free_tmp(tmp); |
2422 | tmp3 = rcache_get_reg_arg(0, SHR_GBR); |
2423 | tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ); |
2424 | emith_add_r_r(tmp3, tmp4); |
e05b81fc |
2425 | emit_memhandler_write(0, pc, drcf.delayed_op); |
52d759c3 |
2426 | cycles += 2; |
2427 | goto end_op; |
2428 | } |
2429 | goto default_; |
2430 | |
2431 | ///////////////////////////////////////////// |
2432 | case 0x0d: |
2433 | // MOV.L @(disp,PC),Rn 1101nnnndddddddd |
23686515 |
2434 | tmp = (pc + (op & 0xff) * 4 + 2) & ~3; |
2435 | #if PROPAGATE_CONSTANTS |
2436 | if (tmp < end_pc + MAX_LITERAL_OFFSET) { |
2437 | gconst_new(GET_Rn(), FETCH32(tmp)); |
2438 | if (last_inlined_literal < tmp) |
2439 | last_inlined_literal = tmp; |
2440 | } |
2441 | else |
2442 | #endif |
2443 | { |
2444 | tmp2 = rcache_get_tmp_arg(0); |
2445 | emith_move_r_imm(tmp2, tmp); |
2446 | tmp2 = emit_memhandler_read(2); |
2447 | tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
2448 | emith_move_r_r(tmp3, tmp2); |
2449 | rcache_free_tmp(tmp2); |
2450 | } |
f0d7b1fa |
2451 | goto end_op; |
52d759c3 |
2452 | |
2453 | ///////////////////////////////////////////// |
2454 | case 0x0e: |
2455 | // MOV #imm,Rn 1110nnnniiiiiiii |
23686515 |
2456 | emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op); |
52d759c3 |
2457 | goto end_op; |
2458 | |
679af8a3 |
2459 | default: |
2460 | default_: |
f0d7b1fa |
2461 | elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", |
2462 | sh2->is_slave ? 's' : 'm', op, pc - 2); |
2463 | #ifdef DRC_DEBUG_INTERP |
679af8a3 |
2464 | emit_move_r_imm32(SHR_PC, pc - 2); |
c18edb34 |
2465 | rcache_flush(); |
f4bb5d6b |
2466 | emith_pass_arg_r(0, CONTEXT_REG); |
2467 | emith_pass_arg_imm(1, op); |
679af8a3 |
2468 | emith_call(sh2_do_op); |
f0d7b1fa |
2469 | #endif |
679af8a3 |
2470 | break; |
2471 | } |
2472 | |
e898de13 |
2473 | end_op: |
23686515 |
2474 | rcache_unlock_all(); |
2475 | |
44e6452e |
2476 | // conditional branch handling (with/without delay) |
2477 | if (pending_branch_cond != -1 && drcf.delayed_op != 2) |
2478 | { |
2479 | u32 target_pc = pending_branch_pc; |
2480 | void *target; |
2481 | |
18b94127 |
2482 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2483 | // handle cycles |
e05b81fc |
2484 | FLUSH_CYCLES(sr); |
18b94127 |
2485 | rcache_clean(); |
18b94127 |
2486 | if (drcf.use_saved_t) |
2487 | emith_tst_r_imm(sr, T_save); |
2488 | else |
2489 | emith_tst_r_imm(sr, T); |
18b94127 |
2490 | |
5686d931 |
2491 | #if LINK_BRANCHES |
44e6452e |
2492 | if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) { |
2493 | // local branch |
2494 | // XXX: jumps back can be linked already |
2495 | branch_patch_pc[branch_patch_count] = target_pc; |
2496 | branch_patch_ptr[branch_patch_count] = tcache_ptr; |
2497 | emith_jump_cond_patchable(pending_branch_cond, tcache_ptr); |
2498 | |
2499 | branch_patch_count++; |
2500 | if (branch_patch_count == MAX_LOCAL_BRANCHES) { |
2501 | printf("warning: too many local branches\n"); |
2502 | break; |
2503 | } |
2504 | } |
5686d931 |
2505 | else |
2506 | #endif |
2507 | { |
44e6452e |
2508 | // can't resolve branch locally, make a block exit |
2509 | emit_move_r_imm32(SHR_PC, target_pc); |
2510 | rcache_clean(); |
2511 | |
2512 | target = dr_prepare_ext_branch(target_pc, sh2, tcache_id); |
2513 | if (target == NULL) |
2514 | return NULL; |
2515 | emith_jump_cond_patchable(pending_branch_cond, target); |
18b94127 |
2516 | } |
44e6452e |
2517 | |
2518 | drcf.use_saved_t = 0; |
2519 | pending_branch_cond = -1; |
e898de13 |
2520 | } |
44e6452e |
2521 | |
18b94127 |
2522 | // test irq? |
e05b81fc |
2523 | // XXX: delay slots.. |
2524 | if (drcf.test_irq && drcf.delayed_op != 2) { |
2525 | if (!drcf.delayed_op) |
2526 | emit_move_r_imm32(SHR_PC, pc); |
2527 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2528 | FLUSH_CYCLES(sr); |
2529 | rcache_flush(); |
2530 | emith_call(sh2_drc_test_irq); |
2531 | drcf.test_irq = 0; |
2532 | } |
e898de13 |
2533 | |
f4bb5d6b |
2534 | do_host_disasm(tcache_id); |
52d759c3 |
2535 | |
44e6452e |
2536 | if (out_pc != 0 && drcf.delayed_op != 2) |
2537 | break; |
2538 | } |
f4bb5d6b |
2539 | |
18b94127 |
2540 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
e05b81fc |
2541 | FLUSH_CYCLES(tmp); |
18b94127 |
2542 | rcache_flush(); |
44e6452e |
2543 | |
2544 | if (out_pc == (u32)-1) { |
2545 | // indirect jump -> back to dispatcher |
2546 | emith_jump(sh2_drc_dispatcher); |
2547 | } else { |
2548 | void *target; |
2549 | if (out_pc == 0) |
2550 | out_pc = pc; |
2551 | emit_move_r_imm32(SHR_PC, out_pc); |
2552 | rcache_flush(); |
2553 | |
2554 | target = dr_prepare_ext_branch(out_pc, sh2, tcache_id); |
2555 | if (target == NULL) |
2556 | return NULL; |
2557 | emith_jump_patchable(target); |
2558 | } |
18b94127 |
2559 | |
2560 | // link local branches |
2561 | for (i = 0; i < branch_patch_count; i++) { |
2562 | void *target; |
2563 | int t; |
18b94127 |
2564 | t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]); |
44e6452e |
2565 | target = branch_target_ptr[t]; |
2566 | if (target == NULL) { |
2567 | // flush pc and go back to dispatcher (should no longer happen) |
18b94127 |
2568 | printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr); |
2569 | target = tcache_ptr; |
2570 | emit_move_r_imm32(SHR_PC, branch_patch_pc[i]); |
2571 | rcache_flush(); |
e05b81fc |
2572 | emith_jump(sh2_drc_dispatcher); |
18b94127 |
2573 | } |
2574 | emith_jump_patch(branch_patch_ptr[i], target); |
2575 | } |
2576 | |
a2b8c5a5 |
2577 | end_pc = pc; |
2578 | if (last_inlined_literal > end_pc) |
2579 | end_pc = last_inlined_literal + 4; |
44e6452e |
2580 | |
f4bb5d6b |
2581 | // mark memory blocks as containing compiled code |
a2b8c5a5 |
2582 | // override any overlay blocks as they become unreachable anyway |
2583 | if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000) |
2584 | { |
2585 | u16 *drc_ram_blk = NULL; |
2586 | u32 mask = 0, shift = 0; |
2587 | |
2588 | if (tcache_id != 0) { |
2589 | // data array, BIOS |
2590 | drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave]; |
2591 | shift = SH2_DRCBLK_DA_SHIFT; |
2592 | mask = 0xfff; |
f4bb5d6b |
2593 | } |
a2b8c5a5 |
2594 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { |
2595 | // SDRAM |
2596 | drc_ram_blk = Pico32xMem->drcblk_ram; |
2597 | shift = SH2_DRCBLK_RAM_SHIFT; |
2598 | mask = 0x3ffff; |
f4bb5d6b |
2599 | } |
a2b8c5a5 |
2600 | |
2601 | drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1; |
2602 | for (pc = base_pc + 2; pc < end_pc; pc += 2) |
2603 | drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1; |
2604 | |
2605 | // mark subblocks too |
2606 | for (i = 0; i < branch_target_count; i++) |
2607 | if (branch_target_blkid[i] != 0) |
2608 | drc_ram_blk[(branch_target_pc[i] >> shift) & mask] = |
2609 | branch_target_blkid[i] << 1; |
679af8a3 |
2610 | } |
2611 | |
f4bb5d6b |
2612 | tcache_ptrs[tcache_id] = tcache_ptr; |
2613 | |
a2b8c5a5 |
2614 | host_instructions_updated(block_entry, tcache_ptr); |
553c3eaa |
2615 | |
f4bb5d6b |
2616 | do_host_disasm(tcache_id); |
2617 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
2618 | tcache_id, block_counts[tcache_id], |
2619 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
2620 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
2621 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
2622 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
18b94127 |
2623 | /* |
2624 | printf("~~~\n"); |
2625 | tcache_dsm_ptrs[tcache_id] = block_entry; |
2626 | do_host_disasm(tcache_id); |
2627 | printf("~~~\n"); |
2628 | */ |
2629 | |
553c3eaa |
2630 | #if (DRC_DEBUG & 2) |
2631 | fflush(stdout); |
2632 | #endif |
2633 | |
679af8a3 |
2634 | return block_entry; |
679af8a3 |
2635 | } |
2636 | |
e05b81fc |
2637 | static void sh2_generate_utils(void) |
679af8a3 |
2638 | { |
e05b81fc |
2639 | int arg0, arg1, arg2, sr, tmp; |
2640 | void *sh2_drc_write_end, *sh2_drc_write_slot_end; |
52d759c3 |
2641 | |
5686d931 |
2642 | sh2_drc_write32 = p32x_sh2_write32; |
2643 | sh2_drc_read8 = p32x_sh2_read8; |
2644 | sh2_drc_read16 = p32x_sh2_read16; |
2645 | sh2_drc_read32 = p32x_sh2_read32; |
2646 | |
e05b81fc |
2647 | host_arg2reg(arg0, 0); |
2648 | host_arg2reg(arg1, 1); |
2649 | host_arg2reg(arg2, 2); |
2650 | emith_move_r_r(arg0, arg0); // nop |
679af8a3 |
2651 | |
e05b81fc |
2652 | // sh2_drc_exit(void) |
2653 | sh2_drc_exit = (void *)tcache_ptr; |
2654 | emit_do_static_regs(1, arg2); |
2655 | emith_sh2_drc_exit(); |
679af8a3 |
2656 | |
e05b81fc |
2657 | // sh2_drc_dispatcher(void) |
2658 | sh2_drc_dispatcher = (void *)tcache_ptr; |
2659 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
2660 | emith_cmp_r_imm(sr, 0); |
2661 | emith_jump_cond(DCOND_LT, sh2_drc_exit); |
2662 | rcache_invalidate(); |
2663 | emith_ctx_read(arg0, SHR_PC * 4); |
2664 | emith_ctx_read(arg1, offsetof(SH2, is_slave)); |
2665 | emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp)); |
a2b8c5a5 |
2666 | emith_call(dr_lookup_block); |
e05b81fc |
2667 | emit_block_entry(); |
2668 | // lookup failed, call sh2_translate() |
2669 | emith_move_r_r(arg0, CONTEXT_REG); |
2670 | emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id |
2671 | emith_call(sh2_translate); |
2672 | emit_block_entry(); |
2673 | // sh2_translate() failed, flush cache and retry |
2674 | emith_ctx_read(arg0, offsetof(SH2, drc_tmp)); |
2675 | emith_call(flush_tcache); |
2676 | emith_move_r_r(arg0, CONTEXT_REG); |
2677 | emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); |
2678 | emith_call(sh2_translate); |
2679 | emit_block_entry(); |
2680 | // XXX: can't translate, fail |
2681 | emith_call(exit); |
2682 | |
2683 | // sh2_drc_test_irq(void) |
2684 | // assumes it's called from main function (may jump to dispatcher) |
2685 | sh2_drc_test_irq = (void *)tcache_ptr; |
2686 | emith_ctx_read(arg1, offsetof(SH2, pending_level)); |
2687 | sr = rcache_get_reg(SHR_SR, RC_GR_READ); |
2688 | emith_lsr(arg0, sr, I_SHIFT); |
2689 | emith_and_r_imm(arg0, 0x0f); |
2690 | emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)? |
2691 | EMITH_SJMP_START(DCOND_GT); |
2692 | emith_ret_c(DCOND_LE); // nope, return |
2693 | EMITH_SJMP_END(DCOND_GT); |
2694 | // adjust SP |
2695 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
2696 | emith_sub_r_imm(tmp, 4*2); |
2697 | rcache_clean(); |
2698 | // push SR |
2699 | tmp = rcache_get_reg_arg(0, SHR_SP); |
2700 | emith_add_r_imm(tmp, 4); |
2701 | tmp = rcache_get_reg_arg(1, SHR_SR); |
2702 | emith_clear_msb(tmp, tmp, 22); |
2703 | emith_move_r_r(arg2, CONTEXT_REG); |
5686d931 |
2704 | emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32? |
e05b81fc |
2705 | rcache_invalidate(); |
2706 | // push PC |
2707 | rcache_get_reg_arg(0, SHR_SP); |
2708 | emith_ctx_read(arg1, SHR_PC * 4); |
2709 | emith_move_r_r(arg2, CONTEXT_REG); |
2710 | emith_call(p32x_sh2_write32); |
2711 | rcache_invalidate(); |
2712 | // update I, cycles, do callback |
2713 | emith_ctx_read(arg1, offsetof(SH2, pending_level)); |
2714 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2715 | emith_bic_r_imm(sr, I); |
2716 | emith_or_r_r_lsl(sr, arg1, I_SHIFT); |
2717 | emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles |
2718 | rcache_flush(); |
2719 | emith_move_r_r(arg0, CONTEXT_REG); |
2720 | emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level); |
2721 | // obtain new PC |
2722 | emith_lsl(arg0, arg0, 2); |
2723 | emith_ctx_read(arg1, SHR_VBR * 4); |
2724 | emith_add_r_r(arg0, arg1); |
2725 | emit_memhandler_read(2); |
2726 | emith_ctx_write(arg0, SHR_PC * 4); |
2727 | #ifdef __i386__ |
2728 | emith_add_r_imm(xSP, 4); // fix stack |
2729 | #endif |
2730 | emith_jump(sh2_drc_dispatcher); |
2731 | rcache_invalidate(); |
2732 | |
2733 | // sh2_drc_entry(SH2 *sh2) |
2734 | sh2_drc_entry = (void *)tcache_ptr; |
2735 | emith_sh2_drc_entry(); |
2736 | emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0 |
2737 | emit_do_static_regs(0, arg2); |
2738 | emith_call(sh2_drc_test_irq); |
2739 | emith_jump(sh2_drc_dispatcher); |
2740 | |
2741 | // write-caused irq detection |
2742 | sh2_drc_write_end = tcache_ptr; |
2743 | emith_tst_r_r(arg0, arg0); |
2744 | EMITH_SJMP_START(DCOND_NE); |
2745 | emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return |
2746 | EMITH_SJMP_END(DCOND_NE); |
e05b81fc |
2747 | emith_call(sh2_drc_test_irq); |
2748 | emith_jump_ctx(offsetof(SH2, drc_tmp)); |
2749 | |
2750 | // write-caused irq detection for writes in delay slot |
2751 | sh2_drc_write_slot_end = tcache_ptr; |
2752 | emith_tst_r_r(arg0, arg0); |
2753 | EMITH_SJMP_START(DCOND_NE); |
2754 | emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); |
2755 | EMITH_SJMP_END(DCOND_NE); |
2756 | // just burn cycles to get back to dispatcher after branch is handled |
2757 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
2758 | emith_ctx_write(sr, offsetof(SH2, irq_cycles)); |
2759 | emith_clear_msb(sr, sr, 20); // clear cycles |
2760 | rcache_flush(); |
2761 | emith_jump_ctx(offsetof(SH2, drc_tmp)); |
2762 | |
2763 | // sh2_drc_write8(u32 a, u32 d) |
2764 | sh2_drc_write8 = (void *)tcache_ptr; |
2765 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2766 | emith_ctx_read(arg2, offsetof(SH2, write8_tab)); |
2767 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); |
2768 | |
2769 | // sh2_drc_write16(u32 a, u32 d) |
2770 | sh2_drc_write16 = (void *)tcache_ptr; |
2771 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2772 | emith_ctx_read(arg2, offsetof(SH2, write16_tab)); |
2773 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); |
2774 | |
2775 | // sh2_drc_write8_slot(u32 a, u32 d) |
2776 | sh2_drc_write8_slot = (void *)tcache_ptr; |
2777 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2778 | emith_ctx_read(arg2, offsetof(SH2, write8_tab)); |
2779 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); |
2780 | |
2781 | // sh2_drc_write16_slot(u32 a, u32 d) |
2782 | sh2_drc_write16_slot = (void *)tcache_ptr; |
2783 | emith_ret_to_ctx(offsetof(SH2, drc_tmp)); |
2784 | emith_ctx_read(arg2, offsetof(SH2, write16_tab)); |
2785 | emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); |
2786 | |
5686d931 |
2787 | #ifdef PDB_NET |
2788 | // debug |
2789 | #define MAKE_READ_WRAPPER(func) { \ |
2790 | void *tmp = (void *)tcache_ptr; \ |
a2b8c5a5 |
2791 | emith_push_ret(); \ |
5686d931 |
2792 | emith_call(func); \ |
2793 | emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \ |
2794 | emith_addf_r_r(arg2, arg0); \ |
2795 | emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \ |
2796 | emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \ |
2797 | emith_adc_r_imm(arg2, 0x01000000); \ |
2798 | emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \ |
a2b8c5a5 |
2799 | emith_pop_and_ret(); \ |
5686d931 |
2800 | func = tmp; \ |
2801 | } |
2802 | #define MAKE_WRITE_WRAPPER(func) { \ |
2803 | void *tmp = (void *)tcache_ptr; \ |
2804 | emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \ |
2805 | emith_addf_r_r(arg2, arg1); \ |
2806 | emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \ |
2807 | emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \ |
2808 | emith_adc_r_imm(arg2, 0x01000000); \ |
2809 | emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \ |
2810 | emith_move_r_r(arg2, CONTEXT_REG); \ |
2811 | emith_jump(func); \ |
2812 | func = tmp; \ |
2813 | } |
2814 | |
2815 | MAKE_READ_WRAPPER(sh2_drc_read8); |
2816 | MAKE_READ_WRAPPER(sh2_drc_read16); |
2817 | MAKE_READ_WRAPPER(sh2_drc_read32); |
2818 | MAKE_WRITE_WRAPPER(sh2_drc_write8); |
2819 | MAKE_WRITE_WRAPPER(sh2_drc_write8_slot); |
2820 | MAKE_WRITE_WRAPPER(sh2_drc_write16); |
2821 | MAKE_WRITE_WRAPPER(sh2_drc_write16_slot); |
2822 | MAKE_WRITE_WRAPPER(sh2_drc_write32); |
2823 | #if (DRC_DEBUG & 2) |
2824 | host_dasm_new_symbol(sh2_drc_read8); |
2825 | host_dasm_new_symbol(sh2_drc_read16); |
2826 | host_dasm_new_symbol(sh2_drc_read32); |
2827 | host_dasm_new_symbol(sh2_drc_write32); |
2828 | #endif |
2829 | #endif |
2830 | |
e05b81fc |
2831 | rcache_invalidate(); |
2832 | #if (DRC_DEBUG & 2) |
2833 | host_dasm_new_symbol(sh2_drc_entry); |
2834 | host_dasm_new_symbol(sh2_drc_dispatcher); |
2835 | host_dasm_new_symbol(sh2_drc_exit); |
2836 | host_dasm_new_symbol(sh2_drc_test_irq); |
2837 | host_dasm_new_symbol(sh2_drc_write_end); |
2838 | host_dasm_new_symbol(sh2_drc_write_slot_end); |
2839 | host_dasm_new_symbol(sh2_drc_write8); |
2840 | host_dasm_new_symbol(sh2_drc_write8_slot); |
2841 | host_dasm_new_symbol(sh2_drc_write16); |
2842 | host_dasm_new_symbol(sh2_drc_write16_slot); |
679af8a3 |
2843 | #endif |
679af8a3 |
2844 | } |
2845 | |
a2b8c5a5 |
2846 | static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id) |
f4bb5d6b |
2847 | { |
a2b8c5a5 |
2848 | // XXX: kill links somehow? |
2849 | dbg(1, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]); |
2850 | bd->addr = 0; |
2851 | // since we never reuse space of dead blocks, |
2852 | // insert jump to dispatcher for blocks that are linked to this point |
2853 | emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher); |
2854 | return bd->tcache_ptr; |
2855 | } |
f4bb5d6b |
2856 | |
a2b8c5a5 |
2857 | static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask) |
2858 | { |
2859 | //block_link *bl = block_links[tcache_id]; |
2860 | //int bl_count = block_link_counts[tcache_id]; |
2861 | block_desc *btab = block_tables[tcache_id]; |
2862 | u16 *p = drc_ram_blk + ((a & mask) >> shift); |
2863 | u16 *pe = drc_ram_blk + (mask >> shift); |
2864 | void *tcache_min, *tcache_max; |
2865 | int main_id, prev_id = 0; |
2866 | |
2867 | while (p > drc_ram_blk && (*p & 1) == 0) |
f4bb5d6b |
2868 | p--; |
2869 | |
a2b8c5a5 |
2870 | if (!(*p & 1)) |
2871 | printf("smc rm: missing block start for %08x?\n", a); |
2872 | main_id = *p >> 1; |
2873 | tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[main_id], tcache_id); |
2874 | |
2875 | for (*p++ = 0; p <= pe && *p != 0 && !(*p & 1); p++) { |
2876 | int id = *p >> 1; |
2877 | if (id != main_id && id != prev_id) |
2878 | tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id); |
2879 | *p = 0; |
2880 | prev_id = id; |
f4bb5d6b |
2881 | } |
2882 | |
a2b8c5a5 |
2883 | host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4)); |
f4bb5d6b |
2884 | } |
2885 | |
2886 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
2887 | { |
f4bb5d6b |
2888 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
a2b8c5a5 |
2889 | sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff); |
f4bb5d6b |
2890 | } |
2891 | |
2892 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
2893 | { |
f4bb5d6b |
2894 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
a2b8c5a5 |
2895 | sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid], |
2896 | 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff); |
f4bb5d6b |
2897 | } |
2898 | |
52d759c3 |
2899 | void sh2_execute(SH2 *sh2c, int cycles) |
679af8a3 |
2900 | { |
e05b81fc |
2901 | int ret_cycles; |
52d759c3 |
2902 | sh2 = sh2c; // XXX |
2903 | |
2904 | sh2c->cycles_aim += cycles; |
2905 | cycles = sh2c->cycles_aim - sh2c->cycles_done; |
679af8a3 |
2906 | |
2907 | // cycles are kept in SHR_SR unused bits (upper 20) |
18b94127 |
2908 | // bit19 contains T saved for delay slot |
2909 | // others are usual SH2 flags |
52d759c3 |
2910 | sh2c->sr &= 0x3f3; |
2911 | sh2c->sr |= cycles << 12; |
e05b81fc |
2912 | sh2_drc_entry(sh2c); |
679af8a3 |
2913 | |
e05b81fc |
2914 | // TODO: irq cycles |
2915 | ret_cycles = (signed int)sh2c->sr >> 12; |
2916 | if (ret_cycles > 0) |
2917 | printf("warning: drc returned with cycles: %d\n", ret_cycles); |
679af8a3 |
2918 | |
e05b81fc |
2919 | sh2c->cycles_done += cycles - ret_cycles; |
679af8a3 |
2920 | } |
2921 | |
f4bb5d6b |
2922 | #if (DRC_DEBUG & 1) |
9bb5d91c |
2923 | void block_stats(void) |
f4bb5d6b |
2924 | { |
2925 | int c, b, i, total = 0; |
2926 | |
9bb5d91c |
2927 | printf("block stats:\n"); |
f4bb5d6b |
2928 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
2929 | for (i = 0; i < block_counts[b]; i++) |
2930 | if (block_tables[b][i].addr != 0) |
2931 | total += block_tables[b][i].refcount; |
2932 | |
2933 | for (c = 0; c < 10; c++) { |
2934 | block_desc *blk, *maxb = NULL; |
2935 | int max = 0; |
2936 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
2937 | for (i = 0; i < block_counts[b]; i++) { |
2938 | blk = &block_tables[b][i]; |
2939 | if (blk->addr != 0 && blk->refcount > max) { |
2940 | max = blk->refcount; |
2941 | maxb = blk; |
2942 | } |
2943 | } |
2944 | } |
2945 | if (maxb == NULL) |
2946 | break; |
2947 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
2948 | (double)maxb->refcount / total * 100.0); |
2949 | maxb->refcount = 0; |
2950 | } |
553c3eaa |
2951 | |
2952 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
2953 | for (i = 0; i < block_counts[b]; i++) |
2954 | block_tables[b][i].refcount = 0; |
f4bb5d6b |
2955 | } |
553c3eaa |
2956 | #else |
2957 | #define block_stats() |
f4bb5d6b |
2958 | #endif |
2959 | |
553c3eaa |
2960 | void sh2_drc_flush_all(void) |
2961 | { |
2962 | block_stats(); |
2963 | flush_tcache(0); |
2964 | flush_tcache(1); |
2965 | flush_tcache(2); |
2966 | } |
2967 | |
23686515 |
2968 | void sh2_drc_mem_setup(SH2 *sh2) |
2969 | { |
2970 | // fill the convenience pointers |
2971 | sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; |
2972 | sh2->p_da = Pico32xMem->data_array[sh2->is_slave]; |
2973 | sh2->p_sdram = Pico32xMem->sdram; |
2974 | sh2->p_rom = Pico.rom; |
2975 | } |
2976 | |
679af8a3 |
2977 | int sh2_drc_init(SH2 *sh2) |
2978 | { |
44e6452e |
2979 | int i; |
7f5a3fc1 |
2980 | |
44e6452e |
2981 | if (block_tables[0] == NULL) |
2982 | { |
2983 | for (i = 0; i < TCACHE_BUFFERS; i++) { |
2984 | block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0])); |
2985 | if (block_tables[i] == NULL) |
2986 | goto fail; |
2987 | // max 2 block links (exits) per block |
2988 | block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0])); |
2989 | if (block_links[i] == NULL) |
2990 | goto fail; |
2991 | } |
2992 | memset(block_counts, 0, sizeof(block_counts)); |
2993 | memset(block_link_counts, 0, sizeof(block_link_counts)); |
e898de13 |
2994 | |
44e6452e |
2995 | drc_cmn_init(); |
8796b7ee |
2996 | tcache_ptr = tcache; |
2997 | sh2_generate_utils(); |
a2b8c5a5 |
2998 | host_instructions_updated(tcache, tcache_ptr); |
8796b7ee |
2999 | |
8796b7ee |
3000 | tcache_bases[0] = tcache_ptrs[0] = tcache_ptr; |
44e6452e |
3001 | for (i = 1; i < ARRAY_SIZE(tcache_bases); i++) |
f4bb5d6b |
3002 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
f4bb5d6b |
3003 | |
553c3eaa |
3004 | // tmp |
3005 | PicoOpt |= POPT_DIS_VDP_FIFO; |
3006 | |
f4bb5d6b |
3007 | #if (DRC_DEBUG & 2) |
3008 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
3009 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
8796b7ee |
3010 | // disasm the utils |
3011 | tcache_dsm_ptrs[0] = tcache; |
3012 | do_host_disasm(0); |
f4bb5d6b |
3013 | #endif |
e898de13 |
3014 | #if (DRC_DEBUG & 1) |
3015 | hash_collisions = 0; |
3016 | #endif |
679af8a3 |
3017 | } |
3018 | |
f4bb5d6b |
3019 | if (hash_table == NULL) { |
3020 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
3021 | if (hash_table == NULL) |
44e6452e |
3022 | goto fail; |
f4bb5d6b |
3023 | } |
41397701 |
3024 | |
679af8a3 |
3025 | return 0; |
44e6452e |
3026 | |
3027 | fail: |
3028 | sh2_drc_finish(sh2); |
3029 | return -1; |
41397701 |
3030 | } |
3031 | |
e898de13 |
3032 | void sh2_drc_finish(SH2 *sh2) |
3033 | { |
44e6452e |
3034 | int i; |
3035 | |
f4bb5d6b |
3036 | if (block_tables[0] != NULL) { |
f4bb5d6b |
3037 | block_stats(); |
44e6452e |
3038 | |
3039 | for (i = 0; i < TCACHE_BUFFERS; i++) { |
3040 | #if (DRC_DEBUG & 2) |
3041 | printf("~~~ tcache %d\n", i); |
3042 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
3043 | tcache_ptr = tcache_ptrs[i]; |
3044 | do_host_disasm(i); |
3045 | #endif |
3046 | |
3047 | if (block_tables[i] != NULL) |
3048 | free(block_tables[i]); |
3049 | block_tables[i] = NULL; |
3050 | if (block_links[i] == NULL) |
3051 | free(block_links[i]); |
3052 | block_links[i] = NULL; |
3053 | } |
7f5a3fc1 |
3054 | |
3055 | drc_cmn_cleanup(); |
e898de13 |
3056 | } |
3057 | |
f4bb5d6b |
3058 | if (hash_table != NULL) { |
3059 | free(hash_table); |
3060 | hash_table = NULL; |
3061 | } |
e898de13 |
3062 | } |