be2c4208 |
1 | #include "../pico_int.h" |
2 | #include "../memory.h" |
3 | |
236990cf |
4 | #if 0 |
c987bb5c |
5 | #undef ash2_end_run |
6 | #undef SekEndRun |
7 | #define ash2_end_run(x) |
8 | #define SekEndRun(x) |
9 | #endif |
10 | |
be2c4208 |
11 | static const char str_mars[] = "MARS"; |
12 | |
974fdb5b |
13 | struct Pico32xMem *Pico32xMem; |
14 | |
5e49c3a8 |
15 | static void bank_switch(int b); |
16 | |
266c6afa |
17 | // poll detection |
4ea707e1 |
18 | #define POLL_THRESHOLD 6 |
19 | |
266c6afa |
20 | struct poll_det { |
be20816c |
21 | u32 addr, cycles, cyc_max; |
22 | int cnt, flag; |
266c6afa |
23 | }; |
b78efee2 |
24 | static struct poll_det m68k_poll, sh2_poll[2]; |
266c6afa |
25 | |
be20816c |
26 | static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp) |
266c6afa |
27 | { |
b78efee2 |
28 | int ret = 0, flag = pd->flag; |
29 | |
30 | if (is_vdp) |
31 | flag <<= 3; |
266c6afa |
32 | |
1d7a28a7 |
33 | if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) { |
266c6afa |
34 | pd->cnt++; |
35 | if (pd->cnt > POLL_THRESHOLD) { |
36 | if (!(Pico32x.emu_flags & flag)) { |
be20816c |
37 | elprintf(EL_32X, "%s poll addr %08x, cyc %u", |
38 | flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" : |
39 | (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles); |
266c6afa |
40 | ret = 1; |
41 | } |
42 | Pico32x.emu_flags |= flag; |
43 | } |
44 | } |
c987bb5c |
45 | else { |
266c6afa |
46 | pd->cnt = 0; |
c987bb5c |
47 | pd->addr = a; |
48 | } |
be20816c |
49 | pd->cycles = cycles; |
266c6afa |
50 | |
51 | return ret; |
52 | } |
53 | |
b78efee2 |
54 | static int p32x_poll_undetect(struct poll_det *pd, int is_vdp) |
266c6afa |
55 | { |
b78efee2 |
56 | int ret = 0, flag = pd->flag; |
57 | if (is_vdp) |
be20816c |
58 | flag <<= 3; // VDP only |
59 | else |
60 | flag |= flag << 3; // both |
61 | if (Pico32x.emu_flags & flag) { |
62 | elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag); |
266c6afa |
63 | ret = 1; |
be20816c |
64 | } |
266c6afa |
65 | Pico32x.emu_flags &= ~flag; |
be20816c |
66 | pd->addr = pd->cnt = 0; |
266c6afa |
67 | return ret; |
68 | } |
69 | |
87accdf7 |
70 | void p32x_poll_event(int cpu_mask, int is_vdp) |
4ea707e1 |
71 | { |
87accdf7 |
72 | if (cpu_mask & 1) |
73 | p32x_poll_undetect(&sh2_poll[0], is_vdp); |
74 | if (cpu_mask & 2) |
75 | p32x_poll_undetect(&sh2_poll[1], is_vdp); |
4ea707e1 |
76 | } |
77 | |
974fdb5b |
78 | // SH2 faking |
b78efee2 |
79 | //#define FAKE_SH2 |
acd35d4c |
80 | int p32x_csum_faked; |
81 | #ifdef FAKE_SH2 |
974fdb5b |
82 | static const u16 comm_fakevals[] = { |
83 | 0x4d5f, 0x4f4b, // M_OK |
84 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
85 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
86 | 0x5331, 0x4d31, // Darxide |
87 | 0x5332, 0x4d32, |
88 | 0x5333, 0x4d33, |
89 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
90 | 0x0002, // Mortal Kombat |
acd35d4c |
91 | // 0, // pad |
be2c4208 |
92 | }; |
acd35d4c |
93 | |
94 | static u32 sh2_comm_faker(u32 a) |
95 | { |
96 | static int f = 0; |
97 | if (a == 0x28 && !p32x_csum_faked) { |
98 | p32x_csum_faked = 1; |
99 | return *(unsigned short *)(Pico.rom + 0x18e); |
100 | } |
101 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
102 | f = 0; |
103 | return comm_fakevals[f++]; |
104 | } |
105 | #endif |
be2c4208 |
106 | |
4ea707e1 |
107 | // DMAC handling |
108 | static struct { |
109 | unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count |
110 | unsigned int chcr0; // chan ctl |
111 | unsigned int sar1, dar1, tcr1; // same for chan 1 |
112 | unsigned int chcr1; |
113 | int pad[4]; |
114 | unsigned int dmaor; |
115 | } * dmac0; |
116 | |
117 | static void dma_68k2sh2_do(void) |
118 | { |
119 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
120 | int i; |
121 | |
122 | if (dmac0->tcr0 != *dreqlen) |
123 | elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); |
124 | |
1b3f5844 |
125 | // HACK: assume bus is busy and SH2 is halted |
126 | // XXX: use different mechanism for this, not poll det |
127 | Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL; |
128 | |
4ea707e1 |
129 | for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { |
b78efee2 |
130 | extern void p32x_sh2_write16(u32 a, u32 d, int id); |
be20816c |
131 | elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); |
b78efee2 |
132 | p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0); |
4ea707e1 |
133 | dmac0->dar0 += 2; |
134 | dmac0->tcr0--; |
135 | (*dreqlen)--; |
136 | } |
137 | |
138 | Pico32x.dmac_ptr = 0; // HACK |
139 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
140 | if (*dreqlen == 0) |
141 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
be20816c |
142 | if (dmac0->tcr0 == 0) { |
4ea707e1 |
143 | dmac0->chcr0 |= 2; // DMA has ended normally |
be20816c |
144 | p32x_poll_undetect(&sh2_poll[0], 0); |
145 | } |
4ea707e1 |
146 | } |
147 | |
148 | // ------------------------------------------------------------------ |
b78efee2 |
149 | // 68k regs |
4ea707e1 |
150 | |
be2c4208 |
151 | static u32 p32x_reg_read16(u32 a) |
152 | { |
153 | a &= 0x3e; |
154 | |
87accdf7 |
155 | if (a == 2) // INTM, INTS |
156 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
3cf9570b |
157 | #if 0 |
974fdb5b |
158 | if ((a & 0x30) == 0x20) |
acd35d4c |
159 | return sh2_comm_faker(a); |
266c6afa |
160 | #else |
5fadfb1c |
161 | if ((a & 0x30) == 0x20) { |
162 | // evil X-Men proto polls in a dbra loop and expects it to expire.. |
163 | static u32 dr2 = 0; |
164 | if (SekDar(2) != dr2) |
165 | m68k_poll.cnt = 0; |
166 | dr2 = SekDar(2); |
167 | |
168 | if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) { |
169 | SekSetStop(1); |
170 | SekEndTimeslice(16); |
171 | } |
172 | dr2 = SekDar(2); |
266c6afa |
173 | } |
acd35d4c |
174 | #endif |
87accdf7 |
175 | |
db1d3564 |
176 | if ((a & 0x30) == 0x30) |
177 | return p32x_pwm_read16(a); |
974fdb5b |
178 | |
be2c4208 |
179 | return Pico32x.regs[a / 2]; |
180 | } |
181 | |
be2c4208 |
182 | static void p32x_reg_write8(u32 a, u32 d) |
183 | { |
acd35d4c |
184 | u16 *r = Pico32x.regs; |
be2c4208 |
185 | a &= 0x3f; |
186 | |
97d3f47f |
187 | // for things like bset on comm port |
188 | m68k_poll.cnt = 0; |
189 | |
acd35d4c |
190 | if (a == 1 && !(r[0] & 1)) { |
191 | r[0] |= 1; |
be2c4208 |
192 | Pico32xStartup(); |
193 | return; |
194 | } |
5e49c3a8 |
195 | |
acd35d4c |
196 | if (!(r[0] & 1)) |
5e49c3a8 |
197 | return; |
198 | |
acd35d4c |
199 | switch (a) { |
4ea707e1 |
200 | case 0: // adapter ctl |
acd35d4c |
201 | r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); |
1b3f5844 |
202 | return; |
4ea707e1 |
203 | case 3: // irq ctl |
204 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
205 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
206 | p32x_update_irls(); |
87accdf7 |
207 | SekEndRun(16); |
4ea707e1 |
208 | } |
b78efee2 |
209 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
210 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
211 | p32x_update_irls(); |
87accdf7 |
212 | SekEndRun(16); |
b78efee2 |
213 | } |
1b3f5844 |
214 | return; |
4ea707e1 |
215 | case 5: // bank |
acd35d4c |
216 | d &= 7; |
4ea707e1 |
217 | if (r[4 / 2] != d) { |
218 | r[4 / 2] = d; |
acd35d4c |
219 | bank_switch(d); |
220 | } |
1b3f5844 |
221 | return; |
4ea707e1 |
222 | case 7: // DREQ ctl |
97d3f47f |
223 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
1b3f5844 |
224 | return; |
87accdf7 |
225 | case 0x1b: // TV |
226 | r[0x1a / 2] = d; |
1b3f5844 |
227 | return; |
228 | } |
229 | |
230 | if ((a & 0x30) == 0x20) { |
231 | u8 *r8 = (u8 *)r; |
232 | r8[a ^ 1] = d; |
236990cf |
233 | p32x_poll_undetect(&sh2_poll[0], 0); |
234 | p32x_poll_undetect(&sh2_poll[1], 0); |
235 | // if some SH2 is busy waiting, it needs to see the result ASAP |
236 | if (SekCyclesLeftNoMCD > 32) |
237 | SekEndRun(32); |
1b3f5844 |
238 | return; |
5e49c3a8 |
239 | } |
240 | } |
241 | |
242 | static void p32x_reg_write16(u32 a, u32 d) |
243 | { |
acd35d4c |
244 | u16 *r = Pico32x.regs; |
245 | a &= 0x3e; |
246 | |
97d3f47f |
247 | // for things like bset on comm port |
248 | m68k_poll.cnt = 0; |
249 | |
acd35d4c |
250 | switch (a) { |
4ea707e1 |
251 | case 0x00: // adapter ctl |
acd35d4c |
252 | r[0] = (r[0] & 0x83) | (d & P32XS_FM); |
253 | return; |
4ea707e1 |
254 | case 0x10: // DREQ len |
255 | r[a / 2] = d & ~3; |
256 | return; |
257 | case 0x12: // FIFO reg |
258 | if (!(r[6 / 2] & P32XS_68S)) { |
259 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
260 | return; |
261 | } |
262 | if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) { |
263 | Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d; |
264 | if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) |
265 | dma_68k2sh2_do(); |
266 | if (Pico32x.dmac_ptr == DMAC_FIFO_LEN) |
267 | r[6 / 2] |= P32XS_FULL; |
268 | } |
269 | break; |
acd35d4c |
270 | } |
271 | |
4ea707e1 |
272 | // DREQ src, dst |
273 | if ((a & 0x38) == 0x08) { |
274 | r[a / 2] = d; |
275 | return; |
276 | } |
277 | // comm port |
278 | else if ((a & 0x30) == 0x20 && r[a / 2] != d) { |
acd35d4c |
279 | r[a / 2] = d; |
236990cf |
280 | p32x_poll_undetect(&sh2_poll[0], 0); |
281 | p32x_poll_undetect(&sh2_poll[1], 0); |
282 | // same as for w8 |
283 | if (SekCyclesLeftNoMCD > 32) |
284 | SekEndRun(32); |
acd35d4c |
285 | return; |
286 | } |
db1d3564 |
287 | // PWM |
288 | else if ((a & 0x30) == 0x30) { |
289 | p32x_pwm_write16(a, d); |
290 | return; |
291 | } |
acd35d4c |
292 | |
5e49c3a8 |
293 | p32x_reg_write8(a + 1, d); |
be2c4208 |
294 | } |
295 | |
4ea707e1 |
296 | // ------------------------------------------------------------------ |
be2c4208 |
297 | // VDP regs |
298 | static u32 p32x_vdp_read16(u32 a) |
299 | { |
300 | a &= 0x0e; |
301 | |
302 | return Pico32x.vdp_regs[a / 2]; |
303 | } |
304 | |
be2c4208 |
305 | static void p32x_vdp_write8(u32 a, u32 d) |
306 | { |
974fdb5b |
307 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
308 | a &= 0x0f; |
309 | |
4ea707e1 |
310 | // for FEN checks between writes |
b78efee2 |
311 | sh2_poll[0].cnt = 0; |
4ea707e1 |
312 | |
974fdb5b |
313 | // TODO: verify what's writeable |
be2c4208 |
314 | switch (a) { |
974fdb5b |
315 | case 0x01: |
5e49c3a8 |
316 | // priority inversion is handled in palette |
317 | if ((r[0] ^ d) & P32XV_PRI) |
318 | Pico32x.dirty_pal = 1; |
974fdb5b |
319 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
320 | break; |
321 | case 0x05: // fill len |
322 | r[4 / 2] = d & 0xff; |
974fdb5b |
323 | break; |
be2c4208 |
324 | case 0x0b: |
974fdb5b |
325 | d &= 1; |
326 | Pico32x.pending_fb = d; |
327 | // if we are blanking and FS bit is changing |
4ea707e1 |
328 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
974fdb5b |
329 | r[0x0a/2] ^= 1; |
330 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
331 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
332 | } |
333 | break; |
334 | } |
335 | } |
336 | |
974fdb5b |
337 | static void p32x_vdp_write16(u32 a, u32 d) |
338 | { |
be20816c |
339 | a &= 0x0e; |
340 | if (a == 6) { // fill start |
341 | Pico32x.vdp_regs[6 / 2] = d; |
342 | return; |
343 | } |
344 | if (a == 8) { // fill data |
345 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
346 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
be20816c |
347 | a = Pico32x.vdp_regs[6 / 2]; |
348 | while (len--) { |
349 | dram[a] = d; |
350 | a = (a & 0xff00) | ((a + 1) & 0xff); |
351 | } |
352 | Pico32x.vdp_regs[6 / 2] = a; |
353 | Pico32x.vdp_regs[8 / 2] = d; |
354 | return; |
355 | } |
356 | |
974fdb5b |
357 | p32x_vdp_write8(a | 1, d); |
358 | } |
359 | |
4ea707e1 |
360 | // ------------------------------------------------------------------ |
acd35d4c |
361 | // SH2 regs |
b78efee2 |
362 | |
363 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
364 | { |
4ea707e1 |
365 | u16 *r = Pico32x.regs; |
366 | a &= 0xfe; // ? |
266c6afa |
367 | |
4ea707e1 |
368 | switch (a) { |
369 | case 0x00: // adapter/irq ctl |
87accdf7 |
370 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; |
c987bb5c |
371 | case 0x04: // H count (often as comm too) |
372 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
373 | ash2_end_run(8); |
87accdf7 |
374 | return Pico32x.sh2_regs[4 / 2]; |
4ea707e1 |
375 | case 0x10: // DREQ len |
376 | return r[a / 2]; |
acd35d4c |
377 | } |
4ea707e1 |
378 | |
db1d3564 |
379 | // DREQ src, dst |
380 | if ((a & 0x38) == 0x08) |
4ea707e1 |
381 | return r[a / 2]; |
db1d3564 |
382 | // comm port |
383 | if ((a & 0x30) == 0x20) { |
be20816c |
384 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
db1d3564 |
385 | ash2_end_run(8); |
386 | return r[a / 2]; |
387 | } |
388 | if ((a & 0x30) == 0x30) { |
389 | sh2_poll[cpuid].cnt = 0; |
390 | return p32x_pwm_read16(a); |
391 | } |
acd35d4c |
392 | |
393 | return 0; |
394 | } |
395 | |
b78efee2 |
396 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
397 | { |
4ea707e1 |
398 | a &= 0xff; |
87accdf7 |
399 | switch (a) { |
400 | case 0: // FM |
401 | Pico32x.regs[0] &= ~P32XS_FM; |
402 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
403 | return; |
87accdf7 |
404 | case 1: // |
405 | Pico32x.sh2irq_mask[cpuid] = d & 0x8f; |
406 | Pico32x.sh2_regs[0] &= ~0x80; |
407 | Pico32x.sh2_regs[0] |= d & 0x80; |
408 | p32x_update_irls(); |
1b3f5844 |
409 | return; |
87accdf7 |
410 | case 5: // H count |
411 | Pico32x.sh2_regs[4 / 2] = d & 0xff; |
c987bb5c |
412 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
1b3f5844 |
413 | return; |
414 | } |
415 | |
416 | if ((a & 0x30) == 0x20) { |
417 | u8 *r8 = (u8 *)Pico32x.regs; |
418 | r8[a ^ 1] = d; |
5fadfb1c |
419 | if (p32x_poll_undetect(&m68k_poll, 0)) |
420 | SekSetStop(0); |
1b3f5844 |
421 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
422 | return; |
4ea707e1 |
423 | } |
acd35d4c |
424 | } |
425 | |
b78efee2 |
426 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
427 | { |
4ea707e1 |
428 | a &= 0xfe; |
acd35d4c |
429 | |
db1d3564 |
430 | // comm |
4ea707e1 |
431 | if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) { |
b78efee2 |
432 | Pico32x.regs[a / 2] = d; |
5fadfb1c |
433 | if (p32x_poll_undetect(&m68k_poll, 0)) |
434 | SekSetStop(0); |
b78efee2 |
435 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
acd35d4c |
436 | return; |
437 | } |
db1d3564 |
438 | // PWM |
439 | else if ((a & 0x30) == 0x30) { |
440 | p32x_pwm_write16(a, d); |
441 | return; |
442 | } |
acd35d4c |
443 | |
4ea707e1 |
444 | switch (a) { |
87accdf7 |
445 | case 0: // FM |
446 | Pico32x.regs[0] &= ~P32XS_FM; |
447 | Pico32x.regs[0] |= d & P32XS_FM; |
448 | break; |
4ea707e1 |
449 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
450 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
451 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
452 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
be20816c |
453 | case 0x1c: |
454 | Pico32x.sh2irqs &= ~P32XI_PWM; |
1d7a28a7 |
455 | p32x_timers_do(0); |
be20816c |
456 | goto irls; |
4ea707e1 |
457 | } |
458 | |
b78efee2 |
459 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
460 | return; |
461 | |
462 | irls: |
463 | p32x_update_irls(); |
464 | } |
465 | |
87accdf7 |
466 | // ------------------------------------------------------------------ |
467 | // SH2 internal peripherals |
1d7a28a7 |
468 | // we keep them in little endian format |
87accdf7 |
469 | static u32 sh2_peripheral_read8(u32 a, int id) |
470 | { |
471 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
472 | u32 d; |
473 | |
474 | a &= 0x1ff; |
1d7a28a7 |
475 | d = PREG8(r, a); |
87accdf7 |
476 | |
477 | elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
478 | return d; |
479 | } |
480 | |
1d7a28a7 |
481 | static u32 sh2_peripheral_read16(u32 a, int id) |
482 | { |
483 | u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
484 | u32 d; |
485 | |
486 | a &= 0x1ff; |
487 | d = r[(a / 2) ^ 1]; |
488 | |
489 | elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
490 | return d; |
491 | } |
492 | |
87accdf7 |
493 | static u32 sh2_peripheral_read32(u32 a, int id) |
4ea707e1 |
494 | { |
495 | u32 d; |
496 | a &= 0x1fc; |
97d3f47f |
497 | d = Pico32xMem->sh2_peri_regs[id][a / 4]; |
4ea707e1 |
498 | |
97d3f47f |
499 | elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
4ea707e1 |
500 | return d; |
acd35d4c |
501 | } |
502 | |
87accdf7 |
503 | static void sh2_peripheral_write8(u32 a, u32 d, int id) |
504 | { |
505 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
506 | elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
507 | |
508 | a &= 0x1ff; |
1d7a28a7 |
509 | PREG8(r, a) = d; |
510 | |
511 | // X-men SCI hack |
512 | if ((a == 2 && (d & 0x20)) || // transmiter enabled |
513 | (a == 4 && !(d & 0x80))) { // valid data in TDR |
514 | void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1]; |
515 | if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled |
516 | int level = PREG8(oregs, 0x60) >> 4; |
517 | int vector = PREG8(oregs, 0x63) & 0x7f; |
518 | elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector); |
519 | sh2_internal_irq(&sh2s[id ^ 1], level, vector); |
520 | } |
521 | } |
522 | } |
523 | |
524 | static void sh2_peripheral_write16(u32 a, u32 d, int id) |
525 | { |
526 | u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
527 | elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
528 | |
529 | a &= 0x1ff; |
530 | |
531 | // evil WDT |
532 | if (a == 0x80) { |
533 | if ((d & 0xff00) == 0xa500) { // WTCSR |
534 | PREG8(r, 0x80) = d; |
535 | p32x_timers_recalc(); |
536 | } |
537 | if ((d & 0xff00) == 0x5a00) // WTCNT |
538 | PREG8(r, 0x81) = d; |
539 | return; |
540 | } |
541 | |
542 | r[(a / 2) ^ 1] = d; |
87accdf7 |
543 | } |
544 | |
545 | static void sh2_peripheral_write32(u32 a, u32 d, int id) |
4ea707e1 |
546 | { |
be20816c |
547 | u32 *r = Pico32xMem->sh2_peri_regs[id]; |
b78efee2 |
548 | elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
4ea707e1 |
549 | |
550 | a &= 0x1fc; |
551 | r[a / 4] = d; |
552 | |
97d3f47f |
553 | switch (a) { |
be20816c |
554 | // division unit (TODO: verify): |
97d3f47f |
555 | case 0x104: // DVDNT: divident L, starts divide |
556 | elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); |
557 | if (r[0x100 / 4]) { |
be20816c |
558 | signed int divisor = r[0x100 / 4]; |
559 | r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; |
560 | r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; |
97d3f47f |
561 | } |
562 | break; |
563 | case 0x114: |
564 | elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", |
565 | id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); |
566 | if (r[0x100 / 4]) { |
be20816c |
567 | signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; |
568 | signed int divisor = r[0x100 / 4]; |
97d3f47f |
569 | // XXX: undocumented mirroring to 0x118,0x11c? |
be20816c |
570 | r[0x118 / 4] = r[0x110 / 4] = divident % divisor; |
571 | r[0x11c / 4] = r[0x114 / 4] = divident / divisor; |
97d3f47f |
572 | } |
573 | break; |
574 | } |
575 | |
4ea707e1 |
576 | if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) { |
577 | elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x", |
b78efee2 |
578 | dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); |
4ea707e1 |
579 | dmac0->tcr0 &= 0xffffff; |
be20816c |
580 | |
1b3f5844 |
581 | // HACK: assume 68k starts writing soon and end the timeslice |
582 | ash2_end_run(16); |
be20816c |
583 | |
4ea707e1 |
584 | // DREQ is only sent after first 4 words are written. |
585 | // we do multiple of 4 words to avoid messing up alignment |
586 | if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) { |
587 | elprintf(EL_32X, "68k -> sh2 DMA"); |
588 | dma_68k2sh2_do(); |
589 | } |
590 | } |
591 | } |
592 | |
593 | // ------------------------------------------------------------------ |
be2c4208 |
594 | // default 32x handlers |
595 | u32 PicoRead8_32x(u32 a) |
596 | { |
597 | u32 d = 0; |
598 | if ((a & 0xffc0) == 0x5100) { // a15100 |
599 | d = p32x_reg_read16(a); |
600 | goto out_16to8; |
601 | } |
602 | |
974fdb5b |
603 | if (!(Pico32x.regs[0] & 1)) |
604 | goto no_vdp; |
605 | |
606 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
607 | d = p32x_vdp_read16(a); |
608 | goto out_16to8; |
609 | } |
610 | |
974fdb5b |
611 | if ((a & 0xfe00) == 0x5200) { // a15200 |
612 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
613 | goto out_16to8; |
614 | } |
615 | |
616 | no_vdp: |
be2c4208 |
617 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
618 | d = str_mars[a & 3]; |
619 | goto out; |
620 | } |
621 | |
622 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
623 | return d; |
624 | |
625 | out_16to8: |
626 | if (a & 1) |
627 | d &= 0xff; |
628 | else |
629 | d >>= 8; |
630 | |
631 | out: |
632 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
633 | return d; |
634 | } |
635 | |
636 | u32 PicoRead16_32x(u32 a) |
637 | { |
638 | u32 d = 0; |
639 | if ((a & 0xffc0) == 0x5100) { // a15100 |
640 | d = p32x_reg_read16(a); |
641 | goto out; |
642 | } |
643 | |
974fdb5b |
644 | if (!(Pico32x.regs[0] & 1)) |
645 | goto no_vdp; |
646 | |
647 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
648 | d = p32x_vdp_read16(a); |
649 | goto out; |
650 | } |
651 | |
974fdb5b |
652 | if ((a & 0xfe00) == 0x5200) { // a15200 |
653 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
654 | goto out; |
655 | } |
656 | |
657 | no_vdp: |
be2c4208 |
658 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
659 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
660 | goto out; |
661 | } |
662 | |
663 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
664 | return d; |
665 | |
666 | out: |
667 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
668 | return d; |
669 | } |
670 | |
671 | void PicoWrite8_32x(u32 a, u32 d) |
672 | { |
673 | if ((a & 0xfc00) == 0x5000) |
674 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
675 | |
676 | if ((a & 0xffc0) == 0x5100) { // a15100 |
677 | p32x_reg_write8(a, d); |
678 | return; |
679 | } |
680 | |
974fdb5b |
681 | if (!(Pico32x.regs[0] & 1)) |
682 | goto no_vdp; |
683 | |
684 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
685 | p32x_vdp_write8(a, d); |
686 | return; |
687 | } |
688 | |
974fdb5b |
689 | // TODO: verify |
690 | if ((a & 0xfe00) == 0x5200) { // a15200 |
691 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
692 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
693 | Pico32x.dirty_pal = 1; |
694 | return; |
695 | } |
696 | |
697 | no_vdp: |
be2c4208 |
698 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
699 | } |
700 | |
701 | void PicoWrite16_32x(u32 a, u32 d) |
702 | { |
703 | if ((a & 0xfc00) == 0x5000) |
704 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
705 | |
706 | if ((a & 0xffc0) == 0x5100) { // a15100 |
707 | p32x_reg_write16(a, d); |
708 | return; |
709 | } |
710 | |
974fdb5b |
711 | if (!(Pico32x.regs[0] & 1)) |
712 | goto no_vdp; |
713 | |
714 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
715 | p32x_vdp_write16(a, d); |
716 | return; |
717 | } |
718 | |
974fdb5b |
719 | if ((a & 0xfe00) == 0x5200) { // a15200 |
720 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
721 | Pico32x.dirty_pal = 1; |
722 | return; |
723 | } |
724 | |
725 | no_vdp: |
be2c4208 |
726 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
727 | } |
728 | |
729 | // hint vector is writeable |
730 | static void PicoWrite8_hint(u32 a, u32 d) |
731 | { |
732 | if ((a & 0xfffc) == 0x0070) { |
733 | Pico32xMem->m68k_rom[a ^ 1] = d; |
734 | return; |
735 | } |
736 | |
737 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
738 | } |
739 | |
740 | static void PicoWrite16_hint(u32 a, u32 d) |
741 | { |
742 | if ((a & 0xfffc) == 0x0070) { |
743 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
744 | return; |
745 | } |
746 | |
747 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
748 | } |
749 | |
974fdb5b |
750 | void Pico32xSwapDRAM(int b) |
751 | { |
752 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
753 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
754 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
755 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
756 | } |
757 | |
5e49c3a8 |
758 | static void bank_switch(int b) |
759 | { |
760 | unsigned int rs, bank; |
761 | |
762 | bank = b << 20; |
763 | if (bank >= Pico.romsize) { |
764 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
765 | return; |
766 | } |
767 | |
768 | // 32X ROM (unbanked, XXX: consider mirroring?) |
769 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
770 | rs -= bank; |
771 | if (rs > 0x100000) |
772 | rs = 0x100000; |
773 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
774 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
775 | |
776 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
777 | } |
778 | |
acd35d4c |
779 | // ----------------------------------------------------------------- |
780 | // SH2 |
781 | // ----------------------------------------------------------------- |
782 | |
b78efee2 |
783 | u32 p32x_sh2_read8(u32 a, int id) |
acd35d4c |
784 | { |
785 | u32 d = 0; |
4ea707e1 |
786 | |
b78efee2 |
787 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
788 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
b78efee2 |
789 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
790 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
acd35d4c |
791 | |
87accdf7 |
792 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
793 | return Pico32xMem->sdram[(a & 0x3ffff) ^ 1]; |
794 | |
87accdf7 |
795 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
796 | if ((a & 0x003fffff) < Pico.romsize) |
797 | return Pico.rom[(a & 0x3fffff) ^ 1]; |
798 | |
b78efee2 |
799 | if ((a & ~0xfff) == 0xc0000000) |
800 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
801 | |
c987bb5c |
802 | if ((a & 0xdffc0000) == 0x04000000) { |
803 | /* XXX: overwrite readable as normal? */ |
97d3f47f |
804 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
805 | return dram[(a & 0x1ffff) ^ 1]; |
806 | } |
807 | |
87accdf7 |
808 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
809 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
810 | goto out_16to8; |
acd35d4c |
811 | } |
812 | |
87accdf7 |
813 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
814 | d = p32x_vdp_read16(a); |
be20816c |
815 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
816 | ash2_end_run(8); |
817 | goto out_16to8; |
acd35d4c |
818 | } |
819 | |
87accdf7 |
820 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
821 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
822 | goto out_16to8; |
823 | } |
824 | |
87accdf7 |
825 | if ((a & 0xfffffe00) == 0xfffffe00) |
826 | return sh2_peripheral_read8(a, id); |
827 | |
b78efee2 |
828 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
829 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
830 | return d; |
831 | |
832 | out_16to8: |
833 | if (a & 1) |
834 | d &= 0xff; |
835 | else |
836 | d >>= 8; |
837 | |
b78efee2 |
838 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
839 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
840 | return d; |
841 | } |
842 | |
b78efee2 |
843 | u32 p32x_sh2_read16(u32 a, int id) |
acd35d4c |
844 | { |
845 | u32 d = 0; |
3cf9570b |
846 | |
b78efee2 |
847 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
848 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
b78efee2 |
849 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
850 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
acd35d4c |
851 | |
87accdf7 |
852 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
853 | return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2]; |
854 | |
87accdf7 |
855 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
856 | if ((a & 0x003fffff) < Pico.romsize) |
857 | return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2]; |
858 | |
b78efee2 |
859 | if ((a & ~0xfff) == 0xc0000000) |
860 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
861 | |
87accdf7 |
862 | if ((a & 0xdffe0000) == 0x04000000) |
97d3f47f |
863 | return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
864 | |
87accdf7 |
865 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
866 | d = p32x_sh2reg_read16(a, id); |
1b3f5844 |
867 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
868 | return d; |
db1d3564 |
869 | goto out; |
acd35d4c |
870 | } |
871 | |
87accdf7 |
872 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
873 | d = p32x_vdp_read16(a); |
be20816c |
874 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
875 | ash2_end_run(8); |
876 | goto out; |
acd35d4c |
877 | } |
878 | |
87accdf7 |
879 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
880 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
881 | goto out; |
882 | } |
883 | |
1d7a28a7 |
884 | if ((a & 0xfffffe00) == 0xfffffe00) |
885 | return sh2_peripheral_read16(a, id); |
886 | |
b78efee2 |
887 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
888 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
889 | return d; |
890 | |
891 | out: |
b78efee2 |
892 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
893 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
894 | return d; |
895 | } |
896 | |
b78efee2 |
897 | u32 p32x_sh2_read32(u32 a, int id) |
acd35d4c |
898 | { |
4ea707e1 |
899 | if ((a & 0xfffffe00) == 0xfffffe00) |
87accdf7 |
900 | return sh2_peripheral_read32(a, id); |
4ea707e1 |
901 | |
acd35d4c |
902 | // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc()); |
b78efee2 |
903 | return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id); |
acd35d4c |
904 | } |
905 | |
b78efee2 |
906 | void p32x_sh2_write8(u32 a, u32 d, int id) |
acd35d4c |
907 | { |
87accdf7 |
908 | if ((a & 0xdffffc00) == 0x4000) |
b78efee2 |
909 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
910 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
911 | |
87accdf7 |
912 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
913 | Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d; |
914 | return; |
915 | } |
916 | |
87accdf7 |
917 | if ((a & 0xdffc0000) == 0x04000000) { |
918 | u8 *dram; |
919 | if (!(a & 0x20000) || d) { |
920 | dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
921 | dram[(a & 0x1ffff) ^ 1] = d; |
87accdf7 |
922 | } |
c987bb5c |
923 | return; |
266c6afa |
924 | } |
925 | |
b78efee2 |
926 | if ((a & ~0xfff) == 0xc0000000) { |
927 | Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; |
928 | return; |
929 | } |
930 | |
87accdf7 |
931 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
932 | p32x_vdp_write8(a, d); |
933 | return; |
934 | } |
935 | |
87accdf7 |
936 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
937 | p32x_sh2reg_write8(a, d, id); |
acd35d4c |
938 | return; |
939 | } |
940 | |
87accdf7 |
941 | if ((a & 0xfffffe00) == 0xfffffe00) { |
942 | sh2_peripheral_write8(a, d, id); |
943 | return; |
944 | } |
945 | |
b78efee2 |
946 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
947 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
948 | } |
949 | |
b78efee2 |
950 | void p32x_sh2_write16(u32 a, u32 d, int id) |
acd35d4c |
951 | { |
1b3f5844 |
952 | if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
b78efee2 |
953 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
954 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
955 | |
87accdf7 |
956 | // ignore "Associative purge space" |
957 | if ((a & 0xf8000000) == 0x40000000) |
958 | return; |
959 | |
960 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
961 | ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d; |
962 | return; |
963 | } |
964 | |
b78efee2 |
965 | if ((a & ~0xfff) == 0xc0000000) { |
966 | ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; |
967 | return; |
968 | } |
969 | |
87accdf7 |
970 | if ((a & 0xdffc0000) == 0x04000000) { |
971 | u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
972 | if (!(a & 0x20000)) { |
973 | *pd = d; |
974 | return; |
975 | } |
976 | // overwrite |
977 | if (!(d & 0xff00)) d |= *pd & 0xff00; |
978 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; |
979 | *pd = d; |
266c6afa |
980 | return; |
981 | } |
982 | |
87accdf7 |
983 | if ((a & 0xdfffff00) == 0x4100) { |
be20816c |
984 | sh2_poll[id].cnt = 0; // for poll before VDP accesses |
acd35d4c |
985 | p32x_vdp_write16(a, d); |
986 | return; |
987 | } |
988 | |
87accdf7 |
989 | if ((a & 0xdffffe00) == 0x4200) { |
acd35d4c |
990 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
991 | Pico32x.dirty_pal = 1; |
992 | return; |
993 | } |
994 | |
87accdf7 |
995 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
996 | p32x_sh2reg_write16(a, d, id); |
acd35d4c |
997 | return; |
998 | } |
999 | |
1d7a28a7 |
1000 | if ((a & 0xfffffe00) == 0xfffffe00) { |
1001 | sh2_peripheral_write16(a, d, id); |
1002 | return; |
1003 | } |
1004 | |
b78efee2 |
1005 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
1006 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
1007 | } |
1008 | |
b78efee2 |
1009 | void p32x_sh2_write32(u32 a, u32 d, int id) |
acd35d4c |
1010 | { |
4ea707e1 |
1011 | if ((a & 0xfffffe00) == 0xfffffe00) { |
87accdf7 |
1012 | sh2_peripheral_write32(a, d, id); |
4ea707e1 |
1013 | return; |
1014 | } |
1015 | |
b78efee2 |
1016 | p32x_sh2_write16(a, d >> 16, id); |
1017 | p32x_sh2_write16(a + 2, d, id); |
acd35d4c |
1018 | } |
1019 | |
be2c4208 |
1020 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
1021 | void PicoMemSetup32x(void) |
1022 | { |
1023 | unsigned short *ps; |
1024 | unsigned int *pl; |
5e49c3a8 |
1025 | unsigned int rs; |
be2c4208 |
1026 | int i; |
1027 | |
1028 | Pico32xMem = calloc(1, sizeof(*Pico32xMem)); |
1029 | if (Pico32xMem == NULL) { |
1030 | elprintf(EL_STATUS, "OOM"); |
1031 | return; |
1032 | } |
1033 | |
4ea707e1 |
1034 | dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; |
1035 | |
be2c4208 |
1036 | // generate 68k ROM |
1037 | ps = (unsigned short *)Pico32xMem->m68k_rom; |
1038 | pl = (unsigned int *)Pico32xMem->m68k_rom; |
1039 | for (i = 1; i < 0xc0/4; i++) |
974fdb5b |
1040 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
1041 | |
1042 | // fill with nops |
1043 | for (i = 0xc0/2; i < 0x100/2; i++) |
1044 | ps[i] = 0x4e71; |
1045 | |
5e49c3a8 |
1046 | #if 0 |
be2c4208 |
1047 | ps[0xc0/2] = 0x46fc; |
1048 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
1049 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
1050 | #else |
1051 | ps[0xfe/2] = 0x4e75; // rts |
1052 | #endif |
be2c4208 |
1053 | |
1054 | // fill remaining mem with ROM |
974fdb5b |
1055 | memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100); |
be2c4208 |
1056 | |
acd35d4c |
1057 | // 32X ROM |
1058 | // TODO: move |
1059 | { |
1060 | FILE *f = fopen("32X_M_BIOS.BIN", "rb"); |
1061 | int i; |
1062 | if (f == NULL) { |
b78efee2 |
1063 | printf("missing 32X_M_BIOS.BIN\n"); |
acd35d4c |
1064 | exit(1); |
1065 | } |
1066 | fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f); |
1067 | fclose(f); |
b78efee2 |
1068 | f = fopen("32X_S_BIOS.BIN", "rb"); |
1069 | if (f == NULL) { |
1070 | printf("missing 32X_S_BIOS.BIN\n"); |
1071 | exit(1); |
1072 | } |
1073 | fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f); |
1074 | fclose(f); |
1075 | // byteswap |
acd35d4c |
1076 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) { |
1077 | int t = Pico32xMem->sh2_rom_m[i]; |
1078 | Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1]; |
1079 | Pico32xMem->sh2_rom_m[i + 1] = t; |
1080 | } |
b78efee2 |
1081 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) { |
1082 | int t = Pico32xMem->sh2_rom_s[i]; |
1083 | Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1]; |
1084 | Pico32xMem->sh2_rom_s[i + 1] = t; |
1085 | } |
acd35d4c |
1086 | } |
1087 | |
be2c4208 |
1088 | // cartridge area becomes unmapped |
1089 | // XXX: we take the easy way and don't unmap ROM, |
1090 | // so that we can avoid handling the RV bit. |
1091 | // m68k_map_unmap(0x000000, 0x3fffff); |
1092 | |
1093 | // MD ROM area |
974fdb5b |
1094 | rs = sizeof(Pico32xMem->m68k_rom); |
1095 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1096 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1097 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1098 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1099 | |
1100 | // DRAM area |
1101 | Pico32xSwapDRAM(1); |
be2c4208 |
1102 | |
1103 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
1104 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1105 | if (rs > 0x80000) |
1106 | rs = 0x80000; |
1107 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1108 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
be2c4208 |
1109 | |
1110 | // 32X ROM (banked) |
5e49c3a8 |
1111 | bank_switch(0); |
b78efee2 |
1112 | |
1113 | // setup poll detector |
1114 | m68k_poll.flag = P32XF_68KPOLL; |
be20816c |
1115 | m68k_poll.cyc_max = 64; |
b78efee2 |
1116 | sh2_poll[0].flag = P32XF_MSH2POLL; |
1d7a28a7 |
1117 | sh2_poll[0].cyc_max = 21; |
b78efee2 |
1118 | sh2_poll[1].flag = P32XF_SSH2POLL; |
be20816c |
1119 | sh2_poll[1].cyc_max = 16; |
be2c4208 |
1120 | } |
1121 | |