don't crash on bad timing
[picodrive.git] / pico / cd / pico.c
CommitLineData
cff531af 1/*
2 * PicoDrive
3 * (C) notaz, 2007
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 */
cc68a136 8
efcba75f 9#include "../pico_int.h"
43e6eaad 10#include "../sound/ym2612.h"
cc68a136 11
76276b0b 12extern unsigned char formatted_bram[4*0x10];
89fa852d 13extern unsigned int s68k_poll_adclk;
14
721cd396 15void (*PicoMCDopenTray)(void) = NULL;
d687ef50 16void (*PicoMCDcloseTray)(void) = NULL;
89fa852d 17
cc68a136 18
2aa27095 19PICO_INTERNAL void PicoInitMCD(void)
cc68a136 20{
21 SekInitS68k();
22 Init_CD_Driver();
cc68a136 23}
24
eff55556 25PICO_INTERNAL void PicoExitMCD(void)
cc68a136 26{
27 End_CD_Driver();
28}
29
1cb1584b 30PICO_INTERNAL void PicoPowerMCD(void)
31{
32 int fmt_size = sizeof(formatted_bram);
33 memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
34 memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
35 memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
36 memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
37 memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
38}
39
40PICO_INTERNAL int PicoResetMCD(void)
cc68a136 41{
51a902ae 42 memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
4f265db7 43 memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
5c69a605 44 memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
51a902ae 45
d1df8786 46 *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
c008977e 47 Pico_mcd->m.state_flags |= 1; // s68k reset pending
672ad671 48 Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
cc68a136 49
cc68a136 50 Reset_CD();
5c69a605 51 LC89510_Reset();
51a902ae 52 gfx_cd_reset();
3aa1e148 53#ifdef _ASM_CD_MEMORY_C
00bd648e 54 //PicoMemResetCDdecode(1); // don't have to call this in 2M mode
4ff2d527 55#endif
cc68a136 56
6cadc2da 57 // use SRam.data for RAM cart
af37bca8 58 if (PicoOpt & POPT_EN_MCD_RAMCART) {
d6114368 59 if (SRam.data == NULL)
60 SRam.data = calloc(1, 0x12000);
61 }
62 else if (SRam.data != NULL) {
63 free(SRam.data);
64 SRam.data = NULL;
65 }
b542be46 66 SRam.start = SRam.end = 0; // unused
6cadc2da 67
cc68a136 68 return 0;
69}
70
eff55556 71static __inline void SekRunM68k(int cyc)
cc68a136 72{
73 int cyc_do;
f6c49d38 74
75 pprof_start(m68k);
76
cc68a136 77 SekCycleAim+=cyc;
3ec29f01 78 if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
b5e5172d 79#if defined(EMU_CORE_DEBUG)
80 SekCycleCnt+=CM_compareRun(cyc_do, 0);
81#elif defined(EMU_C68K)
3aa1e148 82 PicoCpuCM68k.cycles=cyc_do;
83 CycloneRun(&PicoCpuCM68k);
84 SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
b837b69b 85#elif defined(EMU_M68K)
3aa1e148 86 m68k_set_context(&PicoCpuMM68k);
cc68a136 87 SekCycleCnt+=m68k_execute(cyc_do);
3aa1e148 88#elif defined(EMU_F68K)
89 g_m68kcontext=&PicoCpuFM68k;
c060a9ab 90 SekCycleCnt+=fm68k_emulate(cyc_do, 0, 0);
cc68a136 91#endif
f6c49d38 92 pprof_end(m68k);
cc68a136 93}
94
95static __inline void SekRunS68k(int cyc)
96{
97 int cyc_do;
98 SekCycleAimS68k+=cyc;
3ec29f01 99 if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
b5e5172d 100#if defined(EMU_CORE_DEBUG)
101 SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
102#elif defined(EMU_C68K)
3aa1e148 103 PicoCpuCS68k.cycles=cyc_do;
104 CycloneRun(&PicoCpuCS68k);
105 SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
b837b69b 106#elif defined(EMU_M68K)
3aa1e148 107 m68k_set_context(&PicoCpuMS68k);
cc68a136 108 SekCycleCntS68k+=m68k_execute(cyc_do);
3aa1e148 109#elif defined(EMU_F68K)
110 g_m68kcontext=&PicoCpuFS68k;
c060a9ab 111 SekCycleCntS68k+=fm68k_emulate(cyc_do, 0, 0);
cc68a136 112#endif
113}
114
7336a99a 115#define PS_STEP_M68K ((488<<16)/20) // ~24
116//#define PS_STEP_S68K 13
68cba51e 117
8022f53d 118#if defined(_ASM_CD_PICO_C)
119extern void SekRunPS(int cyc_m68k, int cyc_s68k);
120#elif defined(EMU_F68K)
121static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
122{
123 SekCycleAim+=cyc_m68k;
124 SekCycleAimS68k+=cyc_s68k;
c060a9ab 125 fm68k_emulate(0, 1, 0);
8022f53d 126}
a4030801 127#else
68cba51e 128static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
129{
7336a99a 130 int cycn, cycn_s68k, cyc_do;
68cba51e 131 SekCycleAim+=cyc_m68k;
132 SekCycleAimS68k+=cyc_s68k;
7336a99a 133
134// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
135// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
136
137 /* loop 488 downto 0 in steps of PS_STEP */
138 for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
139 {
7336a99a 140 cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
7336a99a 141 if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
68cba51e 142#if defined(EMU_C68K)
3aa1e148 143 PicoCpuCM68k.cycles = cyc_do;
144 CycloneRun(&PicoCpuCM68k);
145 SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
68cba51e 146#elif defined(EMU_M68K)
3aa1e148 147 m68k_set_context(&PicoCpuMM68k);
148 SekCycleCnt += m68k_execute(cyc_do);
149#elif defined(EMU_F68K)
150 g_m68kcontext = &PicoCpuFM68k;
c060a9ab 151 SekCycleCnt += fm68k_emulate(cyc_do, 0, 0);
68cba51e 152#endif
7336a99a 153 }
7336a99a 154 if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
68cba51e 155#if defined(EMU_C68K)
3aa1e148 156 PicoCpuCS68k.cycles = cyc_do;
157 CycloneRun(&PicoCpuCS68k);
158 SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
68cba51e 159#elif defined(EMU_M68K)
3aa1e148 160 m68k_set_context(&PicoCpuMS68k);
161 SekCycleCntS68k += m68k_execute(cyc_do);
162#elif defined(EMU_F68K)
163 g_m68kcontext = &PicoCpuFS68k;
c060a9ab 164 SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0);
68cba51e 165#endif
7336a99a 166 }
68cba51e 167 }
68cba51e 168}
7336a99a 169#endif
68cba51e 170
171
bf098bc5 172static __inline void check_cd_dma(void)
173{
174 int ddx;
175
c459aefd 176 if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
bf098bc5 177
178 ddx = Pico_mcd->s68k_regs[4] & 7;
179 if (ddx < 2) return; // invalid
c459aefd 180 if (ddx < 4) {
181 Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
182 return;
183 }
bf098bc5 184 if (ddx == 6) return; // invalid
185
186 Update_CDC_TRansfer(ddx); // now go and do the actual transfer
187}
188
4f265db7 189static __inline void update_chips(void)
190{
191 int counter_timer, int3_set;
192 int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
193
194 // 75Hz CDC update
195 if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
196 Pico_mcd->m.counter75hz -= counter75hz_lim;
197 Check_CD_Command();
198 }
199
200 // update timers
201 counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
202 Pico_mcd->m.timer_stopwatch += counter_timer;
203 if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
204 Pico_mcd->m.timer_int3 -= counter_timer;
205 if (Pico_mcd->m.timer_int3 < 0) {
206 if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
69996cb7 207 elprintf(EL_INTS, "s68k: timer irq 3");
4f265db7 208 SekInterruptS68k(3);
209 Pico_mcd->m.timer_int3 += int3_set << 16;
210 }
211 // is this really what happens if irq3 is masked out?
212 Pico_mcd->m.timer_int3 &= 0xffffff;
213 }
214 }
215
216 // update gfx chip
217 if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
218 gfx_cd_update();
219}
220
b837b69b 221
bf5fbbb4 222#define PICO_CD
c987bb5c 223#define CPUS_RUN(m68k_cycles,s68k_cycles) \
224{ \
225 if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \
226 SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \
227 } else { \
228 SekRunM68k(m68k_cycles); \
229 if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \
230 SekRunS68k(s68k_cycles); \
231 } \
232}
efcba75f 233#include "../pico_cmn.c"
cc68a136 234
235
2aa27095 236PICO_INTERNAL void PicoFrameMCD(void)
cc68a136 237{
602133e1 238 if (!(PicoOpt&POPT_ALT_RENDERER))
cc68a136 239 PicoFrameStart();
240
bf5fbbb4 241 PicoFrameHints();
cc68a136 242}
243
244