[picodrive.git] / pico / cd / memory.c

/*\r
 * Memory I/O handlers for Sega/Mega CD.\r
 * (C) notaz, 2007-2009\r
 * (C) irixxxx, 2019-2024\r
 *\r
 * This work is licensed under the terms of MAME license.\r
 * See COPYING file in the top-level directory.\r
 */\r
\r
#include "../pico_int.h"\r
#include "../memory.h"\r
\r
uptr s68k_read8_map  [0x1000000 >> M68K_MEM_SHIFT];\r
uptr s68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr s68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr s68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
\r
#ifndef _ASM_CD_MEMORY_C\r
MAKE_68K_READ8(s68k_read8, s68k_read8_map)\r
MAKE_68K_READ16(s68k_read16, s68k_read16_map)\r
MAKE_68K_READ32(s68k_read32, s68k_read16_map)\r
MAKE_68K_WRITE8(s68k_write8, s68k_write8_map)\r
MAKE_68K_WRITE16(s68k_write16, s68k_write16_map)\r
MAKE_68K_WRITE32(s68k_write32, s68k_write16_map)\r
#endif\r
\r
u32 pcd_base_address;\r
#define BASE pcd_base_address\r
\r
// -----------------------------------------------------------------\r
\r
// provided by ASM code:\r
#ifdef _ASM_CD_MEMORY_C\r
u32 PicoReadS68k8_pr(u32 a);\r
u32 PicoReadS68k16_pr(u32 a);\r
void PicoWriteS68k8_pr(u32 a, u32 d);\r
void PicoWriteS68k16_pr(u32 a, u32 d);\r
\r
u32 PicoReadM68k8_cell0(u32 a);\r
u32 PicoReadM68k8_cell1(u32 a);\r
u32 PicoReadM68k16_cell0(u32 a);\r
u32 PicoReadM68k16_cell1(u32 a);\r
void PicoWriteM68k8_cell0(u32 a, u32 d);\r
void PicoWriteM68k8_cell1(u32 a, u32 d);\r
void PicoWriteM68k16_cell0(u32 a, u32 d);\r
void PicoWriteM68k16_cell1(u32 a, u32 d);\r
\r
u32 PicoReadS68k8_dec0(u32 a);\r
u32 PicoReadS68k8_dec1(u32 a);\r
u32 PicoReadS68k16_dec0(u32 a);\r
u32 PicoReadS68k16_dec1(u32 a);\r
void PicoWriteS68k8_dec_m0b0(u32 a, u32 d);\r
void PicoWriteS68k8_dec_m1b0(u32 a, u32 d);\r
void PicoWriteS68k8_dec_m2b0(u32 a, u32 d);\r
void PicoWriteS68k8_dec_m0b1(u32 a, u32 d);\r
void PicoWriteS68k8_dec_m1b1(u32 a, u32 d);\r
void PicoWriteS68k8_dec_m2b1(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m0b0(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m1b0(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m2b0(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m0b1(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m1b1(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m2b1(u32 a, u32 d);\r
#endif\r
\r
static void remap_prg_window(u32 r1, u32 r3);\r
static void remap_word_ram(u32 r3);\r
\r
// poller detection\r
#define POLL_LIMIT 16\r
#define POLL_CYCLES 64\r
\r
void m68k_comm_check(u32 a)\r
{\r
  u32 cycles = SekCyclesDone();\r
  u32 clkdiff = cycles - Pico_mcd->m.m68k_poll_clk;\r
  pcd_sync_s68k(cycles, 0);\r
  if (a == 0x0e && !(Pico_mcd->m.state_flags & PCD_ST_S68K_SYNC) && (Pico_mcd->s68k_regs[3]&0x4)) {\r
    // there are cases when slave updates comm and only switches RAM\r
    // over after that (mcd1 bios), so there must be a resync..\r
    SekEndRun(64);\r
    Pico_mcd->m.state_flags |= PCD_ST_S68K_SYNC;\r
  }\r
  Pico_mcd->m.m68k_poll_clk = cycles;\r
  if (SekNotPolling || a != Pico_mcd->m.m68k_poll_a || clkdiff > POLL_CYCLES || clkdiff <= 16) {\r
    Pico_mcd->m.m68k_poll_a = a;\r
    Pico_mcd->m.m68k_poll_cnt = 0;\r
    SekNotPolling = 0;\r
    return;\r
  }\r
  Pico_mcd->m.m68k_poll_cnt++;\r
  Pico_mcd->m.state_flags &= ~PCD_ST_M68K_POLL;\r
  if (Pico_mcd->m.m68k_poll_cnt >= POLL_LIMIT) {\r
    Pico_mcd->m.state_flags |= PCD_ST_M68K_POLL;\r
    SekEndRun(8);\r
  }\r
}\r
\r
u32 pcd_stopwatch_read(int sub)\r
{\r
  // ugh... stopwatch runs 384 cycles per step, divide by mult with inverse\r
  u32 d = sub ? SekCyclesDoneS68k() : pcd_cycles_m68k_to_s68k(SekCyclesDone());\r
  d = ((d - Pico_mcd->m.stopwatch_base_c) * ((1LL << 32) / 384)) >> 32;\r
  return d & 0x0fff;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
static u32 m68k_reg_read16(u32 a)\r
{\r
  u32 d = 0;\r
  a &= 0x3e;\r
\r
  switch (a) {\r
    case 0:\r
      pcd_sync_s68k(SekCyclesDone(), 0);\r
      d = ((Pico_mcd->s68k_regs[0x33] & PCDS_IEN2) << 13) |\r
          (Pico_mcd->m.state_flags & PCD_ST_S68K_IFL2) | Pico_mcd->m.busreq;\r
      goto end;\r
    case 2:\r
      m68k_comm_check(a);\r
      d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
      elprintf(EL_CDREG3, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
      goto end;\r
    case 4:\r
      d = Pico_mcd->s68k_regs[4]<<8;\r
      goto end;\r
    case 6:\r
      d = *(u16 *)(Pico.rom + 0x72);\r
      goto end;\r
    case 8:\r
      d = cdc_host_r();\r
      goto end;\r
    case 0xa:\r
      elprintf(EL_UIO, "m68k FIXME: reserved read");\r
      goto end;\r
    case 0xc: // 384 cycle stopwatch timer\r
      d = pcd_stopwatch_read(0);\r
      elprintf(EL_CDREGS, "m68k stopwatch timer read (%04x)", d);\r
      goto end;\r
  }\r
\r
  if (a < 0x30) {\r
    // comm flag/cmd/status (0xE-0x2F)\r
    m68k_comm_check(a);\r
    d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
    return d;\r
  }\r
\r
  elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);\r
\r
end:\r
  return d;\r
}\r
#endif\r
\r
#ifndef _ASM_CD_MEMORY_C\r
static\r
#endif\r
void m68k_reg_write8(u32 a, u32 d)\r
{\r
  u32 dold;\r
  a &= 0x3f;\r
\r
  Pico_mcd->m.state_flags &= ~PCD_ST_M68K_POLL;\r
  Pico_mcd->m.m68k_poll_cnt = 0;\r
\r
  switch (a) {\r
    case 0:\r
      d &= 1;\r
      pcd_sync_s68k(SekCyclesDone(), 0);\r
      if (d && (Pico_mcd->s68k_regs[0x33] & PCDS_IEN2)) {\r
        elprintf(EL_INTS, "m68k: s68k irq 2");\r
        Pico_mcd->m.state_flags |= PCD_ST_S68K_IFL2;\r
        pcd_irq_s68k(2, 1);\r
      } else {\r
        Pico_mcd->m.state_flags &= ~PCD_ST_S68K_IFL2;\r
        pcd_irq_s68k(2, 0);\r
      }\r
      return;\r
    case 1:\r
      d &= 3;\r
      dold = Pico_mcd->m.busreq;\r
//      if (!(d & 1))\r
//        d |= 2; // verified: can't release bus on reset\r
      if (dold == d)\r
        return;\r
\r
      pcd_sync_s68k(SekCyclesDone(), 0);\r
\r
      if ((dold ^ d) & 1)\r
        elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));\r
      if (!(d & 1))\r
        Pico_mcd->m.state_flags |= PCD_ST_S68K_RST;\r
      else if (d == 1 && (Pico_mcd->m.state_flags & PCD_ST_S68K_RST)) {\r
        Pico_mcd->m.state_flags &= ~(PCD_ST_S68K_RST|PCD_ST_S68K_POLL|PCD_ST_S68K_SLEEP);\r
        elprintf(EL_CDREGS, "m68k: resetting s68k");\r
        SekResetS68k();\r
        SekCycleCntS68k += 40;\r
      }\r
      if (((dold & 3) == 1) != ((d & 3) == 1)) {\r
        elprintf(EL_INTSW, "m68k: s68k brq %i", d >> 1);\r
        remap_prg_window(d, Pico_mcd->s68k_regs[3]);\r
      }\r
      Pico_mcd->m.busreq = d;\r
      return;\r
    case 2:\r
      elprintf(EL_CDREGS, "m68k: prg wp=%02x", d);\r
      goto write_comm;\r
    case 3:\r
      elprintf(EL_CDREG3, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
      dold = Pico_mcd->s68k_regs[3];\r
      if ((d ^ dold) & 0xc0) {\r
        elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i",\r
          (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
        remap_prg_window(Pico_mcd->m.busreq, d);\r
      }\r
\r
      // 2M mode state is tracked regardless of current mode\r
      if (d & 2) {\r
        Pico_mcd->m.dmna_ret_2m |= 2;\r
        Pico_mcd->m.dmna_ret_2m &= ~1;\r
      }\r
      if (dold & 4) { // 1M mode\r
        d ^= 2;       // 0 sets DMNA, 1 does nothing\r
        d = (d & 0xc2) | (dold & 0x1f);\r
      }\r
      else\r
        d = (d & 0xc0) | (dold & 0x1c) | Pico_mcd->m.dmna_ret_2m;\r
      if ((dold ^ d) & 0x1f)\r
        remap_word_ram(d);\r
      goto write_comm;\r
    case 6:\r
      Pico.rom[MEM_BE2(0x72)] = d; // simple hint vector changer\r
      return;\r
    case 7:\r
      Pico.rom[MEM_BE2(0x73)] = d;\r
      elprintf(EL_CDREGS, "hint vector set to %04x%04x",\r
        ((u16 *)Pico.rom)[0x70/2], ((u16 *)Pico.rom)[0x72/2]);\r
      return;\r
    case 8:\r
      (void) cdc_host_r(); // acts same as reading\r
      return;\r
    case 0x0f:\r
      a = 0x0e;\r
    case 0x0e:\r
      goto write_comm;\r
  }\r
\r
  if ((a&0xf0) == 0x10)\r
    goto write_comm;\r
\r
  elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);\r
  return;\r
\r
write_comm:\r
  if (Pico_mcd->s68k_regs[a] == (u8)d)\r
    return;\r
\r
  pcd_sync_s68k(SekCyclesDone(), 0);\r
  Pico_mcd->s68k_regs[a] = d;\r
  if (a == 0x03) {\r
    // There are cases when master checks for successful switching of RAM to\r
    // slave. This can produce race conditions where slave switches RAM back to\r
    // master while master is delayed by interrupt before the check executes.\r
    // Delay slave a bit to make sure master can check before slave changes.\r
    SekCycleCntS68k += 24; // Silpheed\r
  }\r
  if (!((Pico_mcd->m.s68k_poll_a ^ a) & ~1)) {\r
    if (Pico_mcd->m.state_flags & PCD_ST_S68K_POLL)\r
      elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
    Pico_mcd->m.state_flags &= ~PCD_ST_S68K_POLL;\r
    Pico_mcd->m.s68k_poll_cnt = 0;\r
  }\r
}\r
\r
u32 s68k_poll_detect(u32 a, u32 d)\r
{\r
#ifdef USE_POLL_DETECT\r
  u32 cycles, cnt = 0;\r
  if (Pico_mcd->m.state_flags & (PCD_ST_S68K_POLL|PCD_ST_S68K_SLEEP))\r
    return d;\r
\r
  cycles = SekCyclesDoneS68k();\r
  if (!SekNotPollingS68k && a == Pico_mcd->m.s68k_poll_a) {\r
    u32 clkdiff = cycles - Pico_mcd->m.s68k_poll_clk;\r
    if (clkdiff <= POLL_CYCLES) {\r
      cnt = Pico_mcd->m.s68k_poll_cnt + 1;\r
      //printf("-- diff: %u, cnt = %i\n", clkdiff, cnt);\r
      Pico_mcd->m.state_flags &= ~PCD_ST_S68K_POLL;\r
      if (cnt > POLL_LIMIT) {\r
        Pico_mcd->m.state_flags |= PCD_ST_S68K_POLL;\r
        SekEndRunS68k(8);\r
        elprintf(EL_CDPOLL, "s68k poll detected @%06x, a=%02x",\r
          SekPcS68k, a);\r
      } else if (cnt > 2)\r
        SekEndRunS68k(240);\r
    }\r
  }\r
  Pico_mcd->m.s68k_poll_a = a;\r
  Pico_mcd->m.s68k_poll_clk = cycles;\r
  Pico_mcd->m.s68k_poll_cnt = cnt;\r
  SekNotPollingS68k = 0;\r
#endif\r
  return d;\r
}\r
\r
#define READ_FONT_DATA(basemask) \\r
{ \\r
      unsigned int fnt = CPU_LE4(*(u32 *)(Pico_mcd->s68k_regs + 0x4c)); \\r
      unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f;   \\r
      if (fnt & (basemask << 0)) d  = col1      ; else d  = col0;       \\r
      if (fnt & (basemask << 1)) d |= col1 <<  4; else d |= col0 <<  4; \\r
      if (fnt & (basemask << 2)) d |= col1 <<  8; else d |= col0 <<  8; \\r
      if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \\r
}\r
\r
\r
#ifndef _ASM_CD_MEMORY_C\r
static\r
#endif\r
u32 s68k_reg_read16(u32 a)\r
{\r
  u32 d=0;\r
\r
  switch (a) {\r
    case 0:\r
      d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
      goto end;\r
    case 2:\r
      d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);\r
      elprintf(EL_CDREG3, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);\r
      s68k_poll_detect(a, d);\r
      goto end;\r
    case 4:\r
      d = (Pico_mcd->s68k_regs[4]<<8) | (Pico_mcd->s68k_regs[5]&0x1f);\r
      goto end;\r
    case 6:\r
      d = cdc_reg_r();\r
      goto end;\r
    case 8:\r
      d = cdc_host_r();\r
      goto end;\r
    case 0xc:\r
      d = pcd_stopwatch_read(1);\r
      elprintf(EL_CDREGS, "s68k stopwatch timer read (%04x)", d);\r
      goto end;\r
    case 0x30:\r
      elprintf(EL_CDREGS, "s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[0x31]);\r
      d = Pico_mcd->s68k_regs[0x31];\r
      goto end;\r
    case 0x34: // fader\r
      d = 0; // no busy bit\r
      goto end;\r
    case 0x50: // font data (check: Lunar 2, Silpheed)\r
      READ_FONT_DATA(0x00100000);\r
      goto end;\r
    case 0x52:\r
      READ_FONT_DATA(0x00010000);\r
      goto end;\r
    case 0x54:\r
      READ_FONT_DATA(0x10000000);\r
      goto end;\r
    case 0x56:\r
      READ_FONT_DATA(0x01000000);\r
      goto end;\r
  }\r
\r
  d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
\r
  if ((a >= 0x0e && a < 0x30) || a == 0x58)\r
    d = s68k_poll_detect(a, d);\r
\r
end:\r
  return d;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
static\r
#endif\r
void s68k_reg_write8(u32 a, u32 d)\r
{\r
  // Warning: d might have upper bits set\r
  switch (a) {\r
    case 1:\r
      if (!(d & 1))\r
        pcd_soft_reset();\r
      return;\r
    case 2: a++; // byte access only, ignores LDS/UDS\r
    case 3: {\r
      int dold = Pico_mcd->s68k_regs[3];\r
      elprintf(EL_CDREG3, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);\r
      d &= 0x1d;\r
      d |= dold & 0xc2;\r
\r
      // 2M mode state\r
      if (d & 1) {\r
        Pico_mcd->m.dmna_ret_2m |= 1;\r
        Pico_mcd->m.dmna_ret_2m &= ~2; // DMNA clears\r
      }\r
\r
      if (d & 4)\r
      {\r
        if (!(dold & 4)) {\r
          elprintf(EL_CDREG3, "wram mode 2M->1M");\r
          wram_2M_to_1M(Pico_mcd->word_ram2M);\r
        }\r
\r
        if ((d ^ dold) & 0x05)\r
          d &= ~2; // clear DMNA - swap complete\r
      }\r
      else\r
      {\r
        if (dold & 4) {\r
          elprintf(EL_CDREG3, "wram mode 1M->2M");\r
          wram_1M_to_2M(Pico_mcd->word_ram2M);\r
        }\r
        d = (d & ~3) | Pico_mcd->m.dmna_ret_2m;\r
      }\r
      if ((dold ^ d) & 0x1f)\r
        remap_word_ram(d);\r
      goto write_comm;\r
    }\r
    case 4:\r
      elprintf(EL_CDREGS, "s68k CDC dest: %x", d&7);\r
      Pico_mcd->s68k_regs[a] = (d&7); // CDC mode\r
      Pico_mcd->s68k_regs[0xa] = Pico_mcd->s68k_regs[0xb] = 0; // resets DMA\r
      return;\r
    case 5:\r
      //dprintf("s68k CDC reg addr: %x", d&0x1f);\r
      Pico_mcd->s68k_regs[a] = (d&0x1f);\r
      return;\r
    case 7:\r
      cdc_reg_w(d & 0xff);\r
      return;\r
    case 0xa:\r
    case 0xb:\r
      // word access only. 68k sets both bus halves to value d.\r
      elprintf(EL_CDREGS, "s68k set CDC dma addr");\r
      Pico_mcd->s68k_regs[0xa] = Pico_mcd->s68k_regs[0xb] = d;\r
      return;\r
    case 0xc:\r
    case 0xd: // 384 cycle stopwatch timer\r
      elprintf(EL_CDREGS|EL_CD, "s68k clear stopwatch (%x)", d);\r
      // does this also reset internal 384 cycle counter?\r
      Pico_mcd->m.stopwatch_base_c = SekCyclesDoneS68k();\r
      return;\r
    case 0x0e: a++;\r
    case 0x0f:\r
      goto write_comm;\r
    case 0x30: a++;\r
    case 0x31: // 384 cycle int3 timer\r
      d &= 0xff;\r
      elprintf(EL_CDREGS|EL_CD, "s68k set int3 timer: %02x", d);\r
      Pico_mcd->s68k_regs[a] = (u8) d;\r
      if (d) // XXX: d or d+1? mcd-verificator results suggest d+1\r
        pcd_event_schedule_s68k(PCD_EVENT_TIMER3, (d+1) * 384);\r
      else\r
        pcd_event_schedule(0, PCD_EVENT_TIMER3, 0);\r
      break;\r
    case 0x33: // IRQ mask\r
      elprintf(EL_CDREGS|EL_CD, "s68k irq mask: %02x", d);\r
      d &= 0x7e;\r
      if ((d ^ Pico_mcd->s68k_regs[0x33]) & PCDS_IEN4) {\r
        // XXX: emulate pending irq instead?\r
        if ((d & PCDS_IEN4) && (Pico_mcd->s68k_regs[0x37] & 4)) {\r
          elprintf(EL_INTS, "cdd export irq 4 (unmask)");\r
          pcd_irq_s68k(4, 1);\r
        }\r
      }\r
      if ((d ^ Pico_mcd->s68k_regs[0x33]) & ~d & PCDS_IEN2)\r
	pcd_irq_s68k(2, 0);\r
      break;\r
    case 0x34: // fader\r
      Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r
      return;\r
    case 0x36:\r
      return; // d/m bit is unsetable\r
    case 0x37: {\r
      u32 d_old = Pico_mcd->s68k_regs[0x37];\r
      Pico_mcd->s68k_regs[0x37] = d & 7;\r
      if ((d ^ d_old) & 4) {\r
        // ??\r
	if (d & 4)\r
          pcd_event_schedule_s68k(PCD_EVENT_CDC, 12500000/75);\r
\r
        if ((d & 4) && (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)) {\r
          elprintf(EL_INTS, "cdd export irq 4");\r
          pcd_irq_s68k(4, 1);\r
        }\r
      }\r
      return;\r
    }\r
    case 0x4b:\r
      Pico_mcd->s68k_regs[a] = 0; // (u8) d; ?\r
      cdd_process();\r
      {\r
        static const char *nm[] =\r
          { "stat", "stop", "read_toc", "play",\r
            "seek", "???",  "pause",    "resume",\r
            "ff",   "fr",   "tjump",    "???",\r
            "close","open", "???",      "???" };\r
        u8 *c = &Pico_mcd->s68k_regs[0x42];\r
        u8 *s = &Pico_mcd->s68k_regs[0x38];\r
        elprintf(EL_CD,\r
          "CDD command: %02x %02x %02x %02x %02x %02x %02x %02x %12s",\r
          c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7], nm[c[0] & 0x0f]);\r
        elprintf(EL_CD,\r
          "CDD status:  %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",\r
          s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7], s[8], s[9]);\r
      }\r
      return;\r
    case 0x4c: a++;\r
      break;\r
    case 0x58:\r
      return;\r
  }\r
\r
  if ((a&0x1f0) == 0x20)\r
    goto write_comm;\r
\r
  if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))\r
  {\r
    elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);\r
    return;\r
  }\r
\r
  Pico_mcd->s68k_regs[a] = (u8) d;\r
  return;\r
\r
write_comm:\r
  if (Pico_mcd->s68k_regs[a] == (u8)d)\r
    return;\r
\r
  Pico_mcd->s68k_regs[a] = (u8) d;\r
  if (!((Pico_mcd->m.m68k_poll_a ^ a) & ~1)) {\r
    SekEndRunS68k(8);\r
    Pico_mcd->m.state_flags &= ~PCD_ST_M68K_POLL;\r
    Pico_mcd->m.m68k_poll_cnt = 0;\r
  }\r
}\r
\r
void s68k_reg_write16(u32 a, u32 d)\r
{\r
  u8 *r = Pico_mcd->s68k_regs;\r
\r
  Pico_mcd->m.state_flags &= ~PCD_ST_S68K_POLL;\r
  Pico_mcd->m.s68k_poll_cnt = 0;\r
\r
  if ((a & 0x1f0) == 0x20)\r
    goto write_comm;\r
\r
  switch (a) {\r
    case 0x02:\r
    case 0x0e:\r
    case 0x30:\r
    case 0x4c:\r
      // these are only byte registers, LDS/UDS ignored\r
      return s68k_reg_write8(a + 1, d);\r
    case 0x08:\r
      return (void) cdc_host_r(); // acts same as reading\r
    case 0x0a: // DMA address\r
      r[0xa] = d >> 8;\r
      r[0xb] = d;\r
      return;\r
    case 0x58: // stamp data size\r
      r[0x59] = d & 7;\r
      return;\r
    case 0x5a: // stamp map base address\r
      r[0x5a] = d >> 8;\r
      r[0x5b] = d & 0xe0;\r
      return;\r
    case 0x5c: // V cell size\r
      r[0x5d] = d & 0x1f;\r
      return;\r
    case 0x5e: // image buffer start address\r
      r[0x5e] = d >> 8;\r
      r[0x5f] = d & 0xf8;\r
      return;\r
    case 0x60: // image buffer offset\r
      r[0x61] = d & 0x3f;\r
      return;\r
    case 0x62: // h dot size\r
      r[0x62] = (d >> 8) & 1;\r
      r[0x63] = d;\r
      return;\r
    case 0x64: // v dot size\r
      r[0x65] = d;\r
      return;\r
    case 0x66: // trace vector base address\r
      d &= 0xfffe;\r
      r[0x66] = d >> 8;\r
      r[0x67] = d;\r
      gfx_start(d);\r
      return;\r
    default:\r
      break;\r
  }\r
\r
  s68k_reg_write8(a,     d >> 8);\r
  s68k_reg_write8(a + 1, d & 0xff);\r
  return;\r
\r
write_comm:\r
  if (r[a] == (u8)(d >> 8) && r[a + 1] == (u8)d)\r
    return;\r
\r
  r[a] = d >> 8;\r
  r[a + 1] = d;\r
  if (!((Pico_mcd->m.m68k_poll_a ^ a) & ~1)) {\r
    SekEndRunS68k(8);\r
    Pico_mcd->m.state_flags &= ~PCD_ST_M68K_POLL;\r
    Pico_mcd->m.m68k_poll_cnt = 0;\r
  }\r
}\r
\r
// -----------------------------------------------------------------\r
//                          Main 68k\r
// -----------------------------------------------------------------\r
\r
#ifndef _ASM_CD_MEMORY_C\r
#include "cell_map.c"\r
\r
// WORD RAM, cell aranged area (220000 - 23ffff)\r
static u32 PicoReadM68k8_cell0(u32 a)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
  return Pico_mcd->word_ram1M[0][MEM_BE2(a)];\r
}\r
\r
static u32 PicoReadM68k8_cell1(u32 a)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2);\r
  return Pico_mcd->word_ram1M[1][MEM_BE2(a)];\r
}\r
\r
static u32 PicoReadM68k16_cell0(u32 a)\r
{\r
  a = (a&2) | (cell_map(a >> 2) << 2);\r
  return *(u16 *)(Pico_mcd->word_ram1M[0] + a);\r
}\r
\r
static u32 PicoReadM68k16_cell1(u32 a)\r
{\r
  a = (a&2) | (cell_map(a >> 2) << 2);\r
  return *(u16 *)(Pico_mcd->word_ram1M[1] + a);\r
}\r
\r
static void PicoWriteM68k8_cell0(u32 a, u32 d)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2);\r
  Pico_mcd->word_ram1M[0][MEM_BE2(a)] = d;\r
}\r
\r
static void PicoWriteM68k8_cell1(u32 a, u32 d)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2);\r
  Pico_mcd->word_ram1M[1][MEM_BE2(a)] = d;\r
}\r
\r
static void PicoWriteM68k16_cell0(u32 a, u32 d)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2);\r
  *(u16 *)(Pico_mcd->word_ram1M[0] + a) = d;\r
}\r
\r
static void PicoWriteM68k16_cell1(u32 a, u32 d)\r
{\r
  a = (a&3) | (cell_map(a >> 2) << 2);\r
  *(u16 *)(Pico_mcd->word_ram1M[1] + a) = d;\r
}\r
#endif\r
\r
// BIOS faking for MSU-MD, checks for "SEGA" at 0x400100 to detect CD drive\r
static u8 bios_id[4] = "SEGA";\r
\r
static u32 PicoReadM68k8_bios(u32 a)\r
{\r
  if ((a & 0xfffffc) == BASE+0x100) // CD detection by MSU\r
    return bios_id[a&3];\r
  return 0;\r
}\r
\r
static u32 PicoReadM68k16_bios(u32 a)\r
{\r
  if ((a & 0xfffffc) == BASE+0x100) // CD detection by MSU\r
    return (bios_id[a&2]<<8) | bios_id[(a&2)+1];\r
  return 0;\r
}\r
\r
// RAM cart (400000 - 7fffff, optional)\r
static u32 PicoReadM68k8_ramc(u32 a)\r
{\r
  u32 d = 0;\r
\r
  if (PicoIn.opt & POPT_EN_MCD_RAMCART) {\r
    if ((a & 0xf00001) == 0x400001) {\r
      if (Pico.sv.data != NULL)\r
        d = 3; // 64k cart\r
      return d;\r
    }\r
\r
    if ((a & 0xf00001) == 0x600001) {\r
      if (Pico.sv.data != NULL)\r
        d = Pico.sv.data[((a >> 1) & 0xffff) + 0x2000];\r
      return d;\r
    }\r
\r
    if ((a & 0xf00001) == 0x700001)\r
      return Pico_mcd->m.bcram_reg;\r
  }\r
\r
  elprintf(EL_UIO, "m68k unmapped r8  [%06x] @%06x", a, SekPc);\r
  return d;\r
}\r
\r
static u32 PicoReadM68k16_ramc(u32 a)\r
{\r
  elprintf(EL_ANOMALY, "ramcart r16: [%06x] @%06x", a, SekPc);\r
  return PicoReadM68k8_ramc(a + 1);\r
}\r
\r
static void PicoWriteM68k8_ramc(u32 a, u32 d)\r
{\r
  if (PicoIn.opt & POPT_EN_MCD_RAMCART) {\r
    if ((a & 0xf00001) == 0x600001) {\r
      if (Pico.sv.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
        Pico.sv.data[((a >> 1) & 0xffff) + 0x2000] = d;\r
        Pico.sv.changed = 1;\r
      }\r
      return;\r
    }\r
\r
    if ((a & 0xf00001) == 0x700001) {\r
      Pico_mcd->m.bcram_reg = d;\r
      return;\r
    }\r
  }\r
\r
  elprintf(EL_UIO, "m68k unmapped w8  [%06x]   %02x @%06x",\r
    a, d & 0xff, SekPc);\r
}\r
\r
static void PicoWriteM68k16_ramc(u32 a, u32 d)\r
{\r
  elprintf(EL_ANOMALY, "ramcart w16: [%06x] %04x @%06x",\r
    a, d, SekPcS68k);\r
  PicoWriteM68k8_ramc(a + 1, d);\r
}\r
\r
// IO/control/cd registers (a10000 - ...)\r
#ifndef _ASM_CD_MEMORY_C\r
u32 PicoRead8_mcd_io(u32 a)\r
{\r
  u32 d;\r
  if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
    d = m68k_reg_read16(a); // TODO: m68k_reg_read8\r
    if (!(a & 1))\r
      d >>= 8;\r
    d &= 0xff;\r
    elprintf(EL_CDREGS, "m68k_regs r8:  [%02x]   %02x @%06x",\r
      a & 0x3f, d, SekPc);\r
    return d;\r
  }\r
\r
  // fallback to default MD handler\r
  return PicoRead8_io(a);\r
}\r
\r
u32 PicoRead16_mcd_io(u32 a)\r
{\r
  u32 d;\r
  if ((a & 0xff00) == 0x2000) {\r
    d = m68k_reg_read16(a);\r
    elprintf(EL_CDREGS, "m68k_regs r16: [%02x] %04x @%06x",\r
      a & 0x3f, d, SekPc);\r
    return d;\r
  }\r
\r
  return PicoRead16_io(a);\r
}\r
\r
void PicoWrite8_mcd_io(u32 a, u32 d)\r
{\r
  if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
    elprintf(EL_CDREGS, "m68k_regs w8:  [%02x]   %02x @%06x",\r
      a & 0x3f, d, SekPc);\r
    m68k_reg_write8(a, d);\r
    return;\r
  }\r
\r
  PicoWrite8_io(a, d);\r
}\r
\r
void PicoWrite16_mcd_io(u32 a, u32 d)\r
{\r
  if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
    elprintf(EL_CDREGS, "m68k_regs w16: [%02x] %04x @%06x",\r
      a & 0x3f, d, SekPc);\r
\r
    m68k_reg_write8(a, d >> 8);\r
    if ((a & 0x3e) != 0x0e) // special case\r
      m68k_reg_write8(a + 1, d & 0xff);\r
    return;\r
  }\r
\r
  PicoWrite16_io(a, d);\r
}\r
#endif\r
\r
// -----------------------------------------------------------------\r
//                           Sub 68k\r
// -----------------------------------------------------------------\r
\r
static u32 s68k_unmapped_read8(u32 a)\r
{\r
  elprintf(EL_UIO, "s68k unmapped r8  [%06x] @%06x", a, SekPc);\r
  return 0;\r
}\r
\r
static u32 s68k_unmapped_read16(u32 a)\r
{\r
  elprintf(EL_UIO, "s68k unmapped r16 [%06x] @%06x", a, SekPc);\r
  return 0;\r
}\r
\r
static void s68k_unmapped_write8(u32 a, u32 d)\r
{\r
  elprintf(EL_UIO, "s68k unmapped w8  [%06x]   %02x @%06x",\r
    a, d & 0xff, SekPc);\r
}\r
\r
static void s68k_unmapped_write16(u32 a, u32 d)\r
{\r
  elprintf(EL_UIO, "s68k unmapped w16 [%06x] %04x @%06x",\r
    a, d & 0xffff, SekPc);\r
}\r
\r
// PRG RAM protected range (000000 - 01fdff)?\r
// XXX verify: ff00 or 1fe00 max?\r
static void PicoWriteS68k8_prgwp(u32 a, u32 d)\r
{\r
  if (a >= (Pico_mcd->s68k_regs[2] << 9))\r
    Pico_mcd->prg_ram[MEM_BE2(a)] = d;\r
}\r
\r
static void PicoWriteS68k16_prgwp(u32 a, u32 d)\r
{\r
  if (a >= (Pico_mcd->s68k_regs[2] << 9))\r
    *(u16 *)(Pico_mcd->prg_ram + a) = d;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
\r
// decode (080000 - 0bffff, in 1M mode)\r
static u32 PicoReadS68k8_dec0(u32 a)\r
{\r
  u32 d = Pico_mcd->word_ram1M[0][MEM_BE2(a >> 1) & 0x1ffff];\r
  if (a & 1)\r
    d &= 0x0f;\r
  else\r
    d >>= 4;\r
  return d;\r
}\r
\r
static u32 PicoReadS68k8_dec1(u32 a)\r
{\r
  u32 d = Pico_mcd->word_ram1M[1][MEM_BE2(a >> 1) & 0x1ffff];\r
  if (a & 1)\r
    d &= 0x0f;\r
  else\r
    d >>= 4;\r
  return d;\r
}\r
\r
static u32 PicoReadS68k16_dec0(u32 a)\r
{\r
  u32 d = Pico_mcd->word_ram1M[0][MEM_BE2(a >> 1) & 0x1ffff];\r
  d |= d << 4;\r
  d &= ~0xf0;\r
  return d;\r
}\r
\r
static u32 PicoReadS68k16_dec1(u32 a)\r
{\r
  u32 d = Pico_mcd->word_ram1M[1][MEM_BE2(a >> 1) & 0x1ffff];\r
  d |= d << 4;\r
  d &= ~0xf0;\r
  return d;\r
}\r
\r
/* check: jaguar xj 220 (draws entire world using decode) */\r
#define mk_decode_w8(bank)                                        \\r
static void PicoWriteS68k8_dec_m0b##bank(u32 a, u32 d)            \\r
{                                                                 \\r
  u8 *pd = &Pico_mcd->word_ram1M[bank][MEM_BE2(a >> 1) & 0x1ffff];\\r
                                                                  \\r
  if (!(a & 1))                                                   \\r
    *pd = (*pd & 0x0f) | (d << 4);                                \\r
  else                                                            \\r
    *pd = (*pd & 0xf0) | (d & 0x0f);                              \\r
}                                                                 \\r
                                                                  \\r
static void PicoWriteS68k8_dec_m1b##bank(u32 a, u32 d)            \\r
{                                                                 \\r
  u8 *pd = &Pico_mcd->word_ram1M[bank][MEM_BE2(a >> 1) & 0x1ffff];\\r
  u8 mask = (a & 1) ? 0x0f : 0xf0;                                \\r
                                                                  \\r
  if (!(*pd & mask) && (d & 0x0f)) /* underwrite */               \\r
    PicoWriteS68k8_dec_m0b##bank(a, d);                           \\r
}                                                                 \\r
                                                                  \\r
static void PicoWriteS68k8_dec_m2b##bank(u32 a, u32 d) /* ...and m3? */ \\r
{                                                                 \\r
  if (d & 0x0f) /* overwrite */                                   \\r
    PicoWriteS68k8_dec_m0b##bank(a, d);                           \\r
}\r
\r
mk_decode_w8(0)\r
mk_decode_w8(1)\r
\r
#define mk_decode_w16(bank)                                       \\r
static void PicoWriteS68k16_dec_m0b##bank(u32 a, u32 d)           \\r
{                                                                 \\r
  u8 *pd = &Pico_mcd->word_ram1M[bank][MEM_BE2(a >> 1) & 0x1ffff];\\r
                                                                  \\r
  d &= 0x0f0f;                                                    \\r
  *pd = d | (d >> 4);                                             \\r
}                                                                 \\r
                                                                  \\r
static void PicoWriteS68k16_dec_m1b##bank(u32 a, u32 d)           \\r
{                                                                 \\r
  u8 *pd = &Pico_mcd->word_ram1M[bank][MEM_BE2(a >> 1) & 0x1ffff];\\r
                                                                  \\r
  d &= 0x0f0f; /* underwrite */                                   \\r
  if (!(*pd & 0xf0)) *pd |= d >> 4;                               \\r
  if (!(*pd & 0x0f)) *pd |= d;                                    \\r
}                                                                 \\r
                                                                  \\r
static void PicoWriteS68k16_dec_m2b##bank(u32 a, u32 d)           \\r
{                                                                 \\r
  u8 *pd = &Pico_mcd->word_ram1M[bank][MEM_BE2(a >> 1) & 0x1ffff];\\r
                                                                  \\r
  d &= 0x0f0f; /* overwrite */                                    \\r
  d |= d >> 4;                                                    \\r
                                                                  \\r
  if (!(d & 0xf0)) d |= *pd & 0xf0;                               \\r
  if (!(d & 0x0f)) d |= *pd & 0x0f;                               \\r
  *pd = d;                                                        \\r
}\r
\r
mk_decode_w16(0)\r
mk_decode_w16(1)\r
\r
#endif\r
\r
// backup RAM (fe0000 - feffff)\r
static u32 PicoReadS68k8_bram(u32 a)\r
{\r
  return Pico_mcd->bram[(a>>1)&0x1fff];\r
}\r
\r
static u32 PicoReadS68k16_bram(u32 a)\r
{\r
  u32 d;\r
  elprintf(EL_ANOMALY, "FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);\r
  a = (a >> 1) & 0x1fff;\r
  d = Pico_mcd->bram[a];\r
  return d;\r
}\r
\r
static void PicoWriteS68k8_bram(u32 a, u32 d)\r
{\r
  if (a & 1) {\r
    Pico_mcd->bram[(a >> 1) & 0x1fff] = d;\r
    Pico.sv.changed = 1;\r
  }\r
}\r
\r
static void PicoWriteS68k16_bram(u32 a, u32 d)\r
{\r
  elprintf(EL_ANOMALY, "s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
  a = (a >> 1) & 0x1fff;\r
  Pico_mcd->bram[a++] = d;\r
  Pico.sv.changed = 1;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
\r
// PCM and registers (ff0000 - ffffff)\r
static u32 PicoReadS68k8_pr(u32 a)\r
{\r
  u32 d = 0;\r
\r
  // regs\r
  if ((a & 0xfe00) == 0x8000) {\r
    a &= 0x1ff;\r
    if (a >= 0x0e && a < 0x30) {\r
      d = Pico_mcd->s68k_regs[a];\r
      d = s68k_poll_detect(a & ~1, d);\r
      goto regs_done;\r
    }\r
    d = s68k_reg_read16(a & ~1);\r
    if (!(a & 1))\r
      d >>= 8;\r
\r
regs_done:\r
    d &= 0xff;\r
    elprintf(EL_CDREGS, "s68k_regs r8: [%02x] %02x @%06x",\r
      a, d, SekPcS68k);\r
    return d;\r
  }\r
\r
  // PCM\r
  // XXX: verify: probably odd addrs only?\r
  if ((a & 0x8000) == 0x0000) {\r
    a &= 0x7fff;\r
    if (a >= 0x2000)\r
      d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a >> 1) & 0xfff];\r
    else if (a >= 0x20)\r
      d = pcd_pcm_read(a >> 1);\r
\r
    return d;\r
  }\r
\r
  return s68k_unmapped_read8(a);\r
}\r
\r
static u32 PicoReadS68k16_pr(u32 a)\r
{\r
  u32 d = 0;\r
\r
  // regs\r
  if ((a & 0xfe00) == 0x8000) {\r
    a &= 0x1fe;\r
    d = s68k_reg_read16(a);\r
\r
    elprintf(EL_CDREGS, "s68k_regs r16: [%02x] %04x @%06x",\r
      a, d, SekPcS68k);\r
    return d;\r
  }\r
\r
  // PCM\r
  if ((a & 0x8000) == 0x0000) {\r
    a &= 0x7fff;\r
    if (a >= 0x2000)\r
      d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a >> 1) & 0xfff];\r
    else if (a >= 0x20)\r
      d = pcd_pcm_read(a >> 1);\r
\r
    return d;\r
  }\r
\r
  return s68k_unmapped_read16(a);\r
}\r
\r
static void PicoWriteS68k8_pr(u32 a, u32 d)\r
{\r
  // regs\r
  if ((a & 0xfe00) == 0x8000) {\r
    a &= 0x1ff;\r
    elprintf(EL_CDREGS, "s68k_regs w8: [%02x] %02x @%06x", a, d, SekPcS68k);\r
    if (0x59 <= a && a < 0x68) // word regs\r
      s68k_reg_write16(a & ~1, (d << 8) | d);\r
    else\r
      s68k_reg_write8(a, d);\r
    return;\r
  }\r
\r
  // PCM\r
  if ((a & 0x8000) == 0x0000) {\r
    a &= 0x7fff;\r
    if (a >= 0x2000)\r
      Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
    else if (a < 0x12)\r
      pcd_pcm_write(a>>1, d);\r
    return;\r
  }\r
\r
  s68k_unmapped_write8(a, d);\r
}\r
\r
static void PicoWriteS68k16_pr(u32 a, u32 d)\r
{\r
  // regs\r
  if ((a & 0xfe00) == 0x8000) {\r
    a &= 0x1fe;\r
    elprintf(EL_CDREGS, "s68k_regs w16: [%02x] %04x @%06x", a, d, SekPcS68k);\r
    s68k_reg_write16(a, d);\r
    return;\r
  }\r
\r
  // PCM\r
  if ((a & 0x8000) == 0x0000) {\r
    a &= 0x7fff;\r
    if (a >= 0x2000)\r
      Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
    else if (a < 0x12)\r
      pcd_pcm_write(a>>1, d & 0xff);\r
    return;\r
  }\r
\r
  s68k_unmapped_write16(a, d);\r
}\r
\r
#endif\r
\r
static const void *m68k_cell_read8[]   = { PicoReadM68k8_cell0, PicoReadM68k8_cell1 };\r
static const void *m68k_cell_read16[]  = { PicoReadM68k16_cell0, PicoReadM68k16_cell1 };\r
static const void *m68k_cell_write8[]  = { PicoWriteM68k8_cell0, PicoWriteM68k8_cell1 };\r
static const void *m68k_cell_write16[] = { PicoWriteM68k16_cell0, PicoWriteM68k16_cell1 };\r
\r
static const void *s68k_dec_read8[]   = { PicoReadS68k8_dec0, PicoReadS68k8_dec1 };\r
static const void *s68k_dec_read16[]  = { PicoReadS68k16_dec0, PicoReadS68k16_dec1 };\r
\r
static const void *s68k_dec_write8[2][4] = {\r
  { PicoWriteS68k8_dec_m0b0, PicoWriteS68k8_dec_m1b0, PicoWriteS68k8_dec_m2b0, PicoWriteS68k8_dec_m2b0 },\r
  { PicoWriteS68k8_dec_m0b1, PicoWriteS68k8_dec_m1b1, PicoWriteS68k8_dec_m2b1, PicoWriteS68k8_dec_m2b1 },\r
};\r
\r
static const void *s68k_dec_write16[2][4] = {\r
  { PicoWriteS68k16_dec_m0b0, PicoWriteS68k16_dec_m1b0, PicoWriteS68k16_dec_m2b0, PicoWriteS68k16_dec_m2b0 },\r
  { PicoWriteS68k16_dec_m0b1, PicoWriteS68k16_dec_m1b1, PicoWriteS68k16_dec_m2b1, PicoWriteS68k16_dec_m2b1 },\r
};\r
\r
// -----------------------------------------------------------------\r
\r
static void remap_prg_window(u32 r1, u32 r3)\r
{\r
  // PRG RAM, mapped to main CPU if sub is not running\r
  if ((r1 & 3) != 1) {\r
    void *bank = Pico_mcd->prg_ram_b[(r3 >> 6) & 3];\r
    cpu68k_map_all_ram(BASE+0x020000, BASE+0x03ffff, bank, 0);\r
  } else {\r
    m68k_map_unmap(BASE+0x020000, BASE+0x03ffff);\r
  }\r
}\r
\r
// if sub CPU accesses Word-RAM while it is assigned to the main CPU,\r
// GA doesn't assert DTACK, which means the CPU is blocked until the Word_RAM\r
// is reassigned to it (e.g. Mega Race).\r
// since DTACK isn't on the expansion port, main cpu accesses are not blocked.\r
// XXX is data read/written if main is accessing Word_RAM while not owning it?\r
static u32 s68k_wordram_main_read8(u32 a)\r
{\r
  Pico_mcd->m.state_flags |= PCD_ST_S68K_SLEEP;\r
  SekEndRunS68k(0);\r
  return Pico_mcd->word_ram2M[MEM_BE2(a) & 0x3ffff];\r
}\r
\r
static u32 s68k_wordram_main_read16(u32 a)\r
{\r
  Pico_mcd->m.state_flags |= PCD_ST_S68K_SLEEP;\r
  SekEndRunS68k(0);\r
  return ((u16 *)Pico_mcd->word_ram2M)[(a >> 1) & 0x1ffff];\r
}\r
\r
static void s68k_wordram_main_write8(u32 a, u32 d)\r
{\r
  Pico_mcd->m.state_flags |= PCD_ST_S68K_SLEEP;\r
  SekEndRunS68k(0);\r
  Pico_mcd->word_ram2M[MEM_BE2(a) & 0x3ffff] = d;\r
}\r
\r
static void s68k_wordram_main_write16(u32 a, u32 d)\r
{\r
  Pico_mcd->m.state_flags |= PCD_ST_S68K_SLEEP;\r
  SekEndRunS68k(0);\r
  ((u16 *)Pico_mcd->word_ram2M)[(a >> 1) & 0x1ffff] = d;\r
}\r
\r
static void remap_word_ram(u32 r3)\r
{\r
  void *bank;\r
\r
  // WORD RAM\r
  if (!(r3 & 4)) {\r
    // 2M mode.\r
    bank = Pico_mcd->word_ram2M;\r
    if (r3 & 1) {\r
      cpu68k_map_all_ram(BASE+0x200000, BASE+0x23ffff, bank, 0);\r
      cpu68k_map_all_funcs(0x80000, 0xbffff,\r
          s68k_wordram_main_read8, s68k_wordram_main_read16,\r
          s68k_wordram_main_write8, s68k_wordram_main_write16, 1);\r
    } else {\r
      Pico_mcd->m.state_flags &= ~PCD_ST_S68K_SLEEP;\r
      cpu68k_map_all_ram(0x080000, 0x0bffff, bank, 1);\r
      m68k_map_unmap(BASE+0x200000, BASE+0x23ffff);\r
    }\r
    // TODO: handle 0x0c0000\r
  }\r
  else {\r
    int b0 = r3 & 1;\r
    int m = (r3 & 0x18) >> 3;\r
    Pico_mcd->m.state_flags &= ~PCD_ST_S68K_SLEEP;\r
    bank = Pico_mcd->word_ram1M[b0];\r
    cpu68k_map_all_ram(BASE+0x200000, BASE+0x21ffff, bank, 0);\r
    bank = Pico_mcd->word_ram1M[b0 ^ 1];\r
    cpu68k_map_all_ram(0x0c0000, 0x0effff, bank, 1);\r
    // "cell arrange" on m68k\r
    cpu68k_map_all_funcs(BASE+0x220000, BASE+0x23ffff,\r
        m68k_cell_read8[b0], m68k_cell_read16[b0],\r
        m68k_cell_write8[b0], m68k_cell_write16[b0], 0);\r
    // "decode format" on s68k\r
    cpu68k_map_all_funcs(0x80000, 0xbffff,\r
        s68k_dec_read8[b0^1], s68k_dec_read16[b0^1],\r
        s68k_dec_write8[b0^1][m], s68k_dec_write16[b0^1][m], 1);\r
  }\r
}\r
\r
void pcd_state_loaded_mem(void)\r
{\r
  u32 r3 = Pico_mcd->s68k_regs[3];\r
\r
  /* after load events */\r
  if (r3 & 4) // 1M mode?\r
    wram_2M_to_1M(Pico_mcd->word_ram2M);\r
  remap_word_ram(r3);\r
  remap_prg_window(Pico_mcd->m.busreq, r3);\r
  Pico_mcd->m.dmna_ret_2m &= 3;\r
\r
  // restore hint vector\r
  *(u16 *)(Pico.rom + 0x72) = Pico_mcd->m.hint_vector;\r
}\r
\r
#ifdef EMU_M68K\r
static void m68k_mem_setup_cd(void);\r
#endif\r
\r
PICO_INTERNAL void PicoMemSetupCD(void)\r
{\r
  if (!Pico_mcd) {\r
    Pico_mcd = plat_mmap(0x05000000, sizeof(mcd_state), 0, 0);\r
    memset(Pico_mcd, 0, sizeof(mcd_state));\r
  }\r
  pcd_base_address = (Pico.romsize > 0x20000 ? 0x400000 : 0x000000);\r
\r
  // setup default main68k map\r
  PicoMemSetup();\r
\r
  // main68k map (BIOS or MSU mapped by PicoMemSetup()):\r
  if (Pico.romsize > 0x20000) {\r
    // MSU cartridge. Fake BIOS detection\r
    cpu68k_map_set(m68k_read8_map,   0x400000, 0x41ffff, PicoReadM68k8_bios, 1);\r
    cpu68k_map_set(m68k_read16_map,  0x400000, 0x41ffff, PicoReadM68k16_bios, 1);\r
  } else {\r
    // RAM cart\r
    cpu68k_map_set(m68k_read8_map,   0x400000, 0x7fffff, PicoReadM68k8_ramc, 1);\r
    cpu68k_map_set(m68k_read16_map,  0x400000, 0x7fffff, PicoReadM68k16_ramc, 1);\r
    cpu68k_map_set(m68k_write8_map,  0x400000, 0x7fffff, PicoWriteM68k8_ramc, 1);\r
    cpu68k_map_set(m68k_write16_map, 0x400000, 0x7fffff, PicoWriteM68k16_ramc, 1);\r
  }\r
\r
  // registers/IO:\r
  cpu68k_map_set(m68k_read8_map,   0xa10000, 0xa1ffff, PicoRead8_mcd_io, 1);\r
  cpu68k_map_set(m68k_read16_map,  0xa10000, 0xa1ffff, PicoRead16_mcd_io, 1);\r
  cpu68k_map_set(m68k_write8_map,  0xa10000, 0xa1ffff, PicoWrite8_mcd_io, 1);\r
  cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_mcd_io, 1);\r
\r
  // sub68k map\r
  cpu68k_map_set(s68k_read8_map,   0x000000, 0xffffff, s68k_unmapped_read8, 3);\r
  cpu68k_map_set(s68k_read16_map,  0x000000, 0xffffff, s68k_unmapped_read16, 3);\r
  cpu68k_map_set(s68k_write8_map,  0x000000, 0xffffff, s68k_unmapped_write8, 3);\r
  cpu68k_map_set(s68k_write16_map, 0x000000, 0xffffff, s68k_unmapped_write16, 3);\r
\r
  // PRG RAM\r
  cpu68k_map_set(s68k_read8_map,   0x000000, 0x07ffff, Pico_mcd->prg_ram, 2);\r
  cpu68k_map_set(s68k_read16_map,  0x000000, 0x07ffff, Pico_mcd->prg_ram, 2);\r
  cpu68k_map_set(s68k_write8_map,  0x000000, 0x07ffff, Pico_mcd->prg_ram, 2);\r
  cpu68k_map_set(s68k_write16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 2);\r
  cpu68k_map_set(s68k_write8_map,  0x000000, 0x01ffff, PicoWriteS68k8_prgwp, 3);\r
  cpu68k_map_set(s68k_write16_map, 0x000000, 0x01ffff, PicoWriteS68k16_prgwp, 3);\r
\r
  // BRAM\r
  cpu68k_map_set(s68k_read8_map,   0xfe0000, 0xfeffff, PicoReadS68k8_bram, 3);\r
  cpu68k_map_set(s68k_read16_map,  0xfe0000, 0xfeffff, PicoReadS68k16_bram, 3);\r
  cpu68k_map_set(s68k_write8_map,  0xfe0000, 0xfeffff, PicoWriteS68k8_bram, 3);\r
  cpu68k_map_set(s68k_write16_map, 0xfe0000, 0xfeffff, PicoWriteS68k16_bram, 3);\r
\r
  // PCM, regs\r
  cpu68k_map_set(s68k_read8_map,   0xff0000, 0xffffff, PicoReadS68k8_pr, 3);\r
  cpu68k_map_set(s68k_read16_map,  0xff0000, 0xffffff, PicoReadS68k16_pr, 3);\r
  cpu68k_map_set(s68k_write8_map,  0xff0000, 0xffffff, PicoWriteS68k8_pr, 3);\r
  cpu68k_map_set(s68k_write16_map, 0xff0000, 0xffffff, PicoWriteS68k16_pr, 3);\r
\r
  // RAMs\r
  remap_prg_window(2,1);\r
  remap_word_ram(1);\r
\r
#ifdef EMU_C68K\r
  // s68k\r
  PicoCpuCS68k.read8  = (void *)s68k_read8_map;\r
  PicoCpuCS68k.read16 = (void *)s68k_read16_map;\r
  PicoCpuCS68k.read32 = (void *)s68k_read16_map;\r
  PicoCpuCS68k.write8  = (void *)s68k_write8_map;\r
  PicoCpuCS68k.write16 = (void *)s68k_write16_map;\r
  PicoCpuCS68k.write32 = (void *)s68k_write16_map;\r
  PicoCpuCS68k.checkpc = NULL; /* unused */\r
  PicoCpuCS68k.fetch8  = NULL;\r
  PicoCpuCS68k.fetch16 = NULL;\r
  PicoCpuCS68k.fetch32 = NULL;\r
#endif\r
#ifdef EMU_F68K\r
  // s68k\r
  PicoCpuFS68k.read_byte  = (void *)s68k_read8;\r
  PicoCpuFS68k.read_word  = (void *)s68k_read16;\r
  PicoCpuFS68k.read_long  = (void *)s68k_read32;\r
  PicoCpuFS68k.write_byte = (void *)s68k_write8;\r
  PicoCpuFS68k.write_word = (void *)s68k_write16;\r
  PicoCpuFS68k.write_long = (void *)s68k_write32;\r
#endif\r
#ifdef EMU_M68K\r
  m68k_mem_setup_cd();\r
#endif\r
}\r
\r
\r
#ifdef EMU_M68K\r
u32  m68k_read8(u32 a);\r
u32  m68k_read16(u32 a);\r
u32  m68k_read32(u32 a);\r
void m68k_write8(u32 a, u8 d);\r
void m68k_write16(u32 a, u16 d);\r
void m68k_write32(u32 a, u32 d);\r
\r
static unsigned int PicoReadCD8w (unsigned int a) {\r
	return m68ki_cpu_p == &PicoCpuMS68k ? s68k_read8(a) : m68k_read8(a);\r
}\r
static unsigned int PicoReadCD16w(unsigned int a) {\r
	return m68ki_cpu_p == &PicoCpuMS68k ? s68k_read16(a) : m68k_read16(a);\r
}\r
static unsigned int PicoReadCD32w(unsigned int a) {\r
	return m68ki_cpu_p == &PicoCpuMS68k ? s68k_read32(a) : m68k_read32(a);\r
}\r
static void PicoWriteCD8w (unsigned int a, unsigned char d) {\r
	if (m68ki_cpu_p == &PicoCpuMS68k) s68k_write8(a, d); else m68k_write8(a, d);\r
}\r
static void PicoWriteCD16w(unsigned int a, unsigned short d) {\r
	if (m68ki_cpu_p == &PicoCpuMS68k) s68k_write16(a, d); else m68k_write16(a, d);\r
}\r
static void PicoWriteCD32w(unsigned int a, unsigned int d) {\r
	if (m68ki_cpu_p == &PicoCpuMS68k) s68k_write32(a, d); else m68k_write32(a, d);\r
}\r
\r
extern unsigned int (*pm68k_read_memory_8) (unsigned int address);\r
extern unsigned int (*pm68k_read_memory_16)(unsigned int address);\r
extern unsigned int (*pm68k_read_memory_32)(unsigned int address);\r
extern void (*pm68k_write_memory_8) (unsigned int address, unsigned char  value);\r
extern void (*pm68k_write_memory_16)(unsigned int address, unsigned short value);\r
extern void (*pm68k_write_memory_32)(unsigned int address, unsigned int   value);\r
\r
static void m68k_mem_setup_cd(void)\r
{\r
  pm68k_read_memory_8  = PicoReadCD8w;\r
  pm68k_read_memory_16 = PicoReadCD16w;\r
  pm68k_read_memory_32 = PicoReadCD32w;\r
  pm68k_write_memory_8  = PicoWriteCD8w;\r
  pm68k_write_memory_16 = PicoWriteCD16w;\r
  pm68k_write_memory_32 = PicoWriteCD32w;\r
}\r
#endif // EMU_M68K\r
\r
// vim:shiftwidth=2:ts=2:expandtab\r