cff531af |
1 | /* |
2 | * PicoDrive |
3 | * (C) notaz, 2007 |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
cc68a136 |
8 | |
efcba75f |
9 | #include "../pico_int.h" |
43e6eaad |
10 | #include "../sound/ym2612.h" |
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11 | |
76276b0b |
12 | extern unsigned char formatted_bram[4*0x10]; |
89fa852d |
13 | extern unsigned int s68k_poll_adclk; |
14 | |
721cd396 |
15 | void (*PicoMCDopenTray)(void) = NULL; |
d687ef50 |
16 | void (*PicoMCDcloseTray)(void) = NULL; |
89fa852d |
17 | |
cc68a136 |
18 | |
2aa27095 |
19 | PICO_INTERNAL void PicoInitMCD(void) |
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20 | { |
21 | SekInitS68k(); |
22 | Init_CD_Driver(); |
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23 | } |
24 | |
eff55556 |
25 | PICO_INTERNAL void PicoExitMCD(void) |
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26 | { |
27 | End_CD_Driver(); |
28 | } |
29 | |
1cb1584b |
30 | PICO_INTERNAL void PicoPowerMCD(void) |
31 | { |
32 | int fmt_size = sizeof(formatted_bram); |
33 | memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram)); |
34 | memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M)); |
35 | memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram)); |
36 | memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram)); |
37 | memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size); |
38 | } |
39 | |
40 | PICO_INTERNAL int PicoResetMCD(void) |
cc68a136 |
41 | { |
51a902ae |
42 | memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs)); |
4f265db7 |
43 | memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm)); |
5c69a605 |
44 | memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m)); |
51a902ae |
45 | |
d1df8786 |
46 | *(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6) |
c008977e |
47 | Pico_mcd->m.state_flags |= 1; // s68k reset pending |
672ad671 |
48 | Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset |
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49 | |
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50 | Reset_CD(); |
5c69a605 |
51 | LC89510_Reset(); |
51a902ae |
52 | gfx_cd_reset(); |
3aa1e148 |
53 | #ifdef _ASM_CD_MEMORY_C |
00bd648e |
54 | //PicoMemResetCDdecode(1); // don't have to call this in 2M mode |
4ff2d527 |
55 | #endif |
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56 | |
6cadc2da |
57 | // use SRam.data for RAM cart |
af37bca8 |
58 | if (PicoOpt & POPT_EN_MCD_RAMCART) { |
d6114368 |
59 | if (SRam.data == NULL) |
60 | SRam.data = calloc(1, 0x12000); |
61 | } |
62 | else if (SRam.data != NULL) { |
63 | free(SRam.data); |
64 | SRam.data = NULL; |
65 | } |
b542be46 |
66 | SRam.start = SRam.end = 0; // unused |
6cadc2da |
67 | |
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68 | return 0; |
69 | } |
70 | |
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71 | static __inline void SekRunS68k(int cyc) |
72 | { |
73 | int cyc_do; |
74 | SekCycleAimS68k+=cyc; |
3ec29f01 |
75 | if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return; |
b5e5172d |
76 | #if defined(EMU_CORE_DEBUG) |
77 | SekCycleCntS68k+=CM_compareRun(cyc_do, 1); |
78 | #elif defined(EMU_C68K) |
3aa1e148 |
79 | PicoCpuCS68k.cycles=cyc_do; |
80 | CycloneRun(&PicoCpuCS68k); |
81 | SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles; |
b837b69b |
82 | #elif defined(EMU_M68K) |
3aa1e148 |
83 | m68k_set_context(&PicoCpuMS68k); |
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84 | SekCycleCntS68k+=m68k_execute(cyc_do); |
ed4402a7 |
85 | m68k_set_context(&PicoCpuMM68k); |
3aa1e148 |
86 | #elif defined(EMU_F68K) |
87 | g_m68kcontext=&PicoCpuFS68k; |
c060a9ab |
88 | SekCycleCntS68k+=fm68k_emulate(cyc_do, 0, 0); |
ed4402a7 |
89 | g_m68kcontext=&PicoCpuFM68k; |
cc68a136 |
90 | #endif |
91 | } |
92 | |
7336a99a |
93 | #define PS_STEP_M68K ((488<<16)/20) // ~24 |
94 | //#define PS_STEP_S68K 13 |
68cba51e |
95 | |
8022f53d |
96 | #if defined(_ASM_CD_PICO_C) |
97 | extern void SekRunPS(int cyc_m68k, int cyc_s68k); |
98 | #elif defined(EMU_F68K) |
99 | static __inline void SekRunPS(int cyc_m68k, int cyc_s68k) |
100 | { |
101 | SekCycleAim+=cyc_m68k; |
102 | SekCycleAimS68k+=cyc_s68k; |
c060a9ab |
103 | fm68k_emulate(0, 1, 0); |
8022f53d |
104 | } |
a4030801 |
105 | #else |
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106 | static __inline void SekRunPS(int cyc_m68k, int cyc_s68k) |
107 | { |
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108 | int cycn, cycn_s68k, cyc_do; |
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109 | SekCycleAim+=cyc_m68k; |
110 | SekCycleAimS68k+=cyc_s68k; |
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111 | |
112 | // fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k, |
113 | // SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline); |
114 | |
115 | /* loop 488 downto 0 in steps of PS_STEP */ |
116 | for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K) |
117 | { |
7336a99a |
118 | cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16; |
7336a99a |
119 | if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) { |
68cba51e |
120 | #if defined(EMU_C68K) |
3aa1e148 |
121 | PicoCpuCM68k.cycles = cyc_do; |
122 | CycloneRun(&PicoCpuCM68k); |
123 | SekCycleCnt += cyc_do - PicoCpuCM68k.cycles; |
68cba51e |
124 | #elif defined(EMU_M68K) |
3aa1e148 |
125 | m68k_set_context(&PicoCpuMM68k); |
126 | SekCycleCnt += m68k_execute(cyc_do); |
127 | #elif defined(EMU_F68K) |
128 | g_m68kcontext = &PicoCpuFM68k; |
c060a9ab |
129 | SekCycleCnt += fm68k_emulate(cyc_do, 0, 0); |
68cba51e |
130 | #endif |
7336a99a |
131 | } |
7336a99a |
132 | if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) { |
68cba51e |
133 | #if defined(EMU_C68K) |
3aa1e148 |
134 | PicoCpuCS68k.cycles = cyc_do; |
135 | CycloneRun(&PicoCpuCS68k); |
136 | SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles; |
68cba51e |
137 | #elif defined(EMU_M68K) |
3aa1e148 |
138 | m68k_set_context(&PicoCpuMS68k); |
139 | SekCycleCntS68k += m68k_execute(cyc_do); |
140 | #elif defined(EMU_F68K) |
141 | g_m68kcontext = &PicoCpuFS68k; |
c060a9ab |
142 | SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0); |
68cba51e |
143 | #endif |
7336a99a |
144 | } |
68cba51e |
145 | } |
68cba51e |
146 | } |
7336a99a |
147 | #endif |
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148 | |
149 | |
bf098bc5 |
150 | static __inline void check_cd_dma(void) |
151 | { |
152 | int ddx; |
153 | |
c459aefd |
154 | if (!(Pico_mcd->scd.Status_CDC & 0x08)) return; |
bf098bc5 |
155 | |
156 | ddx = Pico_mcd->s68k_regs[4] & 7; |
157 | if (ddx < 2) return; // invalid |
c459aefd |
158 | if (ddx < 4) { |
159 | Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port |
160 | return; |
161 | } |
bf098bc5 |
162 | if (ddx == 6) return; // invalid |
163 | |
164 | Update_CDC_TRansfer(ddx); // now go and do the actual transfer |
165 | } |
166 | |
4f265db7 |
167 | static __inline void update_chips(void) |
168 | { |
169 | int counter_timer, int3_set; |
170 | int counter75hz_lim = Pico.m.pal ? 2080 : 2096; |
171 | |
172 | // 75Hz CDC update |
173 | if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) { |
174 | Pico_mcd->m.counter75hz -= counter75hz_lim; |
175 | Check_CD_Command(); |
176 | } |
177 | |
178 | // update timers |
179 | counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708; |
180 | Pico_mcd->m.timer_stopwatch += counter_timer; |
181 | if ((int3_set = Pico_mcd->s68k_regs[0x31])) { |
182 | Pico_mcd->m.timer_int3 -= counter_timer; |
183 | if (Pico_mcd->m.timer_int3 < 0) { |
184 | if (Pico_mcd->s68k_regs[0x33] & (1<<3)) { |
69996cb7 |
185 | elprintf(EL_INTS, "s68k: timer irq 3"); |
4f265db7 |
186 | SekInterruptS68k(3); |
187 | Pico_mcd->m.timer_int3 += int3_set << 16; |
188 | } |
189 | // is this really what happens if irq3 is masked out? |
190 | Pico_mcd->m.timer_int3 &= 0xffffff; |
191 | } |
192 | } |
193 | |
194 | // update gfx chip |
195 | if (Pico_mcd->rot_comp.Reg_58 & 0x8000) |
196 | gfx_cd_update(); |
197 | } |
198 | |
b837b69b |
199 | |
bf5fbbb4 |
200 | #define PICO_CD |
c987bb5c |
201 | #define CPUS_RUN(m68k_cycles,s68k_cycles) \ |
202 | { \ |
203 | if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \ |
204 | SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \ |
205 | } else { \ |
206 | SekRunM68k(m68k_cycles); \ |
207 | if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \ |
208 | SekRunS68k(s68k_cycles); \ |
209 | } \ |
210 | } |
efcba75f |
211 | #include "../pico_cmn.c" |
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212 | |
213 | |
2aa27095 |
214 | PICO_INTERNAL void PicoFrameMCD(void) |
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215 | { |
602133e1 |
216 | if (!(PicoOpt&POPT_ALT_RENDERER)) |
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217 | PicoFrameStart(); |
218 | |
bf5fbbb4 |
219 | PicoFrameHints(); |
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220 | } |
221 | |
222 | |