cc68a136 |
1 | // This is part of Pico Library\r |
2 | \r |
3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
af37bca8 |
4 | // (c) Copyright 2006-2009 notaz, All rights reserved.\r |
cc68a136 |
5 | // Free for non-commercial use.\r |
6 | \r |
7 | // For commercial use, separate licencing terms must be obtained.\r |
8 | \r |
9 | \r |
efcba75f |
10 | #include "pico_int.h"\r |
af37bca8 |
11 | #include "memory.h"\r |
cc68a136 |
12 | \r |
cc68a136 |
13 | #include "sound/ym2612.h"\r |
14 | #include "sound/sn76496.h"\r |
15 | \r |
c8d1e9b6 |
16 | extern unsigned int lastSSRamWrite; // used by serial eeprom code\r |
cc68a136 |
17 | \r |
af37bca8 |
18 | unsigned long m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r |
19 | unsigned long m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r |
20 | unsigned long m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r |
21 | unsigned long m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r |
22 | \r |
23 | static void xmap_set(unsigned long *map, int shift, int start_addr, int end_addr,\r |
24 | void *func_or_mh, int is_func)\r |
25 | {\r |
26 | unsigned long addr = (unsigned long)func_or_mh;\r |
27 | int mask = (1 << shift) - 1;\r |
28 | int i;\r |
29 | \r |
30 | if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r |
31 | elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r |
32 | start_addr, end_addr);\r |
33 | return;\r |
34 | }\r |
35 | \r |
36 | if (addr & 1) {\r |
37 | elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r |
38 | return;\r |
39 | }\r |
40 | \r |
41 | if (!is_func)\r |
42 | addr -= start_addr;\r |
43 | \r |
44 | for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r |
45 | map[i] = addr >> 1;\r |
46 | if (is_func)\r |
47 | map[i] |= 1 << (sizeof(addr) * 8 - 1);\r |
48 | }\r |
49 | }\r |
50 | \r |
51 | void z80_map_set(unsigned long *map, int start_addr, int end_addr,\r |
52 | void *func_or_mh, int is_func)\r |
53 | {\r |
54 | xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r |
55 | }\r |
56 | \r |
57 | void cpu68k_map_set(unsigned long *map, int start_addr, int end_addr,\r |
58 | void *func_or_mh, int is_func)\r |
59 | {\r |
60 | xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r |
61 | }\r |
62 | \r |
63 | // more specialized/optimized function (does same as above)\r |
64 | void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r |
65 | {\r |
66 | unsigned long *r8map, *r16map, *w8map, *w16map;\r |
67 | unsigned long addr = (unsigned long)ptr;\r |
68 | int shift = M68K_MEM_SHIFT;\r |
69 | int i;\r |
70 | \r |
71 | if (!is_sub) {\r |
72 | r8map = m68k_read8_map;\r |
73 | r16map = m68k_read16_map;\r |
74 | w8map = m68k_write8_map;\r |
75 | w16map = m68k_write16_map;\r |
76 | } else {\r |
77 | r8map = s68k_read8_map;\r |
78 | r16map = s68k_read16_map;\r |
79 | w8map = s68k_write8_map;\r |
80 | w16map = s68k_write16_map;\r |
81 | }\r |
82 | \r |
83 | addr -= start_addr;\r |
84 | addr >>= 1;\r |
85 | for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r |
86 | r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r |
87 | }\r |
88 | \r |
89 | static u32 m68k_unmapped_read8(u32 a)\r |
90 | {\r |
91 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);\r |
92 | return 0; // assume pulldown, as if MegaCD2 was attached\r |
93 | }\r |
94 | \r |
95 | static u32 m68k_unmapped_read16(u32 a)\r |
96 | {\r |
97 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r |
98 | return 0;\r |
99 | }\r |
100 | \r |
101 | static void m68k_unmapped_write8(u32 a, u32 d)\r |
102 | {\r |
103 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r |
104 | }\r |
105 | \r |
106 | static void m68k_unmapped_write16(u32 a, u32 d)\r |
107 | {\r |
108 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r |
109 | }\r |
110 | \r |
111 | void m68k_map_unmap(int start_addr, int end_addr)\r |
112 | {\r |
113 | unsigned long addr;\r |
114 | int shift = M68K_MEM_SHIFT;\r |
115 | int i;\r |
116 | \r |
117 | addr = (unsigned long)m68k_unmapped_read8;\r |
118 | for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r |
119 | m68k_read8_map[i] = (addr >> 1) | (1 << 31);\r |
120 | \r |
121 | addr = (unsigned long)m68k_unmapped_read16;\r |
122 | for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r |
123 | m68k_read16_map[i] = (addr >> 1) | (1 << 31);\r |
124 | \r |
125 | addr = (unsigned long)m68k_unmapped_write8;\r |
126 | for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r |
127 | m68k_write8_map[i] = (addr >> 1) | (1 << 31);\r |
128 | \r |
129 | addr = (unsigned long)m68k_unmapped_write16;\r |
130 | for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r |
131 | m68k_write16_map[i] = (addr >> 1) | (1 << 31);\r |
132 | }\r |
133 | \r |
134 | MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r |
135 | MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r |
136 | MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r |
137 | MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r |
138 | MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r |
139 | MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r |
140 | \r |
141 | // -----------------------------------------------------------------\r |
142 | \r |
143 | static u32 ym2612_read_local_68k(void);\r |
144 | static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r |
145 | static void z80_mem_setup(void);\r |
cc68a136 |
146 | \r |
147 | \r |
03e4f2a3 |
148 | #ifdef EMU_CORE_DEBUG\r |
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149 | u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r |
150 | int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r |
151 | extern unsigned int ppop;\r |
152 | #endif\r |
153 | \r |
4f65685b |
154 | #ifdef IO_STATS\r |
155 | void log_io(unsigned int addr, int bits, int rw);\r |
dca310c4 |
156 | #elif defined(_MSC_VER)\r |
157 | #define log_io\r |
4f65685b |
158 | #else\r |
159 | #define log_io(...)\r |
160 | #endif\r |
161 | \r |
70357ce5 |
162 | #if defined(EMU_C68K)\r |
cc68a136 |
163 | static __inline int PicoMemBase(u32 pc)\r |
164 | {\r |
165 | int membase=0;\r |
166 | \r |
167 | if (pc<Pico.romsize+4)\r |
168 | {\r |
169 | membase=(int)Pico.rom; // Program Counter in Rom\r |
170 | }\r |
171 | else if ((pc&0xe00000)==0xe00000)\r |
172 | {\r |
173 | membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r |
174 | }\r |
175 | else\r |
176 | {\r |
177 | // Error - Program Counter is invalid\r |
178 | membase=(int)Pico.rom;\r |
179 | }\r |
180 | \r |
181 | return membase;\r |
182 | }\r |
183 | #endif\r |
184 | \r |
185 | \r |
406c96c5 |
186 | PICO_INTERNAL u32 PicoCheckPc(u32 pc)\r |
cc68a136 |
187 | {\r |
188 | u32 ret=0;\r |
189 | #if defined(EMU_C68K)\r |
3aa1e148 |
190 | pc-=PicoCpuCM68k.membase; // Get real pc\r |
0af33fe0 |
191 | // pc&=0xfffffe;\r |
192 | pc&=~1;\r |
193 | if ((pc<<8) == 0)\r |
69996cb7 |
194 | {\r |
f8af9634 |
195 | elprintf(EL_STATUS|EL_ANOMALY, "%i:%03i: game crash detected @ %06x\n",\r |
196 | Pico.m.frame_count, Pico.m.scanline, SekPc);\r |
197 | return (int)Pico.rom + Pico.romsize; // common crash condition, may happen with bad ROMs\r |
69996cb7 |
198 | }\r |
cc68a136 |
199 | \r |
3aa1e148 |
200 | PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r |
201 | PicoCpuCM68k.membase-=pc&0xff000000;\r |
cc68a136 |
202 | \r |
3aa1e148 |
203 | ret = PicoCpuCM68k.membase+pc;\r |
cc68a136 |
204 | #endif\r |
205 | return ret;\r |
206 | }\r |
207 | \r |
208 | \r |
2aa27095 |
209 | PICO_INTERNAL void PicoInitPc(u32 pc)\r |
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210 | {\r |
211 | PicoCheckPc(pc);\r |
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212 | }\r |
213 | \r |
cc68a136 |
214 | // -----------------------------------------------------------------\r |
af37bca8 |
215 | // memmap helpers\r |
cc68a136 |
216 | \r |
af37bca8 |
217 | static int PadRead(int i)\r |
e5503e2f |
218 | {\r |
219 | int pad,value,data_reg;\r |
5f9a0d16 |
220 | pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r |
e5503e2f |
221 | data_reg=Pico.ioports[i+1];\r |
222 | \r |
223 | // orr the bits, which are set as output\r |
224 | value = data_reg&(Pico.ioports[i+4]|0x80);\r |
225 | \r |
602133e1 |
226 | if (PicoOpt & POPT_6BTN_PAD)\r |
227 | {\r |
e5503e2f |
228 | int phase = Pico.m.padTHPhase[i];\r |
229 | \r |
230 | if(phase == 2 && !(data_reg&0x40)) { // TH\r |
231 | value|=(pad&0xc0)>>2; // ?0SA 0000\r |
232 | return value;\r |
233 | } else if(phase == 3) {\r |
234 | if(data_reg&0x40)\r |
235 | value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r |
236 | else\r |
237 | value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r |
238 | return value;\r |
239 | }\r |
240 | }\r |
241 | \r |
242 | if(data_reg&0x40) // TH\r |
243 | value|=(pad&0x3f); // ?1CB RLDU\r |
244 | else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r |
245 | \r |
246 | return value; // will mirror later\r |
247 | }\r |
248 | \r |
af37bca8 |
249 | static u32 io_ports_read(u32 a)\r |
cc68a136 |
250 | {\r |
af37bca8 |
251 | u32 d;\r |
252 | a = (a>>1) & 0xf;\r |
253 | switch (a) {\r |
254 | case 0: d = Pico.m.hardware; break; // Hardware value (Version register)\r |
255 | case 1: d = PadRead(0); break;\r |
256 | case 2: d = PadRead(1); break;\r |
257 | default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r |
7969166e |
258 | }\r |
af37bca8 |
259 | return d;\r |
cc68a136 |
260 | }\r |
cc68a136 |
261 | \r |
af37bca8 |
262 | static void io_ports_write(u32 a, u32 d)\r |
9dc09829 |
263 | {\r |
af37bca8 |
264 | a = (a>>1) & 0xf;\r |
265 | \r |
266 | // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r |
267 | if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))\r |
268 | {\r |
269 | Pico.m.padDelay[a - 1] = 0;\r |
270 | if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r |
271 | Pico.m.padTHPhase[a - 1]++;\r |
9dc09829 |
272 | }\r |
af37bca8 |
273 | \r |
274 | // cartain IO ports can be used as RAM\r |
275 | Pico.ioports[a] = d;\r |
9dc09829 |
276 | }\r |
277 | \r |
af37bca8 |
278 | static void ctl_write_z80busreq(u32 d)\r |
7969166e |
279 | {\r |
af37bca8 |
280 | d&=1; d^=1;\r |
281 | elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r |
282 | if (d ^ Pico.m.z80Run)\r |
283 | {\r |
284 | if (d)\r |
285 | {\r |
286 | z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r |
287 | }\r |
288 | else\r |
289 | {\r |
290 | z80stopCycle = SekCyclesDone();\r |
291 | if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset)\r |
292 | PicoSyncZ80(z80stopCycle);\r |
293 | }\r |
294 | Pico.m.z80Run = d;\r |
7969166e |
295 | }\r |
af37bca8 |
296 | }\r |
297 | \r |
298 | static void ctl_write_z80reset(u32 d)\r |
299 | {\r |
300 | d&=1; d^=1;\r |
301 | elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r |
302 | if (d ^ Pico.m.z80_reset)\r |
303 | {\r |
304 | if (d)\r |
305 | {\r |
306 | if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run)\r |
307 | PicoSyncZ80(SekCyclesDone());\r |
308 | YM2612ResetChip();\r |
309 | timers_reset();\r |
7969166e |
310 | }\r |
af37bca8 |
311 | else\r |
312 | {\r |
313 | z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r |
314 | z80_reset();\r |
7969166e |
315 | }\r |
af37bca8 |
316 | Pico.m.z80_reset = d;\r |
7969166e |
317 | }\r |
318 | }\r |
cc68a136 |
319 | \r |
af37bca8 |
320 | // -----------------------------------------------------------------\r |
fa1e5e29 |
321 | \r |
af37bca8 |
322 | // cart (save) RAM area (usually 0x200000 - ...)\r |
323 | static u32 PicoRead8_sram(u32 a)\r |
324 | {\r |
af37bca8 |
325 | u32 d;\r |
45f2f245 |
326 | if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r |
af37bca8 |
327 | {\r |
45f2f245 |
328 | if (SRam.flags & SRF_EEPROM) {\r |
af37bca8 |
329 | d = EEPROM_read();\r |
45f2f245 |
330 | if (!(a & 1))\r |
331 | d >>= 8;\r |
332 | } else\r |
af37bca8 |
333 | d = *(u8 *)(SRam.data - SRam.start + a);\r |
45f2f245 |
334 | elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r |
af37bca8 |
335 | return d;\r |
336 | }\r |
cc68a136 |
337 | \r |
45f2f245 |
338 | // XXX: this is banking unfriendly\r |
af37bca8 |
339 | if (a < Pico.romsize)\r |
340 | return Pico.rom[a ^ 1];\r |
341 | \r |
342 | return m68k_unmapped_read8(a);\r |
343 | }\r |
cc68a136 |
344 | \r |
af37bca8 |
345 | static u32 PicoRead16_sram(u32 a)\r |
cc68a136 |
346 | {\r |
af37bca8 |
347 | u32 d;\r |
45f2f245 |
348 | if (SRam.end >= a && a >= SRam.start && (Pico.m.sram_reg & SRR_MAPPED))\r |
af37bca8 |
349 | {\r |
45f2f245 |
350 | if (SRam.flags & SRF_EEPROM)\r |
af37bca8 |
351 | d = EEPROM_read();\r |
45f2f245 |
352 | else {\r |
af37bca8 |
353 | u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r |
354 | d = pm[0] << 8;\r |
355 | d |= pm[1];\r |
356 | }\r |
357 | elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r |
358 | return d;\r |
359 | }\r |
cc68a136 |
360 | \r |
af37bca8 |
361 | if (a < Pico.romsize)\r |
362 | return *(u16 *)(Pico.rom + a);\r |
cc68a136 |
363 | \r |
af37bca8 |
364 | return m68k_unmapped_read16(a);\r |
365 | }\r |
cc68a136 |
366 | \r |
af37bca8 |
367 | static void PicoWrite8_sram(u32 a, u32 d)\r |
368 | {\r |
45f2f245 |
369 | if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r |
370 | m68k_unmapped_write8(a, d);\r |
371 | return;\r |
372 | }\r |
373 | \r |
374 | elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);\r |
375 | if (SRam.flags & SRF_EEPROM)\r |
af37bca8 |
376 | {\r |
45f2f245 |
377 | EEPROM_write8(a, d);\r |
cc68a136 |
378 | }\r |
45f2f245 |
379 | else {\r |
380 | u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r |
af37bca8 |
381 | if (*pm != (u8)d) {\r |
382 | SRam.changed = 1;\r |
383 | *pm = (u8)d;\r |
384 | }\r |
385 | }\r |
386 | }\r |
cc68a136 |
387 | \r |
af37bca8 |
388 | static void PicoWrite16_sram(u32 a, u32 d)\r |
389 | {\r |
45f2f245 |
390 | if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r |
391 | m68k_unmapped_write16(a, d);\r |
392 | return;\r |
393 | }\r |
394 | \r |
395 | elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r |
396 | if (SRam.flags & SRF_EEPROM)\r |
397 | {\r |
398 | EEPROM_write16(d);\r |
399 | }\r |
400 | else {\r |
401 | // XXX: hardware could easily use MSB too..\r |
402 | u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r |
403 | if (*pm != (u8)d) {\r |
404 | SRam.changed = 1;\r |
405 | *pm = (u8)d;\r |
406 | }\r |
407 | }\r |
af37bca8 |
408 | }\r |
cc68a136 |
409 | \r |
af37bca8 |
410 | // z80 area (0xa00000 - 0xa0ffff)\r |
411 | // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r |
412 | static u32 PicoRead8_z80(u32 a)\r |
413 | {\r |
414 | u32 d = 0xff;\r |
415 | if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r |
416 | elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r |
417 | // open bus. Pulled down if MegaCD2 is attached.\r |
418 | return 0;\r |
419 | }\r |
c060a9ab |
420 | \r |
af37bca8 |
421 | if ((a & 0x4000) == 0x0000)\r |
422 | d = Pico.zram[a & 0x1fff];\r |
423 | else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r |
424 | d = ym2612_read_local_68k(); \r |
425 | else\r |
426 | elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r |
427 | return d;\r |
428 | }\r |
b542be46 |
429 | \r |
af37bca8 |
430 | static u32 PicoRead16_z80(u32 a)\r |
431 | {\r |
432 | u32 d = PicoRead8_z80(a);\r |
433 | return d | (d << 8);\r |
434 | }\r |
435 | \r |
436 | static void PicoWrite8_z80(u32 a, u32 d)\r |
437 | {\r |
438 | if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r |
439 | // verified on real hw\r |
440 | elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r |
441 | return;\r |
442 | }\r |
443 | \r |
444 | if ((a & 0x4000) == 0x0000) { // z80 RAM\r |
445 | SekCyclesBurn(2); // hack\r |
446 | Pico.zram[a & 0x1fff] = (u8)d;\r |
447 | return;\r |
448 | }\r |
449 | if ((a & 0x6000) == 0x4000) { // FM Sound\r |
450 | if (PicoOpt & POPT_EN_FM)\r |
451 | emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;\r |
452 | return;\r |
453 | }\r |
454 | // TODO: probably other VDP access too? Maybe more mirrors?\r |
455 | if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r |
456 | if (PicoOpt & POPT_EN_PSG)\r |
457 | SN76496Write(d);\r |
458 | return;\r |
459 | }\r |
460 | #if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r |
461 | if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r |
462 | {\r |
463 | Pico.m.z80_bank68k >>= 1;\r |
464 | Pico.m.z80_bank68k |= d << 8;\r |
465 | Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r |
466 | elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r |
467 | return;\r |
cc68a136 |
468 | }\r |
469 | #endif\r |
af37bca8 |
470 | elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r |
cc68a136 |
471 | }\r |
472 | \r |
af37bca8 |
473 | static void PicoWrite16_z80(u32 a, u32 d)\r |
cc68a136 |
474 | {\r |
af37bca8 |
475 | // for RAM, only most significant byte is sent\r |
476 | // TODO: verify remaining accesses\r |
477 | PicoWrite8_z80(a, d >> 8);\r |
478 | }\r |
cc68a136 |
479 | \r |
af37bca8 |
480 | // IO/control area (0xa10000 - 0xa1ffff)\r |
481 | u32 PicoRead8_io(u32 a)\r |
482 | {\r |
483 | u32 d;\r |
cc68a136 |
484 | \r |
af37bca8 |
485 | if ((a & 0xffe0) == 0x0000) { // I/O ports\r |
486 | d = io_ports_read(a);\r |
cc68a136 |
487 | goto end;\r |
488 | }\r |
cc68a136 |
489 | \r |
af37bca8 |
490 | // faking open bus (MegaCD pulldowns don't work here curiously)\r |
491 | d = Pico.m.rotate++;\r |
492 | d ^= d << 6;\r |
cc68a136 |
493 | \r |
af37bca8 |
494 | // bit8 seems to be readable in this range\r |
495 | if ((a & 0xfc01) == 0x1000)\r |
496 | d &= ~0x01;\r |
cc68a136 |
497 | \r |
af37bca8 |
498 | if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r |
499 | d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r |
500 | elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r |
501 | goto end;\r |
cc68a136 |
502 | }\r |
af37bca8 |
503 | \r |
be2c4208 |
504 | if (!(PicoOpt & POPT_DIS_32X)) {\r |
505 | d = PicoRead8_32x(a);\r |
506 | goto end;\r |
507 | }\r |
508 | \r |
af37bca8 |
509 | d = m68k_unmapped_read8(a);\r |
510 | end:\r |
cc68a136 |
511 | return d;\r |
512 | }\r |
513 | \r |
af37bca8 |
514 | u32 PicoRead16_io(u32 a)\r |
cc68a136 |
515 | {\r |
af37bca8 |
516 | u32 d;\r |
cc68a136 |
517 | \r |
af37bca8 |
518 | if ((a & 0xffe0) == 0x0000) { // I/O ports\r |
519 | d = io_ports_read(a);\r |
bdd6a009 |
520 | d |= d << 8;\r |
cc68a136 |
521 | goto end;\r |
522 | }\r |
523 | \r |
af37bca8 |
524 | // faking open bus\r |
525 | d = (Pico.m.rotate += 0x41);\r |
526 | d ^= (d << 5) ^ (d << 8);\r |
cc68a136 |
527 | \r |
af37bca8 |
528 | // bit8 seems to be readable in this range\r |
529 | if ((a & 0xfc00) == 0x1000)\r |
530 | d &= ~0x0100;\r |
cc68a136 |
531 | \r |
af37bca8 |
532 | if ((a & 0xff00) == 0x1100) { // z80 busreq\r |
533 | d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r |
534 | elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r |
535 | goto end;\r |
cc68a136 |
536 | }\r |
af37bca8 |
537 | \r |
be2c4208 |
538 | if (!(PicoOpt & POPT_DIS_32X)) {\r |
539 | d = PicoRead16_32x(a);\r |
540 | goto end;\r |
541 | }\r |
542 | \r |
af37bca8 |
543 | d = m68k_unmapped_read16(a);\r |
544 | end:\r |
cc68a136 |
545 | return d;\r |
546 | }\r |
cc68a136 |
547 | \r |
af37bca8 |
548 | void PicoWrite8_io(u32 a, u32 d)\r |
549 | {\r |
550 | if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r |
551 | io_ports_write(a, d);\r |
552 | return;\r |
553 | }\r |
554 | if ((a & 0xff01) == 0x1100) { // z80 busreq\r |
555 | ctl_write_z80busreq(d);\r |
556 | return;\r |
557 | }\r |
558 | if ((a & 0xff01) == 0x1200) { // z80 reset\r |
559 | ctl_write_z80reset(d);\r |
560 | return;\r |
561 | }\r |
562 | if (a == 0xa130f1) { // sram access register\r |
563 | elprintf(EL_SRAMIO, "sram reg=%02x", d);\r |
45f2f245 |
564 | Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r |
565 | Pico.m.sram_reg |= (u8)(d & 3);\r |
af37bca8 |
566 | return;\r |
567 | }\r |
be2c4208 |
568 | if (!(PicoOpt & POPT_DIS_32X)) {\r |
569 | PicoWrite8_32x(a, d);\r |
570 | return;\r |
571 | }\r |
572 | \r |
af37bca8 |
573 | m68k_unmapped_write8(a, d);\r |
574 | }\r |
cc68a136 |
575 | \r |
af37bca8 |
576 | void PicoWrite16_io(u32 a, u32 d)\r |
cc68a136 |
577 | {\r |
af37bca8 |
578 | if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r |
579 | io_ports_write(a, d);\r |
580 | return;\r |
581 | }\r |
582 | if ((a & 0xff00) == 0x1100) { // z80 busreq\r |
583 | ctl_write_z80busreq(d >> 8);\r |
584 | return;\r |
585 | }\r |
586 | if ((a & 0xff00) == 0x1200) { // z80 reset\r |
587 | ctl_write_z80reset(d >> 8);\r |
588 | return;\r |
589 | }\r |
590 | if (a == 0xa130f0) { // sram access register\r |
591 | elprintf(EL_SRAMIO, "sram reg=%02x", d);\r |
45f2f245 |
592 | Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r |
593 | Pico.m.sram_reg |= (u8)(d & 3);\r |
af37bca8 |
594 | return;\r |
595 | }\r |
be2c4208 |
596 | if (!(PicoOpt & POPT_DIS_32X)) {\r |
597 | PicoWrite16_32x(a, d);\r |
598 | return;\r |
599 | }\r |
af37bca8 |
600 | m68k_unmapped_write16(a, d);\r |
601 | }\r |
cc68a136 |
602 | \r |
af37bca8 |
603 | // VDP area (0xc00000 - 0xdfffff)\r |
604 | // TODO: verify if lower byte goes to PSG on word writes\r |
605 | static u32 PicoRead8_vdp(u32 a)\r |
606 | {\r |
607 | if ((a & 0x00e0) == 0x0000)\r |
608 | return PicoVideoRead8(a);\r |
cc68a136 |
609 | \r |
af37bca8 |
610 | elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r |
611 | return 0;\r |
cc68a136 |
612 | }\r |
613 | \r |
af37bca8 |
614 | static u32 PicoRead16_vdp(u32 a)\r |
cc68a136 |
615 | {\r |
af37bca8 |
616 | if ((a & 0x00e0) == 0x0000)\r |
617 | return PicoVideoRead(a);\r |
cc68a136 |
618 | \r |
af37bca8 |
619 | elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r |
620 | return 0;\r |
cc68a136 |
621 | }\r |
622 | \r |
af37bca8 |
623 | static void PicoWrite8_vdp(u32 a, u32 d)\r |
cc68a136 |
624 | {\r |
af37bca8 |
625 | if ((a & 0x00f9) == 0x0011) { // PSG Sound\r |
626 | if (PicoOpt & POPT_EN_PSG)\r |
627 | SN76496Write(d);\r |
cc68a136 |
628 | return;\r |
629 | }\r |
af37bca8 |
630 | if ((a & 0x00e0) == 0x0000) {\r |
631 | d &= 0xff;\r |
632 | PicoVideoWrite(a, d | (d << 8));\r |
b542be46 |
633 | return;\r |
634 | }\r |
635 | \r |
af37bca8 |
636 | elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r |
cc68a136 |
637 | }\r |
638 | \r |
af37bca8 |
639 | static void PicoWrite16_vdp(u32 a, u32 d)\r |
640 | {\r |
641 | if ((a & 0x00f9) == 0x0010) { // PSG Sound\r |
642 | if (PicoOpt & POPT_EN_PSG)\r |
643 | SN76496Write(d);\r |
644 | return;\r |
645 | }\r |
646 | if ((a & 0x00e0) == 0x0000) {\r |
647 | PicoVideoWrite(a, d);\r |
648 | return;\r |
649 | }\r |
650 | \r |
651 | elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r |
652 | }\r |
cc68a136 |
653 | \r |
654 | // -----------------------------------------------------------------\r |
f53f286a |
655 | \r |
9037e45d |
656 | #ifdef EMU_M68K\r |
657 | static void m68k_mem_setup(void);\r |
658 | #endif\r |
659 | \r |
f8ef8ff7 |
660 | PICO_INTERNAL void PicoMemSetup(void)\r |
661 | {\r |
af37bca8 |
662 | int mask, rs, a;\r |
663 | \r |
664 | // setup the memory map\r |
665 | cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r |
666 | cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);\r |
667 | cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);\r |
668 | cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r |
669 | \r |
670 | // ROM\r |
671 | // align to bank size. We know ROM loader allocated enough for this\r |
672 | mask = (1 << M68K_MEM_SHIFT) - 1;\r |
673 | rs = (Pico.romsize + mask) & ~mask;\r |
674 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);\r |
675 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r |
676 | \r |
677 | // Common case of on-cart (save) RAM, usually at 0x200000-...\r |
45f2f245 |
678 | if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {\r |
679 | rs = SRam.end - SRam.start;\r |
af37bca8 |
680 | rs = (rs + mask) & ~mask;\r |
681 | if (SRam.start + rs >= 0x1000000)\r |
682 | rs = 0x1000000 - SRam.start;\r |
683 | cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r |
684 | cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r |
685 | cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r |
686 | cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r |
687 | }\r |
688 | \r |
689 | // Z80 region\r |
690 | cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r |
691 | cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r |
692 | cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r |
693 | cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r |
694 | \r |
695 | // IO/control region\r |
696 | cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);\r |
697 | cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);\r |
698 | cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r |
699 | cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r |
700 | \r |
701 | // VDP region\r |
702 | for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r |
703 | if ((a & 0xe700e0) != 0xc00000)\r |
704 | continue;\r |
705 | cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);\r |
706 | cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);\r |
707 | cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);\r |
708 | cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r |
709 | }\r |
710 | \r |
711 | // RAM and it's mirrors\r |
712 | for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r |
713 | cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r |
714 | cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r |
715 | cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r |
716 | cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r |
717 | }\r |
718 | \r |
cc68a136 |
719 | // Setup memory callbacks:\r |
70357ce5 |
720 | #ifdef EMU_C68K\r |
af37bca8 |
721 | PicoCpuCM68k.checkpc = PicoCheckPc;\r |
722 | PicoCpuCM68k.fetch8 = PicoCpuCM68k.read8 = m68k_read8;\r |
723 | PicoCpuCM68k.fetch16 = PicoCpuCM68k.read16 = m68k_read16;\r |
724 | PicoCpuCM68k.fetch32 = PicoCpuCM68k.read32 = m68k_read32;\r |
725 | PicoCpuCM68k.write8 = m68k_write8;\r |
726 | PicoCpuCM68k.write16 = m68k_write16;\r |
727 | PicoCpuCM68k.write32 = m68k_write32;\r |
cc68a136 |
728 | #endif\r |
70357ce5 |
729 | #ifdef EMU_F68K\r |
af37bca8 |
730 | PicoCpuFM68k.read_byte = m68k_read8;\r |
731 | PicoCpuFM68k.read_word = m68k_read16;\r |
732 | PicoCpuFM68k.read_long = m68k_read32;\r |
733 | PicoCpuFM68k.write_byte = m68k_write8;\r |
734 | PicoCpuFM68k.write_word = m68k_write16;\r |
735 | PicoCpuFM68k.write_long = m68k_write32;\r |
3aa1e148 |
736 | \r |
737 | // setup FAME fetchmap\r |
738 | {\r |
739 | int i;\r |
9037e45d |
740 | // by default, point everything to first 64k of ROM\r |
3aa1e148 |
741 | for (i = 0; i < M68K_FETCHBANK1; i++)\r |
742 | PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r |
743 | // now real ROM\r |
744 | for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r |
745 | PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r |
746 | // .. and RAM\r |
747 | for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r |
748 | PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r |
749 | }\r |
70357ce5 |
750 | #endif\r |
9037e45d |
751 | #ifdef EMU_M68K\r |
752 | m68k_mem_setup();\r |
753 | #endif\r |
c8d1e9b6 |
754 | \r |
755 | z80_mem_setup();\r |
cc68a136 |
756 | }\r |
757 | \r |
cc68a136 |
758 | #ifdef EMU_M68K\r |
9037e45d |
759 | unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r |
760 | unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r |
761 | unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r |
762 | void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;\r |
763 | void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r |
764 | void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;\r |
cc68a136 |
765 | \r |
9037e45d |
766 | /* it appears that Musashi doesn't always mask the unused bits */\r |
767 | unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r |
768 | unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r |
769 | unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r |
770 | void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r |
771 | void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r |
772 | void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r |
9037e45d |
773 | \r |
774 | static void m68k_mem_setup(void)\r |
775 | {\r |
af37bca8 |
776 | pm68k_read_memory_8 = m68k_read8;\r |
777 | pm68k_read_memory_16 = m68k_read16;\r |
778 | pm68k_read_memory_32 = m68k_read32;\r |
779 | pm68k_write_memory_8 = m68k_write8;\r |
780 | pm68k_write_memory_16 = m68k_write16;\r |
781 | pm68k_write_memory_32 = m68k_write32;\r |
cc68a136 |
782 | }\r |
cc68a136 |
783 | #endif // EMU_M68K\r |
784 | \r |
785 | \r |
4b9c5888 |
786 | // -----------------------------------------------------------------\r |
787 | \r |
4b9c5888 |
788 | static int get_scanline(int is_from_z80)\r |
789 | {\r |
790 | if (is_from_z80) {\r |
791 | int cycles = z80_cyclesDone();\r |
792 | while (cycles - z80_scanline_cycles >= 228)\r |
793 | z80_scanline++, z80_scanline_cycles += 228;\r |
794 | return z80_scanline;\r |
795 | }\r |
796 | \r |
2aa27095 |
797 | return Pico.m.scanline;\r |
4b9c5888 |
798 | }\r |
799 | \r |
48dc74f2 |
800 | /* probably should not be in this file, but it's near related code here */\r |
43e6eaad |
801 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r |
802 | {\r |
803 | int xcycles = z80_cycles << 8;\r |
804 | \r |
805 | /* check for overflows */\r |
806 | if ((mode_old & 4) && xcycles > timer_a_next_oflow)\r |
807 | ym2612.OPN.ST.status |= 1;\r |
808 | \r |
809 | if ((mode_old & 8) && xcycles > timer_b_next_oflow)\r |
810 | ym2612.OPN.ST.status |= 2;\r |
811 | \r |
812 | /* update timer a */\r |
813 | if (mode_old & 1)\r |
e53704e6 |
814 | while (xcycles > timer_a_next_oflow)\r |
43e6eaad |
815 | timer_a_next_oflow += timer_a_step;\r |
816 | \r |
817 | if ((mode_old ^ mode_new) & 1) // turning on/off\r |
818 | {\r |
48dc74f2 |
819 | if (mode_old & 1)\r |
e53704e6 |
820 | timer_a_next_oflow = TIMER_NO_OFLOW;\r |
43e6eaad |
821 | else\r |
48dc74f2 |
822 | timer_a_next_oflow = xcycles + timer_a_step;\r |
43e6eaad |
823 | }\r |
824 | if (mode_new & 1)\r |
825 | elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);\r |
826 | \r |
827 | /* update timer b */\r |
828 | if (mode_old & 2)\r |
e53704e6 |
829 | while (xcycles > timer_b_next_oflow)\r |
43e6eaad |
830 | timer_b_next_oflow += timer_b_step;\r |
831 | \r |
832 | if ((mode_old ^ mode_new) & 2)\r |
833 | {\r |
48dc74f2 |
834 | if (mode_old & 2)\r |
e53704e6 |
835 | timer_b_next_oflow = TIMER_NO_OFLOW;\r |
43e6eaad |
836 | else\r |
48dc74f2 |
837 | timer_b_next_oflow = xcycles + timer_b_step;\r |
43e6eaad |
838 | }\r |
839 | if (mode_new & 2)\r |
840 | elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);\r |
841 | }\r |
842 | \r |
4b9c5888 |
843 | // ym2612 DAC and timer I/O handlers for z80\r |
af37bca8 |
844 | static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r |
4b9c5888 |
845 | {\r |
846 | int addr;\r |
847 | \r |
848 | a &= 3;\r |
849 | if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */\r |
850 | {\r |
851 | int scanline = get_scanline(is_from_z80);\r |
852 | //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);\r |
853 | ym2612.dacout = ((int)d - 0x80) << 6;\r |
854 | if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)\r |
855 | PsndDoDAC(scanline);\r |
856 | return 0;\r |
857 | }\r |
858 | \r |
859 | switch (a)\r |
860 | {\r |
861 | case 0: /* address port 0 */\r |
862 | ym2612.OPN.ST.address = d;\r |
863 | ym2612.addr_A1 = 0;\r |
864 | #ifdef __GP2X__\r |
865 | if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r |
866 | #endif\r |
867 | return 0;\r |
868 | \r |
869 | case 1: /* data port 0 */\r |
870 | if (ym2612.addr_A1 != 0)\r |
871 | return 0;\r |
872 | \r |
873 | addr = ym2612.OPN.ST.address;\r |
874 | ym2612.REGS[addr] = d;\r |
875 | \r |
876 | switch (addr)\r |
877 | {\r |
878 | case 0x24: // timer A High 8\r |
879 | case 0x25: { // timer A Low 2\r |
880 | int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r |
881 | : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r |
882 | if (ym2612.OPN.ST.TA != TAnew)\r |
883 | {\r |
884 | //elprintf(EL_STATUS, "timer a set %i", TAnew);\r |
885 | ym2612.OPN.ST.TA = TAnew;\r |
e53704e6 |
886 | //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r |
4b9c5888 |
887 | //ym2612.OPN.ST.TAT = 0;\r |
48dc74f2 |
888 | timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r |
43e6eaad |
889 | if (ym2612.OPN.ST.mode & 1) {\r |
48dc74f2 |
890 | // this is not right, should really be done on overflow only\r |
4b9c5888 |
891 | int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r |
892 | timer_a_next_oflow = (cycles << 8) + timer_a_step;\r |
4b9c5888 |
893 | }\r |
43e6eaad |
894 | elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r |
4b9c5888 |
895 | }\r |
896 | return 0;\r |
897 | }\r |
898 | case 0x26: // timer B\r |
899 | if (ym2612.OPN.ST.TB != d) {\r |
900 | //elprintf(EL_STATUS, "timer b set %i", d);\r |
901 | ym2612.OPN.ST.TB = d;\r |
e53704e6 |
902 | //ym2612.OPN.ST.TBC = (256-d) * 288;\r |
4b9c5888 |
903 | //ym2612.OPN.ST.TBT = 0;\r |
48dc74f2 |
904 | timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r |
43e6eaad |
905 | if (ym2612.OPN.ST.mode & 2) {\r |
906 | int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r |
907 | timer_b_next_oflow = (cycles << 8) + timer_b_step;\r |
908 | }\r |
909 | elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r |
4b9c5888 |
910 | }\r |
911 | return 0;\r |
912 | case 0x27: { /* mode, timer control */\r |
913 | int old_mode = ym2612.OPN.ST.mode;\r |
43e6eaad |
914 | int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r |
915 | ym2612.OPN.ST.mode = d;\r |
4b9c5888 |
916 | \r |
43e6eaad |
917 | elprintf(EL_YMTIMER, "st mode %02x", d);\r |
918 | ym2612_sync_timers(cycles, old_mode, d);\r |
4b9c5888 |
919 | \r |
43e6eaad |
920 | /* reset Timer a flag */\r |
921 | if (d & 0x10)\r |
922 | ym2612.OPN.ST.status &= ~1;\r |
4b9c5888 |
923 | \r |
924 | /* reset Timer b flag */\r |
925 | if (d & 0x20)\r |
926 | ym2612.OPN.ST.status &= ~2;\r |
927 | \r |
43e6eaad |
928 | if ((d ^ old_mode) & 0xc0) {\r |
4b9c5888 |
929 | #ifdef __GP2X__\r |
52250671 |
930 | if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r |
4b9c5888 |
931 | #endif\r |
43e6eaad |
932 | return 1;\r |
933 | }\r |
4b9c5888 |
934 | return 0;\r |
935 | }\r |
936 | case 0x2b: { /* DAC Sel (YM2612) */\r |
937 | int scanline = get_scanline(is_from_z80);\r |
938 | ym2612.dacen = d & 0x80;\r |
939 | if (d & 0x80) PsndDacLine = scanline;\r |
940 | #ifdef __GP2X__\r |
941 | if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);\r |
942 | #endif\r |
943 | return 0;\r |
944 | }\r |
945 | }\r |
946 | break;\r |
947 | \r |
948 | case 2: /* address port 1 */\r |
949 | ym2612.OPN.ST.address = d;\r |
950 | ym2612.addr_A1 = 1;\r |
951 | #ifdef __GP2X__\r |
952 | if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r |
953 | #endif\r |
954 | return 0;\r |
955 | \r |
956 | case 3: /* data port 1 */\r |
957 | if (ym2612.addr_A1 != 1)\r |
958 | return 0;\r |
959 | \r |
960 | addr = ym2612.OPN.ST.address | 0x100;\r |
961 | ym2612.REGS[addr] = d;\r |
962 | break;\r |
963 | }\r |
964 | \r |
965 | #ifdef __GP2X__\r |
966 | if (PicoOpt & POPT_EXT_FM)\r |
967 | return YM2612Write_940(a, d, get_scanline(is_from_z80));\r |
968 | #endif\r |
969 | return YM2612Write_(a, d);\r |
970 | }\r |
971 | \r |
453d2a6e |
972 | \r |
43e6eaad |
973 | #define ym2612_read_local() \\r |
974 | if (xcycles >= timer_a_next_oflow) \\r |
975 | ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r |
976 | if (xcycles >= timer_b_next_oflow) \\r |
977 | ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r |
978 | \r |
c8d1e9b6 |
979 | static u32 MEMH_FUNC ym2612_read_local_z80(void)\r |
4b9c5888 |
980 | {\r |
981 | int xcycles = z80_cyclesDone() << 8;\r |
4b9c5888 |
982 | \r |
43e6eaad |
983 | ym2612_read_local();\r |
984 | \r |
985 | elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r |
986 | timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r |
987 | return ym2612.OPN.ST.status;\r |
988 | }\r |
989 | \r |
af37bca8 |
990 | static u32 ym2612_read_local_68k(void)\r |
43e6eaad |
991 | {\r |
992 | int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r |
993 | \r |
994 | ym2612_read_local();\r |
995 | \r |
996 | elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r |
997 | timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r |
4b9c5888 |
998 | return ym2612.OPN.ST.status;\r |
999 | }\r |
1000 | \r |
d2721b08 |
1001 | void ym2612_pack_state(void)\r |
1002 | {\r |
e53704e6 |
1003 | // timers are saved as tick counts, in 16.16 int format\r |
1004 | int tac, tat = 0, tbc, tbt = 0;\r |
1005 | tac = 1024 - ym2612.OPN.ST.TA;\r |
1006 | tbc = 256 - ym2612.OPN.ST.TB;\r |
1007 | if (timer_a_next_oflow != TIMER_NO_OFLOW)\r |
1008 | tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);\r |
1009 | if (timer_b_next_oflow != TIMER_NO_OFLOW)\r |
1010 | tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);\r |
1011 | elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r |
1012 | elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r |
1013 | \r |
d2721b08 |
1014 | #ifdef __GP2X__\r |
1015 | if (PicoOpt & POPT_EXT_FM)\r |
e4fb433c |
1016 | YM2612PicoStateSave2_940(tat, tbt);\r |
d2721b08 |
1017 | else\r |
1018 | #endif\r |
e53704e6 |
1019 | YM2612PicoStateSave2(tat, tbt);\r |
d2721b08 |
1020 | }\r |
1021 | \r |
453d2a6e |
1022 | void ym2612_unpack_state(void)\r |
1023 | {\r |
e53704e6 |
1024 | int i, ret, tac, tat, tbc, tbt;\r |
453d2a6e |
1025 | YM2612PicoStateLoad();\r |
1026 | \r |
1027 | // feed all the registers and update internal state\r |
db49317b |
1028 | for (i = 0x20; i < 0xA0; i++) {\r |
453d2a6e |
1029 | ym2612_write_local(0, i, 0);\r |
1030 | ym2612_write_local(1, ym2612.REGS[i], 0);\r |
1031 | }\r |
db49317b |
1032 | for (i = 0x30; i < 0xA0; i++) {\r |
1033 | ym2612_write_local(2, i, 0);\r |
1034 | ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r |
1035 | }\r |
1036 | for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r |
1037 | ym2612_write_local(2, i, 0);\r |
1038 | ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r |
1039 | ym2612_write_local(0, i, 0);\r |
1040 | ym2612_write_local(1, ym2612.REGS[i], 0);\r |
1041 | }\r |
1042 | for (i = 0xB0; i < 0xB8; i++) {\r |
1043 | ym2612_write_local(0, i, 0);\r |
1044 | ym2612_write_local(1, ym2612.REGS[i], 0);\r |
453d2a6e |
1045 | ym2612_write_local(2, i, 0);\r |
1046 | ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r |
1047 | }\r |
d2721b08 |
1048 | \r |
1049 | #ifdef __GP2X__\r |
1050 | if (PicoOpt & POPT_EXT_FM)\r |
e4fb433c |
1051 | ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r |
d2721b08 |
1052 | else\r |
1053 | #endif\r |
1054 | ret = YM2612PicoStateLoad2(&tat, &tbt);\r |
db49317b |
1055 | if (ret != 0) {\r |
1056 | elprintf(EL_STATUS, "old ym2612 state");\r |
1057 | return; // no saved timers\r |
1058 | }\r |
e53704e6 |
1059 | \r |
1060 | tac = (1024 - ym2612.OPN.ST.TA) << 16;\r |
1061 | tbc = (256 - ym2612.OPN.ST.TB) << 16;\r |
1062 | if (ym2612.OPN.ST.mode & 1)\r |
48dc74f2 |
1063 | timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);\r |
e53704e6 |
1064 | else\r |
1065 | timer_a_next_oflow = TIMER_NO_OFLOW;\r |
1066 | if (ym2612.OPN.ST.mode & 2)\r |
48dc74f2 |
1067 | timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);\r |
e53704e6 |
1068 | else\r |
1069 | timer_b_next_oflow = TIMER_NO_OFLOW;\r |
1070 | elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);\r |
1071 | elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);\r |
453d2a6e |
1072 | }\r |
1073 | \r |
cc68a136 |
1074 | // -----------------------------------------------------------------\r |
1075 | // z80 memhandlers\r |
1076 | \r |
c8d1e9b6 |
1077 | static unsigned char MEMH_FUNC z80_md_vdp_read(unsigned short a)\r |
cc68a136 |
1078 | {\r |
c8d1e9b6 |
1079 | // TODO?\r |
1080 | elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r |
1081 | return 0xff;\r |
1082 | }\r |
cc68a136 |
1083 | \r |
c8d1e9b6 |
1084 | static unsigned char MEMH_FUNC z80_md_bank_read(unsigned short a)\r |
1085 | {\r |
c8d1e9b6 |
1086 | unsigned int addr68k;\r |
1087 | unsigned char ret;\r |
cc68a136 |
1088 | \r |
c8d1e9b6 |
1089 | addr68k = Pico.m.z80_bank68k<<15;\r |
1090 | addr68k += a & 0x7fff;\r |
1091 | \r |
af37bca8 |
1092 | ret = m68k_read8(addr68k);\r |
cc68a136 |
1093 | \r |
c8d1e9b6 |
1094 | elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r |
cc68a136 |
1095 | return ret;\r |
1096 | }\r |
1097 | \r |
c8d1e9b6 |
1098 | static void MEMH_FUNC z80_md_ym2612_write(unsigned int a, unsigned char data)\r |
cc68a136 |
1099 | {\r |
c8d1e9b6 |
1100 | if (PicoOpt & POPT_EN_FM)\r |
1101 | emustatus |= ym2612_write_local(a, data, 1) & 1;\r |
1102 | }\r |
cc68a136 |
1103 | \r |
c8d1e9b6 |
1104 | static void MEMH_FUNC z80_md_vdp_br_write(unsigned int a, unsigned char data)\r |
1105 | {\r |
1106 | // TODO: allow full VDP access\r |
1107 | if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r |
cc68a136 |
1108 | {\r |
c8d1e9b6 |
1109 | if (PicoOpt & POPT_EN_PSG)\r |
1110 | SN76496Write(data);\r |
cc68a136 |
1111 | return;\r |
1112 | }\r |
1113 | \r |
c8d1e9b6 |
1114 | if ((a>>8) == 0x60)\r |
cc68a136 |
1115 | {\r |
c8d1e9b6 |
1116 | Pico.m.z80_bank68k >>= 1;\r |
1117 | Pico.m.z80_bank68k |= data << 8;\r |
1118 | Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r |
cc68a136 |
1119 | return;\r |
1120 | }\r |
1121 | \r |
c8d1e9b6 |
1122 | elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r |
1123 | }\r |
cc68a136 |
1124 | \r |
c8d1e9b6 |
1125 | static void MEMH_FUNC z80_md_bank_write(unsigned int a, unsigned char data)\r |
1126 | {\r |
c8d1e9b6 |
1127 | unsigned int addr68k;\r |
69996cb7 |
1128 | \r |
c8d1e9b6 |
1129 | addr68k = Pico.m.z80_bank68k << 15;\r |
1130 | addr68k += a & 0x7fff;\r |
1131 | \r |
1132 | elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r |
af37bca8 |
1133 | m68k_write8(addr68k, data);\r |
cc68a136 |
1134 | }\r |
1135 | \r |
c8d1e9b6 |
1136 | // -----------------------------------------------------------------\r |
1137 | \r |
1138 | static unsigned char z80_md_in(unsigned short p)\r |
a4221917 |
1139 | {\r |
c8d1e9b6 |
1140 | elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r |
1141 | return 0xff;\r |
a4221917 |
1142 | }\r |
1143 | \r |
c8d1e9b6 |
1144 | static void z80_md_out(unsigned short p, unsigned char d)\r |
cc68a136 |
1145 | {\r |
c8d1e9b6 |
1146 | elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r |
cc68a136 |
1147 | }\r |
c8d1e9b6 |
1148 | \r |
af37bca8 |
1149 | static void z80_mem_setup(void)\r |
c8d1e9b6 |
1150 | {\r |
1151 | z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r |
1152 | z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r |
1153 | z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r |
1154 | z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r |
1155 | z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r |
1156 | \r |
1157 | z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r |
1158 | z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r |
1159 | z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r |
1160 | z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r |
1161 | z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r |
1162 | \r |
1163 | #ifdef _USE_DRZ80\r |
1164 | drZ80.z80_in = z80_md_in;\r |
1165 | drZ80.z80_out = z80_md_out;\r |
1166 | #endif\r |
1167 | #ifdef _USE_CZ80\r |
1168 | Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (UINT32)Pico.zram); // main RAM\r |
1169 | Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (UINT32)Pico.zram); // mirror\r |
1170 | Cz80_Set_INPort(&CZ80, z80_md_in);\r |
1171 | Cz80_Set_OUTPort(&CZ80, z80_md_out);\r |
a4221917 |
1172 | #endif\r |
c8d1e9b6 |
1173 | }\r |
cc68a136 |
1174 | \r |