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drc: make BxxZAL implementation complete
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
1e973cb0 182#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 183
184 /* stubs */
185#define CC_STUB 1
186#define FP_STUB 2
187#define LOADB_STUB 3
188#define LOADH_STUB 4
189#define LOADW_STUB 5
190#define LOADD_STUB 6
191#define LOADBU_STUB 7
192#define LOADHU_STUB 8
193#define STOREB_STUB 9
194#define STOREH_STUB 10
195#define STOREW_STUB 11
196#define STORED_STUB 12
197#define STORELR_STUB 13
198#define INVCODE_STUB 14
199
200 /* branch codes */
201#define TAKEN 1
202#define NOTTAKEN 2
203#define NULLDS 3
204
205// asm linkage
206int new_recompile_block(int addr);
207void *get_addr_ht(u_int vaddr);
208void invalidate_block(u_int block);
209void invalidate_addr(u_int addr);
210void remove_hash(int vaddr);
211void jump_vaddr();
212void dyna_linker();
213void dyna_linker_ds();
214void verify_code();
215void verify_code_vm();
216void verify_code_ds();
217void cc_interrupt();
218void fp_exception();
219void fp_exception_ds();
220void jump_syscall();
7139f3c8 221void jump_syscall_hle();
57871462 222void jump_eret();
7139f3c8 223void jump_hlecall();
1e973cb0 224void jump_intcall();
7139f3c8 225void new_dyna_leave();
57871462 226
227// TLB
228void TLBWI_new();
229void TLBWR_new();
230void read_nomem_new();
231void read_nomemb_new();
232void read_nomemh_new();
233void read_nomemd_new();
234void write_nomem_new();
235void write_nomemb_new();
236void write_nomemh_new();
237void write_nomemd_new();
238void write_rdram_new();
239void write_rdramb_new();
240void write_rdramh_new();
241void write_rdramd_new();
242extern u_int memory_map[1048576];
243
244// Needed by assembler
245void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248void load_all_regs(signed char i_regmap[]);
249void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250void load_regs_entry(int t);
251void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253int tracedebug=0;
254
255//#define DEBUG_CYCLE_COUNT 1
256
257void nullf() {}
258//#define assem_debug printf
259//#define inv_debug printf
260#define assem_debug nullf
261#define inv_debug nullf
262
94d23bb9 263static void tlb_hacks()
57871462 264{
94d23bb9 265#ifndef DISABLE_TLB
57871462 266 // Goldeneye hack
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268 {
269 u_int addr;
270 int n;
271 switch (ROM_HEADER->Country_code&0xFF)
272 {
273 case 0x45: // U
274 addr=0x34b30;
275 break;
276 case 0x4A: // J
277 addr=0x34b70;
278 break;
279 case 0x50: // E
280 addr=0x329f0;
281 break;
282 default:
283 // Unknown country code
284 addr=0;
285 break;
286 }
287 u_int rom_addr=(u_int)rom;
288 #ifdef ROM_COPY
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
299 }
300 #endif
301 if(addr) {
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304 }
305 }
306 }
94d23bb9 307#endif
57871462 308}
309
94d23bb9 310static u_int get_page(u_int vaddr)
57871462 311{
312 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 313#ifndef DISABLE_TLB
57871462 314 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 315#endif
57871462 316 if(page>2048) page=2048+(page&2047);
94d23bb9 317 return page;
318}
319
320static u_int get_vpage(u_int vaddr)
321{
322 u_int vpage=(vaddr^0x80000000)>>12;
323#ifndef DISABLE_TLB
57871462 324 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 325#endif
57871462 326 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 327 return vpage;
328}
329
330// Get address from virtual address
331// This is called from the recompiled JR/JALR instructions
332void *get_addr(u_int vaddr)
333{
334 u_int page=get_page(vaddr);
335 u_int vpage=get_vpage(vaddr);
57871462 336 struct ll_entry *head;
337 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 head=jump_in[page];
339 while(head!=NULL) {
340 if(head->vaddr==vaddr&&head->reg32==0) {
341 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
342 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[3]=ht_bin[1];
344 ht_bin[2]=ht_bin[0];
345 ht_bin[1]=(int)head->addr;
346 ht_bin[0]=vaddr;
347 return head->addr;
348 }
349 head=head->next;
350 }
351 head=jump_dirty[vpage];
352 while(head!=NULL) {
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 // Don't restore blocks which are about to expire from the cache
356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
357 if(verify_dirty(head->addr)) {
358 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
359 invalid_code[vaddr>>12]=0;
360 memory_map[vaddr>>12]|=0x40000000;
361 if(vpage<2048) {
94d23bb9 362#ifndef DISABLE_TLB
57871462 363 if(tlb_LUT_r[vaddr>>12]) {
364 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
365 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 }
94d23bb9 367#endif
57871462 368 restore_candidate[vpage>>3]|=1<<(vpage&7);
369 }
370 else restore_candidate[page>>3]|=1<<(page&7);
371 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
372 if(ht_bin[0]==vaddr) {
373 ht_bin[1]=(int)head->addr; // Replace existing entry
374 }
375 else
376 {
377 ht_bin[3]=ht_bin[1];
378 ht_bin[2]=ht_bin[0];
379 ht_bin[1]=(int)head->addr;
380 ht_bin[0]=vaddr;
381 }
382 return head->addr;
383 }
384 }
385 head=head->next;
386 }
387 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
388 int r=new_recompile_block(vaddr);
389 if(r==0) return get_addr(vaddr);
390 // Execute in unmapped page, generate pagefault execption
391 Status|=2;
392 Cause=(vaddr<<31)|0x8;
393 EPC=(vaddr&1)?vaddr-5:vaddr;
394 BadVAddr=(vaddr&~1);
395 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
396 EntryHi=BadVAddr&0xFFFFE000;
397 return get_addr_ht(0x80000000);
398}
399// Look up address in hash table first
400void *get_addr_ht(u_int vaddr)
401{
402 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 return get_addr(vaddr);
407}
408
409void *get_addr_32(u_int vaddr,u_int flags)
410{
7139f3c8 411#ifdef FORCE32
412 return get_addr(vaddr);
560e4a12 413#else
57871462 414 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
415 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
417 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 418 u_int page=get_page(vaddr);
419 u_int vpage=get_vpage(vaddr);
57871462 420 struct ll_entry *head;
421 head=jump_in[page];
422 while(head!=NULL) {
423 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
424 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
425 if(head->reg32==0) {
426 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
427 if(ht_bin[0]==-1) {
428 ht_bin[1]=(int)head->addr;
429 ht_bin[0]=vaddr;
430 }else if(ht_bin[2]==-1) {
431 ht_bin[3]=(int)head->addr;
432 ht_bin[2]=vaddr;
433 }
434 //ht_bin[3]=ht_bin[1];
435 //ht_bin[2]=ht_bin[0];
436 //ht_bin[1]=(int)head->addr;
437 //ht_bin[0]=vaddr;
438 }
439 return head->addr;
440 }
441 head=head->next;
442 }
443 head=jump_dirty[vpage];
444 while(head!=NULL) {
445 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
446 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
447 // Don't restore blocks which are about to expire from the cache
448 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
449 if(verify_dirty(head->addr)) {
450 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
451 invalid_code[vaddr>>12]=0;
452 memory_map[vaddr>>12]|=0x40000000;
453 if(vpage<2048) {
94d23bb9 454#ifndef DISABLE_TLB
57871462 455 if(tlb_LUT_r[vaddr>>12]) {
456 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
457 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 }
94d23bb9 459#endif
57871462 460 restore_candidate[vpage>>3]|=1<<(vpage&7);
461 }
462 else restore_candidate[page>>3]|=1<<(page&7);
463 if(head->reg32==0) {
464 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
465 if(ht_bin[0]==-1) {
466 ht_bin[1]=(int)head->addr;
467 ht_bin[0]=vaddr;
468 }else if(ht_bin[2]==-1) {
469 ht_bin[3]=(int)head->addr;
470 ht_bin[2]=vaddr;
471 }
472 //ht_bin[3]=ht_bin[1];
473 //ht_bin[2]=ht_bin[0];
474 //ht_bin[1]=(int)head->addr;
475 //ht_bin[0]=vaddr;
476 }
477 return head->addr;
478 }
479 }
480 head=head->next;
481 }
482 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
483 int r=new_recompile_block(vaddr);
484 if(r==0) return get_addr(vaddr);
485 // Execute in unmapped page, generate pagefault execption
486 Status|=2;
487 Cause=(vaddr<<31)|0x8;
488 EPC=(vaddr&1)?vaddr-5:vaddr;
489 BadVAddr=(vaddr&~1);
490 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
491 EntryHi=BadVAddr&0xFFFFE000;
492 return get_addr_ht(0x80000000);
560e4a12 493#endif
57871462 494}
495
496void clear_all_regs(signed char regmap[])
497{
498 int hr;
499 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
500}
501
502signed char get_reg(signed char regmap[],int r)
503{
504 int hr;
505 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
506 return -1;
507}
508
509// Find a register that is available for two consecutive cycles
510signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
514 return -1;
515}
516
517int count_free_regs(signed char regmap[])
518{
519 int count=0;
520 int hr;
521 for(hr=0;hr<HOST_REGS;hr++)
522 {
523 if(hr!=EXCLUDE_REG) {
524 if(regmap[hr]<0) count++;
525 }
526 }
527 return count;
528}
529
530void dirty_reg(struct regstat *cur,signed char reg)
531{
532 int hr;
533 if(!reg) return;
534 for (hr=0;hr<HOST_REGS;hr++) {
535 if((cur->regmap[hr]&63)==reg) {
536 cur->dirty|=1<<hr;
537 }
538 }
539}
540
541// If we dirty the lower half of a 64 bit register which is now being
542// sign-extended, we need to dump the upper half.
543// Note: Do this only after completion of the instruction, because
544// some instructions may need to read the full 64-bit value even if
545// overwriting it (eg SLTI, DSRA32).
546static void flush_dirty_uppers(struct regstat *cur)
547{
548 int hr,reg;
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if((cur->dirty>>hr)&1) {
551 reg=cur->regmap[hr];
552 if(reg>=64)
553 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
554 }
555 }
556}
557
558void set_const(struct regstat *cur,signed char reg,uint64_t value)
559{
560 int hr;
561 if(!reg) return;
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if(cur->regmap[hr]==reg) {
564 cur->isconst|=1<<hr;
565 cur->constmap[hr]=value;
566 }
567 else if((cur->regmap[hr]^64)==reg) {
568 cur->isconst|=1<<hr;
569 cur->constmap[hr]=value>>32;
570 }
571 }
572}
573
574void clear_const(struct regstat *cur,signed char reg)
575{
576 int hr;
577 if(!reg) return;
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->regmap[hr]&63)==reg) {
580 cur->isconst&=~(1<<hr);
581 }
582 }
583}
584
585int is_const(struct regstat *cur,signed char reg)
586{
587 int hr;
588 if(!reg) return 1;
589 for (hr=0;hr<HOST_REGS;hr++) {
590 if((cur->regmap[hr]&63)==reg) {
591 return (cur->isconst>>hr)&1;
592 }
593 }
594 return 0;
595}
596uint64_t get_const(struct regstat *cur,signed char reg)
597{
598 int hr;
599 if(!reg) return 0;
600 for (hr=0;hr<HOST_REGS;hr++) {
601 if(cur->regmap[hr]==reg) {
602 return cur->constmap[hr];
603 }
604 }
605 printf("Unknown constant in r%d\n",reg);
606 exit(1);
607}
608
609// Least soon needed registers
610// Look at the next ten instructions and see which registers
611// will be used. Try not to reallocate these.
612void lsn(u_char hsn[], int i, int *preferred_reg)
613{
614 int j;
615 int b=-1;
616 for(j=0;j<9;j++)
617 {
618 if(i+j>=slen) {
619 j=slen-i-1;
620 break;
621 }
622 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
623 {
624 // Don't go past an unconditonal jump
625 j++;
626 break;
627 }
628 }
629 for(;j>=0;j--)
630 {
631 if(rs1[i+j]) hsn[rs1[i+j]]=j;
632 if(rs2[i+j]) hsn[rs2[i+j]]=j;
633 if(rt1[i+j]) hsn[rt1[i+j]]=j;
634 if(rt2[i+j]) hsn[rt2[i+j]]=j;
635 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
636 // Stores can allocate zero
637 hsn[rs1[i+j]]=j;
638 hsn[rs2[i+j]]=j;
639 }
640 // On some architectures stores need invc_ptr
641 #if defined(HOST_IMM8)
b9b61529 642 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 643 hsn[INVCP]=j;
644 }
645 #endif
646 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
647 {
648 hsn[CCREG]=j;
649 b=j;
650 }
651 }
652 if(b>=0)
653 {
654 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
655 {
656 // Follow first branch
657 int t=(ba[i+b]-start)>>2;
658 j=7-b;if(t+j>=slen) j=slen-t-1;
659 for(;j>=0;j--)
660 {
661 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
662 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
663 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
664 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
665 }
666 }
667 // TODO: preferred register based on backward branch
668 }
669 // Delay slot should preferably not overwrite branch conditions or cycle count
670 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
671 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
672 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
673 hsn[CCREG]=1;
674 // ...or hash tables
675 hsn[RHASH]=1;
676 hsn[RHTBL]=1;
677 }
678 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 679 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 680 hsn[FTEMP]=0;
681 }
682 // Load L/R also uses FTEMP as a temporary register
683 if(itype[i]==LOADLR) {
684 hsn[FTEMP]=0;
685 }
b7918751 686 // Also SWL/SWR/SDL/SDR
687 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 688 hsn[FTEMP]=0;
689 }
690 // Don't remove the TLB registers either
b9b61529 691 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 692 hsn[TLREG]=0;
693 }
694 // Don't remove the miniht registers
695 if(itype[i]==UJUMP||itype[i]==RJUMP)
696 {
697 hsn[RHASH]=0;
698 hsn[RHTBL]=0;
699 }
700}
701
702// We only want to allocate registers if we're going to use them again soon
703int needed_again(int r, int i)
704{
705 int j;
706 int b=-1;
707 int rn=10;
708 int hr;
709 u_char hsn[MAXREG+1];
710 int preferred_reg;
711
712 memset(hsn,10,sizeof(hsn));
713 lsn(hsn,i,&preferred_reg);
714
715 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
716 {
717 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
718 return 0; // Don't need any registers if exiting the block
719 }
720 for(j=0;j<9;j++)
721 {
722 if(i+j>=slen) {
723 j=slen-i-1;
724 break;
725 }
726 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
727 {
728 // Don't go past an unconditonal jump
729 j++;
730 break;
731 }
1e973cb0 732 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 733 {
734 break;
735 }
736 }
737 for(;j>=1;j--)
738 {
739 if(rs1[i+j]==r) rn=j;
740 if(rs2[i+j]==r) rn=j;
741 if((unneeded_reg[i+j]>>r)&1) rn=10;
742 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
743 {
744 b=j;
745 }
746 }
747 /*
748 if(b>=0)
749 {
750 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
751 {
752 // Follow first branch
753 int o=rn;
754 int t=(ba[i+b]-start)>>2;
755 j=7-b;if(t+j>=slen) j=slen-t-1;
756 for(;j>=0;j--)
757 {
758 if(!((unneeded_reg[t+j]>>r)&1)) {
759 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
760 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
761 }
762 else rn=o;
763 }
764 }
765 }*/
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(hr!=EXCLUDE_REG) {
768 if(rn<hsn[hr]) return 1;
769 }
770 }
771 return 0;
772}
773
774// Try to match register allocations at the end of a loop with those
775// at the beginning
776int loop_reg(int i, int r, int hr)
777{
778 int j,k;
779 for(j=0;j<9;j++)
780 {
781 if(i+j>=slen) {
782 j=slen-i-1;
783 break;
784 }
785 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
786 {
787 // Don't go past an unconditonal jump
788 j++;
789 break;
790 }
791 }
792 k=0;
793 if(i>0){
794 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
795 k--;
796 }
797 for(;k<j;k++)
798 {
799 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
800 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
801 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
802 {
803 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
804 {
805 int t=(ba[i+k]-start)>>2;
806 int reg=get_reg(regs[t].regmap_entry,r);
807 if(reg>=0) return reg;
808 //reg=get_reg(regs[t+1].regmap_entry,r);
809 //if(reg>=0) return reg;
810 }
811 }
812 }
813 return hr;
814}
815
816
817// Allocate every register, preserving source/target regs
818void alloc_all(struct regstat *cur,int i)
819{
820 int hr;
821
822 for(hr=0;hr<HOST_REGS;hr++) {
823 if(hr!=EXCLUDE_REG) {
824 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
825 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
826 {
827 cur->regmap[hr]=-1;
828 cur->dirty&=~(1<<hr);
829 }
830 // Don't need zeros
831 if((cur->regmap[hr]&63)==0)
832 {
833 cur->regmap[hr]=-1;
834 cur->dirty&=~(1<<hr);
835 }
836 }
837 }
838}
839
840
841void div64(int64_t dividend,int64_t divisor)
842{
843 lo=dividend/divisor;
844 hi=dividend%divisor;
845 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
846 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
847}
848void divu64(uint64_t dividend,uint64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855
856void mult64(uint64_t m1,uint64_t m2)
857{
858 unsigned long long int op1, op2, op3, op4;
859 unsigned long long int result1, result2, result3, result4;
860 unsigned long long int temp1, temp2, temp3, temp4;
861 int sign = 0;
862
863 if (m1 < 0)
864 {
865 op2 = -m1;
866 sign = 1 - sign;
867 }
868 else op2 = m1;
869 if (m2 < 0)
870 {
871 op4 = -m2;
872 sign = 1 - sign;
873 }
874 else op4 = m2;
875
876 op1 = op2 & 0xFFFFFFFF;
877 op2 = (op2 >> 32) & 0xFFFFFFFF;
878 op3 = op4 & 0xFFFFFFFF;
879 op4 = (op4 >> 32) & 0xFFFFFFFF;
880
881 temp1 = op1 * op3;
882 temp2 = (temp1 >> 32) + op1 * op4;
883 temp3 = op2 * op3;
884 temp4 = (temp3 >> 32) + op2 * op4;
885
886 result1 = temp1 & 0xFFFFFFFF;
887 result2 = temp2 + (temp3 & 0xFFFFFFFF);
888 result3 = (result2 >> 32) + temp4;
889 result4 = (result3 >> 32);
890
891 lo = result1 | (result2 << 32);
892 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
893 if (sign)
894 {
895 hi = ~hi;
896 if (!lo) hi++;
897 else lo = ~lo + 1;
898 }
899}
900
901void multu64(uint64_t m1,uint64_t m2)
902{
903 unsigned long long int op1, op2, op3, op4;
904 unsigned long long int result1, result2, result3, result4;
905 unsigned long long int temp1, temp2, temp3, temp4;
906
907 op1 = m1 & 0xFFFFFFFF;
908 op2 = (m1 >> 32) & 0xFFFFFFFF;
909 op3 = m2 & 0xFFFFFFFF;
910 op4 = (m2 >> 32) & 0xFFFFFFFF;
911
912 temp1 = op1 * op3;
913 temp2 = (temp1 >> 32) + op1 * op4;
914 temp3 = op2 * op3;
915 temp4 = (temp3 >> 32) + op2 * op4;
916
917 result1 = temp1 & 0xFFFFFFFF;
918 result2 = temp2 + (temp3 & 0xFFFFFFFF);
919 result3 = (result2 >> 32) + temp4;
920 result4 = (result3 >> 32);
921
922 lo = result1 | (result2 << 32);
923 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
924
925 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
926 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
927}
928
929uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
930{
931 if(bits) {
932 original<<=64-bits;
933 original>>=64-bits;
934 loaded<<=bits;
935 original|=loaded;
936 }
937 else original=loaded;
938 return original;
939}
940uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
941{
942 if(bits^56) {
943 original>>=64-(bits^56);
944 original<<=64-(bits^56);
945 loaded>>=bits^56;
946 original|=loaded;
947 }
948 else original=loaded;
949 return original;
950}
951
952#ifdef __i386__
953#include "assem_x86.c"
954#endif
955#ifdef __x86_64__
956#include "assem_x64.c"
957#endif
958#ifdef __arm__
959#include "assem_arm.c"
960#endif
961
962// Add virtual address mapping to linked list
963void ll_add(struct ll_entry **head,int vaddr,void *addr)
964{
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
969 new_entry->reg32=0;
970 new_entry->addr=addr;
971 new_entry->next=*head;
972 *head=new_entry;
973}
974
975// Add virtual address mapping for 32-bit compiled block
976void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
977{
7139f3c8 978 ll_add(head,vaddr,addr);
979#ifndef FORCE32
980 (*head)->reg32=reg32;
981#endif
57871462 982}
983
984// Check if an address is already compiled
985// but don't return addresses which are about to expire from the cache
986void *check_addr(u_int vaddr)
987{
988 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
989 if(ht_bin[0]==vaddr) {
990 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
991 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
992 }
993 if(ht_bin[2]==vaddr) {
994 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
995 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
996 }
94d23bb9 997 u_int page=get_page(vaddr);
57871462 998 struct ll_entry *head;
999 head=jump_in[page];
1000 while(head!=NULL) {
1001 if(head->vaddr==vaddr&&head->reg32==0) {
1002 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1003 // Update existing entry with current address
1004 if(ht_bin[0]==vaddr) {
1005 ht_bin[1]=(int)head->addr;
1006 return head->addr;
1007 }
1008 if(ht_bin[2]==vaddr) {
1009 ht_bin[3]=(int)head->addr;
1010 return head->addr;
1011 }
1012 // Insert into hash table with low priority.
1013 // Don't evict existing entries, as they are probably
1014 // addresses that are being accessed frequently.
1015 if(ht_bin[0]==-1) {
1016 ht_bin[1]=(int)head->addr;
1017 ht_bin[0]=vaddr;
1018 }else if(ht_bin[2]==-1) {
1019 ht_bin[3]=(int)head->addr;
1020 ht_bin[2]=vaddr;
1021 }
1022 return head->addr;
1023 }
1024 }
1025 head=head->next;
1026 }
1027 return 0;
1028}
1029
1030void remove_hash(int vaddr)
1031{
1032 //printf("remove hash: %x\n",vaddr);
1033 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1034 if(ht_bin[2]==vaddr) {
1035 ht_bin[2]=ht_bin[3]=-1;
1036 }
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[0]=ht_bin[2];
1039 ht_bin[1]=ht_bin[3];
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042}
1043
1044void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1045{
1046 struct ll_entry *next;
1047 while(*head) {
1048 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1049 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1050 {
1051 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1052 remove_hash((*head)->vaddr);
1053 next=(*head)->next;
1054 free(*head);
1055 *head=next;
1056 }
1057 else
1058 {
1059 head=&((*head)->next);
1060 }
1061 }
1062}
1063
1064// Remove all entries from linked list
1065void ll_clear(struct ll_entry **head)
1066{
1067 struct ll_entry *cur;
1068 struct ll_entry *next;
1069 if(cur=*head) {
1070 *head=0;
1071 while(cur) {
1072 next=cur->next;
1073 free(cur);
1074 cur=next;
1075 }
1076 }
1077}
1078
1079// Dereference the pointers and remove if it matches
1080void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1081{
f76eeef9 1082 u_int old_host_addr=0;
57871462 1083 while(head) {
1084 int ptr=get_pointer(head->addr);
1085 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1086 if(((ptr>>shift)==(addr>>shift)) ||
1087 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1088 {
5088bb70 1089 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1090 u_int host_addr=(u_int)kill_pointer(head->addr);
1091
1092 if((host_addr>>12)!=(old_host_addr>>12)) {
1093 #ifdef __arm__
1094 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1095 #endif
1096 old_host_addr=host_addr;
1097 }
57871462 1098 }
1099 head=head->next;
1100 }
f76eeef9 1101 #ifdef __arm__
1102 if (old_host_addr)
1103 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1104 #endif
57871462 1105}
1106
1107// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1108void invalidate_page(u_int page)
57871462 1109{
57871462 1110 struct ll_entry *head;
1111 struct ll_entry *next;
f76eeef9 1112 u_int old_host_addr=0;
57871462 1113 head=jump_in[page];
1114 jump_in[page]=0;
1115 while(head!=NULL) {
1116 inv_debug("INVALIDATE: %x\n",head->vaddr);
1117 remove_hash(head->vaddr);
1118 next=head->next;
1119 free(head);
1120 head=next;
1121 }
1122 head=jump_out[page];
1123 jump_out[page]=0;
1124 while(head!=NULL) {
1125 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1126 u_int host_addr=(u_int)kill_pointer(head->addr);
1127
1128 if((host_addr>>12)!=(old_host_addr>>12)) {
1129 #ifdef __arm__
1130 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1131 #endif
1132 old_host_addr=host_addr;
1133 }
57871462 1134 next=head->next;
1135 free(head);
1136 head=next;
1137 }
f76eeef9 1138 #ifdef __arm__
1139 if (old_host_addr)
1140 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1141 #endif
57871462 1142}
1143void invalidate_block(u_int block)
1144{
94d23bb9 1145 u_int page=get_page(block<<12);
1146 u_int vpage=get_vpage(block<<12);
57871462 1147 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1148 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1149 u_int first,last;
1150 first=last=page;
1151 struct ll_entry *head;
1152 head=jump_dirty[vpage];
1153 //printf("page=%d vpage=%d\n",page,vpage);
1154 while(head!=NULL) {
1155 u_int start,end;
1156 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1157 get_bounds((int)head->addr,&start,&end);
1158 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1159 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1160 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1161 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1162 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1163 }
1164 }
90ae6d4e 1165#ifndef DISABLE_TLB
57871462 1166 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1167 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1168 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1169 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1170 }
1171 }
90ae6d4e 1172#endif
57871462 1173 }
1174 head=head->next;
1175 }
1176 //printf("first=%d last=%d\n",first,last);
f76eeef9 1177 invalidate_page(page);
57871462 1178 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1179 assert(last<page+5);
1180 // Invalidate the adjacent pages if a block crosses a 4K boundary
1181 while(first<page) {
1182 invalidate_page(first);
1183 first++;
1184 }
1185 for(first=page+1;first<last;first++) {
1186 invalidate_page(first);
1187 }
1188
1189 // Don't trap writes
1190 invalid_code[block]=1;
94d23bb9 1191#ifndef DISABLE_TLB
57871462 1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1200 }
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1202#endif
f76eeef9 1203
57871462 1204 #ifdef USE_MINI_HT
1205 memset(mini_ht,-1,sizeof(mini_ht));
1206 #endif
1207}
1208void invalidate_addr(u_int addr)
1209{
1210 invalidate_block(addr>>12);
1211}
1212void invalidate_all_pages()
1213{
1214 u_int page,n;
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1221 }
1222 #ifdef __arm__
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1224 #endif
1225 #ifdef USE_MINI_HT
1226 memset(mini_ht,-1,sizeof(mini_ht));
1227 #endif
94d23bb9 1228 #ifndef DISABLE_TLB
57871462 1229 // TLB
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1235 }
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1238 }
1239 tlb_hacks();
94d23bb9 1240 #endif
57871462 1241}
1242
1243// Add an entry to jump_out after making a link
1244void add_link(u_int vaddr,void *src)
1245{
94d23bb9 1246 u_int page=get_page(vaddr);
57871462 1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1251}
1252
1253// If a code block was found to be unmodified (bit was set in
1254// restore_candidate) and it remains unmodified (bit is clear
1255// in invalid_code) then move the entries for that 4K page from
1256// the dirty list to the clean list.
1257void clean_blocks(u_int page)
1258{
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1262 while(head!=NULL) {
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1266 u_int start,end;
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1269 u_int i;
1270 u_int inv=0;
1271 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1272 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1275 }
1276 }
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1281 }
4cb76aa4 1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1283 inv=1;
1284 }
1285 if(!inv) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1288 u_int ppage=page;
94d23bb9 1289#ifndef DISABLE_TLB
57871462 1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1291#endif
57871462 1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1297 if(!head->reg32) {
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1300 }
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1303 }
1304 }
1305 }
1306 }
1307 }
1308 }
1309 }
1310 head=head->next;
1311 }
1312}
1313
1314
1315void mov_alloc(struct regstat *current,int i)
1316{
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1322 } else {
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1326 }
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1330}
1331
1332void shiftimm_alloc(struct regstat *current,int i)
1333{
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1337 {
1338 if(rt1[i]) {
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1340 else lt1[i]=rs1[i];
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1344 }
1345 }
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1347 {
1348 if(rt1[i]) {
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1353 }
1354 }
1355 if(opcode2[i]==0x3c) // DSLL32
1356 {
1357 if(rt1[i]) {
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1362 }
1363 }
1364 if(opcode2[i]==0x3e) // DSRL32
1365 {
1366 if(rt1[i]) {
1367 alloc_reg64(current,i,rs1[i]);
1368 if(imm[i]==32) {
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1371 } else {
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1374 }
1375 dirty_reg(current,rt1[i]);
1376 }
1377 }
1378 if(opcode2[i]==0x3f) // DSRA32
1379 {
1380 if(rt1[i]) {
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1385 }
1386 }
1387}
1388
1389void shift_alloc(struct regstat *current,int i)
1390{
1391 if(rt1[i]) {
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1393 {
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1406 }
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1411 }
1412}
1413
1414void alu_alloc(struct regstat *current,int i)
1415{
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1417 if(rt1[i]) {
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1421 }
1422 else {
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1425 }
1426 alloc_reg(current,i,rt1[i]);
1427 }
1428 current->is32|=1LL<<rt1[i];
1429 }
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1431 if(rt1[i]) {
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433 {
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1437 } else {
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1441 }
1442 }
1443 current->is32|=1LL<<rt1[i];
1444 }
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1446 if(rt1[i]) {
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1450 }
1451 else
1452 {
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1455 }
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1458 {
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1461 }
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1466 }
1467 else
1468 {
1469 // Is is really worth it to keep 64-bit values in registers?
1470 #ifdef NATIVE_64BIT
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473 #endif
1474 }
1475 }
1476 current->is32&=~(1LL<<rt1[i]);
1477 } else {
1478 current->is32|=1LL<<rt1[i];
1479 }
1480 }
1481 }
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1483 if(rt1[i]) {
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1489 } else {
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1493 }
1494 }
1495 else {
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1506 }
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1512 }
1513 }
1514 }
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1517 } else if(rs1[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1521 } else if(rs2[i]) {
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1525 } else {
1526 current->is32|=1LL<<rt1[i];
1527 }
1528 }
1529 }
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1534}
1535
1536void imm16_alloc(struct regstat *current,int i)
1537{
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1539 else lt1[i]=rs1[i];
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1547 }
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1550 }
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1556 }
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1563 }
1564 }
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1571 }
1572 else clear_const(current,rt1[i]);
1573 }
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1578 }
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1581 }
1582 else {
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1585 }
1586 dirty_reg(current,rt1[i]);
1587}
1588
1589void load_alloc(struct regstat *current,int i)
1590{
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1595 if(rt1[i]) {
1596 alloc_reg(current,i,rt1[i]);
1597 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1598 {
1599 current->is32&=~(1LL<<rt1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 }
1602 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1603 {
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1606 alloc_all(current,i);
1607 alloc_reg64(current,i,FTEMP);
1608 }
1609 else current->is32|=1LL<<rt1[i];
1610 dirty_reg(current,rt1[i]);
1611 // If using TLB, need a register for pointer to the mapping table
1612 if(using_tlb) alloc_reg(current,i,TLREG);
1613 // LWL/LWR need a temporary register for the old value
1614 if(opcode[i]==0x22||opcode[i]==0x26)
1615 {
1616 alloc_reg(current,i,FTEMP);
1617 alloc_reg_temp(current,i,-1);
1618 }
1619 }
1620 else
1621 {
1622 // Load to r0 (dummy load)
1623 // but we still need a register to calculate the address
1624 alloc_reg_temp(current,i,-1);
1625 }
1626}
1627
1628void store_alloc(struct regstat *current,int i)
1629{
1630 clear_const(current,rs2[i]);
1631 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1632 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1633 alloc_reg(current,i,rs2[i]);
1634 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1635 alloc_reg64(current,i,rs2[i]);
1636 if(rs2[i]) alloc_reg(current,i,FTEMP);
1637 }
1638 // If using TLB, need a register for pointer to the mapping table
1639 if(using_tlb) alloc_reg(current,i,TLREG);
1640 #if defined(HOST_IMM8)
1641 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1642 else alloc_reg(current,i,INVCP);
1643 #endif
b7918751 1644 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1645 alloc_reg(current,i,FTEMP);
1646 }
1647 // We need a temporary register for address generation
1648 alloc_reg_temp(current,i,-1);
1649}
1650
1651void c1ls_alloc(struct regstat *current,int i)
1652{
1653 //clear_const(current,rs1[i]); // FIXME
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,CSREG); // Status
1657 alloc_reg(current,i,FTEMP);
1658 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1659 alloc_reg64(current,i,FTEMP);
1660 }
1661 // If using TLB, need a register for pointer to the mapping table
1662 if(using_tlb) alloc_reg(current,i,TLREG);
1663 #if defined(HOST_IMM8)
1664 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1665 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1666 alloc_reg(current,i,INVCP);
1667 #endif
1668 // We need a temporary register for address generation
1669 alloc_reg_temp(current,i,-1);
1670}
1671
b9b61529 1672void c2ls_alloc(struct regstat *current,int i)
1673{
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,FTEMP);
1677 // If using TLB, need a register for pointer to the mapping table
1678 if(using_tlb) alloc_reg(current,i,TLREG);
1679 #if defined(HOST_IMM8)
1680 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1681 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1682 alloc_reg(current,i,INVCP);
1683 #endif
1684 // We need a temporary register for address generation
1685 alloc_reg_temp(current,i,-1);
1686}
1687
57871462 1688#ifndef multdiv_alloc
1689void multdiv_alloc(struct regstat *current,int i)
1690{
1691 // case 0x18: MULT
1692 // case 0x19: MULTU
1693 // case 0x1A: DIV
1694 // case 0x1B: DIVU
1695 // case 0x1C: DMULT
1696 // case 0x1D: DMULTU
1697 // case 0x1E: DDIV
1698 // case 0x1F: DDIVU
1699 clear_const(current,rs1[i]);
1700 clear_const(current,rs2[i]);
1701 if(rs1[i]&&rs2[i])
1702 {
1703 if((opcode2[i]&4)==0) // 32-bit
1704 {
1705 current->u&=~(1LL<<HIREG);
1706 current->u&=~(1LL<<LOREG);
1707 alloc_reg(current,i,HIREG);
1708 alloc_reg(current,i,LOREG);
1709 alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 current->is32|=1LL<<HIREG;
1712 current->is32|=1LL<<LOREG;
1713 dirty_reg(current,HIREG);
1714 dirty_reg(current,LOREG);
1715 }
1716 else // 64-bit
1717 {
1718 current->u&=~(1LL<<HIREG);
1719 current->u&=~(1LL<<LOREG);
1720 current->uu&=~(1LL<<HIREG);
1721 current->uu&=~(1LL<<LOREG);
1722 alloc_reg64(current,i,HIREG);
1723 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1724 alloc_reg64(current,i,rs1[i]);
1725 alloc_reg64(current,i,rs2[i]);
1726 alloc_all(current,i);
1727 current->is32&=~(1LL<<HIREG);
1728 current->is32&=~(1LL<<LOREG);
1729 dirty_reg(current,HIREG);
1730 dirty_reg(current,LOREG);
1731 }
1732 }
1733 else
1734 {
1735 // Multiply by zero is zero.
1736 // MIPS does not have a divide by zero exception.
1737 // The result is undefined, we return zero.
1738 alloc_reg(current,i,HIREG);
1739 alloc_reg(current,i,LOREG);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1744 }
1745}
1746#endif
1747
1748void cop0_alloc(struct regstat *current,int i)
1749{
1750 if(opcode2[i]==0) // MFC0
1751 {
1752 if(rt1[i]) {
1753 clear_const(current,rt1[i]);
1754 alloc_all(current,i);
1755 alloc_reg(current,i,rt1[i]);
1756 current->is32|=1LL<<rt1[i];
1757 dirty_reg(current,rt1[i]);
1758 }
1759 }
1760 else if(opcode2[i]==4) // MTC0
1761 {
1762 if(rs1[i]){
1763 clear_const(current,rs1[i]);
1764 alloc_reg(current,i,rs1[i]);
1765 alloc_all(current,i);
1766 }
1767 else {
1768 alloc_all(current,i); // FIXME: Keep r0
1769 current->u&=~1LL;
1770 alloc_reg(current,i,0);
1771 }
1772 }
1773 else
1774 {
1775 // TLBR/TLBWI/TLBWR/TLBP/ERET
1776 assert(opcode2[i]==0x10);
1777 alloc_all(current,i);
1778 }
1779}
1780
1781void cop1_alloc(struct regstat *current,int i)
1782{
1783 alloc_reg(current,i,CSREG); // Load status
1784 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1785 {
1786 assert(rt1[i]);
1787 clear_const(current,rt1[i]);
1788 if(opcode2[i]==1) {
1789 alloc_reg64(current,i,rt1[i]); // DMFC1
1790 current->is32&=~(1LL<<rt1[i]);
1791 }else{
1792 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1793 current->is32|=1LL<<rt1[i];
1794 }
1795 dirty_reg(current,rt1[i]);
1796 alloc_reg_temp(current,i,-1);
1797 }
1798 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1799 {
1800 if(rs1[i]){
1801 clear_const(current,rs1[i]);
1802 if(opcode2[i]==5)
1803 alloc_reg64(current,i,rs1[i]); // DMTC1
1804 else
1805 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1806 alloc_reg_temp(current,i,-1);
1807 }
1808 else {
1809 current->u&=~1LL;
1810 alloc_reg(current,i,0);
1811 alloc_reg_temp(current,i,-1);
1812 }
1813 }
1814}
1815void fconv_alloc(struct regstat *current,int i)
1816{
1817 alloc_reg(current,i,CSREG); // Load status
1818 alloc_reg_temp(current,i,-1);
1819}
1820void float_alloc(struct regstat *current,int i)
1821{
1822 alloc_reg(current,i,CSREG); // Load status
1823 alloc_reg_temp(current,i,-1);
1824}
b9b61529 1825void c2op_alloc(struct regstat *current,int i)
1826{
1827 alloc_reg_temp(current,i,-1);
1828}
57871462 1829void fcomp_alloc(struct regstat *current,int i)
1830{
1831 alloc_reg(current,i,CSREG); // Load status
1832 alloc_reg(current,i,FSREG); // Load flags
1833 dirty_reg(current,FSREG); // Flag will be modified
1834 alloc_reg_temp(current,i,-1);
1835}
1836
1837void syscall_alloc(struct regstat *current,int i)
1838{
1839 alloc_cc(current,i);
1840 dirty_reg(current,CCREG);
1841 alloc_all(current,i);
1842 current->isconst=0;
1843}
1844
1845void delayslot_alloc(struct regstat *current,int i)
1846{
1847 switch(itype[i]) {
1848 case UJUMP:
1849 case CJUMP:
1850 case SJUMP:
1851 case RJUMP:
1852 case FJUMP:
1853 case SYSCALL:
7139f3c8 1854 case HLECALL:
57871462 1855 case SPAN:
1856 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1857 printf("Disabled speculative precompilation\n");
1858 stop_after_jal=1;
1859 break;
1860 case IMM16:
1861 imm16_alloc(current,i);
1862 break;
1863 case LOAD:
1864 case LOADLR:
1865 load_alloc(current,i);
1866 break;
1867 case STORE:
1868 case STORELR:
1869 store_alloc(current,i);
1870 break;
1871 case ALU:
1872 alu_alloc(current,i);
1873 break;
1874 case SHIFT:
1875 shift_alloc(current,i);
1876 break;
1877 case MULTDIV:
1878 multdiv_alloc(current,i);
1879 break;
1880 case SHIFTIMM:
1881 shiftimm_alloc(current,i);
1882 break;
1883 case MOV:
1884 mov_alloc(current,i);
1885 break;
1886 case COP0:
1887 cop0_alloc(current,i);
1888 break;
1889 case COP1:
b9b61529 1890 case COP2:
57871462 1891 cop1_alloc(current,i);
1892 break;
1893 case C1LS:
1894 c1ls_alloc(current,i);
1895 break;
b9b61529 1896 case C2LS:
1897 c2ls_alloc(current,i);
1898 break;
57871462 1899 case FCONV:
1900 fconv_alloc(current,i);
1901 break;
1902 case FLOAT:
1903 float_alloc(current,i);
1904 break;
1905 case FCOMP:
1906 fcomp_alloc(current,i);
1907 break;
b9b61529 1908 case C2OP:
1909 c2op_alloc(current,i);
1910 break;
57871462 1911 }
1912}
1913
1914// Special case where a branch and delay slot span two pages in virtual memory
1915static void pagespan_alloc(struct regstat *current,int i)
1916{
1917 current->isconst=0;
1918 current->wasconst=0;
1919 regs[i].wasconst=0;
1920 alloc_all(current,i);
1921 alloc_cc(current,i);
1922 dirty_reg(current,CCREG);
1923 if(opcode[i]==3) // JAL
1924 {
1925 alloc_reg(current,i,31);
1926 dirty_reg(current,31);
1927 }
1928 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1929 {
1930 alloc_reg(current,i,rs1[i]);
5067f341 1931 if (rt1[i]!=0) {
1932 alloc_reg(current,i,rt1[i]);
1933 dirty_reg(current,rt1[i]);
57871462 1934 }
1935 }
1936 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1937 {
1938 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1939 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1940 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1941 {
1942 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1943 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1944 }
1945 }
1946 else
1947 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1948 {
1949 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1950 if(!((current->is32>>rs1[i])&1))
1951 {
1952 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1953 }
1954 }
1955 else
1956 if(opcode[i]==0x11) // BC1
1957 {
1958 alloc_reg(current,i,FSREG);
1959 alloc_reg(current,i,CSREG);
1960 }
1961 //else ...
1962}
1963
1964add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1965{
1966 stubs[stubcount][0]=type;
1967 stubs[stubcount][1]=addr;
1968 stubs[stubcount][2]=retaddr;
1969 stubs[stubcount][3]=a;
1970 stubs[stubcount][4]=b;
1971 stubs[stubcount][5]=c;
1972 stubs[stubcount][6]=d;
1973 stubs[stubcount][7]=e;
1974 stubcount++;
1975}
1976
1977// Write out a single register
1978void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1979{
1980 int hr;
1981 for(hr=0;hr<HOST_REGS;hr++) {
1982 if(hr!=EXCLUDE_REG) {
1983 if((regmap[hr]&63)==r) {
1984 if((dirty>>hr)&1) {
1985 if(regmap[hr]<64) {
1986 emit_storereg(r,hr);
24385cae 1987#ifndef FORCE32
57871462 1988 if((is32>>regmap[hr])&1) {
1989 emit_sarimm(hr,31,hr);
1990 emit_storereg(r|64,hr);
1991 }
24385cae 1992#endif
57871462 1993 }else{
1994 emit_storereg(r|64,hr);
1995 }
1996 }
1997 }
1998 }
1999 }
2000}
2001
2002int mchecksum()
2003{
2004 //if(!tracedebug) return 0;
2005 int i;
2006 int sum=0;
2007 for(i=0;i<2097152;i++) {
2008 unsigned int temp=sum;
2009 sum<<=1;
2010 sum|=(~temp)>>31;
2011 sum^=((u_int *)rdram)[i];
2012 }
2013 return sum;
2014}
2015int rchecksum()
2016{
2017 int i;
2018 int sum=0;
2019 for(i=0;i<64;i++)
2020 sum^=((u_int *)reg)[i];
2021 return sum;
2022}
57871462 2023void rlist()
2024{
2025 int i;
2026 printf("TRACE: ");
2027 for(i=0;i<32;i++)
2028 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2029 printf("\n");
3d624f89 2030#ifndef DISABLE_COP1
57871462 2031 printf("TRACE: ");
2032 for(i=0;i<32;i++)
2033 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2034 printf("\n");
3d624f89 2035#endif
57871462 2036}
2037
2038void enabletrace()
2039{
2040 tracedebug=1;
2041}
2042
2043void memdebug(int i)
2044{
2045 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2046 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2047 //rlist();
2048 //if(tracedebug) {
2049 //if(Count>=-2084597794) {
2050 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2051 //if(0) {
2052 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2053 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2054 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2055 rlist();
2056 #ifdef __i386__
2057 printf("TRACE: %x\n",(&i)[-1]);
2058 #endif
2059 #ifdef __arm__
2060 int j;
2061 printf("TRACE: %x \n",(&j)[10]);
2062 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2063 #endif
2064 //fflush(stdout);
2065 }
2066 //printf("TRACE: %x\n",(&i)[-1]);
2067}
2068
2069void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2070{
2071 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2072}
2073
2074void alu_assemble(int i,struct regstat *i_regs)
2075{
2076 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2077 if(rt1[i]) {
2078 signed char s1,s2,t;
2079 t=get_reg(i_regs->regmap,rt1[i]);
2080 if(t>=0) {
2081 s1=get_reg(i_regs->regmap,rs1[i]);
2082 s2=get_reg(i_regs->regmap,rs2[i]);
2083 if(rs1[i]&&rs2[i]) {
2084 assert(s1>=0);
2085 assert(s2>=0);
2086 if(opcode2[i]&2) emit_sub(s1,s2,t);
2087 else emit_add(s1,s2,t);
2088 }
2089 else if(rs1[i]) {
2090 if(s1>=0) emit_mov(s1,t);
2091 else emit_loadreg(rs1[i],t);
2092 }
2093 else if(rs2[i]) {
2094 if(s2>=0) {
2095 if(opcode2[i]&2) emit_neg(s2,t);
2096 else emit_mov(s2,t);
2097 }
2098 else {
2099 emit_loadreg(rs2[i],t);
2100 if(opcode2[i]&2) emit_neg(t,t);
2101 }
2102 }
2103 else emit_zeroreg(t);
2104 }
2105 }
2106 }
2107 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2108 if(rt1[i]) {
2109 signed char s1l,s2l,s1h,s2h,tl,th;
2110 tl=get_reg(i_regs->regmap,rt1[i]);
2111 th=get_reg(i_regs->regmap,rt1[i]|64);
2112 if(tl>=0) {
2113 s1l=get_reg(i_regs->regmap,rs1[i]);
2114 s2l=get_reg(i_regs->regmap,rs2[i]);
2115 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2116 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2117 if(rs1[i]&&rs2[i]) {
2118 assert(s1l>=0);
2119 assert(s2l>=0);
2120 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2121 else emit_adds(s1l,s2l,tl);
2122 if(th>=0) {
2123 #ifdef INVERTED_CARRY
2124 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2125 #else
2126 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2127 #endif
2128 else emit_add(s1h,s2h,th);
2129 }
2130 }
2131 else if(rs1[i]) {
2132 if(s1l>=0) emit_mov(s1l,tl);
2133 else emit_loadreg(rs1[i],tl);
2134 if(th>=0) {
2135 if(s1h>=0) emit_mov(s1h,th);
2136 else emit_loadreg(rs1[i]|64,th);
2137 }
2138 }
2139 else if(rs2[i]) {
2140 if(s2l>=0) {
2141 if(opcode2[i]&2) emit_negs(s2l,tl);
2142 else emit_mov(s2l,tl);
2143 }
2144 else {
2145 emit_loadreg(rs2[i],tl);
2146 if(opcode2[i]&2) emit_negs(tl,tl);
2147 }
2148 if(th>=0) {
2149 #ifdef INVERTED_CARRY
2150 if(s2h>=0) emit_mov(s2h,th);
2151 else emit_loadreg(rs2[i]|64,th);
2152 if(opcode2[i]&2) {
2153 emit_adcimm(-1,th); // x86 has inverted carry flag
2154 emit_not(th,th);
2155 }
2156 #else
2157 if(opcode2[i]&2) {
2158 if(s2h>=0) emit_rscimm(s2h,0,th);
2159 else {
2160 emit_loadreg(rs2[i]|64,th);
2161 emit_rscimm(th,0,th);
2162 }
2163 }else{
2164 if(s2h>=0) emit_mov(s2h,th);
2165 else emit_loadreg(rs2[i]|64,th);
2166 }
2167 #endif
2168 }
2169 }
2170 else {
2171 emit_zeroreg(tl);
2172 if(th>=0) emit_zeroreg(th);
2173 }
2174 }
2175 }
2176 }
2177 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2178 if(rt1[i]) {
2179 signed char s1l,s1h,s2l,s2h,t;
2180 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2181 {
2182 t=get_reg(i_regs->regmap,rt1[i]);
2183 //assert(t>=0);
2184 if(t>=0) {
2185 s1l=get_reg(i_regs->regmap,rs1[i]);
2186 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2187 s2l=get_reg(i_regs->regmap,rs2[i]);
2188 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2189 if(rs2[i]==0) // rx<r0
2190 {
2191 assert(s1h>=0);
2192 if(opcode2[i]==0x2a) // SLT
2193 emit_shrimm(s1h,31,t);
2194 else // SLTU (unsigned can not be less than zero)
2195 emit_zeroreg(t);
2196 }
2197 else if(rs1[i]==0) // r0<rx
2198 {
2199 assert(s2h>=0);
2200 if(opcode2[i]==0x2a) // SLT
2201 emit_set_gz64_32(s2h,s2l,t);
2202 else // SLTU (set if not zero)
2203 emit_set_nz64_32(s2h,s2l,t);
2204 }
2205 else {
2206 assert(s1l>=0);assert(s1h>=0);
2207 assert(s2l>=0);assert(s2h>=0);
2208 if(opcode2[i]==0x2a) // SLT
2209 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2210 else // SLTU
2211 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2212 }
2213 }
2214 } else {
2215 t=get_reg(i_regs->regmap,rt1[i]);
2216 //assert(t>=0);
2217 if(t>=0) {
2218 s1l=get_reg(i_regs->regmap,rs1[i]);
2219 s2l=get_reg(i_regs->regmap,rs2[i]);
2220 if(rs2[i]==0) // rx<r0
2221 {
2222 assert(s1l>=0);
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1l,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2226 emit_zeroreg(t);
2227 }
2228 else if(rs1[i]==0) // r0<rx
2229 {
2230 assert(s2l>=0);
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz32(s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz32(s2l,t);
2235 }
2236 else{
2237 assert(s1l>=0);assert(s2l>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_if_less32(s1l,s2l,t);
2240 else // SLTU
2241 emit_set_if_carry32(s1l,s2l,t);
2242 }
2243 }
2244 }
2245 }
2246 }
2247 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2248 if(rt1[i]) {
2249 signed char s1l,s1h,s2l,s2h,th,tl;
2250 tl=get_reg(i_regs->regmap,rt1[i]);
2251 th=get_reg(i_regs->regmap,rt1[i]|64);
2252 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2253 {
2254 assert(tl>=0);
2255 if(tl>=0) {
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2258 s2l=get_reg(i_regs->regmap,rs2[i]);
2259 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2260 if(rs1[i]&&rs2[i]) {
2261 assert(s1l>=0);assert(s1h>=0);
2262 assert(s2l>=0);assert(s2h>=0);
2263 if(opcode2[i]==0x24) { // AND
2264 emit_and(s1l,s2l,tl);
2265 emit_and(s1h,s2h,th);
2266 } else
2267 if(opcode2[i]==0x25) { // OR
2268 emit_or(s1l,s2l,tl);
2269 emit_or(s1h,s2h,th);
2270 } else
2271 if(opcode2[i]==0x26) { // XOR
2272 emit_xor(s1l,s2l,tl);
2273 emit_xor(s1h,s2h,th);
2274 } else
2275 if(opcode2[i]==0x27) { // NOR
2276 emit_or(s1l,s2l,tl);
2277 emit_or(s1h,s2h,th);
2278 emit_not(tl,tl);
2279 emit_not(th,th);
2280 }
2281 }
2282 else
2283 {
2284 if(opcode2[i]==0x24) { // AND
2285 emit_zeroreg(tl);
2286 emit_zeroreg(th);
2287 } else
2288 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2289 if(rs1[i]){
2290 if(s1l>=0) emit_mov(s1l,tl);
2291 else emit_loadreg(rs1[i],tl);
2292 if(s1h>=0) emit_mov(s1h,th);
2293 else emit_loadreg(rs1[i]|64,th);
2294 }
2295 else
2296 if(rs2[i]){
2297 if(s2l>=0) emit_mov(s2l,tl);
2298 else emit_loadreg(rs2[i],tl);
2299 if(s2h>=0) emit_mov(s2h,th);
2300 else emit_loadreg(rs2[i]|64,th);
2301 }
2302 else{
2303 emit_zeroreg(tl);
2304 emit_zeroreg(th);
2305 }
2306 } else
2307 if(opcode2[i]==0x27) { // NOR
2308 if(rs1[i]){
2309 if(s1l>=0) emit_not(s1l,tl);
2310 else{
2311 emit_loadreg(rs1[i],tl);
2312 emit_not(tl,tl);
2313 }
2314 if(s1h>=0) emit_not(s1h,th);
2315 else{
2316 emit_loadreg(rs1[i]|64,th);
2317 emit_not(th,th);
2318 }
2319 }
2320 else
2321 if(rs2[i]){
2322 if(s2l>=0) emit_not(s2l,tl);
2323 else{
2324 emit_loadreg(rs2[i],tl);
2325 emit_not(tl,tl);
2326 }
2327 if(s2h>=0) emit_not(s2h,th);
2328 else{
2329 emit_loadreg(rs2[i]|64,th);
2330 emit_not(th,th);
2331 }
2332 }
2333 else {
2334 emit_movimm(-1,tl);
2335 emit_movimm(-1,th);
2336 }
2337 }
2338 }
2339 }
2340 }
2341 else
2342 {
2343 // 32 bit
2344 if(tl>=0) {
2345 s1l=get_reg(i_regs->regmap,rs1[i]);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 if(rs1[i]&&rs2[i]) {
2348 assert(s1l>=0);
2349 assert(s2l>=0);
2350 if(opcode2[i]==0x24) { // AND
2351 emit_and(s1l,s2l,tl);
2352 } else
2353 if(opcode2[i]==0x25) { // OR
2354 emit_or(s1l,s2l,tl);
2355 } else
2356 if(opcode2[i]==0x26) { // XOR
2357 emit_xor(s1l,s2l,tl);
2358 } else
2359 if(opcode2[i]==0x27) { // NOR
2360 emit_or(s1l,s2l,tl);
2361 emit_not(tl,tl);
2362 }
2363 }
2364 else
2365 {
2366 if(opcode2[i]==0x24) { // AND
2367 emit_zeroreg(tl);
2368 } else
2369 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2370 if(rs1[i]){
2371 if(s1l>=0) emit_mov(s1l,tl);
2372 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2373 }
2374 else
2375 if(rs2[i]){
2376 if(s2l>=0) emit_mov(s2l,tl);
2377 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2378 }
2379 else emit_zeroreg(tl);
2380 } else
2381 if(opcode2[i]==0x27) { // NOR
2382 if(rs1[i]){
2383 if(s1l>=0) emit_not(s1l,tl);
2384 else {
2385 emit_loadreg(rs1[i],tl);
2386 emit_not(tl,tl);
2387 }
2388 }
2389 else
2390 if(rs2[i]){
2391 if(s2l>=0) emit_not(s2l,tl);
2392 else {
2393 emit_loadreg(rs2[i],tl);
2394 emit_not(tl,tl);
2395 }
2396 }
2397 else emit_movimm(-1,tl);
2398 }
2399 }
2400 }
2401 }
2402 }
2403 }
2404}
2405
2406void imm16_assemble(int i,struct regstat *i_regs)
2407{
2408 if (opcode[i]==0x0f) { // LUI
2409 if(rt1[i]) {
2410 signed char t;
2411 t=get_reg(i_regs->regmap,rt1[i]);
2412 //assert(t>=0);
2413 if(t>=0) {
2414 if(!((i_regs->isconst>>t)&1))
2415 emit_movimm(imm[i]<<16,t);
2416 }
2417 }
2418 }
2419 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2420 if(rt1[i]) {
2421 signed char s,t;
2422 t=get_reg(i_regs->regmap,rt1[i]);
2423 s=get_reg(i_regs->regmap,rs1[i]);
2424 if(rs1[i]) {
2425 //assert(t>=0);
2426 //assert(s>=0);
2427 if(t>=0) {
2428 if(!((i_regs->isconst>>t)&1)) {
2429 if(s<0) {
2430 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2431 emit_addimm(t,imm[i],t);
2432 }else{
2433 if(!((i_regs->wasconst>>s)&1))
2434 emit_addimm(s,imm[i],t);
2435 else
2436 emit_movimm(constmap[i][s]+imm[i],t);
2437 }
2438 }
2439 }
2440 } else {
2441 if(t>=0) {
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i],t);
2444 }
2445 }
2446 }
2447 }
2448 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2449 if(rt1[i]) {
2450 signed char sh,sl,th,tl;
2451 th=get_reg(i_regs->regmap,rt1[i]|64);
2452 tl=get_reg(i_regs->regmap,rt1[i]);
2453 sh=get_reg(i_regs->regmap,rs1[i]|64);
2454 sl=get_reg(i_regs->regmap,rs1[i]);
2455 if(tl>=0) {
2456 if(rs1[i]) {
2457 assert(sh>=0);
2458 assert(sl>=0);
2459 if(th>=0) {
2460 emit_addimm64_32(sh,sl,imm[i],th,tl);
2461 }
2462 else {
2463 emit_addimm(sl,imm[i],tl);
2464 }
2465 } else {
2466 emit_movimm(imm[i],tl);
2467 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2468 }
2469 }
2470 }
2471 }
2472 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2473 if(rt1[i]) {
2474 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2475 signed char sh,sl,t;
2476 t=get_reg(i_regs->regmap,rt1[i]);
2477 sh=get_reg(i_regs->regmap,rs1[i]|64);
2478 sl=get_reg(i_regs->regmap,rs1[i]);
2479 //assert(t>=0);
2480 if(t>=0) {
2481 if(rs1[i]>0) {
2482 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2483 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2484 if(opcode[i]==0x0a) { // SLTI
2485 if(sl<0) {
2486 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2487 emit_slti32(t,imm[i],t);
2488 }else{
2489 emit_slti32(sl,imm[i],t);
2490 }
2491 }
2492 else { // SLTIU
2493 if(sl<0) {
2494 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495 emit_sltiu32(t,imm[i],t);
2496 }else{
2497 emit_sltiu32(sl,imm[i],t);
2498 }
2499 }
2500 }else{ // 64-bit
2501 assert(sl>=0);
2502 if(opcode[i]==0x0a) // SLTI
2503 emit_slti64_32(sh,sl,imm[i],t);
2504 else // SLTIU
2505 emit_sltiu64_32(sh,sl,imm[i],t);
2506 }
2507 }else{
2508 // SLTI(U) with r0 is just stupid,
2509 // nonetheless examples can be found
2510 if(opcode[i]==0x0a) // SLTI
2511 if(0<imm[i]) emit_movimm(1,t);
2512 else emit_zeroreg(t);
2513 else // SLTIU
2514 {
2515 if(imm[i]) emit_movimm(1,t);
2516 else emit_zeroreg(t);
2517 }
2518 }
2519 }
2520 }
2521 }
2522 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2523 if(rt1[i]) {
2524 signed char sh,sl,th,tl;
2525 th=get_reg(i_regs->regmap,rt1[i]|64);
2526 tl=get_reg(i_regs->regmap,rt1[i]);
2527 sh=get_reg(i_regs->regmap,rs1[i]|64);
2528 sl=get_reg(i_regs->regmap,rs1[i]);
2529 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2530 if(opcode[i]==0x0c) //ANDI
2531 {
2532 if(rs1[i]) {
2533 if(sl<0) {
2534 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2535 emit_andimm(tl,imm[i],tl);
2536 }else{
2537 if(!((i_regs->wasconst>>sl)&1))
2538 emit_andimm(sl,imm[i],tl);
2539 else
2540 emit_movimm(constmap[i][sl]&imm[i],tl);
2541 }
2542 }
2543 else
2544 emit_zeroreg(tl);
2545 if(th>=0) emit_zeroreg(th);
2546 }
2547 else
2548 {
2549 if(rs1[i]) {
2550 if(sl<0) {
2551 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2552 }
2553 if(th>=0) {
2554 if(sh<0) {
2555 emit_loadreg(rs1[i]|64,th);
2556 }else{
2557 emit_mov(sh,th);
2558 }
2559 }
2560 if(opcode[i]==0x0d) //ORI
2561 if(sl<0) {
2562 emit_orimm(tl,imm[i],tl);
2563 }else{
2564 if(!((i_regs->wasconst>>sl)&1))
2565 emit_orimm(sl,imm[i],tl);
2566 else
2567 emit_movimm(constmap[i][sl]|imm[i],tl);
2568 }
2569 if(opcode[i]==0x0e) //XORI
2570 if(sl<0) {
2571 emit_xorimm(tl,imm[i],tl);
2572 }else{
2573 if(!((i_regs->wasconst>>sl)&1))
2574 emit_xorimm(sl,imm[i],tl);
2575 else
2576 emit_movimm(constmap[i][sl]^imm[i],tl);
2577 }
2578 }
2579 else {
2580 emit_movimm(imm[i],tl);
2581 if(th>=0) emit_zeroreg(th);
2582 }
2583 }
2584 }
2585 }
2586 }
2587}
2588
2589void shiftimm_assemble(int i,struct regstat *i_regs)
2590{
2591 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2592 {
2593 if(rt1[i]) {
2594 signed char s,t;
2595 t=get_reg(i_regs->regmap,rt1[i]);
2596 s=get_reg(i_regs->regmap,rs1[i]);
2597 //assert(t>=0);
2598 if(t>=0){
2599 if(rs1[i]==0)
2600 {
2601 emit_zeroreg(t);
2602 }
2603 else
2604 {
2605 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2606 if(imm[i]) {
2607 if(opcode2[i]==0) // SLL
2608 {
2609 emit_shlimm(s<0?t:s,imm[i],t);
2610 }
2611 if(opcode2[i]==2) // SRL
2612 {
2613 emit_shrimm(s<0?t:s,imm[i],t);
2614 }
2615 if(opcode2[i]==3) // SRA
2616 {
2617 emit_sarimm(s<0?t:s,imm[i],t);
2618 }
2619 }else{
2620 // Shift by zero
2621 if(s>=0 && s!=t) emit_mov(s,t);
2622 }
2623 }
2624 }
2625 //emit_storereg(rt1[i],t); //DEBUG
2626 }
2627 }
2628 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2629 {
2630 if(rt1[i]) {
2631 signed char sh,sl,th,tl;
2632 th=get_reg(i_regs->regmap,rt1[i]|64);
2633 tl=get_reg(i_regs->regmap,rt1[i]);
2634 sh=get_reg(i_regs->regmap,rs1[i]|64);
2635 sl=get_reg(i_regs->regmap,rs1[i]);
2636 if(tl>=0) {
2637 if(rs1[i]==0)
2638 {
2639 emit_zeroreg(tl);
2640 if(th>=0) emit_zeroreg(th);
2641 }
2642 else
2643 {
2644 assert(sl>=0);
2645 assert(sh>=0);
2646 if(imm[i]) {
2647 if(opcode2[i]==0x38) // DSLL
2648 {
2649 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2650 emit_shlimm(sl,imm[i],tl);
2651 }
2652 if(opcode2[i]==0x3a) // DSRL
2653 {
2654 emit_shrdimm(sl,sh,imm[i],tl);
2655 if(th>=0) emit_shrimm(sh,imm[i],th);
2656 }
2657 if(opcode2[i]==0x3b) // DSRA
2658 {
2659 emit_shrdimm(sl,sh,imm[i],tl);
2660 if(th>=0) emit_sarimm(sh,imm[i],th);
2661 }
2662 }else{
2663 // Shift by zero
2664 if(sl!=tl) emit_mov(sl,tl);
2665 if(th>=0&&sh!=th) emit_mov(sh,th);
2666 }
2667 }
2668 }
2669 }
2670 }
2671 if(opcode2[i]==0x3c) // DSLL32
2672 {
2673 if(rt1[i]) {
2674 signed char sl,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sl=get_reg(i_regs->regmap,rs1[i]);
2678 if(th>=0||tl>=0){
2679 assert(tl>=0);
2680 assert(th>=0);
2681 assert(sl>=0);
2682 emit_mov(sl,th);
2683 emit_zeroreg(tl);
2684 if(imm[i]>32)
2685 {
2686 emit_shlimm(th,imm[i]&31,th);
2687 }
2688 }
2689 }
2690 }
2691 if(opcode2[i]==0x3e) // DSRL32
2692 {
2693 if(rt1[i]) {
2694 signed char sh,tl,th;
2695 tl=get_reg(i_regs->regmap,rt1[i]);
2696 th=get_reg(i_regs->regmap,rt1[i]|64);
2697 sh=get_reg(i_regs->regmap,rs1[i]|64);
2698 if(tl>=0){
2699 assert(sh>=0);
2700 emit_mov(sh,tl);
2701 if(th>=0) emit_zeroreg(th);
2702 if(imm[i]>32)
2703 {
2704 emit_shrimm(tl,imm[i]&31,tl);
2705 }
2706 }
2707 }
2708 }
2709 if(opcode2[i]==0x3f) // DSRA32
2710 {
2711 if(rt1[i]) {
2712 signed char sh,tl;
2713 tl=get_reg(i_regs->regmap,rt1[i]);
2714 sh=get_reg(i_regs->regmap,rs1[i]|64);
2715 if(tl>=0){
2716 assert(sh>=0);
2717 emit_mov(sh,tl);
2718 if(imm[i]>32)
2719 {
2720 emit_sarimm(tl,imm[i]&31,tl);
2721 }
2722 }
2723 }
2724 }
2725}
2726
2727#ifndef shift_assemble
2728void shift_assemble(int i,struct regstat *i_regs)
2729{
2730 printf("Need shift_assemble for this architecture.\n");
2731 exit(1);
2732}
2733#endif
2734
2735void load_assemble(int i,struct regstat *i_regs)
2736{
2737 int s,th,tl,addr,map=-1;
2738 int offset;
2739 int jaddr=0;
5bf843dc 2740 int memtarget=0,c=0;
57871462 2741 u_int hr,reglist=0;
2742 th=get_reg(i_regs->regmap,rt1[i]|64);
2743 tl=get_reg(i_regs->regmap,rt1[i]);
2744 s=get_reg(i_regs->regmap,rs1[i]);
2745 offset=imm[i];
2746 for(hr=0;hr<HOST_REGS;hr++) {
2747 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2748 }
2749 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2750 if(s>=0) {
2751 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2752 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2753 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2754 }
57871462 2755 //printf("load_assemble: c=%d\n",c);
2756 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2757 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2758#ifdef PCSX
f18c0f46 2759 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2760 ||rt1[i]==0) {
5bf843dc 2761 // could be FIFO, must perform the read
f18c0f46 2762 // ||dummy read
5bf843dc 2763 assem_debug("(forced read)\n");
2764 tl=get_reg(i_regs->regmap,-1);
2765 assert(tl>=0);
5bf843dc 2766 }
f18c0f46 2767#endif
5bf843dc 2768 if(offset||s<0||c) addr=tl;
2769 else addr=s;
57871462 2770 if(tl>=0) {
2771 //assert(tl>=0);
2772 //assert(rt1[i]);
2773 reglist&=~(1<<tl);
2774 if(th>=0) reglist&=~(1<<th);
2775 if(!using_tlb) {
2776 if(!c) {
2777//#define R29_HACK 1
2778 #ifdef R29_HACK
2779 // Strmnnrmn's speed hack
4cb76aa4 2780 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 2781 #endif
2782 {
4cb76aa4 2783 emit_cmpimm(addr,RAM_SIZE);
57871462 2784 jaddr=(int)out;
2785 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2786 // Hint to branch predictor that the branch is unlikely to be taken
2787 if(rs1[i]>=28)
2788 emit_jno_unlikely(0);
2789 else
2790 #endif
2791 emit_jno(0);
2792 }
2793 }
2794 }else{ // using tlb
2795 int x=0;
2796 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2797 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2798 map=get_reg(i_regs->regmap,TLREG);
2799 assert(map>=0);
2800 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2801 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2802 }
2803 if (opcode[i]==0x20) { // LB
2804 if(!c||memtarget) {
2805 #ifdef HOST_IMM_ADDR32
2806 if(c)
2807 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2808 else
2809 #endif
2810 {
2811 //emit_xorimm(addr,3,tl);
2812 //gen_tlb_addr_r(tl,map);
2813 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2814 int x=0;
2002a1db 2815#ifdef BIG_ENDIAN_MIPS
57871462 2816 if(!c) emit_xorimm(addr,3,tl);
2817 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2818#else
2819 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2820 else if (tl!=addr) emit_mov(addr,tl);
2821#endif
57871462 2822 emit_movsbl_indexed_tlb(x,tl,map,tl);
2823 }
2824 if(jaddr)
2825 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2826 }
2827 else
2828 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2829 }
2830 if (opcode[i]==0x21) { // LH
2831 if(!c||memtarget) {
2832 #ifdef HOST_IMM_ADDR32
2833 if(c)
2834 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2835 else
2836 #endif
2837 {
2838 int x=0;
2002a1db 2839#ifdef BIG_ENDIAN_MIPS
57871462 2840 if(!c) emit_xorimm(addr,2,tl);
2841 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2842#else
2843 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2844 else if (tl!=addr) emit_mov(addr,tl);
2845#endif
57871462 2846 //#ifdef
2847 //emit_movswl_indexed_tlb(x,tl,map,tl);
2848 //else
2849 if(map>=0) {
2850 gen_tlb_addr_r(tl,map);
2851 emit_movswl_indexed(x,tl,tl);
2852 }else
2853 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2854 }
2855 if(jaddr)
2856 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2857 }
2858 else
2859 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2860 }
2861 if (opcode[i]==0x23) { // LW
2862 if(!c||memtarget) {
2863 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2864 #ifdef HOST_IMM_ADDR32
2865 if(c)
2866 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2867 else
2868 #endif
2869 emit_readword_indexed_tlb(0,addr,map,tl);
2870 if(jaddr)
2871 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2872 }
2873 else
2874 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2875 }
2876 if (opcode[i]==0x24) { // LBU
2877 if(!c||memtarget) {
2878 #ifdef HOST_IMM_ADDR32
2879 if(c)
2880 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2881 else
2882 #endif
2883 {
2884 //emit_xorimm(addr,3,tl);
2885 //gen_tlb_addr_r(tl,map);
2886 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2887 int x=0;
2002a1db 2888#ifdef BIG_ENDIAN_MIPS
57871462 2889 if(!c) emit_xorimm(addr,3,tl);
2890 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2891#else
2892 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2893 else if (tl!=addr) emit_mov(addr,tl);
2894#endif
57871462 2895 emit_movzbl_indexed_tlb(x,tl,map,tl);
2896 }
2897 if(jaddr)
2898 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899 }
2900 else
2901 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2902 }
2903 if (opcode[i]==0x25) { // LHU
2904 if(!c||memtarget) {
2905 #ifdef HOST_IMM_ADDR32
2906 if(c)
2907 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2908 else
2909 #endif
2910 {
2911 int x=0;
2002a1db 2912#ifdef BIG_ENDIAN_MIPS
57871462 2913 if(!c) emit_xorimm(addr,2,tl);
2914 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2915#else
2916 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2917 else if (tl!=addr) emit_mov(addr,tl);
2918#endif
57871462 2919 //#ifdef
2920 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2921 //#else
2922 if(map>=0) {
2923 gen_tlb_addr_r(tl,map);
2924 emit_movzwl_indexed(x,tl,tl);
2925 }else
2926 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2927 if(jaddr)
2928 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2929 }
2930 }
2931 else
2932 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2933 }
2934 if (opcode[i]==0x27) { // LWU
2935 assert(th>=0);
2936 if(!c||memtarget) {
2937 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2938 #ifdef HOST_IMM_ADDR32
2939 if(c)
2940 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2941 else
2942 #endif
2943 emit_readword_indexed_tlb(0,addr,map,tl);
2944 if(jaddr)
2945 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2946 }
2947 else {
2948 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2949 }
2950 emit_zeroreg(th);
2951 }
2952 if (opcode[i]==0x37) { // LD
2953 if(!c||memtarget) {
2954 //gen_tlb_addr_r(tl,map);
2955 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2956 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2957 #ifdef HOST_IMM_ADDR32
2958 if(c)
2959 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2960 else
2961 #endif
2962 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2963 if(jaddr)
2964 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2965 }
2966 else
2967 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2968 }
2969 //emit_storereg(rt1[i],tl); // DEBUG
2970 }
2971 //if(opcode[i]==0x23)
2972 //if(opcode[i]==0x24)
2973 //if(opcode[i]==0x23||opcode[i]==0x24)
2974 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2975 {
2976 //emit_pusha();
2977 save_regs(0x100f);
2978 emit_readword((int)&last_count,ECX);
2979 #ifdef __i386__
2980 if(get_reg(i_regs->regmap,CCREG)<0)
2981 emit_loadreg(CCREG,HOST_CCREG);
2982 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2983 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2984 emit_writeword(HOST_CCREG,(int)&Count);
2985 #endif
2986 #ifdef __arm__
2987 if(get_reg(i_regs->regmap,CCREG)<0)
2988 emit_loadreg(CCREG,0);
2989 else
2990 emit_mov(HOST_CCREG,0);
2991 emit_add(0,ECX,0);
2992 emit_addimm(0,2*ccadj[i],0);
2993 emit_writeword(0,(int)&Count);
2994 #endif
2995 emit_call((int)memdebug);
2996 //emit_popa();
2997 restore_regs(0x100f);
2998 }/**/
2999}
3000
3001#ifndef loadlr_assemble
3002void loadlr_assemble(int i,struct regstat *i_regs)
3003{
3004 printf("Need loadlr_assemble for this architecture.\n");
3005 exit(1);
3006}
3007#endif
3008
3009void store_assemble(int i,struct regstat *i_regs)
3010{
3011 int s,th,tl,map=-1;
3012 int addr,temp;
3013 int offset;
3014 int jaddr=0,jaddr2,type;
666a299d 3015 int memtarget=0,c=0;
57871462 3016 int agr=AGEN1+(i&1);
3017 u_int hr,reglist=0;
3018 th=get_reg(i_regs->regmap,rs2[i]|64);
3019 tl=get_reg(i_regs->regmap,rs2[i]);
3020 s=get_reg(i_regs->regmap,rs1[i]);
3021 temp=get_reg(i_regs->regmap,agr);
3022 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3023 offset=imm[i];
3024 if(s>=0) {
3025 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3026 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3027 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3028 }
3029 assert(tl>=0);
3030 assert(temp>=0);
3031 for(hr=0;hr<HOST_REGS;hr++) {
3032 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3033 }
3034 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3035 if(offset||s<0||c) addr=temp;
3036 else addr=s;
3037 if(!using_tlb) {
3038 if(!c) {
3039 #ifdef R29_HACK
3040 // Strmnnrmn's speed hack
3041 memtarget=1;
4cb76aa4 3042 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3043 #endif
4cb76aa4 3044 emit_cmpimm(addr,RAM_SIZE);
57871462 3045 #ifdef DESTRUCTIVE_SHIFT
3046 if(s==addr) emit_mov(s,temp);
3047 #endif
3048 #ifdef R29_HACK
4cb76aa4 3049 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3050 #endif
3051 {
3052 jaddr=(int)out;
3053 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3054 // Hint to branch predictor that the branch is unlikely to be taken
3055 if(rs1[i]>=28)
3056 emit_jno_unlikely(0);
3057 else
3058 #endif
3059 emit_jno(0);
3060 }
3061 }
3062 }else{ // using tlb
3063 int x=0;
3064 if (opcode[i]==0x28) x=3; // SB
3065 if (opcode[i]==0x29) x=2; // SH
3066 map=get_reg(i_regs->regmap,TLREG);
3067 assert(map>=0);
3068 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3069 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3070 }
3071
3072 if (opcode[i]==0x28) { // SB
3073 if(!c||memtarget) {
3074 int x=0;
2002a1db 3075#ifdef BIG_ENDIAN_MIPS
57871462 3076 if(!c) emit_xorimm(addr,3,temp);
3077 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3078#else
3079 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3080 else if (addr!=temp) emit_mov(addr,temp);
3081#endif
57871462 3082 //gen_tlb_addr_w(temp,map);
3083 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3084 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3085 }
3086 type=STOREB_STUB;
3087 }
3088 if (opcode[i]==0x29) { // SH
3089 if(!c||memtarget) {
3090 int x=0;
2002a1db 3091#ifdef BIG_ENDIAN_MIPS
57871462 3092 if(!c) emit_xorimm(addr,2,temp);
3093 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3094#else
3095 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3096 else if (addr!=temp) emit_mov(addr,temp);
3097#endif
57871462 3098 //#ifdef
3099 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3100 //#else
3101 if(map>=0) {
3102 gen_tlb_addr_w(temp,map);
3103 emit_writehword_indexed(tl,x,temp);
3104 }else
3105 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3106 }
3107 type=STOREH_STUB;
3108 }
3109 if (opcode[i]==0x2B) { // SW
3110 if(!c||memtarget)
3111 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3112 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3113 type=STOREW_STUB;
3114 }
3115 if (opcode[i]==0x3F) { // SD
3116 if(!c||memtarget) {
3117 if(rs2[i]) {
3118 assert(th>=0);
3119 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3120 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3121 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3122 }else{
3123 // Store zero
3124 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3125 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3126 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3127 }
3128 }
3129 type=STORED_STUB;
3130 }
666a299d 3131 if(!using_tlb&&(!c||memtarget))
3132 // addr could be a temp, make sure it survives STORE*_STUB
3133 reglist|=1<<addr;
57871462 3134 if(jaddr) {
3135 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3136 } else if(!memtarget) {
3137 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3138 }
3139 if(!using_tlb) {
3140 if(!c||memtarget) {
3141 #ifdef DESTRUCTIVE_SHIFT
3142 // The x86 shift operation is 'destructive'; it overwrites the
3143 // source register, so we need to make a copy first and use that.
3144 addr=temp;
3145 #endif
3146 #if defined(HOST_IMM8)
3147 int ir=get_reg(i_regs->regmap,INVCP);
3148 assert(ir>=0);
3149 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3150 #else
3151 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3152 #endif
3153 jaddr2=(int)out;
3154 emit_jne(0);
3155 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3156 }
3157 }
3158 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3159 //if(opcode[i]==0x2B || opcode[i]==0x28)
3160 //if(opcode[i]==0x2B || opcode[i]==0x29)
3161 //if(opcode[i]==0x2B)
3162 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3163 {
3164 //emit_pusha();
3165 save_regs(0x100f);
3166 emit_readword((int)&last_count,ECX);
3167 #ifdef __i386__
3168 if(get_reg(i_regs->regmap,CCREG)<0)
3169 emit_loadreg(CCREG,HOST_CCREG);
3170 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3171 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3172 emit_writeword(HOST_CCREG,(int)&Count);
3173 #endif
3174 #ifdef __arm__
3175 if(get_reg(i_regs->regmap,CCREG)<0)
3176 emit_loadreg(CCREG,0);
3177 else
3178 emit_mov(HOST_CCREG,0);
3179 emit_add(0,ECX,0);
3180 emit_addimm(0,2*ccadj[i],0);
3181 emit_writeword(0,(int)&Count);
3182 #endif
3183 emit_call((int)memdebug);
3184 //emit_popa();
3185 restore_regs(0x100f);
3186 }/**/
3187}
3188
3189void storelr_assemble(int i,struct regstat *i_regs)
3190{
3191 int s,th,tl;
3192 int temp;
3193 int temp2;
3194 int offset;
3195 int jaddr=0,jaddr2;
3196 int case1,case2,case3;
3197 int done0,done1,done2;
3198 int memtarget,c=0;
fab5d06d 3199 int agr=AGEN1+(i&1);
57871462 3200 u_int hr,reglist=0;
3201 th=get_reg(i_regs->regmap,rs2[i]|64);
3202 tl=get_reg(i_regs->regmap,rs2[i]);
3203 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3204 temp=get_reg(i_regs->regmap,agr);
3205 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3206 offset=imm[i];
3207 if(s>=0) {
3208 c=(i_regs->isconst>>s)&1;
4cb76aa4 3209 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3210 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3211 }
3212 assert(tl>=0);
3213 for(hr=0;hr<HOST_REGS;hr++) {
3214 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3215 }
3216 if(tl>=0) {
3217 assert(temp>=0);
3218 if(!using_tlb) {
3219 if(!c) {
4cb76aa4 3220 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
57871462 3221 if(!offset&&s!=temp) emit_mov(s,temp);
3222 jaddr=(int)out;
3223 emit_jno(0);
3224 }
3225 else
3226 {
3227 if(!memtarget||!rs1[i]) {
3228 jaddr=(int)out;
3229 emit_jmp(0);
3230 }
3231 }
3232 if((u_int)rdram!=0x80000000)
3233 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3234 }else{ // using tlb
3235 int map=get_reg(i_regs->regmap,TLREG);
3236 assert(map>=0);
3237 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3238 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3239 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240 if(!jaddr&&!memtarget) {
3241 jaddr=(int)out;
3242 emit_jmp(0);
3243 }
3244 gen_tlb_addr_w(temp,map);
3245 }
3246
3247 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3248 temp2=get_reg(i_regs->regmap,FTEMP);
3249 if(!rs2[i]) temp2=th=tl;
3250 }
3251
2002a1db 3252#ifndef BIG_ENDIAN_MIPS
3253 emit_xorimm(temp,3,temp);
3254#endif
57871462 3255 emit_testimm(temp,2);
3256 case2=(int)out;
3257 emit_jne(0);
3258 emit_testimm(temp,1);
3259 case1=(int)out;
3260 emit_jne(0);
3261 // 0
3262 if (opcode[i]==0x2A) { // SWL
3263 emit_writeword_indexed(tl,0,temp);
3264 }
3265 if (opcode[i]==0x2E) { // SWR
3266 emit_writebyte_indexed(tl,3,temp);
3267 }
3268 if (opcode[i]==0x2C) { // SDL
3269 emit_writeword_indexed(th,0,temp);
3270 if(rs2[i]) emit_mov(tl,temp2);
3271 }
3272 if (opcode[i]==0x2D) { // SDR
3273 emit_writebyte_indexed(tl,3,temp);
3274 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3275 }
3276 done0=(int)out;
3277 emit_jmp(0);
3278 // 1
3279 set_jump_target(case1,(int)out);
3280 if (opcode[i]==0x2A) { // SWL
3281 // Write 3 msb into three least significant bytes
3282 if(rs2[i]) emit_rorimm(tl,8,tl);
3283 emit_writehword_indexed(tl,-1,temp);
3284 if(rs2[i]) emit_rorimm(tl,16,tl);
3285 emit_writebyte_indexed(tl,1,temp);
3286 if(rs2[i]) emit_rorimm(tl,8,tl);
3287 }
3288 if (opcode[i]==0x2E) { // SWR
3289 // Write two lsb into two most significant bytes
3290 emit_writehword_indexed(tl,1,temp);
3291 }
3292 if (opcode[i]==0x2C) { // SDL
3293 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3294 // Write 3 msb into three least significant bytes
3295 if(rs2[i]) emit_rorimm(th,8,th);
3296 emit_writehword_indexed(th,-1,temp);
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writebyte_indexed(th,1,temp);
3299 if(rs2[i]) emit_rorimm(th,8,th);
3300 }
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3303 // Write two lsb into two most significant bytes
3304 emit_writehword_indexed(tl,1,temp);
3305 }
3306 done1=(int)out;
3307 emit_jmp(0);
3308 // 2
3309 set_jump_target(case2,(int)out);
3310 emit_testimm(temp,1);
3311 case3=(int)out;
3312 emit_jne(0);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write two msb into two least significant bytes
3315 if(rs2[i]) emit_rorimm(tl,16,tl);
3316 emit_writehword_indexed(tl,-2,temp);
3317 if(rs2[i]) emit_rorimm(tl,16,tl);
3318 }
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write 3 lsb into three most significant bytes
3321 emit_writebyte_indexed(tl,-1,temp);
3322 if(rs2[i]) emit_rorimm(tl,8,tl);
3323 emit_writehword_indexed(tl,0,temp);
3324 if(rs2[i]) emit_rorimm(tl,24,tl);
3325 }
3326 if (opcode[i]==0x2C) { // SDL
3327 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3328 // Write two msb into two least significant bytes
3329 if(rs2[i]) emit_rorimm(th,16,th);
3330 emit_writehword_indexed(th,-2,temp);
3331 if(rs2[i]) emit_rorimm(th,16,th);
3332 }
3333 if (opcode[i]==0x2D) { // SDR
3334 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3335 // Write 3 lsb into three most significant bytes
3336 emit_writebyte_indexed(tl,-1,temp);
3337 if(rs2[i]) emit_rorimm(tl,8,tl);
3338 emit_writehword_indexed(tl,0,temp);
3339 if(rs2[i]) emit_rorimm(tl,24,tl);
3340 }
3341 done2=(int)out;
3342 emit_jmp(0);
3343 // 3
3344 set_jump_target(case3,(int)out);
3345 if (opcode[i]==0x2A) { // SWL
3346 // Write msb into least significant byte
3347 if(rs2[i]) emit_rorimm(tl,24,tl);
3348 emit_writebyte_indexed(tl,-3,temp);
3349 if(rs2[i]) emit_rorimm(tl,8,tl);
3350 }
3351 if (opcode[i]==0x2E) { // SWR
3352 // Write entire word
3353 emit_writeword_indexed(tl,-3,temp);
3354 }
3355 if (opcode[i]==0x2C) { // SDL
3356 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3357 // Write msb into least significant byte
3358 if(rs2[i]) emit_rorimm(th,24,th);
3359 emit_writebyte_indexed(th,-3,temp);
3360 if(rs2[i]) emit_rorimm(th,8,th);
3361 }
3362 if (opcode[i]==0x2D) { // SDR
3363 if(rs2[i]) emit_mov(th,temp2);
3364 // Write entire word
3365 emit_writeword_indexed(tl,-3,temp);
3366 }
3367 set_jump_target(done0,(int)out);
3368 set_jump_target(done1,(int)out);
3369 set_jump_target(done2,(int)out);
3370 if (opcode[i]==0x2C) { // SDL
3371 emit_testimm(temp,4);
3372 done0=(int)out;
3373 emit_jne(0);
3374 emit_andimm(temp,~3,temp);
3375 emit_writeword_indexed(temp2,4,temp);
3376 set_jump_target(done0,(int)out);
3377 }
3378 if (opcode[i]==0x2D) { // SDR
3379 emit_testimm(temp,4);
3380 done0=(int)out;
3381 emit_jeq(0);
3382 emit_andimm(temp,~3,temp);
3383 emit_writeword_indexed(temp2,-4,temp);
3384 set_jump_target(done0,(int)out);
3385 }
3386 if(!c||!memtarget)
b7918751 3387 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3388 }
3389 if(!using_tlb) {
3390 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3391 #if defined(HOST_IMM8)
3392 int ir=get_reg(i_regs->regmap,INVCP);
3393 assert(ir>=0);
3394 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3395 #else
3396 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3397 #endif
3398 jaddr2=(int)out;
3399 emit_jne(0);
3400 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3401 }
3402 /*
3403 emit_pusha();
3404 //save_regs(0x100f);
3405 emit_readword((int)&last_count,ECX);
3406 if(get_reg(i_regs->regmap,CCREG)<0)
3407 emit_loadreg(CCREG,HOST_CCREG);
3408 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3409 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3410 emit_writeword(HOST_CCREG,(int)&Count);
3411 emit_call((int)memdebug);
3412 emit_popa();
3413 //restore_regs(0x100f);
3414 /**/
3415}
3416
3417void c1ls_assemble(int i,struct regstat *i_regs)
3418{
3d624f89 3419#ifndef DISABLE_COP1
57871462 3420 int s,th,tl;
3421 int temp,ar;
3422 int map=-1;
3423 int offset;
3424 int c=0;
3425 int jaddr,jaddr2=0,jaddr3,type;
3426 int agr=AGEN1+(i&1);
3427 u_int hr,reglist=0;
3428 th=get_reg(i_regs->regmap,FTEMP|64);
3429 tl=get_reg(i_regs->regmap,FTEMP);
3430 s=get_reg(i_regs->regmap,rs1[i]);
3431 temp=get_reg(i_regs->regmap,agr);
3432 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3433 offset=imm[i];
3434 assert(tl>=0);
3435 assert(rs1[i]>0);
3436 assert(temp>=0);
3437 for(hr=0;hr<HOST_REGS;hr++) {
3438 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3439 }
3440 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3441 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3442 {
3443 // Loads use a temporary register which we need to save
3444 reglist|=1<<temp;
3445 }
3446 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3447 ar=temp;
3448 else // LWC1/LDC1
3449 ar=tl;
3450 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3451 //else c=(i_regs->wasconst>>s)&1;
3452 if(s>=0) c=(i_regs->wasconst>>s)&1;
3453 // Check cop1 unusable
3454 if(!cop1_usable) {
3455 signed char rs=get_reg(i_regs->regmap,CSREG);
3456 assert(rs>=0);
3457 emit_testimm(rs,0x20000000);
3458 jaddr=(int)out;
3459 emit_jeq(0);
3460 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3461 cop1_usable=1;
3462 }
3463 if (opcode[i]==0x39) { // SWC1 (get float address)
3464 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3465 }
3466 if (opcode[i]==0x3D) { // SDC1 (get double address)
3467 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3468 }
3469 // Generate address + offset
3470 if(!using_tlb) {
3471 if(!c)
4cb76aa4 3472 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3473 }
3474 else
3475 {
3476 map=get_reg(i_regs->regmap,TLREG);
3477 assert(map>=0);
3478 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3479 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3480 }
3481 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3482 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3483 }
3484 }
3485 if (opcode[i]==0x39) { // SWC1 (read float)
3486 emit_readword_indexed(0,tl,tl);
3487 }
3488 if (opcode[i]==0x3D) { // SDC1 (read double)
3489 emit_readword_indexed(4,tl,th);
3490 emit_readword_indexed(0,tl,tl);
3491 }
3492 if (opcode[i]==0x31) { // LWC1 (get target address)
3493 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3494 }
3495 if (opcode[i]==0x35) { // LDC1 (get target address)
3496 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3497 }
3498 if(!using_tlb) {
3499 if(!c) {
3500 jaddr2=(int)out;
3501 emit_jno(0);
3502 }
4cb76aa4 3503 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3504 jaddr2=(int)out;
3505 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3506 }
3507 #ifdef DESTRUCTIVE_SHIFT
3508 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3509 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3510 }
3511 #endif
3512 }else{
3513 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3514 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3515 }
3516 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3517 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3518 }
3519 }
3520 if (opcode[i]==0x31) { // LWC1
3521 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3522 //gen_tlb_addr_r(ar,map);
3523 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3524 #ifdef HOST_IMM_ADDR32
3525 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3526 else
3527 #endif
3528 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3529 type=LOADW_STUB;
3530 }
3531 if (opcode[i]==0x35) { // LDC1
3532 assert(th>=0);
3533 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3534 //gen_tlb_addr_r(ar,map);
3535 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3536 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3537 #ifdef HOST_IMM_ADDR32
3538 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3539 else
3540 #endif
3541 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3542 type=LOADD_STUB;
3543 }
3544 if (opcode[i]==0x39) { // SWC1
3545 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3546 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3547 type=STOREW_STUB;
3548 }
3549 if (opcode[i]==0x3D) { // SDC1
3550 assert(th>=0);
3551 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3552 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3553 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3554 type=STORED_STUB;
3555 }
3556 if(!using_tlb) {
3557 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3558 #ifndef DESTRUCTIVE_SHIFT
3559 temp=offset||c||s<0?ar:s;
3560 #endif
3561 #if defined(HOST_IMM8)
3562 int ir=get_reg(i_regs->regmap,INVCP);
3563 assert(ir>=0);
3564 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3565 #else
3566 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3567 #endif
3568 jaddr3=(int)out;
3569 emit_jne(0);
3570 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3571 }
3572 }
3573 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3574 if (opcode[i]==0x31) { // LWC1 (write float)
3575 emit_writeword_indexed(tl,0,temp);
3576 }
3577 if (opcode[i]==0x35) { // LDC1 (write double)
3578 emit_writeword_indexed(th,4,temp);
3579 emit_writeword_indexed(tl,0,temp);
3580 }
3581 //if(opcode[i]==0x39)
3582 /*if(opcode[i]==0x39||opcode[i]==0x31)
3583 {
3584 emit_pusha();
3585 emit_readword((int)&last_count,ECX);
3586 if(get_reg(i_regs->regmap,CCREG)<0)
3587 emit_loadreg(CCREG,HOST_CCREG);
3588 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3589 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3590 emit_writeword(HOST_CCREG,(int)&Count);
3591 emit_call((int)memdebug);
3592 emit_popa();
3593 }/**/
3d624f89 3594#else
3595 cop1_unusable(i, i_regs);
3596#endif
57871462 3597}
3598
b9b61529 3599void c2ls_assemble(int i,struct regstat *i_regs)
3600{
3601 int s,tl;
3602 int ar;
3603 int offset;
1fd1aceb 3604 int memtarget=0,c=0;
b9b61529 3605 int jaddr,jaddr2=0,jaddr3,type;
3606 int agr=AGEN1+(i&1);
3607 u_int hr,reglist=0;
3608 u_int copr=(source[i]>>16)&0x1f;
3609 s=get_reg(i_regs->regmap,rs1[i]);
3610 tl=get_reg(i_regs->regmap,FTEMP);
3611 offset=imm[i];
3612 assert(rs1[i]>0);
3613 assert(tl>=0);
3614 assert(!using_tlb);
3615
3616 for(hr=0;hr<HOST_REGS;hr++) {
3617 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3618 }
3619 if(i_regs->regmap[HOST_CCREG]==CCREG)
3620 reglist&=~(1<<HOST_CCREG);
3621
3622 // get the address
3623 if (opcode[i]==0x3a) { // SWC2
3624 ar=get_reg(i_regs->regmap,agr);
3625 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3626 reglist|=1<<ar;
3627 } else { // LWC2
3628 ar=tl;
3629 }
1fd1aceb 3630 if(s>=0) c=(i_regs->wasconst>>s)&1;
3631 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3632 if (!offset&&!c&&s>=0) ar=s;
3633 assert(ar>=0);
3634
3635 if (opcode[i]==0x3a) { // SWC2
3636 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3637 type=STOREW_STUB;
b9b61529 3638 }
1fd1aceb 3639 else
b9b61529 3640 type=LOADW_STUB;
1fd1aceb 3641
3642 if(c&&!memtarget) {
3643 jaddr2=(int)out;
3644 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3645 }
1fd1aceb 3646 else {
3647 if(!c) {
3648 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3649 jaddr2=(int)out;
3650 emit_jno(0);
3651 }
3652 if (opcode[i]==0x32) { // LWC2
3653 #ifdef HOST_IMM_ADDR32
3654 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3655 else
3656 #endif
3657 emit_readword_indexed(0,ar,tl);
3658 }
3659 if (opcode[i]==0x3a) { // SWC2
3660 #ifdef DESTRUCTIVE_SHIFT
3661 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3662 #endif
3663 emit_writeword_indexed(tl,0,ar);
3664 }
b9b61529 3665 }
3666 if(jaddr2)
3667 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3668 if (opcode[i]==0x3a) { // SWC2
3669#if defined(HOST_IMM8)
3670 int ir=get_reg(i_regs->regmap,INVCP);
3671 assert(ir>=0);
3672 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3673#else
3674 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3675#endif
3676 jaddr3=(int)out;
3677 emit_jne(0);
3678 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3679 }
3680 if (opcode[i]==0x32) { // LWC2
3681 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3682 }
3683}
3684
57871462 3685#ifndef multdiv_assemble
3686void multdiv_assemble(int i,struct regstat *i_regs)
3687{
3688 printf("Need multdiv_assemble for this architecture.\n");
3689 exit(1);
3690}
3691#endif
3692
3693void mov_assemble(int i,struct regstat *i_regs)
3694{
3695 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3696 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
f5b13bdc 3697 //assert(rt1[i]>0);
57871462 3698 if(rt1[i]) {
3699 signed char sh,sl,th,tl;
3700 th=get_reg(i_regs->regmap,rt1[i]|64);
3701 tl=get_reg(i_regs->regmap,rt1[i]);
3702 //assert(tl>=0);
3703 if(tl>=0) {
3704 sh=get_reg(i_regs->regmap,rs1[i]|64);
3705 sl=get_reg(i_regs->regmap,rs1[i]);
3706 if(sl>=0) emit_mov(sl,tl);
3707 else emit_loadreg(rs1[i],tl);
3708 if(th>=0) {
3709 if(sh>=0) emit_mov(sh,th);
3710 else emit_loadreg(rs1[i]|64,th);
3711 }
3712 }
3713 }
3714}
3715
3716#ifndef fconv_assemble
3717void fconv_assemble(int i,struct regstat *i_regs)
3718{
3719 printf("Need fconv_assemble for this architecture.\n");
3720 exit(1);
3721}
3722#endif
3723
3724#if 0
3725void float_assemble(int i,struct regstat *i_regs)
3726{
3727 printf("Need float_assemble for this architecture.\n");
3728 exit(1);
3729}
3730#endif
3731
3732void syscall_assemble(int i,struct regstat *i_regs)
3733{
3734 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3735 assert(ccreg==HOST_CCREG);
3736 assert(!is_delayslot);
3737 emit_movimm(start+i*4,EAX); // Get PC
3738 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3739 emit_jmp((int)jump_syscall_hle); // XXX
3740}
3741
3742void hlecall_assemble(int i,struct regstat *i_regs)
3743{
3744 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3745 assert(ccreg==HOST_CCREG);
3746 assert(!is_delayslot);
3747 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3748 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3749 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3750 emit_jmp((int)jump_hlecall);
57871462 3751}
3752
1e973cb0 3753void intcall_assemble(int i,struct regstat *i_regs)
3754{
3755 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3756 assert(ccreg==HOST_CCREG);
3757 assert(!is_delayslot);
3758 emit_movimm(start+i*4,0); // Get PC
3759 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3760 emit_jmp((int)jump_intcall);
3761}
3762
57871462 3763void ds_assemble(int i,struct regstat *i_regs)
3764{
3765 is_delayslot=1;
3766 switch(itype[i]) {
3767 case ALU:
3768 alu_assemble(i,i_regs);break;
3769 case IMM16:
3770 imm16_assemble(i,i_regs);break;
3771 case SHIFT:
3772 shift_assemble(i,i_regs);break;
3773 case SHIFTIMM:
3774 shiftimm_assemble(i,i_regs);break;
3775 case LOAD:
3776 load_assemble(i,i_regs);break;
3777 case LOADLR:
3778 loadlr_assemble(i,i_regs);break;
3779 case STORE:
3780 store_assemble(i,i_regs);break;
3781 case STORELR:
3782 storelr_assemble(i,i_regs);break;
3783 case COP0:
3784 cop0_assemble(i,i_regs);break;
3785 case COP1:
3786 cop1_assemble(i,i_regs);break;
3787 case C1LS:
3788 c1ls_assemble(i,i_regs);break;
b9b61529 3789 case COP2:
3790 cop2_assemble(i,i_regs);break;
3791 case C2LS:
3792 c2ls_assemble(i,i_regs);break;
3793 case C2OP:
3794 c2op_assemble(i,i_regs);break;
57871462 3795 case FCONV:
3796 fconv_assemble(i,i_regs);break;
3797 case FLOAT:
3798 float_assemble(i,i_regs);break;
3799 case FCOMP:
3800 fcomp_assemble(i,i_regs);break;
3801 case MULTDIV:
3802 multdiv_assemble(i,i_regs);break;
3803 case MOV:
3804 mov_assemble(i,i_regs);break;
3805 case SYSCALL:
7139f3c8 3806 case HLECALL:
1e973cb0 3807 case INTCALL:
57871462 3808 case SPAN:
3809 case UJUMP:
3810 case RJUMP:
3811 case CJUMP:
3812 case SJUMP:
3813 case FJUMP:
3814 printf("Jump in the delay slot. This is probably a bug.\n");
3815 }
3816 is_delayslot=0;
3817}
3818
3819// Is the branch target a valid internal jump?
3820int internal_branch(uint64_t i_is32,int addr)
3821{
3822 if(addr&1) return 0; // Indirect (register) jump
3823 if(addr>=start && addr<start+slen*4-4)
3824 {
3825 int t=(addr-start)>>2;
3826 // Delay slots are not valid branch targets
3827 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3828 // 64 -> 32 bit transition requires a recompile
3829 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3830 {
3831 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3832 else printf("optimizable: yes\n");
3833 }*/
3834 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3835 if(requires_32bit[t]&~i_is32) return 0;
3836 else return 1;
3837 }
3838 return 0;
3839}
3840
3841#ifndef wb_invalidate
3842void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3843 uint64_t u,uint64_t uu)
3844{
3845 int hr;
3846 for(hr=0;hr<HOST_REGS;hr++) {
3847 if(hr!=EXCLUDE_REG) {
3848 if(pre[hr]!=entry[hr]) {
3849 if(pre[hr]>=0) {
3850 if((dirty>>hr)&1) {
3851 if(get_reg(entry,pre[hr])<0) {
3852 if(pre[hr]<64) {
3853 if(!((u>>pre[hr])&1)) {
3854 emit_storereg(pre[hr],hr);
3855 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3856 emit_sarimm(hr,31,hr);
3857 emit_storereg(pre[hr]|64,hr);
3858 }
3859 }
3860 }else{
3861 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3862 emit_storereg(pre[hr],hr);
3863 }
3864 }
3865 }
3866 }
3867 }
3868 }
3869 }
3870 }
3871 // Move from one register to another (no writeback)
3872 for(hr=0;hr<HOST_REGS;hr++) {
3873 if(hr!=EXCLUDE_REG) {
3874 if(pre[hr]!=entry[hr]) {
3875 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3876 int nr;
3877 if((nr=get_reg(entry,pre[hr]))>=0) {
3878 emit_mov(hr,nr);
3879 }
3880 }
3881 }
3882 }
3883 }
3884}
3885#endif
3886
3887// Load the specified registers
3888// This only loads the registers given as arguments because
3889// we don't want to load things that will be overwritten
3890void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3891{
3892 int hr;
3893 // Load 32-bit regs
3894 for(hr=0;hr<HOST_REGS;hr++) {
3895 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3896 if(entry[hr]!=regmap[hr]) {
3897 if(regmap[hr]==rs1||regmap[hr]==rs2)
3898 {
3899 if(regmap[hr]==0) {
3900 emit_zeroreg(hr);
3901 }
3902 else
3903 {
3904 emit_loadreg(regmap[hr],hr);
3905 }
3906 }
3907 }
3908 }
3909 }
3910 //Load 64-bit regs
3911 for(hr=0;hr<HOST_REGS;hr++) {
3912 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3913 if(entry[hr]!=regmap[hr]) {
3914 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3915 {
3916 assert(regmap[hr]!=64);
3917 if((is32>>(regmap[hr]&63))&1) {
3918 int lr=get_reg(regmap,regmap[hr]-64);
3919 if(lr>=0)
3920 emit_sarimm(lr,31,hr);
3921 else
3922 emit_loadreg(regmap[hr],hr);
3923 }
3924 else
3925 {
3926 emit_loadreg(regmap[hr],hr);
3927 }
3928 }
3929 }
3930 }
3931 }
3932}
3933
3934// Load registers prior to the start of a loop
3935// so that they are not loaded within the loop
3936static void loop_preload(signed char pre[],signed char entry[])
3937{
3938 int hr;
3939 for(hr=0;hr<HOST_REGS;hr++) {
3940 if(hr!=EXCLUDE_REG) {
3941 if(pre[hr]!=entry[hr]) {
3942 if(entry[hr]>=0) {
3943 if(get_reg(pre,entry[hr])<0) {
3944 assem_debug("loop preload:\n");
3945 //printf("loop preload: %d\n",hr);
3946 if(entry[hr]==0) {
3947 emit_zeroreg(hr);
3948 }
3949 else if(entry[hr]<TEMPREG)
3950 {
3951 emit_loadreg(entry[hr],hr);
3952 }
3953 else if(entry[hr]-64<TEMPREG)
3954 {
3955 emit_loadreg(entry[hr],hr);
3956 }
3957 }
3958 }
3959 }
3960 }
3961 }
3962}
3963
3964// Generate address for load/store instruction
b9b61529 3965// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 3966void address_generation(int i,struct regstat *i_regs,signed char entry[])
3967{
b9b61529 3968 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
57871462 3969 int ra;
3970 int agr=AGEN1+(i&1);
3971 int mgr=MGEN1+(i&1);
3972 if(itype[i]==LOAD) {
3973 ra=get_reg(i_regs->regmap,rt1[i]);
3974 //if(rt1[i]) assert(ra>=0);
3975 }
3976 if(itype[i]==LOADLR) {
3977 ra=get_reg(i_regs->regmap,FTEMP);
3978 }
3979 if(itype[i]==STORE||itype[i]==STORELR) {
3980 ra=get_reg(i_regs->regmap,agr);
3981 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3982 }
b9b61529 3983 if(itype[i]==C1LS||itype[i]==C2LS) {
3984 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 3985 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 3986 else { // SWC1/SDC1/SWC2/SDC2
57871462 3987 ra=get_reg(i_regs->regmap,agr);
3988 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3989 }
3990 }
3991 int rs=get_reg(i_regs->regmap,rs1[i]);
3992 int rm=get_reg(i_regs->regmap,TLREG);
3993 if(ra>=0) {
3994 int offset=imm[i];
3995 int c=(i_regs->wasconst>>rs)&1;
3996 if(rs1[i]==0) {
3997 // Using r0 as a base address
3998 /*if(rm>=0) {
3999 if(!entry||entry[rm]!=mgr) {
4000 generate_map_const(offset,rm);
4001 } // else did it in the previous cycle
4002 }*/
4003 if(!entry||entry[ra]!=agr) {
4004 if (opcode[i]==0x22||opcode[i]==0x26) {
4005 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4006 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4007 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4008 }else{
4009 emit_movimm(offset,ra);
4010 }
4011 } // else did it in the previous cycle
4012 }
4013 else if(rs<0) {
4014 if(!entry||entry[ra]!=rs1[i])
4015 emit_loadreg(rs1[i],ra);
4016 //if(!entry||entry[ra]!=rs1[i])
4017 // printf("poor load scheduling!\n");
4018 }
4019 else if(c) {
4020 if(rm>=0) {
4021 if(!entry||entry[rm]!=mgr) {
b9b61529 4022 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4023 // Stores to memory go thru the mapper to detect self-modifying
4024 // code, loads don't.
4025 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4026 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4027 generate_map_const(constmap[i][rs]+offset,rm);
4028 }else{
4029 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4030 generate_map_const(constmap[i][rs]+offset,rm);
4031 }
4032 }
4033 }
4034 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4035 if(!entry||entry[ra]!=agr) {
4036 if (opcode[i]==0x22||opcode[i]==0x26) {
4037 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4038 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4039 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4040 }else{
4041 #ifdef HOST_IMM_ADDR32
b9b61529 4042 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4043 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4044 #endif
4045 emit_movimm(constmap[i][rs]+offset,ra);
4046 }
4047 } // else did it in the previous cycle
4048 } // else load_consts already did it
4049 }
4050 if(offset&&!c&&rs1[i]) {
4051 if(rs>=0) {
4052 emit_addimm(rs,offset,ra);
4053 }else{
4054 emit_addimm(ra,offset,ra);
4055 }
4056 }
4057 }
4058 }
4059 // Preload constants for next instruction
b9b61529 4060 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4061 int agr,ra;
4062 #ifndef HOST_IMM_ADDR32
4063 // Mapper entry
4064 agr=MGEN1+((i+1)&1);
4065 ra=get_reg(i_regs->regmap,agr);
4066 if(ra>=0) {
4067 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4068 int offset=imm[i+1];
4069 int c=(regs[i+1].wasconst>>rs)&1;
4070 if(c) {
b9b61529 4071 if(itype[i+1]==STORE||itype[i+1]==STORELR
4072 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4073 // Stores to memory go thru the mapper to detect self-modifying
4074 // code, loads don't.
4075 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4076 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4077 generate_map_const(constmap[i+1][rs]+offset,ra);
4078 }else{
4079 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4080 generate_map_const(constmap[i+1][rs]+offset,ra);
4081 }
4082 }
4083 /*else if(rs1[i]==0) {
4084 generate_map_const(offset,ra);
4085 }*/
4086 }
4087 #endif
4088 // Actual address
4089 agr=AGEN1+((i+1)&1);
4090 ra=get_reg(i_regs->regmap,agr);
4091 if(ra>=0) {
4092 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4093 int offset=imm[i+1];
4094 int c=(regs[i+1].wasconst>>rs)&1;
4095 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4096 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4097 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4098 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4099 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4100 }else{
4101 #ifdef HOST_IMM_ADDR32
b9b61529 4102 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4103 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4104 #endif
4105 emit_movimm(constmap[i+1][rs]+offset,ra);
4106 }
4107 }
4108 else if(rs1[i+1]==0) {
4109 // Using r0 as a base address
4110 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4111 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4112 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4113 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4114 }else{
4115 emit_movimm(offset,ra);
4116 }
4117 }
4118 }
4119 }
4120}
4121
4122int get_final_value(int hr, int i, int *value)
4123{
4124 int reg=regs[i].regmap[hr];
4125 while(i<slen-1) {
4126 if(regs[i+1].regmap[hr]!=reg) break;
4127 if(!((regs[i+1].isconst>>hr)&1)) break;
4128 if(bt[i+1]) break;
4129 i++;
4130 }
4131 if(i<slen-1) {
4132 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4133 *value=constmap[i][hr];
4134 return 1;
4135 }
4136 if(!bt[i+1]) {
4137 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4138 // Load in delay slot, out-of-order execution
4139 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4140 {
4141 #ifdef HOST_IMM_ADDR32
4142 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4143 #endif
4144 // Precompute load address
4145 *value=constmap[i][hr]+imm[i+2];
4146 return 1;
4147 }
4148 }
4149 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4150 {
4151 #ifdef HOST_IMM_ADDR32
4152 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4153 #endif
4154 // Precompute load address
4155 *value=constmap[i][hr]+imm[i+1];
4156 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4157 return 1;
4158 }
4159 }
4160 }
4161 *value=constmap[i][hr];
4162 //printf("c=%x\n",(int)constmap[i][hr]);
4163 if(i==slen-1) return 1;
4164 if(reg<64) {
4165 return !((unneeded_reg[i+1]>>reg)&1);
4166 }else{
4167 return !((unneeded_reg_upper[i+1]>>reg)&1);
4168 }
4169}
4170
4171// Load registers with known constants
4172void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4173{
4174 int hr;
4175 // Load 32-bit regs
4176 for(hr=0;hr<HOST_REGS;hr++) {
4177 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4178 //if(entry[hr]!=regmap[hr]) {
4179 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4180 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4181 int value;
4182 if(get_final_value(hr,i,&value)) {
4183 if(value==0) {
4184 emit_zeroreg(hr);
4185 }
4186 else {
4187 emit_movimm(value,hr);
4188 }
4189 }
4190 }
4191 }
4192 }
4193 }
4194 // Load 64-bit regs
4195 for(hr=0;hr<HOST_REGS;hr++) {
4196 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4197 //if(entry[hr]!=regmap[hr]) {
4198 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4199 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4200 if((is32>>(regmap[hr]&63))&1) {
4201 int lr=get_reg(regmap,regmap[hr]-64);
4202 assert(lr>=0);
4203 emit_sarimm(lr,31,hr);
4204 }
4205 else
4206 {
4207 int value;
4208 if(get_final_value(hr,i,&value)) {
4209 if(value==0) {
4210 emit_zeroreg(hr);
4211 }
4212 else {
4213 emit_movimm(value,hr);
4214 }
4215 }
4216 }
4217 }
4218 }
4219 }
4220 }
4221}
4222void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4223{
4224 int hr;
4225 // Load 32-bit regs
4226 for(hr=0;hr<HOST_REGS;hr++) {
4227 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4228 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4229 int value=constmap[i][hr];
4230 if(value==0) {
4231 emit_zeroreg(hr);
4232 }
4233 else {
4234 emit_movimm(value,hr);
4235 }
4236 }
4237 }
4238 }
4239 // Load 64-bit regs
4240 for(hr=0;hr<HOST_REGS;hr++) {
4241 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4242 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4243 if((is32>>(regmap[hr]&63))&1) {
4244 int lr=get_reg(regmap,regmap[hr]-64);
4245 assert(lr>=0);
4246 emit_sarimm(lr,31,hr);
4247 }
4248 else
4249 {
4250 int value=constmap[i][hr];
4251 if(value==0) {
4252 emit_zeroreg(hr);
4253 }
4254 else {
4255 emit_movimm(value,hr);
4256 }
4257 }
4258 }
4259 }
4260 }
4261}
4262
4263// Write out all dirty registers (except cycle count)
4264void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4265{
4266 int hr;
4267 for(hr=0;hr<HOST_REGS;hr++) {
4268 if(hr!=EXCLUDE_REG) {
4269 if(i_regmap[hr]>0) {
4270 if(i_regmap[hr]!=CCREG) {
4271 if((i_dirty>>hr)&1) {
4272 if(i_regmap[hr]<64) {
4273 emit_storereg(i_regmap[hr],hr);
24385cae 4274#ifndef FORCE32
57871462 4275 if( ((i_is32>>i_regmap[hr])&1) ) {
4276 #ifdef DESTRUCTIVE_WRITEBACK
4277 emit_sarimm(hr,31,hr);
4278 emit_storereg(i_regmap[hr]|64,hr);
4279 #else
4280 emit_sarimm(hr,31,HOST_TEMPREG);
4281 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4282 #endif
4283 }
24385cae 4284#endif
57871462 4285 }else{
4286 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4287 emit_storereg(i_regmap[hr],hr);
4288 }
4289 }
4290 }
4291 }
4292 }
4293 }
4294 }
4295}
4296// Write out dirty registers that we need to reload (pair with load_needed_regs)
4297// This writes the registers not written by store_regs_bt
4298void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4299{
4300 int hr;
4301 int t=(addr-start)>>2;
4302 for(hr=0;hr<HOST_REGS;hr++) {
4303 if(hr!=EXCLUDE_REG) {
4304 if(i_regmap[hr]>0) {
4305 if(i_regmap[hr]!=CCREG) {
4306 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4307 if((i_dirty>>hr)&1) {
4308 if(i_regmap[hr]<64) {
4309 emit_storereg(i_regmap[hr],hr);
24385cae 4310#ifndef FORCE32
57871462 4311 if( ((i_is32>>i_regmap[hr])&1) ) {
4312 #ifdef DESTRUCTIVE_WRITEBACK
4313 emit_sarimm(hr,31,hr);
4314 emit_storereg(i_regmap[hr]|64,hr);
4315 #else
4316 emit_sarimm(hr,31,HOST_TEMPREG);
4317 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4318 #endif
4319 }
24385cae 4320#endif
57871462 4321 }else{
4322 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4323 emit_storereg(i_regmap[hr],hr);
4324 }
4325 }
4326 }
4327 }
4328 }
4329 }
4330 }
4331 }
4332}
4333
4334// Load all registers (except cycle count)
4335void load_all_regs(signed char i_regmap[])
4336{
4337 int hr;
4338 for(hr=0;hr<HOST_REGS;hr++) {
4339 if(hr!=EXCLUDE_REG) {
4340 if(i_regmap[hr]==0) {
4341 emit_zeroreg(hr);
4342 }
4343 else
4344 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4345 {
4346 emit_loadreg(i_regmap[hr],hr);
4347 }
4348 }
4349 }
4350}
4351
4352// Load all current registers also needed by next instruction
4353void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4354{
4355 int hr;
4356 for(hr=0;hr<HOST_REGS;hr++) {
4357 if(hr!=EXCLUDE_REG) {
4358 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4359 if(i_regmap[hr]==0) {
4360 emit_zeroreg(hr);
4361 }
4362 else
4363 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4364 {
4365 emit_loadreg(i_regmap[hr],hr);
4366 }
4367 }
4368 }
4369 }
4370}
4371
4372// Load all regs, storing cycle count if necessary
4373void load_regs_entry(int t)
4374{
4375 int hr;
4376 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4377 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4378 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4379 emit_storereg(CCREG,HOST_CCREG);
4380 }
4381 // Load 32-bit regs
4382 for(hr=0;hr<HOST_REGS;hr++) {
4383 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4384 if(regs[t].regmap_entry[hr]==0) {
4385 emit_zeroreg(hr);
4386 }
4387 else if(regs[t].regmap_entry[hr]!=CCREG)
4388 {
4389 emit_loadreg(regs[t].regmap_entry[hr],hr);
4390 }
4391 }
4392 }
4393 // Load 64-bit regs
4394 for(hr=0;hr<HOST_REGS;hr++) {
4395 if(regs[t].regmap_entry[hr]>=64) {
4396 assert(regs[t].regmap_entry[hr]!=64);
4397 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4398 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4399 if(lr<0) {
4400 emit_loadreg(regs[t].regmap_entry[hr],hr);
4401 }
4402 else
4403 {
4404 emit_sarimm(lr,31,hr);
4405 }
4406 }
4407 else
4408 {
4409 emit_loadreg(regs[t].regmap_entry[hr],hr);
4410 }
4411 }
4412 }
4413}
4414
4415// Store dirty registers prior to branch
4416void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4417{
4418 if(internal_branch(i_is32,addr))
4419 {
4420 int t=(addr-start)>>2;
4421 int hr;
4422 for(hr=0;hr<HOST_REGS;hr++) {
4423 if(hr!=EXCLUDE_REG) {
4424 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4425 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4426 if((i_dirty>>hr)&1) {
4427 if(i_regmap[hr]<64) {
4428 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4429 emit_storereg(i_regmap[hr],hr);
4430 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4431 #ifdef DESTRUCTIVE_WRITEBACK
4432 emit_sarimm(hr,31,hr);
4433 emit_storereg(i_regmap[hr]|64,hr);
4434 #else
4435 emit_sarimm(hr,31,HOST_TEMPREG);
4436 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4437 #endif
4438 }
4439 }
4440 }else{
4441 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4442 emit_storereg(i_regmap[hr],hr);
4443 }
4444 }
4445 }
4446 }
4447 }
4448 }
4449 }
4450 }
4451 else
4452 {
4453 // Branch out of this block, write out all dirty regs
4454 wb_dirtys(i_regmap,i_is32,i_dirty);
4455 }
4456}
4457
4458// Load all needed registers for branch target
4459void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4460{
4461 //if(addr>=start && addr<(start+slen*4))
4462 if(internal_branch(i_is32,addr))
4463 {
4464 int t=(addr-start)>>2;
4465 int hr;
4466 // Store the cycle count before loading something else
4467 if(i_regmap[HOST_CCREG]!=CCREG) {
4468 assert(i_regmap[HOST_CCREG]==-1);
4469 }
4470 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4471 emit_storereg(CCREG,HOST_CCREG);
4472 }
4473 // Load 32-bit regs
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4476 #ifdef DESTRUCTIVE_WRITEBACK
4477 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4478 #else
4479 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4480 #endif
4481 if(regs[t].regmap_entry[hr]==0) {
4482 emit_zeroreg(hr);
4483 }
4484 else if(regs[t].regmap_entry[hr]!=CCREG)
4485 {
4486 emit_loadreg(regs[t].regmap_entry[hr],hr);
4487 }
4488 }
4489 }
4490 }
4491 //Load 64-bit regs
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4494 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4495 assert(regs[t].regmap_entry[hr]!=64);
4496 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4497 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4498 if(lr<0) {
4499 emit_loadreg(regs[t].regmap_entry[hr],hr);
4500 }
4501 else
4502 {
4503 emit_sarimm(lr,31,hr);
4504 }
4505 }
4506 else
4507 {
4508 emit_loadreg(regs[t].regmap_entry[hr],hr);
4509 }
4510 }
4511 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4512 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4513 assert(lr>=0);
4514 emit_sarimm(lr,31,hr);
4515 }
4516 }
4517 }
4518 }
4519}
4520
4521int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4522{
4523 if(addr>=start && addr<start+slen*4-4)
4524 {
4525 int t=(addr-start)>>2;
4526 int hr;
4527 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4528 for(hr=0;hr<HOST_REGS;hr++)
4529 {
4530 if(hr!=EXCLUDE_REG)
4531 {
4532 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4533 {
4534 if(regs[t].regmap_entry[hr]!=-1)
4535 {
4536 return 0;
4537 }
4538 else
4539 if((i_dirty>>hr)&1)
4540 {
4541 if(i_regmap[hr]<64)
4542 {
4543 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4544 return 0;
4545 }
4546 else
4547 {
4548 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4549 return 0;
4550 }
4551 }
4552 }
4553 else // Same register but is it 32-bit or dirty?
4554 if(i_regmap[hr]>=0)
4555 {
4556 if(!((regs[t].dirty>>hr)&1))
4557 {
4558 if((i_dirty>>hr)&1)
4559 {
4560 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4561 {
4562 //printf("%x: dirty no match\n",addr);
4563 return 0;
4564 }
4565 }
4566 }
4567 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4568 {
4569 //printf("%x: is32 no match\n",addr);
4570 return 0;
4571 }
4572 }
4573 }
4574 }
4575 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4576 if(requires_32bit[t]&~i_is32) return 0;
4577 // Delay slots are not valid branch targets
4578 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4579 // Delay slots require additional processing, so do not match
4580 if(is_ds[t]) return 0;
4581 }
4582 else
4583 {
4584 int hr;
4585 for(hr=0;hr<HOST_REGS;hr++)
4586 {
4587 if(hr!=EXCLUDE_REG)
4588 {
4589 if(i_regmap[hr]>=0)
4590 {
4591 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4592 {
4593 if((i_dirty>>hr)&1)
4594 {
4595 return 0;
4596 }
4597 }
4598 }
4599 }
4600 }
4601 }
4602 return 1;
4603}
4604
4605// Used when a branch jumps into the delay slot of another branch
4606void ds_assemble_entry(int i)
4607{
4608 int t=(ba[i]-start)>>2;
4609 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4610 assem_debug("Assemble delay slot at %x\n",ba[i]);
4611 assem_debug("<->\n");
4612 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4613 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4614 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4615 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4616 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4617 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4618 cop1_usable=0;
4619 is_delayslot=0;
4620 switch(itype[t]) {
4621 case ALU:
4622 alu_assemble(t,&regs[t]);break;
4623 case IMM16:
4624 imm16_assemble(t,&regs[t]);break;
4625 case SHIFT:
4626 shift_assemble(t,&regs[t]);break;
4627 case SHIFTIMM:
4628 shiftimm_assemble(t,&regs[t]);break;
4629 case LOAD:
4630 load_assemble(t,&regs[t]);break;
4631 case LOADLR:
4632 loadlr_assemble(t,&regs[t]);break;
4633 case STORE:
4634 store_assemble(t,&regs[t]);break;
4635 case STORELR:
4636 storelr_assemble(t,&regs[t]);break;
4637 case COP0:
4638 cop0_assemble(t,&regs[t]);break;
4639 case COP1:
4640 cop1_assemble(t,&regs[t]);break;
4641 case C1LS:
4642 c1ls_assemble(t,&regs[t]);break;
b9b61529 4643 case COP2:
4644 cop2_assemble(t,&regs[t]);break;
4645 case C2LS:
4646 c2ls_assemble(t,&regs[t]);break;
4647 case C2OP:
4648 c2op_assemble(t,&regs[t]);break;
57871462 4649 case FCONV:
4650 fconv_assemble(t,&regs[t]);break;
4651 case FLOAT:
4652 float_assemble(t,&regs[t]);break;
4653 case FCOMP:
4654 fcomp_assemble(t,&regs[t]);break;
4655 case MULTDIV:
4656 multdiv_assemble(t,&regs[t]);break;
4657 case MOV:
4658 mov_assemble(t,&regs[t]);break;
4659 case SYSCALL:
7139f3c8 4660 case HLECALL:
1e973cb0 4661 case INTCALL:
57871462 4662 case SPAN:
4663 case UJUMP:
4664 case RJUMP:
4665 case CJUMP:
4666 case SJUMP:
4667 case FJUMP:
4668 printf("Jump in the delay slot. This is probably a bug.\n");
4669 }
4670 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4671 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4672 if(internal_branch(regs[t].is32,ba[i]+4))
4673 assem_debug("branch: internal\n");
4674 else
4675 assem_debug("branch: external\n");
4676 assert(internal_branch(regs[t].is32,ba[i]+4));
4677 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4678 emit_jmp(0);
4679}
4680
4681void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4682{
4683 int count;
4684 int jaddr;
4685 int idle=0;
4686 if(itype[i]==RJUMP)
4687 {
4688 *adj=0;
4689 }
4690 //if(ba[i]>=start && ba[i]<(start+slen*4))
4691 if(internal_branch(branch_regs[i].is32,ba[i]))
4692 {
4693 int t=(ba[i]-start)>>2;
4694 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4695 else *adj=ccadj[t];
4696 }
4697 else
4698 {
4699 *adj=0;
4700 }
4701 count=ccadj[i];
4702 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4703 // Idle loop
4704 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4705 idle=(int)out;
4706 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4707 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4708 jaddr=(int)out;
4709 emit_jmp(0);
4710 }
4711 else if(*adj==0||invert) {
4712 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4713 jaddr=(int)out;
4714 emit_jns(0);
4715 }
4716 else
4717 {
4718 emit_cmpimm(HOST_CCREG,-2*(count+2));
4719 jaddr=(int)out;
4720 emit_jns(0);
4721 }
4722 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4723}
4724
4725void do_ccstub(int n)
4726{
4727 literal_pool(256);
4728 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4729 set_jump_target(stubs[n][1],(int)out);
4730 int i=stubs[n][4];
4731 if(stubs[n][6]==NULLDS) {
4732 // Delay slot instruction is nullified ("likely" branch)
4733 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4734 }
4735 else if(stubs[n][6]!=TAKEN) {
4736 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4737 }
4738 else {
4739 if(internal_branch(branch_regs[i].is32,ba[i]))
4740 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4741 }
4742 if(stubs[n][5]!=-1)
4743 {
4744 // Save PC as return address
4745 emit_movimm(stubs[n][5],EAX);
4746 emit_writeword(EAX,(int)&pcaddr);
4747 }
4748 else
4749 {
4750 // Return address depends on which way the branch goes
4751 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4752 {
4753 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4754 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4755 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4756 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4757 if(rs1[i]==0)
4758 {
4759 s1l=s2l;s1h=s2h;
4760 s2l=s2h=-1;
4761 }
4762 else if(rs2[i]==0)
4763 {
4764 s2l=s2h=-1;
4765 }
4766 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4767 s1h=s2h=-1;
4768 }
4769 assert(s1l>=0);
4770 #ifdef DESTRUCTIVE_WRITEBACK
4771 if(rs1[i]) {
4772 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4773 emit_loadreg(rs1[i],s1l);
4774 }
4775 else {
4776 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4777 emit_loadreg(rs2[i],s1l);
4778 }
4779 if(s2l>=0)
4780 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4781 emit_loadreg(rs2[i],s2l);
4782 #endif
4783 int hr=0;
4784 int addr,alt,ntaddr;
4785 while(hr<HOST_REGS)
4786 {
4787 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4788 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4789 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4790 {
4791 addr=hr++;break;
4792 }
4793 hr++;
4794 }
4795 while(hr<HOST_REGS)
4796 {
4797 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4798 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4799 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4800 {
4801 alt=hr++;break;
4802 }
4803 hr++;
4804 }
4805 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4806 {
4807 while(hr<HOST_REGS)
4808 {
4809 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4810 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4811 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4812 {
4813 ntaddr=hr;break;
4814 }
4815 hr++;
4816 }
4817 assert(hr<HOST_REGS);
4818 }
4819 if((opcode[i]&0x2f)==4) // BEQ
4820 {
4821 #ifdef HAVE_CMOV_IMM
4822 if(s1h<0) {
4823 if(s2l>=0) emit_cmp(s1l,s2l);
4824 else emit_test(s1l,s1l);
4825 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4826 }
4827 else
4828 #endif
4829 {
4830 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4831 if(s1h>=0) {
4832 if(s2h>=0) emit_cmp(s1h,s2h);
4833 else emit_test(s1h,s1h);
4834 emit_cmovne_reg(alt,addr);
4835 }
4836 if(s2l>=0) emit_cmp(s1l,s2l);
4837 else emit_test(s1l,s1l);
4838 emit_cmovne_reg(alt,addr);
4839 }
4840 }
4841 if((opcode[i]&0x2f)==5) // BNE
4842 {
4843 #ifdef HAVE_CMOV_IMM
4844 if(s1h<0) {
4845 if(s2l>=0) emit_cmp(s1l,s2l);
4846 else emit_test(s1l,s1l);
4847 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4848 }
4849 else
4850 #endif
4851 {
4852 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4853 if(s1h>=0) {
4854 if(s2h>=0) emit_cmp(s1h,s2h);
4855 else emit_test(s1h,s1h);
4856 emit_cmovne_reg(alt,addr);
4857 }
4858 if(s2l>=0) emit_cmp(s1l,s2l);
4859 else emit_test(s1l,s1l);
4860 emit_cmovne_reg(alt,addr);
4861 }
4862 }
4863 if((opcode[i]&0x2f)==6) // BLEZ
4864 {
4865 //emit_movimm(ba[i],alt);
4866 //emit_movimm(start+i*4+8,addr);
4867 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4868 emit_cmpimm(s1l,1);
4869 if(s1h>=0) emit_mov(addr,ntaddr);
4870 emit_cmovl_reg(alt,addr);
4871 if(s1h>=0) {
4872 emit_test(s1h,s1h);
4873 emit_cmovne_reg(ntaddr,addr);
4874 emit_cmovs_reg(alt,addr);
4875 }
4876 }
4877 if((opcode[i]&0x2f)==7) // BGTZ
4878 {
4879 //emit_movimm(ba[i],addr);
4880 //emit_movimm(start+i*4+8,ntaddr);
4881 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4882 emit_cmpimm(s1l,1);
4883 if(s1h>=0) emit_mov(addr,alt);
4884 emit_cmovl_reg(ntaddr,addr);
4885 if(s1h>=0) {
4886 emit_test(s1h,s1h);
4887 emit_cmovne_reg(alt,addr);
4888 emit_cmovs_reg(ntaddr,addr);
4889 }
4890 }
4891 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4892 {
4893 //emit_movimm(ba[i],alt);
4894 //emit_movimm(start+i*4+8,addr);
4895 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4896 if(s1h>=0) emit_test(s1h,s1h);
4897 else emit_test(s1l,s1l);
4898 emit_cmovs_reg(alt,addr);
4899 }
4900 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4901 {
4902 //emit_movimm(ba[i],addr);
4903 //emit_movimm(start+i*4+8,alt);
4904 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4905 if(s1h>=0) emit_test(s1h,s1h);
4906 else emit_test(s1l,s1l);
4907 emit_cmovs_reg(alt,addr);
4908 }
4909 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4910 if(source[i]&0x10000) // BC1T
4911 {
4912 //emit_movimm(ba[i],alt);
4913 //emit_movimm(start+i*4+8,addr);
4914 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4915 emit_testimm(s1l,0x800000);
4916 emit_cmovne_reg(alt,addr);
4917 }
4918 else // BC1F
4919 {
4920 //emit_movimm(ba[i],addr);
4921 //emit_movimm(start+i*4+8,alt);
4922 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4923 emit_testimm(s1l,0x800000);
4924 emit_cmovne_reg(alt,addr);
4925 }
4926 }
4927 emit_writeword(addr,(int)&pcaddr);
4928 }
4929 else
4930 if(itype[i]==RJUMP)
4931 {
4932 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4933 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4934 r=get_reg(branch_regs[i].regmap,RTEMP);
4935 }
4936 emit_writeword(r,(int)&pcaddr);
4937 }
4938 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4939 }
4940 // Update cycle count
4941 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4942 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4943 emit_call((int)cc_interrupt);
4944 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4945 if(stubs[n][6]==TAKEN) {
4946 if(internal_branch(branch_regs[i].is32,ba[i]))
4947 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4948 else if(itype[i]==RJUMP) {
4949 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4950 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4951 else
4952 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4953 }
4954 }else if(stubs[n][6]==NOTTAKEN) {
4955 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4956 else load_all_regs(branch_regs[i].regmap);
4957 }else if(stubs[n][6]==NULLDS) {
4958 // Delay slot instruction is nullified ("likely" branch)
4959 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4960 else load_all_regs(regs[i].regmap);
4961 }else{
4962 load_all_regs(branch_regs[i].regmap);
4963 }
4964 emit_jmp(stubs[n][2]); // return address
4965
4966 /* This works but uses a lot of memory...
4967 emit_readword((int)&last_count,ECX);
4968 emit_add(HOST_CCREG,ECX,EAX);
4969 emit_writeword(EAX,(int)&Count);
4970 emit_call((int)gen_interupt);
4971 emit_readword((int)&Count,HOST_CCREG);
4972 emit_readword((int)&next_interupt,EAX);
4973 emit_readword((int)&pending_exception,EBX);
4974 emit_writeword(EAX,(int)&last_count);
4975 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4976 emit_test(EBX,EBX);
4977 int jne_instr=(int)out;
4978 emit_jne(0);
4979 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4980 load_all_regs(branch_regs[i].regmap);
4981 emit_jmp(stubs[n][2]); // return address
4982 set_jump_target(jne_instr,(int)out);
4983 emit_readword((int)&pcaddr,EAX);
4984 // Call get_addr_ht instead of doing the hash table here.
4985 // This code is executed infrequently and takes up a lot of space
4986 // so smaller is better.
4987 emit_storereg(CCREG,HOST_CCREG);
4988 emit_pushreg(EAX);
4989 emit_call((int)get_addr_ht);
4990 emit_loadreg(CCREG,HOST_CCREG);
4991 emit_addimm(ESP,4,ESP);
4992 emit_jmpreg(EAX);*/
4993}
4994
4995add_to_linker(int addr,int target,int ext)
4996{
4997 link_addr[linkcount][0]=addr;
4998 link_addr[linkcount][1]=target;
4999 link_addr[linkcount][2]=ext;
5000 linkcount++;
5001}
5002
5003void ujump_assemble(int i,struct regstat *i_regs)
5004{
5005 signed char *i_regmap=i_regs->regmap;
5006 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5007 address_generation(i+1,i_regs,regs[i].regmap_entry);
5008 #ifdef REG_PREFETCH
5009 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5010 if(rt1[i]==31&&temp>=0)
5011 {
5012 int return_address=start+i*4+8;
5013 if(get_reg(branch_regs[i].regmap,31)>0)
5014 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5015 }
5016 #endif
5017 ds_assemble(i+1,i_regs);
5018 uint64_t bc_unneeded=branch_regs[i].u;
5019 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5020 bc_unneeded|=1|(1LL<<rt1[i]);
5021 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5022 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5023 bc_unneeded,bc_unneeded_upper);
5024 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5025 if(rt1[i]==31) {
5026 int rt;
5027 unsigned int return_address;
5028 assert(rt1[i+1]!=31);
5029 assert(rt2[i+1]!=31);
5030 rt=get_reg(branch_regs[i].regmap,31);
5031 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5032 //assert(rt>=0);
5033 return_address=start+i*4+8;
5034 if(rt>=0) {
5035 #ifdef USE_MINI_HT
5036 if(internal_branch(branch_regs[i].is32,return_address)) {
5037 int temp=rt+1;
5038 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5039 branch_regs[i].regmap[temp]>=0)
5040 {
5041 temp=get_reg(branch_regs[i].regmap,-1);
5042 }
5043 #ifdef HOST_TEMPREG
5044 if(temp<0) temp=HOST_TEMPREG;
5045 #endif
5046 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5047 else emit_movimm(return_address,rt);
5048 }
5049 else
5050 #endif
5051 {
5052 #ifdef REG_PREFETCH
5053 if(temp>=0)
5054 {
5055 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5056 }
5057 #endif
5058 emit_movimm(return_address,rt); // PC into link register
5059 #ifdef IMM_PREFETCH
5060 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5061 #endif
5062 }
5063 }
5064 }
5065 int cc,adj;
5066 cc=get_reg(branch_regs[i].regmap,CCREG);
5067 assert(cc==HOST_CCREG);
5068 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5069 #ifdef REG_PREFETCH
5070 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5071 #endif
5072 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5073 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5074 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5075 if(internal_branch(branch_regs[i].is32,ba[i]))
5076 assem_debug("branch: internal\n");
5077 else
5078 assem_debug("branch: external\n");
5079 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5080 ds_assemble_entry(i);
5081 }
5082 else {
5083 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5084 emit_jmp(0);
5085 }
5086}
5087
5088void rjump_assemble(int i,struct regstat *i_regs)
5089{
5090 signed char *i_regmap=i_regs->regmap;
5091 int temp;
5092 int rs,cc,adj;
5093 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5094 assert(rs>=0);
5095 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5096 // Delay slot abuse, make a copy of the branch address register
5097 temp=get_reg(branch_regs[i].regmap,RTEMP);
5098 assert(temp>=0);
5099 assert(regs[i].regmap[temp]==RTEMP);
5100 emit_mov(rs,temp);
5101 rs=temp;
5102 }
5103 address_generation(i+1,i_regs,regs[i].regmap_entry);
5104 #ifdef REG_PREFETCH
5105 if(rt1[i]==31)
5106 {
5107 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5108 int return_address=start+i*4+8;
5109 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5110 }
5111 }
5112 #endif
5113 #ifdef USE_MINI_HT
5114 if(rs1[i]==31) {
5115 int rh=get_reg(regs[i].regmap,RHASH);
5116 if(rh>=0) do_preload_rhash(rh);
5117 }
5118 #endif
5119 ds_assemble(i+1,i_regs);
5120 uint64_t bc_unneeded=branch_regs[i].u;
5121 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5122 bc_unneeded|=1|(1LL<<rt1[i]);
5123 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5124 bc_unneeded&=~(1LL<<rs1[i]);
5125 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5126 bc_unneeded,bc_unneeded_upper);
5127 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5128 if(rt1[i]!=0) {
57871462 5129 int rt,return_address;
5067f341 5130 assert(rt1[i+1]!=rt1[i]);
5131 assert(rt2[i+1]!=rt1[i]);
5132 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5133 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5134 assert(rt>=0);
5135 return_address=start+i*4+8;
5136 #ifdef REG_PREFETCH
5137 if(temp>=0)
5138 {
5139 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5140 }
5141 #endif
5142 emit_movimm(return_address,rt); // PC into link register
5143 #ifdef IMM_PREFETCH
5144 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5145 #endif
5146 }
5147 cc=get_reg(branch_regs[i].regmap,CCREG);
5148 assert(cc==HOST_CCREG);
5149 #ifdef USE_MINI_HT
5150 int rh=get_reg(branch_regs[i].regmap,RHASH);
5151 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5152 if(rs1[i]==31) {
5153 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5154 do_preload_rhtbl(ht);
5155 do_rhash(rs,rh);
5156 }
5157 #endif
5158 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5159 #ifdef DESTRUCTIVE_WRITEBACK
5160 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5161 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5162 emit_loadreg(rs1[i],rs);
5163 }
5164 }
5165 #endif
5166 #ifdef REG_PREFETCH
5167 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5168 #endif
5169 #ifdef USE_MINI_HT
5170 if(rs1[i]==31) {
5171 do_miniht_load(ht,rh);
5172 }
5173 #endif
5174 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5175 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5176 //assert(adj==0);
5177 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5178 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5179 emit_jns(0);
5180 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5181 #ifdef USE_MINI_HT
5182 if(rs1[i]==31) {
5183 do_miniht_jump(rs,rh,ht);
5184 }
5185 else
5186 #endif
5187 {
5188 //if(rs!=EAX) emit_mov(rs,EAX);
5189 //emit_jmp((int)jump_vaddr_eax);
5190 emit_jmp(jump_vaddr_reg[rs]);
5191 }
5192 /* Check hash table
5193 temp=!rs;
5194 emit_mov(rs,temp);
5195 emit_shrimm(rs,16,rs);
5196 emit_xor(temp,rs,rs);
5197 emit_movzwl_reg(rs,rs);
5198 emit_shlimm(rs,4,rs);
5199 emit_cmpmem_indexed((int)hash_table,rs,temp);
5200 emit_jne((int)out+14);
5201 emit_readword_indexed((int)hash_table+4,rs,rs);
5202 emit_jmpreg(rs);
5203 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5204 emit_addimm_no_flags(8,rs);
5205 emit_jeq((int)out-17);
5206 // No hit on hash table, call compiler
5207 emit_pushreg(temp);
5208//DEBUG >
5209#ifdef DEBUG_CYCLE_COUNT
5210 emit_readword((int)&last_count,ECX);
5211 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5212 emit_readword((int)&next_interupt,ECX);
5213 emit_writeword(HOST_CCREG,(int)&Count);
5214 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5215 emit_writeword(ECX,(int)&last_count);
5216#endif
5217//DEBUG <
5218 emit_storereg(CCREG,HOST_CCREG);
5219 emit_call((int)get_addr);
5220 emit_loadreg(CCREG,HOST_CCREG);
5221 emit_addimm(ESP,4,ESP);
5222 emit_jmpreg(EAX);*/
5223 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5224 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5225 #endif
5226}
5227
5228void cjump_assemble(int i,struct regstat *i_regs)
5229{
5230 signed char *i_regmap=i_regs->regmap;
5231 int cc;
5232 int match;
5233 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5234 assem_debug("match=%d\n",match);
5235 int s1h,s1l,s2h,s2l;
5236 int prev_cop1_usable=cop1_usable;
5237 int unconditional=0,nop=0;
5238 int only32=0;
5239 int ooo=1;
5240 int invert=0;
5241 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5242 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5243 if(likely[i]) ooo=0;
5244 if(!match) invert=1;
5245 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5246 if(i>(ba[i]-start)>>2) invert=1;
5247 #endif
5248
5249 if(ooo)
5250 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5251 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5252 {
5253 // Write-after-read dependency prevents out of order execution
5254 // First test branch condition, then execute delay slot, then branch
5255 ooo=0;
5256 }
5257
5258 if(ooo) {
5259 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5260 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5261 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5262 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5263 }
5264 else {
5265 s1l=get_reg(i_regmap,rs1[i]);
5266 s1h=get_reg(i_regmap,rs1[i]|64);
5267 s2l=get_reg(i_regmap,rs2[i]);
5268 s2h=get_reg(i_regmap,rs2[i]|64);
5269 }
5270 if(rs1[i]==0&&rs2[i]==0)
5271 {
5272 if(opcode[i]&1) nop=1;
5273 else unconditional=1;
5274 //assert(opcode[i]!=5);
5275 //assert(opcode[i]!=7);
5276 //assert(opcode[i]!=0x15);
5277 //assert(opcode[i]!=0x17);
5278 }
5279 else if(rs1[i]==0)
5280 {
5281 s1l=s2l;s1h=s2h;
5282 s2l=s2h=-1;
5283 only32=(regs[i].was32>>rs2[i])&1;
5284 }
5285 else if(rs2[i]==0)
5286 {
5287 s2l=s2h=-1;
5288 only32=(regs[i].was32>>rs1[i])&1;
5289 }
5290 else {
5291 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5292 }
5293
5294 if(ooo) {
5295 // Out of order execution (delay slot first)
5296 //printf("OOOE\n");
5297 address_generation(i+1,i_regs,regs[i].regmap_entry);
5298 ds_assemble(i+1,i_regs);
5299 int adj;
5300 uint64_t bc_unneeded=branch_regs[i].u;
5301 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5302 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5303 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5304 bc_unneeded|=1;
5305 bc_unneeded_upper|=1;
5306 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5307 bc_unneeded,bc_unneeded_upper);
5308 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5309 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5310 cc=get_reg(branch_regs[i].regmap,CCREG);
5311 assert(cc==HOST_CCREG);
5312 if(unconditional)
5313 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5314 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5315 //assem_debug("cycle count (adj)\n");
5316 if(unconditional) {
5317 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5318 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5319 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5320 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5321 if(internal)
5322 assem_debug("branch: internal\n");
5323 else
5324 assem_debug("branch: external\n");
5325 if(internal&&is_ds[(ba[i]-start)>>2]) {
5326 ds_assemble_entry(i);
5327 }
5328 else {
5329 add_to_linker((int)out,ba[i],internal);
5330 emit_jmp(0);
5331 }
5332 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5333 if(((u_int)out)&7) emit_addnop(0);
5334 #endif
5335 }
5336 }
5337 else if(nop) {
5338 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5339 int jaddr=(int)out;
5340 emit_jns(0);
5341 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5342 }
5343 else {
5344 int taken=0,nottaken=0,nottaken1=0;
5345 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5346 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5347 if(!only32)
5348 {
5349 assert(s1h>=0);
5350 if(opcode[i]==4) // BEQ
5351 {
5352 if(s2h>=0) emit_cmp(s1h,s2h);
5353 else emit_test(s1h,s1h);
5354 nottaken1=(int)out;
5355 emit_jne(1);
5356 }
5357 if(opcode[i]==5) // BNE
5358 {
5359 if(s2h>=0) emit_cmp(s1h,s2h);
5360 else emit_test(s1h,s1h);
5361 if(invert) taken=(int)out;
5362 else add_to_linker((int)out,ba[i],internal);
5363 emit_jne(0);
5364 }
5365 if(opcode[i]==6) // BLEZ
5366 {
5367 emit_test(s1h,s1h);
5368 if(invert) taken=(int)out;
5369 else add_to_linker((int)out,ba[i],internal);
5370 emit_js(0);
5371 nottaken1=(int)out;
5372 emit_jne(1);
5373 }
5374 if(opcode[i]==7) // BGTZ
5375 {
5376 emit_test(s1h,s1h);
5377 nottaken1=(int)out;
5378 emit_js(1);
5379 if(invert) taken=(int)out;
5380 else add_to_linker((int)out,ba[i],internal);
5381 emit_jne(0);
5382 }
5383 } // if(!only32)
5384
5385 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5386 assert(s1l>=0);
5387 if(opcode[i]==4) // BEQ
5388 {
5389 if(s2l>=0) emit_cmp(s1l,s2l);
5390 else emit_test(s1l,s1l);
5391 if(invert){
5392 nottaken=(int)out;
5393 emit_jne(1);
5394 }else{
5395 add_to_linker((int)out,ba[i],internal);
5396 emit_jeq(0);
5397 }
5398 }
5399 if(opcode[i]==5) // BNE
5400 {
5401 if(s2l>=0) emit_cmp(s1l,s2l);
5402 else emit_test(s1l,s1l);
5403 if(invert){
5404 nottaken=(int)out;
5405 emit_jeq(1);
5406 }else{
5407 add_to_linker((int)out,ba[i],internal);
5408 emit_jne(0);
5409 }
5410 }
5411 if(opcode[i]==6) // BLEZ
5412 {
5413 emit_cmpimm(s1l,1);
5414 if(invert){
5415 nottaken=(int)out;
5416 emit_jge(1);
5417 }else{
5418 add_to_linker((int)out,ba[i],internal);
5419 emit_jl(0);
5420 }
5421 }
5422 if(opcode[i]==7) // BGTZ
5423 {
5424 emit_cmpimm(s1l,1);
5425 if(invert){
5426 nottaken=(int)out;
5427 emit_jl(1);
5428 }else{
5429 add_to_linker((int)out,ba[i],internal);
5430 emit_jge(0);
5431 }
5432 }
5433 if(invert) {
5434 if(taken) set_jump_target(taken,(int)out);
5435 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5436 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5437 if(adj) {
5438 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5439 add_to_linker((int)out,ba[i],internal);
5440 }else{
5441 emit_addnop(13);
5442 add_to_linker((int)out,ba[i],internal*2);
5443 }
5444 emit_jmp(0);
5445 }else
5446 #endif
5447 {
5448 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5449 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5450 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5451 if(internal)
5452 assem_debug("branch: internal\n");
5453 else
5454 assem_debug("branch: external\n");
5455 if(internal&&is_ds[(ba[i]-start)>>2]) {
5456 ds_assemble_entry(i);
5457 }
5458 else {
5459 add_to_linker((int)out,ba[i],internal);
5460 emit_jmp(0);
5461 }
5462 }
5463 set_jump_target(nottaken,(int)out);
5464 }
5465
5466 if(nottaken1) set_jump_target(nottaken1,(int)out);
5467 if(adj) {
5468 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5469 }
5470 } // (!unconditional)
5471 } // if(ooo)
5472 else
5473 {
5474 // In-order execution (branch first)
5475 //if(likely[i]) printf("IOL\n");
5476 //else
5477 //printf("IOE\n");
5478 int taken=0,nottaken=0,nottaken1=0;
5479 if(!unconditional&&!nop) {
5480 if(!only32)
5481 {
5482 assert(s1h>=0);
5483 if((opcode[i]&0x2f)==4) // BEQ
5484 {
5485 if(s2h>=0) emit_cmp(s1h,s2h);
5486 else emit_test(s1h,s1h);
5487 nottaken1=(int)out;
5488 emit_jne(2);
5489 }
5490 if((opcode[i]&0x2f)==5) // BNE
5491 {
5492 if(s2h>=0) emit_cmp(s1h,s2h);
5493 else emit_test(s1h,s1h);
5494 taken=(int)out;
5495 emit_jne(1);
5496 }
5497 if((opcode[i]&0x2f)==6) // BLEZ
5498 {
5499 emit_test(s1h,s1h);
5500 taken=(int)out;
5501 emit_js(1);
5502 nottaken1=(int)out;
5503 emit_jne(2);
5504 }
5505 if((opcode[i]&0x2f)==7) // BGTZ
5506 {
5507 emit_test(s1h,s1h);
5508 nottaken1=(int)out;
5509 emit_js(2);
5510 taken=(int)out;
5511 emit_jne(1);
5512 }
5513 } // if(!only32)
5514
5515 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5516 assert(s1l>=0);
5517 if((opcode[i]&0x2f)==4) // BEQ
5518 {
5519 if(s2l>=0) emit_cmp(s1l,s2l);
5520 else emit_test(s1l,s1l);
5521 nottaken=(int)out;
5522 emit_jne(2);
5523 }
5524 if((opcode[i]&0x2f)==5) // BNE
5525 {
5526 if(s2l>=0) emit_cmp(s1l,s2l);
5527 else emit_test(s1l,s1l);
5528 nottaken=(int)out;
5529 emit_jeq(2);
5530 }
5531 if((opcode[i]&0x2f)==6) // BLEZ
5532 {
5533 emit_cmpimm(s1l,1);
5534 nottaken=(int)out;
5535 emit_jge(2);
5536 }
5537 if((opcode[i]&0x2f)==7) // BGTZ
5538 {
5539 emit_cmpimm(s1l,1);
5540 nottaken=(int)out;
5541 emit_jl(2);
5542 }
5543 } // if(!unconditional)
5544 int adj;
5545 uint64_t ds_unneeded=branch_regs[i].u;
5546 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5547 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5548 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5549 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5550 ds_unneeded|=1;
5551 ds_unneeded_upper|=1;
5552 // branch taken
5553 if(!nop) {
5554 if(taken) set_jump_target(taken,(int)out);
5555 assem_debug("1:\n");
5556 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5557 ds_unneeded,ds_unneeded_upper);
5558 // load regs
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5560 address_generation(i+1,&branch_regs[i],0);
5561 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5562 ds_assemble(i+1,&branch_regs[i]);
5563 cc=get_reg(branch_regs[i].regmap,CCREG);
5564 if(cc==-1) {
5565 emit_loadreg(CCREG,cc=HOST_CCREG);
5566 // CHECK: Is the following instruction (fall thru) allocated ok?
5567 }
5568 assert(cc==HOST_CCREG);
5569 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5570 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5571 assem_debug("cycle count (adj)\n");
5572 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5573 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5574 if(internal)
5575 assem_debug("branch: internal\n");
5576 else
5577 assem_debug("branch: external\n");
5578 if(internal&&is_ds[(ba[i]-start)>>2]) {
5579 ds_assemble_entry(i);
5580 }
5581 else {
5582 add_to_linker((int)out,ba[i],internal);
5583 emit_jmp(0);
5584 }
5585 }
5586 // branch not taken
5587 cop1_usable=prev_cop1_usable;
5588 if(!unconditional) {
5589 if(nottaken1) set_jump_target(nottaken1,(int)out);
5590 set_jump_target(nottaken,(int)out);
5591 assem_debug("2:\n");
5592 if(!likely[i]) {
5593 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5594 ds_unneeded,ds_unneeded_upper);
5595 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5596 address_generation(i+1,&branch_regs[i],0);
5597 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5598 ds_assemble(i+1,&branch_regs[i]);
5599 }
5600 cc=get_reg(branch_regs[i].regmap,CCREG);
5601 if(cc==-1&&!likely[i]) {
5602 // Cycle count isn't in a register, temporarily load it then write it out
5603 emit_loadreg(CCREG,HOST_CCREG);
5604 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5605 int jaddr=(int)out;
5606 emit_jns(0);
5607 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5608 emit_storereg(CCREG,HOST_CCREG);
5609 }
5610 else{
5611 cc=get_reg(i_regmap,CCREG);
5612 assert(cc==HOST_CCREG);
5613 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5614 int jaddr=(int)out;
5615 emit_jns(0);
5616 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5617 }
5618 }
5619 }
5620}
5621
5622void sjump_assemble(int i,struct regstat *i_regs)
5623{
5624 signed char *i_regmap=i_regs->regmap;
5625 int cc;
5626 int match;
5627 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5628 assem_debug("smatch=%d\n",match);
5629 int s1h,s1l;
5630 int prev_cop1_usable=cop1_usable;
5631 int unconditional=0,nevertaken=0;
5632 int only32=0;
5633 int ooo=1;
5634 int invert=0;
5635 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5636 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5637 if(likely[i]) ooo=0;
5638 if(!match) invert=1;
5639 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5640 if(i>(ba[i]-start)>>2) invert=1;
5641 #endif
5642
5643 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5644 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5645
5646 if(ooo)
5647 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5648 {
5649 // Write-after-read dependency prevents out of order execution
5650 // First test branch condition, then execute delay slot, then branch
5651 ooo=0;
5652 }
57871462 5653
5654 if(ooo) {
5655 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5656 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5657 }
5658 else {
5659 s1l=get_reg(i_regmap,rs1[i]);
5660 s1h=get_reg(i_regmap,rs1[i]|64);
5661 }
5662 if(rs1[i]==0)
5663 {
5664 if(opcode2[i]&1) unconditional=1;
5665 else nevertaken=1;
5666 // These are never taken (r0 is never less than zero)
5667 //assert(opcode2[i]!=0);
5668 //assert(opcode2[i]!=2);
5669 //assert(opcode2[i]!=0x10);
5670 //assert(opcode2[i]!=0x12);
5671 }
5672 else {
5673 only32=(regs[i].was32>>rs1[i])&1;
5674 }
5675
5676 if(ooo) {
5677 // Out of order execution (delay slot first)
5678 //printf("OOOE\n");
5679 address_generation(i+1,i_regs,regs[i].regmap_entry);
5680 ds_assemble(i+1,i_regs);
5681 int adj;
5682 uint64_t bc_unneeded=branch_regs[i].u;
5683 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5684 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5685 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5686 bc_unneeded|=1;
5687 bc_unneeded_upper|=1;
5688 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5689 bc_unneeded,bc_unneeded_upper);
5690 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5691 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5692 if(rt1[i]==31) {
5693 int rt,return_address;
5694 assert(rt1[i+1]!=31);
5695 assert(rt2[i+1]!=31);
5696 rt=get_reg(branch_regs[i].regmap,31);
5697 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5698 if(rt>=0) {
5699 // Save the PC even if the branch is not taken
5700 return_address=start+i*4+8;
5701 emit_movimm(return_address,rt); // PC into link register
5702 #ifdef IMM_PREFETCH
5703 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5704 #endif
5705 }
5706 }
5707 cc=get_reg(branch_regs[i].regmap,CCREG);
5708 assert(cc==HOST_CCREG);
5709 if(unconditional)
5710 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5711 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5712 assem_debug("cycle count (adj)\n");
5713 if(unconditional) {
5714 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5715 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5716 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5717 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5718 if(internal)
5719 assem_debug("branch: internal\n");
5720 else
5721 assem_debug("branch: external\n");
5722 if(internal&&is_ds[(ba[i]-start)>>2]) {
5723 ds_assemble_entry(i);
5724 }
5725 else {
5726 add_to_linker((int)out,ba[i],internal);
5727 emit_jmp(0);
5728 }
5729 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5730 if(((u_int)out)&7) emit_addnop(0);
5731 #endif
5732 }
5733 }
5734 else if(nevertaken) {
5735 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5736 int jaddr=(int)out;
5737 emit_jns(0);
5738 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5739 }
5740 else {
5741 int nottaken=0;
5742 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5743 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5744 if(!only32)
5745 {
5746 assert(s1h>=0);
df894a3a 5747 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5748 {
5749 emit_test(s1h,s1h);
5750 if(invert){
5751 nottaken=(int)out;
5752 emit_jns(1);
5753 }else{
5754 add_to_linker((int)out,ba[i],internal);
5755 emit_js(0);
5756 }
5757 }
df894a3a 5758 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5759 {
5760 emit_test(s1h,s1h);
5761 if(invert){
5762 nottaken=(int)out;
5763 emit_js(1);
5764 }else{
5765 add_to_linker((int)out,ba[i],internal);
5766 emit_jns(0);
5767 }
5768 }
5769 } // if(!only32)
5770 else
5771 {
5772 assert(s1l>=0);
df894a3a 5773 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5774 {
5775 emit_test(s1l,s1l);
5776 if(invert){
5777 nottaken=(int)out;
5778 emit_jns(1);
5779 }else{
5780 add_to_linker((int)out,ba[i],internal);
5781 emit_js(0);
5782 }
5783 }
df894a3a 5784 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5785 {
5786 emit_test(s1l,s1l);
5787 if(invert){
5788 nottaken=(int)out;
5789 emit_js(1);
5790 }else{
5791 add_to_linker((int)out,ba[i],internal);
5792 emit_jns(0);
5793 }
5794 }
5795 } // if(!only32)
5796
5797 if(invert) {
5798 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5799 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5800 if(adj) {
5801 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5802 add_to_linker((int)out,ba[i],internal);
5803 }else{
5804 emit_addnop(13);
5805 add_to_linker((int)out,ba[i],internal*2);
5806 }
5807 emit_jmp(0);
5808 }else
5809 #endif
5810 {
5811 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5812 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5813 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5814 if(internal)
5815 assem_debug("branch: internal\n");
5816 else
5817 assem_debug("branch: external\n");
5818 if(internal&&is_ds[(ba[i]-start)>>2]) {
5819 ds_assemble_entry(i);
5820 }
5821 else {
5822 add_to_linker((int)out,ba[i],internal);
5823 emit_jmp(0);
5824 }
5825 }
5826 set_jump_target(nottaken,(int)out);
5827 }
5828
5829 if(adj) {
5830 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5831 }
5832 } // (!unconditional)
5833 } // if(ooo)
5834 else
5835 {
5836 // In-order execution (branch first)
5837 //printf("IOE\n");
5838 int nottaken=0;
a6491170 5839 if(rt1[i]==31) {
5840 int rt,return_address;
5841 assert(rt1[i+1]!=31);
5842 assert(rt2[i+1]!=31);
5843 rt=get_reg(branch_regs[i].regmap,31);
5844 if(rt>=0) {
5845 // Save the PC even if the branch is not taken
5846 return_address=start+i*4+8;
5847 emit_movimm(return_address,rt); // PC into link register
5848 #ifdef IMM_PREFETCH
5849 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5850 #endif
5851 }
5852 }
57871462 5853 if(!unconditional) {
5854 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5855 if(!only32)
5856 {
5857 assert(s1h>=0);
a6491170 5858 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5859 {
5860 emit_test(s1h,s1h);
5861 nottaken=(int)out;
5862 emit_jns(1);
5863 }
a6491170 5864 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5865 {
5866 emit_test(s1h,s1h);
5867 nottaken=(int)out;
5868 emit_js(1);
5869 }
5870 } // if(!only32)
5871 else
5872 {
5873 assert(s1l>=0);
a6491170 5874 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5875 {
5876 emit_test(s1l,s1l);
5877 nottaken=(int)out;
5878 emit_jns(1);
5879 }
a6491170 5880 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5881 {
5882 emit_test(s1l,s1l);
5883 nottaken=(int)out;
5884 emit_js(1);
5885 }
5886 }
5887 } // if(!unconditional)
5888 int adj;
5889 uint64_t ds_unneeded=branch_regs[i].u;
5890 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5891 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5892 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5893 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5894 ds_unneeded|=1;
5895 ds_unneeded_upper|=1;
5896 // branch taken
5897 if(!nevertaken) {
5898 //assem_debug("1:\n");
5899 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5900 ds_unneeded,ds_unneeded_upper);
5901 // load regs
5902 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5903 address_generation(i+1,&branch_regs[i],0);
5904 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5905 ds_assemble(i+1,&branch_regs[i]);
5906 cc=get_reg(branch_regs[i].regmap,CCREG);
5907 if(cc==-1) {
5908 emit_loadreg(CCREG,cc=HOST_CCREG);
5909 // CHECK: Is the following instruction (fall thru) allocated ok?
5910 }
5911 assert(cc==HOST_CCREG);
5912 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5913 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5914 assem_debug("cycle count (adj)\n");
5915 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5916 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5917 if(internal)
5918 assem_debug("branch: internal\n");
5919 else
5920 assem_debug("branch: external\n");
5921 if(internal&&is_ds[(ba[i]-start)>>2]) {
5922 ds_assemble_entry(i);
5923 }
5924 else {
5925 add_to_linker((int)out,ba[i],internal);
5926 emit_jmp(0);
5927 }
5928 }
5929 // branch not taken
5930 cop1_usable=prev_cop1_usable;
5931 if(!unconditional) {
5932 set_jump_target(nottaken,(int)out);
5933 assem_debug("1:\n");
5934 if(!likely[i]) {
5935 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5936 ds_unneeded,ds_unneeded_upper);
5937 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5938 address_generation(i+1,&branch_regs[i],0);
5939 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5940 ds_assemble(i+1,&branch_regs[i]);
5941 }
5942 cc=get_reg(branch_regs[i].regmap,CCREG);
5943 if(cc==-1&&!likely[i]) {
5944 // Cycle count isn't in a register, temporarily load it then write it out
5945 emit_loadreg(CCREG,HOST_CCREG);
5946 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5947 int jaddr=(int)out;
5948 emit_jns(0);
5949 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5950 emit_storereg(CCREG,HOST_CCREG);
5951 }
5952 else{
5953 cc=get_reg(i_regmap,CCREG);
5954 assert(cc==HOST_CCREG);
5955 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5956 int jaddr=(int)out;
5957 emit_jns(0);
5958 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5959 }
5960 }
5961 }
5962}
5963
5964void fjump_assemble(int i,struct regstat *i_regs)
5965{
5966 signed char *i_regmap=i_regs->regmap;
5967 int cc;
5968 int match;
5969 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5970 assem_debug("fmatch=%d\n",match);
5971 int fs,cs;
5972 int eaddr;
5973 int ooo=1;
5974 int invert=0;
5975 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5976 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5977 if(likely[i]) ooo=0;
5978 if(!match) invert=1;
5979 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5980 if(i>(ba[i]-start)>>2) invert=1;
5981 #endif
5982
5983 if(ooo)
5984 if(itype[i+1]==FCOMP)
5985 {
5986 // Write-after-read dependency prevents out of order execution
5987 // First test branch condition, then execute delay slot, then branch
5988 ooo=0;
5989 }
5990
5991 if(ooo) {
5992 fs=get_reg(branch_regs[i].regmap,FSREG);
5993 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5994 }
5995 else {
5996 fs=get_reg(i_regmap,FSREG);
5997 }
5998
5999 // Check cop1 unusable
6000 if(!cop1_usable) {
6001 cs=get_reg(i_regmap,CSREG);
6002 assert(cs>=0);
6003 emit_testimm(cs,0x20000000);
6004 eaddr=(int)out;
6005 emit_jeq(0);
6006 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6007 cop1_usable=1;
6008 }
6009
6010 if(ooo) {
6011 // Out of order execution (delay slot first)
6012 //printf("OOOE\n");
6013 ds_assemble(i+1,i_regs);
6014 int adj;
6015 uint64_t bc_unneeded=branch_regs[i].u;
6016 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6017 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6018 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6019 bc_unneeded|=1;
6020 bc_unneeded_upper|=1;
6021 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6022 bc_unneeded,bc_unneeded_upper);
6023 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6024 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6025 cc=get_reg(branch_regs[i].regmap,CCREG);
6026 assert(cc==HOST_CCREG);
6027 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6028 assem_debug("cycle count (adj)\n");
6029 if(1) {
6030 int nottaken=0;
6031 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6032 if(1) {
6033 assert(fs>=0);
6034 emit_testimm(fs,0x800000);
6035 if(source[i]&0x10000) // BC1T
6036 {
6037 if(invert){
6038 nottaken=(int)out;
6039 emit_jeq(1);
6040 }else{
6041 add_to_linker((int)out,ba[i],internal);
6042 emit_jne(0);
6043 }
6044 }
6045 else // BC1F
6046 if(invert){
6047 nottaken=(int)out;
6048 emit_jne(1);
6049 }else{
6050 add_to_linker((int)out,ba[i],internal);
6051 emit_jeq(0);
6052 }
6053 {
6054 }
6055 } // if(!only32)
6056
6057 if(invert) {
6058 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6059 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6060 else if(match) emit_addnop(13);
6061 #endif
6062 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6063 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6064 if(internal)
6065 assem_debug("branch: internal\n");
6066 else
6067 assem_debug("branch: external\n");
6068 if(internal&&is_ds[(ba[i]-start)>>2]) {
6069 ds_assemble_entry(i);
6070 }
6071 else {
6072 add_to_linker((int)out,ba[i],internal);
6073 emit_jmp(0);
6074 }
6075 set_jump_target(nottaken,(int)out);
6076 }
6077
6078 if(adj) {
6079 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6080 }
6081 } // (!unconditional)
6082 } // if(ooo)
6083 else
6084 {
6085 // In-order execution (branch first)
6086 //printf("IOE\n");
6087 int nottaken=0;
6088 if(1) {
6089 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6090 if(1) {
6091 assert(fs>=0);
6092 emit_testimm(fs,0x800000);
6093 if(source[i]&0x10000) // BC1T
6094 {
6095 nottaken=(int)out;
6096 emit_jeq(1);
6097 }
6098 else // BC1F
6099 {
6100 nottaken=(int)out;
6101 emit_jne(1);
6102 }
6103 }
6104 } // if(!unconditional)
6105 int adj;
6106 uint64_t ds_unneeded=branch_regs[i].u;
6107 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6108 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6109 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6110 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6111 ds_unneeded|=1;
6112 ds_unneeded_upper|=1;
6113 // branch taken
6114 //assem_debug("1:\n");
6115 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6116 ds_unneeded,ds_unneeded_upper);
6117 // load regs
6118 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6119 address_generation(i+1,&branch_regs[i],0);
6120 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6121 ds_assemble(i+1,&branch_regs[i]);
6122 cc=get_reg(branch_regs[i].regmap,CCREG);
6123 if(cc==-1) {
6124 emit_loadreg(CCREG,cc=HOST_CCREG);
6125 // CHECK: Is the following instruction (fall thru) allocated ok?
6126 }
6127 assert(cc==HOST_CCREG);
6128 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6129 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6130 assem_debug("cycle count (adj)\n");
6131 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6132 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6133 if(internal)
6134 assem_debug("branch: internal\n");
6135 else
6136 assem_debug("branch: external\n");
6137 if(internal&&is_ds[(ba[i]-start)>>2]) {
6138 ds_assemble_entry(i);
6139 }
6140 else {
6141 add_to_linker((int)out,ba[i],internal);
6142 emit_jmp(0);
6143 }
6144
6145 // branch not taken
6146 if(1) { // <- FIXME (don't need this)
6147 set_jump_target(nottaken,(int)out);
6148 assem_debug("1:\n");
6149 if(!likely[i]) {
6150 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6151 ds_unneeded,ds_unneeded_upper);
6152 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6153 address_generation(i+1,&branch_regs[i],0);
6154 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6155 ds_assemble(i+1,&branch_regs[i]);
6156 }
6157 cc=get_reg(branch_regs[i].regmap,CCREG);
6158 if(cc==-1&&!likely[i]) {
6159 // Cycle count isn't in a register, temporarily load it then write it out
6160 emit_loadreg(CCREG,HOST_CCREG);
6161 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6162 int jaddr=(int)out;
6163 emit_jns(0);
6164 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6165 emit_storereg(CCREG,HOST_CCREG);
6166 }
6167 else{
6168 cc=get_reg(i_regmap,CCREG);
6169 assert(cc==HOST_CCREG);
6170 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6171 int jaddr=(int)out;
6172 emit_jns(0);
6173 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6174 }
6175 }
6176 }
6177}
6178
6179static void pagespan_assemble(int i,struct regstat *i_regs)
6180{
6181 int s1l=get_reg(i_regs->regmap,rs1[i]);
6182 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6183 int s2l=get_reg(i_regs->regmap,rs2[i]);
6184 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6185 void *nt_branch=NULL;
6186 int taken=0;
6187 int nottaken=0;
6188 int unconditional=0;
6189 if(rs1[i]==0)
6190 {
6191 s1l=s2l;s1h=s2h;
6192 s2l=s2h=-1;
6193 }
6194 else if(rs2[i]==0)
6195 {
6196 s2l=s2h=-1;
6197 }
6198 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6199 s1h=s2h=-1;
6200 }
6201 int hr=0;
6202 int addr,alt,ntaddr;
6203 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6204 else {
6205 while(hr<HOST_REGS)
6206 {
6207 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6208 (i_regs->regmap[hr]&63)!=rs1[i] &&
6209 (i_regs->regmap[hr]&63)!=rs2[i] )
6210 {
6211 addr=hr++;break;
6212 }
6213 hr++;
6214 }
6215 }
6216 while(hr<HOST_REGS)
6217 {
6218 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6219 (i_regs->regmap[hr]&63)!=rs1[i] &&
6220 (i_regs->regmap[hr]&63)!=rs2[i] )
6221 {
6222 alt=hr++;break;
6223 }
6224 hr++;
6225 }
6226 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6227 {
6228 while(hr<HOST_REGS)
6229 {
6230 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6231 (i_regs->regmap[hr]&63)!=rs1[i] &&
6232 (i_regs->regmap[hr]&63)!=rs2[i] )
6233 {
6234 ntaddr=hr;break;
6235 }
6236 hr++;
6237 }
6238 }
6239 assert(hr<HOST_REGS);
6240 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6241 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6242 }
6243 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6244 if(opcode[i]==2) // J
6245 {
6246 unconditional=1;
6247 }
6248 if(opcode[i]==3) // JAL
6249 {
6250 // TODO: mini_ht
6251 int rt=get_reg(i_regs->regmap,31);
6252 emit_movimm(start+i*4+8,rt);
6253 unconditional=1;
6254 }
6255 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6256 {
6257 emit_mov(s1l,addr);
6258 if(opcode2[i]==9) // JALR
6259 {
5067f341 6260 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6261 emit_movimm(start+i*4+8,rt);
6262 }
6263 }
6264 if((opcode[i]&0x3f)==4) // BEQ
6265 {
6266 if(rs1[i]==rs2[i])
6267 {
6268 unconditional=1;
6269 }
6270 else
6271 #ifdef HAVE_CMOV_IMM
6272 if(s1h<0) {
6273 if(s2l>=0) emit_cmp(s1l,s2l);
6274 else emit_test(s1l,s1l);
6275 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6276 }
6277 else
6278 #endif
6279 {
6280 assert(s1l>=0);
6281 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6282 if(s1h>=0) {
6283 if(s2h>=0) emit_cmp(s1h,s2h);
6284 else emit_test(s1h,s1h);
6285 emit_cmovne_reg(alt,addr);
6286 }
6287 if(s2l>=0) emit_cmp(s1l,s2l);
6288 else emit_test(s1l,s1l);
6289 emit_cmovne_reg(alt,addr);
6290 }
6291 }
6292 if((opcode[i]&0x3f)==5) // BNE
6293 {
6294 #ifdef HAVE_CMOV_IMM
6295 if(s1h<0) {
6296 if(s2l>=0) emit_cmp(s1l,s2l);
6297 else emit_test(s1l,s1l);
6298 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6299 }
6300 else
6301 #endif
6302 {
6303 assert(s1l>=0);
6304 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6305 if(s1h>=0) {
6306 if(s2h>=0) emit_cmp(s1h,s2h);
6307 else emit_test(s1h,s1h);
6308 emit_cmovne_reg(alt,addr);
6309 }
6310 if(s2l>=0) emit_cmp(s1l,s2l);
6311 else emit_test(s1l,s1l);
6312 emit_cmovne_reg(alt,addr);
6313 }
6314 }
6315 if((opcode[i]&0x3f)==0x14) // BEQL
6316 {
6317 if(s1h>=0) {
6318 if(s2h>=0) emit_cmp(s1h,s2h);
6319 else emit_test(s1h,s1h);
6320 nottaken=(int)out;
6321 emit_jne(0);
6322 }
6323 if(s2l>=0) emit_cmp(s1l,s2l);
6324 else emit_test(s1l,s1l);
6325 if(nottaken) set_jump_target(nottaken,(int)out);
6326 nottaken=(int)out;
6327 emit_jne(0);
6328 }
6329 if((opcode[i]&0x3f)==0x15) // BNEL
6330 {
6331 if(s1h>=0) {
6332 if(s2h>=0) emit_cmp(s1h,s2h);
6333 else emit_test(s1h,s1h);
6334 taken=(int)out;
6335 emit_jne(0);
6336 }
6337 if(s2l>=0) emit_cmp(s1l,s2l);
6338 else emit_test(s1l,s1l);
6339 nottaken=(int)out;
6340 emit_jeq(0);
6341 if(taken) set_jump_target(taken,(int)out);
6342 }
6343 if((opcode[i]&0x3f)==6) // BLEZ
6344 {
6345 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6346 emit_cmpimm(s1l,1);
6347 if(s1h>=0) emit_mov(addr,ntaddr);
6348 emit_cmovl_reg(alt,addr);
6349 if(s1h>=0) {
6350 emit_test(s1h,s1h);
6351 emit_cmovne_reg(ntaddr,addr);
6352 emit_cmovs_reg(alt,addr);
6353 }
6354 }
6355 if((opcode[i]&0x3f)==7) // BGTZ
6356 {
6357 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6358 emit_cmpimm(s1l,1);
6359 if(s1h>=0) emit_mov(addr,alt);
6360 emit_cmovl_reg(ntaddr,addr);
6361 if(s1h>=0) {
6362 emit_test(s1h,s1h);
6363 emit_cmovne_reg(alt,addr);
6364 emit_cmovs_reg(ntaddr,addr);
6365 }
6366 }
6367 if((opcode[i]&0x3f)==0x16) // BLEZL
6368 {
6369 assert((opcode[i]&0x3f)!=0x16);
6370 }
6371 if((opcode[i]&0x3f)==0x17) // BGTZL
6372 {
6373 assert((opcode[i]&0x3f)!=0x17);
6374 }
6375 assert(opcode[i]!=1); // BLTZ/BGEZ
6376
6377 //FIXME: Check CSREG
6378 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6379 if((source[i]&0x30000)==0) // BC1F
6380 {
6381 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6382 emit_testimm(s1l,0x800000);
6383 emit_cmovne_reg(alt,addr);
6384 }
6385 if((source[i]&0x30000)==0x10000) // BC1T
6386 {
6387 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6388 emit_testimm(s1l,0x800000);
6389 emit_cmovne_reg(alt,addr);
6390 }
6391 if((source[i]&0x30000)==0x20000) // BC1FL
6392 {
6393 emit_testimm(s1l,0x800000);
6394 nottaken=(int)out;
6395 emit_jne(0);
6396 }
6397 if((source[i]&0x30000)==0x30000) // BC1TL
6398 {
6399 emit_testimm(s1l,0x800000);
6400 nottaken=(int)out;
6401 emit_jeq(0);
6402 }
6403 }
6404
6405 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6406 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6407 if(likely[i]||unconditional)
6408 {
6409 emit_movimm(ba[i],HOST_BTREG);
6410 }
6411 else if(addr!=HOST_BTREG)
6412 {
6413 emit_mov(addr,HOST_BTREG);
6414 }
6415 void *branch_addr=out;
6416 emit_jmp(0);
6417 int target_addr=start+i*4+5;
6418 void *stub=out;
6419 void *compiled_target_addr=check_addr(target_addr);
6420 emit_extjump_ds((int)branch_addr,target_addr);
6421 if(compiled_target_addr) {
6422 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6423 add_link(target_addr,stub);
6424 }
6425 else set_jump_target((int)branch_addr,(int)stub);
6426 if(likely[i]) {
6427 // Not-taken path
6428 set_jump_target((int)nottaken,(int)out);
6429 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6430 void *branch_addr=out;
6431 emit_jmp(0);
6432 int target_addr=start+i*4+8;
6433 void *stub=out;
6434 void *compiled_target_addr=check_addr(target_addr);
6435 emit_extjump_ds((int)branch_addr,target_addr);
6436 if(compiled_target_addr) {
6437 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6438 add_link(target_addr,stub);
6439 }
6440 else set_jump_target((int)branch_addr,(int)stub);
6441 }
6442}
6443
6444// Assemble the delay slot for the above
6445static void pagespan_ds()
6446{
6447 assem_debug("initial delay slot:\n");
6448 u_int vaddr=start+1;
94d23bb9 6449 u_int page=get_page(vaddr);
6450 u_int vpage=get_vpage(vaddr);
57871462 6451 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6452 do_dirty_stub_ds();
6453 ll_add(jump_in+page,vaddr,(void *)out);
6454 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6455 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6456 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6457 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6458 emit_writeword(HOST_BTREG,(int)&branch_target);
6459 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6460 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6461 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6462 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6463 cop1_usable=0;
6464 is_delayslot=0;
6465 switch(itype[0]) {
6466 case ALU:
6467 alu_assemble(0,&regs[0]);break;
6468 case IMM16:
6469 imm16_assemble(0,&regs[0]);break;
6470 case SHIFT:
6471 shift_assemble(0,&regs[0]);break;
6472 case SHIFTIMM:
6473 shiftimm_assemble(0,&regs[0]);break;
6474 case LOAD:
6475 load_assemble(0,&regs[0]);break;
6476 case LOADLR:
6477 loadlr_assemble(0,&regs[0]);break;
6478 case STORE:
6479 store_assemble(0,&regs[0]);break;
6480 case STORELR:
6481 storelr_assemble(0,&regs[0]);break;
6482 case COP0:
6483 cop0_assemble(0,&regs[0]);break;
6484 case COP1:
6485 cop1_assemble(0,&regs[0]);break;
6486 case C1LS:
6487 c1ls_assemble(0,&regs[0]);break;
b9b61529 6488 case COP2:
6489 cop2_assemble(0,&regs[0]);break;
6490 case C2LS:
6491 c2ls_assemble(0,&regs[0]);break;
6492 case C2OP:
6493 c2op_assemble(0,&regs[0]);break;
57871462 6494 case FCONV:
6495 fconv_assemble(0,&regs[0]);break;
6496 case FLOAT:
6497 float_assemble(0,&regs[0]);break;
6498 case FCOMP:
6499 fcomp_assemble(0,&regs[0]);break;
6500 case MULTDIV:
6501 multdiv_assemble(0,&regs[0]);break;
6502 case MOV:
6503 mov_assemble(0,&regs[0]);break;
6504 case SYSCALL:
7139f3c8 6505 case HLECALL:
1e973cb0 6506 case INTCALL:
57871462 6507 case SPAN:
6508 case UJUMP:
6509 case RJUMP:
6510 case CJUMP:
6511 case SJUMP:
6512 case FJUMP:
6513 printf("Jump in the delay slot. This is probably a bug.\n");
6514 }
6515 int btaddr=get_reg(regs[0].regmap,BTREG);
6516 if(btaddr<0) {
6517 btaddr=get_reg(regs[0].regmap,-1);
6518 emit_readword((int)&branch_target,btaddr);
6519 }
6520 assert(btaddr!=HOST_CCREG);
6521 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6522#ifdef HOST_IMM8
6523 emit_movimm(start+4,HOST_TEMPREG);
6524 emit_cmp(btaddr,HOST_TEMPREG);
6525#else
6526 emit_cmpimm(btaddr,start+4);
6527#endif
6528 int branch=(int)out;
6529 emit_jeq(0);
6530 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6531 emit_jmp(jump_vaddr_reg[btaddr]);
6532 set_jump_target(branch,(int)out);
6533 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6534 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6535}
6536
6537// Basic liveness analysis for MIPS registers
6538void unneeded_registers(int istart,int iend,int r)
6539{
6540 int i;
6541 uint64_t u,uu,b,bu;
6542 uint64_t temp_u,temp_uu;
6543 uint64_t tdep;
6544 if(iend==slen-1) {
6545 u=1;uu=1;
6546 }else{
6547 u=unneeded_reg[iend+1];
6548 uu=unneeded_reg_upper[iend+1];
6549 u=1;uu=1;
6550 }
6551 for (i=iend;i>=istart;i--)
6552 {
6553 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6554 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6555 {
6556 // If subroutine call, flag return address as a possible branch target
6557 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6558
6559 if(ba[i]<start || ba[i]>=(start+slen*4))
6560 {
6561 // Branch out of this block, flush all regs
6562 u=1;
6563 uu=1;
6564 /* Hexagon hack
6565 if(itype[i]==UJUMP&&rt1[i]==31)
6566 {
6567 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6568 }
6569 if(itype[i]==RJUMP&&rs1[i]==31)
6570 {
6571 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6572 }
4cb76aa4 6573 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6574 if(itype[i]==UJUMP&&rt1[i]==31)
6575 {
6576 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6577 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6578 }
6579 if(itype[i]==RJUMP&&rs1[i]==31)
6580 {
6581 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6582 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6583 }
6584 }*/
6585 branch_unneeded_reg[i]=u;
6586 branch_unneeded_reg_upper[i]=uu;
6587 // Merge in delay slot
6588 tdep=(~uu>>rt1[i+1])&1;
6589 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6590 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6591 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6592 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6593 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6594 u|=1;uu|=1;
6595 // If branch is "likely" (and conditional)
6596 // then we skip the delay slot on the fall-thru path
6597 if(likely[i]) {
6598 if(i<slen-1) {
6599 u&=unneeded_reg[i+2];
6600 uu&=unneeded_reg_upper[i+2];
6601 }
6602 else
6603 {
6604 u=1;
6605 uu=1;
6606 }
6607 }
6608 }
6609 else
6610 {
6611 // Internal branch, flag target
6612 bt[(ba[i]-start)>>2]=1;
6613 if(ba[i]<=start+i*4) {
6614 // Backward branch
6615 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6616 {
6617 // Unconditional branch
6618 temp_u=1;temp_uu=1;
6619 } else {
6620 // Conditional branch (not taken case)
6621 temp_u=unneeded_reg[i+2];
6622 temp_uu=unneeded_reg_upper[i+2];
6623 }
6624 // Merge in delay slot
6625 tdep=(~temp_uu>>rt1[i+1])&1;
6626 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6627 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6628 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6629 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6630 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6631 temp_u|=1;temp_uu|=1;
6632 // If branch is "likely" (and conditional)
6633 // then we skip the delay slot on the fall-thru path
6634 if(likely[i]) {
6635 if(i<slen-1) {
6636 temp_u&=unneeded_reg[i+2];
6637 temp_uu&=unneeded_reg_upper[i+2];
6638 }
6639 else
6640 {
6641 temp_u=1;
6642 temp_uu=1;
6643 }
6644 }
6645 tdep=(~temp_uu>>rt1[i])&1;
6646 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6647 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6648 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6649 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6650 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6651 temp_u|=1;temp_uu|=1;
6652 unneeded_reg[i]=temp_u;
6653 unneeded_reg_upper[i]=temp_uu;
6654 // Only go three levels deep. This recursion can take an
6655 // excessive amount of time if there are a lot of nested loops.
6656 if(r<2) {
6657 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6658 }else{
6659 unneeded_reg[(ba[i]-start)>>2]=1;
6660 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6661 }
6662 } /*else*/ if(1) {
6663 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6664 {
6665 // Unconditional branch
6666 u=unneeded_reg[(ba[i]-start)>>2];
6667 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6668 branch_unneeded_reg[i]=u;
6669 branch_unneeded_reg_upper[i]=uu;
6670 //u=1;
6671 //uu=1;
6672 //branch_unneeded_reg[i]=u;
6673 //branch_unneeded_reg_upper[i]=uu;
6674 // Merge in delay slot
6675 tdep=(~uu>>rt1[i+1])&1;
6676 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6677 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6678 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6679 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6680 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6681 u|=1;uu|=1;
6682 } else {
6683 // Conditional branch
6684 b=unneeded_reg[(ba[i]-start)>>2];
6685 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6686 branch_unneeded_reg[i]=b;
6687 branch_unneeded_reg_upper[i]=bu;
6688 //b=1;
6689 //bu=1;
6690 //branch_unneeded_reg[i]=b;
6691 //branch_unneeded_reg_upper[i]=bu;
6692 // Branch delay slot
6693 tdep=(~uu>>rt1[i+1])&1;
6694 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6695 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6696 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6697 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6698 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6699 b|=1;bu|=1;
6700 // If branch is "likely" then we skip the
6701 // delay slot on the fall-thru path
6702 if(likely[i]) {
6703 u=b;
6704 uu=bu;
6705 if(i<slen-1) {
6706 u&=unneeded_reg[i+2];
6707 uu&=unneeded_reg_upper[i+2];
6708 //u=1;
6709 //uu=1;
6710 }
6711 } else {
6712 u&=b;
6713 uu&=bu;
6714 //u=1;
6715 //uu=1;
6716 }
6717 if(i<slen-1) {
6718 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6719 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6720 //branch_unneeded_reg[i]=1;
6721 //branch_unneeded_reg_upper[i]=1;
6722 } else {
6723 branch_unneeded_reg[i]=1;
6724 branch_unneeded_reg_upper[i]=1;
6725 }
6726 }
6727 }
6728 }
6729 }
1e973cb0 6730 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6731 {
6732 // SYSCALL instruction (software interrupt)
6733 u=1;
6734 uu=1;
6735 }
6736 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6737 {
6738 // ERET instruction (return from interrupt)
6739 u=1;
6740 uu=1;
6741 }
6742 //u=uu=1; // DEBUG
6743 tdep=(~uu>>rt1[i])&1;
6744 // Written registers are unneeded
6745 u|=1LL<<rt1[i];
6746 u|=1LL<<rt2[i];
6747 uu|=1LL<<rt1[i];
6748 uu|=1LL<<rt2[i];
6749 // Accessed registers are needed
6750 u&=~(1LL<<rs1[i]);
6751 u&=~(1LL<<rs2[i]);
6752 uu&=~(1LL<<us1[i]);
6753 uu&=~(1LL<<us2[i]);
6754 // Source-target dependencies
6755 uu&=~(tdep<<dep1[i]);
6756 uu&=~(tdep<<dep2[i]);
6757 // R0 is always unneeded
6758 u|=1;uu|=1;
6759 // Save it
6760 unneeded_reg[i]=u;
6761 unneeded_reg_upper[i]=uu;
6762 /*
6763 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6764 printf("U:");
6765 int r;
6766 for(r=1;r<=CCREG;r++) {
6767 if((unneeded_reg[i]>>r)&1) {
6768 if(r==HIREG) printf(" HI");
6769 else if(r==LOREG) printf(" LO");
6770 else printf(" r%d",r);
6771 }
6772 }
6773 printf(" UU:");
6774 for(r=1;r<=CCREG;r++) {
6775 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6776 if(r==HIREG) printf(" HI");
6777 else if(r==LOREG) printf(" LO");
6778 else printf(" r%d",r);
6779 }
6780 }
6781 printf("\n");*/
6782 }
252c20fc 6783#ifdef FORCE32
6784 for (i=iend;i>=istart;i--)
6785 {
6786 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6787 }
6788#endif
57871462 6789}
6790
6791// Identify registers which are likely to contain 32-bit values
6792// This is used to predict whether any branches will jump to a
6793// location with 64-bit values in registers.
6794static void provisional_32bit()
6795{
6796 int i,j;
6797 uint64_t is32=1;
6798 uint64_t lastbranch=1;
6799
6800 for(i=0;i<slen;i++)
6801 {
6802 if(i>0) {
6803 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6804 if(i>1) is32=lastbranch;
6805 else is32=1;
6806 }
6807 }
6808 if(i>1)
6809 {
6810 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6811 if(likely[i-2]) {
6812 if(i>2) is32=lastbranch;
6813 else is32=1;
6814 }
6815 }
6816 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6817 {
6818 if(rs1[i-2]==0||rs2[i-2]==0)
6819 {
6820 if(rs1[i-2]) {
6821 is32|=1LL<<rs1[i-2];
6822 }
6823 if(rs2[i-2]) {
6824 is32|=1LL<<rs2[i-2];
6825 }
6826 }
6827 }
6828 }
6829 // If something jumps here with 64-bit values
6830 // then promote those registers to 64 bits
6831 if(bt[i])
6832 {
6833 uint64_t temp_is32=is32;
6834 for(j=i-1;j>=0;j--)
6835 {
6836 if(ba[j]==start+i*4)
6837 //temp_is32&=branch_regs[j].is32;
6838 temp_is32&=p32[j];
6839 }
6840 for(j=i;j<slen;j++)
6841 {
6842 if(ba[j]==start+i*4)
6843 temp_is32=1;
6844 }
6845 is32=temp_is32;
6846 }
6847 int type=itype[i];
6848 int op=opcode[i];
6849 int op2=opcode2[i];
6850 int rt=rt1[i];
6851 int s1=rs1[i];
6852 int s2=rs2[i];
6853 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6854 // Branches don't write registers, consider the delay slot instead.
6855 type=itype[i+1];
6856 op=opcode[i+1];
6857 op2=opcode2[i+1];
6858 rt=rt1[i+1];
6859 s1=rs1[i+1];
6860 s2=rs2[i+1];
6861 lastbranch=is32;
6862 }
6863 switch(type) {
6864 case LOAD:
6865 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6866 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6867 is32&=~(1LL<<rt);
6868 else
6869 is32|=1LL<<rt;
6870 break;
6871 case STORE:
6872 case STORELR:
6873 break;
6874 case LOADLR:
6875 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6876 if(op==0x22) is32|=1LL<<rt; // LWL
6877 break;
6878 case IMM16:
6879 if (op==0x08||op==0x09|| // ADDI/ADDIU
6880 op==0x0a||op==0x0b|| // SLTI/SLTIU
6881 op==0x0c|| // ANDI
6882 op==0x0f) // LUI
6883 {
6884 is32|=1LL<<rt;
6885 }
6886 if(op==0x18||op==0x19) { // DADDI/DADDIU
6887 is32&=~(1LL<<rt);
6888 //if(imm[i]==0)
6889 // is32|=((is32>>s1)&1LL)<<rt;
6890 }
6891 if(op==0x0d||op==0x0e) { // ORI/XORI
6892 uint64_t sr=((is32>>s1)&1LL);
6893 is32&=~(1LL<<rt);
6894 is32|=sr<<rt;
6895 }
6896 break;
6897 case UJUMP:
6898 break;
6899 case RJUMP:
6900 break;
6901 case CJUMP:
6902 break;
6903 case SJUMP:
6904 break;
6905 case FJUMP:
6906 break;
6907 case ALU:
6908 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6909 is32|=1LL<<rt;
6910 }
6911 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6912 is32|=1LL<<rt;
6913 }
6914 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6915 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6916 is32&=~(1LL<<rt);
6917 is32|=sr<<rt;
6918 }
6919 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6920 if(s1==0&&s2==0) {
6921 is32|=1LL<<rt;
6922 }
6923 else if(s2==0) {
6924 uint64_t sr=((is32>>s1)&1LL);
6925 is32&=~(1LL<<rt);
6926 is32|=sr<<rt;
6927 }
6928 else if(s1==0) {
6929 uint64_t sr=((is32>>s2)&1LL);
6930 is32&=~(1LL<<rt);
6931 is32|=sr<<rt;
6932 }
6933 else {
6934 is32&=~(1LL<<rt);
6935 }
6936 }
6937 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6938 if(s1==0&&s2==0) {
6939 is32|=1LL<<rt;
6940 }
6941 else if(s2==0) {
6942 uint64_t sr=((is32>>s1)&1LL);
6943 is32&=~(1LL<<rt);
6944 is32|=sr<<rt;
6945 }
6946 else {
6947 is32&=~(1LL<<rt);
6948 }
6949 }
6950 break;
6951 case MULTDIV:
6952 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6953 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6954 }
6955 else {
6956 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6957 }
6958 break;
6959 case MOV:
6960 {
6961 uint64_t sr=((is32>>s1)&1LL);
6962 is32&=~(1LL<<rt);
6963 is32|=sr<<rt;
6964 }
6965 break;
6966 case SHIFT:
6967 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6968 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6969 break;
6970 case SHIFTIMM:
6971 is32|=1LL<<rt;
6972 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6973 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6974 break;
6975 case COP0:
6976 if(op2==0) is32|=1LL<<rt; // MFC0
6977 break;
6978 case COP1:
b9b61529 6979 case COP2:
57871462 6980 if(op2==0) is32|=1LL<<rt; // MFC1
6981 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6982 if(op2==2) is32|=1LL<<rt; // CFC1
6983 break;
6984 case C1LS:
b9b61529 6985 case C2LS:
57871462 6986 break;
6987 case FLOAT:
6988 case FCONV:
6989 break;
6990 case FCOMP:
6991 break;
b9b61529 6992 case C2OP:
57871462 6993 case SYSCALL:
7139f3c8 6994 case HLECALL:
57871462 6995 break;
6996 default:
6997 break;
6998 }
6999 is32|=1;
7000 p32[i]=is32;
7001
7002 if(i>0)
7003 {
7004 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7005 {
7006 if(rt1[i-1]==31) // JAL/JALR
7007 {
7008 // Subroutine call will return here, don't alloc any registers
7009 is32=1;
7010 }
7011 else if(i+1<slen)
7012 {
7013 // Internal branch will jump here, match registers to caller
7014 is32=0x3FFFFFFFFLL;
7015 }
7016 }
7017 }
7018 }
7019}
7020
7021// Identify registers which may be assumed to contain 32-bit values
7022// and where optimizations will rely on this.
7023// This is used to determine whether backward branches can safely
7024// jump to a location with 64-bit values in registers.
7025static void provisional_r32()
7026{
7027 u_int r32=0;
7028 int i;
7029
7030 for (i=slen-1;i>=0;i--)
7031 {
7032 int hr;
7033 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7034 {
7035 if(ba[i]<start || ba[i]>=(start+slen*4))
7036 {
7037 // Branch out of this block, don't need anything
7038 r32=0;
7039 }
7040 else
7041 {
7042 // Internal branch
7043 // Need whatever matches the target
7044 // (and doesn't get overwritten by the delay slot instruction)
7045 r32=0;
7046 int t=(ba[i]-start)>>2;
7047 if(ba[i]>start+i*4) {
7048 // Forward branch
7049 //if(!(requires_32bit[t]&~regs[i].was32))
7050 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7051 if(!(pr32[t]&~regs[i].was32))
7052 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7053 }else{
7054 // Backward branch
7055 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7056 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7057 }
7058 }
7059 // Conditional branch may need registers for following instructions
7060 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7061 {
7062 if(i<slen-2) {
7063 //r32|=requires_32bit[i+2];
7064 r32|=pr32[i+2];
7065 r32&=regs[i].was32;
7066 // Mark this address as a branch target since it may be called
7067 // upon return from interrupt
7068 //bt[i+2]=1;
7069 }
7070 }
7071 // Merge in delay slot
7072 if(!likely[i]) {
7073 // These are overwritten unless the branch is "likely"
7074 // and the delay slot is nullified if not taken
7075 r32&=~(1LL<<rt1[i+1]);
7076 r32&=~(1LL<<rt2[i+1]);
7077 }
7078 // Assume these are needed (delay slot)
7079 if(us1[i+1]>0)
7080 {
7081 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7082 }
7083 if(us2[i+1]>0)
7084 {
7085 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7086 }
7087 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7088 {
7089 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7090 }
7091 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7092 {
7093 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7094 }
7095 }
1e973cb0 7096 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7097 {
7098 // SYSCALL instruction (software interrupt)
7099 r32=0;
7100 }
7101 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7102 {
7103 // ERET instruction (return from interrupt)
7104 r32=0;
7105 }
7106 // Check 32 bits
7107 r32&=~(1LL<<rt1[i]);
7108 r32&=~(1LL<<rt2[i]);
7109 if(us1[i]>0)
7110 {
7111 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7112 }
7113 if(us2[i]>0)
7114 {
7115 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7116 }
7117 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7118 {
7119 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7120 }
7121 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7122 {
7123 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7124 }
7125 //requires_32bit[i]=r32;
7126 pr32[i]=r32;
7127
7128 // Dirty registers which are 32-bit, require 32-bit input
7129 // as they will be written as 32-bit values
7130 for(hr=0;hr<HOST_REGS;hr++)
7131 {
7132 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7133 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7134 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7135 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7136 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7137 }
7138 }
7139 }
7140 }
7141}
7142
7143// Write back dirty registers as soon as we will no longer modify them,
7144// so that we don't end up with lots of writes at the branches.
7145void clean_registers(int istart,int iend,int wr)
7146{
7147 int i;
7148 int r;
7149 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7150 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7151 if(iend==slen-1) {
7152 will_dirty_i=will_dirty_next=0;
7153 wont_dirty_i=wont_dirty_next=0;
7154 }else{
7155 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7156 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7157 }
7158 for (i=iend;i>=istart;i--)
7159 {
7160 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7161 {
7162 if(ba[i]<start || ba[i]>=(start+slen*4))
7163 {
7164 // Branch out of this block, flush all regs
7165 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7166 {
7167 // Unconditional branch
7168 will_dirty_i=0;
7169 wont_dirty_i=0;
7170 // Merge in delay slot (will dirty)
7171 for(r=0;r<HOST_REGS;r++) {
7172 if(r!=EXCLUDE_REG) {
7173 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7174 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7175 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7176 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7177 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7178 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7179 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7180 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7181 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7182 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7183 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7184 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7185 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7186 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7187 }
7188 }
7189 }
7190 else
7191 {
7192 // Conditional branch
7193 will_dirty_i=0;
7194 wont_dirty_i=wont_dirty_next;
7195 // Merge in delay slot (will dirty)
7196 for(r=0;r<HOST_REGS;r++) {
7197 if(r!=EXCLUDE_REG) {
7198 if(!likely[i]) {
7199 // Might not dirty if likely branch is not taken
7200 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7201 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7202 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7203 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7204 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7205 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7206 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7207 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7208 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7209 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7210 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7211 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7212 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7213 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7214 }
7215 }
7216 }
7217 }
7218 // Merge in delay slot (wont dirty)
7219 for(r=0;r<HOST_REGS;r++) {
7220 if(r!=EXCLUDE_REG) {
7221 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7222 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7223 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7224 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7225 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7226 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7227 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7228 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7229 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7230 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7231 }
7232 }
7233 if(wr) {
7234 #ifndef DESTRUCTIVE_WRITEBACK
7235 branch_regs[i].dirty&=wont_dirty_i;
7236 #endif
7237 branch_regs[i].dirty|=will_dirty_i;
7238 }
7239 }
7240 else
7241 {
7242 // Internal branch
7243 if(ba[i]<=start+i*4) {
7244 // Backward branch
7245 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7246 {
7247 // Unconditional branch
7248 temp_will_dirty=0;
7249 temp_wont_dirty=0;
7250 // Merge in delay slot (will dirty)
7251 for(r=0;r<HOST_REGS;r++) {
7252 if(r!=EXCLUDE_REG) {
7253 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7254 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7255 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7256 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7257 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7258 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7259 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7260 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7261 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7262 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7263 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7264 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7265 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7266 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7267 }
7268 }
7269 } else {
7270 // Conditional branch (not taken case)
7271 temp_will_dirty=will_dirty_next;
7272 temp_wont_dirty=wont_dirty_next;
7273 // Merge in delay slot (will dirty)
7274 for(r=0;r<HOST_REGS;r++) {
7275 if(r!=EXCLUDE_REG) {
7276 if(!likely[i]) {
7277 // Will not dirty if likely branch is not taken
7278 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7279 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7280 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7281 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7282 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7283 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7284 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7285 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7286 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7287 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7288 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7289 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7290 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7291 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7292 }
7293 }
7294 }
7295 }
7296 // Merge in delay slot (wont dirty)
7297 for(r=0;r<HOST_REGS;r++) {
7298 if(r!=EXCLUDE_REG) {
7299 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7300 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7301 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7302 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7303 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7304 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7307 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7308 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7309 }
7310 }
7311 // Deal with changed mappings
7312 if(i<iend) {
7313 for(r=0;r<HOST_REGS;r++) {
7314 if(r!=EXCLUDE_REG) {
7315 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7316 temp_will_dirty&=~(1<<r);
7317 temp_wont_dirty&=~(1<<r);
7318 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7319 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7320 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7321 } else {
7322 temp_will_dirty|=1<<r;
7323 temp_wont_dirty|=1<<r;
7324 }
7325 }
7326 }
7327 }
7328 }
7329 if(wr) {
7330 will_dirty[i]=temp_will_dirty;
7331 wont_dirty[i]=temp_wont_dirty;
7332 clean_registers((ba[i]-start)>>2,i-1,0);
7333 }else{
7334 // Limit recursion. It can take an excessive amount
7335 // of time if there are a lot of nested loops.
7336 will_dirty[(ba[i]-start)>>2]=0;
7337 wont_dirty[(ba[i]-start)>>2]=-1;
7338 }
7339 }
7340 /*else*/ if(1)
7341 {
7342 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7343 {
7344 // Unconditional branch
7345 will_dirty_i=0;
7346 wont_dirty_i=0;
7347 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7348 for(r=0;r<HOST_REGS;r++) {
7349 if(r!=EXCLUDE_REG) {
7350 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7351 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7352 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7353 }
7354 }
7355 }
7356 //}
7357 // Merge in delay slot
7358 for(r=0;r<HOST_REGS;r++) {
7359 if(r!=EXCLUDE_REG) {
7360 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7361 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7362 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7363 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7364 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7365 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7366 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7367 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7368 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7369 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7370 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7371 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7372 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7373 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7374 }
7375 }
7376 } else {
7377 // Conditional branch
7378 will_dirty_i=will_dirty_next;
7379 wont_dirty_i=wont_dirty_next;
7380 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7381 for(r=0;r<HOST_REGS;r++) {
7382 if(r!=EXCLUDE_REG) {
7383 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7384 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7385 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7386 }
7387 else
7388 {
7389 will_dirty_i&=~(1<<r);
7390 }
7391 // Treat delay slot as part of branch too
7392 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7393 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7394 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7395 }
7396 else
7397 {
7398 will_dirty[i+1]&=~(1<<r);
7399 }*/
7400 }
7401 }
7402 //}
7403 // Merge in delay slot
7404 for(r=0;r<HOST_REGS;r++) {
7405 if(r!=EXCLUDE_REG) {
7406 if(!likely[i]) {
7407 // Might not dirty if likely branch is not taken
7408 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7409 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7410 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7411 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7412 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7413 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7414 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7415 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7416 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7417 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7420 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7421 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7422 }
7423 }
7424 }
7425 }
7426 // Merge in delay slot
7427 for(r=0;r<HOST_REGS;r++) {
7428 if(r!=EXCLUDE_REG) {
7429 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7430 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7431 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7433 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7434 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7435 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7436 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7437 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7438 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7439 }
7440 }
7441 if(wr) {
7442 #ifndef DESTRUCTIVE_WRITEBACK
7443 branch_regs[i].dirty&=wont_dirty_i;
7444 #endif
7445 branch_regs[i].dirty|=will_dirty_i;
7446 }
7447 }
7448 }
7449 }
1e973cb0 7450 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7451 {
7452 // SYSCALL instruction (software interrupt)
7453 will_dirty_i=0;
7454 wont_dirty_i=0;
7455 }
7456 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7457 {
7458 // ERET instruction (return from interrupt)
7459 will_dirty_i=0;
7460 wont_dirty_i=0;
7461 }
7462 will_dirty_next=will_dirty_i;
7463 wont_dirty_next=wont_dirty_i;
7464 for(r=0;r<HOST_REGS;r++) {
7465 if(r!=EXCLUDE_REG) {
7466 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7469 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7471 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7473 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7474 if(i>istart) {
7475 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7476 {
7477 // Don't store a register immediately after writing it,
7478 // may prevent dual-issue.
7479 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7480 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7481 }
7482 }
7483 }
7484 }
7485 // Save it
7486 will_dirty[i]=will_dirty_i;
7487 wont_dirty[i]=wont_dirty_i;
7488 // Mark registers that won't be dirtied as not dirty
7489 if(wr) {
7490 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7491 for(r=0;r<HOST_REGS;r++) {
7492 if((will_dirty_i>>r)&1) {
7493 printf(" r%d",r);
7494 }
7495 }
7496 printf("\n");*/
7497
7498 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7499 regs[i].dirty|=will_dirty_i;
7500 #ifndef DESTRUCTIVE_WRITEBACK
7501 regs[i].dirty&=wont_dirty_i;
7502 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7503 {
7504 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7505 for(r=0;r<HOST_REGS;r++) {
7506 if(r!=EXCLUDE_REG) {
7507 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7508 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7509 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7510 }
7511 }
7512 }
7513 }
7514 else
7515 {
7516 if(i<iend) {
7517 for(r=0;r<HOST_REGS;r++) {
7518 if(r!=EXCLUDE_REG) {
7519 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7520 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7521 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7522 }
7523 }
7524 }
7525 }
7526 #endif
7527 //}
7528 }
7529 // Deal with changed mappings
7530 temp_will_dirty=will_dirty_i;
7531 temp_wont_dirty=wont_dirty_i;
7532 for(r=0;r<HOST_REGS;r++) {
7533 if(r!=EXCLUDE_REG) {
7534 int nr;
7535 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7536 if(wr) {
7537 #ifndef DESTRUCTIVE_WRITEBACK
7538 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7539 #endif
7540 regs[i].wasdirty|=will_dirty_i&(1<<r);
7541 }
7542 }
7543 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7544 // Register moved to a different register
7545 will_dirty_i&=~(1<<r);
7546 wont_dirty_i&=~(1<<r);
7547 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7548 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7549 if(wr) {
7550 #ifndef DESTRUCTIVE_WRITEBACK
7551 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7552 #endif
7553 regs[i].wasdirty|=will_dirty_i&(1<<r);
7554 }
7555 }
7556 else {
7557 will_dirty_i&=~(1<<r);
7558 wont_dirty_i&=~(1<<r);
7559 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7560 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7561 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7562 } else {
7563 wont_dirty_i|=1<<r;
7564 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7565 }
7566 }
7567 }
7568 }
7569 }
7570}
7571
7572 /* disassembly */
7573void disassemble_inst(int i)
7574{
7575 if (bt[i]) printf("*"); else printf(" ");
7576 switch(itype[i]) {
7577 case UJUMP:
7578 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7579 case CJUMP:
7580 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7581 case SJUMP:
7582 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7583 case FJUMP:
7584 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7585 case RJUMP:
74426039 7586 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7587 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7588 else
7589 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7590 break;
57871462 7591 case SPAN:
7592 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7593 case IMM16:
7594 if(opcode[i]==0xf) //LUI
7595 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7596 else
7597 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7598 break;
7599 case LOAD:
7600 case LOADLR:
7601 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7602 break;
7603 case STORE:
7604 case STORELR:
7605 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7606 break;
7607 case ALU:
7608 case SHIFT:
7609 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7610 break;
7611 case MULTDIV:
7612 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7613 break;
7614 case SHIFTIMM:
7615 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7616 break;
7617 case MOV:
7618 if((opcode2[i]&0x1d)==0x10)
7619 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7620 else if((opcode2[i]&0x1d)==0x11)
7621 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7622 else
7623 printf (" %x: %s\n",start+i*4,insn[i]);
7624 break;
7625 case COP0:
7626 if(opcode2[i]==0)
7627 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7628 else if(opcode2[i]==4)
7629 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7630 else printf (" %x: %s\n",start+i*4,insn[i]);
7631 break;
7632 case COP1:
7633 if(opcode2[i]<3)
7634 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7635 else if(opcode2[i]>3)
7636 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7637 else printf (" %x: %s\n",start+i*4,insn[i]);
7638 break;
b9b61529 7639 case COP2:
7640 if(opcode2[i]<3)
7641 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7642 else if(opcode2[i]>3)
7643 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7644 else printf (" %x: %s\n",start+i*4,insn[i]);
7645 break;
57871462 7646 case C1LS:
7647 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7648 break;
b9b61529 7649 case C2LS:
7650 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7651 break;
1e973cb0 7652 case INTCALL:
7653 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7654 break;
57871462 7655 default:
7656 //printf (" %s %8x\n",insn[i],source[i]);
7657 printf (" %x: %s\n",start+i*4,insn[i]);
7658 }
7659}
7660
7661void new_dynarec_init()
7662{
7663 printf("Init new dynarec\n");
7664 out=(u_char *)BASE_ADDR;
7665 if (mmap (out, 1<<TARGET_SIZE_2,
7666 PROT_READ | PROT_WRITE | PROT_EXEC,
7667 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7668 -1, 0) <= 0) {printf("mmap() failed\n");}
3d624f89 7669#ifdef MUPEN64
57871462 7670 rdword=&readmem_dword;
7671 fake_pc.f.r.rs=&readmem_dword;
7672 fake_pc.f.r.rt=&readmem_dword;
7673 fake_pc.f.r.rd=&readmem_dword;
3d624f89 7674#endif
57871462 7675 int n;
7676 for(n=0x80000;n<0x80800;n++)
7677 invalid_code[n]=1;
7678 for(n=0;n<65536;n++)
7679 hash_table[n][0]=hash_table[n][2]=-1;
7680 memset(mini_ht,-1,sizeof(mini_ht));
7681 memset(restore_candidate,0,sizeof(restore_candidate));
7682 copy=shadow;
7683 expirep=16384; // Expiry pointer, +2 blocks
7684 pending_exception=0;
7685 literalcount=0;
7686#ifdef HOST_IMM8
7687 // Copy this into local area so we don't have to put it in every literal pool
7688 invc_ptr=invalid_code;
7689#endif
7690 stop_after_jal=0;
7691 // TLB
7692 using_tlb=0;
7693 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7694 memory_map[n]=-1;
7695 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7696 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7697 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7698 memory_map[n]=-1;
24385cae 7699#ifdef MUPEN64
57871462 7700 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7701 writemem[n] = write_nomem_new;
7702 writememb[n] = write_nomemb_new;
7703 writememh[n] = write_nomemh_new;
24385cae 7704#ifndef FORCE32
57871462 7705 writememd[n] = write_nomemd_new;
24385cae 7706#endif
57871462 7707 readmem[n] = read_nomem_new;
7708 readmemb[n] = read_nomemb_new;
7709 readmemh[n] = read_nomemh_new;
24385cae 7710#ifndef FORCE32
57871462 7711 readmemd[n] = read_nomemd_new;
24385cae 7712#endif
57871462 7713 }
7714 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7715 writemem[n] = write_rdram_new;
7716 writememb[n] = write_rdramb_new;
7717 writememh[n] = write_rdramh_new;
24385cae 7718#ifndef FORCE32
57871462 7719 writememd[n] = write_rdramd_new;
24385cae 7720#endif
57871462 7721 }
7722 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7723 writemem[n] = write_nomem_new;
7724 writememb[n] = write_nomemb_new;
7725 writememh[n] = write_nomemh_new;
24385cae 7726#ifndef FORCE32
57871462 7727 writememd[n] = write_nomemd_new;
24385cae 7728#endif
57871462 7729 readmem[n] = read_nomem_new;
7730 readmemb[n] = read_nomemb_new;
7731 readmemh[n] = read_nomemh_new;
24385cae 7732#ifndef FORCE32
57871462 7733 readmemd[n] = read_nomemd_new;
24385cae 7734#endif
57871462 7735 }
24385cae 7736#endif
57871462 7737 tlb_hacks();
7738 arch_init();
7739}
7740
7741void new_dynarec_cleanup()
7742{
7743 int n;
7744 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7745 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7746 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7747 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7748 #ifdef ROM_COPY
7749 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7750 #endif
7751}
7752
7753int new_recompile_block(int addr)
7754{
7755/*
7756 if(addr==0x800cd050) {
7757 int block;
7758 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7759 int n;
7760 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7761 }
7762*/
7763 //if(Count==365117028) tracedebug=1;
7764 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7765 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7766 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7767 //if(debug)
7768 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7769 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7770 /*if(Count>=312978186) {
7771 rlist();
7772 }*/
7773 //rlist();
7774 start = (u_int)addr&~3;
7775 //assert(((u_int)addr&1)==0);
7139f3c8 7776#ifdef PCSX
9ad4d757 7777 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7778 {
7139f3c8 7779 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7780 u_int beginning=(u_int)out;
7139f3c8 7781 u_int page=get_page(start);
7139f3c8 7782 invalid_code[start>>12]=0;
7783 emit_movimm(start,0);
7784 emit_writeword(0,(int)&pcaddr);
bb5285ef 7785 emit_jmp((int)new_dyna_leave);
7786#ifdef __arm__
7787 __clear_cache((void *)beginning,out);
7788#endif
9ad4d757 7789 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7790 return 0;
7791 }
560e4a12 7792 else if ((u_int)addr < 0x00200000 ||
7793 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7794 // used for BIOS calls mostly?
560e4a12 7795 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7796 pagelimit = (addr&0xa0000000)|0x00200000;
7797 }
7798 else if (!Config.HLE && (
7799/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7800 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7801 // BIOS
7802 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7803 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7804 }
7805 else
7806#endif
3d624f89 7807#ifdef MUPEN64
57871462 7808 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7809 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7810 pagelimit = 0xa4001000;
7811 }
3d624f89 7812 else
7813#endif
4cb76aa4 7814 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7815 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7816 pagelimit = 0x80000000+RAM_SIZE;
57871462 7817 }
90ae6d4e 7818#ifndef DISABLE_TLB
57871462 7819 else if ((signed int)addr >= (signed int)0xC0000000) {
7820 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7821 //if(tlb_LUT_r[start>>12])
7822 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7823 if((signed int)memory_map[start>>12]>=0) {
7824 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7825 pagelimit=(start+4096)&0xFFFFF000;
7826 int map=memory_map[start>>12];
7827 int i;
7828 for(i=0;i<5;i++) {
7829 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7830 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7831 }
7832 assem_debug("pagelimit=%x\n",pagelimit);
7833 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7834 }
7835 else {
7836 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7837 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7838 return -1; // Caller will invoke exception handler
57871462 7839 }
7840 //printf("source= %x\n",(int)source);
7841 }
90ae6d4e 7842#endif
57871462 7843 else {
7844 printf("Compile at bogus memory address: %x \n", (int)addr);
7845 exit(1);
7846 }
7847
7848 /* Pass 1: disassemble */
7849 /* Pass 2: register dependencies, branch targets */
7850 /* Pass 3: register allocation */
7851 /* Pass 4: branch dependencies */
7852 /* Pass 5: pre-alloc */
7853 /* Pass 6: optimize clean/dirty state */
7854 /* Pass 7: flag 32-bit registers */
7855 /* Pass 8: assembly */
7856 /* Pass 9: linker */
7857 /* Pass 10: garbage collection / free memory */
7858
7859 int i,j;
7860 int done=0;
7861 unsigned int type,op,op2;
7862
7863 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7864
7865 /* Pass 1 disassembly */
7866
7867 for(i=0;!done;i++) {
7868 bt[i]=0;likely[i]=0;op2=0;
7869 opcode[i]=op=source[i]>>26;
7870 switch(op)
7871 {
7872 case 0x00: strcpy(insn[i],"special"); type=NI;
7873 op2=source[i]&0x3f;
7874 switch(op2)
7875 {
7876 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7877 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7878 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7879 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7880 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7881 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7882 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7883 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7884 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7885 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7886 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7887 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7888 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7889 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7890 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7891 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7892 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7893 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7894 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7895 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7896 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7897 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7898 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7899 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7900 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7901 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7902 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7903 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7904 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7905 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7906 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7907 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7908 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7909 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7910 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7911 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7912 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7913 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7914 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7915 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7916 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7917 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7918 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7919 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7920 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7921 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7922 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7923 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7924 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7925 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7926 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7927 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7928 }
7929 break;
7930 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7931 op2=(source[i]>>16)&0x1f;
7932 switch(op2)
7933 {
7934 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7935 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7936 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7937 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7938 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7939 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7940 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7941 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7942 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7943 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7944 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7945 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7946 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7947 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7948 }
7949 break;
7950 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7951 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7952 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7953 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7954 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7955 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7956 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7957 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7958 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7959 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7960 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7961 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7962 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7963 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7964 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7965 op2=(source[i]>>21)&0x1f;
7966 switch(op2)
7967 {
7968 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7969 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7970 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7971 switch(source[i]&0x3f)
7972 {
7973 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7974 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7975 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7976 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 7977#ifdef PCSX
7978 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7979#else
57871462 7980 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 7981#endif
57871462 7982 }
7983 }
7984 break;
7985 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7986 op2=(source[i]>>21)&0x1f;
7987 switch(op2)
7988 {
7989 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7990 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7991 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7992 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7993 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7994 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7995 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7996 switch((source[i]>>16)&0x3)
7997 {
7998 case 0x00: strcpy(insn[i],"BC1F"); break;
7999 case 0x01: strcpy(insn[i],"BC1T"); break;
8000 case 0x02: strcpy(insn[i],"BC1FL"); break;
8001 case 0x03: strcpy(insn[i],"BC1TL"); break;
8002 }
8003 break;
8004 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8005 switch(source[i]&0x3f)
8006 {
8007 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8008 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8009 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8010 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8011 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8012 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8013 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8014 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8015 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8016 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8017 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8018 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8019 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8020 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8021 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8022 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8023 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8024 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8025 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8026 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8027 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8028 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8029 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8030 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8031 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8032 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8033 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8034 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8035 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8036 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8037 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8038 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8039 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8040 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8041 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8042 }
8043 break;
8044 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8045 switch(source[i]&0x3f)
8046 {
8047 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8048 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8049 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8050 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8051 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8052 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8053 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8054 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8055 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8056 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8057 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8058 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8059 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8060 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8061 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8062 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8063 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8064 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8065 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8066 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8067 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8068 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8069 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8070 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8071 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8072 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8073 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8074 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8075 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8076 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8077 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8078 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8079 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8080 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8081 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8082 }
8083 break;
8084 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8085 switch(source[i]&0x3f)
8086 {
8087 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8088 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8089 }
8090 break;
8091 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8092 switch(source[i]&0x3f)
8093 {
8094 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8095 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8096 }
8097 break;
8098 }
8099 break;
909168d6 8100#ifndef FORCE32
57871462 8101 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8102 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8103 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8104 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8105 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8106 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8107 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8108 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8109#endif
57871462 8110 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8111 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8112 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8113 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8114 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8115 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8116 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8117 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8118 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8119 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8120 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8121 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8122#ifndef FORCE32
57871462 8123 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8124 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8125#endif
57871462 8126 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8127 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8128 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8129 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8130#ifndef FORCE32
57871462 8131 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8132 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8133 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8134#endif
57871462 8135 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8136 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8137#ifndef FORCE32
57871462 8138 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8139 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8140 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8141#endif
b9b61529 8142#ifdef PCSX
8143 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8144 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8145 op2=(source[i]>>21)&0x1f;
c7abc864 8146 if (source[i]&0x3f) {
8147 if (gte_handlers[source[i]&0x3f]!=NULL) {
8148 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8149 type=C2OP;
8150 }
8151 }
8152 else switch(op2)
b9b61529 8153 {
8154 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8155 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8156 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8157 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8158 }
8159 break;
8160 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8161 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8162 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8163#endif
90ae6d4e 8164 default: strcpy(insn[i],"???"); type=NI;
75dec299 8165 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8166 break;
57871462 8167 }
1e973cb0 8168#ifdef PCSX
8169 /* detect branch in delay slot early */
8170 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8171 opcode[i+1]=source[i+1]>>26;
8172 opcode2[i+1]=source[i+1]&0x3f;
8173 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8174 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8175 // don't handle first branch and call interpreter if it's hit
8176 type=INTCALL;
8177 }
8178 }
8179#endif
57871462 8180 itype[i]=type;
8181 opcode2[i]=op2;
8182 /* Get registers/immediates */
8183 lt1[i]=0;
8184 us1[i]=0;
8185 us2[i]=0;
8186 dep1[i]=0;
8187 dep2[i]=0;
8188 switch(type) {
8189 case LOAD:
8190 rs1[i]=(source[i]>>21)&0x1f;
8191 rs2[i]=0;
8192 rt1[i]=(source[i]>>16)&0x1f;
8193 rt2[i]=0;
8194 imm[i]=(short)source[i];
8195 break;
8196 case STORE:
8197 case STORELR:
8198 rs1[i]=(source[i]>>21)&0x1f;
8199 rs2[i]=(source[i]>>16)&0x1f;
8200 rt1[i]=0;
8201 rt2[i]=0;
8202 imm[i]=(short)source[i];
8203 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8204 break;
8205 case LOADLR:
8206 // LWL/LWR only load part of the register,
8207 // therefore the target register must be treated as a source too
8208 rs1[i]=(source[i]>>21)&0x1f;
8209 rs2[i]=(source[i]>>16)&0x1f;
8210 rt1[i]=(source[i]>>16)&0x1f;
8211 rt2[i]=0;
8212 imm[i]=(short)source[i];
8213 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8214 if(op==0x26) dep1[i]=rt1[i]; // LWR
8215 break;
8216 case IMM16:
8217 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8218 else rs1[i]=(source[i]>>21)&0x1f;
8219 rs2[i]=0;
8220 rt1[i]=(source[i]>>16)&0x1f;
8221 rt2[i]=0;
8222 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8223 imm[i]=(unsigned short)source[i];
8224 }else{
8225 imm[i]=(short)source[i];
8226 }
8227 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8228 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8229 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8230 break;
8231 case UJUMP:
8232 rs1[i]=0;
8233 rs2[i]=0;
8234 rt1[i]=0;
8235 rt2[i]=0;
8236 // The JAL instruction writes to r31.
8237 if (op&1) {
8238 rt1[i]=31;
8239 }
8240 rs2[i]=CCREG;
8241 break;
8242 case RJUMP:
8243 rs1[i]=(source[i]>>21)&0x1f;
8244 rs2[i]=0;
8245 rt1[i]=0;
8246 rt2[i]=0;
5067f341 8247 // The JALR instruction writes to rd.
57871462 8248 if (op2&1) {
5067f341 8249 rt1[i]=(source[i]>>11)&0x1f;
57871462 8250 }
8251 rs2[i]=CCREG;
8252 break;
8253 case CJUMP:
8254 rs1[i]=(source[i]>>21)&0x1f;
8255 rs2[i]=(source[i]>>16)&0x1f;
8256 rt1[i]=0;
8257 rt2[i]=0;
8258 if(op&2) { // BGTZ/BLEZ
8259 rs2[i]=0;
8260 }
8261 us1[i]=rs1[i];
8262 us2[i]=rs2[i];
8263 likely[i]=op>>4;
8264 break;
8265 case SJUMP:
8266 rs1[i]=(source[i]>>21)&0x1f;
8267 rs2[i]=CCREG;
8268 rt1[i]=0;
8269 rt2[i]=0;
8270 us1[i]=rs1[i];
8271 if(op2&0x10) { // BxxAL
8272 rt1[i]=31;
8273 // NOTE: If the branch is not taken, r31 is still overwritten
8274 }
8275 likely[i]=(op2&2)>>1;
8276 break;
8277 case FJUMP:
8278 rs1[i]=FSREG;
8279 rs2[i]=CSREG;
8280 rt1[i]=0;
8281 rt2[i]=0;
8282 likely[i]=((source[i])>>17)&1;
8283 break;
8284 case ALU:
8285 rs1[i]=(source[i]>>21)&0x1f; // source
8286 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8287 rt1[i]=(source[i]>>11)&0x1f; // destination
8288 rt2[i]=0;
8289 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8290 us1[i]=rs1[i];us2[i]=rs2[i];
8291 }
8292 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8293 dep1[i]=rs1[i];dep2[i]=rs2[i];
8294 }
8295 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8296 dep1[i]=rs1[i];dep2[i]=rs2[i];
8297 }
8298 break;
8299 case MULTDIV:
8300 rs1[i]=(source[i]>>21)&0x1f; // source
8301 rs2[i]=(source[i]>>16)&0x1f; // divisor
8302 rt1[i]=HIREG;
8303 rt2[i]=LOREG;
8304 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8305 us1[i]=rs1[i];us2[i]=rs2[i];
8306 }
8307 break;
8308 case MOV:
8309 rs1[i]=0;
8310 rs2[i]=0;
8311 rt1[i]=0;
8312 rt2[i]=0;
8313 if(op2==0x10) rs1[i]=HIREG; // MFHI
8314 if(op2==0x11) rt1[i]=HIREG; // MTHI
8315 if(op2==0x12) rs1[i]=LOREG; // MFLO
8316 if(op2==0x13) rt1[i]=LOREG; // MTLO
8317 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8318 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8319 dep1[i]=rs1[i];
8320 break;
8321 case SHIFT:
8322 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8323 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8324 rt1[i]=(source[i]>>11)&0x1f; // destination
8325 rt2[i]=0;
8326 // DSLLV/DSRLV/DSRAV are 64-bit
8327 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8328 break;
8329 case SHIFTIMM:
8330 rs1[i]=(source[i]>>16)&0x1f;
8331 rs2[i]=0;
8332 rt1[i]=(source[i]>>11)&0x1f;
8333 rt2[i]=0;
8334 imm[i]=(source[i]>>6)&0x1f;
8335 // DSxx32 instructions
8336 if(op2>=0x3c) imm[i]|=0x20;
8337 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8338 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8339 break;
8340 case COP0:
8341 rs1[i]=0;
8342 rs2[i]=0;
8343 rt1[i]=0;
8344 rt2[i]=0;
8345 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8346 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8347 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8348 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8349 break;
8350 case COP1:
b9b61529 8351 case COP2:
57871462 8352 rs1[i]=0;
8353 rs2[i]=0;
8354 rt1[i]=0;
8355 rt2[i]=0;
8356 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8357 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8358 if(op2==5) us1[i]=rs1[i]; // DMTC1
8359 rs2[i]=CSREG;
8360 break;
8361 case C1LS:
8362 rs1[i]=(source[i]>>21)&0x1F;
8363 rs2[i]=CSREG;
8364 rt1[i]=0;
8365 rt2[i]=0;
8366 imm[i]=(short)source[i];
8367 break;
b9b61529 8368 case C2LS:
8369 rs1[i]=(source[i]>>21)&0x1F;
8370 rs2[i]=0;
8371 rt1[i]=0;
8372 rt2[i]=0;
8373 imm[i]=(short)source[i];
8374 break;
57871462 8375 case FLOAT:
8376 case FCONV:
8377 rs1[i]=0;
8378 rs2[i]=CSREG;
8379 rt1[i]=0;
8380 rt2[i]=0;
8381 break;
8382 case FCOMP:
8383 rs1[i]=FSREG;
8384 rs2[i]=CSREG;
8385 rt1[i]=FSREG;
8386 rt2[i]=0;
8387 break;
8388 case SYSCALL:
7139f3c8 8389 case HLECALL:
1e973cb0 8390 case INTCALL:
57871462 8391 rs1[i]=CCREG;
8392 rs2[i]=0;
8393 rt1[i]=0;
8394 rt2[i]=0;
8395 break;
8396 default:
8397 rs1[i]=0;
8398 rs2[i]=0;
8399 rt1[i]=0;
8400 rt2[i]=0;
8401 }
8402 /* Calculate branch target addresses */
8403 if(type==UJUMP)
8404 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8405 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8406 ba[i]=start+i*4+8; // Ignore never taken branch
8407 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8408 ba[i]=start+i*4+8; // Ignore never taken branch
8409 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8410 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8411 else ba[i]=-1;
8412 /* Is this the end of the block? */
8413 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8414 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8415 done=2;
57871462 8416 }
8417 else {
8418 if(stop_after_jal) done=1;
8419 // Stop on BREAK
8420 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8421 }
8422 // Don't recompile stuff that's already compiled
8423 if(check_addr(start+i*4+4)) done=1;
8424 // Don't get too close to the limit
8425 if(i>MAXBLOCK/2) done=1;
8426 }
75dec299 8427 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8428 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8429 if(done==2) {
8430 // Does the block continue due to a branch?
8431 for(j=i-1;j>=0;j--)
8432 {
8433 if(ba[j]==start+i*4+4) done=j=0;
8434 if(ba[j]==start+i*4+8) done=j=0;
8435 }
8436 }
75dec299 8437 //assert(i<MAXBLOCK-1);
57871462 8438 if(start+i*4==pagelimit-4) done=1;
8439 assert(start+i*4<pagelimit);
8440 if (i==MAXBLOCK-1) done=1;
8441 // Stop if we're compiling junk
8442 if(itype[i]==NI&&opcode[i]==0x11) {
8443 done=stop_after_jal=1;
8444 printf("Disabled speculative precompilation\n");
8445 }
8446 }
8447 slen=i;
8448 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8449 if(start+i*4==pagelimit) {
8450 itype[i-1]=SPAN;
8451 }
8452 }
8453 assert(slen>0);
8454
8455 /* Pass 2 - Register dependencies and branch targets */
8456
8457 unneeded_registers(0,slen-1,0);
8458
8459 /* Pass 3 - Register allocation */
8460
8461 struct regstat current; // Current register allocations/status
8462 current.is32=1;
8463 current.dirty=0;
8464 current.u=unneeded_reg[0];
8465 current.uu=unneeded_reg_upper[0];
8466 clear_all_regs(current.regmap);
8467 alloc_reg(&current,0,CCREG);
8468 dirty_reg(&current,CCREG);
8469 current.isconst=0;
8470 current.wasconst=0;
8471 int ds=0;
8472 int cc=0;
8473 int hr;
8474
8475 provisional_32bit();
8476
8477 if((u_int)addr&1) {
8478 // First instruction is delay slot
8479 cc=-1;
8480 bt[1]=1;
8481 ds=1;
8482 unneeded_reg[0]=1;
8483 unneeded_reg_upper[0]=1;
8484 current.regmap[HOST_BTREG]=BTREG;
8485 }
8486
8487 for(i=0;i<slen;i++)
8488 {
8489 if(bt[i])
8490 {
8491 int hr;
8492 for(hr=0;hr<HOST_REGS;hr++)
8493 {
8494 // Is this really necessary?
8495 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8496 }
8497 current.isconst=0;
8498 }
8499 if(i>1)
8500 {
8501 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8502 {
8503 if(rs1[i-2]==0||rs2[i-2]==0)
8504 {
8505 if(rs1[i-2]) {
8506 current.is32|=1LL<<rs1[i-2];
8507 int hr=get_reg(current.regmap,rs1[i-2]|64);
8508 if(hr>=0) current.regmap[hr]=-1;
8509 }
8510 if(rs2[i-2]) {
8511 current.is32|=1LL<<rs2[i-2];
8512 int hr=get_reg(current.regmap,rs2[i-2]|64);
8513 if(hr>=0) current.regmap[hr]=-1;
8514 }
8515 }
8516 }
8517 }
8518 // If something jumps here with 64-bit values
8519 // then promote those registers to 64 bits
8520 if(bt[i])
8521 {
8522 uint64_t temp_is32=current.is32;
8523 for(j=i-1;j>=0;j--)
8524 {
8525 if(ba[j]==start+i*4)
8526 temp_is32&=branch_regs[j].is32;
8527 }
8528 for(j=i;j<slen;j++)
8529 {
8530 if(ba[j]==start+i*4)
8531 //temp_is32=1;
8532 temp_is32&=p32[j];
8533 }
8534 if(temp_is32!=current.is32) {
8535 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8536 #ifdef DESTRUCTIVE_WRITEBACK
8537 for(hr=0;hr<HOST_REGS;hr++)
8538 {
8539 int r=current.regmap[hr];
8540 if(r>0&&r<64)
8541 {
8542 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8543 temp_is32|=1LL<<r;
8544 //printf("restore %d\n",r);
8545 }
8546 }
8547 }
8548 #endif
8549 current.is32=temp_is32;
8550 }
8551 }
24385cae 8552#ifdef FORCE32
8553 memset(p32, 0xff, sizeof(p32));
8554 current.is32=-1LL;
8555#endif
8556
57871462 8557 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8558 regs[i].wasconst=current.isconst;
8559 regs[i].was32=current.is32;
8560 regs[i].wasdirty=current.dirty;
8561 #ifdef DESTRUCTIVE_WRITEBACK
8562 // To change a dirty register from 32 to 64 bits, we must write
8563 // it out during the previous cycle (for branches, 2 cycles)
8564 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8565 {
8566 uint64_t temp_is32=current.is32;
8567 for(j=i-1;j>=0;j--)
8568 {
8569 if(ba[j]==start+i*4+4)
8570 temp_is32&=branch_regs[j].is32;
8571 }
8572 for(j=i;j<slen;j++)
8573 {
8574 if(ba[j]==start+i*4+4)
8575 //temp_is32=1;
8576 temp_is32&=p32[j];
8577 }
8578 if(temp_is32!=current.is32) {
8579 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8580 for(hr=0;hr<HOST_REGS;hr++)
8581 {
8582 int r=current.regmap[hr];
8583 if(r>0)
8584 {
8585 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8586 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8587 {
8588 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8589 {
8590 //printf("dump %d/r%d\n",hr,r);
8591 current.regmap[hr]=-1;
8592 if(get_reg(current.regmap,r|64)>=0)
8593 current.regmap[get_reg(current.regmap,r|64)]=-1;
8594 }
8595 }
8596 }
8597 }
8598 }
8599 }
8600 }
8601 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8602 {
8603 uint64_t temp_is32=current.is32;
8604 for(j=i-1;j>=0;j--)
8605 {
8606 if(ba[j]==start+i*4+8)
8607 temp_is32&=branch_regs[j].is32;
8608 }
8609 for(j=i;j<slen;j++)
8610 {
8611 if(ba[j]==start+i*4+8)
8612 //temp_is32=1;
8613 temp_is32&=p32[j];
8614 }
8615 if(temp_is32!=current.is32) {
8616 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8617 for(hr=0;hr<HOST_REGS;hr++)
8618 {
8619 int r=current.regmap[hr];
8620 if(r>0)
8621 {
8622 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8623 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8624 {
8625 //printf("dump %d/r%d\n",hr,r);
8626 current.regmap[hr]=-1;
8627 if(get_reg(current.regmap,r|64)>=0)
8628 current.regmap[get_reg(current.regmap,r|64)]=-1;
8629 }
8630 }
8631 }
8632 }
8633 }
8634 }
8635 #endif
8636 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8637 if(i+1<slen) {
8638 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8639 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8640 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8641 current.u|=1;
8642 current.uu|=1;
8643 } else {
8644 current.u=1;
8645 current.uu=1;
8646 }
8647 } else {
8648 if(i+1<slen) {
8649 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8650 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8651 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8652 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8653 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8654 current.u|=1;
8655 current.uu|=1;
8656 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8657 }
8658 is_ds[i]=ds;
8659 if(ds) {
8660 ds=0; // Skip delay slot, already allocated as part of branch
8661 // ...but we need to alloc it in case something jumps here
8662 if(i+1<slen) {
8663 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8664 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8665 }else{
8666 current.u=branch_unneeded_reg[i-1];
8667 current.uu=branch_unneeded_reg_upper[i-1];
8668 }
8669 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8670 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8671 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8672 current.u|=1;
8673 current.uu|=1;
8674 struct regstat temp;
8675 memcpy(&temp,&current,sizeof(current));
8676 temp.wasdirty=temp.dirty;
8677 temp.was32=temp.is32;
8678 // TODO: Take into account unconditional branches, as below
8679 delayslot_alloc(&temp,i);
8680 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8681 regs[i].wasdirty=temp.wasdirty;
8682 regs[i].was32=temp.was32;
8683 regs[i].dirty=temp.dirty;
8684 regs[i].is32=temp.is32;
8685 regs[i].isconst=0;
8686 regs[i].wasconst=0;
8687 current.isconst=0;
8688 // Create entry (branch target) regmap
8689 for(hr=0;hr<HOST_REGS;hr++)
8690 {
8691 int r=temp.regmap[hr];
8692 if(r>=0) {
8693 if(r!=regmap_pre[i][hr]) {
8694 regs[i].regmap_entry[hr]=-1;
8695 }
8696 else
8697 {
8698 if(r<64){
8699 if((current.u>>r)&1) {
8700 regs[i].regmap_entry[hr]=-1;
8701 regs[i].regmap[hr]=-1;
8702 //Don't clear regs in the delay slot as the branch might need them
8703 //current.regmap[hr]=-1;
8704 }else
8705 regs[i].regmap_entry[hr]=r;
8706 }
8707 else {
8708 if((current.uu>>(r&63))&1) {
8709 regs[i].regmap_entry[hr]=-1;
8710 regs[i].regmap[hr]=-1;
8711 //Don't clear regs in the delay slot as the branch might need them
8712 //current.regmap[hr]=-1;
8713 }else
8714 regs[i].regmap_entry[hr]=r;
8715 }
8716 }
8717 } else {
8718 // First instruction expects CCREG to be allocated
8719 if(i==0&&hr==HOST_CCREG)
8720 regs[i].regmap_entry[hr]=CCREG;
8721 else
8722 regs[i].regmap_entry[hr]=-1;
8723 }
8724 }
8725 }
8726 else { // Not delay slot
8727 switch(itype[i]) {
8728 case UJUMP:
8729 //current.isconst=0; // DEBUG
8730 //current.wasconst=0; // DEBUG
8731 //regs[i].wasconst=0; // DEBUG
8732 clear_const(&current,rt1[i]);
8733 alloc_cc(&current,i);
8734 dirty_reg(&current,CCREG);
8735 if (rt1[i]==31) {
8736 alloc_reg(&current,i,31);
8737 dirty_reg(&current,31);
076655d1 8738 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8739 assert(rt1[i+1]!=rt1[i]);
57871462 8740 #ifdef REG_PREFETCH
8741 alloc_reg(&current,i,PTEMP);
8742 #endif
8743 //current.is32|=1LL<<rt1[i];
8744 }
8745 delayslot_alloc(&current,i+1);
8746 //current.isconst=0; // DEBUG
8747 ds=1;
8748 //printf("i=%d, isconst=%x\n",i,current.isconst);
8749 break;
8750 case RJUMP:
8751 //current.isconst=0;
8752 //current.wasconst=0;
8753 //regs[i].wasconst=0;
8754 clear_const(&current,rs1[i]);
8755 clear_const(&current,rt1[i]);
8756 alloc_cc(&current,i);
8757 dirty_reg(&current,CCREG);
8758 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8759 alloc_reg(&current,i,rs1[i]);
5067f341 8760 if (rt1[i]!=0) {
8761 alloc_reg(&current,i,rt1[i]);
8762 dirty_reg(&current,rt1[i]);
076655d1 8763 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8764 assert(rt1[i+1]!=rt1[i]);
57871462 8765 #ifdef REG_PREFETCH
8766 alloc_reg(&current,i,PTEMP);
8767 #endif
8768 }
8769 #ifdef USE_MINI_HT
8770 if(rs1[i]==31) { // JALR
8771 alloc_reg(&current,i,RHASH);
8772 #ifndef HOST_IMM_ADDR32
8773 alloc_reg(&current,i,RHTBL);
8774 #endif
8775 }
8776 #endif
8777 delayslot_alloc(&current,i+1);
8778 } else {
8779 // The delay slot overwrites our source register,
8780 // allocate a temporary register to hold the old value.
8781 current.isconst=0;
8782 current.wasconst=0;
8783 regs[i].wasconst=0;
8784 delayslot_alloc(&current,i+1);
8785 current.isconst=0;
8786 alloc_reg(&current,i,RTEMP);
8787 }
8788 //current.isconst=0; // DEBUG
8789 ds=1;
8790 break;
8791 case CJUMP:
8792 //current.isconst=0;
8793 //current.wasconst=0;
8794 //regs[i].wasconst=0;
8795 clear_const(&current,rs1[i]);
8796 clear_const(&current,rs2[i]);
8797 if((opcode[i]&0x3E)==4) // BEQ/BNE
8798 {
8799 alloc_cc(&current,i);
8800 dirty_reg(&current,CCREG);
8801 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8802 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8803 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8804 {
8805 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8806 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8807 }
8808 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8809 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8810 // The delay slot overwrites one of our conditions.
8811 // Allocate the branch condition registers instead.
8812 // Note that such a sequence of instructions could
8813 // be considered a bug since the branch can not be
8814 // re-executed if an exception occurs.
8815 current.isconst=0;
8816 current.wasconst=0;
8817 regs[i].wasconst=0;
8818 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8819 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8820 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8821 {
8822 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8823 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8824 }
8825 }
8826 else delayslot_alloc(&current,i+1);
8827 }
8828 else
8829 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8830 {
8831 alloc_cc(&current,i);
8832 dirty_reg(&current,CCREG);
8833 alloc_reg(&current,i,rs1[i]);
8834 if(!(current.is32>>rs1[i]&1))
8835 {
8836 alloc_reg64(&current,i,rs1[i]);
8837 }
8838 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8839 // The delay slot overwrites one of our conditions.
8840 // Allocate the branch condition registers instead.
8841 // Note that such a sequence of instructions could
8842 // be considered a bug since the branch can not be
8843 // re-executed if an exception occurs.
8844 current.isconst=0;
8845 current.wasconst=0;
8846 regs[i].wasconst=0;
8847 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8848 if(!((current.is32>>rs1[i])&1))
8849 {
8850 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8851 }
8852 }
8853 else delayslot_alloc(&current,i+1);
8854 }
8855 else
8856 // Don't alloc the delay slot yet because we might not execute it
8857 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8858 {
8859 current.isconst=0;
8860 current.wasconst=0;
8861 regs[i].wasconst=0;
8862 alloc_cc(&current,i);
8863 dirty_reg(&current,CCREG);
8864 alloc_reg(&current,i,rs1[i]);
8865 alloc_reg(&current,i,rs2[i]);
8866 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8867 {
8868 alloc_reg64(&current,i,rs1[i]);
8869 alloc_reg64(&current,i,rs2[i]);
8870 }
8871 }
8872 else
8873 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8874 {
8875 current.isconst=0;
8876 current.wasconst=0;
8877 regs[i].wasconst=0;
8878 alloc_cc(&current,i);
8879 dirty_reg(&current,CCREG);
8880 alloc_reg(&current,i,rs1[i]);
8881 if(!(current.is32>>rs1[i]&1))
8882 {
8883 alloc_reg64(&current,i,rs1[i]);
8884 }
8885 }
8886 ds=1;
8887 //current.isconst=0;
8888 break;
8889 case SJUMP:
8890 //current.isconst=0;
8891 //current.wasconst=0;
8892 //regs[i].wasconst=0;
8893 clear_const(&current,rs1[i]);
8894 clear_const(&current,rt1[i]);
8895 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8896 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8897 {
8898 alloc_cc(&current,i);
8899 dirty_reg(&current,CCREG);
8900 alloc_reg(&current,i,rs1[i]);
8901 if(!(current.is32>>rs1[i]&1))
8902 {
8903 alloc_reg64(&current,i,rs1[i]);
8904 }
8905 if (rt1[i]==31) { // BLTZAL/BGEZAL
8906 alloc_reg(&current,i,31);
8907 dirty_reg(&current,31);
8908 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8909 //#ifdef REG_PREFETCH
8910 //alloc_reg(&current,i,PTEMP);
8911 //#endif
8912 //current.is32|=1LL<<rt1[i];
8913 }
8914 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8915 // The delay slot overwrites the branch condition.
8916 // Allocate the branch condition registers instead.
8917 // Note that such a sequence of instructions could
8918 // be considered a bug since the branch can not be
8919 // re-executed if an exception occurs.
8920 current.isconst=0;
8921 current.wasconst=0;
8922 regs[i].wasconst=0;
8923 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8924 if(!((current.is32>>rs1[i])&1))
8925 {
8926 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8927 }
8928 }
8929 else delayslot_alloc(&current,i+1);
8930 }
8931 else
8932 // Don't alloc the delay slot yet because we might not execute it
8933 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8934 {
8935 current.isconst=0;
8936 current.wasconst=0;
8937 regs[i].wasconst=0;
8938 alloc_cc(&current,i);
8939 dirty_reg(&current,CCREG);
8940 alloc_reg(&current,i,rs1[i]);
8941 if(!(current.is32>>rs1[i]&1))
8942 {
8943 alloc_reg64(&current,i,rs1[i]);
8944 }
8945 }
8946 ds=1;
8947 //current.isconst=0;
8948 break;
8949 case FJUMP:
8950 current.isconst=0;
8951 current.wasconst=0;
8952 regs[i].wasconst=0;
8953 if(likely[i]==0) // BC1F/BC1T
8954 {
8955 // TODO: Theoretically we can run out of registers here on x86.
8956 // The delay slot can allocate up to six, and we need to check
8957 // CSREG before executing the delay slot. Possibly we can drop
8958 // the cycle count and then reload it after checking that the
8959 // FPU is in a usable state, or don't do out-of-order execution.
8960 alloc_cc(&current,i);
8961 dirty_reg(&current,CCREG);
8962 alloc_reg(&current,i,FSREG);
8963 alloc_reg(&current,i,CSREG);
8964 if(itype[i+1]==FCOMP) {
8965 // The delay slot overwrites the branch condition.
8966 // Allocate the branch condition registers instead.
8967 // Note that such a sequence of instructions could
8968 // be considered a bug since the branch can not be
8969 // re-executed if an exception occurs.
8970 alloc_cc(&current,i);
8971 dirty_reg(&current,CCREG);
8972 alloc_reg(&current,i,CSREG);
8973 alloc_reg(&current,i,FSREG);
8974 }
8975 else {
8976 delayslot_alloc(&current,i+1);
8977 alloc_reg(&current,i+1,CSREG);
8978 }
8979 }
8980 else
8981 // Don't alloc the delay slot yet because we might not execute it
8982 if(likely[i]) // BC1FL/BC1TL
8983 {
8984 alloc_cc(&current,i);
8985 dirty_reg(&current,CCREG);
8986 alloc_reg(&current,i,CSREG);
8987 alloc_reg(&current,i,FSREG);
8988 }
8989 ds=1;
8990 current.isconst=0;
8991 break;
8992 case IMM16:
8993 imm16_alloc(&current,i);
8994 break;
8995 case LOAD:
8996 case LOADLR:
8997 load_alloc(&current,i);
8998 break;
8999 case STORE:
9000 case STORELR:
9001 store_alloc(&current,i);
9002 break;
9003 case ALU:
9004 alu_alloc(&current,i);
9005 break;
9006 case SHIFT:
9007 shift_alloc(&current,i);
9008 break;
9009 case MULTDIV:
9010 multdiv_alloc(&current,i);
9011 break;
9012 case SHIFTIMM:
9013 shiftimm_alloc(&current,i);
9014 break;
9015 case MOV:
9016 mov_alloc(&current,i);
9017 break;
9018 case COP0:
9019 cop0_alloc(&current,i);
9020 break;
9021 case COP1:
b9b61529 9022 case COP2:
57871462 9023 cop1_alloc(&current,i);
9024 break;
9025 case C1LS:
9026 c1ls_alloc(&current,i);
9027 break;
b9b61529 9028 case C2LS:
9029 c2ls_alloc(&current,i);
9030 break;
9031 case C2OP:
9032 c2op_alloc(&current,i);
9033 break;
57871462 9034 case FCONV:
9035 fconv_alloc(&current,i);
9036 break;
9037 case FLOAT:
9038 float_alloc(&current,i);
9039 break;
9040 case FCOMP:
9041 fcomp_alloc(&current,i);
9042 break;
9043 case SYSCALL:
7139f3c8 9044 case HLECALL:
1e973cb0 9045 case INTCALL:
57871462 9046 syscall_alloc(&current,i);
9047 break;
9048 case SPAN:
9049 pagespan_alloc(&current,i);
9050 break;
9051 }
9052
9053 // Drop the upper half of registers that have become 32-bit
9054 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9055 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9056 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9057 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9058 current.uu|=1;
9059 } else {
9060 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9061 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9062 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9063 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9064 current.uu|=1;
9065 }
9066
9067 // Create entry (branch target) regmap
9068 for(hr=0;hr<HOST_REGS;hr++)
9069 {
9070 int r,or,er;
9071 r=current.regmap[hr];
9072 if(r>=0) {
9073 if(r!=regmap_pre[i][hr]) {
9074 // TODO: delay slot (?)
9075 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9076 if(or<0||(r&63)>=TEMPREG){
9077 regs[i].regmap_entry[hr]=-1;
9078 }
9079 else
9080 {
9081 // Just move it to a different register
9082 regs[i].regmap_entry[hr]=r;
9083 // If it was dirty before, it's still dirty
9084 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9085 }
9086 }
9087 else
9088 {
9089 // Unneeded
9090 if(r==0){
9091 regs[i].regmap_entry[hr]=0;
9092 }
9093 else
9094 if(r<64){
9095 if((current.u>>r)&1) {
9096 regs[i].regmap_entry[hr]=-1;
9097 //regs[i].regmap[hr]=-1;
9098 current.regmap[hr]=-1;
9099 }else
9100 regs[i].regmap_entry[hr]=r;
9101 }
9102 else {
9103 if((current.uu>>(r&63))&1) {
9104 regs[i].regmap_entry[hr]=-1;
9105 //regs[i].regmap[hr]=-1;
9106 current.regmap[hr]=-1;
9107 }else
9108 regs[i].regmap_entry[hr]=r;
9109 }
9110 }
9111 } else {
9112 // Branches expect CCREG to be allocated at the target
9113 if(regmap_pre[i][hr]==CCREG)
9114 regs[i].regmap_entry[hr]=CCREG;
9115 else
9116 regs[i].regmap_entry[hr]=-1;
9117 }
9118 }
9119 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9120 }
9121 /* Branch post-alloc */
9122 if(i>0)
9123 {
9124 current.was32=current.is32;
9125 current.wasdirty=current.dirty;
9126 switch(itype[i-1]) {
9127 case UJUMP:
9128 memcpy(&branch_regs[i-1],&current,sizeof(current));
9129 branch_regs[i-1].isconst=0;
9130 branch_regs[i-1].wasconst=0;
9131 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9132 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9133 alloc_cc(&branch_regs[i-1],i-1);
9134 dirty_reg(&branch_regs[i-1],CCREG);
9135 if(rt1[i-1]==31) { // JAL
9136 alloc_reg(&branch_regs[i-1],i-1,31);
9137 dirty_reg(&branch_regs[i-1],31);
9138 branch_regs[i-1].is32|=1LL<<31;
9139 }
9140 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9141 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9142 break;
9143 case RJUMP:
9144 memcpy(&branch_regs[i-1],&current,sizeof(current));
9145 branch_regs[i-1].isconst=0;
9146 branch_regs[i-1].wasconst=0;
9147 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9148 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9149 alloc_cc(&branch_regs[i-1],i-1);
9150 dirty_reg(&branch_regs[i-1],CCREG);
9151 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9152 if(rt1[i-1]!=0) { // JALR
9153 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9154 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9155 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9156 }
9157 #ifdef USE_MINI_HT
9158 if(rs1[i-1]==31) { // JALR
9159 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9160 #ifndef HOST_IMM_ADDR32
9161 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9162 #endif
9163 }
9164 #endif
9165 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9166 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9167 break;
9168 case CJUMP:
9169 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9170 {
9171 alloc_cc(&current,i-1);
9172 dirty_reg(&current,CCREG);
9173 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9174 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9175 // The delay slot overwrote one of our conditions
9176 // Delay slot goes after the test (in order)
9177 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9178 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9179 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9180 current.u|=1;
9181 current.uu|=1;
9182 delayslot_alloc(&current,i);
9183 current.isconst=0;
9184 }
9185 else
9186 {
9187 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9188 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9189 // Alloc the branch condition registers
9190 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9191 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9192 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9193 {
9194 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9195 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9196 }
9197 }
9198 memcpy(&branch_regs[i-1],&current,sizeof(current));
9199 branch_regs[i-1].isconst=0;
9200 branch_regs[i-1].wasconst=0;
9201 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9202 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9203 }
9204 else
9205 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9206 {
9207 alloc_cc(&current,i-1);
9208 dirty_reg(&current,CCREG);
9209 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9210 // The delay slot overwrote the branch condition
9211 // Delay slot goes after the test (in order)
9212 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9213 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9214 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9215 current.u|=1;
9216 current.uu|=1;
9217 delayslot_alloc(&current,i);
9218 current.isconst=0;
9219 }
9220 else
9221 {
9222 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9223 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9224 // Alloc the branch condition register
9225 alloc_reg(&current,i-1,rs1[i-1]);
9226 if(!(current.is32>>rs1[i-1]&1))
9227 {
9228 alloc_reg64(&current,i-1,rs1[i-1]);
9229 }
9230 }
9231 memcpy(&branch_regs[i-1],&current,sizeof(current));
9232 branch_regs[i-1].isconst=0;
9233 branch_regs[i-1].wasconst=0;
9234 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9235 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9236 }
9237 else
9238 // Alloc the delay slot in case the branch is taken
9239 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9240 {
9241 memcpy(&branch_regs[i-1],&current,sizeof(current));
9242 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9243 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9244 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9245 alloc_cc(&branch_regs[i-1],i);
9246 dirty_reg(&branch_regs[i-1],CCREG);
9247 delayslot_alloc(&branch_regs[i-1],i);
9248 branch_regs[i-1].isconst=0;
9249 alloc_reg(&current,i,CCREG); // Not taken path
9250 dirty_reg(&current,CCREG);
9251 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9252 }
9253 else
9254 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9255 {
9256 memcpy(&branch_regs[i-1],&current,sizeof(current));
9257 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9258 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9259 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9260 alloc_cc(&branch_regs[i-1],i);
9261 dirty_reg(&branch_regs[i-1],CCREG);
9262 delayslot_alloc(&branch_regs[i-1],i);
9263 branch_regs[i-1].isconst=0;
9264 alloc_reg(&current,i,CCREG); // Not taken path
9265 dirty_reg(&current,CCREG);
9266 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9267 }
9268 break;
9269 case SJUMP:
9270 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9271 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9272 {
9273 alloc_cc(&current,i-1);
9274 dirty_reg(&current,CCREG);
9275 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9276 // The delay slot overwrote the branch condition
9277 // Delay slot goes after the test (in order)
9278 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9279 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9280 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9281 current.u|=1;
9282 current.uu|=1;
9283 delayslot_alloc(&current,i);
9284 current.isconst=0;
9285 }
9286 else
9287 {
9288 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9289 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9290 // Alloc the branch condition register
9291 alloc_reg(&current,i-1,rs1[i-1]);
9292 if(!(current.is32>>rs1[i-1]&1))
9293 {
9294 alloc_reg64(&current,i-1,rs1[i-1]);
9295 }
9296 }
9297 memcpy(&branch_regs[i-1],&current,sizeof(current));
9298 branch_regs[i-1].isconst=0;
9299 branch_regs[i-1].wasconst=0;
9300 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9301 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9302 }
9303 else
9304 // Alloc the delay slot in case the branch is taken
9305 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9306 {
9307 memcpy(&branch_regs[i-1],&current,sizeof(current));
9308 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9309 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9310 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9311 alloc_cc(&branch_regs[i-1],i);
9312 dirty_reg(&branch_regs[i-1],CCREG);
9313 delayslot_alloc(&branch_regs[i-1],i);
9314 branch_regs[i-1].isconst=0;
9315 alloc_reg(&current,i,CCREG); // Not taken path
9316 dirty_reg(&current,CCREG);
9317 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9318 }
9319 // FIXME: BLTZAL/BGEZAL
9320 if(opcode2[i-1]&0x10) { // BxxZAL
9321 alloc_reg(&branch_regs[i-1],i-1,31);
9322 dirty_reg(&branch_regs[i-1],31);
9323 branch_regs[i-1].is32|=1LL<<31;
9324 }
9325 break;
9326 case FJUMP:
9327 if(likely[i-1]==0) // BC1F/BC1T
9328 {
9329 alloc_cc(&current,i-1);
9330 dirty_reg(&current,CCREG);
9331 if(itype[i]==FCOMP) {
9332 // The delay slot overwrote the branch condition
9333 // Delay slot goes after the test (in order)
9334 delayslot_alloc(&current,i);
9335 current.isconst=0;
9336 }
9337 else
9338 {
9339 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9340 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9341 // Alloc the branch condition register
9342 alloc_reg(&current,i-1,FSREG);
9343 }
9344 memcpy(&branch_regs[i-1],&current,sizeof(current));
9345 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9346 }
9347 else // BC1FL/BC1TL
9348 {
9349 // Alloc the delay slot in case the branch is taken
9350 memcpy(&branch_regs[i-1],&current,sizeof(current));
9351 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9352 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9353 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9354 alloc_cc(&branch_regs[i-1],i);
9355 dirty_reg(&branch_regs[i-1],CCREG);
9356 delayslot_alloc(&branch_regs[i-1],i);
9357 branch_regs[i-1].isconst=0;
9358 alloc_reg(&current,i,CCREG); // Not taken path
9359 dirty_reg(&current,CCREG);
9360 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9361 }
9362 break;
9363 }
9364
9365 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9366 {
9367 if(rt1[i-1]==31) // JAL/JALR
9368 {
9369 // Subroutine call will return here, don't alloc any registers
9370 current.is32=1;
9371 current.dirty=0;
9372 clear_all_regs(current.regmap);
9373 alloc_reg(&current,i,CCREG);
9374 dirty_reg(&current,CCREG);
9375 }
9376 else if(i+1<slen)
9377 {
9378 // Internal branch will jump here, match registers to caller
9379 current.is32=0x3FFFFFFFFLL;
9380 current.dirty=0;
9381 clear_all_regs(current.regmap);
9382 alloc_reg(&current,i,CCREG);
9383 dirty_reg(&current,CCREG);
9384 for(j=i-1;j>=0;j--)
9385 {
9386 if(ba[j]==start+i*4+4) {
9387 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9388 current.is32=branch_regs[j].is32;
9389 current.dirty=branch_regs[j].dirty;
9390 break;
9391 }
9392 }
9393 while(j>=0) {
9394 if(ba[j]==start+i*4+4) {
9395 for(hr=0;hr<HOST_REGS;hr++) {
9396 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9397 current.regmap[hr]=-1;
9398 }
9399 current.is32&=branch_regs[j].is32;
9400 current.dirty&=branch_regs[j].dirty;
9401 }
9402 }
9403 j--;
9404 }
9405 }
9406 }
9407 }
9408
9409 // Count cycles in between branches
9410 ccadj[i]=cc;
7139f3c8 9411 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9412 {
9413 cc=0;
9414 }
9415 else
9416 {
9417 cc++;
9418 }
9419
9420 flush_dirty_uppers(&current);
9421 if(!is_ds[i]) {
9422 regs[i].is32=current.is32;
9423 regs[i].dirty=current.dirty;
9424 regs[i].isconst=current.isconst;
9425 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9426 }
9427 for(hr=0;hr<HOST_REGS;hr++) {
9428 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9429 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9430 regs[i].wasconst&=~(1<<hr);
9431 }
9432 }
9433 }
9434 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9435 }
9436
9437 /* Pass 4 - Cull unused host registers */
9438
9439 uint64_t nr=0;
9440
9441 for (i=slen-1;i>=0;i--)
9442 {
9443 int hr;
9444 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9445 {
9446 if(ba[i]<start || ba[i]>=(start+slen*4))
9447 {
9448 // Branch out of this block, don't need anything
9449 nr=0;
9450 }
9451 else
9452 {
9453 // Internal branch
9454 // Need whatever matches the target
9455 nr=0;
9456 int t=(ba[i]-start)>>2;
9457 for(hr=0;hr<HOST_REGS;hr++)
9458 {
9459 if(regs[i].regmap_entry[hr]>=0) {
9460 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9461 }
9462 }
9463 }
9464 // Conditional branch may need registers for following instructions
9465 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9466 {
9467 if(i<slen-2) {
9468 nr|=needed_reg[i+2];
9469 for(hr=0;hr<HOST_REGS;hr++)
9470 {
9471 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9472 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9473 }
9474 }
9475 }
9476 // Don't need stuff which is overwritten
9477 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9478 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9479 // Merge in delay slot
9480 for(hr=0;hr<HOST_REGS;hr++)
9481 {
9482 if(!likely[i]) {
9483 // These are overwritten unless the branch is "likely"
9484 // and the delay slot is nullified if not taken
9485 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9486 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9487 }
9488 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9489 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9490 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9491 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9492 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9493 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9494 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9495 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9496 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9497 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9498 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9499 }
9500 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9501 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9502 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9503 }
b9b61529 9504 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9505 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9506 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9507 }
9508 }
9509 }
1e973cb0 9510 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9511 {
9512 // SYSCALL instruction (software interrupt)
9513 nr=0;
9514 }
9515 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9516 {
9517 // ERET instruction (return from interrupt)
9518 nr=0;
9519 }
9520 else // Non-branch
9521 {
9522 if(i<slen-1) {
9523 for(hr=0;hr<HOST_REGS;hr++) {
9524 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9525 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9526 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9527 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9528 }
9529 }
9530 }
9531 for(hr=0;hr<HOST_REGS;hr++)
9532 {
9533 // Overwritten registers are not needed
9534 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9535 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9536 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9537 // Source registers are needed
9538 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9539 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9540 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9541 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9542 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9543 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9544 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9545 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9546 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9547 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9548 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9549 }
9550 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9551 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9552 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9553 }
b9b61529 9554 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9555 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9556 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9557 }
9558 // Don't store a register immediately after writing it,
9559 // may prevent dual-issue.
9560 // But do so if this is a branch target, otherwise we
9561 // might have to load the register before the branch.
9562 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9563 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9564 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9565 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9566 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9567 }
9568 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9569 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9570 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9571 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9572 }
9573 }
9574 }
9575 // Cycle count is needed at branches. Assume it is needed at the target too.
9576 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9577 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9578 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9579 }
9580 // Save it
9581 needed_reg[i]=nr;
9582
9583 // Deallocate unneeded registers
9584 for(hr=0;hr<HOST_REGS;hr++)
9585 {
9586 if(!((nr>>hr)&1)) {
9587 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9588 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9589 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9590 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9591 {
9592 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9593 {
9594 if(likely[i]) {
9595 regs[i].regmap[hr]=-1;
9596 regs[i].isconst&=~(1<<hr);
9597 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9598 }
9599 }
9600 }
9601 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9602 {
9603 int d1=0,d2=0,map=0,temp=0;
9604 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9605 {
9606 d1=dep1[i+1];
9607 d2=dep2[i+1];
9608 }
9609 if(using_tlb) {
9610 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9611 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9612 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9613 map=TLREG;
9614 } else
b9b61529 9615 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9616 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9617 map=INVCP;
9618 }
9619 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9620 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9621 temp=FTEMP;
9622 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9623 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9624 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9625 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9626 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9627 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9628 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9629 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9630 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9631 regs[i].regmap[hr]!=map )
9632 {
9633 regs[i].regmap[hr]=-1;
9634 regs[i].isconst&=~(1<<hr);
9635 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9636 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9637 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9638 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9639 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9640 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9641 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9642 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9643 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9644 branch_regs[i].regmap[hr]!=map)
9645 {
9646 branch_regs[i].regmap[hr]=-1;
9647 branch_regs[i].regmap_entry[hr]=-1;
9648 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9649 {
9650 if(!likely[i]&&i<slen-2) {
9651 regmap_pre[i+2][hr]=-1;
9652 }
9653 }
9654 }
9655 }
9656 }
9657 else
9658 {
9659 // Non-branch
9660 if(i>0)
9661 {
9662 int d1=0,d2=0,map=-1,temp=-1;
9663 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9664 {
9665 d1=dep1[i];
9666 d2=dep2[i];
9667 }
9668 if(using_tlb) {
9669 if(itype[i]==LOAD || itype[i]==LOADLR ||
9670 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9671 itype[i]==C1LS || itype[i]==C2LS)
57871462 9672 map=TLREG;
b9b61529 9673 } else if(itype[i]==STORE || itype[i]==STORELR ||
9674 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9675 map=INVCP;
9676 }
9677 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9678 itype[i]==C1LS || itype[i]==C2LS)
57871462 9679 temp=FTEMP;
9680 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9681 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9682 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9683 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9684 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9685 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9686 {
9687 if(i<slen-1&&!is_ds[i]) {
9688 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9689 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9690 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9691 {
9692 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9693 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9694 }
9695 regmap_pre[i+1][hr]=-1;
9696 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9697 }
9698 regs[i].regmap[hr]=-1;
9699 regs[i].isconst&=~(1<<hr);
9700 }
9701 }
9702 }
9703 }
9704 }
9705 }
9706
9707 /* Pass 5 - Pre-allocate registers */
9708
9709 // If a register is allocated during a loop, try to allocate it for the
9710 // entire loop, if possible. This avoids loading/storing registers
9711 // inside of the loop.
9712
9713 signed char f_regmap[HOST_REGS];
9714 clear_all_regs(f_regmap);
9715 for(i=0;i<slen-1;i++)
9716 {
9717 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9718 {
9719 if(ba[i]>=start && ba[i]<(start+i*4))
9720 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9721 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9722 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9723 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9724 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9725 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9726 {
9727 int t=(ba[i]-start)>>2;
9728 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9729 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9730 for(hr=0;hr<HOST_REGS;hr++)
9731 {
9732 if(regs[i].regmap[hr]>64) {
9733 if(!((regs[i].dirty>>hr)&1))
9734 f_regmap[hr]=regs[i].regmap[hr];
9735 else f_regmap[hr]=-1;
9736 }
b372a952 9737 else if(regs[i].regmap[hr]>=0) {
9738 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9739 // dealloc old register
9740 int n;
9741 for(n=0;n<HOST_REGS;n++)
9742 {
9743 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9744 }
9745 // and alloc new one
9746 f_regmap[hr]=regs[i].regmap[hr];
9747 }
9748 }
57871462 9749 if(branch_regs[i].regmap[hr]>64) {
9750 if(!((branch_regs[i].dirty>>hr)&1))
9751 f_regmap[hr]=branch_regs[i].regmap[hr];
9752 else f_regmap[hr]=-1;
9753 }
b372a952 9754 else if(branch_regs[i].regmap[hr]>=0) {
9755 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9756 // dealloc old register
9757 int n;
9758 for(n=0;n<HOST_REGS;n++)
9759 {
9760 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9761 }
9762 // and alloc new one
9763 f_regmap[hr]=branch_regs[i].regmap[hr];
9764 }
9765 }
57871462 9766 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9767 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9768 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9769 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9770 {
9771 // Test both in case the delay slot is ooo,
9772 // could be done better...
9773 if(count_free_regs(branch_regs[i].regmap)<2
9774 ||count_free_regs(regs[i].regmap)<2)
9775 f_regmap[hr]=branch_regs[i].regmap[hr];
9776 }
9777 // Avoid dirty->clean transition
9778 // #ifdef DESTRUCTIVE_WRITEBACK here?
9779 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9780 if(f_regmap[hr]>0) {
9781 if(regs[t].regmap_entry[hr]<0) {
9782 int r=f_regmap[hr];
9783 for(j=t;j<=i;j++)
9784 {
9785 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9786 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9787 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9788 if(r>63) {
9789 // NB This can exclude the case where the upper-half
9790 // register is lower numbered than the lower-half
9791 // register. Not sure if it's worth fixing...
9792 if(get_reg(regs[j].regmap,r&63)<0) break;
9793 if(regs[j].is32&(1LL<<(r&63))) break;
9794 }
9795 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9796 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9797 int k;
9798 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9799 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9800 if(r>63) {
9801 if(get_reg(regs[i].regmap,r&63)<0) break;
9802 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9803 }
9804 k=i;
9805 while(k>1&&regs[k-1].regmap[hr]==-1) {
9806 if(itype[k-1]==STORE||itype[k-1]==STORELR
9807 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
b9b61529 9808 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9809 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 9810 if(count_free_regs(regs[k-1].regmap)<2) {
9811 //printf("no free regs for store %x\n",start+(k-1)*4);
9812 break;
9813 }
9814 }
9815 else
9816 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9817 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9818 //printf("no-match due to different register\n");
9819 break;
9820 }
9821 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9822 //printf("no-match due to branch\n");
9823 break;
9824 }
9825 // call/ret fast path assumes no registers allocated
9826 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9827 break;
9828 }
9829 if(r>63) {
9830 // NB This can exclude the case where the upper-half
9831 // register is lower numbered than the lower-half
9832 // register. Not sure if it's worth fixing...
9833 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9834 if(regs[k-1].is32&(1LL<<(r&63))) break;
9835 }
9836 k--;
9837 }
9838 if(i<slen-1) {
9839 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9840 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9841 //printf("bad match after branch\n");
9842 break;
9843 }
9844 }
9845 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9846 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9847 while(k<i) {
9848 regs[k].regmap_entry[hr]=f_regmap[hr];
9849 regs[k].regmap[hr]=f_regmap[hr];
9850 regmap_pre[k+1][hr]=f_regmap[hr];
9851 regs[k].wasdirty&=~(1<<hr);
9852 regs[k].dirty&=~(1<<hr);
9853 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9854 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9855 regs[k].wasconst&=~(1<<hr);
9856 regs[k].isconst&=~(1<<hr);
9857 k++;
9858 }
9859 }
9860 else {
9861 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9862 break;
9863 }
9864 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9865 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9866 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9867 regs[i].regmap_entry[hr]=f_regmap[hr];
9868 regs[i].regmap[hr]=f_regmap[hr];
9869 regs[i].wasdirty&=~(1<<hr);
9870 regs[i].dirty&=~(1<<hr);
9871 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9872 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9873 regs[i].wasconst&=~(1<<hr);
9874 regs[i].isconst&=~(1<<hr);
9875 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9876 branch_regs[i].wasdirty&=~(1<<hr);
9877 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9878 branch_regs[i].regmap[hr]=f_regmap[hr];
9879 branch_regs[i].dirty&=~(1<<hr);
9880 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9881 branch_regs[i].wasconst&=~(1<<hr);
9882 branch_regs[i].isconst&=~(1<<hr);
9883 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9884 regmap_pre[i+2][hr]=f_regmap[hr];
9885 regs[i+2].wasdirty&=~(1<<hr);
9886 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9887 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9888 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9889 }
9890 }
9891 }
9892 for(k=t;k<j;k++) {
9893 regs[k].regmap_entry[hr]=f_regmap[hr];
9894 regs[k].regmap[hr]=f_regmap[hr];
9895 regmap_pre[k+1][hr]=f_regmap[hr];
9896 regs[k+1].wasdirty&=~(1<<hr);
9897 regs[k].dirty&=~(1<<hr);
9898 regs[k].wasconst&=~(1<<hr);
9899 regs[k].isconst&=~(1<<hr);
9900 }
9901 if(regs[j].regmap[hr]==f_regmap[hr])
9902 regs[j].regmap_entry[hr]=f_regmap[hr];
9903 break;
9904 }
9905 if(j==i) break;
9906 if(regs[j].regmap[hr]>=0)
9907 break;
9908 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9909 //printf("no-match due to different register\n");
9910 break;
9911 }
9912 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9913 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9914 break;
9915 }
9916 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9917 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9918 ||itype[j]==FCOMP||itype[j]==FCONV
9919 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9920 if(count_free_regs(regs[j].regmap)<2) {
9921 //printf("No free regs for store %x\n",start+j*4);
9922 break;
9923 }
9924 }
9925 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9926 if(f_regmap[hr]>=64) {
9927 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9928 break;
9929 }
9930 else
9931 {
9932 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9933 break;
9934 }
9935 }
9936 }
9937 }
9938 }
9939 }
9940 }
9941 }
9942 }else{
9943 int count=0;
9944 for(hr=0;hr<HOST_REGS;hr++)
9945 {
9946 if(hr!=EXCLUDE_REG) {
9947 if(regs[i].regmap[hr]>64) {
9948 if(!((regs[i].dirty>>hr)&1))
9949 f_regmap[hr]=regs[i].regmap[hr];
9950 }
b372a952 9951 else if(regs[i].regmap[hr]>=0) {
9952 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9953 // dealloc old register
9954 int n;
9955 for(n=0;n<HOST_REGS;n++)
9956 {
9957 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9958 }
9959 // and alloc new one
9960 f_regmap[hr]=regs[i].regmap[hr];
9961 }
9962 }
57871462 9963 else if(regs[i].regmap[hr]<0) count++;
9964 }
9965 }
9966 // Try to restore cycle count at branch targets
9967 if(bt[i]) {
9968 for(j=i;j<slen-1;j++) {
9969 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9970 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9971 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9972 ||itype[j]==FCOMP||itype[j]==FCONV
9973 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9974 if(count_free_regs(regs[j].regmap)<2) {
9975 //printf("no free regs for store %x\n",start+j*4);
9976 break;
9977 }
9978 }
9979 else
9980 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9981 }
9982 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9983 int k=i;
9984 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9985 while(k<j) {
9986 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9987 regs[k].regmap[HOST_CCREG]=CCREG;
9988 regmap_pre[k+1][HOST_CCREG]=CCREG;
9989 regs[k+1].wasdirty|=1<<HOST_CCREG;
9990 regs[k].dirty|=1<<HOST_CCREG;
9991 regs[k].wasconst&=~(1<<HOST_CCREG);
9992 regs[k].isconst&=~(1<<HOST_CCREG);
9993 k++;
9994 }
9995 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9996 }
9997 // Work backwards from the branch target
9998 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9999 {
10000 //printf("Extend backwards\n");
10001 int k;
10002 k=i;
10003 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10004 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10005 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
b9b61529 10006 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10007 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 10008 if(count_free_regs(regs[k-1].regmap)<2) {
10009 //printf("no free regs for store %x\n",start+(k-1)*4);
10010 break;
10011 }
10012 }
10013 else
10014 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10015 k--;
10016 }
10017 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10018 //printf("Extend CC, %x ->\n",start+k*4);
10019 while(k<=i) {
10020 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10021 regs[k].regmap[HOST_CCREG]=CCREG;
10022 regmap_pre[k+1][HOST_CCREG]=CCREG;
10023 regs[k+1].wasdirty|=1<<HOST_CCREG;
10024 regs[k].dirty|=1<<HOST_CCREG;
10025 regs[k].wasconst&=~(1<<HOST_CCREG);
10026 regs[k].isconst&=~(1<<HOST_CCREG);
10027 k++;
10028 }
10029 }
10030 else {
10031 //printf("Fail Extend CC, %x ->\n",start+k*4);
10032 }
10033 }
10034 }
10035 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10036 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10037 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
b9b61529 10038 itype[i]!=FCONV&&itype[i]!=FCOMP&&
10039 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
57871462 10040 {
10041 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10042 }
10043 }
10044 }
10045
10046 // This allocates registers (if possible) one instruction prior
10047 // to use, which can avoid a load-use penalty on certain CPUs.
10048 for(i=0;i<slen-1;i++)
10049 {
10050 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10051 {
10052 if(!bt[i+1])
10053 {
b9b61529 10054 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10055 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10056 {
10057 if(rs1[i+1]) {
10058 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10059 {
10060 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10061 {
10062 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10063 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10064 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10065 regs[i].isconst&=~(1<<hr);
10066 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10067 constmap[i][hr]=constmap[i+1][hr];
10068 regs[i+1].wasdirty&=~(1<<hr);
10069 regs[i].dirty&=~(1<<hr);
10070 }
10071 }
10072 }
10073 if(rs2[i+1]) {
10074 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10075 {
10076 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10077 {
10078 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10079 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10080 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10081 regs[i].isconst&=~(1<<hr);
10082 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10083 constmap[i][hr]=constmap[i+1][hr];
10084 regs[i+1].wasdirty&=~(1<<hr);
10085 regs[i].dirty&=~(1<<hr);
10086 }
10087 }
10088 }
10089 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10090 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10091 {
10092 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10093 {
10094 regs[i].regmap[hr]=rs1[i+1];
10095 regmap_pre[i+1][hr]=rs1[i+1];
10096 regs[i+1].regmap_entry[hr]=rs1[i+1];
10097 regs[i].isconst&=~(1<<hr);
10098 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10099 constmap[i][hr]=constmap[i+1][hr];
10100 regs[i+1].wasdirty&=~(1<<hr);
10101 regs[i].dirty&=~(1<<hr);
10102 }
10103 }
10104 }
10105 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10106 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10107 {
10108 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10109 {
10110 regs[i].regmap[hr]=rs1[i+1];
10111 regmap_pre[i+1][hr]=rs1[i+1];
10112 regs[i+1].regmap_entry[hr]=rs1[i+1];
10113 regs[i].isconst&=~(1<<hr);
10114 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10115 constmap[i][hr]=constmap[i+1][hr];
10116 regs[i+1].wasdirty&=~(1<<hr);
10117 regs[i].dirty&=~(1<<hr);
10118 }
10119 }
10120 }
10121 #ifndef HOST_IMM_ADDR32
b9b61529 10122 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10123 hr=get_reg(regs[i+1].regmap,TLREG);
10124 if(hr>=0) {
10125 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10126 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10127 int nr;
10128 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10129 {
10130 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10131 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10132 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10133 regs[i].isconst&=~(1<<hr);
10134 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10135 constmap[i][hr]=constmap[i+1][hr];
10136 regs[i+1].wasdirty&=~(1<<hr);
10137 regs[i].dirty&=~(1<<hr);
10138 }
10139 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10140 {
10141 // move it to another register
10142 regs[i+1].regmap[hr]=-1;
10143 regmap_pre[i+2][hr]=-1;
10144 regs[i+1].regmap[nr]=TLREG;
10145 regmap_pre[i+2][nr]=TLREG;
10146 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10147 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10148 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10149 regs[i].isconst&=~(1<<nr);
10150 regs[i+1].isconst&=~(1<<nr);
10151 regs[i].dirty&=~(1<<nr);
10152 regs[i+1].wasdirty&=~(1<<nr);
10153 regs[i+1].dirty&=~(1<<nr);
10154 regs[i+2].wasdirty&=~(1<<nr);
10155 }
10156 }
10157 }
10158 }
10159 #endif
b9b61529 10160 if(itype[i+1]==STORE||itype[i+1]==STORELR
10161 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10162 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10163 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10164 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10165 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10166 assert(hr>=0);
10167 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10168 {
10169 regs[i].regmap[hr]=rs1[i+1];
10170 regmap_pre[i+1][hr]=rs1[i+1];
10171 regs[i+1].regmap_entry[hr]=rs1[i+1];
10172 regs[i].isconst&=~(1<<hr);
10173 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10174 constmap[i][hr]=constmap[i+1][hr];
10175 regs[i+1].wasdirty&=~(1<<hr);
10176 regs[i].dirty&=~(1<<hr);
10177 }
10178 }
10179 }
b9b61529 10180 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10181 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10182 int nr;
10183 hr=get_reg(regs[i+1].regmap,FTEMP);
10184 assert(hr>=0);
10185 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10186 {
10187 regs[i].regmap[hr]=rs1[i+1];
10188 regmap_pre[i+1][hr]=rs1[i+1];
10189 regs[i+1].regmap_entry[hr]=rs1[i+1];
10190 regs[i].isconst&=~(1<<hr);
10191 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10192 constmap[i][hr]=constmap[i+1][hr];
10193 regs[i+1].wasdirty&=~(1<<hr);
10194 regs[i].dirty&=~(1<<hr);
10195 }
10196 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10197 {
10198 // move it to another register
10199 regs[i+1].regmap[hr]=-1;
10200 regmap_pre[i+2][hr]=-1;
10201 regs[i+1].regmap[nr]=FTEMP;
10202 regmap_pre[i+2][nr]=FTEMP;
10203 regs[i].regmap[nr]=rs1[i+1];
10204 regmap_pre[i+1][nr]=rs1[i+1];
10205 regs[i+1].regmap_entry[nr]=rs1[i+1];
10206 regs[i].isconst&=~(1<<nr);
10207 regs[i+1].isconst&=~(1<<nr);
10208 regs[i].dirty&=~(1<<nr);
10209 regs[i+1].wasdirty&=~(1<<nr);
10210 regs[i+1].dirty&=~(1<<nr);
10211 regs[i+2].wasdirty&=~(1<<nr);
10212 }
10213 }
10214 }
b9b61529 10215 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10216 if(itype[i+1]==LOAD)
10217 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10218 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10219 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10220 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10221 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10222 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10223 }
10224 if(hr>=0&&regs[i].regmap[hr]<0) {
10225 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10226 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10227 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10228 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10229 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10230 regs[i].isconst&=~(1<<hr);
10231 regs[i+1].wasdirty&=~(1<<hr);
10232 regs[i].dirty&=~(1<<hr);
10233 }
10234 }
10235 }
10236 }
10237 }
10238 }
10239 }
10240
10241 /* Pass 6 - Optimize clean/dirty state */
10242 clean_registers(0,slen-1,1);
10243
10244 /* Pass 7 - Identify 32-bit registers */
10245
10246 provisional_r32();
10247
10248 u_int r32=0;
10249
10250 for (i=slen-1;i>=0;i--)
10251 {
10252 int hr;
10253 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10254 {
10255 if(ba[i]<start || ba[i]>=(start+slen*4))
10256 {
10257 // Branch out of this block, don't need anything
10258 r32=0;
10259 }
10260 else
10261 {
10262 // Internal branch
10263 // Need whatever matches the target
10264 // (and doesn't get overwritten by the delay slot instruction)
10265 r32=0;
10266 int t=(ba[i]-start)>>2;
10267 if(ba[i]>start+i*4) {
10268 // Forward branch
10269 if(!(requires_32bit[t]&~regs[i].was32))
10270 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10271 }else{
10272 // Backward branch
10273 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10274 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10275 if(!(pr32[t]&~regs[i].was32))
10276 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10277 }
10278 }
10279 // Conditional branch may need registers for following instructions
10280 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10281 {
10282 if(i<slen-2) {
10283 r32|=requires_32bit[i+2];
10284 r32&=regs[i].was32;
10285 // Mark this address as a branch target since it may be called
10286 // upon return from interrupt
10287 bt[i+2]=1;
10288 }
10289 }
10290 // Merge in delay slot
10291 if(!likely[i]) {
10292 // These are overwritten unless the branch is "likely"
10293 // and the delay slot is nullified if not taken
10294 r32&=~(1LL<<rt1[i+1]);
10295 r32&=~(1LL<<rt2[i+1]);
10296 }
10297 // Assume these are needed (delay slot)
10298 if(us1[i+1]>0)
10299 {
10300 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10301 }
10302 if(us2[i+1]>0)
10303 {
10304 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10305 }
10306 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10307 {
10308 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10309 }
10310 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10311 {
10312 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10313 }
10314 }
1e973cb0 10315 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10316 {
10317 // SYSCALL instruction (software interrupt)
10318 r32=0;
10319 }
10320 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10321 {
10322 // ERET instruction (return from interrupt)
10323 r32=0;
10324 }
10325 // Check 32 bits
10326 r32&=~(1LL<<rt1[i]);
10327 r32&=~(1LL<<rt2[i]);
10328 if(us1[i]>0)
10329 {
10330 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10331 }
10332 if(us2[i]>0)
10333 {
10334 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10335 }
10336 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10337 {
10338 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10339 }
10340 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10341 {
10342 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10343 }
10344 requires_32bit[i]=r32;
10345
10346 // Dirty registers which are 32-bit, require 32-bit input
10347 // as they will be written as 32-bit values
10348 for(hr=0;hr<HOST_REGS;hr++)
10349 {
10350 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10351 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10352 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10353 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10354 }
10355 }
10356 }
10357 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10358 }
10359
10360 if(itype[slen-1]==SPAN) {
10361 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10362 }
10363
10364 /* Debug/disassembly */
10365 if((void*)assem_debug==(void*)printf)
10366 for(i=0;i<slen;i++)
10367 {
10368 printf("U:");
10369 int r;
10370 for(r=1;r<=CCREG;r++) {
10371 if((unneeded_reg[i]>>r)&1) {
10372 if(r==HIREG) printf(" HI");
10373 else if(r==LOREG) printf(" LO");
10374 else printf(" r%d",r);
10375 }
10376 }
90ae6d4e 10377#ifndef FORCE32
57871462 10378 printf(" UU:");
10379 for(r=1;r<=CCREG;r++) {
10380 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10381 if(r==HIREG) printf(" HI");
10382 else if(r==LOREG) printf(" LO");
10383 else printf(" r%d",r);
10384 }
10385 }
10386 printf(" 32:");
10387 for(r=0;r<=CCREG;r++) {
10388 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10389 if((regs[i].was32>>r)&1) {
10390 if(r==CCREG) printf(" CC");
10391 else if(r==HIREG) printf(" HI");
10392 else if(r==LOREG) printf(" LO");
10393 else printf(" r%d",r);
10394 }
10395 }
90ae6d4e 10396#endif
57871462 10397 printf("\n");
10398 #if defined(__i386__) || defined(__x86_64__)
10399 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10400 #endif
10401 #ifdef __arm__
10402 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10403 #endif
10404 printf("needs: ");
10405 if(needed_reg[i]&1) printf("eax ");
10406 if((needed_reg[i]>>1)&1) printf("ecx ");
10407 if((needed_reg[i]>>2)&1) printf("edx ");
10408 if((needed_reg[i]>>3)&1) printf("ebx ");
10409 if((needed_reg[i]>>5)&1) printf("ebp ");
10410 if((needed_reg[i]>>6)&1) printf("esi ");
10411 if((needed_reg[i]>>7)&1) printf("edi ");
10412 printf("r:");
10413 for(r=0;r<=CCREG;r++) {
10414 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10415 if((requires_32bit[i]>>r)&1) {
10416 if(r==CCREG) printf(" CC");
10417 else if(r==HIREG) printf(" HI");
10418 else if(r==LOREG) printf(" LO");
10419 else printf(" r%d",r);
10420 }
10421 }
10422 printf("\n");
10423 /*printf("pr:");
10424 for(r=0;r<=CCREG;r++) {
10425 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10426 if((pr32[i]>>r)&1) {
10427 if(r==CCREG) printf(" CC");
10428 else if(r==HIREG) printf(" HI");
10429 else if(r==LOREG) printf(" LO");
10430 else printf(" r%d",r);
10431 }
10432 }
10433 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10434 printf("\n");*/
10435 #if defined(__i386__) || defined(__x86_64__)
10436 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10437 printf("dirty: ");
10438 if(regs[i].wasdirty&1) printf("eax ");
10439 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10440 if((regs[i].wasdirty>>2)&1) printf("edx ");
10441 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10442 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10443 if((regs[i].wasdirty>>6)&1) printf("esi ");
10444 if((regs[i].wasdirty>>7)&1) printf("edi ");
10445 #endif
10446 #ifdef __arm__
10447 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10448 printf("dirty: ");
10449 if(regs[i].wasdirty&1) printf("r0 ");
10450 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10451 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10452 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10453 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10454 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10455 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10456 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10457 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10458 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10459 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10460 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10461 #endif
10462 printf("\n");
10463 disassemble_inst(i);
10464 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10465 #if defined(__i386__) || defined(__x86_64__)
10466 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10467 if(regs[i].dirty&1) printf("eax ");
10468 if((regs[i].dirty>>1)&1) printf("ecx ");
10469 if((regs[i].dirty>>2)&1) printf("edx ");
10470 if((regs[i].dirty>>3)&1) printf("ebx ");
10471 if((regs[i].dirty>>5)&1) printf("ebp ");
10472 if((regs[i].dirty>>6)&1) printf("esi ");
10473 if((regs[i].dirty>>7)&1) printf("edi ");
10474 #endif
10475 #ifdef __arm__
10476 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10477 if(regs[i].dirty&1) printf("r0 ");
10478 if((regs[i].dirty>>1)&1) printf("r1 ");
10479 if((regs[i].dirty>>2)&1) printf("r2 ");
10480 if((regs[i].dirty>>3)&1) printf("r3 ");
10481 if((regs[i].dirty>>4)&1) printf("r4 ");
10482 if((regs[i].dirty>>5)&1) printf("r5 ");
10483 if((regs[i].dirty>>6)&1) printf("r6 ");
10484 if((regs[i].dirty>>7)&1) printf("r7 ");
10485 if((regs[i].dirty>>8)&1) printf("r8 ");
10486 if((regs[i].dirty>>9)&1) printf("r9 ");
10487 if((regs[i].dirty>>10)&1) printf("r10 ");
10488 if((regs[i].dirty>>12)&1) printf("r12 ");
10489 #endif
10490 printf("\n");
10491 if(regs[i].isconst) {
10492 printf("constants: ");
10493 #if defined(__i386__) || defined(__x86_64__)
10494 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10495 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10496 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10497 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10498 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10499 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10500 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10501 #endif
10502 #ifdef __arm__
10503 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10504 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10505 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10506 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10507 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10508 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10509 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10510 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10511 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10512 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10513 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10514 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10515 #endif
10516 printf("\n");
10517 }
90ae6d4e 10518#ifndef FORCE32
57871462 10519 printf(" 32:");
10520 for(r=0;r<=CCREG;r++) {
10521 if((regs[i].is32>>r)&1) {
10522 if(r==CCREG) printf(" CC");
10523 else if(r==HIREG) printf(" HI");
10524 else if(r==LOREG) printf(" LO");
10525 else printf(" r%d",r);
10526 }
10527 }
10528 printf("\n");
90ae6d4e 10529#endif
57871462 10530 /*printf(" p32:");
10531 for(r=0;r<=CCREG;r++) {
10532 if((p32[i]>>r)&1) {
10533 if(r==CCREG) printf(" CC");
10534 else if(r==HIREG) printf(" HI");
10535 else if(r==LOREG) printf(" LO");
10536 else printf(" r%d",r);
10537 }
10538 }
10539 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10540 else printf("\n");*/
10541 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10542 #if defined(__i386__) || defined(__x86_64__)
10543 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10544 if(branch_regs[i].dirty&1) printf("eax ");
10545 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10546 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10547 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10548 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10549 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10550 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10551 #endif
10552 #ifdef __arm__
10553 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10554 if(branch_regs[i].dirty&1) printf("r0 ");
10555 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10556 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10557 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10558 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10559 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10560 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10561 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10562 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10563 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10564 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10565 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10566 #endif
90ae6d4e 10567#ifndef FORCE32
57871462 10568 printf(" 32:");
10569 for(r=0;r<=CCREG;r++) {
10570 if((branch_regs[i].is32>>r)&1) {
10571 if(r==CCREG) printf(" CC");
10572 else if(r==HIREG) printf(" HI");
10573 else if(r==LOREG) printf(" LO");
10574 else printf(" r%d",r);
10575 }
10576 }
10577 printf("\n");
90ae6d4e 10578#endif
57871462 10579 }
10580 }
10581
10582 /* Pass 8 - Assembly */
10583 linkcount=0;stubcount=0;
10584 ds=0;is_delayslot=0;
10585 cop1_usable=0;
10586 uint64_t is32_pre=0;
10587 u_int dirty_pre=0;
10588 u_int beginning=(u_int)out;
10589 if((u_int)addr&1) {
10590 ds=1;
10591 pagespan_ds();
10592 }
9ad4d757 10593 u_int instr_addr0_override=0;
10594
10595#ifdef PCSX
10596 if (start == 0x80030000) {
10597 // nasty hack for fastbios thing
10598 instr_addr0_override=(u_int)out;
10599 emit_movimm(start,0);
10600 emit_readword((int)&pcaddr,1);
10601 emit_writeword(0,(int)&pcaddr);
10602 emit_cmp(0,1);
10603 emit_jne((int)new_dyna_leave);
10604 }
10605#endif
57871462 10606 for(i=0;i<slen;i++)
10607 {
10608 //if(ds) printf("ds: ");
10609 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10610 if(ds) {
10611 ds=0; // Skip delay slot
10612 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10613 instr_addr[i]=0;
10614 } else {
10615 #ifndef DESTRUCTIVE_WRITEBACK
10616 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10617 {
10618 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10619 unneeded_reg[i],unneeded_reg_upper[i]);
10620 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10621 unneeded_reg[i],unneeded_reg_upper[i]);
10622 }
10623 is32_pre=regs[i].is32;
10624 dirty_pre=regs[i].dirty;
10625 #endif
10626 // write back
10627 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10628 {
10629 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10630 unneeded_reg[i],unneeded_reg_upper[i]);
10631 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10632 }
10633 // branch target entry point
10634 instr_addr[i]=(u_int)out;
10635 assem_debug("<->\n");
10636 // load regs
10637 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10638 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10639 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10640 address_generation(i,&regs[i],regs[i].regmap_entry);
10641 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10642 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10643 {
10644 // Load the delay slot registers if necessary
10645 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10646 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10647 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10648 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10649 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10650 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10651 }
10652 else if(i+1<slen)
10653 {
10654 // Preload registers for following instruction
10655 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10656 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10657 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10658 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10659 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10660 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10661 }
10662 // TODO: if(is_ooo(i)) address_generation(i+1);
10663 if(itype[i]==CJUMP||itype[i]==FJUMP)
10664 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10665 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10666 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10667 if(bt[i]) cop1_usable=0;
10668 // assemble
10669 switch(itype[i]) {
10670 case ALU:
10671 alu_assemble(i,&regs[i]);break;
10672 case IMM16:
10673 imm16_assemble(i,&regs[i]);break;
10674 case SHIFT:
10675 shift_assemble(i,&regs[i]);break;
10676 case SHIFTIMM:
10677 shiftimm_assemble(i,&regs[i]);break;
10678 case LOAD:
10679 load_assemble(i,&regs[i]);break;
10680 case LOADLR:
10681 loadlr_assemble(i,&regs[i]);break;
10682 case STORE:
10683 store_assemble(i,&regs[i]);break;
10684 case STORELR:
10685 storelr_assemble(i,&regs[i]);break;
10686 case COP0:
10687 cop0_assemble(i,&regs[i]);break;
10688 case COP1:
10689 cop1_assemble(i,&regs[i]);break;
10690 case C1LS:
10691 c1ls_assemble(i,&regs[i]);break;
b9b61529 10692 case COP2:
10693 cop2_assemble(i,&regs[i]);break;
10694 case C2LS:
10695 c2ls_assemble(i,&regs[i]);break;
10696 case C2OP:
10697 c2op_assemble(i,&regs[i]);break;
57871462 10698 case FCONV:
10699 fconv_assemble(i,&regs[i]);break;
10700 case FLOAT:
10701 float_assemble(i,&regs[i]);break;
10702 case FCOMP:
10703 fcomp_assemble(i,&regs[i]);break;
10704 case MULTDIV:
10705 multdiv_assemble(i,&regs[i]);break;
10706 case MOV:
10707 mov_assemble(i,&regs[i]);break;
10708 case SYSCALL:
10709 syscall_assemble(i,&regs[i]);break;
7139f3c8 10710 case HLECALL:
10711 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10712 case INTCALL:
10713 intcall_assemble(i,&regs[i]);break;
57871462 10714 case UJUMP:
10715 ujump_assemble(i,&regs[i]);ds=1;break;
10716 case RJUMP:
10717 rjump_assemble(i,&regs[i]);ds=1;break;
10718 case CJUMP:
10719 cjump_assemble(i,&regs[i]);ds=1;break;
10720 case SJUMP:
10721 sjump_assemble(i,&regs[i]);ds=1;break;
10722 case FJUMP:
10723 fjump_assemble(i,&regs[i]);ds=1;break;
10724 case SPAN:
10725 pagespan_assemble(i,&regs[i]);break;
10726 }
10727 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10728 literal_pool(1024);
10729 else
10730 literal_pool_jumpover(256);
10731 }
10732 }
10733 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10734 // If the block did not end with an unconditional branch,
10735 // add a jump to the next instruction.
10736 if(i>1) {
10737 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10738 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10739 assert(i==slen);
10740 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10741 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10742 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10743 emit_loadreg(CCREG,HOST_CCREG);
10744 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10745 }
10746 else if(!likely[i-2])
10747 {
10748 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10749 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10750 }
10751 else
10752 {
10753 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10754 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10755 }
10756 add_to_linker((int)out,start+i*4,0);
10757 emit_jmp(0);
10758 }
10759 }
10760 else
10761 {
10762 assert(i>0);
10763 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10764 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10765 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10766 emit_loadreg(CCREG,HOST_CCREG);
10767 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10768 add_to_linker((int)out,start+i*4,0);
10769 emit_jmp(0);
10770 }
10771
10772 // TODO: delay slot stubs?
10773 // Stubs
10774 for(i=0;i<stubcount;i++)
10775 {
10776 switch(stubs[i][0])
10777 {
10778 case LOADB_STUB:
10779 case LOADH_STUB:
10780 case LOADW_STUB:
10781 case LOADD_STUB:
10782 case LOADBU_STUB:
10783 case LOADHU_STUB:
10784 do_readstub(i);break;
10785 case STOREB_STUB:
10786 case STOREH_STUB:
10787 case STOREW_STUB:
10788 case STORED_STUB:
10789 do_writestub(i);break;
10790 case CC_STUB:
10791 do_ccstub(i);break;
10792 case INVCODE_STUB:
10793 do_invstub(i);break;
10794 case FP_STUB:
10795 do_cop1stub(i);break;
10796 case STORELR_STUB:
10797 do_unalignedwritestub(i);break;
10798 }
10799 }
10800
9ad4d757 10801 if (instr_addr0_override)
10802 instr_addr[0] = instr_addr0_override;
10803
57871462 10804 /* Pass 9 - Linker */
10805 for(i=0;i<linkcount;i++)
10806 {
10807 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10808 literal_pool(64);
10809 if(!link_addr[i][2])
10810 {
10811 void *stub=out;
10812 void *addr=check_addr(link_addr[i][1]);
10813 emit_extjump(link_addr[i][0],link_addr[i][1]);
10814 if(addr) {
10815 set_jump_target(link_addr[i][0],(int)addr);
10816 add_link(link_addr[i][1],stub);
10817 }
10818 else set_jump_target(link_addr[i][0],(int)stub);
10819 }
10820 else
10821 {
10822 // Internal branch
10823 int target=(link_addr[i][1]-start)>>2;
10824 assert(target>=0&&target<slen);
10825 assert(instr_addr[target]);
10826 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10827 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10828 //#else
10829 set_jump_target(link_addr[i][0],instr_addr[target]);
10830 //#endif
10831 }
10832 }
10833 // External Branch Targets (jump_in)
10834 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10835 for(i=0;i<slen;i++)
10836 {
10837 if(bt[i]||i==0)
10838 {
10839 if(instr_addr[i]) // TODO - delay slots (=null)
10840 {
10841 u_int vaddr=start+i*4;
94d23bb9 10842 u_int page=get_page(vaddr);
10843 u_int vpage=get_vpage(vaddr);
57871462 10844 literal_pool(256);
10845 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10846 if(!requires_32bit[i])
10847 {
10848 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10849 assem_debug("jump_in: %x\n",start+i*4);
10850 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10851 int entry_point=do_dirty_stub(i);
10852 ll_add(jump_in+page,vaddr,(void *)entry_point);
10853 // If there was an existing entry in the hash table,
10854 // replace it with the new address.
10855 // Don't add new entries. We'll insert the
10856 // ones that actually get used in check_addr().
10857 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10858 if(ht_bin[0]==vaddr) {
10859 ht_bin[1]=entry_point;
10860 }
10861 if(ht_bin[2]==vaddr) {
10862 ht_bin[3]=entry_point;
10863 }
10864 }
10865 else
10866 {
10867 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10868 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10869 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10870 //int entry_point=(int)out;
10871 ////assem_debug("entry_point: %x\n",entry_point);
10872 //load_regs_entry(i);
10873 //if(entry_point==(int)out)
10874 // entry_point=instr_addr[i];
10875 //else
10876 // emit_jmp(instr_addr[i]);
10877 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10878 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10879 int entry_point=do_dirty_stub(i);
10880 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10881 }
10882 }
10883 }
10884 }
10885 // Write out the literal pool if necessary
10886 literal_pool(0);
10887 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10888 // Align code
10889 if(((u_int)out)&7) emit_addnop(13);
10890 #endif
10891 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10892 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10893 memcpy(copy,source,slen*4);
10894 copy+=slen*4;
10895
10896 #ifdef __arm__
10897 __clear_cache((void *)beginning,out);
10898 #endif
10899
10900 // If we're within 256K of the end of the buffer,
10901 // start over from the beginning. (Is 256K enough?)
10902 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10903
10904 // Trap writes to any of the pages we compiled
10905 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10906 invalid_code[i]=0;
90ae6d4e 10907#ifndef DISABLE_TLB
57871462 10908 memory_map[i]|=0x40000000;
10909 if((signed int)start>=(signed int)0xC0000000) {
10910 assert(using_tlb);
10911 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10912 invalid_code[j]=0;
10913 memory_map[j]|=0x40000000;
10914 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10915 }
90ae6d4e 10916#endif
57871462 10917 }
10918
10919 /* Pass 10 - Free memory by expiring oldest blocks */
10920
10921 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10922 while(expirep!=end)
10923 {
10924 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10925 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10926 inv_debug("EXP: Phase %d\n",expirep);
10927 switch((expirep>>11)&3)
10928 {
10929 case 0:
10930 // Clear jump_in and jump_dirty
10931 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10932 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10933 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10934 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10935 break;
10936 case 1:
10937 // Clear pointers
10938 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10939 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10940 break;
10941 case 2:
10942 // Clear hash table
10943 for(i=0;i<32;i++) {
10944 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10945 if((ht_bin[3]>>shift)==(base>>shift) ||
10946 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10947 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10948 ht_bin[2]=ht_bin[3]=-1;
10949 }
10950 if((ht_bin[1]>>shift)==(base>>shift) ||
10951 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10952 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10953 ht_bin[0]=ht_bin[2];
10954 ht_bin[1]=ht_bin[3];
10955 ht_bin[2]=ht_bin[3]=-1;
10956 }
10957 }
10958 break;
10959 case 3:
10960 // Clear jump_out
57871462 10961 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10962 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10963 break;
10964 }
10965 expirep=(expirep+1)&65535;
10966 }
10967 return 0;
10968}
b9b61529 10969
10970// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork