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drc: lots of new debug code
[picodrive.git] / cpu / sh2 / compiler.c
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e898de13 1/*
cff531af 2 * SH2 recompiler
3 * (C) notaz, 2009,2010
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
44e6452e 7 *
8 * notes:
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
9bb5d91c 11 * - jumps between blocks are tracked for SMC handling (in block_links[]),
12 * except jumps between different tcaches
04092e32 13 * - non-main block entries are called subblocks, as they have same tracking
14 * structures that main blocks have.
9bb5d91c 15 *
16 * implemented:
17 * - static register allocation
18 * - remaining register caching and tracking in temporaries
19 * - block-local branch linking
20 * - block linking (except between tcaches)
23686515 21 * - some constant propagation
9bb5d91c 22 *
23 * TODO:
23686515 24 * - better constant propagation
9bb5d91c 25 * - stack caching?
26 * - bug fixing
e898de13 27 */
f0d7b1fa 28#include <stddef.h>
679af8a3 29#include <stdio.h>
30#include <stdlib.h>
31#include <assert.h>
41397701 32
f4bb5d6b 33#include "../../pico/pico_int.h"
679af8a3 34#include "sh2.h"
35#include "compiler.h"
36#include "../drc/cmn.h"
5686d931 37#include "../debug.h"
679af8a3 38
23686515 39// features
40#define PROPAGATE_CONSTANTS 1
41#define LINK_BRANCHES 1
42
04092e32 43// limits (per block)
04092e32 44#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
45
23686515 46// max literal offset from the block end
47#define MAX_LITERAL_OFFSET 32*2
04092e32 48#define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
49#define MAX_LOCAL_BRANCHES 32
23686515 50
00faec9c 51///
52#define FETCH_OP(pc) \
53 dr_pc_base[(pc) / 2]
54
55#define FETCH32(a) \
56 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
57
58#ifdef DRC_SH2
59
60// debug stuff
61// 1 - ?
62// 2 - ?
63// 4 - log asm
64// {
e898de13 65#ifndef DRC_DEBUG
66#define DRC_DEBUG 0
67#endif
68
553c3eaa 69#if DRC_DEBUG
f4bb5d6b 70#define dbg(l,...) { \
71 if ((l) & DRC_DEBUG) \
72 elprintf(EL_STATUS, ##__VA_ARGS__); \
73}
74
e898de13 75#include "mame/sh2dasm.h"
009ef50c 76#include <platform/libpicofe/linux/host_dasm.h>
e898de13 77static int insns_compiled, hash_collisions, host_insn_count;
553c3eaa 78#define COUNT_OP \
79 host_insn_count++
80#else // !DRC_DEBUG
81#define COUNT_OP
82#define dbg(...)
e898de13 83#endif
553c3eaa 84
fcdefcf6 85#if (DRC_DEBUG & 4)
f4bb5d6b 86static u8 *tcache_dsm_ptrs[3];
e898de13 87static char sh2dasm_buff[64];
f4bb5d6b 88#define do_host_disasm(tcid) \
89 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
90 tcache_dsm_ptrs[tcid] = tcache_ptr
91#else
92#define do_host_disasm(x)
e898de13 93#endif
e05b81fc 94
fcdefcf6 95#if (DRC_DEBUG & 8) || defined(PDB)
5686d931 96static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
e05b81fc 97{
5686d931 98 if (block != NULL) {
fcdefcf6 99 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
e05b81fc 100 sh2->pc, block, (signed int)sr >> 12);
5686d931 101 pdb_step(sh2, sh2->pc);
102 }
e05b81fc 103 return block;
104}
105#endif
8796b7ee 106// } debug
e898de13 107
44e6452e 108#define TCACHE_BUFFERS 3
f4bb5d6b 109
110// we have 3 translation cache buffers, split from one drc/cmn buffer.
111// BIOS shares tcache with data array because it's only used for init
112// and can be discarded early
8796b7ee 113// XXX: need to tune sizes
44e6452e 114static const int tcache_sizes[TCACHE_BUFFERS] = {
f4bb5d6b 115 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
116 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
117 DRC_TCACHE_SIZE / 8, // ... slave
118};
679af8a3 119
44e6452e 120static u8 *tcache_bases[TCACHE_BUFFERS];
121static u8 *tcache_ptrs[TCACHE_BUFFERS];
f4bb5d6b 122
123// ptr for code emiters
124static u8 *tcache_ptr;
e898de13 125
44e6452e 126typedef struct block_desc_ {
127 u32 addr; // SH2 PC address
44e6452e 128 void *tcache_ptr; // translated block for above PC
129 struct block_desc_ *next; // next block with the same PC hash
fcdefcf6 130#if (DRC_DEBUG & 2)
44e6452e 131 int refcount;
132#endif
133} block_desc;
134
135typedef struct block_link_ {
136 u32 target_pc;
a2b8c5a5 137 void *jump; // insn address
44e6452e 138// struct block_link_ *next;
139} block_link;
140
141static const int block_max_counts[TCACHE_BUFFERS] = {
142 4*1024,
143 256,
144 256,
145};
146static block_desc *block_tables[TCACHE_BUFFERS];
147static block_link *block_links[TCACHE_BUFFERS];
148static int block_counts[TCACHE_BUFFERS];
149static int block_link_counts[TCACHE_BUFFERS];
150
c18edb34 151// host register tracking
152enum {
153 HR_FREE,
154 HR_CACHED, // 'val' has sh2_reg_e
23686515 155// HR_CONST, // 'val' has a constant
c18edb34 156 HR_TEMP, // reg used for temp storage
157};
158
23686515 159enum {
160 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
161 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
162};
163
c18edb34 164typedef struct {
23686515 165 u32 hreg:5; // "host" reg
166 u32 greg:5; // "guest" reg
167 u32 type:3;
168 u32 flags:3;
169 u32 stamp:16; // kind of a timestamp
c18edb34 170} temp_reg_t;
171
80599a42 172// note: reg_temp[] must have at least the amount of
3863edbd 173// registers used by handlers in worst case (currently 4)
d4d62665 174#ifdef __arm__
65c75cb0 175#include "../drc/emit_arm.c"
176
177static const int reg_map_g2h[] = {
8b4f38f4 178 4, 5, 6, 7,
179 8, -1, -1, -1,
c18edb34 180 -1, -1, -1, -1,
65514d85 181 -1, -1, -1, 9, // r12 .. sp
182 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
183 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
c18edb34 184};
185
186static temp_reg_t reg_temp[] = {
187 { 0, },
188 { 1, },
189 { 12, },
190 { 14, },
191 { 2, },
192 { 3, },
65c75cb0 193};
194
e05b81fc 195#elif defined(__i386__)
e898de13 196#include "../drc/emit_x86.c"
197
65c75cb0 198static const int reg_map_g2h[] = {
8b4f38f4 199 xSI,-1, -1, -1,
c18edb34 200 -1, -1, -1, -1,
201 -1, -1, -1, -1,
202 -1, -1, -1, -1,
8b4f38f4 203 -1, -1, -1, xDI,
c18edb34 204 -1, -1, -1, -1,
205};
206
3863edbd 207// ax, cx, dx are usually temporaries by convention
c18edb34 208static temp_reg_t reg_temp[] = {
209 { xAX, },
3863edbd 210 { xBX, },
c18edb34 211 { xCX, },
212 { xDX, },
65c75cb0 213};
214
e05b81fc 215#else
216#error unsupported arch
65c75cb0 217#endif
218
80599a42 219#define T 0x00000001
220#define S 0x00000002
221#define I 0x000000f0
222#define Q 0x00000100
223#define M 0x00000200
18b94127 224#define T_save 0x00000800
80599a42 225
e05b81fc 226#define I_SHIFT 4
f0d7b1fa 227#define Q_SHIFT 8
228#define M_SHIFT 9
229
f4bb5d6b 230// ROM hash table
679af8a3 231#define MAX_HASH_ENTRIES 1024
232#define HASH_MASK (MAX_HASH_ENTRIES - 1)
f4bb5d6b 233static void **hash_table;
679af8a3 234
18b94127 235#define HASH_FUNC(hash_tab, addr) \
236 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
237
e05b81fc 238static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
239static void (*sh2_drc_dispatcher)(void);
240static void (*sh2_drc_exit)(void);
241static void (*sh2_drc_test_irq)(void);
5686d931 242
243static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
244static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
245static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
e05b81fc 246static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
247static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
248static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
249static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
5686d931 250static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
679af8a3 251
a2b8c5a5 252// address space stuff
a2b8c5a5 253static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
254{
255 int poffs = -1;
256
257 if ((a & ~0x7ff) == 0) {
258 // BIOS
259 poffs = offsetof(SH2, p_bios);
260 *mask = 0x7ff;
261 }
262 else if ((a & 0xfffff000) == 0xc0000000) {
263 // data array
264 poffs = offsetof(SH2, p_da);
265 *mask = 0xfff;
266 }
267 else if ((a & 0xc6000000) == 0x06000000) {
268 // SDRAM
269 poffs = offsetof(SH2, p_sdram);
270 *mask = 0x03ffff;
271 }
272 else if ((a & 0xc6000000) == 0x02000000) {
273 // ROM
274 poffs = offsetof(SH2, p_rom);
275 *mask = 0x3fffff;
276 }
277
278 return poffs;
279}
280
281static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id)
282{
283 *tcache_id = 0;
284
285 // we have full block id tables for data_array and RAM
286 // BIOS goes to data_array table too
287 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
288 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
289 *tcache_id = 1 + is_slave;
290 if (blkid & 1)
291 return &block_tables[*tcache_id][blkid >> 1];
292 }
293 // RAM
294 else if ((pc & 0xc6000000) == 0x06000000) {
295 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
296 if (blkid & 1)
297 return &block_tables[0][blkid >> 1];
298 }
299 // ROM
300 else if ((pc & 0xc6000000) == 0x02000000) {
301 block_desc *bd = HASH_FUNC(hash_table, pc);
302
303 for (; bd != NULL; bd = bd->next)
304 if (bd->addr == pc)
305 return bd;
306 }
307
308 return NULL;
309}
310
311// ---------------------------------------------------------------
312
313// block management
314static void REGPARM(1) flush_tcache(int tcid)
f4bb5d6b 315{
553c3eaa 316 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
f4bb5d6b 317 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
318 block_counts[tcid], block_max_counts[tcid]);
319
320 block_counts[tcid] = 0;
a2b8c5a5 321 block_link_counts[tcid] = 0;
f4bb5d6b 322 tcache_ptrs[tcid] = tcache_bases[tcid];
323 if (tcid == 0) { // ROM, RAM
324 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
325 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
326 }
327 else
328 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
fcdefcf6 329#if (DRC_DEBUG & 4)
f4bb5d6b 330 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
331#endif
332}
333
5686d931 334#if LINK_BRANCHES
44e6452e 335// add block links (tracked branches)
336static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id)
337{
338 block_link *bl = block_links[tcache_id];
339 int cnt = block_link_counts[tcache_id];
340
341 if (cnt >= block_max_counts[tcache_id] * 2) {
fcdefcf6 342 dbg(1, "bl overflow for tcache %d\n", tcache_id);
44e6452e 343 return -1;
344 }
345
346 bl[cnt].target_pc = target_pc;
347 bl[cnt].jump = jump;
348 block_link_counts[tcache_id]++;
349
350 return 0;
351}
5686d931 352#endif
44e6452e 353
a2b8c5a5 354static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id)
679af8a3 355{
356 block_desc *bd;
a2b8c5a5 357 int tcache_id;
358 int *bcount;
359
360 bd = dr_get_bd(addr, is_slave, &tcache_id);
361 if (bd != NULL) {
fcdefcf6 362 dbg(2, "block override for %08x", addr);
a2b8c5a5 363 bd->tcache_ptr = tcache_ptr;
364 *blk_id = bd - block_tables[tcache_id];
365 return bd;
366 }
679af8a3 367
a2b8c5a5 368 bcount = &block_counts[tcache_id];
44e6452e 369 if (*bcount >= block_max_counts[tcache_id]) {
fcdefcf6 370 dbg(1, "bd overflow for tcache %d", tcache_id);
f4bb5d6b 371 return NULL;
44e6452e 372 }
a2b8c5a5 373 if (*bcount == 0)
374 (*bcount)++; // not using descriptor 0
679af8a3 375
f4bb5d6b 376 bd = &block_tables[tcache_id][*bcount];
679af8a3 377 bd->addr = addr;
378 bd->tcache_ptr = tcache_ptr;
f4bb5d6b 379 *blk_id = *bcount;
380 (*bcount)++;
679af8a3 381
18b94127 382 if ((addr & 0xc6000000) == 0x02000000) { // ROM
383 bd->next = HASH_FUNC(hash_table, addr);
384 HASH_FUNC(hash_table, addr) = bd;
fcdefcf6 385#if (DRC_DEBUG & 2)
18b94127 386 if (bd->next != NULL) {
387 printf(" hash collision with %08x\n", bd->next->addr);
388 hash_collisions++;
389 }
390#endif
391 }
392
679af8a3 393 return bd;
394}
395
a2b8c5a5 396static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
397{
398 block_desc *bd = NULL;
399 void *block = NULL;
400
401 bd = dr_get_bd(pc, is_slave, tcache_id);
402 if (bd != NULL)
403 block = bd->tcache_ptr;
404
fcdefcf6 405#if (DRC_DEBUG & 2)
a2b8c5a5 406 if (bd != NULL)
407 bd->refcount++;
408#endif
409 return block;
410}
411
c25d78ee 412static void *dr_failure(void)
413{
414 lprintf("recompilation failed\n");
415 exit(1);
416}
417
a2b8c5a5 418static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id)
419{
420#if LINK_BRANCHES
421 int target_tcache_id;
422 void *target;
423 int ret;
424
425 target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id);
426 if (target_tcache_id == tcache_id) {
427 // allow linking blocks only from local cache
428 ret = dr_add_block_link(pc, tcache_ptr, tcache_id);
429 if (ret < 0)
430 return NULL;
431 }
432 if (target == NULL || target_tcache_id != tcache_id)
433 target = sh2_drc_dispatcher;
434
435 return target;
436#else
437 return sh2_drc_dispatcher;
438#endif
439}
440
441static void dr_link_blocks(void *target, u32 pc, int tcache_id)
442{
443#if LINK_BRANCHES
444 block_link *bl = block_links[tcache_id];
445 int cnt = block_link_counts[tcache_id];
446 int i;
447
448 for (i = 0; i < cnt; i++) {
449 if (bl[i].target_pc == pc) {
fcdefcf6 450 dbg(2, "- link from %p", bl[i].jump);
a2b8c5a5 451 emith_jump_patch(bl[i].jump, target);
452 // XXX: sync ARM caches (old jump should be fine)?
453 }
454 }
455#endif
456}
457
44e6452e 458#define ADD_TO_ARRAY(array, count, item, failcode) \
459 array[count++] = item; \
460 if (count >= ARRAY_SIZE(array)) { \
fcdefcf6 461 dbg(1, "warning: " #array " overflow"); \
44e6452e 462 failcode; \
463 }
464
a2b8c5a5 465static int find_in_array(u32 *array, size_t size, u32 what)
18b94127 466{
467 size_t i;
468 for (i = 0; i < size; i++)
469 if (what == array[i])
470 return i;
471
472 return -1;
473}
679af8a3 474
475// ---------------------------------------------------------------
476
a2b8c5a5 477// register cache / constant propagation stuff
23686515 478typedef enum {
479 RC_GR_READ,
480 RC_GR_WRITE,
481 RC_GR_RMW,
482} rc_gr_mode;
483
484static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
485
486// guest regs with constants
487static u32 dr_gcregs[24];
488// a mask of constant/dirty regs
489static u32 dr_gcregs_mask;
490static u32 dr_gcregs_dirty;
491
a2b8c5a5 492#if PROPAGATE_CONSTANTS
23686515 493static void gconst_new(sh2_reg_e r, u32 val)
494{
23686515 495 int i;
496
497 dr_gcregs_mask |= 1 << r;
498 dr_gcregs_dirty |= 1 << r;
499 dr_gcregs[r] = val;
500
501 // throw away old r that we might have cached
502 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
503 if ((reg_temp[i].type == HR_CACHED) &&
504 reg_temp[i].greg == r) {
505 reg_temp[i].type = HR_FREE;
506 reg_temp[i].flags = 0;
507 }
508 }
23686515 509}
a2b8c5a5 510#endif
23686515 511
512static int gconst_get(sh2_reg_e r, u32 *val)
513{
514 if (dr_gcregs_mask & (1 << r)) {
515 *val = dr_gcregs[r];
516 return 1;
517 }
518 return 0;
519}
520
521static int gconst_check(sh2_reg_e r)
522{
523 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
524 return 1;
525 return 0;
526}
527
528// update hr if dirty, else do nothing
529static int gconst_try_read(int hr, sh2_reg_e r)
530{
531 if (dr_gcregs_dirty & (1 << r)) {
532 emith_move_r_imm(hr, dr_gcregs[r]);
533 dr_gcregs_dirty &= ~(1 << r);
534 return 1;
535 }
536 return 0;
537}
538
539static void gconst_check_evict(sh2_reg_e r)
540{
541 if (dr_gcregs_mask & (1 << r))
542 // no longer cached in reg, make dirty again
543 dr_gcregs_dirty |= 1 << r;
544}
545
546static void gconst_kill(sh2_reg_e r)
547{
548 dr_gcregs_mask &= ~(1 << r);
549 dr_gcregs_dirty &= ~(1 << r);
550}
551
552static void gconst_clean(void)
553{
554 int i;
555
556 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
557 if (dr_gcregs_dirty & (1 << i)) {
558 // using RC_GR_READ here: it will call gconst_try_read,
559 // cache the reg and mark it dirty.
560 rcache_get_reg_(i, RC_GR_READ, 0);
561 }
562}
563
564static void gconst_invalidate(void)
565{
566 dr_gcregs_mask = dr_gcregs_dirty = 0;
567}
568
c18edb34 569static u16 rcache_counter;
570
571static temp_reg_t *rcache_evict(void)
41397701 572{
c18edb34 573 // evict reg with oldest stamp
574 int i, oldest = -1;
575 u16 min_stamp = (u16)-1;
576
577 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
23686515 578 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
579 reg_temp[i].stamp <= min_stamp) {
580 min_stamp = reg_temp[i].stamp;
581 oldest = i;
582 }
c18edb34 583 }
584
585 if (oldest == -1) {
80599a42 586 printf("no registers to evict, aborting\n");
c18edb34 587 exit(1);
588 }
589
590 i = oldest;
23686515 591 if (reg_temp[i].type == HR_CACHED) {
592 if (reg_temp[i].flags & HRF_DIRTY)
593 // writeback
594 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
595 gconst_check_evict(reg_temp[i].greg);
c18edb34 596 }
597
23686515 598 reg_temp[i].type = HR_FREE;
599 reg_temp[i].flags = 0;
c18edb34 600 return &reg_temp[i];
679af8a3 601}
602
23686515 603static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
604{
605 int i = reg_map_g2h[r];
606 if (i != -1) {
607 if (mode != RC_GR_WRITE)
608 gconst_try_read(i, r);
609 }
610 return i;
611}
c18edb34 612
80599a42 613// note: must not be called when doing conditional code
23686515 614static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
679af8a3 615{
c18edb34 616 temp_reg_t *tr;
23686515 617 int i, ret;
c18edb34 618
23686515 619 // maybe statically mapped?
620 ret = get_reg_static(r, mode);
621 if (ret != -1)
622 goto end;
679af8a3 623
c18edb34 624 rcache_counter++;
625
626 // maybe already cached?
23686515 627 // if so, prefer against gconst (they must be in sync)
c18edb34 628 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
23686515 629 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
c18edb34 630 reg_temp[i].stamp = rcache_counter;
631 if (mode != RC_GR_READ)
23686515 632 reg_temp[i].flags |= HRF_DIRTY;
633 ret = reg_temp[i].hreg;
634 goto end;
c18edb34 635 }
679af8a3 636 }
637
c18edb34 638 // use any free reg
639 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
23686515 640 if (reg_temp[i].type == HR_FREE) {
c18edb34 641 tr = &reg_temp[i];
642 goto do_alloc;
643 }
644 }
645
646 tr = rcache_evict();
647
648do_alloc:
23686515 649 tr->type = HR_CACHED;
650 if (do_locking)
651 tr->flags |= HRF_LOCKED;
652 if (mode != RC_GR_READ)
653 tr->flags |= HRF_DIRTY;
654 tr->greg = r;
c18edb34 655 tr->stamp = rcache_counter;
23686515 656 ret = tr->hreg;
657
658 if (mode != RC_GR_WRITE) {
659 if (gconst_check(r)) {
660 if (gconst_try_read(ret, r))
661 tr->flags |= HRF_DIRTY;
662 }
663 else
664 emith_ctx_read(tr->hreg, r * 4);
665 }
666
667end:
668 if (mode != RC_GR_READ)
669 gconst_kill(r);
670
671 return ret;
672}
673
674static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
675{
676 return rcache_get_reg_(r, mode, 1);
679af8a3 677}
678
c18edb34 679static int rcache_get_tmp(void)
679af8a3 680{
c18edb34 681 temp_reg_t *tr;
682 int i;
683
684 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
23686515 685 if (reg_temp[i].type == HR_FREE) {
c18edb34 686 tr = &reg_temp[i];
687 goto do_alloc;
688 }
689
690 tr = rcache_evict();
691
692do_alloc:
693 tr->type = HR_TEMP;
23686515 694 return tr->hreg;
c18edb34 695}
696
80599a42 697static int rcache_get_arg_id(int arg)
698{
699 int i, r = 0;
700 host_arg2reg(r, arg);
701
702 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
23686515 703 if (reg_temp[i].hreg == r)
80599a42 704 break;
705
04092e32 706 if (i == ARRAY_SIZE(reg_temp)) // can't happen
707 exit(1);
80599a42 708
23686515 709 if (reg_temp[i].type == HR_CACHED) {
80599a42 710 // writeback
23686515 711 if (reg_temp[i].flags & HRF_DIRTY)
712 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
713 gconst_check_evict(reg_temp[i].greg);
80599a42 714 }
715 else if (reg_temp[i].type == HR_TEMP) {
716 printf("arg %d reg %d already used, aborting\n", arg, r);
717 exit(1);
718 }
719
23686515 720 reg_temp[i].type = HR_FREE;
721 reg_temp[i].flags = 0;
722
80599a42 723 return i;
724}
725
726// get a reg to be used as function arg
80599a42 727static int rcache_get_tmp_arg(int arg)
728{
729 int id = rcache_get_arg_id(arg);
730 reg_temp[id].type = HR_TEMP;
731
23686515 732 return reg_temp[id].hreg;
80599a42 733}
734
23686515 735// same but caches a reg. RC_GR_READ only.
80599a42 736static int rcache_get_reg_arg(int arg, sh2_reg_e r)
737{
738 int i, srcr, dstr, dstid;
04092e32 739 int dirty = 0, src_dirty = 0;
80599a42 740
741 dstid = rcache_get_arg_id(arg);
23686515 742 dstr = reg_temp[dstid].hreg;
80599a42 743
744 // maybe already statically mapped?
23686515 745 srcr = get_reg_static(r, RC_GR_READ);
80599a42 746 if (srcr != -1)
747 goto do_cache;
748
749 // maybe already cached?
750 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
23686515 751 if ((reg_temp[i].type == HR_CACHED) &&
752 reg_temp[i].greg == r)
80599a42 753 {
23686515 754 srcr = reg_temp[i].hreg;
04092e32 755 if (reg_temp[i].flags & HRF_DIRTY)
756 src_dirty = 1;
80599a42 757 goto do_cache;
758 }
759 }
760
761 // must read
762 srcr = dstr;
23686515 763 if (gconst_check(r)) {
764 if (gconst_try_read(srcr, r))
765 dirty = 1;
766 }
767 else
768 emith_ctx_read(srcr, r * 4);
80599a42 769
770do_cache:
23686515 771 if (dstr != srcr)
80599a42 772 emith_move_r_r(dstr, srcr);
04092e32 773#if 1
774 else
775 dirty |= src_dirty;
776
777 if (dirty)
778 // must clean, callers might want to modify the arg before call
779 emith_ctx_write(dstr, r * 4);
780#else
781 if (dirty)
782 reg_temp[dstid].flags |= HRF_DIRTY;
783#endif
80599a42 784
785 reg_temp[dstid].stamp = ++rcache_counter;
786 reg_temp[dstid].type = HR_CACHED;
23686515 787 reg_temp[dstid].greg = r;
788 reg_temp[dstid].flags |= HRF_LOCKED;
80599a42 789 return dstr;
790}
791
c18edb34 792static void rcache_free_tmp(int hr)
793{
794 int i;
795 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
23686515 796 if (reg_temp[i].hreg == hr)
c18edb34 797 break;
798
80599a42 799 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
c18edb34 800 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
80599a42 801 return;
802 }
803
804 reg_temp[i].type = HR_FREE;
23686515 805 reg_temp[i].flags = 0;
806}
807
808static void rcache_unlock(int hr)
809{
810 int i;
811 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
812 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
813 reg_temp[i].flags &= ~HRF_LOCKED;
814}
815
816static void rcache_unlock_all(void)
817{
818 int i;
819 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
820 reg_temp[i].flags &= ~HRF_LOCKED;
c18edb34 821}
822
80599a42 823static void rcache_clean(void)
c18edb34 824{
825 int i;
23686515 826 gconst_clean();
827
80599a42 828 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
23686515 829 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
c18edb34 830 // writeback
23686515 831 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
832 reg_temp[i].flags &= ~HRF_DIRTY;
c18edb34 833 }
80599a42 834}
835
836static void rcache_invalidate(void)
837{
838 int i;
23686515 839 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
c18edb34 840 reg_temp[i].type = HR_FREE;
23686515 841 reg_temp[i].flags = 0;
842 }
c18edb34 843 rcache_counter = 0;
23686515 844
845 gconst_invalidate();
c18edb34 846}
847
80599a42 848static void rcache_flush(void)
849{
850 rcache_clean();
851 rcache_invalidate();
852}
853
c18edb34 854// ---------------------------------------------------------------
855
23686515 856static int emit_get_rbase_and_offs(u32 a, u32 *offs)
857{
23686515 858 u32 mask = 0;
a2b8c5a5 859 int poffs;
23686515 860 int hr;
861
a2b8c5a5 862 poffs = dr_ctx_get_mem_ptr(a, &mask);
23686515 863 if (poffs == -1)
864 return -1;
865
a2b8c5a5 866 // XXX: could use some related reg
23686515 867 hr = rcache_get_tmp();
868 emith_ctx_read(hr, poffs);
869 emith_add_r_imm(hr, a & mask & ~0xff);
870 *offs = a & 0xff; // XXX: ARM oriented..
871 return hr;
872}
873
c18edb34 874static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
875{
23686515 876#if PROPAGATE_CONSTANTS
877 gconst_new(dst, imm);
878#else
c18edb34 879 int hr = rcache_get_reg(dst, RC_GR_WRITE);
880 emith_move_r_imm(hr, imm);
23686515 881#endif
c18edb34 882}
883
884static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
885{
886 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
887 int hr_s = rcache_get_reg(src, RC_GR_READ);
888
889 emith_move_r_r(hr_d, hr_s);
679af8a3 890}
891
52d759c3 892// T must be clear, and comparison done just before this
893static void emit_or_t_if_eq(int srr)
894{
895 EMITH_SJMP_START(DCOND_NE);
896 emith_or_r_imm_c(DCOND_EQ, srr, T);
897 EMITH_SJMP_END(DCOND_NE);
898}
899
80599a42 900// arguments must be ready
901// reg cache must be clean before call
23686515 902static int emit_memhandler_read_(int size, int ram_check)
679af8a3 903{
b081408f 904 int arg0, arg1;
905 host_arg2reg(arg0, 0);
906
23686515 907 rcache_clean();
908
b081408f 909 // must writeback cycles for poll detection stuff
23686515 910 // FIXME: rm
b081408f 911 if (reg_map_g2h[SHR_SR] != -1)
912 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
23686515 913
b081408f 914 arg1 = rcache_get_tmp_arg(1);
915 emith_move_r_r(arg1, CONTEXT_REG);
916
5686d931 917#ifndef PDB_NET
23686515 918 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
b081408f 919 int tmp = rcache_get_tmp();
920 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
921 emith_cmp_r_imm(tmp, 0x02000000);
922 switch (size) {
923 case 0: // 8
924 EMITH_SJMP3_START(DCOND_NE);
925 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
926 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
927 EMITH_SJMP3_MID(DCOND_NE);
5686d931 928 emith_call_cond(DCOND_NE, sh2_drc_read8);
b081408f 929 EMITH_SJMP3_END();
930 break;
931 case 1: // 16
932 EMITH_SJMP3_START(DCOND_NE);
933 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
934 EMITH_SJMP3_MID(DCOND_NE);
5686d931 935 emith_call_cond(DCOND_NE, sh2_drc_read16);
b081408f 936 EMITH_SJMP3_END();
937 break;
938 case 2: // 32
939 EMITH_SJMP3_START(DCOND_NE);
940 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
941 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
942 EMITH_SJMP3_MID(DCOND_NE);
5686d931 943 emith_call_cond(DCOND_NE, sh2_drc_read32);
b081408f 944 EMITH_SJMP3_END();
945 break;
946 }
947 }
948 else
949#endif
950 {
951 switch (size) {
952 case 0: // 8
5686d931 953 emith_call(sh2_drc_read8);
b081408f 954 break;
955 case 1: // 16
5686d931 956 emith_call(sh2_drc_read16);
b081408f 957 break;
958 case 2: // 32
5686d931 959 emith_call(sh2_drc_read32);
b081408f 960 break;
961 }
679af8a3 962 }
80599a42 963 rcache_invalidate();
97e95a29 964
965 if (reg_map_g2h[SHR_SR] != -1)
966 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
967
80599a42 968 // assuming arg0 and retval reg matches
969 return rcache_get_tmp_arg(0);
970}
679af8a3 971
23686515 972static int emit_memhandler_read(int size)
973{
974 return emit_memhandler_read_(size, 1);
975}
976
977static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
978{
979 int hr, hr2, ram_check = 1;
980 u32 val, offs2;
981
982 if (gconst_get(rs, &val)) {
983 hr = emit_get_rbase_and_offs(val + offs, &offs2);
984 if (hr != -1) {
985 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
986 switch (size) {
987 case 0: // 8
988 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
989 emith_sext(hr2, hr2, 8);
990 break;
991 case 1: // 16
992 emith_read16_r_r_offs(hr2, hr, offs2);
993 emith_sext(hr2, hr2, 16);
994 break;
995 case 2: // 32
996 emith_read_r_r_offs(hr2, hr, offs2);
997 emith_ror(hr2, hr2, 16);
998 break;
999 }
1000 rcache_free_tmp(hr);
1001 return hr2;
1002 }
1003
1004 ram_check = 0;
1005 }
1006
1007 hr = rcache_get_reg_arg(0, rs);
1008 if (offs != 0)
1009 emith_add_r_imm(hr, offs);
1010 hr = emit_memhandler_read_(size, ram_check);
1011 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1012 if (size != 2) {
1013 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1014 } else
1015 emith_move_r_r(hr2, hr);
1016 rcache_free_tmp(hr);
1017
1018 return hr2;
1019}
1020
e05b81fc 1021static void emit_memhandler_write(int size, u32 pc, int delay)
80599a42 1022{
1023 int ctxr;
1024 host_arg2reg(ctxr, 2);
97e95a29 1025 if (reg_map_g2h[SHR_SR] != -1)
1026 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1027
80599a42 1028 switch (size) {
1029 case 0: // 8
e05b81fc 1030 // XXX: consider inlining sh2_drc_write8
1031 if (delay) {
1032 emith_call(sh2_drc_write8_slot);
1033 } else {
1034 emit_move_r_imm32(SHR_PC, pc);
1035 rcache_clean();
1036 emith_call(sh2_drc_write8);
1037 }
80599a42 1038 break;
1039 case 1: // 16
e05b81fc 1040 if (delay) {
1041 emith_call(sh2_drc_write16_slot);
1042 } else {
1043 emit_move_r_imm32(SHR_PC, pc);
1044 rcache_clean();
1045 emith_call(sh2_drc_write16);
1046 }
80599a42 1047 break;
1048 case 2: // 32
e05b81fc 1049 emith_move_r_r(ctxr, CONTEXT_REG);
5686d931 1050 emith_call(sh2_drc_write32);
80599a42 1051 break;
1052 }
97e95a29 1053
1054 if (reg_map_g2h[SHR_SR] != -1)
1055 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
80599a42 1056 rcache_invalidate();
679af8a3 1057}
80599a42 1058
52d759c3 1059// @(Rx,Ry)
1060static int emit_indirect_indexed_read(int rx, int ry, int size)
1061{
1062 int a0, t;
52d759c3 1063 a0 = rcache_get_reg_arg(0, rx);
1064 t = rcache_get_reg(ry, RC_GR_READ);
1065 emith_add_r_r(a0, t);
1066 return emit_memhandler_read(size);
1067}
1068
f0d7b1fa 1069// read @Rn, @rm
1070static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1071{
1072 int tmp;
1073
f0d7b1fa 1074 rcache_get_reg_arg(0, rn);
1075 tmp = emit_memhandler_read(size);
1076 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1077 rcache_free_tmp(tmp);
1078 tmp = rcache_get_reg(rn, RC_GR_RMW);
1079 emith_add_r_imm(tmp, 1 << size);
23686515 1080 rcache_unlock(tmp);
f0d7b1fa 1081
f0d7b1fa 1082 rcache_get_reg_arg(0, rm);
1083 *rmr = emit_memhandler_read(size);
1084 *rnr = rcache_get_tmp();
1085 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1086 tmp = rcache_get_reg(rm, RC_GR_RMW);
1087 emith_add_r_imm(tmp, 1 << size);
23686515 1088 rcache_unlock(tmp);
f0d7b1fa 1089}
1090
8796b7ee 1091static void emit_do_static_regs(int is_write, int tmpr)
f0d7b1fa 1092{
8796b7ee 1093 int i, r, count;
1094
1095 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1096 r = reg_map_g2h[i];
1097 if (r == -1)
1098 continue;
1099
1100 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1101 if (reg_map_g2h[i + 1] != r + 1)
1102 break;
1103 count++;
1104 }
1105
1106 if (count > 1) {
1107 // i, r point to last item
1108 if (is_write)
1109 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1110 else
1111 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1112 } else {
1113 if (is_write)
1114 emith_ctx_write(r, i * 4);
1115 else
1116 emith_ctx_read(r, i * 4);
1117 }
f0d7b1fa 1118 }
1119}
1120
e05b81fc 1121static void emit_block_entry(void)
f0d7b1fa 1122{
c25d78ee 1123 int arg0;
8796b7ee 1124
e05b81fc 1125 host_arg2reg(arg0, 0);
c25d78ee 1126
1127#if (DRC_DEBUG & 8) || defined(PDB)
1128 int arg1, arg2;
e05b81fc 1129 host_arg2reg(arg1, 1);
1130 host_arg2reg(arg2, 2);
8796b7ee 1131
5686d931 1132 emit_do_static_regs(1, arg2);
e05b81fc 1133 emith_move_r_r(arg1, CONTEXT_REG);
1134 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
5686d931 1135 emith_call(sh2_drc_log_entry);
e05b81fc 1136 rcache_invalidate();
1137#endif
1138 emith_tst_r_r(arg0, arg0);
1139 EMITH_SJMP_START(DCOND_EQ);
1140 emith_jump_reg_c(DCOND_NE, arg0);
1141 EMITH_SJMP_END(DCOND_EQ);
1142}
8796b7ee 1143
e898de13 1144#define DELAYED_OP \
18b94127 1145 drcf.delayed_op = 2
1146
1147#define DELAY_SAVE_T(sr) { \
1148 emith_bic_r_imm(sr, T_save); \
1149 emith_tst_r_imm(sr, T); \
1150 EMITH_SJMP_START(DCOND_EQ); \
1151 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1152 EMITH_SJMP_END(DCOND_EQ); \
1153 drcf.use_saved_t = 1; \
1154}
e898de13 1155
e05b81fc 1156#define FLUSH_CYCLES(sr) \
1157 if (cycles > 0) { \
1158 emith_sub_r_imm(sr, cycles << 12); \
1159 cycles = 0; \
1160 }
1161
e898de13 1162#define CHECK_UNHANDLED_BITS(mask) { \
1163 if ((op & (mask)) != 0) \
1164 goto default_; \
1165}
1166
80599a42 1167#define GET_Fx() \
1168 ((op >> 4) & 0x0f)
1169
1170#define GET_Rm GET_Fx
1171
1172#define GET_Rn() \
1173 ((op >> 8) & 0x0f)
1174
ed8cf79b 1175#define CHECK_FX_LT(n) \
52d759c3 1176 if (GET_Fx() >= n) \
80599a42 1177 goto default_
1178
00faec9c 1179static void *dr_get_pc_base(u32 pc, int is_slave);
18b94127 1180
e05b81fc 1181static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
679af8a3 1182{
18b94127 1183 // XXX: maybe use structs instead?
18b94127 1184 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
a2b8c5a5 1185 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1186 int branch_target_blkid[MAX_LOCAL_BRANCHES];
18b94127 1187 int branch_target_count = 0;
1188 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1189 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1190 int branch_patch_count = 0;
04092e32 1191 u32 literal_addr[MAX_LITERALS];
1192 int literal_addr_count = 0;
44e6452e 1193 int pending_branch_cond = -1;
1194 int pending_branch_pc = 0;
00faec9c 1195 u8 op_flags[BLOCK_CYCLE_LIMIT];
18b94127 1196 struct {
1197 u32 delayed_op:2;
1198 u32 test_irq:1;
1199 u32 use_saved_t:1; // delayed op modifies T
1200 } drcf = { 0, };
1201
44e6452e 1202 // PC of current, first, last, last_target_blk SH2 insn
1203 u32 pc, base_pc, end_pc, out_pc;
f4bb5d6b 1204 void *block_entry;
679af8a3 1205 block_desc *this_block;
23686515 1206 u16 *dr_pc_base;
18b94127 1207 int blkid_main = 0;
23686515 1208 int skip_op = 0;
18b94127 1209 u32 tmp, tmp2;
1210 int cycles;
1211 int op;
1212 int i;
1213
1214 base_pc = sh2->pc;
679af8a3 1215
23686515 1216 // get base/validate PC
1217 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1218 if (dr_pc_base == (void *)-1) {
18b94127 1219 printf("invalid PC, aborting: %08x\n", base_pc);
f4bb5d6b 1220 // FIXME: be less destructive
1221 exit(1);
1222 }
1223
f4bb5d6b 1224 tcache_ptr = tcache_ptrs[tcache_id];
a2b8c5a5 1225 this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main);
44e6452e 1226 if (this_block == NULL)
1227 return NULL;
f4bb5d6b 1228
18b94127 1229 // predict tcache overflow
f4bb5d6b 1230 tmp = tcache_ptr - tcache_bases[tcache_id];
44e6452e 1231 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
fcdefcf6 1232 dbg(1, "tcache %d overflow", tcache_id);
18b94127 1233 return NULL;
44e6452e 1234 }
18b94127 1235
1236 block_entry = tcache_ptr;
fcdefcf6 1237 dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
18b94127 1238 tcache_id, blkid_main, base_pc, block_entry);
1239
44e6452e 1240 dr_link_blocks(tcache_ptr, base_pc, tcache_id);
1241
18b94127 1242 // 1st pass: scan forward for local branches
00faec9c 1243 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
1244
1245 // collect branch_targets that don't land on delay slots
1246 for (pc = base_pc; pc <= end_pc; pc += 2) {
1247 if (!(OP_FLAGS(pc) & OF_TARGET))
1248 continue;
1249 if (OP_FLAGS(pc) & OF_DELAY_OP) {
1250 OP_FLAGS(pc) &= ~OF_TARGET;
18b94127 1251 continue;
1252 }
00faec9c 1253 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
e898de13 1254 }
c25d78ee 1255
c25d78ee 1256 if (branch_target_count > 0) {
1257 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1258 memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
1259 }
679af8a3 1260
18b94127 1261 // -------------------------------------------------
1262 // 2nd pass: actual compilation
44e6452e 1263 out_pc = 0;
18b94127 1264 pc = base_pc;
1265 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
679af8a3 1266 {
18b94127 1267 u32 tmp3, tmp4, sr;
1268
1269 if (drcf.delayed_op > 0)
1270 drcf.delayed_op--;
1271
23686515 1272 op = FETCH_OP(pc);
1273
00faec9c 1274 if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc)
18b94127 1275 {
00faec9c 1276 i = find_in_array(branch_target_pc, branch_target_count, pc);
a2b8c5a5 1277 if (pc != base_pc)
18b94127 1278 {
1279 /* make "subblock" - just a mid-block entry */
1280 block_desc *subblock;
18b94127 1281
1282 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
e05b81fc 1283 FLUSH_CYCLES(sr);
23686515 1284 // decide if to flush rcache
1285 if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2
1286 rcache_clean();
1287 else
1288 rcache_flush();
18b94127 1289 do_host_disasm(tcache_id);
1290
fcdefcf6 1291 dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
04092e32 1292 tcache_id, branch_target_blkid[i], pc, tcache_ptr);
1293
a2b8c5a5 1294 subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]);
18b94127 1295 if (subblock == NULL)
1296 return NULL;
18b94127 1297
44e6452e 1298 // since we made a block entry, link any other blocks that jump to current pc
1299 dr_link_blocks(tcache_ptr, pc, tcache_id);
18b94127 1300 }
04092e32 1301 if (i >= 0)
1302 branch_target_ptr[i] = tcache_ptr;
18b94127 1303
1304 // must update PC
1305 emit_move_r_imm32(SHR_PC, pc);
1306 rcache_clean();
1307
1308 // check cycles
1309 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1310 emith_cmp_r_imm(sr, 0);
1311 emith_jump_cond(DCOND_LE, sh2_drc_exit);
23686515 1312 do_host_disasm(tcache_id);
04092e32 1313 rcache_unlock_all();
18b94127 1314 }
e898de13 1315
e898de13 1316#if (DRC_DEBUG & 2)
fcdefcf6 1317 insns_compiled++;
00faec9c 1318#endif
fcdefcf6 1319#if (DRC_DEBUG & 4)
e898de13 1320 DasmSH2(sh2dasm_buff, pc, op);
1321 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
1322#endif
00faec9c 1323#ifdef DRC_CMP
1324 //if (out_pc != 0 && out_pc != (u32)-1)
1325 // emit_move_r_imm32(SHR_PC, out_pc);
1326 //else
1327 if (!drcf.delayed_op) {
1328 emit_move_r_imm32(SHR_PC, pc);
1329 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1330 FLUSH_CYCLES(sr);
1331 // rcache_clean(); // FIXME
1332 rcache_flush();
1333 emit_do_static_regs(1, 0);
1334 emith_pass_arg_r(0, CONTEXT_REG);
1335 emith_call(do_sh2_cmp);
1336 }
679af8a3 1337#endif
679af8a3 1338
1339 pc += 2;
1340 cycles++;
1341
23686515 1342 if (skip_op > 0) {
1343 skip_op--;
1344 continue;
1345 }
1346
679af8a3 1347 switch ((op >> 12) & 0x0f)
1348 {
3863edbd 1349 /////////////////////////////////////////////
679af8a3 1350 case 0x00:
80599a42 1351 switch (op & 0x0f)
1352 {
1353 case 0x02:
1354 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1355 switch (GET_Fx())
1356 {
1357 case 0: // STC SR,Rn 0000nnnn00000010
1358 tmp2 = SHR_SR;
1359 break;
1360 case 1: // STC GBR,Rn 0000nnnn00010010
1361 tmp2 = SHR_GBR;
1362 break;
1363 case 2: // STC VBR,Rn 0000nnnn00100010
1364 tmp2 = SHR_VBR;
1365 break;
1366 default:
1367 goto default_;
1368 }
ed8cf79b 1369 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1370 emith_move_r_r(tmp, tmp3);
1371 if (tmp2 == SHR_SR)
18b94127 1372 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
80599a42 1373 goto end_op;
e898de13 1374 case 0x03:
1375 CHECK_UNHANDLED_BITS(0xd0);
1376 // BRAF Rm 0000mmmm00100011
1377 // BSRF Rm 0000mmmm00000011
679af8a3 1378 DELAYED_OP;
18b94127 1379 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
80599a42 1380 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
c18edb34 1381 emith_move_r_r(tmp, tmp2);
18b94127 1382 if (op & 0x20)
1383 emith_add_r_imm(tmp, pc + 2);
1384 else { // BSRF
1385 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1386 emith_move_r_imm(tmp3, pc + 2);
1387 emith_add_r_r(tmp, tmp3);
1388 }
44e6452e 1389 out_pc = (u32)-1;
679af8a3 1390 cycles++;
e898de13 1391 goto end_op;
80599a42 1392 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1393 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1394 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
e05b81fc 1395 rcache_clean();
1396 tmp = rcache_get_reg_arg(1, GET_Rm());
1397 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1398 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1399 emith_add_r_r(tmp2, tmp3);
1400 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
80599a42 1401 goto end_op;
1402 case 0x07:
1403 // MUL.L Rm,Rn 0000nnnnmmmm0111
1404 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1405 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1406 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1407 emith_mul(tmp3, tmp2, tmp);
1408 cycles++;
1409 goto end_op;
1410 case 0x08:
1411 CHECK_UNHANDLED_BITS(0xf00);
1412 switch (GET_Fx())
1413 {
1414 case 0: // CLRT 0000000000001000
8796b7ee 1415 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1416 if (drcf.delayed_op)
1417 DELAY_SAVE_T(sr);
8796b7ee 1418 emith_bic_r_imm(sr, T);
80599a42 1419 break;
1420 case 1: // SETT 0000000000011000
8796b7ee 1421 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1422 if (drcf.delayed_op)
1423 DELAY_SAVE_T(sr);
8796b7ee 1424 emith_or_r_imm(sr, T);
80599a42 1425 break;
1426 case 2: // CLRMAC 0000000000101000
23686515 1427 emit_move_r_imm32(SHR_MACL, 0);
1428 emit_move_r_imm32(SHR_MACH, 0);
80599a42 1429 break;
1430 default:
1431 goto default_;
1432 }
1433 goto end_op;
e898de13 1434 case 0x09:
80599a42 1435 switch (GET_Fx())
1436 {
1437 case 0: // NOP 0000000000001001
1438 CHECK_UNHANDLED_BITS(0xf00);
1439 break;
1440 case 1: // DIV0U 0000000000011001
1441 CHECK_UNHANDLED_BITS(0xf00);
8796b7ee 1442 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1443 if (drcf.delayed_op)
1444 DELAY_SAVE_T(sr);
8796b7ee 1445 emith_bic_r_imm(sr, M|Q|T);
80599a42 1446 break;
1447 case 2: // MOVT Rn 0000nnnn00101001
8796b7ee 1448 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
80599a42 1449 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
8796b7ee 1450 emith_clear_msb(tmp2, sr, 31);
80599a42 1451 break;
1452 default:
1453 goto default_;
1454 }
1455 goto end_op;
1456 case 0x0a:
1457 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1458 switch (GET_Fx())
1459 {
1460 case 0: // STS MACH,Rn 0000nnnn00001010
ed8cf79b 1461 tmp2 = SHR_MACH;
80599a42 1462 break;
1463 case 1: // STS MACL,Rn 0000nnnn00011010
ed8cf79b 1464 tmp2 = SHR_MACL;
80599a42 1465 break;
1466 case 2: // STS PR,Rn 0000nnnn00101010
ed8cf79b 1467 tmp2 = SHR_PR;
80599a42 1468 break;
1469 default:
1470 goto default_;
1471 }
ed8cf79b 1472 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
80599a42 1473 emith_move_r_r(tmp, tmp2);
e898de13 1474 goto end_op;
1475 case 0x0b:
80599a42 1476 CHECK_UNHANDLED_BITS(0xf00);
1477 switch (GET_Fx())
1478 {
1479 case 0: // RTS 0000000000001011
1480 DELAYED_OP;
18b94127 1481 emit_move_r_r(SHR_PC, SHR_PR);
44e6452e 1482 out_pc = (u32)-1;
e898de13 1483 cycles++;
80599a42 1484 break;
1485 case 1: // SLEEP 0000000000011011
80599a42 1486 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1487 emith_clear_msb(tmp, tmp, 20); // clear cycles
44e6452e 1488 out_pc = out_pc - 2;
80599a42 1489 cycles = 1;
e05b81fc 1490 goto end_op;
80599a42 1491 case 2: // RTE 0000000000101011
52d759c3 1492 DELAYED_OP;
52d759c3 1493 // pop PC
23686515 1494 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
52d759c3 1495 // pop SR
1496 tmp = rcache_get_reg_arg(0, SHR_SP);
1497 emith_add_r_imm(tmp, 4);
1498 tmp = emit_memhandler_read(2);
18b94127 1499 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1500 emith_write_sr(sr, tmp);
52d759c3 1501 rcache_free_tmp(tmp);
1502 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1503 emith_add_r_imm(tmp, 4*2);
18b94127 1504 drcf.test_irq = 1;
44e6452e 1505 out_pc = (u32)-1;
e898de13 1506 cycles += 3;
80599a42 1507 break;
1508 default:
1509 goto default_;
e898de13 1510 }
1511 goto end_op;
80599a42 1512 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1513 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1514 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
52d759c3 1515 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
80599a42 1516 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
80599a42 1517 if ((op & 3) != 2) {
1518 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1519 } else
1520 emith_move_r_r(tmp2, tmp);
52d759c3 1521 rcache_free_tmp(tmp);
80599a42 1522 goto end_op;
1523 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
f0d7b1fa 1524 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
f0d7b1fa 1525 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1526 /* MS 16 MAC bits unused if saturated */
23686515 1527 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
8796b7ee 1528 emith_tst_r_imm(sr, S);
f0d7b1fa 1529 EMITH_SJMP_START(DCOND_EQ);
1530 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1531 EMITH_SJMP_END(DCOND_EQ);
23686515 1532 rcache_unlock(sr);
f0d7b1fa 1533 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1534 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
f0d7b1fa 1535 rcache_free_tmp(tmp2);
8796b7ee 1536 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1537 emith_tst_r_imm(sr, S);
1538
1539 EMITH_JMP_START(DCOND_EQ);
1540 emith_asr(tmp, tmp4, 15);
1541 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1542 EMITH_SJMP_START(DCOND_GE);
1543 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1544 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1545 EMITH_SJMP_END(DCOND_GE);
1546 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1547 EMITH_SJMP_START(DCOND_LE);
1548 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1549 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1550 EMITH_SJMP_END(DCOND_LE);
1551 EMITH_JMP_END(DCOND_EQ);
1552
1553 rcache_free_tmp(tmp);
f0d7b1fa 1554 cycles += 3;
1555 goto end_op;
80599a42 1556 }
1557 goto default_;
1558
3863edbd 1559 /////////////////////////////////////////////
80599a42 1560 case 0x01:
1561 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1562 rcache_clean();
1563 tmp = rcache_get_reg_arg(0, GET_Rn());
1564 tmp2 = rcache_get_reg_arg(1, GET_Rm());
23686515 1565 if (op & 0x0f)
1566 emith_add_r_imm(tmp, (op & 0x0f) * 4);
e05b81fc 1567 emit_memhandler_write(2, pc, drcf.delayed_op);
80599a42 1568 goto end_op;
1569
1570 case 0x02:
1571 switch (op & 0x0f)
1572 {
1573 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1574 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1575 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1576 rcache_clean();
1577 rcache_get_reg_arg(0, GET_Rn());
1578 rcache_get_reg_arg(1, GET_Rm());
e05b81fc 1579 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
80599a42 1580 goto end_op;
1581 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1582 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1583 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1584 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1585 emith_sub_r_imm(tmp, (1 << (op & 3)));
1586 rcache_clean();
1587 rcache_get_reg_arg(0, GET_Rn());
1588 rcache_get_reg_arg(1, GET_Rm());
e05b81fc 1589 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
80599a42 1590 goto end_op;
1591 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
8796b7ee 1592 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
80599a42 1593 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1594 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
18b94127 1595 if (drcf.delayed_op)
1596 DELAY_SAVE_T(sr);
8796b7ee 1597 emith_bic_r_imm(sr, M|Q|T);
80599a42 1598 emith_tst_r_imm(tmp2, (1<<31));
1599 EMITH_SJMP_START(DCOND_EQ);
8796b7ee 1600 emith_or_r_imm_c(DCOND_NE, sr, Q);
80599a42 1601 EMITH_SJMP_END(DCOND_EQ);
1602 emith_tst_r_imm(tmp3, (1<<31));
1603 EMITH_SJMP_START(DCOND_EQ);
8796b7ee 1604 emith_or_r_imm_c(DCOND_NE, sr, M);
80599a42 1605 EMITH_SJMP_END(DCOND_EQ);
1606 emith_teq_r_r(tmp2, tmp3);
1607 EMITH_SJMP_START(DCOND_PL);
8796b7ee 1608 emith_or_r_imm_c(DCOND_MI, sr, T);
80599a42 1609 EMITH_SJMP_END(DCOND_PL);
1610 goto end_op;
3863edbd 1611 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
8796b7ee 1612 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
3863edbd 1613 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1614 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
18b94127 1615 if (drcf.delayed_op)
1616 DELAY_SAVE_T(sr);
8796b7ee 1617 emith_bic_r_imm(sr, T);
3863edbd 1618 emith_tst_r_r(tmp2, tmp3);
8796b7ee 1619 emit_or_t_if_eq(sr);
3863edbd 1620 goto end_op;
1621 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1622 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1623 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1624 emith_and_r_r(tmp, tmp2);
1625 goto end_op;
1626 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1627 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1628 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1629 emith_eor_r_r(tmp, tmp2);
1630 goto end_op;
1631 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1632 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1633 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1634 emith_or_r_r(tmp, tmp2);
1635 goto end_op;
1636 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1637 tmp = rcache_get_tmp();
1638 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1639 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1640 emith_eor_r_r_r(tmp, tmp2, tmp3);
8796b7ee 1641 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1642 if (drcf.delayed_op)
1643 DELAY_SAVE_T(sr);
8796b7ee 1644 emith_bic_r_imm(sr, T);
3863edbd 1645 emith_tst_r_imm(tmp, 0x000000ff);
52d759c3 1646 emit_or_t_if_eq(tmp);
3863edbd 1647 emith_tst_r_imm(tmp, 0x0000ff00);
52d759c3 1648 emit_or_t_if_eq(tmp);
3863edbd 1649 emith_tst_r_imm(tmp, 0x00ff0000);
52d759c3 1650 emit_or_t_if_eq(tmp);
3863edbd 1651 emith_tst_r_imm(tmp, 0xff000000);
52d759c3 1652 emit_or_t_if_eq(tmp);
3863edbd 1653 rcache_free_tmp(tmp);
1654 goto end_op;
1655 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1656 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1657 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1658 emith_lsr(tmp, tmp, 16);
f0d7b1fa 1659 emith_or_r_r_lsl(tmp, tmp2, 16);
3863edbd 1660 goto end_op;
1661 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1662 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1663 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1664 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1665 if (op & 1) {
1666 emith_sext(tmp, tmp2, 16);
1667 } else
1668 emith_clear_msb(tmp, tmp2, 16);
1669 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1670 tmp2 = rcache_get_tmp();
1671 if (op & 1) {
1672 emith_sext(tmp2, tmp3, 16);
1673 } else
1674 emith_clear_msb(tmp2, tmp3, 16);
1675 emith_mul(tmp, tmp, tmp2);
1676 rcache_free_tmp(tmp2);
1677// FIXME: causes timing issues in Doom?
1678// cycles++;
1679 goto end_op;
679af8a3 1680 }
1681 goto default_;
1682
3863edbd 1683 /////////////////////////////////////////////
1684 case 0x03:
1685 switch (op & 0x0f)
1686 {
1687 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1688 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1689 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1690 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1691 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
8796b7ee 1692 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
3863edbd 1693 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1694 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
18b94127 1695 if (drcf.delayed_op)
1696 DELAY_SAVE_T(sr);
8796b7ee 1697 emith_bic_r_imm(sr, T);
3863edbd 1698 emith_cmp_r_r(tmp2, tmp3);
1699 switch (op & 0x07)
1700 {
1701 case 0x00: // CMP/EQ
8796b7ee 1702 emit_or_t_if_eq(sr);
3863edbd 1703 break;
1704 case 0x02: // CMP/HS
1705 EMITH_SJMP_START(DCOND_LO);
8796b7ee 1706 emith_or_r_imm_c(DCOND_HS, sr, T);
3863edbd 1707 EMITH_SJMP_END(DCOND_LO);
1708 break;
1709 case 0x03: // CMP/GE
1710 EMITH_SJMP_START(DCOND_LT);
8796b7ee 1711 emith_or_r_imm_c(DCOND_GE, sr, T);
3863edbd 1712 EMITH_SJMP_END(DCOND_LT);
1713 break;
1714 case 0x06: // CMP/HI
1715 EMITH_SJMP_START(DCOND_LS);
8796b7ee 1716 emith_or_r_imm_c(DCOND_HI, sr, T);
3863edbd 1717 EMITH_SJMP_END(DCOND_LS);
1718 break;
1719 case 0x07: // CMP/GT
1720 EMITH_SJMP_START(DCOND_LE);
8796b7ee 1721 emith_or_r_imm_c(DCOND_GT, sr, T);
3863edbd 1722 EMITH_SJMP_END(DCOND_LE);
1723 break;
1724 }
1725 goto end_op;
1726 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
f0d7b1fa 1727 // Q1 = carry(Rn = (Rn << 1) | T)
1728 // if Q ^ M
1729 // Q2 = carry(Rn += Rm)
1730 // else
1731 // Q2 = carry(Rn -= Rm)
1732 // Q = M ^ Q1 ^ Q2
1733 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1734 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1735 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1736 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1737 if (drcf.delayed_op)
1738 DELAY_SAVE_T(sr);
8b4f38f4 1739 emith_tpop_carry(sr, 0);
f0d7b1fa 1740 emith_adcf_r_r(tmp2, tmp2);
8b4f38f4 1741 emith_tpush_carry(sr, 0); // keep Q1 in T for now
f0d7b1fa 1742 tmp4 = rcache_get_tmp();
1743 emith_and_r_r_imm(tmp4, sr, M);
1744 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1745 rcache_free_tmp(tmp4);
1746 // add or sub, invert T if carry to get Q1 ^ Q2
1747 // in: (Q ^ M) passed in Q, Q1 in T
1748 emith_sh2_div1_step(tmp2, tmp3, sr);
18b94127 1749 emith_bic_r_imm(sr, Q);
1750 emith_tst_r_imm(sr, M);
1751 EMITH_SJMP_START(DCOND_EQ);
1752 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1753 EMITH_SJMP_END(DCOND_EQ);
1754 emith_tst_r_imm(sr, T);
1755 EMITH_SJMP_START(DCOND_EQ);
1756 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1757 EMITH_SJMP_END(DCOND_EQ);
1758 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
f0d7b1fa 1759 goto end_op;
3863edbd 1760 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1761 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1762 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1763 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1764 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1765 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1766 goto end_op;
1767 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1768 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1769 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1770 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1771 if (op & 4) {
1772 emith_add_r_r(tmp, tmp2);
1773 } else
1774 emith_sub_r_r(tmp, tmp2);
1775 goto end_op;
1776 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1777 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1778 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1779 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
8796b7ee 1780 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1781 if (drcf.delayed_op)
1782 DELAY_SAVE_T(sr);
3863edbd 1783 if (op & 4) { // adc
8b4f38f4 1784 emith_tpop_carry(sr, 0);
3863edbd 1785 emith_adcf_r_r(tmp, tmp2);
8b4f38f4 1786 emith_tpush_carry(sr, 0);
3863edbd 1787 } else {
8b4f38f4 1788 emith_tpop_carry(sr, 1);
3863edbd 1789 emith_sbcf_r_r(tmp, tmp2);
8b4f38f4 1790 emith_tpush_carry(sr, 1);
3863edbd 1791 }
3863edbd 1792 goto end_op;
1793 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1794 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1795 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1796 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
8796b7ee 1797 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1798 if (drcf.delayed_op)
1799 DELAY_SAVE_T(sr);
8796b7ee 1800 emith_bic_r_imm(sr, T);
3863edbd 1801 if (op & 4) {
1802 emith_addf_r_r(tmp, tmp2);
1803 } else
1804 emith_subf_r_r(tmp, tmp2);
1805 EMITH_SJMP_START(DCOND_VC);
8796b7ee 1806 emith_or_r_imm_c(DCOND_VS, sr, T);
3863edbd 1807 EMITH_SJMP_END(DCOND_VC);
1808 goto end_op;
1809 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1810 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1811 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1812 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1813 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1814 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1815 goto end_op;
1816 }
1817 goto default_;
1818
1819 /////////////////////////////////////////////
679af8a3 1820 case 0x04:
3863edbd 1821 switch (op & 0x0f)
1822 {
c18edb34 1823 case 0x00:
3863edbd 1824 switch (GET_Fx())
1825 {
1826 case 0: // SHLL Rn 0100nnnn00000000
1827 case 2: // SHAL Rn 0100nnnn00100000
8796b7ee 1828 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1829 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1830 if (drcf.delayed_op)
1831 DELAY_SAVE_T(sr);
8b4f38f4 1832 emith_tpop_carry(sr, 0); // dummy
3863edbd 1833 emith_lslf(tmp, tmp, 1);
8b4f38f4 1834 emith_tpush_carry(sr, 0);
3863edbd 1835 goto end_op;
1836 case 1: // DT Rn 0100nnnn00010000
8796b7ee 1837 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1838 if (drcf.delayed_op)
1839 DELAY_SAVE_T(sr);
00faec9c 1840#ifndef DRC_CMP
23686515 1841 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1842 if (gconst_get(GET_Rn(), &tmp)) {
1843 // XXX: limit burned cycles
1844 emit_move_r_imm32(GET_Rn(), 0);
1845 emith_or_r_imm(sr, T);
a2b8c5a5 1846 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
23686515 1847 skip_op = 1;
1848 }
1849 else
1850 emith_sh2_dtbf_loop();
1851 goto end_op;
1852 }
00faec9c 1853#endif
23686515 1854 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
8796b7ee 1855 emith_bic_r_imm(sr, T);
3863edbd 1856 emith_subf_r_imm(tmp, 1);
8796b7ee 1857 emit_or_t_if_eq(sr);
80599a42 1858 goto end_op;
1859 }
3863edbd 1860 goto default_;
ed8cf79b 1861 case 0x01:
1862 switch (GET_Fx())
1863 {
1864 case 0: // SHLR Rn 0100nnnn00000001
1865 case 2: // SHAR Rn 0100nnnn00100001
8796b7ee 1866 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1867 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1868 if (drcf.delayed_op)
1869 DELAY_SAVE_T(sr);
8b4f38f4 1870 emith_tpop_carry(sr, 0); // dummy
ed8cf79b 1871 if (op & 0x20) {
1872 emith_asrf(tmp, tmp, 1);
1873 } else
1874 emith_lsrf(tmp, tmp, 1);
8b4f38f4 1875 emith_tpush_carry(sr, 0);
ed8cf79b 1876 goto end_op;
1877 case 1: // CMP/PZ Rn 0100nnnn00010001
8796b7ee 1878 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1879 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1880 if (drcf.delayed_op)
1881 DELAY_SAVE_T(sr);
8796b7ee 1882 emith_bic_r_imm(sr, T);
ed8cf79b 1883 emith_cmp_r_imm(tmp, 0);
1884 EMITH_SJMP_START(DCOND_LT);
8796b7ee 1885 emith_or_r_imm_c(DCOND_GE, sr, T);
ed8cf79b 1886 EMITH_SJMP_END(DCOND_LT);
1887 goto end_op;
1888 }
1889 goto default_;
1890 case 0x02:
1891 case 0x03:
1892 switch (op & 0x3f)
1893 {
1894 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1895 tmp = SHR_MACH;
1896 break;
1897 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1898 tmp = SHR_MACL;
1899 break;
1900 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1901 tmp = SHR_PR;
1902 break;
1903 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1904 tmp = SHR_SR;
1905 break;
1906 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1907 tmp = SHR_GBR;
1908 break;
1909 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1910 tmp = SHR_VBR;
1911 break;
1912 default:
e898de13 1913 goto default_;
ed8cf79b 1914 }
1915 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1916 emith_sub_r_imm(tmp2, 4);
1917 rcache_clean();
1918 rcache_get_reg_arg(0, GET_Rn());
1919 tmp3 = rcache_get_reg_arg(1, tmp);
1920 if (tmp == SHR_SR)
e05b81fc 1921 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1922 emit_memhandler_write(2, pc, drcf.delayed_op);
ed8cf79b 1923 goto end_op;
1924 case 0x04:
1925 case 0x05:
1926 switch (op & 0x3f)
1927 {
1928 case 0x04: // ROTL Rn 0100nnnn00000100
1929 case 0x05: // ROTR Rn 0100nnnn00000101
8796b7ee 1930 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1931 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1932 if (drcf.delayed_op)
1933 DELAY_SAVE_T(sr);
8b4f38f4 1934 emith_tpop_carry(sr, 0); // dummy
ed8cf79b 1935 if (op & 1) {
1936 emith_rorf(tmp, tmp, 1);
1937 } else
1938 emith_rolf(tmp, tmp, 1);
8b4f38f4 1939 emith_tpush_carry(sr, 0);
ed8cf79b 1940 goto end_op;
1941 case 0x24: // ROTCL Rn 0100nnnn00100100
1942 case 0x25: // ROTCR Rn 0100nnnn00100101
8796b7ee 1943 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1944 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1945 if (drcf.delayed_op)
1946 DELAY_SAVE_T(sr);
8b4f38f4 1947 emith_tpop_carry(sr, 0);
ed8cf79b 1948 if (op & 1) {
1949 emith_rorcf(tmp);
1950 } else
1951 emith_rolcf(tmp);
8b4f38f4 1952 emith_tpush_carry(sr, 0);
ed8cf79b 1953 goto end_op;
1954 case 0x15: // CMP/PL Rn 0100nnnn00010101
8796b7ee 1955 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1956 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 1957 if (drcf.delayed_op)
1958 DELAY_SAVE_T(sr);
8796b7ee 1959 emith_bic_r_imm(sr, T);
ed8cf79b 1960 emith_cmp_r_imm(tmp, 0);
1961 EMITH_SJMP_START(DCOND_LE);
8796b7ee 1962 emith_or_r_imm_c(DCOND_GT, sr, T);
ed8cf79b 1963 EMITH_SJMP_END(DCOND_LE);
1964 goto end_op;
1965 }
e898de13 1966 goto default_;
ed8cf79b 1967 case 0x06:
1968 case 0x07:
1969 switch (op & 0x3f)
1970 {
1971 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1972 tmp = SHR_MACH;
1973 break;
1974 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1975 tmp = SHR_MACL;
1976 break;
1977 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1978 tmp = SHR_PR;
1979 break;
1980 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1981 tmp = SHR_SR;
1982 break;
1983 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1984 tmp = SHR_GBR;
1985 break;
1986 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1987 tmp = SHR_VBR;
1988 break;
1989 default:
1990 goto default_;
1991 }
ed8cf79b 1992 rcache_get_reg_arg(0, GET_Rn());
1993 tmp2 = emit_memhandler_read(2);
1994 if (tmp == SHR_SR) {
18b94127 1995 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1996 if (drcf.delayed_op)
1997 DELAY_SAVE_T(sr);
1998 emith_write_sr(sr, tmp2);
1999 drcf.test_irq = 1;
ed8cf79b 2000 } else {
2001 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2002 emith_move_r_r(tmp, tmp2);
2003 }
2004 rcache_free_tmp(tmp2);
2005 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2006 emith_add_r_imm(tmp, 4);
2007 goto end_op;
52d759c3 2008 case 0x08:
2009 case 0x09:
2010 switch (GET_Fx())
2011 {
2012 case 0:
2013 // SHLL2 Rn 0100nnnn00001000
2014 // SHLR2 Rn 0100nnnn00001001
2015 tmp = 2;
2016 break;
2017 case 1:
2018 // SHLL8 Rn 0100nnnn00011000
2019 // SHLR8 Rn 0100nnnn00011001
2020 tmp = 8;
2021 break;
2022 case 2:
2023 // SHLL16 Rn 0100nnnn00101000
2024 // SHLR16 Rn 0100nnnn00101001
2025 tmp = 16;
2026 break;
2027 default:
2028 goto default_;
2029 }
2030 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2031 if (op & 1) {
2032 emith_lsr(tmp2, tmp2, tmp);
2033 } else
2034 emith_lsl(tmp2, tmp2, tmp);
2035 goto end_op;
2036 case 0x0a:
2037 switch (GET_Fx())
2038 {
2039 case 0: // LDS Rm,MACH 0100mmmm00001010
2040 tmp2 = SHR_MACH;
2041 break;
2042 case 1: // LDS Rm,MACL 0100mmmm00011010
2043 tmp2 = SHR_MACL;
2044 break;
2045 case 2: // LDS Rm,PR 0100mmmm00101010
2046 tmp2 = SHR_PR;
2047 break;
2048 default:
2049 goto default_;
2050 }
2051 emit_move_r_r(tmp2, GET_Rn());
2052 goto end_op;
e898de13 2053 case 0x0b:
52d759c3 2054 switch (GET_Fx())
2055 {
2056 case 0: // JSR @Rm 0100mmmm00001011
2057 case 2: // JMP @Rm 0100mmmm00101011
2058 DELAYED_OP;
2059 if (!(op & 0x20))
2060 emit_move_r_imm32(SHR_PR, pc + 2);
18b94127 2061 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
44e6452e 2062 out_pc = (u32)-1;
52d759c3 2063 cycles++;
2064 break;
2065 case 1: // TAS.B @Rn 0100nnnn00011011
2066 // XXX: is TAS working on 32X?
52d759c3 2067 rcache_get_reg_arg(0, GET_Rn());
8796b7ee 2068 tmp = emit_memhandler_read(0);
2069 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 2070 if (drcf.delayed_op)
2071 DELAY_SAVE_T(sr);
8796b7ee 2072 emith_bic_r_imm(sr, T);
52d759c3 2073 emith_cmp_r_imm(tmp, 0);
8796b7ee 2074 emit_or_t_if_eq(sr);
52d759c3 2075 rcache_clean();
2076 emith_or_r_imm(tmp, 0x80);
2077 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2078 emith_move_r_r(tmp2, tmp);
2079 rcache_free_tmp(tmp);
2080 rcache_get_reg_arg(0, GET_Rn());
e05b81fc 2081 emit_memhandler_write(0, pc, drcf.delayed_op);
52d759c3 2082 cycles += 3;
2083 break;
2084 default:
e898de13 2085 goto default_;
52d759c3 2086 }
e898de13 2087 goto end_op;
2088 case 0x0e:
52d759c3 2089 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2090 switch (GET_Fx())
2091 {
2092 case 0: // LDC Rm,SR 0100mmmm00001110
2093 tmp2 = SHR_SR;
2094 break;
2095 case 1: // LDC Rm,GBR 0100mmmm00011110
2096 tmp2 = SHR_GBR;
2097 break;
2098 case 2: // LDC Rm,VBR 0100mmmm00101110
2099 tmp2 = SHR_VBR;
2100 break;
2101 default:
e898de13 2102 goto default_;
52d759c3 2103 }
2104 if (tmp2 == SHR_SR) {
18b94127 2105 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2106 if (drcf.delayed_op)
2107 DELAY_SAVE_T(sr);
2108 emith_write_sr(sr, tmp);
2109 drcf.test_irq = 1;
52d759c3 2110 } else {
2111 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2112 emith_move_r_r(tmp2, tmp);
2113 }
2114 goto end_op;
2115 case 0x0f:
23686515 2116 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
f0d7b1fa 2117 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2118 emith_sext(tmp, tmp, 16);
2119 emith_sext(tmp2, tmp2, 16);
2120 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2121 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2122 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
f0d7b1fa 2123 rcache_free_tmp(tmp2);
f0d7b1fa 2124 // XXX: MACH should be untouched when S is set?
8796b7ee 2125 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2126 emith_tst_r_imm(sr, S);
2127 EMITH_JMP_START(DCOND_EQ);
2128
2129 emith_asr(tmp, tmp3, 31);
2130 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2131 EMITH_JMP_START(DCOND_EQ);
2132 emith_move_r_imm(tmp3, 0x80000000);
2133 emith_tst_r_r(tmp4, tmp4);
2134 EMITH_SJMP_START(DCOND_MI);
2135 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2136 EMITH_SJMP_END(DCOND_MI);
2137 EMITH_JMP_END(DCOND_EQ);
2138
2139 EMITH_JMP_END(DCOND_EQ);
2140 rcache_free_tmp(tmp);
f0d7b1fa 2141 cycles += 2;
2142 goto end_op;
679af8a3 2143 }
2144 goto default_;
2145
52d759c3 2146 /////////////////////////////////////////////
2147 case 0x05:
2148 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
23686515 2149 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
52d759c3 2150 goto end_op;
2151
2152 /////////////////////////////////////////////
2153 case 0x06:
2154 switch (op & 0x0f)
2155 {
2156 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2157 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2158 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2159 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2160 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2161 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
23686515 2162 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
52d759c3 2163 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2164 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2165 emith_add_r_imm(tmp, (1 << (op & 3)));
2166 }
2167 goto end_op;
2168 case 0x03:
2169 case 0x07 ... 0x0f:
2170 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2171 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2172 switch (op & 0x0f)
2173 {
2174 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2175 emith_move_r_r(tmp2, tmp);
2176 break;
2177 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2178 emith_mvn_r_r(tmp2, tmp);
2179 break;
2180 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2181 tmp3 = tmp2;
2182 if (tmp == tmp2)
2183 tmp3 = rcache_get_tmp();
2184 tmp4 = rcache_get_tmp();
2185 emith_lsr(tmp3, tmp, 16);
f0d7b1fa 2186 emith_or_r_r_lsl(tmp3, tmp, 24);
52d759c3 2187 emith_and_r_r_imm(tmp4, tmp, 0xff00);
f0d7b1fa 2188 emith_or_r_r_lsl(tmp3, tmp4, 8);
52d759c3 2189 emith_rol(tmp2, tmp3, 16);
2190 rcache_free_tmp(tmp4);
2191 if (tmp == tmp2)
2192 rcache_free_tmp(tmp3);
2193 break;
2194 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2195 emith_rol(tmp2, tmp, 16);
2196 break;
2197 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
8796b7ee 2198 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 2199 if (drcf.delayed_op)
2200 DELAY_SAVE_T(sr);
8b4f38f4 2201 emith_tpop_carry(sr, 1);
52d759c3 2202 emith_negcf_r_r(tmp2, tmp);
8b4f38f4 2203 emith_tpush_carry(sr, 1);
52d759c3 2204 break;
2205 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2206 emith_neg_r_r(tmp2, tmp);
2207 break;
2208 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2209 emith_clear_msb(tmp2, tmp, 24);
2210 break;
2211 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2212 emith_clear_msb(tmp2, tmp, 16);
2213 break;
2214 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2215 emith_sext(tmp2, tmp, 8);
2216 break;
2217 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2218 emith_sext(tmp2, tmp, 16);
2219 break;
2220 }
2221 goto end_op;
2222 }
2223 goto default_;
2224
2225 /////////////////////////////////////////////
2226 case 0x07:
2227 // ADD #imm,Rn 0111nnnniiiiiiii
2228 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2229 if (op & 0x80) { // adding negative
2230 emith_sub_r_imm(tmp, -op & 0xff);
2231 } else
2232 emith_add_r_imm(tmp, op & 0xff);
2233 goto end_op;
2234
3863edbd 2235 /////////////////////////////////////////////
e898de13 2236 case 0x08:
52d759c3 2237 switch (op & 0x0f00)
2238 {
2239 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2240 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2241 rcache_clean();
2242 tmp = rcache_get_reg_arg(0, GET_Rm());
2243 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2244 tmp3 = (op & 0x100) >> 8;
23686515 2245 if (op & 0x0f)
2246 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
e05b81fc 2247 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
52d759c3 2248 goto end_op;
2249 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2250 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
23686515 2251 tmp = (op & 0x100) >> 8;
2252 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
52d759c3 2253 goto end_op;
2254 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2255 // XXX: could use cmn
2256 tmp = rcache_get_tmp();
2257 tmp2 = rcache_get_reg(0, RC_GR_READ);
8796b7ee 2258 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 2259 if (drcf.delayed_op)
2260 DELAY_SAVE_T(sr);
52d759c3 2261 emith_move_r_imm_s8(tmp, op & 0xff);
8796b7ee 2262 emith_bic_r_imm(sr, T);
52d759c3 2263 emith_cmp_r_r(tmp2, tmp);
8796b7ee 2264 emit_or_t_if_eq(sr);
52d759c3 2265 rcache_free_tmp(tmp);
2266 goto end_op;
2267 case 0x0d00: // BT/S label 10001101dddddddd
2268 case 0x0f00: // BF/S label 10001111dddddddd
679af8a3 2269 DELAYED_OP;
2270 cycles--;
679af8a3 2271 // fallthrough
44e6452e 2272 case 0x0900: // BT label 10001001dddddddd
2273 case 0x0b00: // BF label 10001011dddddddd
2274 // will handle conditional branches later
2275 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
2276 i = ((signed int)(op << 24) >> 23);
2277 pending_branch_pc = pc + i + 2;
e898de13 2278 cycles += 2;
e898de13 2279 goto end_op;
44e6452e 2280 }
679af8a3 2281 goto default_;
679af8a3 2282
52d759c3 2283 /////////////////////////////////////////////
2284 case 0x09:
2285 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
23686515 2286 tmp = pc + (op & 0xff) * 2 + 2;
2287#if PROPAGATE_CONSTANTS
04092e32 2288 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2289 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
23686515 2290 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
23686515 2291 }
2292 else
2293#endif
2294 {
2295 tmp2 = rcache_get_tmp_arg(0);
2296 emith_move_r_imm(tmp2, tmp);
2297 tmp2 = emit_memhandler_read(1);
2298 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2299 emith_sext(tmp3, tmp2, 16);
2300 rcache_free_tmp(tmp2);
2301 }
f0d7b1fa 2302 goto end_op;
52d759c3 2303
3863edbd 2304 /////////////////////////////////////////////
679af8a3 2305 case 0x0a:
2306 // BRA label 1010dddddddddddd
2307 DELAYED_OP;
44e6452e 2308 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
679af8a3 2309 tmp = ((signed int)(op << 20) >> 19);
44e6452e 2310 out_pc = pc + tmp + 2;
2311 if (tmp == (u32)-4)
2312 emith_clear_msb(sr, sr, 20); // burn cycles
679af8a3 2313 cycles++;
e898de13 2314 break;
679af8a3 2315
3863edbd 2316 /////////////////////////////////////////////
679af8a3 2317 case 0x0b:
2318 // BSR label 1011dddddddddddd
2319 DELAYED_OP;
e898de13 2320 emit_move_r_imm32(SHR_PR, pc + 2);
44e6452e 2321 tmp = ((signed int)(op << 20) >> 19);
2322 out_pc = pc + tmp + 2;
2323 cycles++;
2324 break;
679af8a3 2325
52d759c3 2326 /////////////////////////////////////////////
2327 case 0x0c:
2328 switch (op & 0x0f00)
2329 {
2330 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2331 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2332 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2333 rcache_clean();
2334 tmp = rcache_get_reg_arg(0, SHR_GBR);
2335 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2336 tmp3 = (op & 0x300) >> 8;
2337 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
e05b81fc 2338 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
52d759c3 2339 goto end_op;
2340 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2341 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2342 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
23686515 2343 tmp = (op & 0x300) >> 8;
2344 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
52d759c3 2345 goto end_op;
2346 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2347 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2348 emith_sub_r_imm(tmp, 4*2);
52d759c3 2349 // push SR
2350 tmp = rcache_get_reg_arg(0, SHR_SP);
2351 emith_add_r_imm(tmp, 4);
2352 tmp = rcache_get_reg_arg(1, SHR_SR);
18b94127 2353 emith_clear_msb(tmp, tmp, 22);
e05b81fc 2354 emit_memhandler_write(2, pc, drcf.delayed_op);
52d759c3 2355 // push PC
2356 rcache_get_reg_arg(0, SHR_SP);
2357 tmp = rcache_get_tmp_arg(1);
2358 emith_move_r_imm(tmp, pc);
e05b81fc 2359 emit_memhandler_write(2, pc, drcf.delayed_op);
52d759c3 2360 // obtain new PC
23686515 2361 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
44e6452e 2362 out_pc = (u32)-1;
52d759c3 2363 cycles += 7;
44e6452e 2364 goto end_op;
52d759c3 2365 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2366 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2367 goto end_op;
2368 case 0x0800: // TST #imm,R0 11001000iiiiiiii
8796b7ee 2369 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2370 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 2371 if (drcf.delayed_op)
2372 DELAY_SAVE_T(sr);
8796b7ee 2373 emith_bic_r_imm(sr, T);
52d759c3 2374 emith_tst_r_imm(tmp, op & 0xff);
8796b7ee 2375 emit_or_t_if_eq(sr);
52d759c3 2376 goto end_op;
2377 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2378 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2379 emith_and_r_imm(tmp, op & 0xff);
2380 goto end_op;
2381 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2382 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2383 emith_eor_r_imm(tmp, op & 0xff);
2384 goto end_op;
2385 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2386 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2387 emith_or_r_imm(tmp, op & 0xff);
2388 goto end_op;
2389 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
8796b7ee 2390 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2391 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
18b94127 2392 if (drcf.delayed_op)
2393 DELAY_SAVE_T(sr);
8796b7ee 2394 emith_bic_r_imm(sr, T);
52d759c3 2395 emith_tst_r_imm(tmp, op & 0xff);
8796b7ee 2396 emit_or_t_if_eq(sr);
52d759c3 2397 rcache_free_tmp(tmp);
2398 cycles += 2;
2399 goto end_op;
2400 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2401 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2402 emith_and_r_imm(tmp, op & 0xff);
8796b7ee 2403 goto end_rmw_op;
52d759c3 2404 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2405 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2406 emith_eor_r_imm(tmp, op & 0xff);
8796b7ee 2407 goto end_rmw_op;
52d759c3 2408 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2409 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2410 emith_or_r_imm(tmp, op & 0xff);
8796b7ee 2411 end_rmw_op:
2412 tmp2 = rcache_get_tmp_arg(1);
2413 emith_move_r_r(tmp2, tmp);
2414 rcache_free_tmp(tmp);
2415 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2416 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2417 emith_add_r_r(tmp3, tmp4);
e05b81fc 2418 emit_memhandler_write(0, pc, drcf.delayed_op);
52d759c3 2419 cycles += 2;
2420 goto end_op;
2421 }
2422 goto default_;
2423
2424 /////////////////////////////////////////////
2425 case 0x0d:
2426 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
23686515 2427 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2428#if PROPAGATE_CONSTANTS
04092e32 2429 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2430 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
23686515 2431 gconst_new(GET_Rn(), FETCH32(tmp));
23686515 2432 }
2433 else
2434#endif
2435 {
2436 tmp2 = rcache_get_tmp_arg(0);
2437 emith_move_r_imm(tmp2, tmp);
2438 tmp2 = emit_memhandler_read(2);
2439 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2440 emith_move_r_r(tmp3, tmp2);
2441 rcache_free_tmp(tmp2);
2442 }
f0d7b1fa 2443 goto end_op;
52d759c3 2444
2445 /////////////////////////////////////////////
2446 case 0x0e:
2447 // MOV #imm,Rn 1110nnnniiiiiiii
23686515 2448 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
52d759c3 2449 goto end_op;
2450
679af8a3 2451 default:
2452 default_:
f0d7b1fa 2453 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2454 sh2->is_slave ? 's' : 'm', op, pc - 2);
679af8a3 2455 break;
2456 }
2457
e898de13 2458end_op:
23686515 2459 rcache_unlock_all();
2460
44e6452e 2461 // conditional branch handling (with/without delay)
2462 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2463 {
2464 u32 target_pc = pending_branch_pc;
2465 void *target;
2466
18b94127 2467 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2468 // handle cycles
e05b81fc 2469 FLUSH_CYCLES(sr);
18b94127 2470 rcache_clean();
18b94127 2471 if (drcf.use_saved_t)
2472 emith_tst_r_imm(sr, T_save);
2473 else
2474 emith_tst_r_imm(sr, T);
18b94127 2475
5686d931 2476#if LINK_BRANCHES
44e6452e 2477 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2478 // local branch
2479 // XXX: jumps back can be linked already
2480 branch_patch_pc[branch_patch_count] = target_pc;
2481 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2482 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2483
2484 branch_patch_count++;
2485 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
fcdefcf6 2486 dbg(1, "warning: too many local branches");
44e6452e 2487 break;
2488 }
2489 }
5686d931 2490 else
2491#endif
2492 {
44e6452e 2493 // can't resolve branch locally, make a block exit
2494 emit_move_r_imm32(SHR_PC, target_pc);
2495 rcache_clean();
2496
2497 target = dr_prepare_ext_branch(target_pc, sh2, tcache_id);
2498 if (target == NULL)
2499 return NULL;
2500 emith_jump_cond_patchable(pending_branch_cond, target);
18b94127 2501 }
44e6452e 2502
2503 drcf.use_saved_t = 0;
2504 pending_branch_cond = -1;
e898de13 2505 }
44e6452e 2506
18b94127 2507 // test irq?
e05b81fc 2508 // XXX: delay slots..
2509 if (drcf.test_irq && drcf.delayed_op != 2) {
2510 if (!drcf.delayed_op)
2511 emit_move_r_imm32(SHR_PC, pc);
2512 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2513 FLUSH_CYCLES(sr);
2514 rcache_flush();
2515 emith_call(sh2_drc_test_irq);
2516 drcf.test_irq = 0;
2517 }
e898de13 2518
f4bb5d6b 2519 do_host_disasm(tcache_id);
52d759c3 2520
44e6452e 2521 if (out_pc != 0 && drcf.delayed_op != 2)
2522 break;
2523 }
f4bb5d6b 2524
18b94127 2525 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
e05b81fc 2526 FLUSH_CYCLES(tmp);
18b94127 2527 rcache_flush();
44e6452e 2528
2529 if (out_pc == (u32)-1) {
2530 // indirect jump -> back to dispatcher
2531 emith_jump(sh2_drc_dispatcher);
2532 } else {
2533 void *target;
2534 if (out_pc == 0)
2535 out_pc = pc;
2536 emit_move_r_imm32(SHR_PC, out_pc);
2537 rcache_flush();
2538
2539 target = dr_prepare_ext_branch(out_pc, sh2, tcache_id);
2540 if (target == NULL)
2541 return NULL;
2542 emith_jump_patchable(target);
2543 }
18b94127 2544
2545 // link local branches
2546 for (i = 0; i < branch_patch_count; i++) {
2547 void *target;
2548 int t;
18b94127 2549 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
44e6452e 2550 target = branch_target_ptr[t];
2551 if (target == NULL) {
fcdefcf6 2552 // flush pc and go back to dispatcher (this should no longer happen)
2553 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
18b94127 2554 target = tcache_ptr;
2555 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2556 rcache_flush();
e05b81fc 2557 emith_jump(sh2_drc_dispatcher);
18b94127 2558 }
2559 emith_jump_patch(branch_patch_ptr[i], target);
2560 }
2561
a2b8c5a5 2562 end_pc = pc;
44e6452e 2563
f4bb5d6b 2564 // mark memory blocks as containing compiled code
a2b8c5a5 2565 // override any overlay blocks as they become unreachable anyway
2566 if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000)
2567 {
2568 u16 *drc_ram_blk = NULL;
2569 u32 mask = 0, shift = 0;
2570
2571 if (tcache_id != 0) {
2572 // data array, BIOS
2573 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2574 shift = SH2_DRCBLK_DA_SHIFT;
2575 mask = 0xfff;
f4bb5d6b 2576 }
a2b8c5a5 2577 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) {
2578 // SDRAM
2579 drc_ram_blk = Pico32xMem->drcblk_ram;
2580 shift = SH2_DRCBLK_RAM_SHIFT;
2581 mask = 0x3ffff;
f4bb5d6b 2582 }
a2b8c5a5 2583
2584 drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1;
2585 for (pc = base_pc + 2; pc < end_pc; pc += 2)
2586 drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1;
2587
04092e32 2588 // mark subblocks
a2b8c5a5 2589 for (i = 0; i < branch_target_count; i++)
2590 if (branch_target_blkid[i] != 0)
2591 drc_ram_blk[(branch_target_pc[i] >> shift) & mask] =
04092e32 2592 (branch_target_blkid[i] << 1) | 1;
2593
2594 // mark literals
2595 for (i = 0; i < literal_addr_count; i++) {
2596 tmp = literal_addr[i];
04092e32 2597 drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1;
2598 if (!(tmp & 3)) // assume long
2599 drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1;
2600 }
679af8a3 2601 }
2602
f4bb5d6b 2603 tcache_ptrs[tcache_id] = tcache_ptr;
2604
a2b8c5a5 2605 host_instructions_updated(block_entry, tcache_ptr);
553c3eaa 2606
f4bb5d6b 2607 do_host_disasm(tcache_id);
fcdefcf6 2608 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
f4bb5d6b 2609 tcache_id, block_counts[tcache_id],
2610 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2611 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2612 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
fcdefcf6 2613 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
18b94127 2614/*
2615 printf("~~~\n");
2616 tcache_dsm_ptrs[tcache_id] = block_entry;
2617 do_host_disasm(tcache_id);
2618 printf("~~~\n");
2619*/
2620
fcdefcf6 2621#if (DRC_DEBUG & 4)
553c3eaa 2622 fflush(stdout);
2623#endif
2624
679af8a3 2625 return block_entry;
679af8a3 2626}
2627
e05b81fc 2628static void sh2_generate_utils(void)
679af8a3 2629{
e05b81fc 2630 int arg0, arg1, arg2, sr, tmp;
2631 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
52d759c3 2632
5686d931 2633 sh2_drc_write32 = p32x_sh2_write32;
2634 sh2_drc_read8 = p32x_sh2_read8;
2635 sh2_drc_read16 = p32x_sh2_read16;
2636 sh2_drc_read32 = p32x_sh2_read32;
2637
e05b81fc 2638 host_arg2reg(arg0, 0);
2639 host_arg2reg(arg1, 1);
2640 host_arg2reg(arg2, 2);
2641 emith_move_r_r(arg0, arg0); // nop
679af8a3 2642
e05b81fc 2643 // sh2_drc_exit(void)
2644 sh2_drc_exit = (void *)tcache_ptr;
2645 emit_do_static_regs(1, arg2);
2646 emith_sh2_drc_exit();
679af8a3 2647
e05b81fc 2648 // sh2_drc_dispatcher(void)
2649 sh2_drc_dispatcher = (void *)tcache_ptr;
2650 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2651 emith_cmp_r_imm(sr, 0);
2652 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2653 rcache_invalidate();
2654 emith_ctx_read(arg0, SHR_PC * 4);
2655 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2656 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
a2b8c5a5 2657 emith_call(dr_lookup_block);
e05b81fc 2658 emit_block_entry();
2659 // lookup failed, call sh2_translate()
2660 emith_move_r_r(arg0, CONTEXT_REG);
2661 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2662 emith_call(sh2_translate);
2663 emit_block_entry();
2664 // sh2_translate() failed, flush cache and retry
2665 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2666 emith_call(flush_tcache);
2667 emith_move_r_r(arg0, CONTEXT_REG);
2668 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2669 emith_call(sh2_translate);
2670 emit_block_entry();
2671 // XXX: can't translate, fail
c25d78ee 2672 emith_call(dr_failure);
e05b81fc 2673
2674 // sh2_drc_test_irq(void)
2675 // assumes it's called from main function (may jump to dispatcher)
2676 sh2_drc_test_irq = (void *)tcache_ptr;
2677 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2678 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2679 emith_lsr(arg0, sr, I_SHIFT);
2680 emith_and_r_imm(arg0, 0x0f);
2681 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2682 EMITH_SJMP_START(DCOND_GT);
2683 emith_ret_c(DCOND_LE); // nope, return
2684 EMITH_SJMP_END(DCOND_GT);
2685 // adjust SP
2686 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2687 emith_sub_r_imm(tmp, 4*2);
2688 rcache_clean();
2689 // push SR
2690 tmp = rcache_get_reg_arg(0, SHR_SP);
2691 emith_add_r_imm(tmp, 4);
2692 tmp = rcache_get_reg_arg(1, SHR_SR);
2693 emith_clear_msb(tmp, tmp, 22);
2694 emith_move_r_r(arg2, CONTEXT_REG);
5686d931 2695 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
e05b81fc 2696 rcache_invalidate();
2697 // push PC
2698 rcache_get_reg_arg(0, SHR_SP);
2699 emith_ctx_read(arg1, SHR_PC * 4);
2700 emith_move_r_r(arg2, CONTEXT_REG);
2701 emith_call(p32x_sh2_write32);
2702 rcache_invalidate();
2703 // update I, cycles, do callback
2704 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2705 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2706 emith_bic_r_imm(sr, I);
2707 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2708 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2709 rcache_flush();
2710 emith_move_r_r(arg0, CONTEXT_REG);
2711 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2712 // obtain new PC
2713 emith_lsl(arg0, arg0, 2);
2714 emith_ctx_read(arg1, SHR_VBR * 4);
2715 emith_add_r_r(arg0, arg1);
2716 emit_memhandler_read(2);
2717 emith_ctx_write(arg0, SHR_PC * 4);
2718#ifdef __i386__
2719 emith_add_r_imm(xSP, 4); // fix stack
2720#endif
2721 emith_jump(sh2_drc_dispatcher);
2722 rcache_invalidate();
2723
2724 // sh2_drc_entry(SH2 *sh2)
2725 sh2_drc_entry = (void *)tcache_ptr;
2726 emith_sh2_drc_entry();
2727 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2728 emit_do_static_regs(0, arg2);
2729 emith_call(sh2_drc_test_irq);
2730 emith_jump(sh2_drc_dispatcher);
2731
2732 // write-caused irq detection
2733 sh2_drc_write_end = tcache_ptr;
2734 emith_tst_r_r(arg0, arg0);
2735 EMITH_SJMP_START(DCOND_NE);
2736 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2737 EMITH_SJMP_END(DCOND_NE);
e05b81fc 2738 emith_call(sh2_drc_test_irq);
2739 emith_jump_ctx(offsetof(SH2, drc_tmp));
2740
2741 // write-caused irq detection for writes in delay slot
2742 sh2_drc_write_slot_end = tcache_ptr;
2743 emith_tst_r_r(arg0, arg0);
2744 EMITH_SJMP_START(DCOND_NE);
2745 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2746 EMITH_SJMP_END(DCOND_NE);
2747 // just burn cycles to get back to dispatcher after branch is handled
2748 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2749 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2750 emith_clear_msb(sr, sr, 20); // clear cycles
2751 rcache_flush();
2752 emith_jump_ctx(offsetof(SH2, drc_tmp));
2753
2754 // sh2_drc_write8(u32 a, u32 d)
2755 sh2_drc_write8 = (void *)tcache_ptr;
2756 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2757 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2758 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2759
2760 // sh2_drc_write16(u32 a, u32 d)
2761 sh2_drc_write16 = (void *)tcache_ptr;
2762 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2763 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2764 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2765
2766 // sh2_drc_write8_slot(u32 a, u32 d)
2767 sh2_drc_write8_slot = (void *)tcache_ptr;
2768 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2769 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2770 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2771
2772 // sh2_drc_write16_slot(u32 a, u32 d)
2773 sh2_drc_write16_slot = (void *)tcache_ptr;
2774 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2775 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2776 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2777
5686d931 2778#ifdef PDB_NET
2779 // debug
2780 #define MAKE_READ_WRAPPER(func) { \
2781 void *tmp = (void *)tcache_ptr; \
a2b8c5a5 2782 emith_push_ret(); \
5686d931 2783 emith_call(func); \
2784 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2785 emith_addf_r_r(arg2, arg0); \
2786 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2787 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2788 emith_adc_r_imm(arg2, 0x01000000); \
2789 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
a2b8c5a5 2790 emith_pop_and_ret(); \
5686d931 2791 func = tmp; \
2792 }
2793 #define MAKE_WRITE_WRAPPER(func) { \
2794 void *tmp = (void *)tcache_ptr; \
2795 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2796 emith_addf_r_r(arg2, arg1); \
2797 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2798 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2799 emith_adc_r_imm(arg2, 0x01000000); \
2800 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2801 emith_move_r_r(arg2, CONTEXT_REG); \
2802 emith_jump(func); \
2803 func = tmp; \
2804 }
2805
2806 MAKE_READ_WRAPPER(sh2_drc_read8);
2807 MAKE_READ_WRAPPER(sh2_drc_read16);
2808 MAKE_READ_WRAPPER(sh2_drc_read32);
2809 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2810 MAKE_WRITE_WRAPPER(sh2_drc_write8_slot);
2811 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2812 MAKE_WRITE_WRAPPER(sh2_drc_write16_slot);
2813 MAKE_WRITE_WRAPPER(sh2_drc_write32);
fcdefcf6 2814#if (DRC_DEBUG & 4)
5686d931 2815 host_dasm_new_symbol(sh2_drc_read8);
2816 host_dasm_new_symbol(sh2_drc_read16);
2817 host_dasm_new_symbol(sh2_drc_read32);
2818 host_dasm_new_symbol(sh2_drc_write32);
2819#endif
2820#endif
2821
e05b81fc 2822 rcache_invalidate();
fcdefcf6 2823#if (DRC_DEBUG & 4)
e05b81fc 2824 host_dasm_new_symbol(sh2_drc_entry);
2825 host_dasm_new_symbol(sh2_drc_dispatcher);
2826 host_dasm_new_symbol(sh2_drc_exit);
2827 host_dasm_new_symbol(sh2_drc_test_irq);
2828 host_dasm_new_symbol(sh2_drc_write_end);
2829 host_dasm_new_symbol(sh2_drc_write_slot_end);
2830 host_dasm_new_symbol(sh2_drc_write8);
2831 host_dasm_new_symbol(sh2_drc_write8_slot);
2832 host_dasm_new_symbol(sh2_drc_write16);
2833 host_dasm_new_symbol(sh2_drc_write16_slot);
679af8a3 2834#endif
679af8a3 2835}
2836
a2b8c5a5 2837static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id)
f4bb5d6b 2838{
04092e32 2839 void *tmp;
2840
a2b8c5a5 2841 // XXX: kill links somehow?
fcdefcf6 2842 dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]);
04092e32 2843 if (bd->addr == 0 || bd->tcache_ptr == NULL) {
fcdefcf6 2844 dbg(1, " killing dead block!? %08x", bd->addr);
04092e32 2845 return bd->tcache_ptr;
2846 }
2847
a2b8c5a5 2848 // since we never reuse space of dead blocks,
2849 // insert jump to dispatcher for blocks that are linked to this point
04092e32 2850 //emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher);
2851
2852 // attempt to handle self-modifying blocks by exiting at nearest known PC
2853 tmp = tcache_ptr;
2854 tcache_ptr = bd->tcache_ptr;
2855 emit_move_r_imm32(SHR_PC, bd->addr);
2856 rcache_flush();
2857 emith_jump(sh2_drc_dispatcher);
2858 tcache_ptr = tmp;
2859
2860 bd->addr = 0;
a2b8c5a5 2861 return bd->tcache_ptr;
2862}
f4bb5d6b 2863
a2b8c5a5 2864static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2865{
2866 //block_link *bl = block_links[tcache_id];
2867 //int bl_count = block_link_counts[tcache_id];
2868 block_desc *btab = block_tables[tcache_id];
2869 u16 *p = drc_ram_blk + ((a & mask) >> shift);
04092e32 2870 u16 *pmax = drc_ram_blk + (mask >> shift);
a2b8c5a5 2871 void *tcache_min, *tcache_max;
04092e32 2872 int zeros;
2873 u16 *pt;
2874
2875 // Figure out what the main block is, as subblocks also have the flag set.
2876 // This relies on sub having single entry. It's possible that innocent
2877 // block might be hit, but that's not such a big deal.
2878 if ((p[0] >> 1) != (p[1] >> 1)) {
2879 for (; p > drc_ram_blk; p--)
2880 if (p[-1] == 0 || (p[-1] >> 1) == (*p >> 1))
2881 break;
2882 }
2883 pt = p;
a2b8c5a5 2884
04092e32 2885 for (; p > drc_ram_blk; p--)
2886 if ((*p & 1))
2887 break;
f4bb5d6b 2888
04092e32 2889 if (!(*p & 1)) {
fcdefcf6 2890 dbg(1, "smc rm: missing block start for %08x?", a);
04092e32 2891 p = pt;
2892 }
2893
2894 if (*p == 0)
2895 return;
2896
2897 tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id);
2898 *p = 0;
a2b8c5a5 2899
04092e32 2900 for (p++, zeros = 0; p < pmax && zeros < MAX_LITERAL_OFFSET / 2; p++) {
a2b8c5a5 2901 int id = *p >> 1;
04092e32 2902 if (id == 0) {
2903 // there can be holes because games sometimes keep variables
2904 // directly in literal pool and we don't inline them to avoid recompile
2905 // (Star Wars Arcade)
2906 zeros++;
2907 continue;
2908 }
2909 if (*p & 1) {
2910 if (id == (p[1] >> 1))
2911 // hit other block
2912 break;
2913 tcache_max = sh2_smc_rm_block_entry(&btab[id], tcache_id);
2914 }
a2b8c5a5 2915 *p = 0;
f4bb5d6b 2916 }
2917
04092e32 2918 host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4*4 + 4));
f4bb5d6b 2919}
2920
2921void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2922{
fcdefcf6 2923 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
a2b8c5a5 2924 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
f4bb5d6b 2925}
2926
2927void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2928{
fcdefcf6 2929 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
a2b8c5a5 2930 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
2931 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
f4bb5d6b 2932}
2933
ed4402a7 2934int sh2_execute(SH2 *sh2c, int cycles)
679af8a3 2935{
e05b81fc 2936 int ret_cycles;
52d759c3 2937
ed4402a7 2938 sh2c->cycles_timeslice = cycles;
679af8a3 2939
2940 // cycles are kept in SHR_SR unused bits (upper 20)
65514d85 2941 // bit11 contains T saved for delay slot
18b94127 2942 // others are usual SH2 flags
52d759c3 2943 sh2c->sr &= 0x3f3;
2944 sh2c->sr |= cycles << 12;
e05b81fc 2945 sh2_drc_entry(sh2c);
679af8a3 2946
e05b81fc 2947 // TODO: irq cycles
2948 ret_cycles = (signed int)sh2c->sr >> 12;
2949 if (ret_cycles > 0)
fcdefcf6 2950 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
679af8a3 2951
ed4402a7 2952 return sh2c->cycles_timeslice - ret_cycles;
679af8a3 2953}
2954
fcdefcf6 2955#if (DRC_DEBUG & 2)
9bb5d91c 2956void block_stats(void)
f4bb5d6b 2957{
2958 int c, b, i, total = 0;
2959
9bb5d91c 2960 printf("block stats:\n");
f4bb5d6b 2961 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2962 for (i = 0; i < block_counts[b]; i++)
2963 if (block_tables[b][i].addr != 0)
2964 total += block_tables[b][i].refcount;
2965
2966 for (c = 0; c < 10; c++) {
2967 block_desc *blk, *maxb = NULL;
2968 int max = 0;
2969 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
2970 for (i = 0; i < block_counts[b]; i++) {
2971 blk = &block_tables[b][i];
2972 if (blk->addr != 0 && blk->refcount > max) {
2973 max = blk->refcount;
2974 maxb = blk;
2975 }
2976 }
2977 }
2978 if (maxb == NULL)
2979 break;
2980 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
2981 (double)maxb->refcount / total * 100.0);
2982 maxb->refcount = 0;
2983 }
553c3eaa 2984
2985 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2986 for (i = 0; i < block_counts[b]; i++)
2987 block_tables[b][i].refcount = 0;
f4bb5d6b 2988}
553c3eaa 2989#else
2990#define block_stats()
f4bb5d6b 2991#endif
2992
553c3eaa 2993void sh2_drc_flush_all(void)
2994{
2995 block_stats();
2996 flush_tcache(0);
2997 flush_tcache(1);
2998 flush_tcache(2);
2999}
3000
23686515 3001void sh2_drc_mem_setup(SH2 *sh2)
3002{
3003 // fill the convenience pointers
3004 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3005 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3006 sh2->p_sdram = Pico32xMem->sdram;
3007 sh2->p_rom = Pico.rom;
3008}
3009
679af8a3 3010int sh2_drc_init(SH2 *sh2)
3011{
44e6452e 3012 int i;
7f5a3fc1 3013
44e6452e 3014 if (block_tables[0] == NULL)
3015 {
3016 for (i = 0; i < TCACHE_BUFFERS; i++) {
3017 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3018 if (block_tables[i] == NULL)
3019 goto fail;
3020 // max 2 block links (exits) per block
3021 block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0]));
3022 if (block_links[i] == NULL)
3023 goto fail;
3024 }
3025 memset(block_counts, 0, sizeof(block_counts));
3026 memset(block_link_counts, 0, sizeof(block_link_counts));
e898de13 3027
44e6452e 3028 drc_cmn_init();
8796b7ee 3029 tcache_ptr = tcache;
3030 sh2_generate_utils();
a2b8c5a5 3031 host_instructions_updated(tcache, tcache_ptr);
8796b7ee 3032
8796b7ee 3033 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
44e6452e 3034 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
f4bb5d6b 3035 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
f4bb5d6b 3036
553c3eaa 3037 // tmp
3038 PicoOpt |= POPT_DIS_VDP_FIFO;
3039
fcdefcf6 3040#if (DRC_DEBUG & 4)
f4bb5d6b 3041 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3042 tcache_dsm_ptrs[i] = tcache_bases[i];
8796b7ee 3043 // disasm the utils
3044 tcache_dsm_ptrs[0] = tcache;
3045 do_host_disasm(0);
f4bb5d6b 3046#endif
e898de13 3047#if (DRC_DEBUG & 1)
3048 hash_collisions = 0;
3049#endif
679af8a3 3050 }
3051
f4bb5d6b 3052 if (hash_table == NULL) {
3053 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
3054 if (hash_table == NULL)
44e6452e 3055 goto fail;
f4bb5d6b 3056 }
41397701 3057
679af8a3 3058 return 0;
44e6452e 3059
3060fail:
3061 sh2_drc_finish(sh2);
3062 return -1;
41397701 3063}
3064
e898de13 3065void sh2_drc_finish(SH2 *sh2)
3066{
44e6452e 3067 int i;
3068
f4bb5d6b 3069 if (block_tables[0] != NULL) {
f4bb5d6b 3070 block_stats();
44e6452e 3071
3072 for (i = 0; i < TCACHE_BUFFERS; i++) {
fcdefcf6 3073#if (DRC_DEBUG & 4)
44e6452e 3074 printf("~~~ tcache %d\n", i);
3075 tcache_dsm_ptrs[i] = tcache_bases[i];
3076 tcache_ptr = tcache_ptrs[i];
3077 do_host_disasm(i);
3078#endif
3079
3080 if (block_tables[i] != NULL)
3081 free(block_tables[i]);
3082 block_tables[i] = NULL;
3083 if (block_links[i] == NULL)
3084 free(block_links[i]);
3085 block_links[i] = NULL;
3086 }
7f5a3fc1 3087
3088 drc_cmn_cleanup();
e898de13 3089 }
3090
f4bb5d6b 3091 if (hash_table != NULL) {
3092 free(hash_table);
3093 hash_table = NULL;
3094 }
e898de13 3095}
cff531af 3096
00faec9c 3097#endif /* DRC_SH2 */
3098
3099static void *dr_get_pc_base(u32 pc, int is_slave)
3100{
3101 void *ret = NULL;
3102 u32 mask = 0;
3103
3104 if ((pc & ~0x7ff) == 0) {
3105 // BIOS
3106 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3107 mask = 0x7ff;
3108 }
3109 else if ((pc & 0xfffff000) == 0xc0000000) {
3110 // data array
3111 ret = Pico32xMem->data_array[is_slave];
3112 mask = 0xfff;
3113 }
3114 else if ((pc & 0xc6000000) == 0x06000000) {
3115 // SDRAM
3116 ret = Pico32xMem->sdram;
3117 mask = 0x03ffff;
3118 }
3119 else if ((pc & 0xc6000000) == 0x02000000) {
3120 // ROM
3121 ret = Pico.rom;
3122 mask = 0x3fffff;
3123 }
3124
3125 if (ret == NULL)
3126 return (void *)-1; // NULL is valid value
3127
3128 return (char *)ret - (pc & ~mask);
3129}
3130
3131void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
3132{
3133 u16 *dr_pc_base;
3134 u32 pc, target, op;
3135 int cycles;
3136
3137 memset(op_flags, 0, BLOCK_CYCLE_LIMIT);
3138
3139 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3140
3141 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) {
3142 op = FETCH_OP(pc);
3143 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
3144 signed int offs = ((signed int)(op << 20) >> 19);
3145 pc += 2;
3146 OP_FLAGS(pc) |= OF_DELAY_OP;
3147 target = pc + offs + 2;
3148 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3149 OP_FLAGS(target) |= OF_TARGET;
3150 break;
3151 }
3152 if ((op & 0xf000) == 0) {
3153 op &= 0xff;
3154 if (op == 0x1b) // SLEEP
3155 break;
3156 // BRAF, BSRF, RTS, RTE
3157 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
3158 pc += 2;
3159 OP_FLAGS(pc) |= OF_DELAY_OP;
3160 break;
3161 }
3162 continue;
3163 }
3164 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
3165 pc += 2;
3166 OP_FLAGS(pc) |= OF_DELAY_OP;
3167 break;
3168 }
3169 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
3170 signed int offs = ((signed int)(op << 24) >> 23);
3171 if (op & 0x0400)
3172 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
3173 target = pc + offs + 4;
3174 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3175 OP_FLAGS(target) |= OF_TARGET;
3176 }
3177 if ((op & 0xff00) == 0xc300) // TRAPA
3178 break;
3179 }
3180 *end_pc = pc;
3181}
3182
cff531af 3183// vim:shiftwidth=2:expandtab
fast MegaDrive/MegaCD/32X emulator