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32x: drc: all opcodes covered, some TODOs left
[picodrive.git] / pico / 32x / memory.c
CommitLineData
83ff19ec 1/*
bcf65fd6 2 * SH2 addr lines:
3 * iii. .cc. ..xx * // Internal, Cs, x
4 *
83ff19ec 5 * Register map:
6 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
7 * a15102 ........ ......SM ? 4002 // intS intM
8 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
9 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
10 * a15108 (32bit DREQ src) 4008
11 * a1510c (32bit DREQ dst) 400c
12 * a15110 llllllll llllll00 4010 // DREQ Len
13 * a15112 (16bit FIFO reg) 4012
14 * a15114 ? (16bit VRES clr) 4014
15 * a15116 ? (16bit Vint clr) 4016
16 * a15118 ? (16bit Hint clr) 4018
17 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
18 * a1511c ? (16bit PWM clr) 401c
19 * a1511e ? ? 401e
20 * a15120 (16 bytes comm) 2020
21 * a15130 (PWM) 2030
22 */
be2c4208 23#include "../pico_int.h"
24#include "../memory.h"
f4bb5d6b 25#ifdef DRC_SH2
26#include "../../cpu/sh2/compiler.h"
27#endif
be2c4208 28
236990cf 29#if 0
c987bb5c 30#undef ash2_end_run
31#undef SekEndRun
32#define ash2_end_run(x)
33#define SekEndRun(x)
34#endif
35
be2c4208 36static const char str_mars[] = "MARS";
37
83ff19ec 38void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
974fdb5b 39struct Pico32xMem *Pico32xMem;
40
5e49c3a8 41static void bank_switch(int b);
42
266c6afa 43// poll detection
4ea707e1 44#define POLL_THRESHOLD 6
45
266c6afa 46struct poll_det {
be20816c 47 u32 addr, cycles, cyc_max;
48 int cnt, flag;
266c6afa 49};
b78efee2 50static struct poll_det m68k_poll, sh2_poll[2];
266c6afa 51
be20816c 52static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
266c6afa 53{
b78efee2 54 int ret = 0, flag = pd->flag;
55
56 if (is_vdp)
57 flag <<= 3;
266c6afa 58
1d7a28a7 59 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
266c6afa 60 pd->cnt++;
61 if (pd->cnt > POLL_THRESHOLD) {
62 if (!(Pico32x.emu_flags & flag)) {
be20816c 63 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
64 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
65 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
266c6afa 66 ret = 1;
67 }
68 Pico32x.emu_flags |= flag;
69 }
70 }
c987bb5c 71 else {
266c6afa 72 pd->cnt = 0;
c987bb5c 73 pd->addr = a;
74 }
be20816c 75 pd->cycles = cycles;
266c6afa 76
77 return ret;
78}
79
b78efee2 80static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
266c6afa 81{
b78efee2 82 int ret = 0, flag = pd->flag;
83 if (is_vdp)
be20816c 84 flag <<= 3; // VDP only
85 else
86 flag |= flag << 3; // both
87 if (Pico32x.emu_flags & flag) {
88 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
266c6afa 89 ret = 1;
be20816c 90 }
266c6afa 91 Pico32x.emu_flags &= ~flag;
be20816c 92 pd->addr = pd->cnt = 0;
266c6afa 93 return ret;
94}
95
87accdf7 96void p32x_poll_event(int cpu_mask, int is_vdp)
4ea707e1 97{
87accdf7 98 if (cpu_mask & 1)
99 p32x_poll_undetect(&sh2_poll[0], is_vdp);
100 if (cpu_mask & 2)
101 p32x_poll_undetect(&sh2_poll[1], is_vdp);
4ea707e1 102}
103
974fdb5b 104// SH2 faking
b78efee2 105//#define FAKE_SH2
acd35d4c 106int p32x_csum_faked;
107#ifdef FAKE_SH2
974fdb5b 108static const u16 comm_fakevals[] = {
109 0x4d5f, 0x4f4b, // M_OK
110 0x535f, 0x4f4b, // S_OK
5e49c3a8 111 0x4D41, 0x5346, // MASF - Brutal Unleashed
112 0x5331, 0x4d31, // Darxide
113 0x5332, 0x4d32,
114 0x5333, 0x4d33,
115 0x0000, 0x0000, // eq for doom
974fdb5b 116 0x0002, // Mortal Kombat
acd35d4c 117// 0, // pad
be2c4208 118};
acd35d4c 119
120static u32 sh2_comm_faker(u32 a)
121{
122 static int f = 0;
123 if (a == 0x28 && !p32x_csum_faked) {
124 p32x_csum_faked = 1;
125 return *(unsigned short *)(Pico.rom + 0x18e);
126 }
127 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
128 f = 0;
129 return comm_fakevals[f++];
130}
131#endif
be2c4208 132
4ea707e1 133// DMAC handling
134static struct {
135 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
136 unsigned int chcr0; // chan ctl
137 unsigned int sar1, dar1, tcr1; // same for chan 1
138 unsigned int chcr1;
139 int pad[4];
140 unsigned int dmaor;
141} * dmac0;
142
143static void dma_68k2sh2_do(void)
144{
145 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
146 int i;
147
148 if (dmac0->tcr0 != *dreqlen)
149 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
150
1b3f5844 151 // HACK: assume bus is busy and SH2 is halted
152 // XXX: use different mechanism for this, not poll det
153 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
154
4ea707e1 155 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
bcf65fd6 156 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
157 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
4ea707e1 158 dmac0->dar0 += 2;
159 dmac0->tcr0--;
160 (*dreqlen)--;
161 }
162
163 Pico32x.dmac_ptr = 0; // HACK
164 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
165 if (*dreqlen == 0)
166 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
be20816c 167 if (dmac0->tcr0 == 0) {
4ea707e1 168 dmac0->chcr0 |= 2; // DMA has ended normally
be20816c 169 p32x_poll_undetect(&sh2_poll[0], 0);
170 }
4ea707e1 171}
172
173// ------------------------------------------------------------------
b78efee2 174// 68k regs
4ea707e1 175
be2c4208 176static u32 p32x_reg_read16(u32 a)
177{
178 a &= 0x3e;
179
87accdf7 180 if (a == 2) // INTM, INTS
181 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
3cf9570b 182#if 0
974fdb5b 183 if ((a & 0x30) == 0x20)
acd35d4c 184 return sh2_comm_faker(a);
266c6afa 185#else
5fadfb1c 186 if ((a & 0x30) == 0x20) {
187 // evil X-Men proto polls in a dbra loop and expects it to expire..
188 static u32 dr2 = 0;
189 if (SekDar(2) != dr2)
190 m68k_poll.cnt = 0;
191 dr2 = SekDar(2);
192
193 if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
194 SekSetStop(1);
195 SekEndTimeslice(16);
196 }
197 dr2 = SekDar(2);
266c6afa 198 }
acd35d4c 199#endif
87accdf7 200
db1d3564 201 if ((a & 0x30) == 0x30)
202 return p32x_pwm_read16(a);
974fdb5b 203
be2c4208 204 return Pico32x.regs[a / 2];
205}
206
be2c4208 207static void p32x_reg_write8(u32 a, u32 d)
208{
acd35d4c 209 u16 *r = Pico32x.regs;
be2c4208 210 a &= 0x3f;
211
97d3f47f 212 // for things like bset on comm port
213 m68k_poll.cnt = 0;
214
acd35d4c 215 switch (a) {
4ea707e1 216 case 0: // adapter ctl
83ff19ec 217 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
218 return;
219 case 1: // adapter ctl, RES bit writeable
220 if ((d ^ r[0]) & d & P32XS_nRES)
221 p32x_reset_sh2s();
222 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
1b3f5844 223 return;
4ea707e1 224 case 3: // irq ctl
225 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
226 Pico32x.sh2irqi[0] |= P32XI_CMD;
227 p32x_update_irls();
87accdf7 228 SekEndRun(16);
4ea707e1 229 }
b78efee2 230 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
231 Pico32x.sh2irqi[1] |= P32XI_CMD;
232 p32x_update_irls();
87accdf7 233 SekEndRun(16);
b78efee2 234 }
1b3f5844 235 return;
4ea707e1 236 case 5: // bank
acd35d4c 237 d &= 7;
4ea707e1 238 if (r[4 / 2] != d) {
239 r[4 / 2] = d;
acd35d4c 240 bank_switch(d);
241 }
1b3f5844 242 return;
4ea707e1 243 case 7: // DREQ ctl
97d3f47f 244 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
1b3f5844 245 return;
87accdf7 246 case 0x1b: // TV
247 r[0x1a / 2] = d;
1b3f5844 248 return;
249 }
250
251 if ((a & 0x30) == 0x20) {
252 u8 *r8 = (u8 *)r;
253 r8[a ^ 1] = d;
236990cf 254 p32x_poll_undetect(&sh2_poll[0], 0);
255 p32x_poll_undetect(&sh2_poll[1], 0);
256 // if some SH2 is busy waiting, it needs to see the result ASAP
257 if (SekCyclesLeftNoMCD > 32)
258 SekEndRun(32);
1b3f5844 259 return;
5e49c3a8 260 }
261}
262
263static void p32x_reg_write16(u32 a, u32 d)
264{
acd35d4c 265 u16 *r = Pico32x.regs;
266 a &= 0x3e;
267
97d3f47f 268 // for things like bset on comm port
269 m68k_poll.cnt = 0;
270
acd35d4c 271 switch (a) {
4ea707e1 272 case 0x00: // adapter ctl
83ff19ec 273 if ((d ^ r[0]) & d & P32XS_nRES)
274 p32x_reset_sh2s();
275 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
acd35d4c 276 return;
4ea707e1 277 case 0x10: // DREQ len
278 r[a / 2] = d & ~3;
279 return;
280 case 0x12: // FIFO reg
281 if (!(r[6 / 2] & P32XS_68S)) {
282 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
283 return;
284 }
285 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
286 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
287 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
288 dma_68k2sh2_do();
289 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
290 r[6 / 2] |= P32XS_FULL;
291 }
292 break;
acd35d4c 293 }
294
4ea707e1 295 // DREQ src, dst
296 if ((a & 0x38) == 0x08) {
297 r[a / 2] = d;
298 return;
299 }
300 // comm port
301 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
acd35d4c 302 r[a / 2] = d;
236990cf 303 p32x_poll_undetect(&sh2_poll[0], 0);
304 p32x_poll_undetect(&sh2_poll[1], 0);
305 // same as for w8
306 if (SekCyclesLeftNoMCD > 32)
307 SekEndRun(32);
acd35d4c 308 return;
309 }
db1d3564 310 // PWM
311 else if ((a & 0x30) == 0x30) {
312 p32x_pwm_write16(a, d);
313 return;
314 }
acd35d4c 315
5e49c3a8 316 p32x_reg_write8(a + 1, d);
be2c4208 317}
318
4ea707e1 319// ------------------------------------------------------------------
be2c4208 320// VDP regs
321static u32 p32x_vdp_read16(u32 a)
322{
323 a &= 0x0e;
324
325 return Pico32x.vdp_regs[a / 2];
326}
327
be2c4208 328static void p32x_vdp_write8(u32 a, u32 d)
329{
974fdb5b 330 u16 *r = Pico32x.vdp_regs;
be2c4208 331 a &= 0x0f;
332
4ea707e1 333 // for FEN checks between writes
b78efee2 334 sh2_poll[0].cnt = 0;
4ea707e1 335
974fdb5b 336 // TODO: verify what's writeable
be2c4208 337 switch (a) {
974fdb5b 338 case 0x01:
5e49c3a8 339 // priority inversion is handled in palette
340 if ((r[0] ^ d) & P32XV_PRI)
341 Pico32x.dirty_pal = 1;
974fdb5b 342 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
be20816c 343 break;
344 case 0x05: // fill len
345 r[4 / 2] = d & 0xff;
974fdb5b 346 break;
be2c4208 347 case 0x0b:
974fdb5b 348 d &= 1;
349 Pico32x.pending_fb = d;
350 // if we are blanking and FS bit is changing
4ea707e1 351 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
974fdb5b 352 r[0x0a/2] ^= 1;
353 Pico32xSwapDRAM(d ^ 1);
266c6afa 354 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
be2c4208 355 }
356 break;
357 }
358}
359
974fdb5b 360static void p32x_vdp_write16(u32 a, u32 d)
361{
be20816c 362 a &= 0x0e;
363 if (a == 6) { // fill start
364 Pico32x.vdp_regs[6 / 2] = d;
365 return;
366 }
367 if (a == 8) { // fill data
368 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
1b3f5844 369 int len = Pico32x.vdp_regs[4 / 2] + 1;
be20816c 370 a = Pico32x.vdp_regs[6 / 2];
371 while (len--) {
372 dram[a] = d;
373 a = (a & 0xff00) | ((a + 1) & 0xff);
374 }
375 Pico32x.vdp_regs[6 / 2] = a;
376 Pico32x.vdp_regs[8 / 2] = d;
377 return;
378 }
379
974fdb5b 380 p32x_vdp_write8(a | 1, d);
381}
382
4ea707e1 383// ------------------------------------------------------------------
acd35d4c 384// SH2 regs
b78efee2 385
386static u32 p32x_sh2reg_read16(u32 a, int cpuid)
acd35d4c 387{
4ea707e1 388 u16 *r = Pico32x.regs;
389 a &= 0xfe; // ?
266c6afa 390
4ea707e1 391 switch (a) {
392 case 0x00: // adapter/irq ctl
87accdf7 393 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
c987bb5c 394 case 0x04: // H count (often as comm too)
395 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
396 ash2_end_run(8);
87accdf7 397 return Pico32x.sh2_regs[4 / 2];
4ea707e1 398 case 0x10: // DREQ len
399 return r[a / 2];
acd35d4c 400 }
4ea707e1 401
db1d3564 402 // DREQ src, dst
403 if ((a & 0x38) == 0x08)
4ea707e1 404 return r[a / 2];
db1d3564 405 // comm port
406 if ((a & 0x30) == 0x20) {
be20816c 407 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
db1d3564 408 ash2_end_run(8);
409 return r[a / 2];
410 }
411 if ((a & 0x30) == 0x30) {
412 sh2_poll[cpuid].cnt = 0;
413 return p32x_pwm_read16(a);
414 }
acd35d4c 415
416 return 0;
417}
418
b78efee2 419static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
acd35d4c 420{
4ea707e1 421 a &= 0xff;
87accdf7 422 switch (a) {
423 case 0: // FM
424 Pico32x.regs[0] &= ~P32XS_FM;
425 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
1b3f5844 426 return;
87accdf7 427 case 1: //
428 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
429 Pico32x.sh2_regs[0] &= ~0x80;
430 Pico32x.sh2_regs[0] |= d & 0x80;
431 p32x_update_irls();
1b3f5844 432 return;
87accdf7 433 case 5: // H count
434 Pico32x.sh2_regs[4 / 2] = d & 0xff;
c987bb5c 435 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
1b3f5844 436 return;
437 }
438
439 if ((a & 0x30) == 0x20) {
440 u8 *r8 = (u8 *)Pico32x.regs;
441 r8[a ^ 1] = d;
5fadfb1c 442 if (p32x_poll_undetect(&m68k_poll, 0))
443 SekSetStop(0);
1b3f5844 444 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
445 return;
4ea707e1 446 }
acd35d4c 447}
448
b78efee2 449static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
acd35d4c 450{
4ea707e1 451 a &= 0xfe;
acd35d4c 452
db1d3564 453 // comm
4ea707e1 454 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
b78efee2 455 Pico32x.regs[a / 2] = d;
5fadfb1c 456 if (p32x_poll_undetect(&m68k_poll, 0))
457 SekSetStop(0);
b78efee2 458 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
acd35d4c 459 return;
460 }
db1d3564 461 // PWM
462 else if ((a & 0x30) == 0x30) {
463 p32x_pwm_write16(a, d);
464 return;
465 }
acd35d4c 466
4ea707e1 467 switch (a) {
87accdf7 468 case 0: // FM
469 Pico32x.regs[0] &= ~P32XS_FM;
470 Pico32x.regs[0] |= d & P32XS_FM;
471 break;
4ea707e1 472 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
473 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
474 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
b78efee2 475 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
be20816c 476 case 0x1c:
477 Pico32x.sh2irqs &= ~P32XI_PWM;
1d7a28a7 478 p32x_timers_do(0);
be20816c 479 goto irls;
4ea707e1 480 }
481
b78efee2 482 p32x_sh2reg_write8(a | 1, d, cpuid);
4ea707e1 483 return;
484
485irls:
486 p32x_update_irls();
487}
488
87accdf7 489// ------------------------------------------------------------------
490// SH2 internal peripherals
1d7a28a7 491// we keep them in little endian format
87accdf7 492static u32 sh2_peripheral_read8(u32 a, int id)
493{
494 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
495 u32 d;
496
497 a &= 0x1ff;
1d7a28a7 498 d = PREG8(r, a);
87accdf7 499
500 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
501 return d;
502}
503
1d7a28a7 504static u32 sh2_peripheral_read16(u32 a, int id)
505{
506 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
507 u32 d;
508
509 a &= 0x1ff;
510 d = r[(a / 2) ^ 1];
511
512 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
513 return d;
514}
515
87accdf7 516static u32 sh2_peripheral_read32(u32 a, int id)
4ea707e1 517{
518 u32 d;
519 a &= 0x1fc;
97d3f47f 520 d = Pico32xMem->sh2_peri_regs[id][a / 4];
4ea707e1 521
97d3f47f 522 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
4ea707e1 523 return d;
acd35d4c 524}
525
87accdf7 526static void sh2_peripheral_write8(u32 a, u32 d, int id)
527{
528 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
529 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
530
531 a &= 0x1ff;
1d7a28a7 532 PREG8(r, a) = d;
533
534 // X-men SCI hack
535 if ((a == 2 && (d & 0x20)) || // transmiter enabled
536 (a == 4 && !(d & 0x80))) { // valid data in TDR
537 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
538 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
539 int level = PREG8(oregs, 0x60) >> 4;
540 int vector = PREG8(oregs, 0x63) & 0x7f;
541 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
542 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
543 }
544 }
545}
546
547static void sh2_peripheral_write16(u32 a, u32 d, int id)
548{
549 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
550 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
551
552 a &= 0x1ff;
553
554 // evil WDT
555 if (a == 0x80) {
556 if ((d & 0xff00) == 0xa500) { // WTCSR
557 PREG8(r, 0x80) = d;
558 p32x_timers_recalc();
559 }
560 if ((d & 0xff00) == 0x5a00) // WTCNT
561 PREG8(r, 0x81) = d;
562 return;
563 }
564
565 r[(a / 2) ^ 1] = d;
87accdf7 566}
567
568static void sh2_peripheral_write32(u32 a, u32 d, int id)
4ea707e1 569{
be20816c 570 u32 *r = Pico32xMem->sh2_peri_regs[id];
b78efee2 571 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
4ea707e1 572
573 a &= 0x1fc;
574 r[a / 4] = d;
575
97d3f47f 576 switch (a) {
be20816c 577 // division unit (TODO: verify):
97d3f47f 578 case 0x104: // DVDNT: divident L, starts divide
579 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
580 if (r[0x100 / 4]) {
be20816c 581 signed int divisor = r[0x100 / 4];
582 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
583 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
97d3f47f 584 }
1625ed01 585 else
586 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
97d3f47f 587 break;
588 case 0x114:
589 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
590 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
591 if (r[0x100 / 4]) {
be20816c 592 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
593 signed int divisor = r[0x100 / 4];
97d3f47f 594 // XXX: undocumented mirroring to 0x118,0x11c?
be20816c 595 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
1625ed01 596 divident /= divisor;
597 r[0x11c / 4] = r[0x114 / 4] = divident;
598 divident >>= 31;
599 if ((unsigned long long)divident + 1 > 1) {
600 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
601 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
602 }
97d3f47f 603 }
1625ed01 604 else
605 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
97d3f47f 606 break;
607 }
608
4ea707e1 609 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
610 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
b78efee2 611 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
4ea707e1 612 dmac0->tcr0 &= 0xffffff;
be20816c 613
1b3f5844 614 // HACK: assume 68k starts writing soon and end the timeslice
615 ash2_end_run(16);
be20816c 616
4ea707e1 617 // DREQ is only sent after first 4 words are written.
618 // we do multiple of 4 words to avoid messing up alignment
619 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
620 elprintf(EL_32X, "68k -> sh2 DMA");
621 dma_68k2sh2_do();
622 }
623 }
624}
625
626// ------------------------------------------------------------------
83ff19ec 627// 32x handlers
628
629// after ADEN
630static u32 PicoRead8_32x_on(u32 a)
be2c4208 631{
632 u32 d = 0;
633 if ((a & 0xffc0) == 0x5100) { // a15100
634 d = p32x_reg_read16(a);
635 goto out_16to8;
636 }
637
83ff19ec 638 if ((a & 0xfc00) != 0x5000)
639 return PicoRead8_io(a);
974fdb5b 640
641 if ((a & 0xfff0) == 0x5180) { // a15180
be2c4208 642 d = p32x_vdp_read16(a);
643 goto out_16to8;
644 }
645
974fdb5b 646 if ((a & 0xfe00) == 0x5200) { // a15200
647 d = Pico32xMem->pal[(a & 0x1ff) / 2];
648 goto out_16to8;
649 }
650
be2c4208 651 if ((a & 0xfffc) == 0x30ec) { // a130ec
652 d = str_mars[a & 3];
653 goto out;
654 }
655
656 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
657 return d;
658
659out_16to8:
660 if (a & 1)
661 d &= 0xff;
662 else
663 d >>= 8;
664
665out:
666 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
667 return d;
668}
669
83ff19ec 670static u32 PicoRead16_32x_on(u32 a)
be2c4208 671{
672 u32 d = 0;
673 if ((a & 0xffc0) == 0x5100) { // a15100
674 d = p32x_reg_read16(a);
675 goto out;
676 }
677
83ff19ec 678 if ((a & 0xfc00) != 0x5000)
679 return PicoRead16_io(a);
974fdb5b 680
681 if ((a & 0xfff0) == 0x5180) { // a15180
be2c4208 682 d = p32x_vdp_read16(a);
683 goto out;
684 }
685
974fdb5b 686 if ((a & 0xfe00) == 0x5200) { // a15200
687 d = Pico32xMem->pal[(a & 0x1ff) / 2];
688 goto out;
689 }
690
be2c4208 691 if ((a & 0xfffc) == 0x30ec) { // a130ec
692 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
693 goto out;
694 }
695
696 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
697 return d;
698
699out:
700 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
701 return d;
702}
703
83ff19ec 704static void PicoWrite8_32x_on(u32 a, u32 d)
be2c4208 705{
706 if ((a & 0xfc00) == 0x5000)
707 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
708
709 if ((a & 0xffc0) == 0x5100) { // a15100
710 p32x_reg_write8(a, d);
711 return;
712 }
713
83ff19ec 714 if ((a & 0xfc00) != 0x5000) {
715 PicoWrite8_io(a, d);
716 return;
717 }
974fdb5b 718
719 if ((a & 0xfff0) == 0x5180) { // a15180
be2c4208 720 p32x_vdp_write8(a, d);
721 return;
722 }
723
974fdb5b 724 // TODO: verify
725 if ((a & 0xfe00) == 0x5200) { // a15200
726 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
727 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
728 Pico32x.dirty_pal = 1;
729 return;
730 }
731
be2c4208 732 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
733}
734
83ff19ec 735static void PicoWrite16_32x_on(u32 a, u32 d)
be2c4208 736{
737 if ((a & 0xfc00) == 0x5000)
553c3eaa 738 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
be2c4208 739
740 if ((a & 0xffc0) == 0x5100) { // a15100
741 p32x_reg_write16(a, d);
742 return;
743 }
744
83ff19ec 745 if ((a & 0xfc00) != 0x5000) {
746 PicoWrite16_io(a, d);
747 return;
748 }
974fdb5b 749
750 if ((a & 0xfff0) == 0x5180) { // a15180
be2c4208 751 p32x_vdp_write16(a, d);
752 return;
753 }
754
974fdb5b 755 if ((a & 0xfe00) == 0x5200) { // a15200
756 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
757 Pico32x.dirty_pal = 1;
758 return;
759 }
760
be2c4208 761 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
762}
763
83ff19ec 764// before ADEN
765u32 PicoRead8_32x(u32 a)
766{
767 u32 d = 0;
768 if ((a & 0xffc0) == 0x5100) { // a15100
769 // regs are always readable
770 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
771 goto out;
772 }
773
774 if ((a & 0xfffc) == 0x30ec) { // a130ec
775 d = str_mars[a & 3];
776 goto out;
777 }
778
779 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
780 return d;
781
782out:
783 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
784 return d;
785}
786
787u32 PicoRead16_32x(u32 a)
788{
789 u32 d = 0;
790 if ((a & 0xffc0) == 0x5100) { // a15100
791 d = Pico32x.regs[(a & 0x3f) / 2];
792 goto out;
793 }
794
795 if ((a & 0xfffc) == 0x30ec) { // a130ec
796 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
797 goto out;
798 }
799
800 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
801 return d;
802
803out:
804 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
805 return d;
806}
807
808void PicoWrite8_32x(u32 a, u32 d)
809{
810 if ((a & 0xffc0) == 0x5100) { // a15100
811 u16 *r = Pico32x.regs;
812
813 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
814 a &= 0x3f;
815 if (a == 1) {
816 if ((d ^ r[0]) & d & P32XS_ADEN) {
817 Pico32xStartup();
818 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
819 r[0] |= P32XS_ADEN;
820 p32x_reg_write8(a, d); // forward for reset processing
821 }
822 return;
823 }
824
825 // allow only COMM for now
826 if ((a & 0x30) == 0x20) {
827 u8 *r8 = (u8 *)r;
828 r8[a ^ 1] = d;
829 }
830 return;
831 }
832
833 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
834}
835
836void PicoWrite16_32x(u32 a, u32 d)
837{
838 if ((a & 0xffc0) == 0x5100) { // a15100
839 u16 *r = Pico32x.regs;
840
841 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
842 a &= 0x3e;
843 if (a == 0) {
844 if ((d ^ r[0]) & d & P32XS_ADEN) {
845 Pico32xStartup();
846 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
847 r[0] |= P32XS_ADEN;
848 p32x_reg_write16(a, d); // forward for reset processing
849 }
850 return;
851 }
852
853 // allow only COMM for now
854 if ((a & 0x30) == 0x20)
855 r[a / 2] = d;
856 return;
857 }
858
859 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
860}
861
862// -----------------------------------------------------------------
863
be2c4208 864// hint vector is writeable
865static void PicoWrite8_hint(u32 a, u32 d)
866{
867 if ((a & 0xfffc) == 0x0070) {
868 Pico32xMem->m68k_rom[a ^ 1] = d;
869 return;
870 }
871
872 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
873}
874
875static void PicoWrite16_hint(u32 a, u32 d)
876{
877 if ((a & 0xfffc) == 0x0070) {
878 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
879 return;
880 }
881
882 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
883}
884
5e49c3a8 885static void bank_switch(int b)
886{
887 unsigned int rs, bank;
888
889 bank = b << 20;
890 if (bank >= Pico.romsize) {
891 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
892 return;
893 }
894
895 // 32X ROM (unbanked, XXX: consider mirroring?)
896 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
897 rs -= bank;
898 if (rs > 0x100000)
899 rs = 0x100000;
900 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
901 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
902
903 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
602c28ca 904
905#ifdef EMU_F68K
906 // setup FAME fetchmap
907 for (rs = 0x90; rs < 0xa0; rs++)
908 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
909#endif
5e49c3a8 910}
911
acd35d4c 912// -----------------------------------------------------------------
913// SH2
914// -----------------------------------------------------------------
915
bcf65fd6 916// read8
917static u32 sh2_read8_unmapped(u32 a, int id)
acd35d4c 918{
bcf65fd6 919 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
920 id ? 's' : 'm', a, 0, sh2_pc(id));
921 return 0;
922}
b78efee2 923
bcf65fd6 924static u32 sh2_read8_cs0(u32 a, int id)
925{
926 u32 d = 0;
97d3f47f 927
bcf65fd6 928 // 0x3ff00 is veridied
929 if ((a & 0x3ff00) == 0x4000) {
b78efee2 930 d = p32x_sh2reg_read16(a, id);
db1d3564 931 goto out_16to8;
acd35d4c 932 }
933
bcf65fd6 934 if ((a & 0x3ff00) == 0x4100) {
acd35d4c 935 d = p32x_vdp_read16(a);
be20816c 936 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
db1d3564 937 ash2_end_run(8);
938 goto out_16to8;
acd35d4c 939 }
940
bcf65fd6 941 // TODO: mirroring?
942 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
943 return Pico32xMem->sh2_rom_m[a ^ 1];
944 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
945 return Pico32xMem->sh2_rom_s[a ^ 1];
946
947 if ((a & 0x3ff00) == 0x4200) {
acd35d4c 948 d = Pico32xMem->pal[(a & 0x1ff) / 2];
949 goto out_16to8;
950 }
951
bcf65fd6 952 return sh2_read8_unmapped(a, id);
acd35d4c 953
954out_16to8:
955 if (a & 1)
956 d &= 0xff;
957 else
958 d >>= 8;
959
b78efee2 960 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
961 id ? 's' : 'm', a, d, sh2_pc(id));
acd35d4c 962 return d;
963}
964
bcf65fd6 965static u32 sh2_read8_da(u32 a, int id)
acd35d4c 966{
bcf65fd6 967 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
968}
acd35d4c 969
bcf65fd6 970// read16
971static u32 sh2_read16_unmapped(u32 a, int id)
972{
973 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
974 id ? 's' : 'm', a, 0, sh2_pc(id));
975 return 0;
976}
b78efee2 977
bcf65fd6 978static u32 sh2_read16_cs0(u32 a, int id)
979{
980 u32 d = 0;
97d3f47f 981
bcf65fd6 982 if ((a & 0x3ff00) == 0x4000) {
b78efee2 983 d = p32x_sh2reg_read16(a, id);
1b3f5844 984 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
985 return d;
db1d3564 986 goto out;
acd35d4c 987 }
988
bcf65fd6 989 if ((a & 0x3ff00) == 0x4100) {
acd35d4c 990 d = p32x_vdp_read16(a);
be20816c 991 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
db1d3564 992 ash2_end_run(8);
993 goto out;
acd35d4c 994 }
995
bcf65fd6 996 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
997 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
998 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
999 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1000
1001 if ((a & 0x3ff00) == 0x4200) {
acd35d4c 1002 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1003 goto out;
1004 }
1005
bcf65fd6 1006 return sh2_read16_unmapped(a, id);
acd35d4c 1007
1008out:
b78efee2 1009 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1010 id ? 's' : 'm', a, d, sh2_pc(id));
acd35d4c 1011 return d;
1012}
1013
bcf65fd6 1014static u32 sh2_read16_da(u32 a, int id)
acd35d4c 1015{
bcf65fd6 1016 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
acd35d4c 1017}
1018
bcf65fd6 1019// write8
1020static void sh2_write8_unmapped(u32 a, u32 d, int id)
acd35d4c 1021{
bcf65fd6 1022 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1023 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1024}
266c6afa 1025
bcf65fd6 1026static void sh2_write8_cs0(u32 a, u32 d, int id)
1027{
1028 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1029 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
b78efee2 1030
bcf65fd6 1031 if ((a & 0x3ff00) == 0x4100) {
acd35d4c 1032 p32x_vdp_write8(a, d);
1033 return;
1034 }
1035
bcf65fd6 1036 if ((a & 0x3ff00) == 0x4000) {
b78efee2 1037 p32x_sh2reg_write8(a, d, id);
acd35d4c 1038 return;
1039 }
1040
bcf65fd6 1041 sh2_write8_unmapped(a, d, id);
1042}
1043
1044#define sh2_write8_dramN(n) \
1045 if (!(a & 0x20000) || d) { \
1046 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1047 dram[(a & 0x1ffff) ^ 1] = d; \
87accdf7 1048 }
1049
bcf65fd6 1050static void sh2_write8_dram0(u32 a, u32 d, int id)
1051{
1052 sh2_write8_dramN(0);
acd35d4c 1053}
1054
bcf65fd6 1055static void sh2_write8_dram1(u32 a, u32 d, int id)
acd35d4c 1056{
bcf65fd6 1057 sh2_write8_dramN(1);
1058}
87accdf7 1059
f4bb5d6b 1060static void sh2_write8_sdram(u32 a, u32 d, int id)
1061{
1062 u32 a1 = a & 0x3ffff;
1063#ifdef DRC_SH2
1064 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1065 if (t)
1066 sh2_drc_wcheck_ram(a, t, id);
1067#endif
1068 Pico32xMem->sdram[a1 ^ 1] = d;
1069}
1070
bcf65fd6 1071static void sh2_write8_da(u32 a, u32 d, int id)
1072{
f4bb5d6b 1073 u32 a1 = a & 0xfff;
1074#ifdef DRC_SH2
1075 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1076 if (t)
1077 sh2_drc_wcheck_da(a, t, id);
1078#endif
1079 Pico32xMem->data_array[id][a1 ^ 1] = d;
bcf65fd6 1080}
acd35d4c 1081
bcf65fd6 1082// write16
1083static void sh2_write16_unmapped(u32 a, u32 d, int id)
1084{
1085 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1086 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1087}
b78efee2 1088
bcf65fd6 1089static void sh2_write16_cs0(u32 a, u32 d, int id)
1090{
1091 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1092 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1093 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
266c6afa 1094
bcf65fd6 1095 if ((a & 0x3ff00) == 0x4100) {
be20816c 1096 sh2_poll[id].cnt = 0; // for poll before VDP accesses
acd35d4c 1097 p32x_vdp_write16(a, d);
1098 return;
1099 }
1100
bcf65fd6 1101 if ((a & 0x3fe00) == 0x4200) {
acd35d4c 1102 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1103 Pico32x.dirty_pal = 1;
1104 return;
1105 }
1106
bcf65fd6 1107 if ((a & 0x3ff00) == 0x4000) {
b78efee2 1108 p32x_sh2reg_write16(a, d, id);
acd35d4c 1109 return;
1110 }
1111
bcf65fd6 1112 sh2_write16_unmapped(a, d, id);
1113}
1114
1115#define sh2_write16_dramN(n) \
1116 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1117 if (!(a & 0x20000)) { \
1118 *pd = d; \
1119 return; \
1120 } \
1121 /* overwrite */ \
1122 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1123 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1124 *pd = d
1125
1126static void sh2_write16_dram0(u32 a, u32 d, int id)
1127{
1128 sh2_write16_dramN(0);
1129}
1130
1131static void sh2_write16_dram1(u32 a, u32 d, int id)
1132{
1133 sh2_write16_dramN(1);
1134}
1135
f4bb5d6b 1136static void sh2_write16_sdram(u32 a, u32 d, int id)
1137{
1138 u32 a1 = a & 0x3ffff;
1139#ifdef DRC_SH2
1140 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1141 if (t)
1142 sh2_drc_wcheck_ram(a, t, id);
1143#endif
1144 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1145}
1146
bcf65fd6 1147static void sh2_write16_da(u32 a, u32 d, int id)
1148{
f4bb5d6b 1149 u32 a1 = a & 0xfff;
1150#ifdef DRC_SH2
1151 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1152 if (t)
1153 sh2_drc_wcheck_da(a, t, id);
1154#endif
1155 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
bcf65fd6 1156}
1157
1158
1159typedef struct {
1160 uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
1161 u32 mask;
1162} sh2_memmap;
1163
1164typedef u32 (sh2_read_handler)(u32 a, int id);
1165typedef void (sh2_write_handler)(u32 a, u32 d, int id);
1166
1167#define SH2MAP_ADDR2OFFS(a) \
1168 (((a >> 25) & 3) | ((a >> 27) & 0x1c))
1169
80599a42 1170u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
bcf65fd6 1171{
1172 const sh2_memmap *sh2_map = sh2->read8_map;
1173 uptr p;
1174
1175 sh2_map += SH2MAP_ADDR2OFFS(a);
1176 p = sh2_map->addr;
1177 if (p & (1 << 31))
1178 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1179 else
1180 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1181}
1182
80599a42 1183u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
bcf65fd6 1184{
1185 const sh2_memmap *sh2_map = sh2->read16_map;
1186 uptr p;
1187
1188 sh2_map += SH2MAP_ADDR2OFFS(a);
1189 p = sh2_map->addr;
1190 if (p & (1 << 31))
1191 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1192 else
1193 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1194}
1195
80599a42 1196u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
bcf65fd6 1197{
1198 const sh2_memmap *sh2_map = sh2->read16_map;
1199 sh2_read_handler *handler;
1200 u32 offs;
1201 uptr p;
1202
1203 offs = SH2MAP_ADDR2OFFS(a);
1204 sh2_map += offs;
1205 p = sh2_map->addr;
1206 if (!(p & (1 << 31))) {
1207 // XXX: maybe 32bit access instead with ror?
1208 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1209 return (pd[0] << 16) | pd[1];
1d7a28a7 1210 }
1211
bcf65fd6 1212 if (offs == 0x1f)
1213 return sh2_peripheral_read32(a, sh2->is_slave);
1214
1215 handler = (sh2_read_handler *)(p << 1);
1216 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1217}
1218
80599a42 1219void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
bcf65fd6 1220{
f4bb5d6b 1221 const void **sh2_wmap = sh2->write8_tab;
1222 sh2_write_handler *wh;
bcf65fd6 1223
f4bb5d6b 1224 wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
1225 wh(a, d, sh2->is_slave);
bcf65fd6 1226}
1227
80599a42 1228void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
bcf65fd6 1229{
f4bb5d6b 1230 const void **sh2_wmap = sh2->write16_tab;
1231 sh2_write_handler *wh;
bcf65fd6 1232
f4bb5d6b 1233 wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
1234 wh(a, d, sh2->is_slave);
acd35d4c 1235}
1236
80599a42 1237void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
acd35d4c 1238{
f4bb5d6b 1239 const void **sh2_wmap = sh2->write16_tab;
bcf65fd6 1240 sh2_write_handler *handler;
1241 u32 offs;
bcf65fd6 1242
1243 offs = SH2MAP_ADDR2OFFS(a);
bcf65fd6 1244
1245 if (offs == 0x1f) {
1246 sh2_peripheral_write32(a, d, sh2->is_slave);
4ea707e1 1247 return;
1248 }
1249
f4bb5d6b 1250 handler = sh2_wmap[offs];
bcf65fd6 1251 handler(a, d >> 16, sh2->is_slave);
1252 handler(a + 2, d, sh2->is_slave);
acd35d4c 1253}
1254
bcf65fd6 1255// -----------------------------------------------------------------
1256
83ff19ec 1257static const u16 msh2_code[] = {
1258 // trap instructions
1259 0xaffe, // bra <self>
1260 0x0009, // nop
1261 // have to wait a bit until m68k initial program finishes clearing stuff
1262 // to avoid races with game SH2 code, like in Tempo
1263 0xd004, // mov.l @(_m_ok,pc), r0
1264 0xd105, // mov.l @(_cnt,pc), r1
1265 0xd205, // mov.l @(_start,pc), r2
1266 0x71ff, // add #-1, r1
1267 0x4115, // cmp/pl r1
1268 0x89fc, // bt -2
1269 0xc208, // mov.l r0, @(h'20,gbr)
1270 0x6822, // mov.l @r2, r8
1271 0x482b, // jmp @r8
1272 0x0009, // nop
1273 ('M'<<8)|'_', ('O'<<8)|'K',
1274 0x0001, 0x0000,
1275 0x2200, 0x03e0 // master start pointer in ROM
1276};
1277
1278static const u16 ssh2_code[] = {
1279 0xaffe, // bra <self>
1280 0x0009, // nop
1281 // code to wait for master, in case authentic master BIOS is used
1282 0xd104, // mov.l @(_m_ok,pc), r1
1283 0xd206, // mov.l @(_start,pc), r2
1284 0xc608, // mov.l @(h'20,gbr), r0
1285 0x3100, // cmp/eq r0, r1
1286 0x8bfc, // bf #-2
1287 0xd003, // mov.l @(_s_ok,pc), r0
1288 0xc209, // mov.l r0, @(h'24,gbr)
1289 0x6822, // mov.l @r2, r8
1290 0x482b, // jmp @r8
1291 0x0009, // nop
1292 ('M'<<8)|'_', ('O'<<8)|'K',
1293 ('S'<<8)|'_', ('O'<<8)|'K',
1294 0x2200, 0x03e4 // slave start pointer in ROM
1295};
1296
be2c4208 1297#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
83ff19ec 1298static void get_bios(void)
be2c4208 1299{
83ff19ec 1300 u16 *ps;
1301 u32 *pl;
be2c4208 1302 int i;
1303
83ff19ec 1304 // M68K ROM
1305 if (p32x_bios_g != NULL) {
1306 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1307 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
be2c4208 1308 }
83ff19ec 1309 else {
1310 // generate 68k ROM
1311 ps = (u16 *)Pico32xMem->m68k_rom;
1312 pl = (u32 *)ps;
1313 for (i = 1; i < 0xc0/4; i++)
1314 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
be2c4208 1315
83ff19ec 1316 // fill with nops
1317 for (i = 0xc0/2; i < 0x100/2; i++)
1318 ps[i] = 0x4e71;
be2c4208 1319
5e49c3a8 1320#if 0
83ff19ec 1321 ps[0xc0/2] = 0x46fc;
1322 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1323 ps[0xfe/2] = 0x60fe; // jump to self
5e49c3a8 1324#else
83ff19ec 1325 ps[0xfe/2] = 0x4e75; // rts
5e49c3a8 1326#endif
83ff19ec 1327 }
1328 // fill remaining m68k_rom page with game ROM
974fdb5b 1329 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
be2c4208 1330
83ff19ec 1331 // MSH2
1332 if (p32x_bios_m != NULL) {
1333 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1334 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
acd35d4c 1335 }
83ff19ec 1336 else {
1337 pl = (u32 *)Pico32xMem->sh2_rom_m;
1338
1339 // fill exception vector table to our trap address
1340 for (i = 0; i < 128; i++)
1341 pl[i] = HWSWAP(0x200);
1342
1343 // startup code
1344 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1345
1346 // reset SP
1347 pl[1] = pl[3] = HWSWAP(0x6040000);
1348 // start
1349 pl[0] = pl[2] = HWSWAP(0x204);
1350 }
1351
1352 // SSH2
1353 if (p32x_bios_s != NULL) {
1354 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1355 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1356 }
1357 else {
1358 pl = (u32 *)Pico32xMem->sh2_rom_s;
1359
1360 // fill exception vector table to our trap address
1361 for (i = 0; i < 128; i++)
1362 pl[i] = HWSWAP(0x200);
1363
1364 // startup code
1365 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1366
1367 // reset SP
1368 pl[1] = pl[3] = HWSWAP(0x603f800);
1369 // start
1370 pl[0] = pl[2] = HWSWAP(0x204);
1371 }
1372}
1373
bcf65fd6 1374#define MAP_MEMORY(m) ((uptr)(m) >> 1)
1375#define MAP_HANDLER(h) (((uptr)(h) >> 1) | (1 << 31))
1376
1377static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
f4bb5d6b 1378// for writes we are using handlers only
1379static void *sh2_write8_map[0x20], *sh2_write16_map[0x20];
bcf65fd6 1380
1381void Pico32xSwapDRAM(int b)
1382{
1383 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1384 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1385 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1386 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1387
1388 // SH2
1389 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1390 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1391
f4bb5d6b 1392 sh2_write8_map[2] = sh2_write8_map[6] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1393 sh2_write16_map[2] = sh2_write16_map[6] = b ? sh2_write16_dram1 : sh2_write16_dram0;
bcf65fd6 1394}
1395
83ff19ec 1396void PicoMemSetup32x(void)
1397{
1398 unsigned int rs;
bcf65fd6 1399 int i;
83ff19ec 1400
1401 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
1402 if (Pico32xMem == NULL) {
1403 elprintf(EL_STATUS, "OOM");
1404 return;
1405 }
1406
1407 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1408
1409 get_bios();
acd35d4c 1410
be2c4208 1411 // cartridge area becomes unmapped
1412 // XXX: we take the easy way and don't unmap ROM,
1413 // so that we can avoid handling the RV bit.
1414 // m68k_map_unmap(0x000000, 0x3fffff);
1415
1416 // MD ROM area
974fdb5b 1417 rs = sizeof(Pico32xMem->m68k_rom);
1418 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1419 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1420 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1421 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1422
be2c4208 1423 // 32X ROM (unbanked, XXX: consider mirroring?)
5e49c3a8 1424 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1425 if (rs > 0x80000)
1426 rs = 0x80000;
1427 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1428 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
602c28ca 1429#ifdef EMU_F68K
1430 // setup FAME fetchmap
1431 PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
1432 for (rs = 0x88; rs < 0x90; rs++)
1433 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
1434#endif
be2c4208 1435
1436 // 32X ROM (banked)
5e49c3a8 1437 bank_switch(0);
b78efee2 1438
83ff19ec 1439 // SYS regs
1440 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1441 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1442 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1443 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1444
bcf65fd6 1445 // SH2 maps: A31,A30,A29,CS1,CS0
1446 // all unmapped by default
1447 for (i = 0; i < 0x20; i++) {
1448 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1449 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
f4bb5d6b 1450 sh2_write8_map[i] = sh2_write8_unmapped;
1451 sh2_write16_map[i] = sh2_write16_unmapped;
bcf65fd6 1452 }
1453
1454 // CS0
1455 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1456 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
f4bb5d6b 1457 sh2_write8_map[0] = sh2_write8_map[4] = sh2_write8_cs0;
1458 sh2_write16_map[0] = sh2_write16_map[4] = sh2_write16_cs0;
bcf65fd6 1459 // CS1 - ROM
1460 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1461 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1462 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1463 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1464 // CS2 - DRAM - done by Pico32xSwapDRAM()
1465 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1466 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1467 // CS3 - SDRAM
1468 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
f4bb5d6b 1469 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1470 sh2_write8_map[3] = sh2_write8_map[7] = sh2_write8_sdram;
1471 sh2_write16_map[3] = sh2_write16_map[7] = sh2_write16_sdram;
bcf65fd6 1472 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
f4bb5d6b 1473 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
bcf65fd6 1474 // SH2 data array
1475 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1476 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
f4bb5d6b 1477 sh2_write8_map[0x18] = sh2_write8_da;
1478 sh2_write16_map[0x18] = sh2_write16_da;
bcf65fd6 1479 // SH2 IO
1480 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1481 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
f4bb5d6b 1482 sh2_write8_map[0x1f] = sh2_peripheral_write8;
1483 sh2_write16_map[0x1f] = sh2_peripheral_write16;
bcf65fd6 1484
1485 // map DRAM area, both 68k and SH2
1486 Pico32xSwapDRAM(1);
1487
1488 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1489 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
f4bb5d6b 1490 msh2.write8_tab = ssh2.write8_tab = (const void **)sh2_write8_map;
1491 msh2.write16_tab = ssh2.write16_tab = (const void **)sh2_write16_map;
bcf65fd6 1492
b78efee2 1493 // setup poll detector
1494 m68k_poll.flag = P32XF_68KPOLL;
be20816c 1495 m68k_poll.cyc_max = 64;
b78efee2 1496 sh2_poll[0].flag = P32XF_MSH2POLL;
1d7a28a7 1497 sh2_poll[0].cyc_max = 21;
b78efee2 1498 sh2_poll[1].flag = P32XF_SSH2POLL;
be20816c 1499 sh2_poll[1].cyc_max = 16;
be2c4208 1500}
1501
bcf65fd6 1502// vim:shiftwidth=2:expandtab
fast MegaDrive/MegaCD/32X emulator