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updated EEPROM code, gmv fixed
[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
16\r
89fa852d 17//\r
18#define USE_POLL_DETECT\r
19\r
eff55556 20#ifndef PICO_INTERNAL\r
21#define PICO_INTERNAL\r
22#endif\r
23#ifndef PICO_INTERNAL_ASM\r
24#define PICO_INTERNAL_ASM\r
25#endif\r
cc68a136 26\r
ab0607f7 27// to select core, define EMU_C68K, EMU_M68K or EMU_A68K in your makefile or project\r
cc68a136 28\r
29#ifdef __cplusplus\r
30extern "C" {\r
31#endif\r
32\r
33\r
34// ----------------------- 68000 CPU -----------------------\r
35#ifdef EMU_C68K\r
36#include "../cpu/Cyclone/Cyclone.h"\r
b837b69b 37extern struct Cyclone PicoCpu, PicoCpuS68k;\r
7336a99a 38#define SekCyclesLeftNoMCD PicoCpu.cycles // cycles left for this run\r
39#define SekCyclesLeft \\r
40 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 41#define SekCyclesLeftS68k \\r
42 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuS68k.cycles)\r
7336a99a 43#define SekSetCyclesLeftNoMCD(c) PicoCpu.cycles=c\r
44#define SekSetCyclesLeft(c) { \\r
45 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
46}\r
cc68a136 47#define SekPc (PicoCpu.pc-PicoCpu.membase)\r
b837b69b 48#define SekPcS68k (PicoCpuS68k.pc-PicoCpuS68k.membase)\r
0af33fe0 49#define SekSetStop(x) { PicoCpu.state_flags&=~1; if (x) { PicoCpu.state_flags|=1; PicoCpu.cycles=0; } }\r
50#define SekSetStopS68k(x) { PicoCpuS68k.state_flags&=~1; if (x) { PicoCpuS68k.state_flags|=1; PicoCpuS68k.cycles=0; } }\r
cc68a136 51#endif\r
52\r
53#ifdef EMU_A68K\r
54void __cdecl M68000_RUN();\r
55// The format of the data in a68k.asm (at the _M68000_regs location)\r
56struct A68KContext\r
57{\r
58 unsigned int d[8],a[8];\r
59 unsigned int isp,srh,ccr,xc,pc,irq,sr;\r
60 int (*IrqCallback) (int nIrq);\r
61 unsigned int ppc;\r
62 void *pResetCallback;\r
63 unsigned int sfc,dfc,usp,vbr;\r
64 unsigned int AsmBank,CpuVersion;\r
65};\r
66struct A68KContext M68000_regs;\r
67extern int m68k_ICount;\r
68#define SekCyclesLeft m68k_ICount\r
69#define SekSetCyclesLeft(c) m68k_ICount=c\r
70#define SekPc M68000_regs.pc\r
71#endif\r
72\r
73#ifdef EMU_M68K\r
74#include "../cpu/musashi/m68kcpu.h"\r
75extern m68ki_cpu_core PicoM68kCPU; // MD's CPU\r
76extern m68ki_cpu_core PicoS68kCPU; // Mega CD's CPU\r
77#ifndef SekCyclesLeft\r
7a1f6e45 78#define SekCyclesLeftNoMCD PicoM68kCPU.cyc_remaining_cycles\r
7336a99a 79#define SekCyclesLeft \\r
80 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 81#define SekCyclesLeftS68k \\r
82 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoS68kCPU.cyc_remaining_cycles)\r
7336a99a 83#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
84#define SekSetCyclesLeft(c) { \\r
85 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
86}\r
cc68a136 87#define SekPc m68k_get_reg(&PicoM68kCPU, M68K_REG_PC)\r
88#define SekPcS68k m68k_get_reg(&PicoS68kCPU, M68K_REG_PC)\r
7a1f6e45 89#define SekSetStop(x) { \\r
90 if(x) { SET_CYCLES(0); PicoM68kCPU.stopped=STOP_LEVEL_STOP; } \\r
91 else PicoM68kCPU.stopped=0; \\r
92}\r
93#define SekSetStopS68k(x) { \\r
94 if(x) { SET_CYCLES(0); PicoS68kCPU.stopped=STOP_LEVEL_STOP; } \\r
95 else PicoS68kCPU.stopped=0; \\r
96}\r
cc68a136 97#endif\r
98#endif\r
99\r
100extern int SekCycleCnt; // cycles done in this frame\r
101extern int SekCycleAim; // cycle aim\r
102extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
103\r
b8cbd802 104#define SekCyclesReset() { \\r
105 SekCycleCntT+=SekCycleAim; \\r
106 SekCycleCnt-=SekCycleAim; \\r
107 SekCycleAim=0; \\r
108}\r
cc68a136 109#define SekCyclesBurn(c) SekCycleCnt+=c\r
110#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
111#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
112\r
113#define SekEndRun(after) { \\r
114 SekCycleCnt -= SekCyclesLeft - after; \\r
115 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
116 SekSetCyclesLeft(after); \\r
117}\r
118\r
119extern int SekCycleCntS68k;\r
120extern int SekCycleAimS68k;\r
121\r
122#define SekCyclesResetS68k() {SekCycleCntS68k=SekCycleAimS68k=0;}\r
7a1f6e45 123#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 124\r
2d0b15bb 125// debug cyclone\r
126#if defined(EMU_C68K) && defined(EMU_M68K)\r
127#undef SekSetCyclesLeftNoMCD\r
128#undef SekSetCyclesLeft\r
129#undef SekCyclesBurn\r
130#undef SekEndRun\r
131#define SekSetCyclesLeftNoMCD(c)\r
132#define SekSetCyclesLeft(c)\r
2270612a 133#define SekCyclesBurn(c) c\r
2d0b15bb 134#define SekEndRun(c)\r
135#endif\r
cc68a136 136\r
137extern int PicoMCD;\r
138\r
139// ---------------------------------------------------------\r
140\r
141// main oscillator clock which controls timing\r
142#define OSC_NTSC 53693100\r
b8cbd802 143// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
144#define OSC_PAL 53203424\r
cc68a136 145\r
146struct PicoVideo\r
147{\r
148 unsigned char reg[0x20];\r
b8cbd802 149 unsigned int command; // 32-bit Command\r
150 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
151 unsigned char type; // Command type (v/c/vsram read/write)\r
152 unsigned short addr; // Read/Write address\r
153 int status; // Status bits\r
cc68a136 154 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 155 signed char lwrite_cnt; // VDP write count during active display line\r
156 unsigned char pad[0x12];\r
cc68a136 157};\r
158\r
159struct PicoMisc\r
160{\r
161 unsigned char rotate;\r
162 unsigned char z80Run;\r
e5503e2f 163 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
164 short scanline; // 04 0 to 261||311; -1 in fast mode\r
165 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
166 unsigned char hardware; // 07 Hardware value for country\r
167 unsigned char pal; // 08 1=PAL 0=NTSC\r
168 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
169 unsigned short z80_bank68k; // 0a\r
cc68a136 170 unsigned short z80_lastaddr; // this is for Z80 faking\r
171 unsigned char z80_fakeval;\r
172 unsigned char pad0;\r
e5503e2f 173 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 174 unsigned short eeprom_addr; // EEPROM address register\r
175 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
176 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 177 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 178 unsigned short dma_xfers;\r
312e9ce1 179 unsigned char pad[2];\r
180 unsigned int frame_count; // mainly for movies\r
cc68a136 181};\r
182\r
183// some assembly stuff depend on these, do not touch!\r
184struct Pico\r
185{\r
186 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
187 unsigned short vram[0x8000]; // 0x10000\r
188 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
189 unsigned char ioports[0x10];\r
190 unsigned int pad[0x3c]; // unused\r
191 unsigned short cram[0x40]; // 0x22100\r
192 unsigned short vsram[0x40]; // 0x22180\r
193\r
194 unsigned char *rom; // 0x22200\r
195 unsigned int romsize; // 0x22204\r
196\r
197 struct PicoMisc m;\r
198 struct PicoVideo video;\r
199};\r
200\r
201// sram\r
202struct PicoSRAM\r
203{\r
4ff2d527 204 unsigned char *data; // actual data\r
205 unsigned int start; // start address in 68k address space\r
cc68a136 206 unsigned int end;\r
1dceadae 207 unsigned char unused1; // 0c: unused\r
208 unsigned char unused2;\r
cc68a136 209 unsigned char changed;\r
1dceadae 210 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
211 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
212 unsigned char eeprom_bit_cl; // bit number for cl\r
213 unsigned char eeprom_bit_in; // bit number for in\r
214 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 215};\r
216\r
217// MCD\r
218#include "cd/cd_sys.h"\r
219#include "cd/LC89510.h"\r
d1df8786 220#include "cd/gfx_cd.h"\r
cc68a136 221\r
4f265db7 222struct mcd_pcm\r
223{\r
224 unsigned char control; // reg7\r
225 unsigned char enabled; // reg8\r
226 unsigned char cur_ch;\r
227 unsigned char bank;\r
228 int pad1;\r
229\r
4ff2d527 230 struct pcm_chan // 08, size 0x10\r
4f265db7 231 {\r
232 unsigned char regs[8];\r
4ff2d527 233 unsigned int addr; // .08: played sample address\r
4f265db7 234 int pad;\r
235 } ch[8];\r
236};\r
237\r
c459aefd 238struct mcd_misc\r
239{\r
240 unsigned short hint_vector;\r
241 unsigned char busreq;\r
51a902ae 242 unsigned char s68k_pend_ints;\r
89fa852d 243 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 244 unsigned int counter75hz;\r
4ff2d527 245 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 246 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 247 char pad1;\r
4ff2d527 248 int timer_int3; // 10\r
4f265db7 249 unsigned int timer_stopwatch;\r
6cadc2da 250 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
251 unsigned char pad2;\r
252 unsigned short pad3;\r
253 int pad[9];\r
c459aefd 254};\r
255\r
cc68a136 256typedef struct\r
257{\r
4ff2d527 258 unsigned char bios[0x20000]; // 000000: 128K\r
259 union { // 020000: 512K\r
fa1e5e29 260 unsigned char prg_ram[0x80000];\r
cc68a136 261 unsigned char prg_ram_b[4][0x20000];\r
262 };\r
4ff2d527 263 union { // 0a0000: 256K\r
fa1e5e29 264 struct {\r
265 unsigned char word_ram2M[0x40000];\r
266 unsigned char unused[0x20000];\r
267 };\r
268 struct {\r
269 unsigned char unused[0x20000];\r
270 unsigned char word_ram1M[2][0x20000];\r
271 };\r
272 };\r
4ff2d527 273 union { // 100000: 64K\r
fa1e5e29 274 unsigned char pcm_ram[0x10000];\r
4f265db7 275 unsigned char pcm_ram_b[0x10][0x1000];\r
276 };\r
4ff2d527 277 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
278 unsigned char bram[0x2000]; // 110200: 8K\r
279 struct mcd_misc m; // 112200: misc\r
280 struct mcd_pcm pcm; // 112240:\r
75736070 281 _scd_toc TOC; // not to be saved\r
cc68a136 282 CDD cdd;\r
283 CDC cdc;\r
284 _scd scd;\r
d1df8786 285 Rot_Comp rot_comp;\r
cc68a136 286} mcd_state;\r
287\r
288#define Pico_mcd ((mcd_state *)Pico.rom)\r
289\r
51a902ae 290// Area.c\r
eff55556 291PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
292PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae 293\r
294// cd/Area.c\r
eff55556 295PICO_INTERNAL int PicoCdSaveState(void *file);\r
296PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 297\r
1dceadae 298// Cart.c\r
299PICO_INTERNAL void PicoCartDetect(void);\r
300\r
cc68a136 301// Draw.c\r
eff55556 302PICO_INTERNAL int PicoLine(int scan);\r
303PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 304\r
305// Draw2.c\r
eff55556 306PICO_INTERNAL void PicoFrameFull();\r
cc68a136 307\r
308// Memory.c\r
eff55556 309PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
310PICO_INTERNAL_ASM unsigned int CPU_CALL PicoRead32(unsigned int a);\r
311PICO_INTERNAL void PicoMemSetup(void);\r
312PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f 313PICO_INTERNAL int PadRead(int i);\r
eff55556 314PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
315PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
316PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
317PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
cc68a136 318\r
319// cd/Memory.c\r
eff55556 320PICO_INTERNAL void PicoMemSetupCD(void);\r
321PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
322PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 323\r
324// Pico.c\r
325extern struct Pico Pico;\r
326extern struct PicoSRAM SRam;\r
327extern int emustatus;\r
d9153729 328extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556 329PICO_INTERNAL int CheckDMA(void);\r
cc68a136 330\r
331// cd/Pico.c\r
e5f426aa 332PICO_INTERNAL int PicoInitMCD(void);\r
333PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 334PICO_INTERNAL int PicoResetMCD(int hard);\r
335PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 336\r
337// Sek.c\r
eff55556 338PICO_INTERNAL int SekInit(void);\r
339PICO_INTERNAL int SekReset(void);\r
340PICO_INTERNAL int SekInterrupt(int irq);\r
341PICO_INTERNAL void SekState(unsigned char *data);\r
342PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 343\r
344// cd/Sek.c\r
eff55556 345PICO_INTERNAL int SekInitS68k(void);\r
346PICO_INTERNAL int SekResetS68k(void);\r
347PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 348\r
7a93adeb 349// sound/sound.c\r
350extern int PsndLen_exc_cnt;\r
351extern int PsndLen_exc_add;\r
352\r
cc68a136 353// VideoPort.c\r
eff55556 354PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
355PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136 356\r
357// Misc.c\r
eff55556 358PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
359PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
360PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
361PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
362PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
363PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
364PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 365\r
fa1e5e29 366// cd/Misc.c\r
eff55556 367PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
368PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
369\r
370// cd/buffering.c\r
371PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
372\r
373// sound/sound.c\r
374PICO_INTERNAL void sound_reset(void);\r
375PICO_INTERNAL void sound_timers_and_dac(int raster);\r
376PICO_INTERNAL int sound_render(int offset, int length);\r
377PICO_INTERNAL void sound_clear(void);\r
378// z80 functionality wrappers\r
379PICO_INTERNAL void z80_init(void);\r
380PICO_INTERNAL void z80_resetCycles(void);\r
381PICO_INTERNAL void z80_int(void);\r
382PICO_INTERNAL int z80_run(int cycles);\r
383PICO_INTERNAL void z80_pack(unsigned char *data);\r
384PICO_INTERNAL void z80_unpack(unsigned char *data);\r
385PICO_INTERNAL void z80_reset(void);\r
386PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 387\r
cc68a136 388\r
389#ifdef __cplusplus\r
390} // End of extern "C"\r
391#endif\r
eff55556 392\r
b8cbd802 393// emulation event logging\r
394#ifndef EL_LOGMASK\r
395#define EL_LOGMASK 0\r
396#endif\r
397\r
398#define EL_HVCNT 0x0001 /* hv counter reads */\r
399#define EL_SR 0x0002 /* SR reads */\r
400#define EL_INTS 0x0004 /* ints and acks */\r
401#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
402#define EL_INTSW 0x0010 /* log irq switching on/off */\r
403#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
404#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
405#define EL_BUSREQ 0x0080 /* z80 busreq r/w */\r
406#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae 407#define EL_SRAMIO 0x0200 /* sram i/o */\r
408#define EL_EEPROM 0x0400 /* eeprom debug */\r
409#define EL_UIO 0x0800 /* unmapped i/o */\r
410#define EL_IO 0x1000 /* all i/o */\r
b8cbd802 411\r
412#define EL_STATUS 0x4000 /* status messages */\r
413#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
414\r
415#if EL_LOGMASK\r
416#define elprintf(w,f,...) \\r
417{ \\r
418 if ((w) & EL_LOGMASK) \\r
419 printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
420}\r
421#else\r
422#define elprintf(w,f,...)\r
423#endif\r
424\r
eff55556 425#endif // PICO_INTERNAL_INCLUDED\r
426\r
fast MegaDrive/MegaCD/32X emulator