drc: some portability fixes
[picodrive.git] / pico / memory.c
CommitLineData
cff531af 1/*\r
2 * memory handling\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
efcba75f 10#include "pico_int.h"\r
af37bca8 11#include "memory.h"\r
cc68a136 12\r
cc68a136 13#include "sound/ym2612.h"\r
14#include "sound/sn76496.h"\r
15\r
c8d1e9b6 16extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
cc68a136 17\r
bcf65fd6 18uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
19uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
20uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
21uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
af37bca8 22\r
bcf65fd6 23static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,\r
0ace9b9a 24 const void *func_or_mh, int is_func)\r
af37bca8 25{\r
bcf65fd6 26 uptr addr = (uptr)func_or_mh;\r
af37bca8 27 int mask = (1 << shift) - 1;\r
28 int i;\r
29\r
30 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r
31 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r
32 start_addr, end_addr);\r
33 return;\r
34 }\r
35\r
36 if (addr & 1) {\r
37 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r
38 return;\r
39 }\r
40\r
41 if (!is_func)\r
42 addr -= start_addr;\r
43\r
44 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
45 map[i] = addr >> 1;\r
46 if (is_func)\r
b8a1c09a 47 map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);\r
af37bca8 48 }\r
49}\r
50\r
bcf65fd6 51void z80_map_set(uptr *map, int start_addr, int end_addr,\r
0ace9b9a 52 const void *func_or_mh, int is_func)\r
af37bca8 53{\r
54 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
55}\r
56\r
bcf65fd6 57void cpu68k_map_set(uptr *map, int start_addr, int end_addr,\r
0ace9b9a 58 const void *func_or_mh, int is_func)\r
af37bca8 59{\r
60 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
61}\r
62\r
63// more specialized/optimized function (does same as above)\r
64void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r
65{\r
bcf65fd6 66 uptr *r8map, *r16map, *w8map, *w16map;\r
67 uptr addr = (uptr)ptr;\r
af37bca8 68 int shift = M68K_MEM_SHIFT;\r
69 int i;\r
70\r
71 if (!is_sub) {\r
72 r8map = m68k_read8_map;\r
73 r16map = m68k_read16_map;\r
74 w8map = m68k_write8_map;\r
75 w16map = m68k_write16_map;\r
76 } else {\r
77 r8map = s68k_read8_map;\r
78 r16map = s68k_read16_map;\r
79 w8map = s68k_write8_map;\r
80 w16map = s68k_write16_map;\r
81 }\r
82\r
83 addr -= start_addr;\r
84 addr >>= 1;\r
85 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
86 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r
87}\r
88\r
89static u32 m68k_unmapped_read8(u32 a)\r
90{\r
91 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);\r
92 return 0; // assume pulldown, as if MegaCD2 was attached\r
93}\r
94\r
95static u32 m68k_unmapped_read16(u32 a)\r
96{\r
97 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r
98 return 0;\r
99}\r
100\r
101static void m68k_unmapped_write8(u32 a, u32 d)\r
102{\r
103 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
104}\r
105\r
106static void m68k_unmapped_write16(u32 a, u32 d)\r
107{\r
108 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
109}\r
110\r
111void m68k_map_unmap(int start_addr, int end_addr)\r
112{\r
bcf65fd6 113 uptr addr;\r
af37bca8 114 int shift = M68K_MEM_SHIFT;\r
115 int i;\r
116\r
bcf65fd6 117 addr = (uptr)m68k_unmapped_read8;\r
af37bca8 118 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
119 m68k_read8_map[i] = (addr >> 1) | (1 << 31);\r
120\r
bcf65fd6 121 addr = (uptr)m68k_unmapped_read16;\r
af37bca8 122 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
123 m68k_read16_map[i] = (addr >> 1) | (1 << 31);\r
124\r
bcf65fd6 125 addr = (uptr)m68k_unmapped_write8;\r
af37bca8 126 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
127 m68k_write8_map[i] = (addr >> 1) | (1 << 31);\r
128\r
bcf65fd6 129 addr = (uptr)m68k_unmapped_write16;\r
af37bca8 130 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
131 m68k_write16_map[i] = (addr >> 1) | (1 << 31);\r
132}\r
133\r
134MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r
135MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r
136MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r
137MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r
138MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r
139MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r
140\r
141// -----------------------------------------------------------------\r
142\r
143static u32 ym2612_read_local_68k(void);\r
144static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
145static void z80_mem_setup(void);\r
cc68a136 146\r
0ace9b9a 147#ifdef _ASM_MEMORY_C\r
148u32 PicoRead8_sram(u32 a);\r
149u32 PicoRead16_sram(u32 a);\r
150#endif\r
cc68a136 151\r
03e4f2a3 152#ifdef EMU_CORE_DEBUG\r
cc68a136 153u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
154int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
155extern unsigned int ppop;\r
156#endif\r
157\r
4f65685b 158#ifdef IO_STATS\r
159void log_io(unsigned int addr, int bits, int rw);\r
dca310c4 160#elif defined(_MSC_VER)\r
161#define log_io\r
4f65685b 162#else\r
163#define log_io(...)\r
164#endif\r
165\r
70357ce5 166#if defined(EMU_C68K)\r
5e89f0f5 167void cyclone_crashed(u32 pc, struct Cyclone *context)\r
cc68a136 168{\r
bf61bea0 169 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",\r
5e89f0f5 170 context == &PicoCpuCM68k ? 'm' : 's', pc);\r
171 context->membase = (u32)Pico.rom;\r
172 context->pc = (u32)Pico.rom + Pico.romsize;\r
cc68a136 173}\r
174#endif\r
175\r
cc68a136 176// -----------------------------------------------------------------\r
af37bca8 177// memmap helpers\r
cc68a136 178\r
0ace9b9a 179#ifndef _ASM_MEMORY_C\r
180static\r
181#endif\r
182int PadRead(int i)\r
e5503e2f 183{\r
184 int pad,value,data_reg;\r
5f9a0d16 185 pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
e5503e2f 186 data_reg=Pico.ioports[i+1];\r
187\r
188 // orr the bits, which are set as output\r
189 value = data_reg&(Pico.ioports[i+4]|0x80);\r
190\r
602133e1 191 if (PicoOpt & POPT_6BTN_PAD)\r
192 {\r
e5503e2f 193 int phase = Pico.m.padTHPhase[i];\r
194\r
195 if(phase == 2 && !(data_reg&0x40)) { // TH\r
196 value|=(pad&0xc0)>>2; // ?0SA 0000\r
197 return value;\r
198 } else if(phase == 3) {\r
199 if(data_reg&0x40)\r
200 value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
201 else\r
202 value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
203 return value;\r
204 }\r
205 }\r
206\r
207 if(data_reg&0x40) // TH\r
208 value|=(pad&0x3f); // ?1CB RLDU\r
209 else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
210\r
211 return value; // will mirror later\r
212}\r
213\r
0ace9b9a 214#ifndef _ASM_MEMORY_C\r
215\r
af37bca8 216static u32 io_ports_read(u32 a)\r
cc68a136 217{\r
af37bca8 218 u32 d;\r
219 a = (a>>1) & 0xf;\r
220 switch (a) {\r
221 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)\r
222 case 1: d = PadRead(0); break;\r
223 case 2: d = PadRead(1); break;\r
224 default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r
7969166e 225 }\r
af37bca8 226 return d;\r
cc68a136 227}\r
cc68a136 228\r
5e89f0f5 229static void NOINLINE io_ports_write(u32 a, u32 d)\r
9dc09829 230{\r
af37bca8 231 a = (a>>1) & 0xf;\r
232\r
233 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
234 if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))\r
235 {\r
236 Pico.m.padDelay[a - 1] = 0;\r
237 if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r
238 Pico.m.padTHPhase[a - 1]++;\r
9dc09829 239 }\r
af37bca8 240\r
5e89f0f5 241 // certain IO ports can be used as RAM\r
af37bca8 242 Pico.ioports[a] = d;\r
9dc09829 243}\r
244\r
0ace9b9a 245#endif // _ASM_MEMORY_C\r
246\r
247void NOINLINE ctl_write_z80busreq(u32 d)\r
7969166e 248{\r
af37bca8 249 d&=1; d^=1;\r
250 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
251 if (d ^ Pico.m.z80Run)\r
252 {\r
253 if (d)\r
254 {\r
255 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
256 }\r
257 else\r
258 {\r
259 z80stopCycle = SekCyclesDone();\r
f6c49d38 260 if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {\r
261 pprof_start(m68k);\r
af37bca8 262 PicoSyncZ80(z80stopCycle);\r
f6c49d38 263 pprof_end_sub(m68k);\r
264 }\r
af37bca8 265 }\r
266 Pico.m.z80Run = d;\r
7969166e 267 }\r
af37bca8 268}\r
269\r
0ace9b9a 270void NOINLINE ctl_write_z80reset(u32 d)\r
af37bca8 271{\r
272 d&=1; d^=1;\r
273 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
274 if (d ^ Pico.m.z80_reset)\r
275 {\r
276 if (d)\r
277 {\r
f6c49d38 278 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {\r
279 pprof_start(m68k);\r
af37bca8 280 PicoSyncZ80(SekCyclesDone());\r
f6c49d38 281 pprof_end_sub(m68k);\r
282 }\r
af37bca8 283 YM2612ResetChip();\r
284 timers_reset();\r
7969166e 285 }\r
af37bca8 286 else\r
287 {\r
288 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
289 z80_reset();\r
7969166e 290 }\r
af37bca8 291 Pico.m.z80_reset = d;\r
7969166e 292 }\r
293}\r
cc68a136 294\r
af37bca8 295// -----------------------------------------------------------------\r
fa1e5e29 296\r
0ace9b9a 297#ifndef _ASM_MEMORY_C\r
298\r
af37bca8 299// cart (save) RAM area (usually 0x200000 - ...)\r
300static u32 PicoRead8_sram(u32 a)\r
301{\r
af37bca8 302 u32 d;\r
45f2f245 303 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
af37bca8 304 {\r
45f2f245 305 if (SRam.flags & SRF_EEPROM) {\r
af37bca8 306 d = EEPROM_read();\r
45f2f245 307 if (!(a & 1))\r
308 d >>= 8;\r
309 } else\r
af37bca8 310 d = *(u8 *)(SRam.data - SRam.start + a);\r
45f2f245 311 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
af37bca8 312 return d;\r
313 }\r
cc68a136 314\r
45f2f245 315 // XXX: this is banking unfriendly\r
af37bca8 316 if (a < Pico.romsize)\r
317 return Pico.rom[a ^ 1];\r
318 \r
319 return m68k_unmapped_read8(a);\r
320}\r
cc68a136 321\r
af37bca8 322static u32 PicoRead16_sram(u32 a)\r
cc68a136 323{\r
af37bca8 324 u32 d;\r
b4db550e 325 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
af37bca8 326 {\r
45f2f245 327 if (SRam.flags & SRF_EEPROM)\r
af37bca8 328 d = EEPROM_read();\r
45f2f245 329 else {\r
af37bca8 330 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
331 d = pm[0] << 8;\r
332 d |= pm[1];\r
333 }\r
334 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
335 return d;\r
336 }\r
cc68a136 337\r
af37bca8 338 if (a < Pico.romsize)\r
339 return *(u16 *)(Pico.rom + a);\r
cc68a136 340\r
af37bca8 341 return m68k_unmapped_read16(a);\r
342}\r
cc68a136 343\r
0ace9b9a 344#endif // _ASM_MEMORY_C\r
345\r
af37bca8 346static void PicoWrite8_sram(u32 a, u32 d)\r
347{\r
45f2f245 348 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
349 m68k_unmapped_write8(a, d);\r
350 return;\r
351 }\r
352\r
353 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);\r
354 if (SRam.flags & SRF_EEPROM)\r
af37bca8 355 {\r
45f2f245 356 EEPROM_write8(a, d);\r
cc68a136 357 }\r
45f2f245 358 else {\r
359 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
af37bca8 360 if (*pm != (u8)d) {\r
361 SRam.changed = 1;\r
362 *pm = (u8)d;\r
363 }\r
364 }\r
365}\r
cc68a136 366\r
af37bca8 367static void PicoWrite16_sram(u32 a, u32 d)\r
368{\r
45f2f245 369 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
370 m68k_unmapped_write16(a, d);\r
371 return;\r
372 }\r
373\r
374 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r
375 if (SRam.flags & SRF_EEPROM)\r
376 {\r
377 EEPROM_write16(d);\r
378 }\r
379 else {\r
380 // XXX: hardware could easily use MSB too..\r
381 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
382 if (*pm != (u8)d) {\r
383 SRam.changed = 1;\r
384 *pm = (u8)d;\r
385 }\r
386 }\r
af37bca8 387}\r
cc68a136 388\r
af37bca8 389// z80 area (0xa00000 - 0xa0ffff)\r
390// TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r
391static u32 PicoRead8_z80(u32 a)\r
392{\r
393 u32 d = 0xff;\r
394 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
395 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r
396 // open bus. Pulled down if MegaCD2 is attached.\r
397 return 0;\r
398 }\r
c060a9ab 399\r
af37bca8 400 if ((a & 0x4000) == 0x0000)\r
401 d = Pico.zram[a & 0x1fff];\r
402 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
403 d = ym2612_read_local_68k(); \r
404 else\r
405 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
406 return d;\r
407}\r
b542be46 408\r
af37bca8 409static u32 PicoRead16_z80(u32 a)\r
410{\r
411 u32 d = PicoRead8_z80(a);\r
412 return d | (d << 8);\r
413}\r
414\r
415static void PicoWrite8_z80(u32 a, u32 d)\r
416{\r
417 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
418 // verified on real hw\r
419 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
420 return;\r
421 }\r
422\r
423 if ((a & 0x4000) == 0x0000) { // z80 RAM\r
424 SekCyclesBurn(2); // hack\r
425 Pico.zram[a & 0x1fff] = (u8)d;\r
426 return;\r
427 }\r
428 if ((a & 0x6000) == 0x4000) { // FM Sound\r
429 if (PicoOpt & POPT_EN_FM)\r
430 emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;\r
431 return;\r
432 }\r
433 // TODO: probably other VDP access too? Maybe more mirrors?\r
434 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r
435 if (PicoOpt & POPT_EN_PSG)\r
436 SN76496Write(d);\r
437 return;\r
438 }\r
af37bca8 439 if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
440 {\r
441 Pico.m.z80_bank68k >>= 1;\r
442 Pico.m.z80_bank68k |= d << 8;\r
443 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
444 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
445 return;\r
cc68a136 446 }\r
af37bca8 447 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
cc68a136 448}\r
449\r
af37bca8 450static void PicoWrite16_z80(u32 a, u32 d)\r
cc68a136 451{\r
af37bca8 452 // for RAM, only most significant byte is sent\r
453 // TODO: verify remaining accesses\r
454 PicoWrite8_z80(a, d >> 8);\r
455}\r
cc68a136 456\r
0ace9b9a 457#ifndef _ASM_MEMORY_C\r
458\r
af37bca8 459// IO/control area (0xa10000 - 0xa1ffff)\r
460u32 PicoRead8_io(u32 a)\r
461{\r
462 u32 d;\r
cc68a136 463\r
af37bca8 464 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
465 d = io_ports_read(a);\r
cc68a136 466 goto end;\r
467 }\r
cc68a136 468\r
af37bca8 469 // faking open bus (MegaCD pulldowns don't work here curiously)\r
470 d = Pico.m.rotate++;\r
471 d ^= d << 6;\r
cc68a136 472\r
5e89f0f5 473 if ((a & 0xfc00) == 0x1000) {\r
474 // bit8 seems to be readable in this range\r
475 if (!(a & 1))\r
476 d &= ~0x01;\r
cc68a136 477\r
5e89f0f5 478 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
479 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
480 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
481 }\r
af37bca8 482 goto end;\r
cc68a136 483 }\r
af37bca8 484\r
db1d3564 485 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 486 d = PicoRead8_32x(a);\r
487 goto end;\r
488 }\r
489\r
af37bca8 490 d = m68k_unmapped_read8(a);\r
491end:\r
cc68a136 492 return d;\r
493}\r
494\r
af37bca8 495u32 PicoRead16_io(u32 a)\r
cc68a136 496{\r
af37bca8 497 u32 d;\r
cc68a136 498\r
af37bca8 499 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
500 d = io_ports_read(a);\r
bdd6a009 501 d |= d << 8;\r
cc68a136 502 goto end;\r
503 }\r
504\r
af37bca8 505 // faking open bus\r
506 d = (Pico.m.rotate += 0x41);\r
507 d ^= (d << 5) ^ (d << 8);\r
cc68a136 508\r
af37bca8 509 // bit8 seems to be readable in this range\r
5e89f0f5 510 if ((a & 0xfc00) == 0x1000) {\r
af37bca8 511 d &= ~0x0100;\r
cc68a136 512\r
5e89f0f5 513 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
514 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
515 elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
516 }\r
af37bca8 517 goto end;\r
cc68a136 518 }\r
af37bca8 519\r
db1d3564 520 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 521 d = PicoRead16_32x(a);\r
522 goto end;\r
523 }\r
524\r
af37bca8 525 d = m68k_unmapped_read16(a);\r
526end:\r
cc68a136 527 return d;\r
528}\r
cc68a136 529\r
af37bca8 530void PicoWrite8_io(u32 a, u32 d)\r
531{\r
532 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r
533 io_ports_write(a, d);\r
534 return;\r
535 }\r
536 if ((a & 0xff01) == 0x1100) { // z80 busreq\r
537 ctl_write_z80busreq(d);\r
538 return;\r
539 }\r
540 if ((a & 0xff01) == 0x1200) { // z80 reset\r
541 ctl_write_z80reset(d);\r
542 return;\r
543 }\r
544 if (a == 0xa130f1) { // sram access register\r
545 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
45f2f245 546 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
547 Pico.m.sram_reg |= (u8)(d & 3);\r
af37bca8 548 return;\r
549 }\r
db1d3564 550 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 551 PicoWrite8_32x(a, d);\r
552 return;\r
553 }\r
554\r
af37bca8 555 m68k_unmapped_write8(a, d);\r
556}\r
cc68a136 557\r
af37bca8 558void PicoWrite16_io(u32 a, u32 d)\r
cc68a136 559{\r
af37bca8 560 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r
561 io_ports_write(a, d);\r
562 return;\r
563 }\r
564 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
565 ctl_write_z80busreq(d >> 8);\r
566 return;\r
567 }\r
568 if ((a & 0xff00) == 0x1200) { // z80 reset\r
569 ctl_write_z80reset(d >> 8);\r
570 return;\r
571 }\r
572 if (a == 0xa130f0) { // sram access register\r
573 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
45f2f245 574 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
575 Pico.m.sram_reg |= (u8)(d & 3);\r
af37bca8 576 return;\r
577 }\r
db1d3564 578 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 579 PicoWrite16_32x(a, d);\r
580 return;\r
581 }\r
af37bca8 582 m68k_unmapped_write16(a, d);\r
583}\r
cc68a136 584\r
0ace9b9a 585#endif // _ASM_MEMORY_C\r
586\r
af37bca8 587// VDP area (0xc00000 - 0xdfffff)\r
588// TODO: verify if lower byte goes to PSG on word writes\r
589static u32 PicoRead8_vdp(u32 a)\r
590{\r
591 if ((a & 0x00e0) == 0x0000)\r
592 return PicoVideoRead8(a);\r
cc68a136 593\r
af37bca8 594 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
595 return 0;\r
cc68a136 596}\r
597\r
af37bca8 598static u32 PicoRead16_vdp(u32 a)\r
cc68a136 599{\r
af37bca8 600 if ((a & 0x00e0) == 0x0000)\r
601 return PicoVideoRead(a);\r
cc68a136 602\r
af37bca8 603 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
604 return 0;\r
cc68a136 605}\r
606\r
af37bca8 607static void PicoWrite8_vdp(u32 a, u32 d)\r
cc68a136 608{\r
af37bca8 609 if ((a & 0x00f9) == 0x0011) { // PSG Sound\r
610 if (PicoOpt & POPT_EN_PSG)\r
611 SN76496Write(d);\r
cc68a136 612 return;\r
613 }\r
af37bca8 614 if ((a & 0x00e0) == 0x0000) {\r
615 d &= 0xff;\r
616 PicoVideoWrite(a, d | (d << 8));\r
b542be46 617 return;\r
618 }\r
619\r
af37bca8 620 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
cc68a136 621}\r
622\r
af37bca8 623static void PicoWrite16_vdp(u32 a, u32 d)\r
624{\r
625 if ((a & 0x00f9) == 0x0010) { // PSG Sound\r
626 if (PicoOpt & POPT_EN_PSG)\r
627 SN76496Write(d);\r
628 return;\r
629 }\r
630 if ((a & 0x00e0) == 0x0000) {\r
631 PicoVideoWrite(a, d);\r
632 return;\r
633 }\r
634\r
635 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
636}\r
cc68a136 637\r
638// -----------------------------------------------------------------\r
f53f286a 639\r
9037e45d 640#ifdef EMU_M68K\r
641static void m68k_mem_setup(void);\r
642#endif\r
643\r
f8ef8ff7 644PICO_INTERNAL void PicoMemSetup(void)\r
645{\r
af37bca8 646 int mask, rs, a;\r
647\r
648 // setup the memory map\r
649 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
650 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);\r
651 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);\r
652 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r
653\r
654 // ROM\r
655 // align to bank size. We know ROM loader allocated enough for this\r
656 mask = (1 << M68K_MEM_SHIFT) - 1;\r
657 rs = (Pico.romsize + mask) & ~mask;\r
658 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);\r
659 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
660\r
661 // Common case of on-cart (save) RAM, usually at 0x200000-...\r
45f2f245 662 if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {\r
663 rs = SRam.end - SRam.start;\r
af37bca8 664 rs = (rs + mask) & ~mask;\r
665 if (SRam.start + rs >= 0x1000000)\r
666 rs = 0x1000000 - SRam.start;\r
667 cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r
668 cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r
669 cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r
670 cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r
671 }\r
672\r
673 // Z80 region\r
674 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r
675 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r
676 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r
677 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r
678\r
679 // IO/control region\r
680 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);\r
681 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);\r
682 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r
683 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r
684\r
685 // VDP region\r
686 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r
687 if ((a & 0xe700e0) != 0xc00000)\r
688 continue;\r
689 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);\r
690 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);\r
691 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);\r
692 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r
693 }\r
694\r
695 // RAM and it's mirrors\r
696 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
697 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r
698 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r
699 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r
700 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r
701 }\r
702\r
cc68a136 703 // Setup memory callbacks:\r
70357ce5 704#ifdef EMU_C68K\r
5e89f0f5 705 PicoCpuCM68k.read8 = (void *)m68k_read8_map;\r
706 PicoCpuCM68k.read16 = (void *)m68k_read16_map;\r
707 PicoCpuCM68k.read32 = (void *)m68k_read16_map;\r
708 PicoCpuCM68k.write8 = (void *)m68k_write8_map;\r
709 PicoCpuCM68k.write16 = (void *)m68k_write16_map;\r
710 PicoCpuCM68k.write32 = (void *)m68k_write16_map;\r
711 PicoCpuCM68k.checkpc = NULL; /* unused */\r
712 PicoCpuCM68k.fetch8 = NULL;\r
713 PicoCpuCM68k.fetch16 = NULL;\r
714 PicoCpuCM68k.fetch32 = NULL;\r
cc68a136 715#endif\r
70357ce5 716#ifdef EMU_F68K\r
af37bca8 717 PicoCpuFM68k.read_byte = m68k_read8;\r
718 PicoCpuFM68k.read_word = m68k_read16;\r
719 PicoCpuFM68k.read_long = m68k_read32;\r
720 PicoCpuFM68k.write_byte = m68k_write8;\r
721 PicoCpuFM68k.write_word = m68k_write16;\r
722 PicoCpuFM68k.write_long = m68k_write32;\r
3aa1e148 723\r
724 // setup FAME fetchmap\r
725 {\r
726 int i;\r
9037e45d 727 // by default, point everything to first 64k of ROM\r
3aa1e148 728 for (i = 0; i < M68K_FETCHBANK1; i++)\r
729 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
730 // now real ROM\r
731 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
732 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
733 // .. and RAM\r
734 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
735 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
736 }\r
70357ce5 737#endif\r
9037e45d 738#ifdef EMU_M68K\r
739 m68k_mem_setup();\r
740#endif\r
c8d1e9b6 741\r
742 z80_mem_setup();\r
cc68a136 743}\r
744\r
cc68a136 745#ifdef EMU_M68K\r
9037e45d 746unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r
747unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r
748unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r
749void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;\r
750void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r
751void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;\r
cc68a136 752\r
9037e45d 753/* it appears that Musashi doesn't always mask the unused bits */\r
754unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r
755unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r
756unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r
757void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r
758void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r
759void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r
9037e45d 760\r
761static void m68k_mem_setup(void)\r
762{\r
af37bca8 763 pm68k_read_memory_8 = m68k_read8;\r
764 pm68k_read_memory_16 = m68k_read16;\r
765 pm68k_read_memory_32 = m68k_read32;\r
766 pm68k_write_memory_8 = m68k_write8;\r
767 pm68k_write_memory_16 = m68k_write16;\r
768 pm68k_write_memory_32 = m68k_write32;\r
cc68a136 769}\r
cc68a136 770#endif // EMU_M68K\r
771\r
772\r
4b9c5888 773// -----------------------------------------------------------------\r
774\r
4b9c5888 775static int get_scanline(int is_from_z80)\r
776{\r
777 if (is_from_z80) {\r
778 int cycles = z80_cyclesDone();\r
779 while (cycles - z80_scanline_cycles >= 228)\r
780 z80_scanline++, z80_scanline_cycles += 228;\r
781 return z80_scanline;\r
782 }\r
783\r
2aa27095 784 return Pico.m.scanline;\r
4b9c5888 785}\r
786\r
48dc74f2 787/* probably should not be in this file, but it's near related code here */\r
43e6eaad 788void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r
789{\r
790 int xcycles = z80_cycles << 8;\r
791\r
792 /* check for overflows */\r
793 if ((mode_old & 4) && xcycles > timer_a_next_oflow)\r
794 ym2612.OPN.ST.status |= 1;\r
795\r
796 if ((mode_old & 8) && xcycles > timer_b_next_oflow)\r
797 ym2612.OPN.ST.status |= 2;\r
798\r
799 /* update timer a */\r
800 if (mode_old & 1)\r
e53704e6 801 while (xcycles > timer_a_next_oflow)\r
43e6eaad 802 timer_a_next_oflow += timer_a_step;\r
803\r
804 if ((mode_old ^ mode_new) & 1) // turning on/off\r
805 {\r
48dc74f2 806 if (mode_old & 1)\r
e53704e6 807 timer_a_next_oflow = TIMER_NO_OFLOW;\r
43e6eaad 808 else\r
48dc74f2 809 timer_a_next_oflow = xcycles + timer_a_step;\r
43e6eaad 810 }\r
811 if (mode_new & 1)\r
812 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);\r
813\r
814 /* update timer b */\r
815 if (mode_old & 2)\r
e53704e6 816 while (xcycles > timer_b_next_oflow)\r
43e6eaad 817 timer_b_next_oflow += timer_b_step;\r
818\r
819 if ((mode_old ^ mode_new) & 2)\r
820 {\r
48dc74f2 821 if (mode_old & 2)\r
e53704e6 822 timer_b_next_oflow = TIMER_NO_OFLOW;\r
43e6eaad 823 else\r
48dc74f2 824 timer_b_next_oflow = xcycles + timer_b_step;\r
43e6eaad 825 }\r
826 if (mode_new & 2)\r
827 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);\r
828}\r
829\r
4b9c5888 830// ym2612 DAC and timer I/O handlers for z80\r
af37bca8 831static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
4b9c5888 832{\r
833 int addr;\r
834\r
835 a &= 3;\r
836 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */\r
837 {\r
838 int scanline = get_scanline(is_from_z80);\r
839 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);\r
840 ym2612.dacout = ((int)d - 0x80) << 6;\r
841 if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)\r
842 PsndDoDAC(scanline);\r
843 return 0;\r
844 }\r
845\r
846 switch (a)\r
847 {\r
848 case 0: /* address port 0 */\r
849 ym2612.OPN.ST.address = d;\r
850 ym2612.addr_A1 = 0;\r
851#ifdef __GP2X__\r
852 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
853#endif\r
854 return 0;\r
855\r
856 case 1: /* data port 0 */\r
857 if (ym2612.addr_A1 != 0)\r
858 return 0;\r
859\r
860 addr = ym2612.OPN.ST.address;\r
861 ym2612.REGS[addr] = d;\r
862\r
863 switch (addr)\r
864 {\r
865 case 0x24: // timer A High 8\r
866 case 0x25: { // timer A Low 2\r
867 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r
868 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r
869 if (ym2612.OPN.ST.TA != TAnew)\r
870 {\r
871 //elprintf(EL_STATUS, "timer a set %i", TAnew);\r
872 ym2612.OPN.ST.TA = TAnew;\r
e53704e6 873 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r
4b9c5888 874 //ym2612.OPN.ST.TAT = 0;\r
48dc74f2 875 timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
43e6eaad 876 if (ym2612.OPN.ST.mode & 1) {\r
48dc74f2 877 // this is not right, should really be done on overflow only\r
4b9c5888 878 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
879 timer_a_next_oflow = (cycles << 8) + timer_a_step;\r
4b9c5888 880 }\r
43e6eaad 881 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r
4b9c5888 882 }\r
883 return 0;\r
884 }\r
885 case 0x26: // timer B\r
886 if (ym2612.OPN.ST.TB != d) {\r
887 //elprintf(EL_STATUS, "timer b set %i", d);\r
888 ym2612.OPN.ST.TB = d;\r
e53704e6 889 //ym2612.OPN.ST.TBC = (256-d) * 288;\r
4b9c5888 890 //ym2612.OPN.ST.TBT = 0;\r
48dc74f2 891 timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r
43e6eaad 892 if (ym2612.OPN.ST.mode & 2) {\r
893 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
894 timer_b_next_oflow = (cycles << 8) + timer_b_step;\r
895 }\r
896 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r
4b9c5888 897 }\r
898 return 0;\r
899 case 0x27: { /* mode, timer control */\r
900 int old_mode = ym2612.OPN.ST.mode;\r
43e6eaad 901 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
902 ym2612.OPN.ST.mode = d;\r
4b9c5888 903\r
43e6eaad 904 elprintf(EL_YMTIMER, "st mode %02x", d);\r
905 ym2612_sync_timers(cycles, old_mode, d);\r
4b9c5888 906\r
43e6eaad 907 /* reset Timer a flag */\r
908 if (d & 0x10)\r
909 ym2612.OPN.ST.status &= ~1;\r
4b9c5888 910\r
911 /* reset Timer b flag */\r
912 if (d & 0x20)\r
913 ym2612.OPN.ST.status &= ~2;\r
914\r
43e6eaad 915 if ((d ^ old_mode) & 0xc0) {\r
4b9c5888 916#ifdef __GP2X__\r
52250671 917 if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
4b9c5888 918#endif\r
43e6eaad 919 return 1;\r
920 }\r
4b9c5888 921 return 0;\r
922 }\r
923 case 0x2b: { /* DAC Sel (YM2612) */\r
924 int scanline = get_scanline(is_from_z80);\r
925 ym2612.dacen = d & 0x80;\r
926 if (d & 0x80) PsndDacLine = scanline;\r
927#ifdef __GP2X__\r
928 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);\r
929#endif\r
930 return 0;\r
931 }\r
932 }\r
933 break;\r
934\r
935 case 2: /* address port 1 */\r
936 ym2612.OPN.ST.address = d;\r
937 ym2612.addr_A1 = 1;\r
938#ifdef __GP2X__\r
939 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
940#endif\r
941 return 0;\r
942\r
943 case 3: /* data port 1 */\r
944 if (ym2612.addr_A1 != 1)\r
945 return 0;\r
946\r
947 addr = ym2612.OPN.ST.address | 0x100;\r
948 ym2612.REGS[addr] = d;\r
949 break;\r
950 }\r
951\r
952#ifdef __GP2X__\r
953 if (PicoOpt & POPT_EXT_FM)\r
954 return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
955#endif\r
956 return YM2612Write_(a, d);\r
957}\r
958\r
453d2a6e 959\r
43e6eaad 960#define ym2612_read_local() \\r
961 if (xcycles >= timer_a_next_oflow) \\r
962 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r
963 if (xcycles >= timer_b_next_oflow) \\r
964 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
965\r
553c3eaa 966static u32 ym2612_read_local_z80(void)\r
4b9c5888 967{\r
968 int xcycles = z80_cyclesDone() << 8;\r
4b9c5888 969\r
43e6eaad 970 ym2612_read_local();\r
971\r
972 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
973 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
974 return ym2612.OPN.ST.status;\r
975}\r
976\r
af37bca8 977static u32 ym2612_read_local_68k(void)\r
43e6eaad 978{\r
979 int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r
980\r
981 ym2612_read_local();\r
982\r
983 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
984 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
4b9c5888 985 return ym2612.OPN.ST.status;\r
986}\r
987\r
d2721b08 988void ym2612_pack_state(void)\r
989{\r
e53704e6 990 // timers are saved as tick counts, in 16.16 int format\r
991 int tac, tat = 0, tbc, tbt = 0;\r
992 tac = 1024 - ym2612.OPN.ST.TA;\r
993 tbc = 256 - ym2612.OPN.ST.TB;\r
994 if (timer_a_next_oflow != TIMER_NO_OFLOW)\r
995 tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);\r
996 if (timer_b_next_oflow != TIMER_NO_OFLOW)\r
997 tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);\r
998 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r
999 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r
1000\r
d2721b08 1001#ifdef __GP2X__\r
1002 if (PicoOpt & POPT_EXT_FM)\r
e4fb433c 1003 YM2612PicoStateSave2_940(tat, tbt);\r
d2721b08 1004 else\r
1005#endif\r
e53704e6 1006 YM2612PicoStateSave2(tat, tbt);\r
d2721b08 1007}\r
1008\r
453d2a6e 1009void ym2612_unpack_state(void)\r
1010{\r
e53704e6 1011 int i, ret, tac, tat, tbc, tbt;\r
453d2a6e 1012 YM2612PicoStateLoad();\r
1013\r
1014 // feed all the registers and update internal state\r
db49317b 1015 for (i = 0x20; i < 0xA0; i++) {\r
453d2a6e 1016 ym2612_write_local(0, i, 0);\r
1017 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1018 }\r
db49317b 1019 for (i = 0x30; i < 0xA0; i++) {\r
1020 ym2612_write_local(2, i, 0);\r
1021 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1022 }\r
1023 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r
1024 ym2612_write_local(2, i, 0);\r
1025 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1026 ym2612_write_local(0, i, 0);\r
1027 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1028 }\r
1029 for (i = 0xB0; i < 0xB8; i++) {\r
1030 ym2612_write_local(0, i, 0);\r
1031 ym2612_write_local(1, ym2612.REGS[i], 0);\r
453d2a6e 1032 ym2612_write_local(2, i, 0);\r
1033 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1034 }\r
d2721b08 1035\r
1036#ifdef __GP2X__\r
1037 if (PicoOpt & POPT_EXT_FM)\r
e4fb433c 1038 ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r
d2721b08 1039 else\r
1040#endif\r
1041 ret = YM2612PicoStateLoad2(&tat, &tbt);\r
db49317b 1042 if (ret != 0) {\r
1043 elprintf(EL_STATUS, "old ym2612 state");\r
1044 return; // no saved timers\r
1045 }\r
e53704e6 1046\r
1047 tac = (1024 - ym2612.OPN.ST.TA) << 16;\r
1048 tbc = (256 - ym2612.OPN.ST.TB) << 16;\r
1049 if (ym2612.OPN.ST.mode & 1)\r
48dc74f2 1050 timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);\r
e53704e6 1051 else\r
1052 timer_a_next_oflow = TIMER_NO_OFLOW;\r
1053 if (ym2612.OPN.ST.mode & 2)\r
48dc74f2 1054 timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);\r
e53704e6 1055 else\r
1056 timer_b_next_oflow = TIMER_NO_OFLOW;\r
1057 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);\r
1058 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);\r
453d2a6e 1059}\r
1060\r
f3a57b2d 1061#if defined(NO_32X) && defined(_ASM_MEMORY_C)\r
1062// referenced by asm code\r
1063u32 PicoRead8_32x(u32 a) { return 0; }\r
1064u32 PicoRead16_32x(u32 a) { return 0; }\r
1065void PicoWrite8_32x(u32 a, u32 d) {}\r
1066void PicoWrite16_32x(u32 a, u32 d) {}\r
1067#endif\r
1068\r
cc68a136 1069// -----------------------------------------------------------------\r
1070// z80 memhandlers\r
1071\r
553c3eaa 1072static unsigned char z80_md_vdp_read(unsigned short a)\r
cc68a136 1073{\r
c8d1e9b6 1074 // TODO?\r
1075 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
1076 return 0xff;\r
1077}\r
cc68a136 1078\r
553c3eaa 1079static unsigned char z80_md_bank_read(unsigned short a)\r
c8d1e9b6 1080{\r
c8d1e9b6 1081 unsigned int addr68k;\r
1082 unsigned char ret;\r
cc68a136 1083\r
c8d1e9b6 1084 addr68k = Pico.m.z80_bank68k<<15;\r
1085 addr68k += a & 0x7fff;\r
1086\r
af37bca8 1087 ret = m68k_read8(addr68k);\r
cc68a136 1088\r
c8d1e9b6 1089 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
cc68a136 1090 return ret;\r
1091}\r
1092\r
553c3eaa 1093static void z80_md_ym2612_write(unsigned int a, unsigned char data)\r
cc68a136 1094{\r
c8d1e9b6 1095 if (PicoOpt & POPT_EN_FM)\r
1096 emustatus |= ym2612_write_local(a, data, 1) & 1;\r
1097}\r
cc68a136 1098\r
553c3eaa 1099static void z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
c8d1e9b6 1100{\r
1101 // TODO: allow full VDP access\r
1102 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
cc68a136 1103 {\r
c8d1e9b6 1104 if (PicoOpt & POPT_EN_PSG)\r
1105 SN76496Write(data);\r
cc68a136 1106 return;\r
1107 }\r
1108\r
c8d1e9b6 1109 if ((a>>8) == 0x60)\r
cc68a136 1110 {\r
c8d1e9b6 1111 Pico.m.z80_bank68k >>= 1;\r
1112 Pico.m.z80_bank68k |= data << 8;\r
1113 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
cc68a136 1114 return;\r
1115 }\r
1116\r
c8d1e9b6 1117 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
1118}\r
cc68a136 1119\r
553c3eaa 1120static void z80_md_bank_write(unsigned int a, unsigned char data)\r
c8d1e9b6 1121{\r
c8d1e9b6 1122 unsigned int addr68k;\r
69996cb7 1123\r
c8d1e9b6 1124 addr68k = Pico.m.z80_bank68k << 15;\r
1125 addr68k += a & 0x7fff;\r
1126\r
1127 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
af37bca8 1128 m68k_write8(addr68k, data);\r
cc68a136 1129}\r
1130\r
c8d1e9b6 1131// -----------------------------------------------------------------\r
1132\r
1133static unsigned char z80_md_in(unsigned short p)\r
a4221917 1134{\r
c8d1e9b6 1135 elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r
1136 return 0xff;\r
a4221917 1137}\r
1138\r
c8d1e9b6 1139static void z80_md_out(unsigned short p, unsigned char d)\r
cc68a136 1140{\r
c8d1e9b6 1141 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
cc68a136 1142}\r
c8d1e9b6 1143\r
af37bca8 1144static void z80_mem_setup(void)\r
c8d1e9b6 1145{\r
1146 z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1147 z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1148 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
1149 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
1150 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
1151\r
1152 z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1153 z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1154 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
1155 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
1156 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
1157\r
1158#ifdef _USE_DRZ80\r
1159 drZ80.z80_in = z80_md_in;\r
1160 drZ80.z80_out = z80_md_out;\r
1161#endif\r
1162#ifdef _USE_CZ80\r
b8a1c09a 1163 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM\r
1164 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror\r
c8d1e9b6 1165 Cz80_Set_INPort(&CZ80, z80_md_in);\r
1166 Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
a4221917 1167#endif\r
c8d1e9b6 1168}\r
cc68a136 1169\r