drc: split disassembly to separate pass
[picodrive.git] / pico / memory.c
CommitLineData
cff531af 1/*\r
2 * memory handling\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
efcba75f 10#include "pico_int.h"\r
af37bca8 11#include "memory.h"\r
cc68a136 12\r
cc68a136 13#include "sound/ym2612.h"\r
14#include "sound/sn76496.h"\r
15\r
c8d1e9b6 16extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
cc68a136 17\r
bcf65fd6 18uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
19uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
20uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
21uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
af37bca8 22\r
bcf65fd6 23static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,\r
0ace9b9a 24 const void *func_or_mh, int is_func)\r
af37bca8 25{\r
faf543ce 26#ifdef __clang__\r
27 // workaround bug (segfault) in \r
28 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
29 volatile \r
30#endif\r
bcf65fd6 31 uptr addr = (uptr)func_or_mh;\r
af37bca8 32 int mask = (1 << shift) - 1;\r
33 int i;\r
34\r
35 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r
36 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r
37 start_addr, end_addr);\r
38 return;\r
39 }\r
40\r
41 if (addr & 1) {\r
42 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r
43 return;\r
44 }\r
45\r
46 if (!is_func)\r
47 addr -= start_addr;\r
48\r
49 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
50 map[i] = addr >> 1;\r
51 if (is_func)\r
b8a1c09a 52 map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);\r
af37bca8 53 }\r
54}\r
55\r
bcf65fd6 56void z80_map_set(uptr *map, int start_addr, int end_addr,\r
0ace9b9a 57 const void *func_or_mh, int is_func)\r
af37bca8 58{\r
59 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
60}\r
61\r
bcf65fd6 62void cpu68k_map_set(uptr *map, int start_addr, int end_addr,\r
0ace9b9a 63 const void *func_or_mh, int is_func)\r
af37bca8 64{\r
65 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
66}\r
67\r
68// more specialized/optimized function (does same as above)\r
69void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r
70{\r
bcf65fd6 71 uptr *r8map, *r16map, *w8map, *w16map;\r
72 uptr addr = (uptr)ptr;\r
af37bca8 73 int shift = M68K_MEM_SHIFT;\r
74 int i;\r
75\r
76 if (!is_sub) {\r
77 r8map = m68k_read8_map;\r
78 r16map = m68k_read16_map;\r
79 w8map = m68k_write8_map;\r
80 w16map = m68k_write16_map;\r
81 } else {\r
82 r8map = s68k_read8_map;\r
83 r16map = s68k_read16_map;\r
84 w8map = s68k_write8_map;\r
85 w16map = s68k_write16_map;\r
86 }\r
87\r
88 addr -= start_addr;\r
89 addr >>= 1;\r
90 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
91 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r
92}\r
93\r
94static u32 m68k_unmapped_read8(u32 a)\r
95{\r
96 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);\r
97 return 0; // assume pulldown, as if MegaCD2 was attached\r
98}\r
99\r
100static u32 m68k_unmapped_read16(u32 a)\r
101{\r
102 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r
103 return 0;\r
104}\r
105\r
106static void m68k_unmapped_write8(u32 a, u32 d)\r
107{\r
108 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
109}\r
110\r
111static void m68k_unmapped_write16(u32 a, u32 d)\r
112{\r
113 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
114}\r
115\r
116void m68k_map_unmap(int start_addr, int end_addr)\r
117{\r
faf543ce 118#ifdef __clang__\r
119 // workaround bug (segfault) in \r
120 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
121 volatile \r
122#endif\r
bcf65fd6 123 uptr addr;\r
af37bca8 124 int shift = M68K_MEM_SHIFT;\r
125 int i;\r
126\r
bcf65fd6 127 addr = (uptr)m68k_unmapped_read8;\r
af37bca8 128 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
129 m68k_read8_map[i] = (addr >> 1) | (1 << 31);\r
130\r
bcf65fd6 131 addr = (uptr)m68k_unmapped_read16;\r
af37bca8 132 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
133 m68k_read16_map[i] = (addr >> 1) | (1 << 31);\r
134\r
bcf65fd6 135 addr = (uptr)m68k_unmapped_write8;\r
af37bca8 136 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
137 m68k_write8_map[i] = (addr >> 1) | (1 << 31);\r
138\r
bcf65fd6 139 addr = (uptr)m68k_unmapped_write16;\r
af37bca8 140 for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
141 m68k_write16_map[i] = (addr >> 1) | (1 << 31);\r
142}\r
143\r
144MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r
145MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r
146MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r
147MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r
148MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r
149MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r
150\r
151// -----------------------------------------------------------------\r
152\r
153static u32 ym2612_read_local_68k(void);\r
154static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
155static void z80_mem_setup(void);\r
cc68a136 156\r
0ace9b9a 157#ifdef _ASM_MEMORY_C\r
158u32 PicoRead8_sram(u32 a);\r
159u32 PicoRead16_sram(u32 a);\r
160#endif\r
cc68a136 161\r
03e4f2a3 162#ifdef EMU_CORE_DEBUG\r
cc68a136 163u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
164int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
165extern unsigned int ppop;\r
166#endif\r
167\r
4f65685b 168#ifdef IO_STATS\r
169void log_io(unsigned int addr, int bits, int rw);\r
dca310c4 170#elif defined(_MSC_VER)\r
171#define log_io\r
4f65685b 172#else\r
173#define log_io(...)\r
174#endif\r
175\r
70357ce5 176#if defined(EMU_C68K)\r
5e89f0f5 177void cyclone_crashed(u32 pc, struct Cyclone *context)\r
cc68a136 178{\r
bf61bea0 179 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",\r
5e89f0f5 180 context == &PicoCpuCM68k ? 'm' : 's', pc);\r
181 context->membase = (u32)Pico.rom;\r
182 context->pc = (u32)Pico.rom + Pico.romsize;\r
cc68a136 183}\r
184#endif\r
185\r
cc68a136 186// -----------------------------------------------------------------\r
af37bca8 187// memmap helpers\r
cc68a136 188\r
0ace9b9a 189#ifndef _ASM_MEMORY_C\r
190static\r
191#endif\r
192int PadRead(int i)\r
e5503e2f 193{\r
194 int pad,value,data_reg;\r
5f9a0d16 195 pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
e5503e2f 196 data_reg=Pico.ioports[i+1];\r
197\r
198 // orr the bits, which are set as output\r
199 value = data_reg&(Pico.ioports[i+4]|0x80);\r
200\r
602133e1 201 if (PicoOpt & POPT_6BTN_PAD)\r
202 {\r
e5503e2f 203 int phase = Pico.m.padTHPhase[i];\r
204\r
205 if(phase == 2 && !(data_reg&0x40)) { // TH\r
206 value|=(pad&0xc0)>>2; // ?0SA 0000\r
207 return value;\r
208 } else if(phase == 3) {\r
209 if(data_reg&0x40)\r
210 value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
211 else\r
212 value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
213 return value;\r
214 }\r
215 }\r
216\r
217 if(data_reg&0x40) // TH\r
218 value|=(pad&0x3f); // ?1CB RLDU\r
219 else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
220\r
221 return value; // will mirror later\r
222}\r
223\r
0ace9b9a 224#ifndef _ASM_MEMORY_C\r
225\r
af37bca8 226static u32 io_ports_read(u32 a)\r
cc68a136 227{\r
af37bca8 228 u32 d;\r
229 a = (a>>1) & 0xf;\r
230 switch (a) {\r
231 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)\r
232 case 1: d = PadRead(0); break;\r
233 case 2: d = PadRead(1); break;\r
234 default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r
7969166e 235 }\r
af37bca8 236 return d;\r
cc68a136 237}\r
cc68a136 238\r
5e89f0f5 239static void NOINLINE io_ports_write(u32 a, u32 d)\r
9dc09829 240{\r
af37bca8 241 a = (a>>1) & 0xf;\r
242\r
243 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
244 if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))\r
245 {\r
246 Pico.m.padDelay[a - 1] = 0;\r
247 if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r
248 Pico.m.padTHPhase[a - 1]++;\r
9dc09829 249 }\r
af37bca8 250\r
5e89f0f5 251 // certain IO ports can be used as RAM\r
af37bca8 252 Pico.ioports[a] = d;\r
9dc09829 253}\r
254\r
0ace9b9a 255#endif // _ASM_MEMORY_C\r
256\r
257void NOINLINE ctl_write_z80busreq(u32 d)\r
7969166e 258{\r
af37bca8 259 d&=1; d^=1;\r
260 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
261 if (d ^ Pico.m.z80Run)\r
262 {\r
263 if (d)\r
264 {\r
265 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
266 }\r
267 else\r
268 {\r
269 z80stopCycle = SekCyclesDone();\r
f6c49d38 270 if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {\r
271 pprof_start(m68k);\r
af37bca8 272 PicoSyncZ80(z80stopCycle);\r
f6c49d38 273 pprof_end_sub(m68k);\r
274 }\r
af37bca8 275 }\r
276 Pico.m.z80Run = d;\r
7969166e 277 }\r
af37bca8 278}\r
279\r
0ace9b9a 280void NOINLINE ctl_write_z80reset(u32 d)\r
af37bca8 281{\r
282 d&=1; d^=1;\r
283 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
284 if (d ^ Pico.m.z80_reset)\r
285 {\r
286 if (d)\r
287 {\r
f6c49d38 288 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {\r
289 pprof_start(m68k);\r
af37bca8 290 PicoSyncZ80(SekCyclesDone());\r
f6c49d38 291 pprof_end_sub(m68k);\r
292 }\r
af37bca8 293 YM2612ResetChip();\r
294 timers_reset();\r
7969166e 295 }\r
af37bca8 296 else\r
297 {\r
298 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
299 z80_reset();\r
7969166e 300 }\r
af37bca8 301 Pico.m.z80_reset = d;\r
7969166e 302 }\r
303}\r
cc68a136 304\r
af37bca8 305// -----------------------------------------------------------------\r
fa1e5e29 306\r
0ace9b9a 307#ifndef _ASM_MEMORY_C\r
308\r
af37bca8 309// cart (save) RAM area (usually 0x200000 - ...)\r
310static u32 PicoRead8_sram(u32 a)\r
311{\r
af37bca8 312 u32 d;\r
45f2f245 313 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
af37bca8 314 {\r
45f2f245 315 if (SRam.flags & SRF_EEPROM) {\r
af37bca8 316 d = EEPROM_read();\r
45f2f245 317 if (!(a & 1))\r
318 d >>= 8;\r
319 } else\r
af37bca8 320 d = *(u8 *)(SRam.data - SRam.start + a);\r
45f2f245 321 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
af37bca8 322 return d;\r
323 }\r
cc68a136 324\r
45f2f245 325 // XXX: this is banking unfriendly\r
af37bca8 326 if (a < Pico.romsize)\r
327 return Pico.rom[a ^ 1];\r
328 \r
329 return m68k_unmapped_read8(a);\r
330}\r
cc68a136 331\r
af37bca8 332static u32 PicoRead16_sram(u32 a)\r
cc68a136 333{\r
af37bca8 334 u32 d;\r
b4db550e 335 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
af37bca8 336 {\r
45f2f245 337 if (SRam.flags & SRF_EEPROM)\r
af37bca8 338 d = EEPROM_read();\r
45f2f245 339 else {\r
af37bca8 340 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
341 d = pm[0] << 8;\r
342 d |= pm[1];\r
343 }\r
344 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
345 return d;\r
346 }\r
cc68a136 347\r
af37bca8 348 if (a < Pico.romsize)\r
349 return *(u16 *)(Pico.rom + a);\r
cc68a136 350\r
af37bca8 351 return m68k_unmapped_read16(a);\r
352}\r
cc68a136 353\r
0ace9b9a 354#endif // _ASM_MEMORY_C\r
355\r
af37bca8 356static void PicoWrite8_sram(u32 a, u32 d)\r
357{\r
45f2f245 358 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
359 m68k_unmapped_write8(a, d);\r
360 return;\r
361 }\r
362\r
363 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);\r
364 if (SRam.flags & SRF_EEPROM)\r
af37bca8 365 {\r
45f2f245 366 EEPROM_write8(a, d);\r
cc68a136 367 }\r
45f2f245 368 else {\r
369 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
af37bca8 370 if (*pm != (u8)d) {\r
371 SRam.changed = 1;\r
372 *pm = (u8)d;\r
373 }\r
374 }\r
375}\r
cc68a136 376\r
af37bca8 377static void PicoWrite16_sram(u32 a, u32 d)\r
378{\r
45f2f245 379 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
380 m68k_unmapped_write16(a, d);\r
381 return;\r
382 }\r
383\r
384 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r
385 if (SRam.flags & SRF_EEPROM)\r
386 {\r
387 EEPROM_write16(d);\r
388 }\r
389 else {\r
390 // XXX: hardware could easily use MSB too..\r
391 u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
392 if (*pm != (u8)d) {\r
393 SRam.changed = 1;\r
394 *pm = (u8)d;\r
395 }\r
396 }\r
af37bca8 397}\r
cc68a136 398\r
af37bca8 399// z80 area (0xa00000 - 0xa0ffff)\r
400// TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r
401static u32 PicoRead8_z80(u32 a)\r
402{\r
403 u32 d = 0xff;\r
404 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
405 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r
406 // open bus. Pulled down if MegaCD2 is attached.\r
407 return 0;\r
408 }\r
c060a9ab 409\r
af37bca8 410 if ((a & 0x4000) == 0x0000)\r
411 d = Pico.zram[a & 0x1fff];\r
412 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
413 d = ym2612_read_local_68k(); \r
414 else\r
415 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
416 return d;\r
417}\r
b542be46 418\r
af37bca8 419static u32 PicoRead16_z80(u32 a)\r
420{\r
421 u32 d = PicoRead8_z80(a);\r
422 return d | (d << 8);\r
423}\r
424\r
425static void PicoWrite8_z80(u32 a, u32 d)\r
426{\r
427 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
428 // verified on real hw\r
429 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
430 return;\r
431 }\r
432\r
433 if ((a & 0x4000) == 0x0000) { // z80 RAM\r
434 SekCyclesBurn(2); // hack\r
435 Pico.zram[a & 0x1fff] = (u8)d;\r
436 return;\r
437 }\r
438 if ((a & 0x6000) == 0x4000) { // FM Sound\r
439 if (PicoOpt & POPT_EN_FM)\r
440 emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;\r
441 return;\r
442 }\r
443 // TODO: probably other VDP access too? Maybe more mirrors?\r
444 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r
445 if (PicoOpt & POPT_EN_PSG)\r
446 SN76496Write(d);\r
447 return;\r
448 }\r
af37bca8 449 if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
450 {\r
451 Pico.m.z80_bank68k >>= 1;\r
452 Pico.m.z80_bank68k |= d << 8;\r
453 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
454 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
455 return;\r
cc68a136 456 }\r
af37bca8 457 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
cc68a136 458}\r
459\r
af37bca8 460static void PicoWrite16_z80(u32 a, u32 d)\r
cc68a136 461{\r
af37bca8 462 // for RAM, only most significant byte is sent\r
463 // TODO: verify remaining accesses\r
464 PicoWrite8_z80(a, d >> 8);\r
465}\r
cc68a136 466\r
0ace9b9a 467#ifndef _ASM_MEMORY_C\r
468\r
af37bca8 469// IO/control area (0xa10000 - 0xa1ffff)\r
470u32 PicoRead8_io(u32 a)\r
471{\r
472 u32 d;\r
cc68a136 473\r
af37bca8 474 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
475 d = io_ports_read(a);\r
cc68a136 476 goto end;\r
477 }\r
cc68a136 478\r
af37bca8 479 // faking open bus (MegaCD pulldowns don't work here curiously)\r
480 d = Pico.m.rotate++;\r
481 d ^= d << 6;\r
cc68a136 482\r
5e89f0f5 483 if ((a & 0xfc00) == 0x1000) {\r
484 // bit8 seems to be readable in this range\r
485 if (!(a & 1))\r
486 d &= ~0x01;\r
cc68a136 487\r
5e89f0f5 488 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
489 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
490 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
491 }\r
af37bca8 492 goto end;\r
cc68a136 493 }\r
af37bca8 494\r
db1d3564 495 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 496 d = PicoRead8_32x(a);\r
497 goto end;\r
498 }\r
499\r
af37bca8 500 d = m68k_unmapped_read8(a);\r
501end:\r
cc68a136 502 return d;\r
503}\r
504\r
af37bca8 505u32 PicoRead16_io(u32 a)\r
cc68a136 506{\r
af37bca8 507 u32 d;\r
cc68a136 508\r
af37bca8 509 if ((a & 0xffe0) == 0x0000) { // I/O ports\r
510 d = io_ports_read(a);\r
bdd6a009 511 d |= d << 8;\r
cc68a136 512 goto end;\r
513 }\r
514\r
af37bca8 515 // faking open bus\r
516 d = (Pico.m.rotate += 0x41);\r
517 d ^= (d << 5) ^ (d << 8);\r
cc68a136 518\r
af37bca8 519 // bit8 seems to be readable in this range\r
5e89f0f5 520 if ((a & 0xfc00) == 0x1000) {\r
af37bca8 521 d &= ~0x0100;\r
cc68a136 522\r
5e89f0f5 523 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
524 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
525 elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
526 }\r
af37bca8 527 goto end;\r
cc68a136 528 }\r
af37bca8 529\r
db1d3564 530 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 531 d = PicoRead16_32x(a);\r
532 goto end;\r
533 }\r
534\r
af37bca8 535 d = m68k_unmapped_read16(a);\r
536end:\r
cc68a136 537 return d;\r
538}\r
cc68a136 539\r
af37bca8 540void PicoWrite8_io(u32 a, u32 d)\r
541{\r
542 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r
543 io_ports_write(a, d);\r
544 return;\r
545 }\r
546 if ((a & 0xff01) == 0x1100) { // z80 busreq\r
547 ctl_write_z80busreq(d);\r
548 return;\r
549 }\r
550 if ((a & 0xff01) == 0x1200) { // z80 reset\r
551 ctl_write_z80reset(d);\r
552 return;\r
553 }\r
554 if (a == 0xa130f1) { // sram access register\r
555 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
45f2f245 556 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
557 Pico.m.sram_reg |= (u8)(d & 3);\r
af37bca8 558 return;\r
559 }\r
db1d3564 560 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 561 PicoWrite8_32x(a, d);\r
562 return;\r
563 }\r
564\r
af37bca8 565 m68k_unmapped_write8(a, d);\r
566}\r
cc68a136 567\r
af37bca8 568void PicoWrite16_io(u32 a, u32 d)\r
cc68a136 569{\r
af37bca8 570 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r
571 io_ports_write(a, d);\r
572 return;\r
573 }\r
574 if ((a & 0xff00) == 0x1100) { // z80 busreq\r
575 ctl_write_z80busreq(d >> 8);\r
576 return;\r
577 }\r
578 if ((a & 0xff00) == 0x1200) { // z80 reset\r
579 ctl_write_z80reset(d >> 8);\r
580 return;\r
581 }\r
582 if (a == 0xa130f0) { // sram access register\r
583 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
45f2f245 584 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
585 Pico.m.sram_reg |= (u8)(d & 3);\r
af37bca8 586 return;\r
587 }\r
db1d3564 588 if (PicoOpt & POPT_EN_32X) {\r
be2c4208 589 PicoWrite16_32x(a, d);\r
590 return;\r
591 }\r
af37bca8 592 m68k_unmapped_write16(a, d);\r
593}\r
cc68a136 594\r
0ace9b9a 595#endif // _ASM_MEMORY_C\r
596\r
af37bca8 597// VDP area (0xc00000 - 0xdfffff)\r
598// TODO: verify if lower byte goes to PSG on word writes\r
599static u32 PicoRead8_vdp(u32 a)\r
600{\r
601 if ((a & 0x00e0) == 0x0000)\r
602 return PicoVideoRead8(a);\r
cc68a136 603\r
af37bca8 604 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
605 return 0;\r
cc68a136 606}\r
607\r
af37bca8 608static u32 PicoRead16_vdp(u32 a)\r
cc68a136 609{\r
af37bca8 610 if ((a & 0x00e0) == 0x0000)\r
611 return PicoVideoRead(a);\r
cc68a136 612\r
af37bca8 613 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
614 return 0;\r
cc68a136 615}\r
616\r
af37bca8 617static void PicoWrite8_vdp(u32 a, u32 d)\r
cc68a136 618{\r
af37bca8 619 if ((a & 0x00f9) == 0x0011) { // PSG Sound\r
620 if (PicoOpt & POPT_EN_PSG)\r
621 SN76496Write(d);\r
cc68a136 622 return;\r
623 }\r
af37bca8 624 if ((a & 0x00e0) == 0x0000) {\r
625 d &= 0xff;\r
626 PicoVideoWrite(a, d | (d << 8));\r
b542be46 627 return;\r
628 }\r
629\r
af37bca8 630 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
cc68a136 631}\r
632\r
af37bca8 633static void PicoWrite16_vdp(u32 a, u32 d)\r
634{\r
635 if ((a & 0x00f9) == 0x0010) { // PSG Sound\r
636 if (PicoOpt & POPT_EN_PSG)\r
637 SN76496Write(d);\r
638 return;\r
639 }\r
640 if ((a & 0x00e0) == 0x0000) {\r
641 PicoVideoWrite(a, d);\r
642 return;\r
643 }\r
644\r
645 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
646}\r
cc68a136 647\r
648// -----------------------------------------------------------------\r
f53f286a 649\r
9037e45d 650#ifdef EMU_M68K\r
651static void m68k_mem_setup(void);\r
652#endif\r
653\r
f8ef8ff7 654PICO_INTERNAL void PicoMemSetup(void)\r
655{\r
af37bca8 656 int mask, rs, a;\r
657\r
658 // setup the memory map\r
659 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
660 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);\r
661 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);\r
662 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r
663\r
664 // ROM\r
665 // align to bank size. We know ROM loader allocated enough for this\r
666 mask = (1 << M68K_MEM_SHIFT) - 1;\r
667 rs = (Pico.romsize + mask) & ~mask;\r
668 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);\r
669 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
670\r
671 // Common case of on-cart (save) RAM, usually at 0x200000-...\r
45f2f245 672 if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {\r
673 rs = SRam.end - SRam.start;\r
af37bca8 674 rs = (rs + mask) & ~mask;\r
675 if (SRam.start + rs >= 0x1000000)\r
676 rs = 0x1000000 - SRam.start;\r
677 cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r
678 cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r
679 cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r
680 cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r
681 }\r
682\r
683 // Z80 region\r
684 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r
685 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r
686 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r
687 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r
688\r
689 // IO/control region\r
690 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);\r
691 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);\r
692 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r
693 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r
694\r
695 // VDP region\r
696 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r
697 if ((a & 0xe700e0) != 0xc00000)\r
698 continue;\r
699 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);\r
700 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);\r
701 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);\r
702 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r
703 }\r
704\r
705 // RAM and it's mirrors\r
706 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
707 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r
708 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r
709 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r
710 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r
711 }\r
712\r
cc68a136 713 // Setup memory callbacks:\r
70357ce5 714#ifdef EMU_C68K\r
5e89f0f5 715 PicoCpuCM68k.read8 = (void *)m68k_read8_map;\r
716 PicoCpuCM68k.read16 = (void *)m68k_read16_map;\r
717 PicoCpuCM68k.read32 = (void *)m68k_read16_map;\r
718 PicoCpuCM68k.write8 = (void *)m68k_write8_map;\r
719 PicoCpuCM68k.write16 = (void *)m68k_write16_map;\r
720 PicoCpuCM68k.write32 = (void *)m68k_write16_map;\r
721 PicoCpuCM68k.checkpc = NULL; /* unused */\r
722 PicoCpuCM68k.fetch8 = NULL;\r
723 PicoCpuCM68k.fetch16 = NULL;\r
724 PicoCpuCM68k.fetch32 = NULL;\r
cc68a136 725#endif\r
70357ce5 726#ifdef EMU_F68K\r
af37bca8 727 PicoCpuFM68k.read_byte = m68k_read8;\r
728 PicoCpuFM68k.read_word = m68k_read16;\r
729 PicoCpuFM68k.read_long = m68k_read32;\r
730 PicoCpuFM68k.write_byte = m68k_write8;\r
731 PicoCpuFM68k.write_word = m68k_write16;\r
732 PicoCpuFM68k.write_long = m68k_write32;\r
3aa1e148 733\r
734 // setup FAME fetchmap\r
735 {\r
736 int i;\r
9037e45d 737 // by default, point everything to first 64k of ROM\r
3aa1e148 738 for (i = 0; i < M68K_FETCHBANK1; i++)\r
be26eb23 739 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
3aa1e148 740 // now real ROM\r
741 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
be26eb23 742 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
3aa1e148 743 // .. and RAM\r
744 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
be26eb23 745 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
3aa1e148 746 }\r
70357ce5 747#endif\r
9037e45d 748#ifdef EMU_M68K\r
749 m68k_mem_setup();\r
750#endif\r
c8d1e9b6 751\r
752 z80_mem_setup();\r
cc68a136 753}\r
754\r
cc68a136 755#ifdef EMU_M68K\r
9037e45d 756unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r
757unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r
758unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r
759void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;\r
760void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r
761void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;\r
cc68a136 762\r
9037e45d 763/* it appears that Musashi doesn't always mask the unused bits */\r
764unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r
765unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r
766unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r
767void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r
768void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r
769void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r
9037e45d 770\r
771static void m68k_mem_setup(void)\r
772{\r
af37bca8 773 pm68k_read_memory_8 = m68k_read8;\r
774 pm68k_read_memory_16 = m68k_read16;\r
775 pm68k_read_memory_32 = m68k_read32;\r
776 pm68k_write_memory_8 = m68k_write8;\r
777 pm68k_write_memory_16 = m68k_write16;\r
778 pm68k_write_memory_32 = m68k_write32;\r
cc68a136 779}\r
cc68a136 780#endif // EMU_M68K\r
781\r
782\r
4b9c5888 783// -----------------------------------------------------------------\r
784\r
4b9c5888 785static int get_scanline(int is_from_z80)\r
786{\r
787 if (is_from_z80) {\r
788 int cycles = z80_cyclesDone();\r
789 while (cycles - z80_scanline_cycles >= 228)\r
790 z80_scanline++, z80_scanline_cycles += 228;\r
791 return z80_scanline;\r
792 }\r
793\r
2aa27095 794 return Pico.m.scanline;\r
4b9c5888 795}\r
796\r
48dc74f2 797/* probably should not be in this file, but it's near related code here */\r
43e6eaad 798void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r
799{\r
800 int xcycles = z80_cycles << 8;\r
801\r
802 /* check for overflows */\r
803 if ((mode_old & 4) && xcycles > timer_a_next_oflow)\r
804 ym2612.OPN.ST.status |= 1;\r
805\r
806 if ((mode_old & 8) && xcycles > timer_b_next_oflow)\r
807 ym2612.OPN.ST.status |= 2;\r
808\r
809 /* update timer a */\r
810 if (mode_old & 1)\r
e53704e6 811 while (xcycles > timer_a_next_oflow)\r
43e6eaad 812 timer_a_next_oflow += timer_a_step;\r
813\r
814 if ((mode_old ^ mode_new) & 1) // turning on/off\r
815 {\r
48dc74f2 816 if (mode_old & 1)\r
e53704e6 817 timer_a_next_oflow = TIMER_NO_OFLOW;\r
43e6eaad 818 else\r
48dc74f2 819 timer_a_next_oflow = xcycles + timer_a_step;\r
43e6eaad 820 }\r
821 if (mode_new & 1)\r
822 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);\r
823\r
824 /* update timer b */\r
825 if (mode_old & 2)\r
e53704e6 826 while (xcycles > timer_b_next_oflow)\r
43e6eaad 827 timer_b_next_oflow += timer_b_step;\r
828\r
829 if ((mode_old ^ mode_new) & 2)\r
830 {\r
48dc74f2 831 if (mode_old & 2)\r
e53704e6 832 timer_b_next_oflow = TIMER_NO_OFLOW;\r
43e6eaad 833 else\r
48dc74f2 834 timer_b_next_oflow = xcycles + timer_b_step;\r
43e6eaad 835 }\r
836 if (mode_new & 2)\r
837 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);\r
838}\r
839\r
4b9c5888 840// ym2612 DAC and timer I/O handlers for z80\r
af37bca8 841static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
4b9c5888 842{\r
843 int addr;\r
844\r
845 a &= 3;\r
846 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */\r
847 {\r
848 int scanline = get_scanline(is_from_z80);\r
849 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);\r
850 ym2612.dacout = ((int)d - 0x80) << 6;\r
851 if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)\r
852 PsndDoDAC(scanline);\r
853 return 0;\r
854 }\r
855\r
856 switch (a)\r
857 {\r
858 case 0: /* address port 0 */\r
859 ym2612.OPN.ST.address = d;\r
860 ym2612.addr_A1 = 0;\r
861#ifdef __GP2X__\r
862 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
863#endif\r
864 return 0;\r
865\r
866 case 1: /* data port 0 */\r
867 if (ym2612.addr_A1 != 0)\r
868 return 0;\r
869\r
870 addr = ym2612.OPN.ST.address;\r
871 ym2612.REGS[addr] = d;\r
872\r
873 switch (addr)\r
874 {\r
875 case 0x24: // timer A High 8\r
876 case 0x25: { // timer A Low 2\r
877 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r
878 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r
879 if (ym2612.OPN.ST.TA != TAnew)\r
880 {\r
881 //elprintf(EL_STATUS, "timer a set %i", TAnew);\r
882 ym2612.OPN.ST.TA = TAnew;\r
e53704e6 883 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r
4b9c5888 884 //ym2612.OPN.ST.TAT = 0;\r
48dc74f2 885 timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
43e6eaad 886 if (ym2612.OPN.ST.mode & 1) {\r
48dc74f2 887 // this is not right, should really be done on overflow only\r
4b9c5888 888 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
889 timer_a_next_oflow = (cycles << 8) + timer_a_step;\r
4b9c5888 890 }\r
43e6eaad 891 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r
4b9c5888 892 }\r
893 return 0;\r
894 }\r
895 case 0x26: // timer B\r
896 if (ym2612.OPN.ST.TB != d) {\r
897 //elprintf(EL_STATUS, "timer b set %i", d);\r
898 ym2612.OPN.ST.TB = d;\r
e53704e6 899 //ym2612.OPN.ST.TBC = (256-d) * 288;\r
4b9c5888 900 //ym2612.OPN.ST.TBT = 0;\r
48dc74f2 901 timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r
43e6eaad 902 if (ym2612.OPN.ST.mode & 2) {\r
903 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
904 timer_b_next_oflow = (cycles << 8) + timer_b_step;\r
905 }\r
906 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r
4b9c5888 907 }\r
908 return 0;\r
909 case 0x27: { /* mode, timer control */\r
910 int old_mode = ym2612.OPN.ST.mode;\r
43e6eaad 911 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
912 ym2612.OPN.ST.mode = d;\r
4b9c5888 913\r
43e6eaad 914 elprintf(EL_YMTIMER, "st mode %02x", d);\r
915 ym2612_sync_timers(cycles, old_mode, d);\r
4b9c5888 916\r
43e6eaad 917 /* reset Timer a flag */\r
918 if (d & 0x10)\r
919 ym2612.OPN.ST.status &= ~1;\r
4b9c5888 920\r
921 /* reset Timer b flag */\r
922 if (d & 0x20)\r
923 ym2612.OPN.ST.status &= ~2;\r
924\r
43e6eaad 925 if ((d ^ old_mode) & 0xc0) {\r
4b9c5888 926#ifdef __GP2X__\r
52250671 927 if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
4b9c5888 928#endif\r
43e6eaad 929 return 1;\r
930 }\r
4b9c5888 931 return 0;\r
932 }\r
933 case 0x2b: { /* DAC Sel (YM2612) */\r
934 int scanline = get_scanline(is_from_z80);\r
935 ym2612.dacen = d & 0x80;\r
936 if (d & 0x80) PsndDacLine = scanline;\r
937#ifdef __GP2X__\r
938 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);\r
939#endif\r
940 return 0;\r
941 }\r
942 }\r
943 break;\r
944\r
945 case 2: /* address port 1 */\r
946 ym2612.OPN.ST.address = d;\r
947 ym2612.addr_A1 = 1;\r
948#ifdef __GP2X__\r
949 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
950#endif\r
951 return 0;\r
952\r
953 case 3: /* data port 1 */\r
954 if (ym2612.addr_A1 != 1)\r
955 return 0;\r
956\r
957 addr = ym2612.OPN.ST.address | 0x100;\r
958 ym2612.REGS[addr] = d;\r
959 break;\r
960 }\r
961\r
962#ifdef __GP2X__\r
963 if (PicoOpt & POPT_EXT_FM)\r
964 return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
965#endif\r
966 return YM2612Write_(a, d);\r
967}\r
968\r
453d2a6e 969\r
43e6eaad 970#define ym2612_read_local() \\r
971 if (xcycles >= timer_a_next_oflow) \\r
972 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r
973 if (xcycles >= timer_b_next_oflow) \\r
974 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
975\r
553c3eaa 976static u32 ym2612_read_local_z80(void)\r
4b9c5888 977{\r
978 int xcycles = z80_cyclesDone() << 8;\r
4b9c5888 979\r
43e6eaad 980 ym2612_read_local();\r
981\r
982 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
983 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
984 return ym2612.OPN.ST.status;\r
985}\r
986\r
af37bca8 987static u32 ym2612_read_local_68k(void)\r
43e6eaad 988{\r
989 int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r
990\r
991 ym2612_read_local();\r
992\r
993 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,\r
994 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);\r
4b9c5888 995 return ym2612.OPN.ST.status;\r
996}\r
997\r
d2721b08 998void ym2612_pack_state(void)\r
999{\r
e53704e6 1000 // timers are saved as tick counts, in 16.16 int format\r
1001 int tac, tat = 0, tbc, tbt = 0;\r
1002 tac = 1024 - ym2612.OPN.ST.TA;\r
1003 tbc = 256 - ym2612.OPN.ST.TB;\r
1004 if (timer_a_next_oflow != TIMER_NO_OFLOW)\r
1005 tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);\r
1006 if (timer_b_next_oflow != TIMER_NO_OFLOW)\r
1007 tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);\r
1008 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r
1009 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r
1010\r
d2721b08 1011#ifdef __GP2X__\r
1012 if (PicoOpt & POPT_EXT_FM)\r
e4fb433c 1013 YM2612PicoStateSave2_940(tat, tbt);\r
d2721b08 1014 else\r
1015#endif\r
e53704e6 1016 YM2612PicoStateSave2(tat, tbt);\r
d2721b08 1017}\r
1018\r
453d2a6e 1019void ym2612_unpack_state(void)\r
1020{\r
e53704e6 1021 int i, ret, tac, tat, tbc, tbt;\r
453d2a6e 1022 YM2612PicoStateLoad();\r
1023\r
1024 // feed all the registers and update internal state\r
db49317b 1025 for (i = 0x20; i < 0xA0; i++) {\r
453d2a6e 1026 ym2612_write_local(0, i, 0);\r
1027 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1028 }\r
db49317b 1029 for (i = 0x30; i < 0xA0; i++) {\r
1030 ym2612_write_local(2, i, 0);\r
1031 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1032 }\r
1033 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r
1034 ym2612_write_local(2, i, 0);\r
1035 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1036 ym2612_write_local(0, i, 0);\r
1037 ym2612_write_local(1, ym2612.REGS[i], 0);\r
1038 }\r
1039 for (i = 0xB0; i < 0xB8; i++) {\r
1040 ym2612_write_local(0, i, 0);\r
1041 ym2612_write_local(1, ym2612.REGS[i], 0);\r
453d2a6e 1042 ym2612_write_local(2, i, 0);\r
1043 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
1044 }\r
d2721b08 1045\r
1046#ifdef __GP2X__\r
1047 if (PicoOpt & POPT_EXT_FM)\r
e4fb433c 1048 ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r
d2721b08 1049 else\r
1050#endif\r
1051 ret = YM2612PicoStateLoad2(&tat, &tbt);\r
db49317b 1052 if (ret != 0) {\r
1053 elprintf(EL_STATUS, "old ym2612 state");\r
1054 return; // no saved timers\r
1055 }\r
e53704e6 1056\r
1057 tac = (1024 - ym2612.OPN.ST.TA) << 16;\r
1058 tbc = (256 - ym2612.OPN.ST.TB) << 16;\r
1059 if (ym2612.OPN.ST.mode & 1)\r
48dc74f2 1060 timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);\r
e53704e6 1061 else\r
1062 timer_a_next_oflow = TIMER_NO_OFLOW;\r
1063 if (ym2612.OPN.ST.mode & 2)\r
48dc74f2 1064 timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);\r
e53704e6 1065 else\r
1066 timer_b_next_oflow = TIMER_NO_OFLOW;\r
1067 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);\r
1068 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);\r
453d2a6e 1069}\r
1070\r
f3a57b2d 1071#if defined(NO_32X) && defined(_ASM_MEMORY_C)\r
1072// referenced by asm code\r
1073u32 PicoRead8_32x(u32 a) { return 0; }\r
1074u32 PicoRead16_32x(u32 a) { return 0; }\r
1075void PicoWrite8_32x(u32 a, u32 d) {}\r
1076void PicoWrite16_32x(u32 a, u32 d) {}\r
1077#endif\r
1078\r
cc68a136 1079// -----------------------------------------------------------------\r
1080// z80 memhandlers\r
1081\r
553c3eaa 1082static unsigned char z80_md_vdp_read(unsigned short a)\r
cc68a136 1083{\r
c8d1e9b6 1084 // TODO?\r
1085 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
1086 return 0xff;\r
1087}\r
cc68a136 1088\r
553c3eaa 1089static unsigned char z80_md_bank_read(unsigned short a)\r
c8d1e9b6 1090{\r
c8d1e9b6 1091 unsigned int addr68k;\r
1092 unsigned char ret;\r
cc68a136 1093\r
c8d1e9b6 1094 addr68k = Pico.m.z80_bank68k<<15;\r
1095 addr68k += a & 0x7fff;\r
1096\r
af37bca8 1097 ret = m68k_read8(addr68k);\r
cc68a136 1098\r
c8d1e9b6 1099 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
cc68a136 1100 return ret;\r
1101}\r
1102\r
553c3eaa 1103static void z80_md_ym2612_write(unsigned int a, unsigned char data)\r
cc68a136 1104{\r
c8d1e9b6 1105 if (PicoOpt & POPT_EN_FM)\r
1106 emustatus |= ym2612_write_local(a, data, 1) & 1;\r
1107}\r
cc68a136 1108\r
553c3eaa 1109static void z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
c8d1e9b6 1110{\r
1111 // TODO: allow full VDP access\r
1112 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
cc68a136 1113 {\r
c8d1e9b6 1114 if (PicoOpt & POPT_EN_PSG)\r
1115 SN76496Write(data);\r
cc68a136 1116 return;\r
1117 }\r
1118\r
c8d1e9b6 1119 if ((a>>8) == 0x60)\r
cc68a136 1120 {\r
c8d1e9b6 1121 Pico.m.z80_bank68k >>= 1;\r
1122 Pico.m.z80_bank68k |= data << 8;\r
1123 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
cc68a136 1124 return;\r
1125 }\r
1126\r
c8d1e9b6 1127 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
1128}\r
cc68a136 1129\r
553c3eaa 1130static void z80_md_bank_write(unsigned int a, unsigned char data)\r
c8d1e9b6 1131{\r
c8d1e9b6 1132 unsigned int addr68k;\r
69996cb7 1133\r
c8d1e9b6 1134 addr68k = Pico.m.z80_bank68k << 15;\r
1135 addr68k += a & 0x7fff;\r
1136\r
1137 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
af37bca8 1138 m68k_write8(addr68k, data);\r
cc68a136 1139}\r
1140\r
c8d1e9b6 1141// -----------------------------------------------------------------\r
1142\r
1143static unsigned char z80_md_in(unsigned short p)\r
a4221917 1144{\r
c8d1e9b6 1145 elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r
1146 return 0xff;\r
a4221917 1147}\r
1148\r
c8d1e9b6 1149static void z80_md_out(unsigned short p, unsigned char d)\r
cc68a136 1150{\r
c8d1e9b6 1151 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
cc68a136 1152}\r
c8d1e9b6 1153\r
af37bca8 1154static void z80_mem_setup(void)\r
c8d1e9b6 1155{\r
1156 z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1157 z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1158 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
1159 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
1160 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
1161\r
1162 z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r
1163 z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r
1164 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
1165 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
1166 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
1167\r
1168#ifdef _USE_DRZ80\r
1169 drZ80.z80_in = z80_md_in;\r
1170 drZ80.z80_out = z80_md_out;\r
1171#endif\r
1172#ifdef _USE_CZ80\r
b8a1c09a 1173 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM\r
1174 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror\r
c8d1e9b6 1175 Cz80_Set_INPort(&CZ80, z80_md_in);\r
1176 Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
a4221917 1177#endif\r
c8d1e9b6 1178}\r
cc68a136 1179\r