notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: handle $ra accesses in DS (BxxZAL case only)
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
1e973cb0 182#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 183
184 /* stubs */
185#define CC_STUB 1
186#define FP_STUB 2
187#define LOADB_STUB 3
188#define LOADH_STUB 4
189#define LOADW_STUB 5
190#define LOADD_STUB 6
191#define LOADBU_STUB 7
192#define LOADHU_STUB 8
193#define STOREB_STUB 9
194#define STOREH_STUB 10
195#define STOREW_STUB 11
196#define STORED_STUB 12
197#define STORELR_STUB 13
198#define INVCODE_STUB 14
199
200 /* branch codes */
201#define TAKEN 1
202#define NOTTAKEN 2
203#define NULLDS 3
204
205// asm linkage
206int new_recompile_block(int addr);
207void *get_addr_ht(u_int vaddr);
208void invalidate_block(u_int block);
209void invalidate_addr(u_int addr);
210void remove_hash(int vaddr);
211void jump_vaddr();
212void dyna_linker();
213void dyna_linker_ds();
214void verify_code();
215void verify_code_vm();
216void verify_code_ds();
217void cc_interrupt();
218void fp_exception();
219void fp_exception_ds();
220void jump_syscall();
7139f3c8 221void jump_syscall_hle();
57871462 222void jump_eret();
7139f3c8 223void jump_hlecall();
1e973cb0 224void jump_intcall();
7139f3c8 225void new_dyna_leave();
57871462 226
227// TLB
228void TLBWI_new();
229void TLBWR_new();
230void read_nomem_new();
231void read_nomemb_new();
232void read_nomemh_new();
233void read_nomemd_new();
234void write_nomem_new();
235void write_nomemb_new();
236void write_nomemh_new();
237void write_nomemd_new();
238void write_rdram_new();
239void write_rdramb_new();
240void write_rdramh_new();
241void write_rdramd_new();
242extern u_int memory_map[1048576];
243
244// Needed by assembler
245void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248void load_all_regs(signed char i_regmap[]);
249void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250void load_regs_entry(int t);
251void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253int tracedebug=0;
254
255//#define DEBUG_CYCLE_COUNT 1
256
257void nullf() {}
258//#define assem_debug printf
259//#define inv_debug printf
260#define assem_debug nullf
261#define inv_debug nullf
262
94d23bb9 263static void tlb_hacks()
57871462 264{
94d23bb9 265#ifndef DISABLE_TLB
57871462 266 // Goldeneye hack
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268 {
269 u_int addr;
270 int n;
271 switch (ROM_HEADER->Country_code&0xFF)
272 {
273 case 0x45: // U
274 addr=0x34b30;
275 break;
276 case 0x4A: // J
277 addr=0x34b70;
278 break;
279 case 0x50: // E
280 addr=0x329f0;
281 break;
282 default:
283 // Unknown country code
284 addr=0;
285 break;
286 }
287 u_int rom_addr=(u_int)rom;
288 #ifdef ROM_COPY
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
299 }
300 #endif
301 if(addr) {
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304 }
305 }
306 }
94d23bb9 307#endif
57871462 308}
309
94d23bb9 310static u_int get_page(u_int vaddr)
57871462 311{
312 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 313#ifndef DISABLE_TLB
57871462 314 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 315#endif
57871462 316 if(page>2048) page=2048+(page&2047);
94d23bb9 317 return page;
318}
319
320static u_int get_vpage(u_int vaddr)
321{
322 u_int vpage=(vaddr^0x80000000)>>12;
323#ifndef DISABLE_TLB
57871462 324 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 325#endif
57871462 326 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 327 return vpage;
328}
329
330// Get address from virtual address
331// This is called from the recompiled JR/JALR instructions
332void *get_addr(u_int vaddr)
333{
334 u_int page=get_page(vaddr);
335 u_int vpage=get_vpage(vaddr);
57871462 336 struct ll_entry *head;
337 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 head=jump_in[page];
339 while(head!=NULL) {
340 if(head->vaddr==vaddr&&head->reg32==0) {
341 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
342 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[3]=ht_bin[1];
344 ht_bin[2]=ht_bin[0];
345 ht_bin[1]=(int)head->addr;
346 ht_bin[0]=vaddr;
347 return head->addr;
348 }
349 head=head->next;
350 }
351 head=jump_dirty[vpage];
352 while(head!=NULL) {
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 // Don't restore blocks which are about to expire from the cache
356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
357 if(verify_dirty(head->addr)) {
358 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
359 invalid_code[vaddr>>12]=0;
360 memory_map[vaddr>>12]|=0x40000000;
361 if(vpage<2048) {
94d23bb9 362#ifndef DISABLE_TLB
57871462 363 if(tlb_LUT_r[vaddr>>12]) {
364 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
365 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 }
94d23bb9 367#endif
57871462 368 restore_candidate[vpage>>3]|=1<<(vpage&7);
369 }
370 else restore_candidate[page>>3]|=1<<(page&7);
371 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
372 if(ht_bin[0]==vaddr) {
373 ht_bin[1]=(int)head->addr; // Replace existing entry
374 }
375 else
376 {
377 ht_bin[3]=ht_bin[1];
378 ht_bin[2]=ht_bin[0];
379 ht_bin[1]=(int)head->addr;
380 ht_bin[0]=vaddr;
381 }
382 return head->addr;
383 }
384 }
385 head=head->next;
386 }
387 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
388 int r=new_recompile_block(vaddr);
389 if(r==0) return get_addr(vaddr);
390 // Execute in unmapped page, generate pagefault execption
391 Status|=2;
392 Cause=(vaddr<<31)|0x8;
393 EPC=(vaddr&1)?vaddr-5:vaddr;
394 BadVAddr=(vaddr&~1);
395 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
396 EntryHi=BadVAddr&0xFFFFE000;
397 return get_addr_ht(0x80000000);
398}
399// Look up address in hash table first
400void *get_addr_ht(u_int vaddr)
401{
402 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 return get_addr(vaddr);
407}
408
409void *get_addr_32(u_int vaddr,u_int flags)
410{
7139f3c8 411#ifdef FORCE32
412 return get_addr(vaddr);
560e4a12 413#else
57871462 414 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
415 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
417 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 418 u_int page=get_page(vaddr);
419 u_int vpage=get_vpage(vaddr);
57871462 420 struct ll_entry *head;
421 head=jump_in[page];
422 while(head!=NULL) {
423 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
424 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
425 if(head->reg32==0) {
426 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
427 if(ht_bin[0]==-1) {
428 ht_bin[1]=(int)head->addr;
429 ht_bin[0]=vaddr;
430 }else if(ht_bin[2]==-1) {
431 ht_bin[3]=(int)head->addr;
432 ht_bin[2]=vaddr;
433 }
434 //ht_bin[3]=ht_bin[1];
435 //ht_bin[2]=ht_bin[0];
436 //ht_bin[1]=(int)head->addr;
437 //ht_bin[0]=vaddr;
438 }
439 return head->addr;
440 }
441 head=head->next;
442 }
443 head=jump_dirty[vpage];
444 while(head!=NULL) {
445 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
446 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
447 // Don't restore blocks which are about to expire from the cache
448 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
449 if(verify_dirty(head->addr)) {
450 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
451 invalid_code[vaddr>>12]=0;
452 memory_map[vaddr>>12]|=0x40000000;
453 if(vpage<2048) {
94d23bb9 454#ifndef DISABLE_TLB
57871462 455 if(tlb_LUT_r[vaddr>>12]) {
456 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
457 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 }
94d23bb9 459#endif
57871462 460 restore_candidate[vpage>>3]|=1<<(vpage&7);
461 }
462 else restore_candidate[page>>3]|=1<<(page&7);
463 if(head->reg32==0) {
464 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
465 if(ht_bin[0]==-1) {
466 ht_bin[1]=(int)head->addr;
467 ht_bin[0]=vaddr;
468 }else if(ht_bin[2]==-1) {
469 ht_bin[3]=(int)head->addr;
470 ht_bin[2]=vaddr;
471 }
472 //ht_bin[3]=ht_bin[1];
473 //ht_bin[2]=ht_bin[0];
474 //ht_bin[1]=(int)head->addr;
475 //ht_bin[0]=vaddr;
476 }
477 return head->addr;
478 }
479 }
480 head=head->next;
481 }
482 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
483 int r=new_recompile_block(vaddr);
484 if(r==0) return get_addr(vaddr);
485 // Execute in unmapped page, generate pagefault execption
486 Status|=2;
487 Cause=(vaddr<<31)|0x8;
488 EPC=(vaddr&1)?vaddr-5:vaddr;
489 BadVAddr=(vaddr&~1);
490 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
491 EntryHi=BadVAddr&0xFFFFE000;
492 return get_addr_ht(0x80000000);
560e4a12 493#endif
57871462 494}
495
496void clear_all_regs(signed char regmap[])
497{
498 int hr;
499 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
500}
501
502signed char get_reg(signed char regmap[],int r)
503{
504 int hr;
505 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
506 return -1;
507}
508
509// Find a register that is available for two consecutive cycles
510signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
514 return -1;
515}
516
517int count_free_regs(signed char regmap[])
518{
519 int count=0;
520 int hr;
521 for(hr=0;hr<HOST_REGS;hr++)
522 {
523 if(hr!=EXCLUDE_REG) {
524 if(regmap[hr]<0) count++;
525 }
526 }
527 return count;
528}
529
530void dirty_reg(struct regstat *cur,signed char reg)
531{
532 int hr;
533 if(!reg) return;
534 for (hr=0;hr<HOST_REGS;hr++) {
535 if((cur->regmap[hr]&63)==reg) {
536 cur->dirty|=1<<hr;
537 }
538 }
539}
540
541// If we dirty the lower half of a 64 bit register which is now being
542// sign-extended, we need to dump the upper half.
543// Note: Do this only after completion of the instruction, because
544// some instructions may need to read the full 64-bit value even if
545// overwriting it (eg SLTI, DSRA32).
546static void flush_dirty_uppers(struct regstat *cur)
547{
548 int hr,reg;
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if((cur->dirty>>hr)&1) {
551 reg=cur->regmap[hr];
552 if(reg>=64)
553 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
554 }
555 }
556}
557
558void set_const(struct regstat *cur,signed char reg,uint64_t value)
559{
560 int hr;
561 if(!reg) return;
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if(cur->regmap[hr]==reg) {
564 cur->isconst|=1<<hr;
565 cur->constmap[hr]=value;
566 }
567 else if((cur->regmap[hr]^64)==reg) {
568 cur->isconst|=1<<hr;
569 cur->constmap[hr]=value>>32;
570 }
571 }
572}
573
574void clear_const(struct regstat *cur,signed char reg)
575{
576 int hr;
577 if(!reg) return;
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->regmap[hr]&63)==reg) {
580 cur->isconst&=~(1<<hr);
581 }
582 }
583}
584
585int is_const(struct regstat *cur,signed char reg)
586{
587 int hr;
588 if(!reg) return 1;
589 for (hr=0;hr<HOST_REGS;hr++) {
590 if((cur->regmap[hr]&63)==reg) {
591 return (cur->isconst>>hr)&1;
592 }
593 }
594 return 0;
595}
596uint64_t get_const(struct regstat *cur,signed char reg)
597{
598 int hr;
599 if(!reg) return 0;
600 for (hr=0;hr<HOST_REGS;hr++) {
601 if(cur->regmap[hr]==reg) {
602 return cur->constmap[hr];
603 }
604 }
605 printf("Unknown constant in r%d\n",reg);
606 exit(1);
607}
608
609// Least soon needed registers
610// Look at the next ten instructions and see which registers
611// will be used. Try not to reallocate these.
612void lsn(u_char hsn[], int i, int *preferred_reg)
613{
614 int j;
615 int b=-1;
616 for(j=0;j<9;j++)
617 {
618 if(i+j>=slen) {
619 j=slen-i-1;
620 break;
621 }
622 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
623 {
624 // Don't go past an unconditonal jump
625 j++;
626 break;
627 }
628 }
629 for(;j>=0;j--)
630 {
631 if(rs1[i+j]) hsn[rs1[i+j]]=j;
632 if(rs2[i+j]) hsn[rs2[i+j]]=j;
633 if(rt1[i+j]) hsn[rt1[i+j]]=j;
634 if(rt2[i+j]) hsn[rt2[i+j]]=j;
635 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
636 // Stores can allocate zero
637 hsn[rs1[i+j]]=j;
638 hsn[rs2[i+j]]=j;
639 }
640 // On some architectures stores need invc_ptr
641 #if defined(HOST_IMM8)
b9b61529 642 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 643 hsn[INVCP]=j;
644 }
645 #endif
646 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
647 {
648 hsn[CCREG]=j;
649 b=j;
650 }
651 }
652 if(b>=0)
653 {
654 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
655 {
656 // Follow first branch
657 int t=(ba[i+b]-start)>>2;
658 j=7-b;if(t+j>=slen) j=slen-t-1;
659 for(;j>=0;j--)
660 {
661 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
662 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
663 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
664 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
665 }
666 }
667 // TODO: preferred register based on backward branch
668 }
669 // Delay slot should preferably not overwrite branch conditions or cycle count
670 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
671 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
672 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
673 hsn[CCREG]=1;
674 // ...or hash tables
675 hsn[RHASH]=1;
676 hsn[RHTBL]=1;
677 }
678 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 679 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 680 hsn[FTEMP]=0;
681 }
682 // Load L/R also uses FTEMP as a temporary register
683 if(itype[i]==LOADLR) {
684 hsn[FTEMP]=0;
685 }
b7918751 686 // Also SWL/SWR/SDL/SDR
687 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 688 hsn[FTEMP]=0;
689 }
690 // Don't remove the TLB registers either
b9b61529 691 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 692 hsn[TLREG]=0;
693 }
694 // Don't remove the miniht registers
695 if(itype[i]==UJUMP||itype[i]==RJUMP)
696 {
697 hsn[RHASH]=0;
698 hsn[RHTBL]=0;
699 }
700}
701
702// We only want to allocate registers if we're going to use them again soon
703int needed_again(int r, int i)
704{
705 int j;
706 int b=-1;
707 int rn=10;
708 int hr;
709 u_char hsn[MAXREG+1];
710 int preferred_reg;
711
712 memset(hsn,10,sizeof(hsn));
713 lsn(hsn,i,&preferred_reg);
714
715 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
716 {
717 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
718 return 0; // Don't need any registers if exiting the block
719 }
720 for(j=0;j<9;j++)
721 {
722 if(i+j>=slen) {
723 j=slen-i-1;
724 break;
725 }
726 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
727 {
728 // Don't go past an unconditonal jump
729 j++;
730 break;
731 }
1e973cb0 732 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 733 {
734 break;
735 }
736 }
737 for(;j>=1;j--)
738 {
739 if(rs1[i+j]==r) rn=j;
740 if(rs2[i+j]==r) rn=j;
741 if((unneeded_reg[i+j]>>r)&1) rn=10;
742 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
743 {
744 b=j;
745 }
746 }
747 /*
748 if(b>=0)
749 {
750 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
751 {
752 // Follow first branch
753 int o=rn;
754 int t=(ba[i+b]-start)>>2;
755 j=7-b;if(t+j>=slen) j=slen-t-1;
756 for(;j>=0;j--)
757 {
758 if(!((unneeded_reg[t+j]>>r)&1)) {
759 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
760 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
761 }
762 else rn=o;
763 }
764 }
765 }*/
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(hr!=EXCLUDE_REG) {
768 if(rn<hsn[hr]) return 1;
769 }
770 }
771 return 0;
772}
773
774// Try to match register allocations at the end of a loop with those
775// at the beginning
776int loop_reg(int i, int r, int hr)
777{
778 int j,k;
779 for(j=0;j<9;j++)
780 {
781 if(i+j>=slen) {
782 j=slen-i-1;
783 break;
784 }
785 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
786 {
787 // Don't go past an unconditonal jump
788 j++;
789 break;
790 }
791 }
792 k=0;
793 if(i>0){
794 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
795 k--;
796 }
797 for(;k<j;k++)
798 {
799 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
800 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
801 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
802 {
803 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
804 {
805 int t=(ba[i+k]-start)>>2;
806 int reg=get_reg(regs[t].regmap_entry,r);
807 if(reg>=0) return reg;
808 //reg=get_reg(regs[t+1].regmap_entry,r);
809 //if(reg>=0) return reg;
810 }
811 }
812 }
813 return hr;
814}
815
816
817// Allocate every register, preserving source/target regs
818void alloc_all(struct regstat *cur,int i)
819{
820 int hr;
821
822 for(hr=0;hr<HOST_REGS;hr++) {
823 if(hr!=EXCLUDE_REG) {
824 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
825 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
826 {
827 cur->regmap[hr]=-1;
828 cur->dirty&=~(1<<hr);
829 }
830 // Don't need zeros
831 if((cur->regmap[hr]&63)==0)
832 {
833 cur->regmap[hr]=-1;
834 cur->dirty&=~(1<<hr);
835 }
836 }
837 }
838}
839
840
841void div64(int64_t dividend,int64_t divisor)
842{
843 lo=dividend/divisor;
844 hi=dividend%divisor;
845 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
846 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
847}
848void divu64(uint64_t dividend,uint64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855
856void mult64(uint64_t m1,uint64_t m2)
857{
858 unsigned long long int op1, op2, op3, op4;
859 unsigned long long int result1, result2, result3, result4;
860 unsigned long long int temp1, temp2, temp3, temp4;
861 int sign = 0;
862
863 if (m1 < 0)
864 {
865 op2 = -m1;
866 sign = 1 - sign;
867 }
868 else op2 = m1;
869 if (m2 < 0)
870 {
871 op4 = -m2;
872 sign = 1 - sign;
873 }
874 else op4 = m2;
875
876 op1 = op2 & 0xFFFFFFFF;
877 op2 = (op2 >> 32) & 0xFFFFFFFF;
878 op3 = op4 & 0xFFFFFFFF;
879 op4 = (op4 >> 32) & 0xFFFFFFFF;
880
881 temp1 = op1 * op3;
882 temp2 = (temp1 >> 32) + op1 * op4;
883 temp3 = op2 * op3;
884 temp4 = (temp3 >> 32) + op2 * op4;
885
886 result1 = temp1 & 0xFFFFFFFF;
887 result2 = temp2 + (temp3 & 0xFFFFFFFF);
888 result3 = (result2 >> 32) + temp4;
889 result4 = (result3 >> 32);
890
891 lo = result1 | (result2 << 32);
892 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
893 if (sign)
894 {
895 hi = ~hi;
896 if (!lo) hi++;
897 else lo = ~lo + 1;
898 }
899}
900
901void multu64(uint64_t m1,uint64_t m2)
902{
903 unsigned long long int op1, op2, op3, op4;
904 unsigned long long int result1, result2, result3, result4;
905 unsigned long long int temp1, temp2, temp3, temp4;
906
907 op1 = m1 & 0xFFFFFFFF;
908 op2 = (m1 >> 32) & 0xFFFFFFFF;
909 op3 = m2 & 0xFFFFFFFF;
910 op4 = (m2 >> 32) & 0xFFFFFFFF;
911
912 temp1 = op1 * op3;
913 temp2 = (temp1 >> 32) + op1 * op4;
914 temp3 = op2 * op3;
915 temp4 = (temp3 >> 32) + op2 * op4;
916
917 result1 = temp1 & 0xFFFFFFFF;
918 result2 = temp2 + (temp3 & 0xFFFFFFFF);
919 result3 = (result2 >> 32) + temp4;
920 result4 = (result3 >> 32);
921
922 lo = result1 | (result2 << 32);
923 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
924
925 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
926 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
927}
928
929uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
930{
931 if(bits) {
932 original<<=64-bits;
933 original>>=64-bits;
934 loaded<<=bits;
935 original|=loaded;
936 }
937 else original=loaded;
938 return original;
939}
940uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
941{
942 if(bits^56) {
943 original>>=64-(bits^56);
944 original<<=64-(bits^56);
945 loaded>>=bits^56;
946 original|=loaded;
947 }
948 else original=loaded;
949 return original;
950}
951
952#ifdef __i386__
953#include "assem_x86.c"
954#endif
955#ifdef __x86_64__
956#include "assem_x64.c"
957#endif
958#ifdef __arm__
959#include "assem_arm.c"
960#endif
961
962// Add virtual address mapping to linked list
963void ll_add(struct ll_entry **head,int vaddr,void *addr)
964{
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
969 new_entry->reg32=0;
970 new_entry->addr=addr;
971 new_entry->next=*head;
972 *head=new_entry;
973}
974
975// Add virtual address mapping for 32-bit compiled block
976void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
977{
7139f3c8 978 ll_add(head,vaddr,addr);
979#ifndef FORCE32
980 (*head)->reg32=reg32;
981#endif
57871462 982}
983
984// Check if an address is already compiled
985// but don't return addresses which are about to expire from the cache
986void *check_addr(u_int vaddr)
987{
988 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
989 if(ht_bin[0]==vaddr) {
990 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
991 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
992 }
993 if(ht_bin[2]==vaddr) {
994 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
995 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
996 }
94d23bb9 997 u_int page=get_page(vaddr);
57871462 998 struct ll_entry *head;
999 head=jump_in[page];
1000 while(head!=NULL) {
1001 if(head->vaddr==vaddr&&head->reg32==0) {
1002 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1003 // Update existing entry with current address
1004 if(ht_bin[0]==vaddr) {
1005 ht_bin[1]=(int)head->addr;
1006 return head->addr;
1007 }
1008 if(ht_bin[2]==vaddr) {
1009 ht_bin[3]=(int)head->addr;
1010 return head->addr;
1011 }
1012 // Insert into hash table with low priority.
1013 // Don't evict existing entries, as they are probably
1014 // addresses that are being accessed frequently.
1015 if(ht_bin[0]==-1) {
1016 ht_bin[1]=(int)head->addr;
1017 ht_bin[0]=vaddr;
1018 }else if(ht_bin[2]==-1) {
1019 ht_bin[3]=(int)head->addr;
1020 ht_bin[2]=vaddr;
1021 }
1022 return head->addr;
1023 }
1024 }
1025 head=head->next;
1026 }
1027 return 0;
1028}
1029
1030void remove_hash(int vaddr)
1031{
1032 //printf("remove hash: %x\n",vaddr);
1033 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1034 if(ht_bin[2]==vaddr) {
1035 ht_bin[2]=ht_bin[3]=-1;
1036 }
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[0]=ht_bin[2];
1039 ht_bin[1]=ht_bin[3];
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042}
1043
1044void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1045{
1046 struct ll_entry *next;
1047 while(*head) {
1048 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1049 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1050 {
1051 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1052 remove_hash((*head)->vaddr);
1053 next=(*head)->next;
1054 free(*head);
1055 *head=next;
1056 }
1057 else
1058 {
1059 head=&((*head)->next);
1060 }
1061 }
1062}
1063
1064// Remove all entries from linked list
1065void ll_clear(struct ll_entry **head)
1066{
1067 struct ll_entry *cur;
1068 struct ll_entry *next;
1069 if(cur=*head) {
1070 *head=0;
1071 while(cur) {
1072 next=cur->next;
1073 free(cur);
1074 cur=next;
1075 }
1076 }
1077}
1078
1079// Dereference the pointers and remove if it matches
1080void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1081{
f76eeef9 1082 u_int old_host_addr=0;
57871462 1083 while(head) {
1084 int ptr=get_pointer(head->addr);
1085 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1086 if(((ptr>>shift)==(addr>>shift)) ||
1087 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1088 {
5088bb70 1089 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1090 u_int host_addr=(u_int)kill_pointer(head->addr);
1091
1092 if((host_addr>>12)!=(old_host_addr>>12)) {
1093 #ifdef __arm__
1094 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1095 #endif
1096 old_host_addr=host_addr;
1097 }
57871462 1098 }
1099 head=head->next;
1100 }
f76eeef9 1101 #ifdef __arm__
1102 if (old_host_addr)
1103 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1104 #endif
57871462 1105}
1106
1107// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1108void invalidate_page(u_int page)
57871462 1109{
57871462 1110 struct ll_entry *head;
1111 struct ll_entry *next;
f76eeef9 1112 u_int old_host_addr=0;
57871462 1113 head=jump_in[page];
1114 jump_in[page]=0;
1115 while(head!=NULL) {
1116 inv_debug("INVALIDATE: %x\n",head->vaddr);
1117 remove_hash(head->vaddr);
1118 next=head->next;
1119 free(head);
1120 head=next;
1121 }
1122 head=jump_out[page];
1123 jump_out[page]=0;
1124 while(head!=NULL) {
1125 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1126 u_int host_addr=(u_int)kill_pointer(head->addr);
1127
1128 if((host_addr>>12)!=(old_host_addr>>12)) {
1129 #ifdef __arm__
1130 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1131 #endif
1132 old_host_addr=host_addr;
1133 }
57871462 1134 next=head->next;
1135 free(head);
1136 head=next;
1137 }
f76eeef9 1138 #ifdef __arm__
1139 if (old_host_addr)
1140 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1141 #endif
57871462 1142}
1143void invalidate_block(u_int block)
1144{
94d23bb9 1145 u_int page=get_page(block<<12);
1146 u_int vpage=get_vpage(block<<12);
57871462 1147 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1148 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1149 u_int first,last;
1150 first=last=page;
1151 struct ll_entry *head;
1152 head=jump_dirty[vpage];
1153 //printf("page=%d vpage=%d\n",page,vpage);
1154 while(head!=NULL) {
1155 u_int start,end;
1156 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1157 get_bounds((int)head->addr,&start,&end);
1158 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1159 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1160 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1161 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1162 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1163 }
1164 }
90ae6d4e 1165#ifndef DISABLE_TLB
57871462 1166 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1167 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1168 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1169 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1170 }
1171 }
90ae6d4e 1172#endif
57871462 1173 }
1174 head=head->next;
1175 }
1176 //printf("first=%d last=%d\n",first,last);
f76eeef9 1177 invalidate_page(page);
57871462 1178 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1179 assert(last<page+5);
1180 // Invalidate the adjacent pages if a block crosses a 4K boundary
1181 while(first<page) {
1182 invalidate_page(first);
1183 first++;
1184 }
1185 for(first=page+1;first<last;first++) {
1186 invalidate_page(first);
1187 }
1188
1189 // Don't trap writes
1190 invalid_code[block]=1;
94d23bb9 1191#ifndef DISABLE_TLB
57871462 1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1200 }
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1202#endif
f76eeef9 1203
57871462 1204 #ifdef USE_MINI_HT
1205 memset(mini_ht,-1,sizeof(mini_ht));
1206 #endif
1207}
1208void invalidate_addr(u_int addr)
1209{
1210 invalidate_block(addr>>12);
1211}
1212void invalidate_all_pages()
1213{
1214 u_int page,n;
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1221 }
1222 #ifdef __arm__
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1224 #endif
1225 #ifdef USE_MINI_HT
1226 memset(mini_ht,-1,sizeof(mini_ht));
1227 #endif
94d23bb9 1228 #ifndef DISABLE_TLB
57871462 1229 // TLB
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1235 }
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1238 }
1239 tlb_hacks();
94d23bb9 1240 #endif
57871462 1241}
1242
1243// Add an entry to jump_out after making a link
1244void add_link(u_int vaddr,void *src)
1245{
94d23bb9 1246 u_int page=get_page(vaddr);
57871462 1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1251}
1252
1253// If a code block was found to be unmodified (bit was set in
1254// restore_candidate) and it remains unmodified (bit is clear
1255// in invalid_code) then move the entries for that 4K page from
1256// the dirty list to the clean list.
1257void clean_blocks(u_int page)
1258{
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1262 while(head!=NULL) {
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1266 u_int start,end;
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1269 u_int i;
1270 u_int inv=0;
1271 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1272 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1275 }
1276 }
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1281 }
4cb76aa4 1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1283 inv=1;
1284 }
1285 if(!inv) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1288 u_int ppage=page;
94d23bb9 1289#ifndef DISABLE_TLB
57871462 1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1291#endif
57871462 1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1297 if(!head->reg32) {
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1300 }
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1303 }
1304 }
1305 }
1306 }
1307 }
1308 }
1309 }
1310 head=head->next;
1311 }
1312}
1313
1314
1315void mov_alloc(struct regstat *current,int i)
1316{
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1322 } else {
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1326 }
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1330}
1331
1332void shiftimm_alloc(struct regstat *current,int i)
1333{
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1337 {
1338 if(rt1[i]) {
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1340 else lt1[i]=rs1[i];
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1344 }
1345 }
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1347 {
1348 if(rt1[i]) {
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1353 }
1354 }
1355 if(opcode2[i]==0x3c) // DSLL32
1356 {
1357 if(rt1[i]) {
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1362 }
1363 }
1364 if(opcode2[i]==0x3e) // DSRL32
1365 {
1366 if(rt1[i]) {
1367 alloc_reg64(current,i,rs1[i]);
1368 if(imm[i]==32) {
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1371 } else {
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1374 }
1375 dirty_reg(current,rt1[i]);
1376 }
1377 }
1378 if(opcode2[i]==0x3f) // DSRA32
1379 {
1380 if(rt1[i]) {
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1385 }
1386 }
1387}
1388
1389void shift_alloc(struct regstat *current,int i)
1390{
1391 if(rt1[i]) {
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1393 {
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1406 }
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1411 }
1412}
1413
1414void alu_alloc(struct regstat *current,int i)
1415{
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1417 if(rt1[i]) {
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1421 }
1422 else {
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1425 }
1426 alloc_reg(current,i,rt1[i]);
1427 }
1428 current->is32|=1LL<<rt1[i];
1429 }
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1431 if(rt1[i]) {
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433 {
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1437 } else {
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1441 }
1442 }
1443 current->is32|=1LL<<rt1[i];
1444 }
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1446 if(rt1[i]) {
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1450 }
1451 else
1452 {
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1455 }
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1458 {
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1461 }
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1466 }
1467 else
1468 {
1469 // Is is really worth it to keep 64-bit values in registers?
1470 #ifdef NATIVE_64BIT
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473 #endif
1474 }
1475 }
1476 current->is32&=~(1LL<<rt1[i]);
1477 } else {
1478 current->is32|=1LL<<rt1[i];
1479 }
1480 }
1481 }
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1483 if(rt1[i]) {
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1489 } else {
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1493 }
1494 }
1495 else {
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1506 }
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1512 }
1513 }
1514 }
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1517 } else if(rs1[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1521 } else if(rs2[i]) {
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1525 } else {
1526 current->is32|=1LL<<rt1[i];
1527 }
1528 }
1529 }
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1534}
1535
1536void imm16_alloc(struct regstat *current,int i)
1537{
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1539 else lt1[i]=rs1[i];
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1547 }
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1550 }
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1556 }
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1563 }
1564 }
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1571 }
1572 else clear_const(current,rt1[i]);
1573 }
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1578 }
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1581 }
1582 else {
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1585 }
1586 dirty_reg(current,rt1[i]);
1587}
1588
1589void load_alloc(struct regstat *current,int i)
1590{
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1595 if(rt1[i]) {
1596 alloc_reg(current,i,rt1[i]);
1597 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1598 {
1599 current->is32&=~(1LL<<rt1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 }
1602 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1603 {
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1606 alloc_all(current,i);
1607 alloc_reg64(current,i,FTEMP);
1608 }
1609 else current->is32|=1LL<<rt1[i];
1610 dirty_reg(current,rt1[i]);
1611 // If using TLB, need a register for pointer to the mapping table
1612 if(using_tlb) alloc_reg(current,i,TLREG);
1613 // LWL/LWR need a temporary register for the old value
1614 if(opcode[i]==0x22||opcode[i]==0x26)
1615 {
1616 alloc_reg(current,i,FTEMP);
1617 alloc_reg_temp(current,i,-1);
1618 }
1619 }
1620 else
1621 {
1622 // Load to r0 (dummy load)
1623 // but we still need a register to calculate the address
1624 alloc_reg_temp(current,i,-1);
1625 }
1626}
1627
1628void store_alloc(struct regstat *current,int i)
1629{
1630 clear_const(current,rs2[i]);
1631 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1632 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1633 alloc_reg(current,i,rs2[i]);
1634 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1635 alloc_reg64(current,i,rs2[i]);
1636 if(rs2[i]) alloc_reg(current,i,FTEMP);
1637 }
1638 // If using TLB, need a register for pointer to the mapping table
1639 if(using_tlb) alloc_reg(current,i,TLREG);
1640 #if defined(HOST_IMM8)
1641 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1642 else alloc_reg(current,i,INVCP);
1643 #endif
b7918751 1644 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1645 alloc_reg(current,i,FTEMP);
1646 }
1647 // We need a temporary register for address generation
1648 alloc_reg_temp(current,i,-1);
1649}
1650
1651void c1ls_alloc(struct regstat *current,int i)
1652{
1653 //clear_const(current,rs1[i]); // FIXME
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,CSREG); // Status
1657 alloc_reg(current,i,FTEMP);
1658 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1659 alloc_reg64(current,i,FTEMP);
1660 }
1661 // If using TLB, need a register for pointer to the mapping table
1662 if(using_tlb) alloc_reg(current,i,TLREG);
1663 #if defined(HOST_IMM8)
1664 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1665 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1666 alloc_reg(current,i,INVCP);
1667 #endif
1668 // We need a temporary register for address generation
1669 alloc_reg_temp(current,i,-1);
1670}
1671
b9b61529 1672void c2ls_alloc(struct regstat *current,int i)
1673{
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,FTEMP);
1677 // If using TLB, need a register for pointer to the mapping table
1678 if(using_tlb) alloc_reg(current,i,TLREG);
1679 #if defined(HOST_IMM8)
1680 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1681 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1682 alloc_reg(current,i,INVCP);
1683 #endif
1684 // We need a temporary register for address generation
1685 alloc_reg_temp(current,i,-1);
1686}
1687
57871462 1688#ifndef multdiv_alloc
1689void multdiv_alloc(struct regstat *current,int i)
1690{
1691 // case 0x18: MULT
1692 // case 0x19: MULTU
1693 // case 0x1A: DIV
1694 // case 0x1B: DIVU
1695 // case 0x1C: DMULT
1696 // case 0x1D: DMULTU
1697 // case 0x1E: DDIV
1698 // case 0x1F: DDIVU
1699 clear_const(current,rs1[i]);
1700 clear_const(current,rs2[i]);
1701 if(rs1[i]&&rs2[i])
1702 {
1703 if((opcode2[i]&4)==0) // 32-bit
1704 {
1705 current->u&=~(1LL<<HIREG);
1706 current->u&=~(1LL<<LOREG);
1707 alloc_reg(current,i,HIREG);
1708 alloc_reg(current,i,LOREG);
1709 alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 current->is32|=1LL<<HIREG;
1712 current->is32|=1LL<<LOREG;
1713 dirty_reg(current,HIREG);
1714 dirty_reg(current,LOREG);
1715 }
1716 else // 64-bit
1717 {
1718 current->u&=~(1LL<<HIREG);
1719 current->u&=~(1LL<<LOREG);
1720 current->uu&=~(1LL<<HIREG);
1721 current->uu&=~(1LL<<LOREG);
1722 alloc_reg64(current,i,HIREG);
1723 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1724 alloc_reg64(current,i,rs1[i]);
1725 alloc_reg64(current,i,rs2[i]);
1726 alloc_all(current,i);
1727 current->is32&=~(1LL<<HIREG);
1728 current->is32&=~(1LL<<LOREG);
1729 dirty_reg(current,HIREG);
1730 dirty_reg(current,LOREG);
1731 }
1732 }
1733 else
1734 {
1735 // Multiply by zero is zero.
1736 // MIPS does not have a divide by zero exception.
1737 // The result is undefined, we return zero.
1738 alloc_reg(current,i,HIREG);
1739 alloc_reg(current,i,LOREG);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1744 }
1745}
1746#endif
1747
1748void cop0_alloc(struct regstat *current,int i)
1749{
1750 if(opcode2[i]==0) // MFC0
1751 {
1752 if(rt1[i]) {
1753 clear_const(current,rt1[i]);
1754 alloc_all(current,i);
1755 alloc_reg(current,i,rt1[i]);
1756 current->is32|=1LL<<rt1[i];
1757 dirty_reg(current,rt1[i]);
1758 }
1759 }
1760 else if(opcode2[i]==4) // MTC0
1761 {
1762 if(rs1[i]){
1763 clear_const(current,rs1[i]);
1764 alloc_reg(current,i,rs1[i]);
1765 alloc_all(current,i);
1766 }
1767 else {
1768 alloc_all(current,i); // FIXME: Keep r0
1769 current->u&=~1LL;
1770 alloc_reg(current,i,0);
1771 }
1772 }
1773 else
1774 {
1775 // TLBR/TLBWI/TLBWR/TLBP/ERET
1776 assert(opcode2[i]==0x10);
1777 alloc_all(current,i);
1778 }
1779}
1780
1781void cop1_alloc(struct regstat *current,int i)
1782{
1783 alloc_reg(current,i,CSREG); // Load status
1784 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1785 {
7de557a6 1786 if(rt1[i]){
1787 clear_const(current,rt1[i]);
1788 if(opcode2[i]==1) {
1789 alloc_reg64(current,i,rt1[i]); // DMFC1
1790 current->is32&=~(1LL<<rt1[i]);
1791 }else{
1792 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1793 current->is32|=1LL<<rt1[i];
1794 }
1795 dirty_reg(current,rt1[i]);
57871462 1796 }
57871462 1797 alloc_reg_temp(current,i,-1);
1798 }
1799 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1800 {
1801 if(rs1[i]){
1802 clear_const(current,rs1[i]);
1803 if(opcode2[i]==5)
1804 alloc_reg64(current,i,rs1[i]); // DMTC1
1805 else
1806 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1807 alloc_reg_temp(current,i,-1);
1808 }
1809 else {
1810 current->u&=~1LL;
1811 alloc_reg(current,i,0);
1812 alloc_reg_temp(current,i,-1);
1813 }
1814 }
1815}
1816void fconv_alloc(struct regstat *current,int i)
1817{
1818 alloc_reg(current,i,CSREG); // Load status
1819 alloc_reg_temp(current,i,-1);
1820}
1821void float_alloc(struct regstat *current,int i)
1822{
1823 alloc_reg(current,i,CSREG); // Load status
1824 alloc_reg_temp(current,i,-1);
1825}
b9b61529 1826void c2op_alloc(struct regstat *current,int i)
1827{
1828 alloc_reg_temp(current,i,-1);
1829}
57871462 1830void fcomp_alloc(struct regstat *current,int i)
1831{
1832 alloc_reg(current,i,CSREG); // Load status
1833 alloc_reg(current,i,FSREG); // Load flags
1834 dirty_reg(current,FSREG); // Flag will be modified
1835 alloc_reg_temp(current,i,-1);
1836}
1837
1838void syscall_alloc(struct regstat *current,int i)
1839{
1840 alloc_cc(current,i);
1841 dirty_reg(current,CCREG);
1842 alloc_all(current,i);
1843 current->isconst=0;
1844}
1845
1846void delayslot_alloc(struct regstat *current,int i)
1847{
1848 switch(itype[i]) {
1849 case UJUMP:
1850 case CJUMP:
1851 case SJUMP:
1852 case RJUMP:
1853 case FJUMP:
1854 case SYSCALL:
7139f3c8 1855 case HLECALL:
57871462 1856 case SPAN:
1857 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1858 printf("Disabled speculative precompilation\n");
1859 stop_after_jal=1;
1860 break;
1861 case IMM16:
1862 imm16_alloc(current,i);
1863 break;
1864 case LOAD:
1865 case LOADLR:
1866 load_alloc(current,i);
1867 break;
1868 case STORE:
1869 case STORELR:
1870 store_alloc(current,i);
1871 break;
1872 case ALU:
1873 alu_alloc(current,i);
1874 break;
1875 case SHIFT:
1876 shift_alloc(current,i);
1877 break;
1878 case MULTDIV:
1879 multdiv_alloc(current,i);
1880 break;
1881 case SHIFTIMM:
1882 shiftimm_alloc(current,i);
1883 break;
1884 case MOV:
1885 mov_alloc(current,i);
1886 break;
1887 case COP0:
1888 cop0_alloc(current,i);
1889 break;
1890 case COP1:
b9b61529 1891 case COP2:
57871462 1892 cop1_alloc(current,i);
1893 break;
1894 case C1LS:
1895 c1ls_alloc(current,i);
1896 break;
b9b61529 1897 case C2LS:
1898 c2ls_alloc(current,i);
1899 break;
57871462 1900 case FCONV:
1901 fconv_alloc(current,i);
1902 break;
1903 case FLOAT:
1904 float_alloc(current,i);
1905 break;
1906 case FCOMP:
1907 fcomp_alloc(current,i);
1908 break;
b9b61529 1909 case C2OP:
1910 c2op_alloc(current,i);
1911 break;
57871462 1912 }
1913}
1914
1915// Special case where a branch and delay slot span two pages in virtual memory
1916static void pagespan_alloc(struct regstat *current,int i)
1917{
1918 current->isconst=0;
1919 current->wasconst=0;
1920 regs[i].wasconst=0;
1921 alloc_all(current,i);
1922 alloc_cc(current,i);
1923 dirty_reg(current,CCREG);
1924 if(opcode[i]==3) // JAL
1925 {
1926 alloc_reg(current,i,31);
1927 dirty_reg(current,31);
1928 }
1929 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1930 {
1931 alloc_reg(current,i,rs1[i]);
5067f341 1932 if (rt1[i]!=0) {
1933 alloc_reg(current,i,rt1[i]);
1934 dirty_reg(current,rt1[i]);
57871462 1935 }
1936 }
1937 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1938 {
1939 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1940 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1941 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1942 {
1943 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1944 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1945 }
1946 }
1947 else
1948 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1949 {
1950 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1951 if(!((current->is32>>rs1[i])&1))
1952 {
1953 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1954 }
1955 }
1956 else
1957 if(opcode[i]==0x11) // BC1
1958 {
1959 alloc_reg(current,i,FSREG);
1960 alloc_reg(current,i,CSREG);
1961 }
1962 //else ...
1963}
1964
1965add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1966{
1967 stubs[stubcount][0]=type;
1968 stubs[stubcount][1]=addr;
1969 stubs[stubcount][2]=retaddr;
1970 stubs[stubcount][3]=a;
1971 stubs[stubcount][4]=b;
1972 stubs[stubcount][5]=c;
1973 stubs[stubcount][6]=d;
1974 stubs[stubcount][7]=e;
1975 stubcount++;
1976}
1977
1978// Write out a single register
1979void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1980{
1981 int hr;
1982 for(hr=0;hr<HOST_REGS;hr++) {
1983 if(hr!=EXCLUDE_REG) {
1984 if((regmap[hr]&63)==r) {
1985 if((dirty>>hr)&1) {
1986 if(regmap[hr]<64) {
1987 emit_storereg(r,hr);
24385cae 1988#ifndef FORCE32
57871462 1989 if((is32>>regmap[hr])&1) {
1990 emit_sarimm(hr,31,hr);
1991 emit_storereg(r|64,hr);
1992 }
24385cae 1993#endif
57871462 1994 }else{
1995 emit_storereg(r|64,hr);
1996 }
1997 }
1998 }
1999 }
2000 }
2001}
2002
2003int mchecksum()
2004{
2005 //if(!tracedebug) return 0;
2006 int i;
2007 int sum=0;
2008 for(i=0;i<2097152;i++) {
2009 unsigned int temp=sum;
2010 sum<<=1;
2011 sum|=(~temp)>>31;
2012 sum^=((u_int *)rdram)[i];
2013 }
2014 return sum;
2015}
2016int rchecksum()
2017{
2018 int i;
2019 int sum=0;
2020 for(i=0;i<64;i++)
2021 sum^=((u_int *)reg)[i];
2022 return sum;
2023}
57871462 2024void rlist()
2025{
2026 int i;
2027 printf("TRACE: ");
2028 for(i=0;i<32;i++)
2029 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2030 printf("\n");
3d624f89 2031#ifndef DISABLE_COP1
57871462 2032 printf("TRACE: ");
2033 for(i=0;i<32;i++)
2034 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2035 printf("\n");
3d624f89 2036#endif
57871462 2037}
2038
2039void enabletrace()
2040{
2041 tracedebug=1;
2042}
2043
2044void memdebug(int i)
2045{
2046 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2047 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2048 //rlist();
2049 //if(tracedebug) {
2050 //if(Count>=-2084597794) {
2051 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2052 //if(0) {
2053 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2054 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2055 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2056 rlist();
2057 #ifdef __i386__
2058 printf("TRACE: %x\n",(&i)[-1]);
2059 #endif
2060 #ifdef __arm__
2061 int j;
2062 printf("TRACE: %x \n",(&j)[10]);
2063 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2064 #endif
2065 //fflush(stdout);
2066 }
2067 //printf("TRACE: %x\n",(&i)[-1]);
2068}
2069
2070void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2071{
2072 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2073}
2074
2075void alu_assemble(int i,struct regstat *i_regs)
2076{
2077 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2078 if(rt1[i]) {
2079 signed char s1,s2,t;
2080 t=get_reg(i_regs->regmap,rt1[i]);
2081 if(t>=0) {
2082 s1=get_reg(i_regs->regmap,rs1[i]);
2083 s2=get_reg(i_regs->regmap,rs2[i]);
2084 if(rs1[i]&&rs2[i]) {
2085 assert(s1>=0);
2086 assert(s2>=0);
2087 if(opcode2[i]&2) emit_sub(s1,s2,t);
2088 else emit_add(s1,s2,t);
2089 }
2090 else if(rs1[i]) {
2091 if(s1>=0) emit_mov(s1,t);
2092 else emit_loadreg(rs1[i],t);
2093 }
2094 else if(rs2[i]) {
2095 if(s2>=0) {
2096 if(opcode2[i]&2) emit_neg(s2,t);
2097 else emit_mov(s2,t);
2098 }
2099 else {
2100 emit_loadreg(rs2[i],t);
2101 if(opcode2[i]&2) emit_neg(t,t);
2102 }
2103 }
2104 else emit_zeroreg(t);
2105 }
2106 }
2107 }
2108 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2109 if(rt1[i]) {
2110 signed char s1l,s2l,s1h,s2h,tl,th;
2111 tl=get_reg(i_regs->regmap,rt1[i]);
2112 th=get_reg(i_regs->regmap,rt1[i]|64);
2113 if(tl>=0) {
2114 s1l=get_reg(i_regs->regmap,rs1[i]);
2115 s2l=get_reg(i_regs->regmap,rs2[i]);
2116 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2117 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2118 if(rs1[i]&&rs2[i]) {
2119 assert(s1l>=0);
2120 assert(s2l>=0);
2121 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2122 else emit_adds(s1l,s2l,tl);
2123 if(th>=0) {
2124 #ifdef INVERTED_CARRY
2125 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2126 #else
2127 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2128 #endif
2129 else emit_add(s1h,s2h,th);
2130 }
2131 }
2132 else if(rs1[i]) {
2133 if(s1l>=0) emit_mov(s1l,tl);
2134 else emit_loadreg(rs1[i],tl);
2135 if(th>=0) {
2136 if(s1h>=0) emit_mov(s1h,th);
2137 else emit_loadreg(rs1[i]|64,th);
2138 }
2139 }
2140 else if(rs2[i]) {
2141 if(s2l>=0) {
2142 if(opcode2[i]&2) emit_negs(s2l,tl);
2143 else emit_mov(s2l,tl);
2144 }
2145 else {
2146 emit_loadreg(rs2[i],tl);
2147 if(opcode2[i]&2) emit_negs(tl,tl);
2148 }
2149 if(th>=0) {
2150 #ifdef INVERTED_CARRY
2151 if(s2h>=0) emit_mov(s2h,th);
2152 else emit_loadreg(rs2[i]|64,th);
2153 if(opcode2[i]&2) {
2154 emit_adcimm(-1,th); // x86 has inverted carry flag
2155 emit_not(th,th);
2156 }
2157 #else
2158 if(opcode2[i]&2) {
2159 if(s2h>=0) emit_rscimm(s2h,0,th);
2160 else {
2161 emit_loadreg(rs2[i]|64,th);
2162 emit_rscimm(th,0,th);
2163 }
2164 }else{
2165 if(s2h>=0) emit_mov(s2h,th);
2166 else emit_loadreg(rs2[i]|64,th);
2167 }
2168 #endif
2169 }
2170 }
2171 else {
2172 emit_zeroreg(tl);
2173 if(th>=0) emit_zeroreg(th);
2174 }
2175 }
2176 }
2177 }
2178 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2179 if(rt1[i]) {
2180 signed char s1l,s1h,s2l,s2h,t;
2181 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2182 {
2183 t=get_reg(i_regs->regmap,rt1[i]);
2184 //assert(t>=0);
2185 if(t>=0) {
2186 s1l=get_reg(i_regs->regmap,rs1[i]);
2187 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2188 s2l=get_reg(i_regs->regmap,rs2[i]);
2189 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2190 if(rs2[i]==0) // rx<r0
2191 {
2192 assert(s1h>=0);
2193 if(opcode2[i]==0x2a) // SLT
2194 emit_shrimm(s1h,31,t);
2195 else // SLTU (unsigned can not be less than zero)
2196 emit_zeroreg(t);
2197 }
2198 else if(rs1[i]==0) // r0<rx
2199 {
2200 assert(s2h>=0);
2201 if(opcode2[i]==0x2a) // SLT
2202 emit_set_gz64_32(s2h,s2l,t);
2203 else // SLTU (set if not zero)
2204 emit_set_nz64_32(s2h,s2l,t);
2205 }
2206 else {
2207 assert(s1l>=0);assert(s1h>=0);
2208 assert(s2l>=0);assert(s2h>=0);
2209 if(opcode2[i]==0x2a) // SLT
2210 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2211 else // SLTU
2212 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2213 }
2214 }
2215 } else {
2216 t=get_reg(i_regs->regmap,rt1[i]);
2217 //assert(t>=0);
2218 if(t>=0) {
2219 s1l=get_reg(i_regs->regmap,rs1[i]);
2220 s2l=get_reg(i_regs->regmap,rs2[i]);
2221 if(rs2[i]==0) // rx<r0
2222 {
2223 assert(s1l>=0);
2224 if(opcode2[i]==0x2a) // SLT
2225 emit_shrimm(s1l,31,t);
2226 else // SLTU (unsigned can not be less than zero)
2227 emit_zeroreg(t);
2228 }
2229 else if(rs1[i]==0) // r0<rx
2230 {
2231 assert(s2l>=0);
2232 if(opcode2[i]==0x2a) // SLT
2233 emit_set_gz32(s2l,t);
2234 else // SLTU (set if not zero)
2235 emit_set_nz32(s2l,t);
2236 }
2237 else{
2238 assert(s1l>=0);assert(s2l>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less32(s1l,s2l,t);
2241 else // SLTU
2242 emit_set_if_carry32(s1l,s2l,t);
2243 }
2244 }
2245 }
2246 }
2247 }
2248 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2249 if(rt1[i]) {
2250 signed char s1l,s1h,s2l,s2h,th,tl;
2251 tl=get_reg(i_regs->regmap,rt1[i]);
2252 th=get_reg(i_regs->regmap,rt1[i]|64);
2253 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2254 {
2255 assert(tl>=0);
2256 if(tl>=0) {
2257 s1l=get_reg(i_regs->regmap,rs1[i]);
2258 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2259 s2l=get_reg(i_regs->regmap,rs2[i]);
2260 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2261 if(rs1[i]&&rs2[i]) {
2262 assert(s1l>=0);assert(s1h>=0);
2263 assert(s2l>=0);assert(s2h>=0);
2264 if(opcode2[i]==0x24) { // AND
2265 emit_and(s1l,s2l,tl);
2266 emit_and(s1h,s2h,th);
2267 } else
2268 if(opcode2[i]==0x25) { // OR
2269 emit_or(s1l,s2l,tl);
2270 emit_or(s1h,s2h,th);
2271 } else
2272 if(opcode2[i]==0x26) { // XOR
2273 emit_xor(s1l,s2l,tl);
2274 emit_xor(s1h,s2h,th);
2275 } else
2276 if(opcode2[i]==0x27) { // NOR
2277 emit_or(s1l,s2l,tl);
2278 emit_or(s1h,s2h,th);
2279 emit_not(tl,tl);
2280 emit_not(th,th);
2281 }
2282 }
2283 else
2284 {
2285 if(opcode2[i]==0x24) { // AND
2286 emit_zeroreg(tl);
2287 emit_zeroreg(th);
2288 } else
2289 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2290 if(rs1[i]){
2291 if(s1l>=0) emit_mov(s1l,tl);
2292 else emit_loadreg(rs1[i],tl);
2293 if(s1h>=0) emit_mov(s1h,th);
2294 else emit_loadreg(rs1[i]|64,th);
2295 }
2296 else
2297 if(rs2[i]){
2298 if(s2l>=0) emit_mov(s2l,tl);
2299 else emit_loadreg(rs2[i],tl);
2300 if(s2h>=0) emit_mov(s2h,th);
2301 else emit_loadreg(rs2[i]|64,th);
2302 }
2303 else{
2304 emit_zeroreg(tl);
2305 emit_zeroreg(th);
2306 }
2307 } else
2308 if(opcode2[i]==0x27) { // NOR
2309 if(rs1[i]){
2310 if(s1l>=0) emit_not(s1l,tl);
2311 else{
2312 emit_loadreg(rs1[i],tl);
2313 emit_not(tl,tl);
2314 }
2315 if(s1h>=0) emit_not(s1h,th);
2316 else{
2317 emit_loadreg(rs1[i]|64,th);
2318 emit_not(th,th);
2319 }
2320 }
2321 else
2322 if(rs2[i]){
2323 if(s2l>=0) emit_not(s2l,tl);
2324 else{
2325 emit_loadreg(rs2[i],tl);
2326 emit_not(tl,tl);
2327 }
2328 if(s2h>=0) emit_not(s2h,th);
2329 else{
2330 emit_loadreg(rs2[i]|64,th);
2331 emit_not(th,th);
2332 }
2333 }
2334 else {
2335 emit_movimm(-1,tl);
2336 emit_movimm(-1,th);
2337 }
2338 }
2339 }
2340 }
2341 }
2342 else
2343 {
2344 // 32 bit
2345 if(tl>=0) {
2346 s1l=get_reg(i_regs->regmap,rs1[i]);
2347 s2l=get_reg(i_regs->regmap,rs2[i]);
2348 if(rs1[i]&&rs2[i]) {
2349 assert(s1l>=0);
2350 assert(s2l>=0);
2351 if(opcode2[i]==0x24) { // AND
2352 emit_and(s1l,s2l,tl);
2353 } else
2354 if(opcode2[i]==0x25) { // OR
2355 emit_or(s1l,s2l,tl);
2356 } else
2357 if(opcode2[i]==0x26) { // XOR
2358 emit_xor(s1l,s2l,tl);
2359 } else
2360 if(opcode2[i]==0x27) { // NOR
2361 emit_or(s1l,s2l,tl);
2362 emit_not(tl,tl);
2363 }
2364 }
2365 else
2366 {
2367 if(opcode2[i]==0x24) { // AND
2368 emit_zeroreg(tl);
2369 } else
2370 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2371 if(rs1[i]){
2372 if(s1l>=0) emit_mov(s1l,tl);
2373 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2374 }
2375 else
2376 if(rs2[i]){
2377 if(s2l>=0) emit_mov(s2l,tl);
2378 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2379 }
2380 else emit_zeroreg(tl);
2381 } else
2382 if(opcode2[i]==0x27) { // NOR
2383 if(rs1[i]){
2384 if(s1l>=0) emit_not(s1l,tl);
2385 else {
2386 emit_loadreg(rs1[i],tl);
2387 emit_not(tl,tl);
2388 }
2389 }
2390 else
2391 if(rs2[i]){
2392 if(s2l>=0) emit_not(s2l,tl);
2393 else {
2394 emit_loadreg(rs2[i],tl);
2395 emit_not(tl,tl);
2396 }
2397 }
2398 else emit_movimm(-1,tl);
2399 }
2400 }
2401 }
2402 }
2403 }
2404 }
2405}
2406
2407void imm16_assemble(int i,struct regstat *i_regs)
2408{
2409 if (opcode[i]==0x0f) { // LUI
2410 if(rt1[i]) {
2411 signed char t;
2412 t=get_reg(i_regs->regmap,rt1[i]);
2413 //assert(t>=0);
2414 if(t>=0) {
2415 if(!((i_regs->isconst>>t)&1))
2416 emit_movimm(imm[i]<<16,t);
2417 }
2418 }
2419 }
2420 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2421 if(rt1[i]) {
2422 signed char s,t;
2423 t=get_reg(i_regs->regmap,rt1[i]);
2424 s=get_reg(i_regs->regmap,rs1[i]);
2425 if(rs1[i]) {
2426 //assert(t>=0);
2427 //assert(s>=0);
2428 if(t>=0) {
2429 if(!((i_regs->isconst>>t)&1)) {
2430 if(s<0) {
2431 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2432 emit_addimm(t,imm[i],t);
2433 }else{
2434 if(!((i_regs->wasconst>>s)&1))
2435 emit_addimm(s,imm[i],t);
2436 else
2437 emit_movimm(constmap[i][s]+imm[i],t);
2438 }
2439 }
2440 }
2441 } else {
2442 if(t>=0) {
2443 if(!((i_regs->isconst>>t)&1))
2444 emit_movimm(imm[i],t);
2445 }
2446 }
2447 }
2448 }
2449 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2450 if(rt1[i]) {
2451 signed char sh,sl,th,tl;
2452 th=get_reg(i_regs->regmap,rt1[i]|64);
2453 tl=get_reg(i_regs->regmap,rt1[i]);
2454 sh=get_reg(i_regs->regmap,rs1[i]|64);
2455 sl=get_reg(i_regs->regmap,rs1[i]);
2456 if(tl>=0) {
2457 if(rs1[i]) {
2458 assert(sh>=0);
2459 assert(sl>=0);
2460 if(th>=0) {
2461 emit_addimm64_32(sh,sl,imm[i],th,tl);
2462 }
2463 else {
2464 emit_addimm(sl,imm[i],tl);
2465 }
2466 } else {
2467 emit_movimm(imm[i],tl);
2468 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2469 }
2470 }
2471 }
2472 }
2473 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2474 if(rt1[i]) {
2475 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2476 signed char sh,sl,t;
2477 t=get_reg(i_regs->regmap,rt1[i]);
2478 sh=get_reg(i_regs->regmap,rs1[i]|64);
2479 sl=get_reg(i_regs->regmap,rs1[i]);
2480 //assert(t>=0);
2481 if(t>=0) {
2482 if(rs1[i]>0) {
2483 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2484 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2485 if(opcode[i]==0x0a) { // SLTI
2486 if(sl<0) {
2487 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2488 emit_slti32(t,imm[i],t);
2489 }else{
2490 emit_slti32(sl,imm[i],t);
2491 }
2492 }
2493 else { // SLTIU
2494 if(sl<0) {
2495 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2496 emit_sltiu32(t,imm[i],t);
2497 }else{
2498 emit_sltiu32(sl,imm[i],t);
2499 }
2500 }
2501 }else{ // 64-bit
2502 assert(sl>=0);
2503 if(opcode[i]==0x0a) // SLTI
2504 emit_slti64_32(sh,sl,imm[i],t);
2505 else // SLTIU
2506 emit_sltiu64_32(sh,sl,imm[i],t);
2507 }
2508 }else{
2509 // SLTI(U) with r0 is just stupid,
2510 // nonetheless examples can be found
2511 if(opcode[i]==0x0a) // SLTI
2512 if(0<imm[i]) emit_movimm(1,t);
2513 else emit_zeroreg(t);
2514 else // SLTIU
2515 {
2516 if(imm[i]) emit_movimm(1,t);
2517 else emit_zeroreg(t);
2518 }
2519 }
2520 }
2521 }
2522 }
2523 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2524 if(rt1[i]) {
2525 signed char sh,sl,th,tl;
2526 th=get_reg(i_regs->regmap,rt1[i]|64);
2527 tl=get_reg(i_regs->regmap,rt1[i]);
2528 sh=get_reg(i_regs->regmap,rs1[i]|64);
2529 sl=get_reg(i_regs->regmap,rs1[i]);
2530 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2531 if(opcode[i]==0x0c) //ANDI
2532 {
2533 if(rs1[i]) {
2534 if(sl<0) {
2535 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2536 emit_andimm(tl,imm[i],tl);
2537 }else{
2538 if(!((i_regs->wasconst>>sl)&1))
2539 emit_andimm(sl,imm[i],tl);
2540 else
2541 emit_movimm(constmap[i][sl]&imm[i],tl);
2542 }
2543 }
2544 else
2545 emit_zeroreg(tl);
2546 if(th>=0) emit_zeroreg(th);
2547 }
2548 else
2549 {
2550 if(rs1[i]) {
2551 if(sl<0) {
2552 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2553 }
2554 if(th>=0) {
2555 if(sh<0) {
2556 emit_loadreg(rs1[i]|64,th);
2557 }else{
2558 emit_mov(sh,th);
2559 }
2560 }
2561 if(opcode[i]==0x0d) //ORI
2562 if(sl<0) {
2563 emit_orimm(tl,imm[i],tl);
2564 }else{
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_orimm(sl,imm[i],tl);
2567 else
2568 emit_movimm(constmap[i][sl]|imm[i],tl);
2569 }
2570 if(opcode[i]==0x0e) //XORI
2571 if(sl<0) {
2572 emit_xorimm(tl,imm[i],tl);
2573 }else{
2574 if(!((i_regs->wasconst>>sl)&1))
2575 emit_xorimm(sl,imm[i],tl);
2576 else
2577 emit_movimm(constmap[i][sl]^imm[i],tl);
2578 }
2579 }
2580 else {
2581 emit_movimm(imm[i],tl);
2582 if(th>=0) emit_zeroreg(th);
2583 }
2584 }
2585 }
2586 }
2587 }
2588}
2589
2590void shiftimm_assemble(int i,struct regstat *i_regs)
2591{
2592 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2593 {
2594 if(rt1[i]) {
2595 signed char s,t;
2596 t=get_reg(i_regs->regmap,rt1[i]);
2597 s=get_reg(i_regs->regmap,rs1[i]);
2598 //assert(t>=0);
2599 if(t>=0){
2600 if(rs1[i]==0)
2601 {
2602 emit_zeroreg(t);
2603 }
2604 else
2605 {
2606 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2607 if(imm[i]) {
2608 if(opcode2[i]==0) // SLL
2609 {
2610 emit_shlimm(s<0?t:s,imm[i],t);
2611 }
2612 if(opcode2[i]==2) // SRL
2613 {
2614 emit_shrimm(s<0?t:s,imm[i],t);
2615 }
2616 if(opcode2[i]==3) // SRA
2617 {
2618 emit_sarimm(s<0?t:s,imm[i],t);
2619 }
2620 }else{
2621 // Shift by zero
2622 if(s>=0 && s!=t) emit_mov(s,t);
2623 }
2624 }
2625 }
2626 //emit_storereg(rt1[i],t); //DEBUG
2627 }
2628 }
2629 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2630 {
2631 if(rt1[i]) {
2632 signed char sh,sl,th,tl;
2633 th=get_reg(i_regs->regmap,rt1[i]|64);
2634 tl=get_reg(i_regs->regmap,rt1[i]);
2635 sh=get_reg(i_regs->regmap,rs1[i]|64);
2636 sl=get_reg(i_regs->regmap,rs1[i]);
2637 if(tl>=0) {
2638 if(rs1[i]==0)
2639 {
2640 emit_zeroreg(tl);
2641 if(th>=0) emit_zeroreg(th);
2642 }
2643 else
2644 {
2645 assert(sl>=0);
2646 assert(sh>=0);
2647 if(imm[i]) {
2648 if(opcode2[i]==0x38) // DSLL
2649 {
2650 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2651 emit_shlimm(sl,imm[i],tl);
2652 }
2653 if(opcode2[i]==0x3a) // DSRL
2654 {
2655 emit_shrdimm(sl,sh,imm[i],tl);
2656 if(th>=0) emit_shrimm(sh,imm[i],th);
2657 }
2658 if(opcode2[i]==0x3b) // DSRA
2659 {
2660 emit_shrdimm(sl,sh,imm[i],tl);
2661 if(th>=0) emit_sarimm(sh,imm[i],th);
2662 }
2663 }else{
2664 // Shift by zero
2665 if(sl!=tl) emit_mov(sl,tl);
2666 if(th>=0&&sh!=th) emit_mov(sh,th);
2667 }
2668 }
2669 }
2670 }
2671 }
2672 if(opcode2[i]==0x3c) // DSLL32
2673 {
2674 if(rt1[i]) {
2675 signed char sl,tl,th;
2676 tl=get_reg(i_regs->regmap,rt1[i]);
2677 th=get_reg(i_regs->regmap,rt1[i]|64);
2678 sl=get_reg(i_regs->regmap,rs1[i]);
2679 if(th>=0||tl>=0){
2680 assert(tl>=0);
2681 assert(th>=0);
2682 assert(sl>=0);
2683 emit_mov(sl,th);
2684 emit_zeroreg(tl);
2685 if(imm[i]>32)
2686 {
2687 emit_shlimm(th,imm[i]&31,th);
2688 }
2689 }
2690 }
2691 }
2692 if(opcode2[i]==0x3e) // DSRL32
2693 {
2694 if(rt1[i]) {
2695 signed char sh,tl,th;
2696 tl=get_reg(i_regs->regmap,rt1[i]);
2697 th=get_reg(i_regs->regmap,rt1[i]|64);
2698 sh=get_reg(i_regs->regmap,rs1[i]|64);
2699 if(tl>=0){
2700 assert(sh>=0);
2701 emit_mov(sh,tl);
2702 if(th>=0) emit_zeroreg(th);
2703 if(imm[i]>32)
2704 {
2705 emit_shrimm(tl,imm[i]&31,tl);
2706 }
2707 }
2708 }
2709 }
2710 if(opcode2[i]==0x3f) // DSRA32
2711 {
2712 if(rt1[i]) {
2713 signed char sh,tl;
2714 tl=get_reg(i_regs->regmap,rt1[i]);
2715 sh=get_reg(i_regs->regmap,rs1[i]|64);
2716 if(tl>=0){
2717 assert(sh>=0);
2718 emit_mov(sh,tl);
2719 if(imm[i]>32)
2720 {
2721 emit_sarimm(tl,imm[i]&31,tl);
2722 }
2723 }
2724 }
2725 }
2726}
2727
2728#ifndef shift_assemble
2729void shift_assemble(int i,struct regstat *i_regs)
2730{
2731 printf("Need shift_assemble for this architecture.\n");
2732 exit(1);
2733}
2734#endif
2735
2736void load_assemble(int i,struct regstat *i_regs)
2737{
2738 int s,th,tl,addr,map=-1;
2739 int offset;
2740 int jaddr=0;
5bf843dc 2741 int memtarget=0,c=0;
57871462 2742 u_int hr,reglist=0;
2743 th=get_reg(i_regs->regmap,rt1[i]|64);
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 s=get_reg(i_regs->regmap,rs1[i]);
2746 offset=imm[i];
2747 for(hr=0;hr<HOST_REGS;hr++) {
2748 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2749 }
2750 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2751 if(s>=0) {
2752 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2753 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2754 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2755 }
57871462 2756 //printf("load_assemble: c=%d\n",c);
2757 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2758 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2759#ifdef PCSX
f18c0f46 2760 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2761 ||rt1[i]==0) {
5bf843dc 2762 // could be FIFO, must perform the read
f18c0f46 2763 // ||dummy read
5bf843dc 2764 assem_debug("(forced read)\n");
2765 tl=get_reg(i_regs->regmap,-1);
2766 assert(tl>=0);
5bf843dc 2767 }
f18c0f46 2768#endif
5bf843dc 2769 if(offset||s<0||c) addr=tl;
2770 else addr=s;
57871462 2771 if(tl>=0) {
2772 //assert(tl>=0);
2773 //assert(rt1[i]);
2774 reglist&=~(1<<tl);
2775 if(th>=0) reglist&=~(1<<th);
2776 if(!using_tlb) {
2777 if(!c) {
2778//#define R29_HACK 1
2779 #ifdef R29_HACK
2780 // Strmnnrmn's speed hack
4cb76aa4 2781 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 2782 #endif
2783 {
4cb76aa4 2784 emit_cmpimm(addr,RAM_SIZE);
57871462 2785 jaddr=(int)out;
2786 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2787 // Hint to branch predictor that the branch is unlikely to be taken
2788 if(rs1[i]>=28)
2789 emit_jno_unlikely(0);
2790 else
2791 #endif
2792 emit_jno(0);
2793 }
2794 }
2795 }else{ // using tlb
2796 int x=0;
2797 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2798 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2799 map=get_reg(i_regs->regmap,TLREG);
2800 assert(map>=0);
2801 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2802 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2803 }
2804 if (opcode[i]==0x20) { // LB
2805 if(!c||memtarget) {
2806 #ifdef HOST_IMM_ADDR32
2807 if(c)
2808 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2809 else
2810 #endif
2811 {
2812 //emit_xorimm(addr,3,tl);
2813 //gen_tlb_addr_r(tl,map);
2814 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2815 int x=0;
2002a1db 2816#ifdef BIG_ENDIAN_MIPS
57871462 2817 if(!c) emit_xorimm(addr,3,tl);
2818 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2819#else
2820 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2821 else if (tl!=addr) emit_mov(addr,tl);
2822#endif
57871462 2823 emit_movsbl_indexed_tlb(x,tl,map,tl);
2824 }
2825 if(jaddr)
2826 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2827 }
2828 else
2829 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830 }
2831 if (opcode[i]==0x21) { // LH
2832 if(!c||memtarget) {
2833 #ifdef HOST_IMM_ADDR32
2834 if(c)
2835 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2836 else
2837 #endif
2838 {
2839 int x=0;
2002a1db 2840#ifdef BIG_ENDIAN_MIPS
57871462 2841 if(!c) emit_xorimm(addr,2,tl);
2842 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2843#else
2844 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2845 else if (tl!=addr) emit_mov(addr,tl);
2846#endif
57871462 2847 //#ifdef
2848 //emit_movswl_indexed_tlb(x,tl,map,tl);
2849 //else
2850 if(map>=0) {
2851 gen_tlb_addr_r(tl,map);
2852 emit_movswl_indexed(x,tl,tl);
2853 }else
2854 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2855 }
2856 if(jaddr)
2857 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2858 }
2859 else
2860 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2861 }
2862 if (opcode[i]==0x23) { // LW
2863 if(!c||memtarget) {
2864 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2865 #ifdef HOST_IMM_ADDR32
2866 if(c)
2867 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2868 else
2869 #endif
2870 emit_readword_indexed_tlb(0,addr,map,tl);
2871 if(jaddr)
2872 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2873 }
2874 else
2875 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2876 }
2877 if (opcode[i]==0x24) { // LBU
2878 if(!c||memtarget) {
2879 #ifdef HOST_IMM_ADDR32
2880 if(c)
2881 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2882 else
2883 #endif
2884 {
2885 //emit_xorimm(addr,3,tl);
2886 //gen_tlb_addr_r(tl,map);
2887 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2888 int x=0;
2002a1db 2889#ifdef BIG_ENDIAN_MIPS
57871462 2890 if(!c) emit_xorimm(addr,3,tl);
2891 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2892#else
2893 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2894 else if (tl!=addr) emit_mov(addr,tl);
2895#endif
57871462 2896 emit_movzbl_indexed_tlb(x,tl,map,tl);
2897 }
2898 if(jaddr)
2899 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2900 }
2901 else
2902 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903 }
2904 if (opcode[i]==0x25) { // LHU
2905 if(!c||memtarget) {
2906 #ifdef HOST_IMM_ADDR32
2907 if(c)
2908 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2909 else
2910 #endif
2911 {
2912 int x=0;
2002a1db 2913#ifdef BIG_ENDIAN_MIPS
57871462 2914 if(!c) emit_xorimm(addr,2,tl);
2915 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2916#else
2917 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2918 else if (tl!=addr) emit_mov(addr,tl);
2919#endif
57871462 2920 //#ifdef
2921 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2922 //#else
2923 if(map>=0) {
2924 gen_tlb_addr_r(tl,map);
2925 emit_movzwl_indexed(x,tl,tl);
2926 }else
2927 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2928 if(jaddr)
2929 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2930 }
2931 }
2932 else
2933 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2934 }
2935 if (opcode[i]==0x27) { // LWU
2936 assert(th>=0);
2937 if(!c||memtarget) {
2938 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2939 #ifdef HOST_IMM_ADDR32
2940 if(c)
2941 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2942 else
2943 #endif
2944 emit_readword_indexed_tlb(0,addr,map,tl);
2945 if(jaddr)
2946 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2947 }
2948 else {
2949 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950 }
2951 emit_zeroreg(th);
2952 }
2953 if (opcode[i]==0x37) { // LD
2954 if(!c||memtarget) {
2955 //gen_tlb_addr_r(tl,map);
2956 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2957 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2958 #ifdef HOST_IMM_ADDR32
2959 if(c)
2960 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2961 else
2962 #endif
2963 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2964 if(jaddr)
2965 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2966 }
2967 else
2968 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969 }
2970 //emit_storereg(rt1[i],tl); // DEBUG
2971 }
2972 //if(opcode[i]==0x23)
2973 //if(opcode[i]==0x24)
2974 //if(opcode[i]==0x23||opcode[i]==0x24)
2975 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2976 {
2977 //emit_pusha();
2978 save_regs(0x100f);
2979 emit_readword((int)&last_count,ECX);
2980 #ifdef __i386__
2981 if(get_reg(i_regs->regmap,CCREG)<0)
2982 emit_loadreg(CCREG,HOST_CCREG);
2983 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2984 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2985 emit_writeword(HOST_CCREG,(int)&Count);
2986 #endif
2987 #ifdef __arm__
2988 if(get_reg(i_regs->regmap,CCREG)<0)
2989 emit_loadreg(CCREG,0);
2990 else
2991 emit_mov(HOST_CCREG,0);
2992 emit_add(0,ECX,0);
2993 emit_addimm(0,2*ccadj[i],0);
2994 emit_writeword(0,(int)&Count);
2995 #endif
2996 emit_call((int)memdebug);
2997 //emit_popa();
2998 restore_regs(0x100f);
2999 }/**/
3000}
3001
3002#ifndef loadlr_assemble
3003void loadlr_assemble(int i,struct regstat *i_regs)
3004{
3005 printf("Need loadlr_assemble for this architecture.\n");
3006 exit(1);
3007}
3008#endif
3009
3010void store_assemble(int i,struct regstat *i_regs)
3011{
3012 int s,th,tl,map=-1;
3013 int addr,temp;
3014 int offset;
3015 int jaddr=0,jaddr2,type;
666a299d 3016 int memtarget=0,c=0;
57871462 3017 int agr=AGEN1+(i&1);
3018 u_int hr,reglist=0;
3019 th=get_reg(i_regs->regmap,rs2[i]|64);
3020 tl=get_reg(i_regs->regmap,rs2[i]);
3021 s=get_reg(i_regs->regmap,rs1[i]);
3022 temp=get_reg(i_regs->regmap,agr);
3023 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3024 offset=imm[i];
3025 if(s>=0) {
3026 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3027 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3028 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3029 }
3030 assert(tl>=0);
3031 assert(temp>=0);
3032 for(hr=0;hr<HOST_REGS;hr++) {
3033 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3034 }
3035 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3036 if(offset||s<0||c) addr=temp;
3037 else addr=s;
3038 if(!using_tlb) {
3039 if(!c) {
3040 #ifdef R29_HACK
3041 // Strmnnrmn's speed hack
3042 memtarget=1;
4cb76aa4 3043 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3044 #endif
4cb76aa4 3045 emit_cmpimm(addr,RAM_SIZE);
57871462 3046 #ifdef DESTRUCTIVE_SHIFT
3047 if(s==addr) emit_mov(s,temp);
3048 #endif
3049 #ifdef R29_HACK
4cb76aa4 3050 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3051 #endif
3052 {
3053 jaddr=(int)out;
3054 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3055 // Hint to branch predictor that the branch is unlikely to be taken
3056 if(rs1[i]>=28)
3057 emit_jno_unlikely(0);
3058 else
3059 #endif
3060 emit_jno(0);
3061 }
3062 }
3063 }else{ // using tlb
3064 int x=0;
3065 if (opcode[i]==0x28) x=3; // SB
3066 if (opcode[i]==0x29) x=2; // SH
3067 map=get_reg(i_regs->regmap,TLREG);
3068 assert(map>=0);
3069 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3070 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3071 }
3072
3073 if (opcode[i]==0x28) { // SB
3074 if(!c||memtarget) {
3075 int x=0;
2002a1db 3076#ifdef BIG_ENDIAN_MIPS
57871462 3077 if(!c) emit_xorimm(addr,3,temp);
3078 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3079#else
3080 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3081 else if (addr!=temp) emit_mov(addr,temp);
3082#endif
57871462 3083 //gen_tlb_addr_w(temp,map);
3084 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3085 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3086 }
3087 type=STOREB_STUB;
3088 }
3089 if (opcode[i]==0x29) { // SH
3090 if(!c||memtarget) {
3091 int x=0;
2002a1db 3092#ifdef BIG_ENDIAN_MIPS
57871462 3093 if(!c) emit_xorimm(addr,2,temp);
3094 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3095#else
3096 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3097 else if (addr!=temp) emit_mov(addr,temp);
3098#endif
57871462 3099 //#ifdef
3100 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3101 //#else
3102 if(map>=0) {
3103 gen_tlb_addr_w(temp,map);
3104 emit_writehword_indexed(tl,x,temp);
3105 }else
3106 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3107 }
3108 type=STOREH_STUB;
3109 }
3110 if (opcode[i]==0x2B) { // SW
3111 if(!c||memtarget)
3112 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3113 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3114 type=STOREW_STUB;
3115 }
3116 if (opcode[i]==0x3F) { // SD
3117 if(!c||memtarget) {
3118 if(rs2[i]) {
3119 assert(th>=0);
3120 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3121 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3122 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3123 }else{
3124 // Store zero
3125 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3126 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3127 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3128 }
3129 }
3130 type=STORED_STUB;
3131 }
666a299d 3132 if(!using_tlb&&(!c||memtarget))
3133 // addr could be a temp, make sure it survives STORE*_STUB
3134 reglist|=1<<addr;
57871462 3135 if(jaddr) {
3136 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3137 } else if(!memtarget) {
3138 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3139 }
3140 if(!using_tlb) {
3141 if(!c||memtarget) {
3142 #ifdef DESTRUCTIVE_SHIFT
3143 // The x86 shift operation is 'destructive'; it overwrites the
3144 // source register, so we need to make a copy first and use that.
3145 addr=temp;
3146 #endif
3147 #if defined(HOST_IMM8)
3148 int ir=get_reg(i_regs->regmap,INVCP);
3149 assert(ir>=0);
3150 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3151 #else
3152 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3153 #endif
3154 jaddr2=(int)out;
3155 emit_jne(0);
3156 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3157 }
3158 }
3159 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3160 //if(opcode[i]==0x2B || opcode[i]==0x28)
3161 //if(opcode[i]==0x2B || opcode[i]==0x29)
3162 //if(opcode[i]==0x2B)
3163 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3164 {
3165 //emit_pusha();
3166 save_regs(0x100f);
3167 emit_readword((int)&last_count,ECX);
3168 #ifdef __i386__
3169 if(get_reg(i_regs->regmap,CCREG)<0)
3170 emit_loadreg(CCREG,HOST_CCREG);
3171 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3172 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3173 emit_writeword(HOST_CCREG,(int)&Count);
3174 #endif
3175 #ifdef __arm__
3176 if(get_reg(i_regs->regmap,CCREG)<0)
3177 emit_loadreg(CCREG,0);
3178 else
3179 emit_mov(HOST_CCREG,0);
3180 emit_add(0,ECX,0);
3181 emit_addimm(0,2*ccadj[i],0);
3182 emit_writeword(0,(int)&Count);
3183 #endif
3184 emit_call((int)memdebug);
3185 //emit_popa();
3186 restore_regs(0x100f);
3187 }/**/
3188}
3189
3190void storelr_assemble(int i,struct regstat *i_regs)
3191{
3192 int s,th,tl;
3193 int temp;
3194 int temp2;
3195 int offset;
3196 int jaddr=0,jaddr2;
3197 int case1,case2,case3;
3198 int done0,done1,done2;
3199 int memtarget,c=0;
fab5d06d 3200 int agr=AGEN1+(i&1);
57871462 3201 u_int hr,reglist=0;
3202 th=get_reg(i_regs->regmap,rs2[i]|64);
3203 tl=get_reg(i_regs->regmap,rs2[i]);
3204 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3205 temp=get_reg(i_regs->regmap,agr);
3206 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3207 offset=imm[i];
3208 if(s>=0) {
3209 c=(i_regs->isconst>>s)&1;
4cb76aa4 3210 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3211 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3212 }
3213 assert(tl>=0);
3214 for(hr=0;hr<HOST_REGS;hr++) {
3215 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3216 }
3217 if(tl>=0) {
3218 assert(temp>=0);
3219 if(!using_tlb) {
3220 if(!c) {
4cb76aa4 3221 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
57871462 3222 if(!offset&&s!=temp) emit_mov(s,temp);
3223 jaddr=(int)out;
3224 emit_jno(0);
3225 }
3226 else
3227 {
3228 if(!memtarget||!rs1[i]) {
3229 jaddr=(int)out;
3230 emit_jmp(0);
3231 }
3232 }
3233 if((u_int)rdram!=0x80000000)
3234 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3235 }else{ // using tlb
3236 int map=get_reg(i_regs->regmap,TLREG);
3237 assert(map>=0);
3238 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3239 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3240 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3241 if(!jaddr&&!memtarget) {
3242 jaddr=(int)out;
3243 emit_jmp(0);
3244 }
3245 gen_tlb_addr_w(temp,map);
3246 }
3247
3248 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3249 temp2=get_reg(i_regs->regmap,FTEMP);
3250 if(!rs2[i]) temp2=th=tl;
3251 }
3252
2002a1db 3253#ifndef BIG_ENDIAN_MIPS
3254 emit_xorimm(temp,3,temp);
3255#endif
57871462 3256 emit_testimm(temp,2);
3257 case2=(int)out;
3258 emit_jne(0);
3259 emit_testimm(temp,1);
3260 case1=(int)out;
3261 emit_jne(0);
3262 // 0
3263 if (opcode[i]==0x2A) { // SWL
3264 emit_writeword_indexed(tl,0,temp);
3265 }
3266 if (opcode[i]==0x2E) { // SWR
3267 emit_writebyte_indexed(tl,3,temp);
3268 }
3269 if (opcode[i]==0x2C) { // SDL
3270 emit_writeword_indexed(th,0,temp);
3271 if(rs2[i]) emit_mov(tl,temp2);
3272 }
3273 if (opcode[i]==0x2D) { // SDR
3274 emit_writebyte_indexed(tl,3,temp);
3275 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3276 }
3277 done0=(int)out;
3278 emit_jmp(0);
3279 // 1
3280 set_jump_target(case1,(int)out);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write 3 msb into three least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,8,tl);
3284 emit_writehword_indexed(tl,-1,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3286 emit_writebyte_indexed(tl,1,temp);
3287 if(rs2[i]) emit_rorimm(tl,8,tl);
3288 }
3289 if (opcode[i]==0x2E) { // SWR
3290 // Write two lsb into two most significant bytes
3291 emit_writehword_indexed(tl,1,temp);
3292 }
3293 if (opcode[i]==0x2C) { // SDL
3294 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3295 // Write 3 msb into three least significant bytes
3296 if(rs2[i]) emit_rorimm(th,8,th);
3297 emit_writehword_indexed(th,-1,temp);
3298 if(rs2[i]) emit_rorimm(th,16,th);
3299 emit_writebyte_indexed(th,1,temp);
3300 if(rs2[i]) emit_rorimm(th,8,th);
3301 }
3302 if (opcode[i]==0x2D) { // SDR
3303 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3304 // Write two lsb into two most significant bytes
3305 emit_writehword_indexed(tl,1,temp);
3306 }
3307 done1=(int)out;
3308 emit_jmp(0);
3309 // 2
3310 set_jump_target(case2,(int)out);
3311 emit_testimm(temp,1);
3312 case3=(int)out;
3313 emit_jne(0);
3314 if (opcode[i]==0x2A) { // SWL
3315 // Write two msb into two least significant bytes
3316 if(rs2[i]) emit_rorimm(tl,16,tl);
3317 emit_writehword_indexed(tl,-2,temp);
3318 if(rs2[i]) emit_rorimm(tl,16,tl);
3319 }
3320 if (opcode[i]==0x2E) { // SWR
3321 // Write 3 lsb into three most significant bytes
3322 emit_writebyte_indexed(tl,-1,temp);
3323 if(rs2[i]) emit_rorimm(tl,8,tl);
3324 emit_writehword_indexed(tl,0,temp);
3325 if(rs2[i]) emit_rorimm(tl,24,tl);
3326 }
3327 if (opcode[i]==0x2C) { // SDL
3328 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3329 // Write two msb into two least significant bytes
3330 if(rs2[i]) emit_rorimm(th,16,th);
3331 emit_writehword_indexed(th,-2,temp);
3332 if(rs2[i]) emit_rorimm(th,16,th);
3333 }
3334 if (opcode[i]==0x2D) { // SDR
3335 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3336 // Write 3 lsb into three most significant bytes
3337 emit_writebyte_indexed(tl,-1,temp);
3338 if(rs2[i]) emit_rorimm(tl,8,tl);
3339 emit_writehword_indexed(tl,0,temp);
3340 if(rs2[i]) emit_rorimm(tl,24,tl);
3341 }
3342 done2=(int)out;
3343 emit_jmp(0);
3344 // 3
3345 set_jump_target(case3,(int)out);
3346 if (opcode[i]==0x2A) { // SWL
3347 // Write msb into least significant byte
3348 if(rs2[i]) emit_rorimm(tl,24,tl);
3349 emit_writebyte_indexed(tl,-3,temp);
3350 if(rs2[i]) emit_rorimm(tl,8,tl);
3351 }
3352 if (opcode[i]==0x2E) { // SWR
3353 // Write entire word
3354 emit_writeword_indexed(tl,-3,temp);
3355 }
3356 if (opcode[i]==0x2C) { // SDL
3357 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3358 // Write msb into least significant byte
3359 if(rs2[i]) emit_rorimm(th,24,th);
3360 emit_writebyte_indexed(th,-3,temp);
3361 if(rs2[i]) emit_rorimm(th,8,th);
3362 }
3363 if (opcode[i]==0x2D) { // SDR
3364 if(rs2[i]) emit_mov(th,temp2);
3365 // Write entire word
3366 emit_writeword_indexed(tl,-3,temp);
3367 }
3368 set_jump_target(done0,(int)out);
3369 set_jump_target(done1,(int)out);
3370 set_jump_target(done2,(int)out);
3371 if (opcode[i]==0x2C) { // SDL
3372 emit_testimm(temp,4);
3373 done0=(int)out;
3374 emit_jne(0);
3375 emit_andimm(temp,~3,temp);
3376 emit_writeword_indexed(temp2,4,temp);
3377 set_jump_target(done0,(int)out);
3378 }
3379 if (opcode[i]==0x2D) { // SDR
3380 emit_testimm(temp,4);
3381 done0=(int)out;
3382 emit_jeq(0);
3383 emit_andimm(temp,~3,temp);
3384 emit_writeword_indexed(temp2,-4,temp);
3385 set_jump_target(done0,(int)out);
3386 }
3387 if(!c||!memtarget)
b7918751 3388 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3389 }
3390 if(!using_tlb) {
3391 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3392 #if defined(HOST_IMM8)
3393 int ir=get_reg(i_regs->regmap,INVCP);
3394 assert(ir>=0);
3395 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3396 #else
3397 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3398 #endif
3399 jaddr2=(int)out;
3400 emit_jne(0);
3401 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3402 }
3403 /*
3404 emit_pusha();
3405 //save_regs(0x100f);
3406 emit_readword((int)&last_count,ECX);
3407 if(get_reg(i_regs->regmap,CCREG)<0)
3408 emit_loadreg(CCREG,HOST_CCREG);
3409 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3410 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3411 emit_writeword(HOST_CCREG,(int)&Count);
3412 emit_call((int)memdebug);
3413 emit_popa();
3414 //restore_regs(0x100f);
3415 /**/
3416}
3417
3418void c1ls_assemble(int i,struct regstat *i_regs)
3419{
3d624f89 3420#ifndef DISABLE_COP1
57871462 3421 int s,th,tl;
3422 int temp,ar;
3423 int map=-1;
3424 int offset;
3425 int c=0;
3426 int jaddr,jaddr2=0,jaddr3,type;
3427 int agr=AGEN1+(i&1);
3428 u_int hr,reglist=0;
3429 th=get_reg(i_regs->regmap,FTEMP|64);
3430 tl=get_reg(i_regs->regmap,FTEMP);
3431 s=get_reg(i_regs->regmap,rs1[i]);
3432 temp=get_reg(i_regs->regmap,agr);
3433 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3434 offset=imm[i];
3435 assert(tl>=0);
3436 assert(rs1[i]>0);
3437 assert(temp>=0);
3438 for(hr=0;hr<HOST_REGS;hr++) {
3439 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3440 }
3441 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3442 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3443 {
3444 // Loads use a temporary register which we need to save
3445 reglist|=1<<temp;
3446 }
3447 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3448 ar=temp;
3449 else // LWC1/LDC1
3450 ar=tl;
3451 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3452 //else c=(i_regs->wasconst>>s)&1;
3453 if(s>=0) c=(i_regs->wasconst>>s)&1;
3454 // Check cop1 unusable
3455 if(!cop1_usable) {
3456 signed char rs=get_reg(i_regs->regmap,CSREG);
3457 assert(rs>=0);
3458 emit_testimm(rs,0x20000000);
3459 jaddr=(int)out;
3460 emit_jeq(0);
3461 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3462 cop1_usable=1;
3463 }
3464 if (opcode[i]==0x39) { // SWC1 (get float address)
3465 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3466 }
3467 if (opcode[i]==0x3D) { // SDC1 (get double address)
3468 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3469 }
3470 // Generate address + offset
3471 if(!using_tlb) {
3472 if(!c)
4cb76aa4 3473 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3474 }
3475 else
3476 {
3477 map=get_reg(i_regs->regmap,TLREG);
3478 assert(map>=0);
3479 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3480 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3481 }
3482 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3483 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3484 }
3485 }
3486 if (opcode[i]==0x39) { // SWC1 (read float)
3487 emit_readword_indexed(0,tl,tl);
3488 }
3489 if (opcode[i]==0x3D) { // SDC1 (read double)
3490 emit_readword_indexed(4,tl,th);
3491 emit_readword_indexed(0,tl,tl);
3492 }
3493 if (opcode[i]==0x31) { // LWC1 (get target address)
3494 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3495 }
3496 if (opcode[i]==0x35) { // LDC1 (get target address)
3497 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3498 }
3499 if(!using_tlb) {
3500 if(!c) {
3501 jaddr2=(int)out;
3502 emit_jno(0);
3503 }
4cb76aa4 3504 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3505 jaddr2=(int)out;
3506 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3507 }
3508 #ifdef DESTRUCTIVE_SHIFT
3509 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3510 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3511 }
3512 #endif
3513 }else{
3514 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3515 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3516 }
3517 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3518 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3519 }
3520 }
3521 if (opcode[i]==0x31) { // LWC1
3522 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3523 //gen_tlb_addr_r(ar,map);
3524 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3525 #ifdef HOST_IMM_ADDR32
3526 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3527 else
3528 #endif
3529 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3530 type=LOADW_STUB;
3531 }
3532 if (opcode[i]==0x35) { // LDC1
3533 assert(th>=0);
3534 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3535 //gen_tlb_addr_r(ar,map);
3536 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3537 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3538 #ifdef HOST_IMM_ADDR32
3539 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3540 else
3541 #endif
3542 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3543 type=LOADD_STUB;
3544 }
3545 if (opcode[i]==0x39) { // SWC1
3546 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3547 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3548 type=STOREW_STUB;
3549 }
3550 if (opcode[i]==0x3D) { // SDC1
3551 assert(th>=0);
3552 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3553 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3554 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3555 type=STORED_STUB;
3556 }
3557 if(!using_tlb) {
3558 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3559 #ifndef DESTRUCTIVE_SHIFT
3560 temp=offset||c||s<0?ar:s;
3561 #endif
3562 #if defined(HOST_IMM8)
3563 int ir=get_reg(i_regs->regmap,INVCP);
3564 assert(ir>=0);
3565 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3566 #else
3567 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3568 #endif
3569 jaddr3=(int)out;
3570 emit_jne(0);
3571 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3572 }
3573 }
3574 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3575 if (opcode[i]==0x31) { // LWC1 (write float)
3576 emit_writeword_indexed(tl,0,temp);
3577 }
3578 if (opcode[i]==0x35) { // LDC1 (write double)
3579 emit_writeword_indexed(th,4,temp);
3580 emit_writeword_indexed(tl,0,temp);
3581 }
3582 //if(opcode[i]==0x39)
3583 /*if(opcode[i]==0x39||opcode[i]==0x31)
3584 {
3585 emit_pusha();
3586 emit_readword((int)&last_count,ECX);
3587 if(get_reg(i_regs->regmap,CCREG)<0)
3588 emit_loadreg(CCREG,HOST_CCREG);
3589 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3590 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3591 emit_writeword(HOST_CCREG,(int)&Count);
3592 emit_call((int)memdebug);
3593 emit_popa();
3594 }/**/
3d624f89 3595#else
3596 cop1_unusable(i, i_regs);
3597#endif
57871462 3598}
3599
b9b61529 3600void c2ls_assemble(int i,struct regstat *i_regs)
3601{
3602 int s,tl;
3603 int ar;
3604 int offset;
1fd1aceb 3605 int memtarget=0,c=0;
b9b61529 3606 int jaddr,jaddr2=0,jaddr3,type;
3607 int agr=AGEN1+(i&1);
3608 u_int hr,reglist=0;
3609 u_int copr=(source[i]>>16)&0x1f;
3610 s=get_reg(i_regs->regmap,rs1[i]);
3611 tl=get_reg(i_regs->regmap,FTEMP);
3612 offset=imm[i];
3613 assert(rs1[i]>0);
3614 assert(tl>=0);
3615 assert(!using_tlb);
3616
3617 for(hr=0;hr<HOST_REGS;hr++) {
3618 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3619 }
3620 if(i_regs->regmap[HOST_CCREG]==CCREG)
3621 reglist&=~(1<<HOST_CCREG);
3622
3623 // get the address
3624 if (opcode[i]==0x3a) { // SWC2
3625 ar=get_reg(i_regs->regmap,agr);
3626 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3627 reglist|=1<<ar;
3628 } else { // LWC2
3629 ar=tl;
3630 }
1fd1aceb 3631 if(s>=0) c=(i_regs->wasconst>>s)&1;
3632 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3633 if (!offset&&!c&&s>=0) ar=s;
3634 assert(ar>=0);
3635
3636 if (opcode[i]==0x3a) { // SWC2
3637 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3638 type=STOREW_STUB;
b9b61529 3639 }
1fd1aceb 3640 else
b9b61529 3641 type=LOADW_STUB;
1fd1aceb 3642
3643 if(c&&!memtarget) {
3644 jaddr2=(int)out;
3645 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3646 }
1fd1aceb 3647 else {
3648 if(!c) {
3649 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3650 jaddr2=(int)out;
3651 emit_jno(0);
3652 }
3653 if (opcode[i]==0x32) { // LWC2
3654 #ifdef HOST_IMM_ADDR32
3655 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3656 else
3657 #endif
3658 emit_readword_indexed(0,ar,tl);
3659 }
3660 if (opcode[i]==0x3a) { // SWC2
3661 #ifdef DESTRUCTIVE_SHIFT
3662 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3663 #endif
3664 emit_writeword_indexed(tl,0,ar);
3665 }
b9b61529 3666 }
3667 if(jaddr2)
3668 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3669 if (opcode[i]==0x3a) { // SWC2
3670#if defined(HOST_IMM8)
3671 int ir=get_reg(i_regs->regmap,INVCP);
3672 assert(ir>=0);
3673 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3674#else
3675 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3676#endif
3677 jaddr3=(int)out;
3678 emit_jne(0);
3679 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3680 }
3681 if (opcode[i]==0x32) { // LWC2
3682 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3683 }
3684}
3685
57871462 3686#ifndef multdiv_assemble
3687void multdiv_assemble(int i,struct regstat *i_regs)
3688{
3689 printf("Need multdiv_assemble for this architecture.\n");
3690 exit(1);
3691}
3692#endif
3693
3694void mov_assemble(int i,struct regstat *i_regs)
3695{
3696 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3697 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
f5b13bdc 3698 //assert(rt1[i]>0);
57871462 3699 if(rt1[i]) {
3700 signed char sh,sl,th,tl;
3701 th=get_reg(i_regs->regmap,rt1[i]|64);
3702 tl=get_reg(i_regs->regmap,rt1[i]);
3703 //assert(tl>=0);
3704 if(tl>=0) {
3705 sh=get_reg(i_regs->regmap,rs1[i]|64);
3706 sl=get_reg(i_regs->regmap,rs1[i]);
3707 if(sl>=0) emit_mov(sl,tl);
3708 else emit_loadreg(rs1[i],tl);
3709 if(th>=0) {
3710 if(sh>=0) emit_mov(sh,th);
3711 else emit_loadreg(rs1[i]|64,th);
3712 }
3713 }
3714 }
3715}
3716
3717#ifndef fconv_assemble
3718void fconv_assemble(int i,struct regstat *i_regs)
3719{
3720 printf("Need fconv_assemble for this architecture.\n");
3721 exit(1);
3722}
3723#endif
3724
3725#if 0
3726void float_assemble(int i,struct regstat *i_regs)
3727{
3728 printf("Need float_assemble for this architecture.\n");
3729 exit(1);
3730}
3731#endif
3732
3733void syscall_assemble(int i,struct regstat *i_regs)
3734{
3735 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3736 assert(ccreg==HOST_CCREG);
3737 assert(!is_delayslot);
3738 emit_movimm(start+i*4,EAX); // Get PC
3739 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3740 emit_jmp((int)jump_syscall_hle); // XXX
3741}
3742
3743void hlecall_assemble(int i,struct regstat *i_regs)
3744{
3745 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3746 assert(ccreg==HOST_CCREG);
3747 assert(!is_delayslot);
3748 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3749 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3750 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3751 emit_jmp((int)jump_hlecall);
57871462 3752}
3753
1e973cb0 3754void intcall_assemble(int i,struct regstat *i_regs)
3755{
3756 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3757 assert(ccreg==HOST_CCREG);
3758 assert(!is_delayslot);
3759 emit_movimm(start+i*4,0); // Get PC
3760 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3761 emit_jmp((int)jump_intcall);
3762}
3763
57871462 3764void ds_assemble(int i,struct regstat *i_regs)
3765{
3766 is_delayslot=1;
3767 switch(itype[i]) {
3768 case ALU:
3769 alu_assemble(i,i_regs);break;
3770 case IMM16:
3771 imm16_assemble(i,i_regs);break;
3772 case SHIFT:
3773 shift_assemble(i,i_regs);break;
3774 case SHIFTIMM:
3775 shiftimm_assemble(i,i_regs);break;
3776 case LOAD:
3777 load_assemble(i,i_regs);break;
3778 case LOADLR:
3779 loadlr_assemble(i,i_regs);break;
3780 case STORE:
3781 store_assemble(i,i_regs);break;
3782 case STORELR:
3783 storelr_assemble(i,i_regs);break;
3784 case COP0:
3785 cop0_assemble(i,i_regs);break;
3786 case COP1:
3787 cop1_assemble(i,i_regs);break;
3788 case C1LS:
3789 c1ls_assemble(i,i_regs);break;
b9b61529 3790 case COP2:
3791 cop2_assemble(i,i_regs);break;
3792 case C2LS:
3793 c2ls_assemble(i,i_regs);break;
3794 case C2OP:
3795 c2op_assemble(i,i_regs);break;
57871462 3796 case FCONV:
3797 fconv_assemble(i,i_regs);break;
3798 case FLOAT:
3799 float_assemble(i,i_regs);break;
3800 case FCOMP:
3801 fcomp_assemble(i,i_regs);break;
3802 case MULTDIV:
3803 multdiv_assemble(i,i_regs);break;
3804 case MOV:
3805 mov_assemble(i,i_regs);break;
3806 case SYSCALL:
7139f3c8 3807 case HLECALL:
1e973cb0 3808 case INTCALL:
57871462 3809 case SPAN:
3810 case UJUMP:
3811 case RJUMP:
3812 case CJUMP:
3813 case SJUMP:
3814 case FJUMP:
3815 printf("Jump in the delay slot. This is probably a bug.\n");
3816 }
3817 is_delayslot=0;
3818}
3819
3820// Is the branch target a valid internal jump?
3821int internal_branch(uint64_t i_is32,int addr)
3822{
3823 if(addr&1) return 0; // Indirect (register) jump
3824 if(addr>=start && addr<start+slen*4-4)
3825 {
3826 int t=(addr-start)>>2;
3827 // Delay slots are not valid branch targets
3828 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3829 // 64 -> 32 bit transition requires a recompile
3830 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3831 {
3832 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3833 else printf("optimizable: yes\n");
3834 }*/
3835 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3836 if(requires_32bit[t]&~i_is32) return 0;
3837 else return 1;
3838 }
3839 return 0;
3840}
3841
3842#ifndef wb_invalidate
3843void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3844 uint64_t u,uint64_t uu)
3845{
3846 int hr;
3847 for(hr=0;hr<HOST_REGS;hr++) {
3848 if(hr!=EXCLUDE_REG) {
3849 if(pre[hr]!=entry[hr]) {
3850 if(pre[hr]>=0) {
3851 if((dirty>>hr)&1) {
3852 if(get_reg(entry,pre[hr])<0) {
3853 if(pre[hr]<64) {
3854 if(!((u>>pre[hr])&1)) {
3855 emit_storereg(pre[hr],hr);
3856 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3857 emit_sarimm(hr,31,hr);
3858 emit_storereg(pre[hr]|64,hr);
3859 }
3860 }
3861 }else{
3862 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3863 emit_storereg(pre[hr],hr);
3864 }
3865 }
3866 }
3867 }
3868 }
3869 }
3870 }
3871 }
3872 // Move from one register to another (no writeback)
3873 for(hr=0;hr<HOST_REGS;hr++) {
3874 if(hr!=EXCLUDE_REG) {
3875 if(pre[hr]!=entry[hr]) {
3876 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3877 int nr;
3878 if((nr=get_reg(entry,pre[hr]))>=0) {
3879 emit_mov(hr,nr);
3880 }
3881 }
3882 }
3883 }
3884 }
3885}
3886#endif
3887
3888// Load the specified registers
3889// This only loads the registers given as arguments because
3890// we don't want to load things that will be overwritten
3891void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3892{
3893 int hr;
3894 // Load 32-bit regs
3895 for(hr=0;hr<HOST_REGS;hr++) {
3896 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3897 if(entry[hr]!=regmap[hr]) {
3898 if(regmap[hr]==rs1||regmap[hr]==rs2)
3899 {
3900 if(regmap[hr]==0) {
3901 emit_zeroreg(hr);
3902 }
3903 else
3904 {
3905 emit_loadreg(regmap[hr],hr);
3906 }
3907 }
3908 }
3909 }
3910 }
3911 //Load 64-bit regs
3912 for(hr=0;hr<HOST_REGS;hr++) {
3913 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3914 if(entry[hr]!=regmap[hr]) {
3915 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3916 {
3917 assert(regmap[hr]!=64);
3918 if((is32>>(regmap[hr]&63))&1) {
3919 int lr=get_reg(regmap,regmap[hr]-64);
3920 if(lr>=0)
3921 emit_sarimm(lr,31,hr);
3922 else
3923 emit_loadreg(regmap[hr],hr);
3924 }
3925 else
3926 {
3927 emit_loadreg(regmap[hr],hr);
3928 }
3929 }
3930 }
3931 }
3932 }
3933}
3934
3935// Load registers prior to the start of a loop
3936// so that they are not loaded within the loop
3937static void loop_preload(signed char pre[],signed char entry[])
3938{
3939 int hr;
3940 for(hr=0;hr<HOST_REGS;hr++) {
3941 if(hr!=EXCLUDE_REG) {
3942 if(pre[hr]!=entry[hr]) {
3943 if(entry[hr]>=0) {
3944 if(get_reg(pre,entry[hr])<0) {
3945 assem_debug("loop preload:\n");
3946 //printf("loop preload: %d\n",hr);
3947 if(entry[hr]==0) {
3948 emit_zeroreg(hr);
3949 }
3950 else if(entry[hr]<TEMPREG)
3951 {
3952 emit_loadreg(entry[hr],hr);
3953 }
3954 else if(entry[hr]-64<TEMPREG)
3955 {
3956 emit_loadreg(entry[hr],hr);
3957 }
3958 }
3959 }
3960 }
3961 }
3962 }
3963}
3964
3965// Generate address for load/store instruction
b9b61529 3966// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 3967void address_generation(int i,struct regstat *i_regs,signed char entry[])
3968{
b9b61529 3969 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
57871462 3970 int ra;
3971 int agr=AGEN1+(i&1);
3972 int mgr=MGEN1+(i&1);
3973 if(itype[i]==LOAD) {
3974 ra=get_reg(i_regs->regmap,rt1[i]);
3975 //if(rt1[i]) assert(ra>=0);
3976 }
3977 if(itype[i]==LOADLR) {
3978 ra=get_reg(i_regs->regmap,FTEMP);
3979 }
3980 if(itype[i]==STORE||itype[i]==STORELR) {
3981 ra=get_reg(i_regs->regmap,agr);
3982 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3983 }
b9b61529 3984 if(itype[i]==C1LS||itype[i]==C2LS) {
3985 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 3986 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 3987 else { // SWC1/SDC1/SWC2/SDC2
57871462 3988 ra=get_reg(i_regs->regmap,agr);
3989 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3990 }
3991 }
3992 int rs=get_reg(i_regs->regmap,rs1[i]);
3993 int rm=get_reg(i_regs->regmap,TLREG);
3994 if(ra>=0) {
3995 int offset=imm[i];
3996 int c=(i_regs->wasconst>>rs)&1;
3997 if(rs1[i]==0) {
3998 // Using r0 as a base address
3999 /*if(rm>=0) {
4000 if(!entry||entry[rm]!=mgr) {
4001 generate_map_const(offset,rm);
4002 } // else did it in the previous cycle
4003 }*/
4004 if(!entry||entry[ra]!=agr) {
4005 if (opcode[i]==0x22||opcode[i]==0x26) {
4006 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4007 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4008 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4009 }else{
4010 emit_movimm(offset,ra);
4011 }
4012 } // else did it in the previous cycle
4013 }
4014 else if(rs<0) {
4015 if(!entry||entry[ra]!=rs1[i])
4016 emit_loadreg(rs1[i],ra);
4017 //if(!entry||entry[ra]!=rs1[i])
4018 // printf("poor load scheduling!\n");
4019 }
4020 else if(c) {
4021 if(rm>=0) {
4022 if(!entry||entry[rm]!=mgr) {
b9b61529 4023 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4024 // Stores to memory go thru the mapper to detect self-modifying
4025 // code, loads don't.
4026 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4027 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4028 generate_map_const(constmap[i][rs]+offset,rm);
4029 }else{
4030 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4031 generate_map_const(constmap[i][rs]+offset,rm);
4032 }
4033 }
4034 }
4035 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4036 if(!entry||entry[ra]!=agr) {
4037 if (opcode[i]==0x22||opcode[i]==0x26) {
4038 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4039 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4040 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4041 }else{
4042 #ifdef HOST_IMM_ADDR32
b9b61529 4043 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4044 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4045 #endif
4046 emit_movimm(constmap[i][rs]+offset,ra);
4047 }
4048 } // else did it in the previous cycle
4049 } // else load_consts already did it
4050 }
4051 if(offset&&!c&&rs1[i]) {
4052 if(rs>=0) {
4053 emit_addimm(rs,offset,ra);
4054 }else{
4055 emit_addimm(ra,offset,ra);
4056 }
4057 }
4058 }
4059 }
4060 // Preload constants for next instruction
b9b61529 4061 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4062 int agr,ra;
4063 #ifndef HOST_IMM_ADDR32
4064 // Mapper entry
4065 agr=MGEN1+((i+1)&1);
4066 ra=get_reg(i_regs->regmap,agr);
4067 if(ra>=0) {
4068 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4069 int offset=imm[i+1];
4070 int c=(regs[i+1].wasconst>>rs)&1;
4071 if(c) {
b9b61529 4072 if(itype[i+1]==STORE||itype[i+1]==STORELR
4073 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4074 // Stores to memory go thru the mapper to detect self-modifying
4075 // code, loads don't.
4076 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4077 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4078 generate_map_const(constmap[i+1][rs]+offset,ra);
4079 }else{
4080 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4081 generate_map_const(constmap[i+1][rs]+offset,ra);
4082 }
4083 }
4084 /*else if(rs1[i]==0) {
4085 generate_map_const(offset,ra);
4086 }*/
4087 }
4088 #endif
4089 // Actual address
4090 agr=AGEN1+((i+1)&1);
4091 ra=get_reg(i_regs->regmap,agr);
4092 if(ra>=0) {
4093 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4094 int offset=imm[i+1];
4095 int c=(regs[i+1].wasconst>>rs)&1;
4096 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4097 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4098 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4099 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4100 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4101 }else{
4102 #ifdef HOST_IMM_ADDR32
b9b61529 4103 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4104 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4105 #endif
4106 emit_movimm(constmap[i+1][rs]+offset,ra);
4107 }
4108 }
4109 else if(rs1[i+1]==0) {
4110 // Using r0 as a base address
4111 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4112 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4113 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4114 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4115 }else{
4116 emit_movimm(offset,ra);
4117 }
4118 }
4119 }
4120 }
4121}
4122
4123int get_final_value(int hr, int i, int *value)
4124{
4125 int reg=regs[i].regmap[hr];
4126 while(i<slen-1) {
4127 if(regs[i+1].regmap[hr]!=reg) break;
4128 if(!((regs[i+1].isconst>>hr)&1)) break;
4129 if(bt[i+1]) break;
4130 i++;
4131 }
4132 if(i<slen-1) {
4133 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4134 *value=constmap[i][hr];
4135 return 1;
4136 }
4137 if(!bt[i+1]) {
4138 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4139 // Load in delay slot, out-of-order execution
4140 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4141 {
4142 #ifdef HOST_IMM_ADDR32
4143 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4144 #endif
4145 // Precompute load address
4146 *value=constmap[i][hr]+imm[i+2];
4147 return 1;
4148 }
4149 }
4150 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4151 {
4152 #ifdef HOST_IMM_ADDR32
4153 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4154 #endif
4155 // Precompute load address
4156 *value=constmap[i][hr]+imm[i+1];
4157 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4158 return 1;
4159 }
4160 }
4161 }
4162 *value=constmap[i][hr];
4163 //printf("c=%x\n",(int)constmap[i][hr]);
4164 if(i==slen-1) return 1;
4165 if(reg<64) {
4166 return !((unneeded_reg[i+1]>>reg)&1);
4167 }else{
4168 return !((unneeded_reg_upper[i+1]>>reg)&1);
4169 }
4170}
4171
4172// Load registers with known constants
4173void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4174{
4175 int hr;
4176 // Load 32-bit regs
4177 for(hr=0;hr<HOST_REGS;hr++) {
4178 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4179 //if(entry[hr]!=regmap[hr]) {
4180 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4181 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4182 int value;
4183 if(get_final_value(hr,i,&value)) {
4184 if(value==0) {
4185 emit_zeroreg(hr);
4186 }
4187 else {
4188 emit_movimm(value,hr);
4189 }
4190 }
4191 }
4192 }
4193 }
4194 }
4195 // Load 64-bit regs
4196 for(hr=0;hr<HOST_REGS;hr++) {
4197 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4198 //if(entry[hr]!=regmap[hr]) {
4199 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4200 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4201 if((is32>>(regmap[hr]&63))&1) {
4202 int lr=get_reg(regmap,regmap[hr]-64);
4203 assert(lr>=0);
4204 emit_sarimm(lr,31,hr);
4205 }
4206 else
4207 {
4208 int value;
4209 if(get_final_value(hr,i,&value)) {
4210 if(value==0) {
4211 emit_zeroreg(hr);
4212 }
4213 else {
4214 emit_movimm(value,hr);
4215 }
4216 }
4217 }
4218 }
4219 }
4220 }
4221 }
4222}
4223void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4224{
4225 int hr;
4226 // Load 32-bit regs
4227 for(hr=0;hr<HOST_REGS;hr++) {
4228 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4229 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4230 int value=constmap[i][hr];
4231 if(value==0) {
4232 emit_zeroreg(hr);
4233 }
4234 else {
4235 emit_movimm(value,hr);
4236 }
4237 }
4238 }
4239 }
4240 // Load 64-bit regs
4241 for(hr=0;hr<HOST_REGS;hr++) {
4242 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4243 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4244 if((is32>>(regmap[hr]&63))&1) {
4245 int lr=get_reg(regmap,regmap[hr]-64);
4246 assert(lr>=0);
4247 emit_sarimm(lr,31,hr);
4248 }
4249 else
4250 {
4251 int value=constmap[i][hr];
4252 if(value==0) {
4253 emit_zeroreg(hr);
4254 }
4255 else {
4256 emit_movimm(value,hr);
4257 }
4258 }
4259 }
4260 }
4261 }
4262}
4263
4264// Write out all dirty registers (except cycle count)
4265void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4266{
4267 int hr;
4268 for(hr=0;hr<HOST_REGS;hr++) {
4269 if(hr!=EXCLUDE_REG) {
4270 if(i_regmap[hr]>0) {
4271 if(i_regmap[hr]!=CCREG) {
4272 if((i_dirty>>hr)&1) {
4273 if(i_regmap[hr]<64) {
4274 emit_storereg(i_regmap[hr],hr);
24385cae 4275#ifndef FORCE32
57871462 4276 if( ((i_is32>>i_regmap[hr])&1) ) {
4277 #ifdef DESTRUCTIVE_WRITEBACK
4278 emit_sarimm(hr,31,hr);
4279 emit_storereg(i_regmap[hr]|64,hr);
4280 #else
4281 emit_sarimm(hr,31,HOST_TEMPREG);
4282 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4283 #endif
4284 }
24385cae 4285#endif
57871462 4286 }else{
4287 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4288 emit_storereg(i_regmap[hr],hr);
4289 }
4290 }
4291 }
4292 }
4293 }
4294 }
4295 }
4296}
4297// Write out dirty registers that we need to reload (pair with load_needed_regs)
4298// This writes the registers not written by store_regs_bt
4299void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4300{
4301 int hr;
4302 int t=(addr-start)>>2;
4303 for(hr=0;hr<HOST_REGS;hr++) {
4304 if(hr!=EXCLUDE_REG) {
4305 if(i_regmap[hr]>0) {
4306 if(i_regmap[hr]!=CCREG) {
4307 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4308 if((i_dirty>>hr)&1) {
4309 if(i_regmap[hr]<64) {
4310 emit_storereg(i_regmap[hr],hr);
24385cae 4311#ifndef FORCE32
57871462 4312 if( ((i_is32>>i_regmap[hr])&1) ) {
4313 #ifdef DESTRUCTIVE_WRITEBACK
4314 emit_sarimm(hr,31,hr);
4315 emit_storereg(i_regmap[hr]|64,hr);
4316 #else
4317 emit_sarimm(hr,31,HOST_TEMPREG);
4318 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4319 #endif
4320 }
24385cae 4321#endif
57871462 4322 }else{
4323 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4324 emit_storereg(i_regmap[hr],hr);
4325 }
4326 }
4327 }
4328 }
4329 }
4330 }
4331 }
4332 }
4333}
4334
4335// Load all registers (except cycle count)
4336void load_all_regs(signed char i_regmap[])
4337{
4338 int hr;
4339 for(hr=0;hr<HOST_REGS;hr++) {
4340 if(hr!=EXCLUDE_REG) {
4341 if(i_regmap[hr]==0) {
4342 emit_zeroreg(hr);
4343 }
4344 else
4345 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4346 {
4347 emit_loadreg(i_regmap[hr],hr);
4348 }
4349 }
4350 }
4351}
4352
4353// Load all current registers also needed by next instruction
4354void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4355{
4356 int hr;
4357 for(hr=0;hr<HOST_REGS;hr++) {
4358 if(hr!=EXCLUDE_REG) {
4359 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4360 if(i_regmap[hr]==0) {
4361 emit_zeroreg(hr);
4362 }
4363 else
4364 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4365 {
4366 emit_loadreg(i_regmap[hr],hr);
4367 }
4368 }
4369 }
4370 }
4371}
4372
4373// Load all regs, storing cycle count if necessary
4374void load_regs_entry(int t)
4375{
4376 int hr;
4377 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4378 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4379 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4380 emit_storereg(CCREG,HOST_CCREG);
4381 }
4382 // Load 32-bit regs
4383 for(hr=0;hr<HOST_REGS;hr++) {
4384 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4385 if(regs[t].regmap_entry[hr]==0) {
4386 emit_zeroreg(hr);
4387 }
4388 else if(regs[t].regmap_entry[hr]!=CCREG)
4389 {
4390 emit_loadreg(regs[t].regmap_entry[hr],hr);
4391 }
4392 }
4393 }
4394 // Load 64-bit regs
4395 for(hr=0;hr<HOST_REGS;hr++) {
4396 if(regs[t].regmap_entry[hr]>=64) {
4397 assert(regs[t].regmap_entry[hr]!=64);
4398 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4399 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4400 if(lr<0) {
4401 emit_loadreg(regs[t].regmap_entry[hr],hr);
4402 }
4403 else
4404 {
4405 emit_sarimm(lr,31,hr);
4406 }
4407 }
4408 else
4409 {
4410 emit_loadreg(regs[t].regmap_entry[hr],hr);
4411 }
4412 }
4413 }
4414}
4415
4416// Store dirty registers prior to branch
4417void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4418{
4419 if(internal_branch(i_is32,addr))
4420 {
4421 int t=(addr-start)>>2;
4422 int hr;
4423 for(hr=0;hr<HOST_REGS;hr++) {
4424 if(hr!=EXCLUDE_REG) {
4425 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4426 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4427 if((i_dirty>>hr)&1) {
4428 if(i_regmap[hr]<64) {
4429 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4430 emit_storereg(i_regmap[hr],hr);
4431 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4432 #ifdef DESTRUCTIVE_WRITEBACK
4433 emit_sarimm(hr,31,hr);
4434 emit_storereg(i_regmap[hr]|64,hr);
4435 #else
4436 emit_sarimm(hr,31,HOST_TEMPREG);
4437 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4438 #endif
4439 }
4440 }
4441 }else{
4442 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4443 emit_storereg(i_regmap[hr],hr);
4444 }
4445 }
4446 }
4447 }
4448 }
4449 }
4450 }
4451 }
4452 else
4453 {
4454 // Branch out of this block, write out all dirty regs
4455 wb_dirtys(i_regmap,i_is32,i_dirty);
4456 }
4457}
4458
4459// Load all needed registers for branch target
4460void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4461{
4462 //if(addr>=start && addr<(start+slen*4))
4463 if(internal_branch(i_is32,addr))
4464 {
4465 int t=(addr-start)>>2;
4466 int hr;
4467 // Store the cycle count before loading something else
4468 if(i_regmap[HOST_CCREG]!=CCREG) {
4469 assert(i_regmap[HOST_CCREG]==-1);
4470 }
4471 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4472 emit_storereg(CCREG,HOST_CCREG);
4473 }
4474 // Load 32-bit regs
4475 for(hr=0;hr<HOST_REGS;hr++) {
4476 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4477 #ifdef DESTRUCTIVE_WRITEBACK
4478 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4479 #else
4480 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4481 #endif
4482 if(regs[t].regmap_entry[hr]==0) {
4483 emit_zeroreg(hr);
4484 }
4485 else if(regs[t].regmap_entry[hr]!=CCREG)
4486 {
4487 emit_loadreg(regs[t].regmap_entry[hr],hr);
4488 }
4489 }
4490 }
4491 }
4492 //Load 64-bit regs
4493 for(hr=0;hr<HOST_REGS;hr++) {
4494 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4495 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4496 assert(regs[t].regmap_entry[hr]!=64);
4497 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4498 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4499 if(lr<0) {
4500 emit_loadreg(regs[t].regmap_entry[hr],hr);
4501 }
4502 else
4503 {
4504 emit_sarimm(lr,31,hr);
4505 }
4506 }
4507 else
4508 {
4509 emit_loadreg(regs[t].regmap_entry[hr],hr);
4510 }
4511 }
4512 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4513 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4514 assert(lr>=0);
4515 emit_sarimm(lr,31,hr);
4516 }
4517 }
4518 }
4519 }
4520}
4521
4522int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4523{
4524 if(addr>=start && addr<start+slen*4-4)
4525 {
4526 int t=(addr-start)>>2;
4527 int hr;
4528 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4529 for(hr=0;hr<HOST_REGS;hr++)
4530 {
4531 if(hr!=EXCLUDE_REG)
4532 {
4533 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4534 {
4535 if(regs[t].regmap_entry[hr]!=-1)
4536 {
4537 return 0;
4538 }
4539 else
4540 if((i_dirty>>hr)&1)
4541 {
4542 if(i_regmap[hr]<64)
4543 {
4544 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4545 return 0;
4546 }
4547 else
4548 {
4549 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4550 return 0;
4551 }
4552 }
4553 }
4554 else // Same register but is it 32-bit or dirty?
4555 if(i_regmap[hr]>=0)
4556 {
4557 if(!((regs[t].dirty>>hr)&1))
4558 {
4559 if((i_dirty>>hr)&1)
4560 {
4561 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4562 {
4563 //printf("%x: dirty no match\n",addr);
4564 return 0;
4565 }
4566 }
4567 }
4568 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4569 {
4570 //printf("%x: is32 no match\n",addr);
4571 return 0;
4572 }
4573 }
4574 }
4575 }
4576 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4577 if(requires_32bit[t]&~i_is32) return 0;
4578 // Delay slots are not valid branch targets
4579 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4580 // Delay slots require additional processing, so do not match
4581 if(is_ds[t]) return 0;
4582 }
4583 else
4584 {
4585 int hr;
4586 for(hr=0;hr<HOST_REGS;hr++)
4587 {
4588 if(hr!=EXCLUDE_REG)
4589 {
4590 if(i_regmap[hr]>=0)
4591 {
4592 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4593 {
4594 if((i_dirty>>hr)&1)
4595 {
4596 return 0;
4597 }
4598 }
4599 }
4600 }
4601 }
4602 }
4603 return 1;
4604}
4605
4606// Used when a branch jumps into the delay slot of another branch
4607void ds_assemble_entry(int i)
4608{
4609 int t=(ba[i]-start)>>2;
4610 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4611 assem_debug("Assemble delay slot at %x\n",ba[i]);
4612 assem_debug("<->\n");
4613 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4614 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4615 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4616 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4617 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4618 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4619 cop1_usable=0;
4620 is_delayslot=0;
4621 switch(itype[t]) {
4622 case ALU:
4623 alu_assemble(t,&regs[t]);break;
4624 case IMM16:
4625 imm16_assemble(t,&regs[t]);break;
4626 case SHIFT:
4627 shift_assemble(t,&regs[t]);break;
4628 case SHIFTIMM:
4629 shiftimm_assemble(t,&regs[t]);break;
4630 case LOAD:
4631 load_assemble(t,&regs[t]);break;
4632 case LOADLR:
4633 loadlr_assemble(t,&regs[t]);break;
4634 case STORE:
4635 store_assemble(t,&regs[t]);break;
4636 case STORELR:
4637 storelr_assemble(t,&regs[t]);break;
4638 case COP0:
4639 cop0_assemble(t,&regs[t]);break;
4640 case COP1:
4641 cop1_assemble(t,&regs[t]);break;
4642 case C1LS:
4643 c1ls_assemble(t,&regs[t]);break;
b9b61529 4644 case COP2:
4645 cop2_assemble(t,&regs[t]);break;
4646 case C2LS:
4647 c2ls_assemble(t,&regs[t]);break;
4648 case C2OP:
4649 c2op_assemble(t,&regs[t]);break;
57871462 4650 case FCONV:
4651 fconv_assemble(t,&regs[t]);break;
4652 case FLOAT:
4653 float_assemble(t,&regs[t]);break;
4654 case FCOMP:
4655 fcomp_assemble(t,&regs[t]);break;
4656 case MULTDIV:
4657 multdiv_assemble(t,&regs[t]);break;
4658 case MOV:
4659 mov_assemble(t,&regs[t]);break;
4660 case SYSCALL:
7139f3c8 4661 case HLECALL:
1e973cb0 4662 case INTCALL:
57871462 4663 case SPAN:
4664 case UJUMP:
4665 case RJUMP:
4666 case CJUMP:
4667 case SJUMP:
4668 case FJUMP:
4669 printf("Jump in the delay slot. This is probably a bug.\n");
4670 }
4671 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4672 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4673 if(internal_branch(regs[t].is32,ba[i]+4))
4674 assem_debug("branch: internal\n");
4675 else
4676 assem_debug("branch: external\n");
4677 assert(internal_branch(regs[t].is32,ba[i]+4));
4678 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4679 emit_jmp(0);
4680}
4681
4682void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4683{
4684 int count;
4685 int jaddr;
4686 int idle=0;
4687 if(itype[i]==RJUMP)
4688 {
4689 *adj=0;
4690 }
4691 //if(ba[i]>=start && ba[i]<(start+slen*4))
4692 if(internal_branch(branch_regs[i].is32,ba[i]))
4693 {
4694 int t=(ba[i]-start)>>2;
4695 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4696 else *adj=ccadj[t];
4697 }
4698 else
4699 {
4700 *adj=0;
4701 }
4702 count=ccadj[i];
4703 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4704 // Idle loop
4705 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4706 idle=(int)out;
4707 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4708 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4709 jaddr=(int)out;
4710 emit_jmp(0);
4711 }
4712 else if(*adj==0||invert) {
4713 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4714 jaddr=(int)out;
4715 emit_jns(0);
4716 }
4717 else
4718 {
4719 emit_cmpimm(HOST_CCREG,-2*(count+2));
4720 jaddr=(int)out;
4721 emit_jns(0);
4722 }
4723 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4724}
4725
4726void do_ccstub(int n)
4727{
4728 literal_pool(256);
4729 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4730 set_jump_target(stubs[n][1],(int)out);
4731 int i=stubs[n][4];
4732 if(stubs[n][6]==NULLDS) {
4733 // Delay slot instruction is nullified ("likely" branch)
4734 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4735 }
4736 else if(stubs[n][6]!=TAKEN) {
4737 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4738 }
4739 else {
4740 if(internal_branch(branch_regs[i].is32,ba[i]))
4741 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4742 }
4743 if(stubs[n][5]!=-1)
4744 {
4745 // Save PC as return address
4746 emit_movimm(stubs[n][5],EAX);
4747 emit_writeword(EAX,(int)&pcaddr);
4748 }
4749 else
4750 {
4751 // Return address depends on which way the branch goes
4752 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4753 {
4754 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4755 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4756 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4757 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4758 if(rs1[i]==0)
4759 {
4760 s1l=s2l;s1h=s2h;
4761 s2l=s2h=-1;
4762 }
4763 else if(rs2[i]==0)
4764 {
4765 s2l=s2h=-1;
4766 }
4767 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4768 s1h=s2h=-1;
4769 }
4770 assert(s1l>=0);
4771 #ifdef DESTRUCTIVE_WRITEBACK
4772 if(rs1[i]) {
4773 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4774 emit_loadreg(rs1[i],s1l);
4775 }
4776 else {
4777 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4778 emit_loadreg(rs2[i],s1l);
4779 }
4780 if(s2l>=0)
4781 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4782 emit_loadreg(rs2[i],s2l);
4783 #endif
4784 int hr=0;
4785 int addr,alt,ntaddr;
4786 while(hr<HOST_REGS)
4787 {
4788 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4789 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4790 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4791 {
4792 addr=hr++;break;
4793 }
4794 hr++;
4795 }
4796 while(hr<HOST_REGS)
4797 {
4798 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4799 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4800 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4801 {
4802 alt=hr++;break;
4803 }
4804 hr++;
4805 }
4806 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4807 {
4808 while(hr<HOST_REGS)
4809 {
4810 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4811 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4812 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4813 {
4814 ntaddr=hr;break;
4815 }
4816 hr++;
4817 }
4818 assert(hr<HOST_REGS);
4819 }
4820 if((opcode[i]&0x2f)==4) // BEQ
4821 {
4822 #ifdef HAVE_CMOV_IMM
4823 if(s1h<0) {
4824 if(s2l>=0) emit_cmp(s1l,s2l);
4825 else emit_test(s1l,s1l);
4826 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4827 }
4828 else
4829 #endif
4830 {
4831 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4832 if(s1h>=0) {
4833 if(s2h>=0) emit_cmp(s1h,s2h);
4834 else emit_test(s1h,s1h);
4835 emit_cmovne_reg(alt,addr);
4836 }
4837 if(s2l>=0) emit_cmp(s1l,s2l);
4838 else emit_test(s1l,s1l);
4839 emit_cmovne_reg(alt,addr);
4840 }
4841 }
4842 if((opcode[i]&0x2f)==5) // BNE
4843 {
4844 #ifdef HAVE_CMOV_IMM
4845 if(s1h<0) {
4846 if(s2l>=0) emit_cmp(s1l,s2l);
4847 else emit_test(s1l,s1l);
4848 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4849 }
4850 else
4851 #endif
4852 {
4853 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4854 if(s1h>=0) {
4855 if(s2h>=0) emit_cmp(s1h,s2h);
4856 else emit_test(s1h,s1h);
4857 emit_cmovne_reg(alt,addr);
4858 }
4859 if(s2l>=0) emit_cmp(s1l,s2l);
4860 else emit_test(s1l,s1l);
4861 emit_cmovne_reg(alt,addr);
4862 }
4863 }
4864 if((opcode[i]&0x2f)==6) // BLEZ
4865 {
4866 //emit_movimm(ba[i],alt);
4867 //emit_movimm(start+i*4+8,addr);
4868 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4869 emit_cmpimm(s1l,1);
4870 if(s1h>=0) emit_mov(addr,ntaddr);
4871 emit_cmovl_reg(alt,addr);
4872 if(s1h>=0) {
4873 emit_test(s1h,s1h);
4874 emit_cmovne_reg(ntaddr,addr);
4875 emit_cmovs_reg(alt,addr);
4876 }
4877 }
4878 if((opcode[i]&0x2f)==7) // BGTZ
4879 {
4880 //emit_movimm(ba[i],addr);
4881 //emit_movimm(start+i*4+8,ntaddr);
4882 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4883 emit_cmpimm(s1l,1);
4884 if(s1h>=0) emit_mov(addr,alt);
4885 emit_cmovl_reg(ntaddr,addr);
4886 if(s1h>=0) {
4887 emit_test(s1h,s1h);
4888 emit_cmovne_reg(alt,addr);
4889 emit_cmovs_reg(ntaddr,addr);
4890 }
4891 }
4892 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4893 {
4894 //emit_movimm(ba[i],alt);
4895 //emit_movimm(start+i*4+8,addr);
4896 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4897 if(s1h>=0) emit_test(s1h,s1h);
4898 else emit_test(s1l,s1l);
4899 emit_cmovs_reg(alt,addr);
4900 }
4901 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4902 {
4903 //emit_movimm(ba[i],addr);
4904 //emit_movimm(start+i*4+8,alt);
4905 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4906 if(s1h>=0) emit_test(s1h,s1h);
4907 else emit_test(s1l,s1l);
4908 emit_cmovs_reg(alt,addr);
4909 }
4910 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4911 if(source[i]&0x10000) // BC1T
4912 {
4913 //emit_movimm(ba[i],alt);
4914 //emit_movimm(start+i*4+8,addr);
4915 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4916 emit_testimm(s1l,0x800000);
4917 emit_cmovne_reg(alt,addr);
4918 }
4919 else // BC1F
4920 {
4921 //emit_movimm(ba[i],addr);
4922 //emit_movimm(start+i*4+8,alt);
4923 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4924 emit_testimm(s1l,0x800000);
4925 emit_cmovne_reg(alt,addr);
4926 }
4927 }
4928 emit_writeword(addr,(int)&pcaddr);
4929 }
4930 else
4931 if(itype[i]==RJUMP)
4932 {
4933 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4934 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4935 r=get_reg(branch_regs[i].regmap,RTEMP);
4936 }
4937 emit_writeword(r,(int)&pcaddr);
4938 }
4939 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4940 }
4941 // Update cycle count
4942 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4943 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4944 emit_call((int)cc_interrupt);
4945 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4946 if(stubs[n][6]==TAKEN) {
4947 if(internal_branch(branch_regs[i].is32,ba[i]))
4948 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4949 else if(itype[i]==RJUMP) {
4950 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4951 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4952 else
4953 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4954 }
4955 }else if(stubs[n][6]==NOTTAKEN) {
4956 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4957 else load_all_regs(branch_regs[i].regmap);
4958 }else if(stubs[n][6]==NULLDS) {
4959 // Delay slot instruction is nullified ("likely" branch)
4960 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4961 else load_all_regs(regs[i].regmap);
4962 }else{
4963 load_all_regs(branch_regs[i].regmap);
4964 }
4965 emit_jmp(stubs[n][2]); // return address
4966
4967 /* This works but uses a lot of memory...
4968 emit_readword((int)&last_count,ECX);
4969 emit_add(HOST_CCREG,ECX,EAX);
4970 emit_writeword(EAX,(int)&Count);
4971 emit_call((int)gen_interupt);
4972 emit_readword((int)&Count,HOST_CCREG);
4973 emit_readword((int)&next_interupt,EAX);
4974 emit_readword((int)&pending_exception,EBX);
4975 emit_writeword(EAX,(int)&last_count);
4976 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4977 emit_test(EBX,EBX);
4978 int jne_instr=(int)out;
4979 emit_jne(0);
4980 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4981 load_all_regs(branch_regs[i].regmap);
4982 emit_jmp(stubs[n][2]); // return address
4983 set_jump_target(jne_instr,(int)out);
4984 emit_readword((int)&pcaddr,EAX);
4985 // Call get_addr_ht instead of doing the hash table here.
4986 // This code is executed infrequently and takes up a lot of space
4987 // so smaller is better.
4988 emit_storereg(CCREG,HOST_CCREG);
4989 emit_pushreg(EAX);
4990 emit_call((int)get_addr_ht);
4991 emit_loadreg(CCREG,HOST_CCREG);
4992 emit_addimm(ESP,4,ESP);
4993 emit_jmpreg(EAX);*/
4994}
4995
4996add_to_linker(int addr,int target,int ext)
4997{
4998 link_addr[linkcount][0]=addr;
4999 link_addr[linkcount][1]=target;
5000 link_addr[linkcount][2]=ext;
5001 linkcount++;
5002}
5003
5004void ujump_assemble(int i,struct regstat *i_regs)
5005{
5006 signed char *i_regmap=i_regs->regmap;
5007 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5008 address_generation(i+1,i_regs,regs[i].regmap_entry);
5009 #ifdef REG_PREFETCH
5010 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5011 if(rt1[i]==31&&temp>=0)
5012 {
5013 int return_address=start+i*4+8;
5014 if(get_reg(branch_regs[i].regmap,31)>0)
5015 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5016 }
5017 #endif
5018 ds_assemble(i+1,i_regs);
5019 uint64_t bc_unneeded=branch_regs[i].u;
5020 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5021 bc_unneeded|=1|(1LL<<rt1[i]);
5022 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5023 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5024 bc_unneeded,bc_unneeded_upper);
5025 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5026 if(rt1[i]==31) {
5027 int rt;
5028 unsigned int return_address;
5029 assert(rt1[i+1]!=31);
5030 assert(rt2[i+1]!=31);
5031 rt=get_reg(branch_regs[i].regmap,31);
5032 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5033 //assert(rt>=0);
5034 return_address=start+i*4+8;
5035 if(rt>=0) {
5036 #ifdef USE_MINI_HT
5037 if(internal_branch(branch_regs[i].is32,return_address)) {
5038 int temp=rt+1;
5039 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5040 branch_regs[i].regmap[temp]>=0)
5041 {
5042 temp=get_reg(branch_regs[i].regmap,-1);
5043 }
5044 #ifdef HOST_TEMPREG
5045 if(temp<0) temp=HOST_TEMPREG;
5046 #endif
5047 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5048 else emit_movimm(return_address,rt);
5049 }
5050 else
5051 #endif
5052 {
5053 #ifdef REG_PREFETCH
5054 if(temp>=0)
5055 {
5056 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5057 }
5058 #endif
5059 emit_movimm(return_address,rt); // PC into link register
5060 #ifdef IMM_PREFETCH
5061 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5062 #endif
5063 }
5064 }
5065 }
5066 int cc,adj;
5067 cc=get_reg(branch_regs[i].regmap,CCREG);
5068 assert(cc==HOST_CCREG);
5069 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5070 #ifdef REG_PREFETCH
5071 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5072 #endif
5073 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5074 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5075 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5076 if(internal_branch(branch_regs[i].is32,ba[i]))
5077 assem_debug("branch: internal\n");
5078 else
5079 assem_debug("branch: external\n");
5080 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5081 ds_assemble_entry(i);
5082 }
5083 else {
5084 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5085 emit_jmp(0);
5086 }
5087}
5088
5089void rjump_assemble(int i,struct regstat *i_regs)
5090{
5091 signed char *i_regmap=i_regs->regmap;
5092 int temp;
5093 int rs,cc,adj;
5094 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5095 assert(rs>=0);
5096 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5097 // Delay slot abuse, make a copy of the branch address register
5098 temp=get_reg(branch_regs[i].regmap,RTEMP);
5099 assert(temp>=0);
5100 assert(regs[i].regmap[temp]==RTEMP);
5101 emit_mov(rs,temp);
5102 rs=temp;
5103 }
5104 address_generation(i+1,i_regs,regs[i].regmap_entry);
5105 #ifdef REG_PREFETCH
5106 if(rt1[i]==31)
5107 {
5108 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5109 int return_address=start+i*4+8;
5110 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5111 }
5112 }
5113 #endif
5114 #ifdef USE_MINI_HT
5115 if(rs1[i]==31) {
5116 int rh=get_reg(regs[i].regmap,RHASH);
5117 if(rh>=0) do_preload_rhash(rh);
5118 }
5119 #endif
5120 ds_assemble(i+1,i_regs);
5121 uint64_t bc_unneeded=branch_regs[i].u;
5122 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5123 bc_unneeded|=1|(1LL<<rt1[i]);
5124 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5125 bc_unneeded&=~(1LL<<rs1[i]);
5126 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5127 bc_unneeded,bc_unneeded_upper);
5128 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5129 if(rt1[i]!=0) {
57871462 5130 int rt,return_address;
5067f341 5131 assert(rt1[i+1]!=rt1[i]);
5132 assert(rt2[i+1]!=rt1[i]);
5133 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5134 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5135 assert(rt>=0);
5136 return_address=start+i*4+8;
5137 #ifdef REG_PREFETCH
5138 if(temp>=0)
5139 {
5140 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5141 }
5142 #endif
5143 emit_movimm(return_address,rt); // PC into link register
5144 #ifdef IMM_PREFETCH
5145 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5146 #endif
5147 }
5148 cc=get_reg(branch_regs[i].regmap,CCREG);
5149 assert(cc==HOST_CCREG);
5150 #ifdef USE_MINI_HT
5151 int rh=get_reg(branch_regs[i].regmap,RHASH);
5152 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5153 if(rs1[i]==31) {
5154 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5155 do_preload_rhtbl(ht);
5156 do_rhash(rs,rh);
5157 }
5158 #endif
5159 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5160 #ifdef DESTRUCTIVE_WRITEBACK
5161 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5162 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5163 emit_loadreg(rs1[i],rs);
5164 }
5165 }
5166 #endif
5167 #ifdef REG_PREFETCH
5168 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5169 #endif
5170 #ifdef USE_MINI_HT
5171 if(rs1[i]==31) {
5172 do_miniht_load(ht,rh);
5173 }
5174 #endif
5175 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5176 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5177 //assert(adj==0);
5178 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5179 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5180 emit_jns(0);
5181 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5182 #ifdef USE_MINI_HT
5183 if(rs1[i]==31) {
5184 do_miniht_jump(rs,rh,ht);
5185 }
5186 else
5187 #endif
5188 {
5189 //if(rs!=EAX) emit_mov(rs,EAX);
5190 //emit_jmp((int)jump_vaddr_eax);
5191 emit_jmp(jump_vaddr_reg[rs]);
5192 }
5193 /* Check hash table
5194 temp=!rs;
5195 emit_mov(rs,temp);
5196 emit_shrimm(rs,16,rs);
5197 emit_xor(temp,rs,rs);
5198 emit_movzwl_reg(rs,rs);
5199 emit_shlimm(rs,4,rs);
5200 emit_cmpmem_indexed((int)hash_table,rs,temp);
5201 emit_jne((int)out+14);
5202 emit_readword_indexed((int)hash_table+4,rs,rs);
5203 emit_jmpreg(rs);
5204 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5205 emit_addimm_no_flags(8,rs);
5206 emit_jeq((int)out-17);
5207 // No hit on hash table, call compiler
5208 emit_pushreg(temp);
5209//DEBUG >
5210#ifdef DEBUG_CYCLE_COUNT
5211 emit_readword((int)&last_count,ECX);
5212 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5213 emit_readword((int)&next_interupt,ECX);
5214 emit_writeword(HOST_CCREG,(int)&Count);
5215 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5216 emit_writeword(ECX,(int)&last_count);
5217#endif
5218//DEBUG <
5219 emit_storereg(CCREG,HOST_CCREG);
5220 emit_call((int)get_addr);
5221 emit_loadreg(CCREG,HOST_CCREG);
5222 emit_addimm(ESP,4,ESP);
5223 emit_jmpreg(EAX);*/
5224 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5225 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5226 #endif
5227}
5228
5229void cjump_assemble(int i,struct regstat *i_regs)
5230{
5231 signed char *i_regmap=i_regs->regmap;
5232 int cc;
5233 int match;
5234 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5235 assem_debug("match=%d\n",match);
5236 int s1h,s1l,s2h,s2l;
5237 int prev_cop1_usable=cop1_usable;
5238 int unconditional=0,nop=0;
5239 int only32=0;
5240 int ooo=1;
5241 int invert=0;
5242 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5243 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5244 if(likely[i]) ooo=0;
5245 if(!match) invert=1;
5246 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5247 if(i>(ba[i]-start)>>2) invert=1;
5248 #endif
5249
5250 if(ooo)
5251 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5252 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5253 {
5254 // Write-after-read dependency prevents out of order execution
5255 // First test branch condition, then execute delay slot, then branch
5256 ooo=0;
5257 }
5258
5259 if(ooo) {
5260 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5261 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5262 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5263 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5264 }
5265 else {
5266 s1l=get_reg(i_regmap,rs1[i]);
5267 s1h=get_reg(i_regmap,rs1[i]|64);
5268 s2l=get_reg(i_regmap,rs2[i]);
5269 s2h=get_reg(i_regmap,rs2[i]|64);
5270 }
5271 if(rs1[i]==0&&rs2[i]==0)
5272 {
5273 if(opcode[i]&1) nop=1;
5274 else unconditional=1;
5275 //assert(opcode[i]!=5);
5276 //assert(opcode[i]!=7);
5277 //assert(opcode[i]!=0x15);
5278 //assert(opcode[i]!=0x17);
5279 }
5280 else if(rs1[i]==0)
5281 {
5282 s1l=s2l;s1h=s2h;
5283 s2l=s2h=-1;
5284 only32=(regs[i].was32>>rs2[i])&1;
5285 }
5286 else if(rs2[i]==0)
5287 {
5288 s2l=s2h=-1;
5289 only32=(regs[i].was32>>rs1[i])&1;
5290 }
5291 else {
5292 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5293 }
5294
5295 if(ooo) {
5296 // Out of order execution (delay slot first)
5297 //printf("OOOE\n");
5298 address_generation(i+1,i_regs,regs[i].regmap_entry);
5299 ds_assemble(i+1,i_regs);
5300 int adj;
5301 uint64_t bc_unneeded=branch_regs[i].u;
5302 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5303 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5304 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5305 bc_unneeded|=1;
5306 bc_unneeded_upper|=1;
5307 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5308 bc_unneeded,bc_unneeded_upper);
5309 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5310 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5311 cc=get_reg(branch_regs[i].regmap,CCREG);
5312 assert(cc==HOST_CCREG);
5313 if(unconditional)
5314 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5315 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5316 //assem_debug("cycle count (adj)\n");
5317 if(unconditional) {
5318 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5319 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5320 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5321 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5322 if(internal)
5323 assem_debug("branch: internal\n");
5324 else
5325 assem_debug("branch: external\n");
5326 if(internal&&is_ds[(ba[i]-start)>>2]) {
5327 ds_assemble_entry(i);
5328 }
5329 else {
5330 add_to_linker((int)out,ba[i],internal);
5331 emit_jmp(0);
5332 }
5333 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5334 if(((u_int)out)&7) emit_addnop(0);
5335 #endif
5336 }
5337 }
5338 else if(nop) {
5339 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5340 int jaddr=(int)out;
5341 emit_jns(0);
5342 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5343 }
5344 else {
5345 int taken=0,nottaken=0,nottaken1=0;
5346 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5347 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5348 if(!only32)
5349 {
5350 assert(s1h>=0);
5351 if(opcode[i]==4) // BEQ
5352 {
5353 if(s2h>=0) emit_cmp(s1h,s2h);
5354 else emit_test(s1h,s1h);
5355 nottaken1=(int)out;
5356 emit_jne(1);
5357 }
5358 if(opcode[i]==5) // BNE
5359 {
5360 if(s2h>=0) emit_cmp(s1h,s2h);
5361 else emit_test(s1h,s1h);
5362 if(invert) taken=(int)out;
5363 else add_to_linker((int)out,ba[i],internal);
5364 emit_jne(0);
5365 }
5366 if(opcode[i]==6) // BLEZ
5367 {
5368 emit_test(s1h,s1h);
5369 if(invert) taken=(int)out;
5370 else add_to_linker((int)out,ba[i],internal);
5371 emit_js(0);
5372 nottaken1=(int)out;
5373 emit_jne(1);
5374 }
5375 if(opcode[i]==7) // BGTZ
5376 {
5377 emit_test(s1h,s1h);
5378 nottaken1=(int)out;
5379 emit_js(1);
5380 if(invert) taken=(int)out;
5381 else add_to_linker((int)out,ba[i],internal);
5382 emit_jne(0);
5383 }
5384 } // if(!only32)
5385
5386 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5387 assert(s1l>=0);
5388 if(opcode[i]==4) // BEQ
5389 {
5390 if(s2l>=0) emit_cmp(s1l,s2l);
5391 else emit_test(s1l,s1l);
5392 if(invert){
5393 nottaken=(int)out;
5394 emit_jne(1);
5395 }else{
5396 add_to_linker((int)out,ba[i],internal);
5397 emit_jeq(0);
5398 }
5399 }
5400 if(opcode[i]==5) // BNE
5401 {
5402 if(s2l>=0) emit_cmp(s1l,s2l);
5403 else emit_test(s1l,s1l);
5404 if(invert){
5405 nottaken=(int)out;
5406 emit_jeq(1);
5407 }else{
5408 add_to_linker((int)out,ba[i],internal);
5409 emit_jne(0);
5410 }
5411 }
5412 if(opcode[i]==6) // BLEZ
5413 {
5414 emit_cmpimm(s1l,1);
5415 if(invert){
5416 nottaken=(int)out;
5417 emit_jge(1);
5418 }else{
5419 add_to_linker((int)out,ba[i],internal);
5420 emit_jl(0);
5421 }
5422 }
5423 if(opcode[i]==7) // BGTZ
5424 {
5425 emit_cmpimm(s1l,1);
5426 if(invert){
5427 nottaken=(int)out;
5428 emit_jl(1);
5429 }else{
5430 add_to_linker((int)out,ba[i],internal);
5431 emit_jge(0);
5432 }
5433 }
5434 if(invert) {
5435 if(taken) set_jump_target(taken,(int)out);
5436 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5437 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5438 if(adj) {
5439 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5440 add_to_linker((int)out,ba[i],internal);
5441 }else{
5442 emit_addnop(13);
5443 add_to_linker((int)out,ba[i],internal*2);
5444 }
5445 emit_jmp(0);
5446 }else
5447 #endif
5448 {
5449 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5450 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5451 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5452 if(internal)
5453 assem_debug("branch: internal\n");
5454 else
5455 assem_debug("branch: external\n");
5456 if(internal&&is_ds[(ba[i]-start)>>2]) {
5457 ds_assemble_entry(i);
5458 }
5459 else {
5460 add_to_linker((int)out,ba[i],internal);
5461 emit_jmp(0);
5462 }
5463 }
5464 set_jump_target(nottaken,(int)out);
5465 }
5466
5467 if(nottaken1) set_jump_target(nottaken1,(int)out);
5468 if(adj) {
5469 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5470 }
5471 } // (!unconditional)
5472 } // if(ooo)
5473 else
5474 {
5475 // In-order execution (branch first)
5476 //if(likely[i]) printf("IOL\n");
5477 //else
5478 //printf("IOE\n");
5479 int taken=0,nottaken=0,nottaken1=0;
5480 if(!unconditional&&!nop) {
5481 if(!only32)
5482 {
5483 assert(s1h>=0);
5484 if((opcode[i]&0x2f)==4) // BEQ
5485 {
5486 if(s2h>=0) emit_cmp(s1h,s2h);
5487 else emit_test(s1h,s1h);
5488 nottaken1=(int)out;
5489 emit_jne(2);
5490 }
5491 if((opcode[i]&0x2f)==5) // BNE
5492 {
5493 if(s2h>=0) emit_cmp(s1h,s2h);
5494 else emit_test(s1h,s1h);
5495 taken=(int)out;
5496 emit_jne(1);
5497 }
5498 if((opcode[i]&0x2f)==6) // BLEZ
5499 {
5500 emit_test(s1h,s1h);
5501 taken=(int)out;
5502 emit_js(1);
5503 nottaken1=(int)out;
5504 emit_jne(2);
5505 }
5506 if((opcode[i]&0x2f)==7) // BGTZ
5507 {
5508 emit_test(s1h,s1h);
5509 nottaken1=(int)out;
5510 emit_js(2);
5511 taken=(int)out;
5512 emit_jne(1);
5513 }
5514 } // if(!only32)
5515
5516 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5517 assert(s1l>=0);
5518 if((opcode[i]&0x2f)==4) // BEQ
5519 {
5520 if(s2l>=0) emit_cmp(s1l,s2l);
5521 else emit_test(s1l,s1l);
5522 nottaken=(int)out;
5523 emit_jne(2);
5524 }
5525 if((opcode[i]&0x2f)==5) // BNE
5526 {
5527 if(s2l>=0) emit_cmp(s1l,s2l);
5528 else emit_test(s1l,s1l);
5529 nottaken=(int)out;
5530 emit_jeq(2);
5531 }
5532 if((opcode[i]&0x2f)==6) // BLEZ
5533 {
5534 emit_cmpimm(s1l,1);
5535 nottaken=(int)out;
5536 emit_jge(2);
5537 }
5538 if((opcode[i]&0x2f)==7) // BGTZ
5539 {
5540 emit_cmpimm(s1l,1);
5541 nottaken=(int)out;
5542 emit_jl(2);
5543 }
5544 } // if(!unconditional)
5545 int adj;
5546 uint64_t ds_unneeded=branch_regs[i].u;
5547 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5548 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5549 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5550 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5551 ds_unneeded|=1;
5552 ds_unneeded_upper|=1;
5553 // branch taken
5554 if(!nop) {
5555 if(taken) set_jump_target(taken,(int)out);
5556 assem_debug("1:\n");
5557 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5558 ds_unneeded,ds_unneeded_upper);
5559 // load regs
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5561 address_generation(i+1,&branch_regs[i],0);
5562 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5563 ds_assemble(i+1,&branch_regs[i]);
5564 cc=get_reg(branch_regs[i].regmap,CCREG);
5565 if(cc==-1) {
5566 emit_loadreg(CCREG,cc=HOST_CCREG);
5567 // CHECK: Is the following instruction (fall thru) allocated ok?
5568 }
5569 assert(cc==HOST_CCREG);
5570 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5571 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5572 assem_debug("cycle count (adj)\n");
5573 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5574 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5575 if(internal)
5576 assem_debug("branch: internal\n");
5577 else
5578 assem_debug("branch: external\n");
5579 if(internal&&is_ds[(ba[i]-start)>>2]) {
5580 ds_assemble_entry(i);
5581 }
5582 else {
5583 add_to_linker((int)out,ba[i],internal);
5584 emit_jmp(0);
5585 }
5586 }
5587 // branch not taken
5588 cop1_usable=prev_cop1_usable;
5589 if(!unconditional) {
5590 if(nottaken1) set_jump_target(nottaken1,(int)out);
5591 set_jump_target(nottaken,(int)out);
5592 assem_debug("2:\n");
5593 if(!likely[i]) {
5594 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5595 ds_unneeded,ds_unneeded_upper);
5596 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5597 address_generation(i+1,&branch_regs[i],0);
5598 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5599 ds_assemble(i+1,&branch_regs[i]);
5600 }
5601 cc=get_reg(branch_regs[i].regmap,CCREG);
5602 if(cc==-1&&!likely[i]) {
5603 // Cycle count isn't in a register, temporarily load it then write it out
5604 emit_loadreg(CCREG,HOST_CCREG);
5605 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5606 int jaddr=(int)out;
5607 emit_jns(0);
5608 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5609 emit_storereg(CCREG,HOST_CCREG);
5610 }
5611 else{
5612 cc=get_reg(i_regmap,CCREG);
5613 assert(cc==HOST_CCREG);
5614 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5615 int jaddr=(int)out;
5616 emit_jns(0);
5617 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5618 }
5619 }
5620 }
5621}
5622
5623void sjump_assemble(int i,struct regstat *i_regs)
5624{
5625 signed char *i_regmap=i_regs->regmap;
5626 int cc;
5627 int match;
5628 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5629 assem_debug("smatch=%d\n",match);
5630 int s1h,s1l;
5631 int prev_cop1_usable=cop1_usable;
5632 int unconditional=0,nevertaken=0;
5633 int only32=0;
5634 int ooo=1;
5635 int invert=0;
5636 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5637 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5638 if(likely[i]) ooo=0;
5639 if(!match) invert=1;
5640 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5641 if(i>(ba[i]-start)>>2) invert=1;
5642 #endif
5643
5644 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5645 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5646
68b3faee 5647 if(ooo) {
57871462 5648 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
68b3faee 5649 {
5650 // Write-after-read dependency prevents out of order execution
5651 // First test branch condition, then execute delay slot, then branch
5652 ooo=0;
5653 }
5654 if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))
5655 // BxxZAL $ra is available to delay insn, so do it in order
5656 ooo=0;
57871462 5657 }
57871462 5658
5659 if(ooo) {
5660 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5661 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5662 }
5663 else {
5664 s1l=get_reg(i_regmap,rs1[i]);
5665 s1h=get_reg(i_regmap,rs1[i]|64);
5666 }
5667 if(rs1[i]==0)
5668 {
5669 if(opcode2[i]&1) unconditional=1;
5670 else nevertaken=1;
5671 // These are never taken (r0 is never less than zero)
5672 //assert(opcode2[i]!=0);
5673 //assert(opcode2[i]!=2);
5674 //assert(opcode2[i]!=0x10);
5675 //assert(opcode2[i]!=0x12);
5676 }
5677 else {
5678 only32=(regs[i].was32>>rs1[i])&1;
5679 }
5680
5681 if(ooo) {
5682 // Out of order execution (delay slot first)
5683 //printf("OOOE\n");
5684 address_generation(i+1,i_regs,regs[i].regmap_entry);
5685 ds_assemble(i+1,i_regs);
5686 int adj;
5687 uint64_t bc_unneeded=branch_regs[i].u;
5688 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5689 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5690 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5691 bc_unneeded|=1;
5692 bc_unneeded_upper|=1;
5693 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5694 bc_unneeded,bc_unneeded_upper);
5695 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5696 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5697 if(rt1[i]==31) {
5698 int rt,return_address;
57871462 5699 rt=get_reg(branch_regs[i].regmap,31);
5700 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5701 if(rt>=0) {
5702 // Save the PC even if the branch is not taken
5703 return_address=start+i*4+8;
5704 emit_movimm(return_address,rt); // PC into link register
5705 #ifdef IMM_PREFETCH
5706 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5707 #endif
5708 }
5709 }
5710 cc=get_reg(branch_regs[i].regmap,CCREG);
5711 assert(cc==HOST_CCREG);
5712 if(unconditional)
5713 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5714 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5715 assem_debug("cycle count (adj)\n");
5716 if(unconditional) {
5717 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5718 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5719 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5720 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5721 if(internal)
5722 assem_debug("branch: internal\n");
5723 else
5724 assem_debug("branch: external\n");
5725 if(internal&&is_ds[(ba[i]-start)>>2]) {
5726 ds_assemble_entry(i);
5727 }
5728 else {
5729 add_to_linker((int)out,ba[i],internal);
5730 emit_jmp(0);
5731 }
5732 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5733 if(((u_int)out)&7) emit_addnop(0);
5734 #endif
5735 }
5736 }
5737 else if(nevertaken) {
5738 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5739 int jaddr=(int)out;
5740 emit_jns(0);
5741 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5742 }
5743 else {
5744 int nottaken=0;
5745 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5746 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5747 if(!only32)
5748 {
5749 assert(s1h>=0);
df894a3a 5750 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5751 {
5752 emit_test(s1h,s1h);
5753 if(invert){
5754 nottaken=(int)out;
5755 emit_jns(1);
5756 }else{
5757 add_to_linker((int)out,ba[i],internal);
5758 emit_js(0);
5759 }
5760 }
df894a3a 5761 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5762 {
5763 emit_test(s1h,s1h);
5764 if(invert){
5765 nottaken=(int)out;
5766 emit_js(1);
5767 }else{
5768 add_to_linker((int)out,ba[i],internal);
5769 emit_jns(0);
5770 }
5771 }
5772 } // if(!only32)
5773 else
5774 {
5775 assert(s1l>=0);
df894a3a 5776 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5777 {
5778 emit_test(s1l,s1l);
5779 if(invert){
5780 nottaken=(int)out;
5781 emit_jns(1);
5782 }else{
5783 add_to_linker((int)out,ba[i],internal);
5784 emit_js(0);
5785 }
5786 }
df894a3a 5787 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5788 {
5789 emit_test(s1l,s1l);
5790 if(invert){
5791 nottaken=(int)out;
5792 emit_js(1);
5793 }else{
5794 add_to_linker((int)out,ba[i],internal);
5795 emit_jns(0);
5796 }
5797 }
5798 } // if(!only32)
5799
5800 if(invert) {
5801 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5802 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5803 if(adj) {
5804 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5805 add_to_linker((int)out,ba[i],internal);
5806 }else{
5807 emit_addnop(13);
5808 add_to_linker((int)out,ba[i],internal*2);
5809 }
5810 emit_jmp(0);
5811 }else
5812 #endif
5813 {
5814 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5815 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5816 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5817 if(internal)
5818 assem_debug("branch: internal\n");
5819 else
5820 assem_debug("branch: external\n");
5821 if(internal&&is_ds[(ba[i]-start)>>2]) {
5822 ds_assemble_entry(i);
5823 }
5824 else {
5825 add_to_linker((int)out,ba[i],internal);
5826 emit_jmp(0);
5827 }
5828 }
5829 set_jump_target(nottaken,(int)out);
5830 }
5831
5832 if(adj) {
5833 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5834 }
5835 } // (!unconditional)
5836 } // if(ooo)
5837 else
5838 {
5839 // In-order execution (branch first)
5840 //printf("IOE\n");
5841 int nottaken=0;
a6491170 5842 if(rt1[i]==31) {
5843 int rt,return_address;
a6491170 5844 rt=get_reg(branch_regs[i].regmap,31);
5845 if(rt>=0) {
5846 // Save the PC even if the branch is not taken
5847 return_address=start+i*4+8;
5848 emit_movimm(return_address,rt); // PC into link register
5849 #ifdef IMM_PREFETCH
5850 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5851 #endif
5852 }
5853 }
57871462 5854 if(!unconditional) {
5855 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5856 if(!only32)
5857 {
5858 assert(s1h>=0);
a6491170 5859 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5860 {
5861 emit_test(s1h,s1h);
5862 nottaken=(int)out;
5863 emit_jns(1);
5864 }
a6491170 5865 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5866 {
5867 emit_test(s1h,s1h);
5868 nottaken=(int)out;
5869 emit_js(1);
5870 }
5871 } // if(!only32)
5872 else
5873 {
5874 assert(s1l>=0);
a6491170 5875 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5876 {
5877 emit_test(s1l,s1l);
5878 nottaken=(int)out;
5879 emit_jns(1);
5880 }
a6491170 5881 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5882 {
5883 emit_test(s1l,s1l);
5884 nottaken=(int)out;
5885 emit_js(1);
5886 }
5887 }
5888 } // if(!unconditional)
5889 int adj;
5890 uint64_t ds_unneeded=branch_regs[i].u;
5891 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5892 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5893 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5894 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5895 ds_unneeded|=1;
5896 ds_unneeded_upper|=1;
5897 // branch taken
5898 if(!nevertaken) {
5899 //assem_debug("1:\n");
5900 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5901 ds_unneeded,ds_unneeded_upper);
5902 // load regs
5903 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5904 address_generation(i+1,&branch_regs[i],0);
5905 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5906 ds_assemble(i+1,&branch_regs[i]);
5907 cc=get_reg(branch_regs[i].regmap,CCREG);
5908 if(cc==-1) {
5909 emit_loadreg(CCREG,cc=HOST_CCREG);
5910 // CHECK: Is the following instruction (fall thru) allocated ok?
5911 }
5912 assert(cc==HOST_CCREG);
5913 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5914 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5915 assem_debug("cycle count (adj)\n");
5916 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5917 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5918 if(internal)
5919 assem_debug("branch: internal\n");
5920 else
5921 assem_debug("branch: external\n");
5922 if(internal&&is_ds[(ba[i]-start)>>2]) {
5923 ds_assemble_entry(i);
5924 }
5925 else {
5926 add_to_linker((int)out,ba[i],internal);
5927 emit_jmp(0);
5928 }
5929 }
5930 // branch not taken
5931 cop1_usable=prev_cop1_usable;
5932 if(!unconditional) {
5933 set_jump_target(nottaken,(int)out);
5934 assem_debug("1:\n");
5935 if(!likely[i]) {
5936 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5937 ds_unneeded,ds_unneeded_upper);
5938 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5939 address_generation(i+1,&branch_regs[i],0);
5940 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5941 ds_assemble(i+1,&branch_regs[i]);
5942 }
5943 cc=get_reg(branch_regs[i].regmap,CCREG);
5944 if(cc==-1&&!likely[i]) {
5945 // Cycle count isn't in a register, temporarily load it then write it out
5946 emit_loadreg(CCREG,HOST_CCREG);
5947 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5948 int jaddr=(int)out;
5949 emit_jns(0);
5950 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5951 emit_storereg(CCREG,HOST_CCREG);
5952 }
5953 else{
5954 cc=get_reg(i_regmap,CCREG);
5955 assert(cc==HOST_CCREG);
5956 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5957 int jaddr=(int)out;
5958 emit_jns(0);
5959 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5960 }
5961 }
5962 }
5963}
5964
5965void fjump_assemble(int i,struct regstat *i_regs)
5966{
5967 signed char *i_regmap=i_regs->regmap;
5968 int cc;
5969 int match;
5970 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5971 assem_debug("fmatch=%d\n",match);
5972 int fs,cs;
5973 int eaddr;
5974 int ooo=1;
5975 int invert=0;
5976 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5977 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5978 if(likely[i]) ooo=0;
5979 if(!match) invert=1;
5980 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5981 if(i>(ba[i]-start)>>2) invert=1;
5982 #endif
5983
5984 if(ooo)
5985 if(itype[i+1]==FCOMP)
5986 {
5987 // Write-after-read dependency prevents out of order execution
5988 // First test branch condition, then execute delay slot, then branch
5989 ooo=0;
5990 }
5991
5992 if(ooo) {
5993 fs=get_reg(branch_regs[i].regmap,FSREG);
5994 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5995 }
5996 else {
5997 fs=get_reg(i_regmap,FSREG);
5998 }
5999
6000 // Check cop1 unusable
6001 if(!cop1_usable) {
6002 cs=get_reg(i_regmap,CSREG);
6003 assert(cs>=0);
6004 emit_testimm(cs,0x20000000);
6005 eaddr=(int)out;
6006 emit_jeq(0);
6007 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6008 cop1_usable=1;
6009 }
6010
6011 if(ooo) {
6012 // Out of order execution (delay slot first)
6013 //printf("OOOE\n");
6014 ds_assemble(i+1,i_regs);
6015 int adj;
6016 uint64_t bc_unneeded=branch_regs[i].u;
6017 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6018 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6019 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6020 bc_unneeded|=1;
6021 bc_unneeded_upper|=1;
6022 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6023 bc_unneeded,bc_unneeded_upper);
6024 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6025 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6026 cc=get_reg(branch_regs[i].regmap,CCREG);
6027 assert(cc==HOST_CCREG);
6028 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6029 assem_debug("cycle count (adj)\n");
6030 if(1) {
6031 int nottaken=0;
6032 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6033 if(1) {
6034 assert(fs>=0);
6035 emit_testimm(fs,0x800000);
6036 if(source[i]&0x10000) // BC1T
6037 {
6038 if(invert){
6039 nottaken=(int)out;
6040 emit_jeq(1);
6041 }else{
6042 add_to_linker((int)out,ba[i],internal);
6043 emit_jne(0);
6044 }
6045 }
6046 else // BC1F
6047 if(invert){
6048 nottaken=(int)out;
6049 emit_jne(1);
6050 }else{
6051 add_to_linker((int)out,ba[i],internal);
6052 emit_jeq(0);
6053 }
6054 {
6055 }
6056 } // if(!only32)
6057
6058 if(invert) {
6059 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6060 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6061 else if(match) emit_addnop(13);
6062 #endif
6063 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6064 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6065 if(internal)
6066 assem_debug("branch: internal\n");
6067 else
6068 assem_debug("branch: external\n");
6069 if(internal&&is_ds[(ba[i]-start)>>2]) {
6070 ds_assemble_entry(i);
6071 }
6072 else {
6073 add_to_linker((int)out,ba[i],internal);
6074 emit_jmp(0);
6075 }
6076 set_jump_target(nottaken,(int)out);
6077 }
6078
6079 if(adj) {
6080 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6081 }
6082 } // (!unconditional)
6083 } // if(ooo)
6084 else
6085 {
6086 // In-order execution (branch first)
6087 //printf("IOE\n");
6088 int nottaken=0;
6089 if(1) {
6090 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6091 if(1) {
6092 assert(fs>=0);
6093 emit_testimm(fs,0x800000);
6094 if(source[i]&0x10000) // BC1T
6095 {
6096 nottaken=(int)out;
6097 emit_jeq(1);
6098 }
6099 else // BC1F
6100 {
6101 nottaken=(int)out;
6102 emit_jne(1);
6103 }
6104 }
6105 } // if(!unconditional)
6106 int adj;
6107 uint64_t ds_unneeded=branch_regs[i].u;
6108 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6109 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6110 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6111 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6112 ds_unneeded|=1;
6113 ds_unneeded_upper|=1;
6114 // branch taken
6115 //assem_debug("1:\n");
6116 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6117 ds_unneeded,ds_unneeded_upper);
6118 // load regs
6119 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6120 address_generation(i+1,&branch_regs[i],0);
6121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6122 ds_assemble(i+1,&branch_regs[i]);
6123 cc=get_reg(branch_regs[i].regmap,CCREG);
6124 if(cc==-1) {
6125 emit_loadreg(CCREG,cc=HOST_CCREG);
6126 // CHECK: Is the following instruction (fall thru) allocated ok?
6127 }
6128 assert(cc==HOST_CCREG);
6129 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6130 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6131 assem_debug("cycle count (adj)\n");
6132 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6133 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6134 if(internal)
6135 assem_debug("branch: internal\n");
6136 else
6137 assem_debug("branch: external\n");
6138 if(internal&&is_ds[(ba[i]-start)>>2]) {
6139 ds_assemble_entry(i);
6140 }
6141 else {
6142 add_to_linker((int)out,ba[i],internal);
6143 emit_jmp(0);
6144 }
6145
6146 // branch not taken
6147 if(1) { // <- FIXME (don't need this)
6148 set_jump_target(nottaken,(int)out);
6149 assem_debug("1:\n");
6150 if(!likely[i]) {
6151 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6152 ds_unneeded,ds_unneeded_upper);
6153 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6154 address_generation(i+1,&branch_regs[i],0);
6155 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6156 ds_assemble(i+1,&branch_regs[i]);
6157 }
6158 cc=get_reg(branch_regs[i].regmap,CCREG);
6159 if(cc==-1&&!likely[i]) {
6160 // Cycle count isn't in a register, temporarily load it then write it out
6161 emit_loadreg(CCREG,HOST_CCREG);
6162 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6163 int jaddr=(int)out;
6164 emit_jns(0);
6165 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6166 emit_storereg(CCREG,HOST_CCREG);
6167 }
6168 else{
6169 cc=get_reg(i_regmap,CCREG);
6170 assert(cc==HOST_CCREG);
6171 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6172 int jaddr=(int)out;
6173 emit_jns(0);
6174 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6175 }
6176 }
6177 }
6178}
6179
6180static void pagespan_assemble(int i,struct regstat *i_regs)
6181{
6182 int s1l=get_reg(i_regs->regmap,rs1[i]);
6183 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6184 int s2l=get_reg(i_regs->regmap,rs2[i]);
6185 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6186 void *nt_branch=NULL;
6187 int taken=0;
6188 int nottaken=0;
6189 int unconditional=0;
6190 if(rs1[i]==0)
6191 {
6192 s1l=s2l;s1h=s2h;
6193 s2l=s2h=-1;
6194 }
6195 else if(rs2[i]==0)
6196 {
6197 s2l=s2h=-1;
6198 }
6199 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6200 s1h=s2h=-1;
6201 }
6202 int hr=0;
6203 int addr,alt,ntaddr;
6204 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6205 else {
6206 while(hr<HOST_REGS)
6207 {
6208 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6209 (i_regs->regmap[hr]&63)!=rs1[i] &&
6210 (i_regs->regmap[hr]&63)!=rs2[i] )
6211 {
6212 addr=hr++;break;
6213 }
6214 hr++;
6215 }
6216 }
6217 while(hr<HOST_REGS)
6218 {
6219 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6220 (i_regs->regmap[hr]&63)!=rs1[i] &&
6221 (i_regs->regmap[hr]&63)!=rs2[i] )
6222 {
6223 alt=hr++;break;
6224 }
6225 hr++;
6226 }
6227 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6228 {
6229 while(hr<HOST_REGS)
6230 {
6231 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6232 (i_regs->regmap[hr]&63)!=rs1[i] &&
6233 (i_regs->regmap[hr]&63)!=rs2[i] )
6234 {
6235 ntaddr=hr;break;
6236 }
6237 hr++;
6238 }
6239 }
6240 assert(hr<HOST_REGS);
6241 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6242 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6243 }
6244 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6245 if(opcode[i]==2) // J
6246 {
6247 unconditional=1;
6248 }
6249 if(opcode[i]==3) // JAL
6250 {
6251 // TODO: mini_ht
6252 int rt=get_reg(i_regs->regmap,31);
6253 emit_movimm(start+i*4+8,rt);
6254 unconditional=1;
6255 }
6256 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6257 {
6258 emit_mov(s1l,addr);
6259 if(opcode2[i]==9) // JALR
6260 {
5067f341 6261 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6262 emit_movimm(start+i*4+8,rt);
6263 }
6264 }
6265 if((opcode[i]&0x3f)==4) // BEQ
6266 {
6267 if(rs1[i]==rs2[i])
6268 {
6269 unconditional=1;
6270 }
6271 else
6272 #ifdef HAVE_CMOV_IMM
6273 if(s1h<0) {
6274 if(s2l>=0) emit_cmp(s1l,s2l);
6275 else emit_test(s1l,s1l);
6276 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6277 }
6278 else
6279 #endif
6280 {
6281 assert(s1l>=0);
6282 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6283 if(s1h>=0) {
6284 if(s2h>=0) emit_cmp(s1h,s2h);
6285 else emit_test(s1h,s1h);
6286 emit_cmovne_reg(alt,addr);
6287 }
6288 if(s2l>=0) emit_cmp(s1l,s2l);
6289 else emit_test(s1l,s1l);
6290 emit_cmovne_reg(alt,addr);
6291 }
6292 }
6293 if((opcode[i]&0x3f)==5) // BNE
6294 {
6295 #ifdef HAVE_CMOV_IMM
6296 if(s1h<0) {
6297 if(s2l>=0) emit_cmp(s1l,s2l);
6298 else emit_test(s1l,s1l);
6299 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6300 }
6301 else
6302 #endif
6303 {
6304 assert(s1l>=0);
6305 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6306 if(s1h>=0) {
6307 if(s2h>=0) emit_cmp(s1h,s2h);
6308 else emit_test(s1h,s1h);
6309 emit_cmovne_reg(alt,addr);
6310 }
6311 if(s2l>=0) emit_cmp(s1l,s2l);
6312 else emit_test(s1l,s1l);
6313 emit_cmovne_reg(alt,addr);
6314 }
6315 }
6316 if((opcode[i]&0x3f)==0x14) // BEQL
6317 {
6318 if(s1h>=0) {
6319 if(s2h>=0) emit_cmp(s1h,s2h);
6320 else emit_test(s1h,s1h);
6321 nottaken=(int)out;
6322 emit_jne(0);
6323 }
6324 if(s2l>=0) emit_cmp(s1l,s2l);
6325 else emit_test(s1l,s1l);
6326 if(nottaken) set_jump_target(nottaken,(int)out);
6327 nottaken=(int)out;
6328 emit_jne(0);
6329 }
6330 if((opcode[i]&0x3f)==0x15) // BNEL
6331 {
6332 if(s1h>=0) {
6333 if(s2h>=0) emit_cmp(s1h,s2h);
6334 else emit_test(s1h,s1h);
6335 taken=(int)out;
6336 emit_jne(0);
6337 }
6338 if(s2l>=0) emit_cmp(s1l,s2l);
6339 else emit_test(s1l,s1l);
6340 nottaken=(int)out;
6341 emit_jeq(0);
6342 if(taken) set_jump_target(taken,(int)out);
6343 }
6344 if((opcode[i]&0x3f)==6) // BLEZ
6345 {
6346 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6347 emit_cmpimm(s1l,1);
6348 if(s1h>=0) emit_mov(addr,ntaddr);
6349 emit_cmovl_reg(alt,addr);
6350 if(s1h>=0) {
6351 emit_test(s1h,s1h);
6352 emit_cmovne_reg(ntaddr,addr);
6353 emit_cmovs_reg(alt,addr);
6354 }
6355 }
6356 if((opcode[i]&0x3f)==7) // BGTZ
6357 {
6358 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6359 emit_cmpimm(s1l,1);
6360 if(s1h>=0) emit_mov(addr,alt);
6361 emit_cmovl_reg(ntaddr,addr);
6362 if(s1h>=0) {
6363 emit_test(s1h,s1h);
6364 emit_cmovne_reg(alt,addr);
6365 emit_cmovs_reg(ntaddr,addr);
6366 }
6367 }
6368 if((opcode[i]&0x3f)==0x16) // BLEZL
6369 {
6370 assert((opcode[i]&0x3f)!=0x16);
6371 }
6372 if((opcode[i]&0x3f)==0x17) // BGTZL
6373 {
6374 assert((opcode[i]&0x3f)!=0x17);
6375 }
6376 assert(opcode[i]!=1); // BLTZ/BGEZ
6377
6378 //FIXME: Check CSREG
6379 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6380 if((source[i]&0x30000)==0) // BC1F
6381 {
6382 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6383 emit_testimm(s1l,0x800000);
6384 emit_cmovne_reg(alt,addr);
6385 }
6386 if((source[i]&0x30000)==0x10000) // BC1T
6387 {
6388 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6389 emit_testimm(s1l,0x800000);
6390 emit_cmovne_reg(alt,addr);
6391 }
6392 if((source[i]&0x30000)==0x20000) // BC1FL
6393 {
6394 emit_testimm(s1l,0x800000);
6395 nottaken=(int)out;
6396 emit_jne(0);
6397 }
6398 if((source[i]&0x30000)==0x30000) // BC1TL
6399 {
6400 emit_testimm(s1l,0x800000);
6401 nottaken=(int)out;
6402 emit_jeq(0);
6403 }
6404 }
6405
6406 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6407 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6408 if(likely[i]||unconditional)
6409 {
6410 emit_movimm(ba[i],HOST_BTREG);
6411 }
6412 else if(addr!=HOST_BTREG)
6413 {
6414 emit_mov(addr,HOST_BTREG);
6415 }
6416 void *branch_addr=out;
6417 emit_jmp(0);
6418 int target_addr=start+i*4+5;
6419 void *stub=out;
6420 void *compiled_target_addr=check_addr(target_addr);
6421 emit_extjump_ds((int)branch_addr,target_addr);
6422 if(compiled_target_addr) {
6423 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6424 add_link(target_addr,stub);
6425 }
6426 else set_jump_target((int)branch_addr,(int)stub);
6427 if(likely[i]) {
6428 // Not-taken path
6429 set_jump_target((int)nottaken,(int)out);
6430 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6431 void *branch_addr=out;
6432 emit_jmp(0);
6433 int target_addr=start+i*4+8;
6434 void *stub=out;
6435 void *compiled_target_addr=check_addr(target_addr);
6436 emit_extjump_ds((int)branch_addr,target_addr);
6437 if(compiled_target_addr) {
6438 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6439 add_link(target_addr,stub);
6440 }
6441 else set_jump_target((int)branch_addr,(int)stub);
6442 }
6443}
6444
6445// Assemble the delay slot for the above
6446static void pagespan_ds()
6447{
6448 assem_debug("initial delay slot:\n");
6449 u_int vaddr=start+1;
94d23bb9 6450 u_int page=get_page(vaddr);
6451 u_int vpage=get_vpage(vaddr);
57871462 6452 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6453 do_dirty_stub_ds();
6454 ll_add(jump_in+page,vaddr,(void *)out);
6455 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6456 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6457 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6458 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6459 emit_writeword(HOST_BTREG,(int)&branch_target);
6460 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6461 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6462 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6463 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6464 cop1_usable=0;
6465 is_delayslot=0;
6466 switch(itype[0]) {
6467 case ALU:
6468 alu_assemble(0,&regs[0]);break;
6469 case IMM16:
6470 imm16_assemble(0,&regs[0]);break;
6471 case SHIFT:
6472 shift_assemble(0,&regs[0]);break;
6473 case SHIFTIMM:
6474 shiftimm_assemble(0,&regs[0]);break;
6475 case LOAD:
6476 load_assemble(0,&regs[0]);break;
6477 case LOADLR:
6478 loadlr_assemble(0,&regs[0]);break;
6479 case STORE:
6480 store_assemble(0,&regs[0]);break;
6481 case STORELR:
6482 storelr_assemble(0,&regs[0]);break;
6483 case COP0:
6484 cop0_assemble(0,&regs[0]);break;
6485 case COP1:
6486 cop1_assemble(0,&regs[0]);break;
6487 case C1LS:
6488 c1ls_assemble(0,&regs[0]);break;
b9b61529 6489 case COP2:
6490 cop2_assemble(0,&regs[0]);break;
6491 case C2LS:
6492 c2ls_assemble(0,&regs[0]);break;
6493 case C2OP:
6494 c2op_assemble(0,&regs[0]);break;
57871462 6495 case FCONV:
6496 fconv_assemble(0,&regs[0]);break;
6497 case FLOAT:
6498 float_assemble(0,&regs[0]);break;
6499 case FCOMP:
6500 fcomp_assemble(0,&regs[0]);break;
6501 case MULTDIV:
6502 multdiv_assemble(0,&regs[0]);break;
6503 case MOV:
6504 mov_assemble(0,&regs[0]);break;
6505 case SYSCALL:
7139f3c8 6506 case HLECALL:
1e973cb0 6507 case INTCALL:
57871462 6508 case SPAN:
6509 case UJUMP:
6510 case RJUMP:
6511 case CJUMP:
6512 case SJUMP:
6513 case FJUMP:
6514 printf("Jump in the delay slot. This is probably a bug.\n");
6515 }
6516 int btaddr=get_reg(regs[0].regmap,BTREG);
6517 if(btaddr<0) {
6518 btaddr=get_reg(regs[0].regmap,-1);
6519 emit_readword((int)&branch_target,btaddr);
6520 }
6521 assert(btaddr!=HOST_CCREG);
6522 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6523#ifdef HOST_IMM8
6524 emit_movimm(start+4,HOST_TEMPREG);
6525 emit_cmp(btaddr,HOST_TEMPREG);
6526#else
6527 emit_cmpimm(btaddr,start+4);
6528#endif
6529 int branch=(int)out;
6530 emit_jeq(0);
6531 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6532 emit_jmp(jump_vaddr_reg[btaddr]);
6533 set_jump_target(branch,(int)out);
6534 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6535 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6536}
6537
6538// Basic liveness analysis for MIPS registers
6539void unneeded_registers(int istart,int iend,int r)
6540{
6541 int i;
6542 uint64_t u,uu,b,bu;
6543 uint64_t temp_u,temp_uu;
6544 uint64_t tdep;
6545 if(iend==slen-1) {
6546 u=1;uu=1;
6547 }else{
6548 u=unneeded_reg[iend+1];
6549 uu=unneeded_reg_upper[iend+1];
6550 u=1;uu=1;
6551 }
6552 for (i=iend;i>=istart;i--)
6553 {
6554 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6555 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6556 {
6557 // If subroutine call, flag return address as a possible branch target
6558 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6559
6560 if(ba[i]<start || ba[i]>=(start+slen*4))
6561 {
6562 // Branch out of this block, flush all regs
6563 u=1;
6564 uu=1;
6565 /* Hexagon hack
6566 if(itype[i]==UJUMP&&rt1[i]==31)
6567 {
6568 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6569 }
6570 if(itype[i]==RJUMP&&rs1[i]==31)
6571 {
6572 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6573 }
4cb76aa4 6574 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6575 if(itype[i]==UJUMP&&rt1[i]==31)
6576 {
6577 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6578 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6579 }
6580 if(itype[i]==RJUMP&&rs1[i]==31)
6581 {
6582 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6583 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6584 }
6585 }*/
6586 branch_unneeded_reg[i]=u;
6587 branch_unneeded_reg_upper[i]=uu;
6588 // Merge in delay slot
6589 tdep=(~uu>>rt1[i+1])&1;
6590 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6591 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6592 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6593 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6594 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6595 u|=1;uu|=1;
6596 // If branch is "likely" (and conditional)
6597 // then we skip the delay slot on the fall-thru path
6598 if(likely[i]) {
6599 if(i<slen-1) {
6600 u&=unneeded_reg[i+2];
6601 uu&=unneeded_reg_upper[i+2];
6602 }
6603 else
6604 {
6605 u=1;
6606 uu=1;
6607 }
6608 }
6609 }
6610 else
6611 {
6612 // Internal branch, flag target
6613 bt[(ba[i]-start)>>2]=1;
6614 if(ba[i]<=start+i*4) {
6615 // Backward branch
6616 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6617 {
6618 // Unconditional branch
6619 temp_u=1;temp_uu=1;
6620 } else {
6621 // Conditional branch (not taken case)
6622 temp_u=unneeded_reg[i+2];
6623 temp_uu=unneeded_reg_upper[i+2];
6624 }
6625 // Merge in delay slot
6626 tdep=(~temp_uu>>rt1[i+1])&1;
6627 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6628 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6629 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6630 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6631 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6632 temp_u|=1;temp_uu|=1;
6633 // If branch is "likely" (and conditional)
6634 // then we skip the delay slot on the fall-thru path
6635 if(likely[i]) {
6636 if(i<slen-1) {
6637 temp_u&=unneeded_reg[i+2];
6638 temp_uu&=unneeded_reg_upper[i+2];
6639 }
6640 else
6641 {
6642 temp_u=1;
6643 temp_uu=1;
6644 }
6645 }
6646 tdep=(~temp_uu>>rt1[i])&1;
6647 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6648 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6649 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6650 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6651 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6652 temp_u|=1;temp_uu|=1;
6653 unneeded_reg[i]=temp_u;
6654 unneeded_reg_upper[i]=temp_uu;
6655 // Only go three levels deep. This recursion can take an
6656 // excessive amount of time if there are a lot of nested loops.
6657 if(r<2) {
6658 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6659 }else{
6660 unneeded_reg[(ba[i]-start)>>2]=1;
6661 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6662 }
6663 } /*else*/ if(1) {
6664 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6665 {
6666 // Unconditional branch
6667 u=unneeded_reg[(ba[i]-start)>>2];
6668 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6669 branch_unneeded_reg[i]=u;
6670 branch_unneeded_reg_upper[i]=uu;
6671 //u=1;
6672 //uu=1;
6673 //branch_unneeded_reg[i]=u;
6674 //branch_unneeded_reg_upper[i]=uu;
6675 // Merge in delay slot
6676 tdep=(~uu>>rt1[i+1])&1;
6677 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6678 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6679 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6680 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6681 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6682 u|=1;uu|=1;
6683 } else {
6684 // Conditional branch
6685 b=unneeded_reg[(ba[i]-start)>>2];
6686 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6687 branch_unneeded_reg[i]=b;
6688 branch_unneeded_reg_upper[i]=bu;
6689 //b=1;
6690 //bu=1;
6691 //branch_unneeded_reg[i]=b;
6692 //branch_unneeded_reg_upper[i]=bu;
6693 // Branch delay slot
6694 tdep=(~uu>>rt1[i+1])&1;
6695 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6696 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6697 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6698 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6699 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6700 b|=1;bu|=1;
6701 // If branch is "likely" then we skip the
6702 // delay slot on the fall-thru path
6703 if(likely[i]) {
6704 u=b;
6705 uu=bu;
6706 if(i<slen-1) {
6707 u&=unneeded_reg[i+2];
6708 uu&=unneeded_reg_upper[i+2];
6709 //u=1;
6710 //uu=1;
6711 }
6712 } else {
6713 u&=b;
6714 uu&=bu;
6715 //u=1;
6716 //uu=1;
6717 }
6718 if(i<slen-1) {
6719 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6720 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6721 //branch_unneeded_reg[i]=1;
6722 //branch_unneeded_reg_upper[i]=1;
6723 } else {
6724 branch_unneeded_reg[i]=1;
6725 branch_unneeded_reg_upper[i]=1;
6726 }
6727 }
6728 }
6729 }
6730 }
1e973cb0 6731 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6732 {
6733 // SYSCALL instruction (software interrupt)
6734 u=1;
6735 uu=1;
6736 }
6737 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6738 {
6739 // ERET instruction (return from interrupt)
6740 u=1;
6741 uu=1;
6742 }
6743 //u=uu=1; // DEBUG
6744 tdep=(~uu>>rt1[i])&1;
6745 // Written registers are unneeded
6746 u|=1LL<<rt1[i];
6747 u|=1LL<<rt2[i];
6748 uu|=1LL<<rt1[i];
6749 uu|=1LL<<rt2[i];
6750 // Accessed registers are needed
6751 u&=~(1LL<<rs1[i]);
6752 u&=~(1LL<<rs2[i]);
6753 uu&=~(1LL<<us1[i]);
6754 uu&=~(1LL<<us2[i]);
6755 // Source-target dependencies
6756 uu&=~(tdep<<dep1[i]);
6757 uu&=~(tdep<<dep2[i]);
6758 // R0 is always unneeded
6759 u|=1;uu|=1;
6760 // Save it
6761 unneeded_reg[i]=u;
6762 unneeded_reg_upper[i]=uu;
6763 /*
6764 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6765 printf("U:");
6766 int r;
6767 for(r=1;r<=CCREG;r++) {
6768 if((unneeded_reg[i]>>r)&1) {
6769 if(r==HIREG) printf(" HI");
6770 else if(r==LOREG) printf(" LO");
6771 else printf(" r%d",r);
6772 }
6773 }
6774 printf(" UU:");
6775 for(r=1;r<=CCREG;r++) {
6776 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6777 if(r==HIREG) printf(" HI");
6778 else if(r==LOREG) printf(" LO");
6779 else printf(" r%d",r);
6780 }
6781 }
6782 printf("\n");*/
6783 }
252c20fc 6784#ifdef FORCE32
6785 for (i=iend;i>=istart;i--)
6786 {
6787 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6788 }
6789#endif
57871462 6790}
6791
6792// Identify registers which are likely to contain 32-bit values
6793// This is used to predict whether any branches will jump to a
6794// location with 64-bit values in registers.
6795static void provisional_32bit()
6796{
6797 int i,j;
6798 uint64_t is32=1;
6799 uint64_t lastbranch=1;
6800
6801 for(i=0;i<slen;i++)
6802 {
6803 if(i>0) {
6804 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6805 if(i>1) is32=lastbranch;
6806 else is32=1;
6807 }
6808 }
6809 if(i>1)
6810 {
6811 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6812 if(likely[i-2]) {
6813 if(i>2) is32=lastbranch;
6814 else is32=1;
6815 }
6816 }
6817 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6818 {
6819 if(rs1[i-2]==0||rs2[i-2]==0)
6820 {
6821 if(rs1[i-2]) {
6822 is32|=1LL<<rs1[i-2];
6823 }
6824 if(rs2[i-2]) {
6825 is32|=1LL<<rs2[i-2];
6826 }
6827 }
6828 }
6829 }
6830 // If something jumps here with 64-bit values
6831 // then promote those registers to 64 bits
6832 if(bt[i])
6833 {
6834 uint64_t temp_is32=is32;
6835 for(j=i-1;j>=0;j--)
6836 {
6837 if(ba[j]==start+i*4)
6838 //temp_is32&=branch_regs[j].is32;
6839 temp_is32&=p32[j];
6840 }
6841 for(j=i;j<slen;j++)
6842 {
6843 if(ba[j]==start+i*4)
6844 temp_is32=1;
6845 }
6846 is32=temp_is32;
6847 }
6848 int type=itype[i];
6849 int op=opcode[i];
6850 int op2=opcode2[i];
6851 int rt=rt1[i];
6852 int s1=rs1[i];
6853 int s2=rs2[i];
6854 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6855 // Branches don't write registers, consider the delay slot instead.
6856 type=itype[i+1];
6857 op=opcode[i+1];
6858 op2=opcode2[i+1];
6859 rt=rt1[i+1];
6860 s1=rs1[i+1];
6861 s2=rs2[i+1];
6862 lastbranch=is32;
6863 }
6864 switch(type) {
6865 case LOAD:
6866 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6867 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6868 is32&=~(1LL<<rt);
6869 else
6870 is32|=1LL<<rt;
6871 break;
6872 case STORE:
6873 case STORELR:
6874 break;
6875 case LOADLR:
6876 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6877 if(op==0x22) is32|=1LL<<rt; // LWL
6878 break;
6879 case IMM16:
6880 if (op==0x08||op==0x09|| // ADDI/ADDIU
6881 op==0x0a||op==0x0b|| // SLTI/SLTIU
6882 op==0x0c|| // ANDI
6883 op==0x0f) // LUI
6884 {
6885 is32|=1LL<<rt;
6886 }
6887 if(op==0x18||op==0x19) { // DADDI/DADDIU
6888 is32&=~(1LL<<rt);
6889 //if(imm[i]==0)
6890 // is32|=((is32>>s1)&1LL)<<rt;
6891 }
6892 if(op==0x0d||op==0x0e) { // ORI/XORI
6893 uint64_t sr=((is32>>s1)&1LL);
6894 is32&=~(1LL<<rt);
6895 is32|=sr<<rt;
6896 }
6897 break;
6898 case UJUMP:
6899 break;
6900 case RJUMP:
6901 break;
6902 case CJUMP:
6903 break;
6904 case SJUMP:
6905 break;
6906 case FJUMP:
6907 break;
6908 case ALU:
6909 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6910 is32|=1LL<<rt;
6911 }
6912 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6913 is32|=1LL<<rt;
6914 }
6915 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6916 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6917 is32&=~(1LL<<rt);
6918 is32|=sr<<rt;
6919 }
6920 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6921 if(s1==0&&s2==0) {
6922 is32|=1LL<<rt;
6923 }
6924 else if(s2==0) {
6925 uint64_t sr=((is32>>s1)&1LL);
6926 is32&=~(1LL<<rt);
6927 is32|=sr<<rt;
6928 }
6929 else if(s1==0) {
6930 uint64_t sr=((is32>>s2)&1LL);
6931 is32&=~(1LL<<rt);
6932 is32|=sr<<rt;
6933 }
6934 else {
6935 is32&=~(1LL<<rt);
6936 }
6937 }
6938 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6939 if(s1==0&&s2==0) {
6940 is32|=1LL<<rt;
6941 }
6942 else if(s2==0) {
6943 uint64_t sr=((is32>>s1)&1LL);
6944 is32&=~(1LL<<rt);
6945 is32|=sr<<rt;
6946 }
6947 else {
6948 is32&=~(1LL<<rt);
6949 }
6950 }
6951 break;
6952 case MULTDIV:
6953 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6954 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6955 }
6956 else {
6957 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6958 }
6959 break;
6960 case MOV:
6961 {
6962 uint64_t sr=((is32>>s1)&1LL);
6963 is32&=~(1LL<<rt);
6964 is32|=sr<<rt;
6965 }
6966 break;
6967 case SHIFT:
6968 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6969 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6970 break;
6971 case SHIFTIMM:
6972 is32|=1LL<<rt;
6973 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6974 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6975 break;
6976 case COP0:
6977 if(op2==0) is32|=1LL<<rt; // MFC0
6978 break;
6979 case COP1:
b9b61529 6980 case COP2:
57871462 6981 if(op2==0) is32|=1LL<<rt; // MFC1
6982 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6983 if(op2==2) is32|=1LL<<rt; // CFC1
6984 break;
6985 case C1LS:
b9b61529 6986 case C2LS:
57871462 6987 break;
6988 case FLOAT:
6989 case FCONV:
6990 break;
6991 case FCOMP:
6992 break;
b9b61529 6993 case C2OP:
57871462 6994 case SYSCALL:
7139f3c8 6995 case HLECALL:
57871462 6996 break;
6997 default:
6998 break;
6999 }
7000 is32|=1;
7001 p32[i]=is32;
7002
7003 if(i>0)
7004 {
7005 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7006 {
7007 if(rt1[i-1]==31) // JAL/JALR
7008 {
7009 // Subroutine call will return here, don't alloc any registers
7010 is32=1;
7011 }
7012 else if(i+1<slen)
7013 {
7014 // Internal branch will jump here, match registers to caller
7015 is32=0x3FFFFFFFFLL;
7016 }
7017 }
7018 }
7019 }
7020}
7021
7022// Identify registers which may be assumed to contain 32-bit values
7023// and where optimizations will rely on this.
7024// This is used to determine whether backward branches can safely
7025// jump to a location with 64-bit values in registers.
7026static void provisional_r32()
7027{
7028 u_int r32=0;
7029 int i;
7030
7031 for (i=slen-1;i>=0;i--)
7032 {
7033 int hr;
7034 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7035 {
7036 if(ba[i]<start || ba[i]>=(start+slen*4))
7037 {
7038 // Branch out of this block, don't need anything
7039 r32=0;
7040 }
7041 else
7042 {
7043 // Internal branch
7044 // Need whatever matches the target
7045 // (and doesn't get overwritten by the delay slot instruction)
7046 r32=0;
7047 int t=(ba[i]-start)>>2;
7048 if(ba[i]>start+i*4) {
7049 // Forward branch
7050 //if(!(requires_32bit[t]&~regs[i].was32))
7051 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7052 if(!(pr32[t]&~regs[i].was32))
7053 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7054 }else{
7055 // Backward branch
7056 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7057 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7058 }
7059 }
7060 // Conditional branch may need registers for following instructions
7061 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7062 {
7063 if(i<slen-2) {
7064 //r32|=requires_32bit[i+2];
7065 r32|=pr32[i+2];
7066 r32&=regs[i].was32;
7067 // Mark this address as a branch target since it may be called
7068 // upon return from interrupt
7069 //bt[i+2]=1;
7070 }
7071 }
7072 // Merge in delay slot
7073 if(!likely[i]) {
7074 // These are overwritten unless the branch is "likely"
7075 // and the delay slot is nullified if not taken
7076 r32&=~(1LL<<rt1[i+1]);
7077 r32&=~(1LL<<rt2[i+1]);
7078 }
7079 // Assume these are needed (delay slot)
7080 if(us1[i+1]>0)
7081 {
7082 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7083 }
7084 if(us2[i+1]>0)
7085 {
7086 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7087 }
7088 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7089 {
7090 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7091 }
7092 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7093 {
7094 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7095 }
7096 }
1e973cb0 7097 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7098 {
7099 // SYSCALL instruction (software interrupt)
7100 r32=0;
7101 }
7102 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7103 {
7104 // ERET instruction (return from interrupt)
7105 r32=0;
7106 }
7107 // Check 32 bits
7108 r32&=~(1LL<<rt1[i]);
7109 r32&=~(1LL<<rt2[i]);
7110 if(us1[i]>0)
7111 {
7112 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7113 }
7114 if(us2[i]>0)
7115 {
7116 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7117 }
7118 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7119 {
7120 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7121 }
7122 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7123 {
7124 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7125 }
7126 //requires_32bit[i]=r32;
7127 pr32[i]=r32;
7128
7129 // Dirty registers which are 32-bit, require 32-bit input
7130 // as they will be written as 32-bit values
7131 for(hr=0;hr<HOST_REGS;hr++)
7132 {
7133 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7134 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7135 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7136 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7137 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7138 }
7139 }
7140 }
7141 }
7142}
7143
7144// Write back dirty registers as soon as we will no longer modify them,
7145// so that we don't end up with lots of writes at the branches.
7146void clean_registers(int istart,int iend,int wr)
7147{
7148 int i;
7149 int r;
7150 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7151 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7152 if(iend==slen-1) {
7153 will_dirty_i=will_dirty_next=0;
7154 wont_dirty_i=wont_dirty_next=0;
7155 }else{
7156 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7157 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7158 }
7159 for (i=iend;i>=istart;i--)
7160 {
7161 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7162 {
7163 if(ba[i]<start || ba[i]>=(start+slen*4))
7164 {
7165 // Branch out of this block, flush all regs
7166 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7167 {
7168 // Unconditional branch
7169 will_dirty_i=0;
7170 wont_dirty_i=0;
7171 // Merge in delay slot (will dirty)
7172 for(r=0;r<HOST_REGS;r++) {
7173 if(r!=EXCLUDE_REG) {
7174 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7175 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7176 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7177 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7178 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7179 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7180 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7181 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7182 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7183 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7184 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7185 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7186 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7187 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7188 }
7189 }
7190 }
7191 else
7192 {
7193 // Conditional branch
7194 will_dirty_i=0;
7195 wont_dirty_i=wont_dirty_next;
7196 // Merge in delay slot (will dirty)
7197 for(r=0;r<HOST_REGS;r++) {
7198 if(r!=EXCLUDE_REG) {
7199 if(!likely[i]) {
7200 // Might not dirty if likely branch is not taken
7201 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7202 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7203 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7204 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7205 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7206 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7207 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7208 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7209 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7210 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7211 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7212 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7213 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7214 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7215 }
7216 }
7217 }
7218 }
7219 // Merge in delay slot (wont dirty)
7220 for(r=0;r<HOST_REGS;r++) {
7221 if(r!=EXCLUDE_REG) {
7222 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7223 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7224 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7225 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7226 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7227 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7228 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7229 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7230 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7231 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7232 }
7233 }
7234 if(wr) {
7235 #ifndef DESTRUCTIVE_WRITEBACK
7236 branch_regs[i].dirty&=wont_dirty_i;
7237 #endif
7238 branch_regs[i].dirty|=will_dirty_i;
7239 }
7240 }
7241 else
7242 {
7243 // Internal branch
7244 if(ba[i]<=start+i*4) {
7245 // Backward branch
7246 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7247 {
7248 // Unconditional branch
7249 temp_will_dirty=0;
7250 temp_wont_dirty=0;
7251 // Merge in delay slot (will dirty)
7252 for(r=0;r<HOST_REGS;r++) {
7253 if(r!=EXCLUDE_REG) {
7254 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7255 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7256 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7257 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7258 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7259 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7260 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7261 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7262 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7263 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7264 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7265 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7266 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7267 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7268 }
7269 }
7270 } else {
7271 // Conditional branch (not taken case)
7272 temp_will_dirty=will_dirty_next;
7273 temp_wont_dirty=wont_dirty_next;
7274 // Merge in delay slot (will dirty)
7275 for(r=0;r<HOST_REGS;r++) {
7276 if(r!=EXCLUDE_REG) {
7277 if(!likely[i]) {
7278 // Will not dirty if likely branch is not taken
7279 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7280 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7281 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7282 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7283 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7284 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7285 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7286 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7287 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7288 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7289 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7290 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7291 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7292 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7293 }
7294 }
7295 }
7296 }
7297 // Merge in delay slot (wont dirty)
7298 for(r=0;r<HOST_REGS;r++) {
7299 if(r!=EXCLUDE_REG) {
7300 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7301 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7302 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7304 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7307 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7308 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7309 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7310 }
7311 }
7312 // Deal with changed mappings
7313 if(i<iend) {
7314 for(r=0;r<HOST_REGS;r++) {
7315 if(r!=EXCLUDE_REG) {
7316 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7317 temp_will_dirty&=~(1<<r);
7318 temp_wont_dirty&=~(1<<r);
7319 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7320 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7321 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7322 } else {
7323 temp_will_dirty|=1<<r;
7324 temp_wont_dirty|=1<<r;
7325 }
7326 }
7327 }
7328 }
7329 }
7330 if(wr) {
7331 will_dirty[i]=temp_will_dirty;
7332 wont_dirty[i]=temp_wont_dirty;
7333 clean_registers((ba[i]-start)>>2,i-1,0);
7334 }else{
7335 // Limit recursion. It can take an excessive amount
7336 // of time if there are a lot of nested loops.
7337 will_dirty[(ba[i]-start)>>2]=0;
7338 wont_dirty[(ba[i]-start)>>2]=-1;
7339 }
7340 }
7341 /*else*/ if(1)
7342 {
7343 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7344 {
7345 // Unconditional branch
7346 will_dirty_i=0;
7347 wont_dirty_i=0;
7348 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7349 for(r=0;r<HOST_REGS;r++) {
7350 if(r!=EXCLUDE_REG) {
7351 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7352 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7353 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7354 }
7355 }
7356 }
7357 //}
7358 // Merge in delay slot
7359 for(r=0;r<HOST_REGS;r++) {
7360 if(r!=EXCLUDE_REG) {
7361 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7362 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7363 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7364 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7365 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7366 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7367 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7368 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7369 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7370 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7371 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7372 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7373 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7374 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7375 }
7376 }
7377 } else {
7378 // Conditional branch
7379 will_dirty_i=will_dirty_next;
7380 wont_dirty_i=wont_dirty_next;
7381 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7382 for(r=0;r<HOST_REGS;r++) {
7383 if(r!=EXCLUDE_REG) {
7384 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7385 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7386 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7387 }
7388 else
7389 {
7390 will_dirty_i&=~(1<<r);
7391 }
7392 // Treat delay slot as part of branch too
7393 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7394 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7395 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7396 }
7397 else
7398 {
7399 will_dirty[i+1]&=~(1<<r);
7400 }*/
7401 }
7402 }
7403 //}
7404 // Merge in delay slot
7405 for(r=0;r<HOST_REGS;r++) {
7406 if(r!=EXCLUDE_REG) {
7407 if(!likely[i]) {
7408 // Might not dirty if likely branch is not taken
7409 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7412 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7413 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7414 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7415 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7416 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7423 }
7424 }
7425 }
7426 }
7427 // Merge in delay slot
7428 for(r=0;r<HOST_REGS;r++) {
7429 if(r!=EXCLUDE_REG) {
7430 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7431 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7433 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7434 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7435 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7436 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7437 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7438 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7439 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7440 }
7441 }
7442 if(wr) {
7443 #ifndef DESTRUCTIVE_WRITEBACK
7444 branch_regs[i].dirty&=wont_dirty_i;
7445 #endif
7446 branch_regs[i].dirty|=will_dirty_i;
7447 }
7448 }
7449 }
7450 }
1e973cb0 7451 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7452 {
7453 // SYSCALL instruction (software interrupt)
7454 will_dirty_i=0;
7455 wont_dirty_i=0;
7456 }
7457 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7458 {
7459 // ERET instruction (return from interrupt)
7460 will_dirty_i=0;
7461 wont_dirty_i=0;
7462 }
7463 will_dirty_next=will_dirty_i;
7464 wont_dirty_next=wont_dirty_i;
7465 for(r=0;r<HOST_REGS;r++) {
7466 if(r!=EXCLUDE_REG) {
7467 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7474 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7475 if(i>istart) {
7476 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7477 {
7478 // Don't store a register immediately after writing it,
7479 // may prevent dual-issue.
7480 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7481 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7482 }
7483 }
7484 }
7485 }
7486 // Save it
7487 will_dirty[i]=will_dirty_i;
7488 wont_dirty[i]=wont_dirty_i;
7489 // Mark registers that won't be dirtied as not dirty
7490 if(wr) {
7491 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7492 for(r=0;r<HOST_REGS;r++) {
7493 if((will_dirty_i>>r)&1) {
7494 printf(" r%d",r);
7495 }
7496 }
7497 printf("\n");*/
7498
7499 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7500 regs[i].dirty|=will_dirty_i;
7501 #ifndef DESTRUCTIVE_WRITEBACK
7502 regs[i].dirty&=wont_dirty_i;
7503 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7504 {
7505 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7506 for(r=0;r<HOST_REGS;r++) {
7507 if(r!=EXCLUDE_REG) {
7508 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7509 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7510 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7511 }
7512 }
7513 }
7514 }
7515 else
7516 {
7517 if(i<iend) {
7518 for(r=0;r<HOST_REGS;r++) {
7519 if(r!=EXCLUDE_REG) {
7520 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7521 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7522 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7523 }
7524 }
7525 }
7526 }
7527 #endif
7528 //}
7529 }
7530 // Deal with changed mappings
7531 temp_will_dirty=will_dirty_i;
7532 temp_wont_dirty=wont_dirty_i;
7533 for(r=0;r<HOST_REGS;r++) {
7534 if(r!=EXCLUDE_REG) {
7535 int nr;
7536 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7537 if(wr) {
7538 #ifndef DESTRUCTIVE_WRITEBACK
7539 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7540 #endif
7541 regs[i].wasdirty|=will_dirty_i&(1<<r);
7542 }
7543 }
7544 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7545 // Register moved to a different register
7546 will_dirty_i&=~(1<<r);
7547 wont_dirty_i&=~(1<<r);
7548 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7549 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7550 if(wr) {
7551 #ifndef DESTRUCTIVE_WRITEBACK
7552 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7553 #endif
7554 regs[i].wasdirty|=will_dirty_i&(1<<r);
7555 }
7556 }
7557 else {
7558 will_dirty_i&=~(1<<r);
7559 wont_dirty_i&=~(1<<r);
7560 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7561 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7562 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7563 } else {
7564 wont_dirty_i|=1<<r;
7565 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7566 }
7567 }
7568 }
7569 }
7570 }
7571}
7572
7573 /* disassembly */
7574void disassemble_inst(int i)
7575{
7576 if (bt[i]) printf("*"); else printf(" ");
7577 switch(itype[i]) {
7578 case UJUMP:
7579 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7580 case CJUMP:
7581 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7582 case SJUMP:
7583 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7584 case FJUMP:
7585 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7586 case RJUMP:
74426039 7587 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7588 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7589 else
7590 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7591 break;
57871462 7592 case SPAN:
7593 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7594 case IMM16:
7595 if(opcode[i]==0xf) //LUI
7596 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7597 else
7598 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7599 break;
7600 case LOAD:
7601 case LOADLR:
7602 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7603 break;
7604 case STORE:
7605 case STORELR:
7606 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7607 break;
7608 case ALU:
7609 case SHIFT:
7610 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7611 break;
7612 case MULTDIV:
7613 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7614 break;
7615 case SHIFTIMM:
7616 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7617 break;
7618 case MOV:
7619 if((opcode2[i]&0x1d)==0x10)
7620 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7621 else if((opcode2[i]&0x1d)==0x11)
7622 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7623 else
7624 printf (" %x: %s\n",start+i*4,insn[i]);
7625 break;
7626 case COP0:
7627 if(opcode2[i]==0)
7628 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7629 else if(opcode2[i]==4)
7630 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7631 else printf (" %x: %s\n",start+i*4,insn[i]);
7632 break;
7633 case COP1:
7634 if(opcode2[i]<3)
7635 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7636 else if(opcode2[i]>3)
7637 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7638 else printf (" %x: %s\n",start+i*4,insn[i]);
7639 break;
b9b61529 7640 case COP2:
7641 if(opcode2[i]<3)
7642 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7643 else if(opcode2[i]>3)
7644 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7645 else printf (" %x: %s\n",start+i*4,insn[i]);
7646 break;
57871462 7647 case C1LS:
7648 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7649 break;
b9b61529 7650 case C2LS:
7651 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7652 break;
1e973cb0 7653 case INTCALL:
7654 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7655 break;
57871462 7656 default:
7657 //printf (" %s %8x\n",insn[i],source[i]);
7658 printf (" %x: %s\n",start+i*4,insn[i]);
7659 }
7660}
7661
7662void new_dynarec_init()
7663{
7664 printf("Init new dynarec\n");
7665 out=(u_char *)BASE_ADDR;
7666 if (mmap (out, 1<<TARGET_SIZE_2,
7667 PROT_READ | PROT_WRITE | PROT_EXEC,
7668 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7669 -1, 0) <= 0) {printf("mmap() failed\n");}
3d624f89 7670#ifdef MUPEN64
57871462 7671 rdword=&readmem_dword;
7672 fake_pc.f.r.rs=&readmem_dword;
7673 fake_pc.f.r.rt=&readmem_dword;
7674 fake_pc.f.r.rd=&readmem_dword;
3d624f89 7675#endif
57871462 7676 int n;
7677 for(n=0x80000;n<0x80800;n++)
7678 invalid_code[n]=1;
7679 for(n=0;n<65536;n++)
7680 hash_table[n][0]=hash_table[n][2]=-1;
7681 memset(mini_ht,-1,sizeof(mini_ht));
7682 memset(restore_candidate,0,sizeof(restore_candidate));
7683 copy=shadow;
7684 expirep=16384; // Expiry pointer, +2 blocks
7685 pending_exception=0;
7686 literalcount=0;
7687#ifdef HOST_IMM8
7688 // Copy this into local area so we don't have to put it in every literal pool
7689 invc_ptr=invalid_code;
7690#endif
7691 stop_after_jal=0;
7692 // TLB
7693 using_tlb=0;
7694 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7695 memory_map[n]=-1;
7696 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7697 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7698 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7699 memory_map[n]=-1;
24385cae 7700#ifdef MUPEN64
57871462 7701 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7702 writemem[n] = write_nomem_new;
7703 writememb[n] = write_nomemb_new;
7704 writememh[n] = write_nomemh_new;
24385cae 7705#ifndef FORCE32
57871462 7706 writememd[n] = write_nomemd_new;
24385cae 7707#endif
57871462 7708 readmem[n] = read_nomem_new;
7709 readmemb[n] = read_nomemb_new;
7710 readmemh[n] = read_nomemh_new;
24385cae 7711#ifndef FORCE32
57871462 7712 readmemd[n] = read_nomemd_new;
24385cae 7713#endif
57871462 7714 }
7715 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7716 writemem[n] = write_rdram_new;
7717 writememb[n] = write_rdramb_new;
7718 writememh[n] = write_rdramh_new;
24385cae 7719#ifndef FORCE32
57871462 7720 writememd[n] = write_rdramd_new;
24385cae 7721#endif
57871462 7722 }
7723 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7724 writemem[n] = write_nomem_new;
7725 writememb[n] = write_nomemb_new;
7726 writememh[n] = write_nomemh_new;
24385cae 7727#ifndef FORCE32
57871462 7728 writememd[n] = write_nomemd_new;
24385cae 7729#endif
57871462 7730 readmem[n] = read_nomem_new;
7731 readmemb[n] = read_nomemb_new;
7732 readmemh[n] = read_nomemh_new;
24385cae 7733#ifndef FORCE32
57871462 7734 readmemd[n] = read_nomemd_new;
24385cae 7735#endif
57871462 7736 }
24385cae 7737#endif
57871462 7738 tlb_hacks();
7739 arch_init();
7740}
7741
7742void new_dynarec_cleanup()
7743{
7744 int n;
7745 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7746 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7747 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7748 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7749 #ifdef ROM_COPY
7750 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7751 #endif
7752}
7753
7754int new_recompile_block(int addr)
7755{
7756/*
7757 if(addr==0x800cd050) {
7758 int block;
7759 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7760 int n;
7761 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7762 }
7763*/
7764 //if(Count==365117028) tracedebug=1;
7765 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7766 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7767 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7768 //if(debug)
7769 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7770 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7771 /*if(Count>=312978186) {
7772 rlist();
7773 }*/
7774 //rlist();
7775 start = (u_int)addr&~3;
7776 //assert(((u_int)addr&1)==0);
7139f3c8 7777#ifdef PCSX
9ad4d757 7778 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7779 {
7139f3c8 7780 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7781 u_int beginning=(u_int)out;
7139f3c8 7782 u_int page=get_page(start);
7139f3c8 7783 invalid_code[start>>12]=0;
7784 emit_movimm(start,0);
7785 emit_writeword(0,(int)&pcaddr);
bb5285ef 7786 emit_jmp((int)new_dyna_leave);
7787#ifdef __arm__
7788 __clear_cache((void *)beginning,out);
7789#endif
9ad4d757 7790 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7791 return 0;
7792 }
560e4a12 7793 else if ((u_int)addr < 0x00200000 ||
7794 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7795 // used for BIOS calls mostly?
560e4a12 7796 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7797 pagelimit = (addr&0xa0000000)|0x00200000;
7798 }
7799 else if (!Config.HLE && (
7800/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7801 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7802 // BIOS
7803 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7804 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7805 }
7806 else
7807#endif
3d624f89 7808#ifdef MUPEN64
57871462 7809 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7810 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7811 pagelimit = 0xa4001000;
7812 }
3d624f89 7813 else
7814#endif
4cb76aa4 7815 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7816 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7817 pagelimit = 0x80000000+RAM_SIZE;
57871462 7818 }
90ae6d4e 7819#ifndef DISABLE_TLB
57871462 7820 else if ((signed int)addr >= (signed int)0xC0000000) {
7821 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7822 //if(tlb_LUT_r[start>>12])
7823 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7824 if((signed int)memory_map[start>>12]>=0) {
7825 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7826 pagelimit=(start+4096)&0xFFFFF000;
7827 int map=memory_map[start>>12];
7828 int i;
7829 for(i=0;i<5;i++) {
7830 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7831 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7832 }
7833 assem_debug("pagelimit=%x\n",pagelimit);
7834 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7835 }
7836 else {
7837 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7838 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7839 return -1; // Caller will invoke exception handler
57871462 7840 }
7841 //printf("source= %x\n",(int)source);
7842 }
90ae6d4e 7843#endif
57871462 7844 else {
7845 printf("Compile at bogus memory address: %x \n", (int)addr);
7846 exit(1);
7847 }
7848
7849 /* Pass 1: disassemble */
7850 /* Pass 2: register dependencies, branch targets */
7851 /* Pass 3: register allocation */
7852 /* Pass 4: branch dependencies */
7853 /* Pass 5: pre-alloc */
7854 /* Pass 6: optimize clean/dirty state */
7855 /* Pass 7: flag 32-bit registers */
7856 /* Pass 8: assembly */
7857 /* Pass 9: linker */
7858 /* Pass 10: garbage collection / free memory */
7859
7860 int i,j;
7861 int done=0;
7862 unsigned int type,op,op2;
7863
7864 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7865
7866 /* Pass 1 disassembly */
7867
7868 for(i=0;!done;i++) {
7869 bt[i]=0;likely[i]=0;op2=0;
7870 opcode[i]=op=source[i]>>26;
7871 switch(op)
7872 {
7873 case 0x00: strcpy(insn[i],"special"); type=NI;
7874 op2=source[i]&0x3f;
7875 switch(op2)
7876 {
7877 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7878 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7879 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7880 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7881 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7882 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7883 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7884 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7885 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7886 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7887 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7888 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7889 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7890 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7891 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7892 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7893 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7894 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7895 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7896 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7897 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7898 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7899 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7900 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7901 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7902 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7903 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7904 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7905 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7906 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7907 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7908 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7909 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7910 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7911 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7912 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7913 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7914 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7915 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7916 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7917 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7918 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7919 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7920 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7921 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7922 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7923 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7924 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7925 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7926 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7927 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7928 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7929 }
7930 break;
7931 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7932 op2=(source[i]>>16)&0x1f;
7933 switch(op2)
7934 {
7935 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7936 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7937 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7938 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7939 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7940 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7941 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7942 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7943 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7944 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7945 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7946 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7947 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7948 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7949 }
7950 break;
7951 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7952 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7953 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7954 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7955 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7956 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7957 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7958 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7959 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7960 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7961 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7962 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7963 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7964 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7965 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7966 op2=(source[i]>>21)&0x1f;
7967 switch(op2)
7968 {
7969 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7970 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7971 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7972 switch(source[i]&0x3f)
7973 {
7974 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7975 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7976 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7977 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 7978#ifdef PCSX
7979 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7980#else
57871462 7981 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 7982#endif
57871462 7983 }
7984 }
7985 break;
7986 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7987 op2=(source[i]>>21)&0x1f;
7988 switch(op2)
7989 {
7990 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7991 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7992 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7993 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7994 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7995 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7996 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7997 switch((source[i]>>16)&0x3)
7998 {
7999 case 0x00: strcpy(insn[i],"BC1F"); break;
8000 case 0x01: strcpy(insn[i],"BC1T"); break;
8001 case 0x02: strcpy(insn[i],"BC1FL"); break;
8002 case 0x03: strcpy(insn[i],"BC1TL"); break;
8003 }
8004 break;
8005 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8006 switch(source[i]&0x3f)
8007 {
8008 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8009 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8010 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8011 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8012 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8013 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8014 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8015 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8016 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8017 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8018 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8019 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8020 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8021 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8022 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8023 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8024 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8025 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8026 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8027 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8028 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8029 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8030 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8031 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8032 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8033 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8034 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8035 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8036 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8037 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8038 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8039 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8040 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8041 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8042 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8043 }
8044 break;
8045 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8046 switch(source[i]&0x3f)
8047 {
8048 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8049 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8050 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8051 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8052 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8053 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8054 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8055 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8056 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8057 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8058 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8059 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8060 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8061 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8062 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8063 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8064 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8065 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8066 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8067 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8068 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8069 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8070 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8071 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8072 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8073 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8074 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8075 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8076 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8077 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8078 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8079 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8080 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8081 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8082 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8083 }
8084 break;
8085 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8086 switch(source[i]&0x3f)
8087 {
8088 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8089 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8090 }
8091 break;
8092 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8093 switch(source[i]&0x3f)
8094 {
8095 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8096 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8097 }
8098 break;
8099 }
8100 break;
909168d6 8101#ifndef FORCE32
57871462 8102 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8103 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8104 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8105 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8106 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8107 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8108 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8109 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8110#endif
57871462 8111 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8112 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8113 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8114 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8115 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8116 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8117 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8118 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8119 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8120 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8121 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8122 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8123#ifndef FORCE32
57871462 8124 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8125 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8126#endif
57871462 8127 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8128 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8129 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8130 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8131#ifndef FORCE32
57871462 8132 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8133 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8134 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8135#endif
57871462 8136 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8137 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8138#ifndef FORCE32
57871462 8139 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8140 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8141 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8142#endif
b9b61529 8143#ifdef PCSX
8144 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8145 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8146 op2=(source[i]>>21)&0x1f;
c7abc864 8147 if (source[i]&0x3f) {
8148 if (gte_handlers[source[i]&0x3f]!=NULL) {
8149 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8150 type=C2OP;
8151 }
8152 }
8153 else switch(op2)
b9b61529 8154 {
8155 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8156 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8157 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8158 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8159 }
8160 break;
8161 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8162 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8163 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8164#endif
90ae6d4e 8165 default: strcpy(insn[i],"???"); type=NI;
75dec299 8166 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8167 break;
57871462 8168 }
1e973cb0 8169#ifdef PCSX
8170 /* detect branch in delay slot early */
8171 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8172 opcode[i+1]=source[i+1]>>26;
8173 opcode2[i+1]=source[i+1]&0x3f;
8174 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8175 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8176 // don't handle first branch and call interpreter if it's hit
8177 type=INTCALL;
8178 }
8179 }
8180#endif
57871462 8181 itype[i]=type;
8182 opcode2[i]=op2;
8183 /* Get registers/immediates */
8184 lt1[i]=0;
8185 us1[i]=0;
8186 us2[i]=0;
8187 dep1[i]=0;
8188 dep2[i]=0;
8189 switch(type) {
8190 case LOAD:
8191 rs1[i]=(source[i]>>21)&0x1f;
8192 rs2[i]=0;
8193 rt1[i]=(source[i]>>16)&0x1f;
8194 rt2[i]=0;
8195 imm[i]=(short)source[i];
8196 break;
8197 case STORE:
8198 case STORELR:
8199 rs1[i]=(source[i]>>21)&0x1f;
8200 rs2[i]=(source[i]>>16)&0x1f;
8201 rt1[i]=0;
8202 rt2[i]=0;
8203 imm[i]=(short)source[i];
8204 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8205 break;
8206 case LOADLR:
8207 // LWL/LWR only load part of the register,
8208 // therefore the target register must be treated as a source too
8209 rs1[i]=(source[i]>>21)&0x1f;
8210 rs2[i]=(source[i]>>16)&0x1f;
8211 rt1[i]=(source[i]>>16)&0x1f;
8212 rt2[i]=0;
8213 imm[i]=(short)source[i];
8214 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8215 if(op==0x26) dep1[i]=rt1[i]; // LWR
8216 break;
8217 case IMM16:
8218 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8219 else rs1[i]=(source[i]>>21)&0x1f;
8220 rs2[i]=0;
8221 rt1[i]=(source[i]>>16)&0x1f;
8222 rt2[i]=0;
8223 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8224 imm[i]=(unsigned short)source[i];
8225 }else{
8226 imm[i]=(short)source[i];
8227 }
8228 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8229 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8230 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8231 break;
8232 case UJUMP:
8233 rs1[i]=0;
8234 rs2[i]=0;
8235 rt1[i]=0;
8236 rt2[i]=0;
8237 // The JAL instruction writes to r31.
8238 if (op&1) {
8239 rt1[i]=31;
8240 }
8241 rs2[i]=CCREG;
8242 break;
8243 case RJUMP:
8244 rs1[i]=(source[i]>>21)&0x1f;
8245 rs2[i]=0;
8246 rt1[i]=0;
8247 rt2[i]=0;
5067f341 8248 // The JALR instruction writes to rd.
57871462 8249 if (op2&1) {
5067f341 8250 rt1[i]=(source[i]>>11)&0x1f;
57871462 8251 }
8252 rs2[i]=CCREG;
8253 break;
8254 case CJUMP:
8255 rs1[i]=(source[i]>>21)&0x1f;
8256 rs2[i]=(source[i]>>16)&0x1f;
8257 rt1[i]=0;
8258 rt2[i]=0;
8259 if(op&2) { // BGTZ/BLEZ
8260 rs2[i]=0;
8261 }
8262 us1[i]=rs1[i];
8263 us2[i]=rs2[i];
8264 likely[i]=op>>4;
8265 break;
8266 case SJUMP:
8267 rs1[i]=(source[i]>>21)&0x1f;
8268 rs2[i]=CCREG;
8269 rt1[i]=0;
8270 rt2[i]=0;
8271 us1[i]=rs1[i];
8272 if(op2&0x10) { // BxxAL
8273 rt1[i]=31;
8274 // NOTE: If the branch is not taken, r31 is still overwritten
8275 }
8276 likely[i]=(op2&2)>>1;
8277 break;
8278 case FJUMP:
8279 rs1[i]=FSREG;
8280 rs2[i]=CSREG;
8281 rt1[i]=0;
8282 rt2[i]=0;
8283 likely[i]=((source[i])>>17)&1;
8284 break;
8285 case ALU:
8286 rs1[i]=(source[i]>>21)&0x1f; // source
8287 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8288 rt1[i]=(source[i]>>11)&0x1f; // destination
8289 rt2[i]=0;
8290 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8291 us1[i]=rs1[i];us2[i]=rs2[i];
8292 }
8293 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8294 dep1[i]=rs1[i];dep2[i]=rs2[i];
8295 }
8296 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8297 dep1[i]=rs1[i];dep2[i]=rs2[i];
8298 }
8299 break;
8300 case MULTDIV:
8301 rs1[i]=(source[i]>>21)&0x1f; // source
8302 rs2[i]=(source[i]>>16)&0x1f; // divisor
8303 rt1[i]=HIREG;
8304 rt2[i]=LOREG;
8305 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8306 us1[i]=rs1[i];us2[i]=rs2[i];
8307 }
8308 break;
8309 case MOV:
8310 rs1[i]=0;
8311 rs2[i]=0;
8312 rt1[i]=0;
8313 rt2[i]=0;
8314 if(op2==0x10) rs1[i]=HIREG; // MFHI
8315 if(op2==0x11) rt1[i]=HIREG; // MTHI
8316 if(op2==0x12) rs1[i]=LOREG; // MFLO
8317 if(op2==0x13) rt1[i]=LOREG; // MTLO
8318 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8319 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8320 dep1[i]=rs1[i];
8321 break;
8322 case SHIFT:
8323 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8324 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8325 rt1[i]=(source[i]>>11)&0x1f; // destination
8326 rt2[i]=0;
8327 // DSLLV/DSRLV/DSRAV are 64-bit
8328 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8329 break;
8330 case SHIFTIMM:
8331 rs1[i]=(source[i]>>16)&0x1f;
8332 rs2[i]=0;
8333 rt1[i]=(source[i]>>11)&0x1f;
8334 rt2[i]=0;
8335 imm[i]=(source[i]>>6)&0x1f;
8336 // DSxx32 instructions
8337 if(op2>=0x3c) imm[i]|=0x20;
8338 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8339 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8340 break;
8341 case COP0:
8342 rs1[i]=0;
8343 rs2[i]=0;
8344 rt1[i]=0;
8345 rt2[i]=0;
8346 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8347 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8348 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8349 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8350 break;
8351 case COP1:
b9b61529 8352 case COP2:
57871462 8353 rs1[i]=0;
8354 rs2[i]=0;
8355 rt1[i]=0;
8356 rt2[i]=0;
8357 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8358 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8359 if(op2==5) us1[i]=rs1[i]; // DMTC1
8360 rs2[i]=CSREG;
8361 break;
8362 case C1LS:
8363 rs1[i]=(source[i]>>21)&0x1F;
8364 rs2[i]=CSREG;
8365 rt1[i]=0;
8366 rt2[i]=0;
8367 imm[i]=(short)source[i];
8368 break;
b9b61529 8369 case C2LS:
8370 rs1[i]=(source[i]>>21)&0x1F;
8371 rs2[i]=0;
8372 rt1[i]=0;
8373 rt2[i]=0;
8374 imm[i]=(short)source[i];
8375 break;
57871462 8376 case FLOAT:
8377 case FCONV:
8378 rs1[i]=0;
8379 rs2[i]=CSREG;
8380 rt1[i]=0;
8381 rt2[i]=0;
8382 break;
8383 case FCOMP:
8384 rs1[i]=FSREG;
8385 rs2[i]=CSREG;
8386 rt1[i]=FSREG;
8387 rt2[i]=0;
8388 break;
8389 case SYSCALL:
7139f3c8 8390 case HLECALL:
1e973cb0 8391 case INTCALL:
57871462 8392 rs1[i]=CCREG;
8393 rs2[i]=0;
8394 rt1[i]=0;
8395 rt2[i]=0;
8396 break;
8397 default:
8398 rs1[i]=0;
8399 rs2[i]=0;
8400 rt1[i]=0;
8401 rt2[i]=0;
8402 }
8403 /* Calculate branch target addresses */
8404 if(type==UJUMP)
8405 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8406 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8407 ba[i]=start+i*4+8; // Ignore never taken branch
8408 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8409 ba[i]=start+i*4+8; // Ignore never taken branch
8410 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8411 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8412 else ba[i]=-1;
8413 /* Is this the end of the block? */
8414 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8415 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8416 done=2;
57871462 8417 }
8418 else {
8419 if(stop_after_jal) done=1;
8420 // Stop on BREAK
8421 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8422 }
8423 // Don't recompile stuff that's already compiled
8424 if(check_addr(start+i*4+4)) done=1;
8425 // Don't get too close to the limit
8426 if(i>MAXBLOCK/2) done=1;
8427 }
75dec299 8428 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8429 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8430 if(done==2) {
8431 // Does the block continue due to a branch?
8432 for(j=i-1;j>=0;j--)
8433 {
8434 if(ba[j]==start+i*4+4) done=j=0;
8435 if(ba[j]==start+i*4+8) done=j=0;
8436 }
8437 }
75dec299 8438 //assert(i<MAXBLOCK-1);
57871462 8439 if(start+i*4==pagelimit-4) done=1;
8440 assert(start+i*4<pagelimit);
8441 if (i==MAXBLOCK-1) done=1;
8442 // Stop if we're compiling junk
8443 if(itype[i]==NI&&opcode[i]==0x11) {
8444 done=stop_after_jal=1;
8445 printf("Disabled speculative precompilation\n");
8446 }
8447 }
8448 slen=i;
8449 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8450 if(start+i*4==pagelimit) {
8451 itype[i-1]=SPAN;
8452 }
8453 }
8454 assert(slen>0);
8455
8456 /* Pass 2 - Register dependencies and branch targets */
8457
8458 unneeded_registers(0,slen-1,0);
8459
8460 /* Pass 3 - Register allocation */
8461
8462 struct regstat current; // Current register allocations/status
8463 current.is32=1;
8464 current.dirty=0;
8465 current.u=unneeded_reg[0];
8466 current.uu=unneeded_reg_upper[0];
8467 clear_all_regs(current.regmap);
8468 alloc_reg(&current,0,CCREG);
8469 dirty_reg(&current,CCREG);
8470 current.isconst=0;
8471 current.wasconst=0;
8472 int ds=0;
8473 int cc=0;
8474 int hr;
8475
8476 provisional_32bit();
8477
8478 if((u_int)addr&1) {
8479 // First instruction is delay slot
8480 cc=-1;
8481 bt[1]=1;
8482 ds=1;
8483 unneeded_reg[0]=1;
8484 unneeded_reg_upper[0]=1;
8485 current.regmap[HOST_BTREG]=BTREG;
8486 }
8487
8488 for(i=0;i<slen;i++)
8489 {
8490 if(bt[i])
8491 {
8492 int hr;
8493 for(hr=0;hr<HOST_REGS;hr++)
8494 {
8495 // Is this really necessary?
8496 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8497 }
8498 current.isconst=0;
8499 }
8500 if(i>1)
8501 {
8502 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8503 {
8504 if(rs1[i-2]==0||rs2[i-2]==0)
8505 {
8506 if(rs1[i-2]) {
8507 current.is32|=1LL<<rs1[i-2];
8508 int hr=get_reg(current.regmap,rs1[i-2]|64);
8509 if(hr>=0) current.regmap[hr]=-1;
8510 }
8511 if(rs2[i-2]) {
8512 current.is32|=1LL<<rs2[i-2];
8513 int hr=get_reg(current.regmap,rs2[i-2]|64);
8514 if(hr>=0) current.regmap[hr]=-1;
8515 }
8516 }
8517 }
8518 }
8519 // If something jumps here with 64-bit values
8520 // then promote those registers to 64 bits
8521 if(bt[i])
8522 {
8523 uint64_t temp_is32=current.is32;
8524 for(j=i-1;j>=0;j--)
8525 {
8526 if(ba[j]==start+i*4)
8527 temp_is32&=branch_regs[j].is32;
8528 }
8529 for(j=i;j<slen;j++)
8530 {
8531 if(ba[j]==start+i*4)
8532 //temp_is32=1;
8533 temp_is32&=p32[j];
8534 }
8535 if(temp_is32!=current.is32) {
8536 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8537 #ifdef DESTRUCTIVE_WRITEBACK
8538 for(hr=0;hr<HOST_REGS;hr++)
8539 {
8540 int r=current.regmap[hr];
8541 if(r>0&&r<64)
8542 {
8543 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8544 temp_is32|=1LL<<r;
8545 //printf("restore %d\n",r);
8546 }
8547 }
8548 }
8549 #endif
8550 current.is32=temp_is32;
8551 }
8552 }
24385cae 8553#ifdef FORCE32
8554 memset(p32, 0xff, sizeof(p32));
8555 current.is32=-1LL;
8556#endif
8557
57871462 8558 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8559 regs[i].wasconst=current.isconst;
8560 regs[i].was32=current.is32;
8561 regs[i].wasdirty=current.dirty;
8562 #ifdef DESTRUCTIVE_WRITEBACK
8563 // To change a dirty register from 32 to 64 bits, we must write
8564 // it out during the previous cycle (for branches, 2 cycles)
8565 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8566 {
8567 uint64_t temp_is32=current.is32;
8568 for(j=i-1;j>=0;j--)
8569 {
8570 if(ba[j]==start+i*4+4)
8571 temp_is32&=branch_regs[j].is32;
8572 }
8573 for(j=i;j<slen;j++)
8574 {
8575 if(ba[j]==start+i*4+4)
8576 //temp_is32=1;
8577 temp_is32&=p32[j];
8578 }
8579 if(temp_is32!=current.is32) {
8580 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8581 for(hr=0;hr<HOST_REGS;hr++)
8582 {
8583 int r=current.regmap[hr];
8584 if(r>0)
8585 {
8586 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8587 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8588 {
8589 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8590 {
8591 //printf("dump %d/r%d\n",hr,r);
8592 current.regmap[hr]=-1;
8593 if(get_reg(current.regmap,r|64)>=0)
8594 current.regmap[get_reg(current.regmap,r|64)]=-1;
8595 }
8596 }
8597 }
8598 }
8599 }
8600 }
8601 }
8602 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8603 {
8604 uint64_t temp_is32=current.is32;
8605 for(j=i-1;j>=0;j--)
8606 {
8607 if(ba[j]==start+i*4+8)
8608 temp_is32&=branch_regs[j].is32;
8609 }
8610 for(j=i;j<slen;j++)
8611 {
8612 if(ba[j]==start+i*4+8)
8613 //temp_is32=1;
8614 temp_is32&=p32[j];
8615 }
8616 if(temp_is32!=current.is32) {
8617 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8618 for(hr=0;hr<HOST_REGS;hr++)
8619 {
8620 int r=current.regmap[hr];
8621 if(r>0)
8622 {
8623 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8624 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8625 {
8626 //printf("dump %d/r%d\n",hr,r);
8627 current.regmap[hr]=-1;
8628 if(get_reg(current.regmap,r|64)>=0)
8629 current.regmap[get_reg(current.regmap,r|64)]=-1;
8630 }
8631 }
8632 }
8633 }
8634 }
8635 }
8636 #endif
8637 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8638 if(i+1<slen) {
8639 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8640 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8641 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8642 current.u|=1;
8643 current.uu|=1;
8644 } else {
8645 current.u=1;
8646 current.uu=1;
8647 }
8648 } else {
8649 if(i+1<slen) {
8650 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8651 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8652 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8653 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8654 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8655 current.u|=1;
8656 current.uu|=1;
8657 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8658 }
8659 is_ds[i]=ds;
8660 if(ds) {
8661 ds=0; // Skip delay slot, already allocated as part of branch
8662 // ...but we need to alloc it in case something jumps here
8663 if(i+1<slen) {
8664 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8665 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8666 }else{
8667 current.u=branch_unneeded_reg[i-1];
8668 current.uu=branch_unneeded_reg_upper[i-1];
8669 }
8670 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8671 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8672 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8673 current.u|=1;
8674 current.uu|=1;
8675 struct regstat temp;
8676 memcpy(&temp,&current,sizeof(current));
8677 temp.wasdirty=temp.dirty;
8678 temp.was32=temp.is32;
8679 // TODO: Take into account unconditional branches, as below
8680 delayslot_alloc(&temp,i);
8681 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8682 regs[i].wasdirty=temp.wasdirty;
8683 regs[i].was32=temp.was32;
8684 regs[i].dirty=temp.dirty;
8685 regs[i].is32=temp.is32;
8686 regs[i].isconst=0;
8687 regs[i].wasconst=0;
8688 current.isconst=0;
8689 // Create entry (branch target) regmap
8690 for(hr=0;hr<HOST_REGS;hr++)
8691 {
8692 int r=temp.regmap[hr];
8693 if(r>=0) {
8694 if(r!=regmap_pre[i][hr]) {
8695 regs[i].regmap_entry[hr]=-1;
8696 }
8697 else
8698 {
8699 if(r<64){
8700 if((current.u>>r)&1) {
8701 regs[i].regmap_entry[hr]=-1;
8702 regs[i].regmap[hr]=-1;
8703 //Don't clear regs in the delay slot as the branch might need them
8704 //current.regmap[hr]=-1;
8705 }else
8706 regs[i].regmap_entry[hr]=r;
8707 }
8708 else {
8709 if((current.uu>>(r&63))&1) {
8710 regs[i].regmap_entry[hr]=-1;
8711 regs[i].regmap[hr]=-1;
8712 //Don't clear regs in the delay slot as the branch might need them
8713 //current.regmap[hr]=-1;
8714 }else
8715 regs[i].regmap_entry[hr]=r;
8716 }
8717 }
8718 } else {
8719 // First instruction expects CCREG to be allocated
8720 if(i==0&&hr==HOST_CCREG)
8721 regs[i].regmap_entry[hr]=CCREG;
8722 else
8723 regs[i].regmap_entry[hr]=-1;
8724 }
8725 }
8726 }
8727 else { // Not delay slot
8728 switch(itype[i]) {
8729 case UJUMP:
8730 //current.isconst=0; // DEBUG
8731 //current.wasconst=0; // DEBUG
8732 //regs[i].wasconst=0; // DEBUG
8733 clear_const(&current,rt1[i]);
8734 alloc_cc(&current,i);
8735 dirty_reg(&current,CCREG);
8736 if (rt1[i]==31) {
8737 alloc_reg(&current,i,31);
8738 dirty_reg(&current,31);
68b3faee 8739 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
076655d1 8740 assert(rt1[i+1]!=rt1[i]);
57871462 8741 #ifdef REG_PREFETCH
8742 alloc_reg(&current,i,PTEMP);
8743 #endif
8744 //current.is32|=1LL<<rt1[i];
8745 }
8746 delayslot_alloc(&current,i+1);
8747 //current.isconst=0; // DEBUG
8748 ds=1;
8749 //printf("i=%d, isconst=%x\n",i,current.isconst);
8750 break;
8751 case RJUMP:
8752 //current.isconst=0;
8753 //current.wasconst=0;
8754 //regs[i].wasconst=0;
8755 clear_const(&current,rs1[i]);
8756 clear_const(&current,rt1[i]);
8757 alloc_cc(&current,i);
8758 dirty_reg(&current,CCREG);
8759 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8760 alloc_reg(&current,i,rs1[i]);
5067f341 8761 if (rt1[i]!=0) {
8762 alloc_reg(&current,i,rt1[i]);
8763 dirty_reg(&current,rt1[i]);
68b3faee 8764 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8765 assert(rt1[i+1]!=rt1[i]);
57871462 8766 #ifdef REG_PREFETCH
8767 alloc_reg(&current,i,PTEMP);
8768 #endif
8769 }
8770 #ifdef USE_MINI_HT
8771 if(rs1[i]==31) { // JALR
8772 alloc_reg(&current,i,RHASH);
8773 #ifndef HOST_IMM_ADDR32
8774 alloc_reg(&current,i,RHTBL);
8775 #endif
8776 }
8777 #endif
8778 delayslot_alloc(&current,i+1);
8779 } else {
8780 // The delay slot overwrites our source register,
8781 // allocate a temporary register to hold the old value.
8782 current.isconst=0;
8783 current.wasconst=0;
8784 regs[i].wasconst=0;
8785 delayslot_alloc(&current,i+1);
8786 current.isconst=0;
8787 alloc_reg(&current,i,RTEMP);
8788 }
8789 //current.isconst=0; // DEBUG
8790 ds=1;
8791 break;
8792 case CJUMP:
8793 //current.isconst=0;
8794 //current.wasconst=0;
8795 //regs[i].wasconst=0;
8796 clear_const(&current,rs1[i]);
8797 clear_const(&current,rs2[i]);
8798 if((opcode[i]&0x3E)==4) // BEQ/BNE
8799 {
8800 alloc_cc(&current,i);
8801 dirty_reg(&current,CCREG);
8802 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8803 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8804 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8805 {
8806 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8807 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8808 }
8809 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8810 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8811 // The delay slot overwrites one of our conditions.
8812 // Allocate the branch condition registers instead.
8813 // Note that such a sequence of instructions could
8814 // be considered a bug since the branch can not be
8815 // re-executed if an exception occurs.
8816 current.isconst=0;
8817 current.wasconst=0;
8818 regs[i].wasconst=0;
8819 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8820 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8821 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8822 {
8823 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8824 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8825 }
8826 }
8827 else delayslot_alloc(&current,i+1);
8828 }
8829 else
8830 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8831 {
8832 alloc_cc(&current,i);
8833 dirty_reg(&current,CCREG);
8834 alloc_reg(&current,i,rs1[i]);
8835 if(!(current.is32>>rs1[i]&1))
8836 {
8837 alloc_reg64(&current,i,rs1[i]);
8838 }
8839 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8840 // The delay slot overwrites one of our conditions.
8841 // Allocate the branch condition registers instead.
8842 // Note that such a sequence of instructions could
8843 // be considered a bug since the branch can not be
8844 // re-executed if an exception occurs.
8845 current.isconst=0;
8846 current.wasconst=0;
8847 regs[i].wasconst=0;
8848 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8849 if(!((current.is32>>rs1[i])&1))
8850 {
8851 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8852 }
8853 }
8854 else delayslot_alloc(&current,i+1);
8855 }
8856 else
8857 // Don't alloc the delay slot yet because we might not execute it
8858 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8859 {
8860 current.isconst=0;
8861 current.wasconst=0;
8862 regs[i].wasconst=0;
8863 alloc_cc(&current,i);
8864 dirty_reg(&current,CCREG);
8865 alloc_reg(&current,i,rs1[i]);
8866 alloc_reg(&current,i,rs2[i]);
8867 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8868 {
8869 alloc_reg64(&current,i,rs1[i]);
8870 alloc_reg64(&current,i,rs2[i]);
8871 }
8872 }
8873 else
8874 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8875 {
8876 current.isconst=0;
8877 current.wasconst=0;
8878 regs[i].wasconst=0;
8879 alloc_cc(&current,i);
8880 dirty_reg(&current,CCREG);
8881 alloc_reg(&current,i,rs1[i]);
8882 if(!(current.is32>>rs1[i]&1))
8883 {
8884 alloc_reg64(&current,i,rs1[i]);
8885 }
8886 }
8887 ds=1;
8888 //current.isconst=0;
8889 break;
8890 case SJUMP:
8891 //current.isconst=0;
8892 //current.wasconst=0;
8893 //regs[i].wasconst=0;
8894 clear_const(&current,rs1[i]);
8895 clear_const(&current,rt1[i]);
8896 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8897 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8898 {
8899 alloc_cc(&current,i);
8900 dirty_reg(&current,CCREG);
8901 alloc_reg(&current,i,rs1[i]);
8902 if(!(current.is32>>rs1[i]&1))
8903 {
8904 alloc_reg64(&current,i,rs1[i]);
8905 }
8906 if (rt1[i]==31) { // BLTZAL/BGEZAL
8907 alloc_reg(&current,i,31);
8908 dirty_reg(&current,31);
57871462 8909 //#ifdef REG_PREFETCH
8910 //alloc_reg(&current,i,PTEMP);
8911 //#endif
8912 //current.is32|=1LL<<rt1[i];
8913 }
8914 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8915 // The delay slot overwrites the branch condition.
8916 // Allocate the branch condition registers instead.
8917 // Note that such a sequence of instructions could
8918 // be considered a bug since the branch can not be
8919 // re-executed if an exception occurs.
8920 current.isconst=0;
8921 current.wasconst=0;
8922 regs[i].wasconst=0;
8923 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8924 if(!((current.is32>>rs1[i])&1))
8925 {
8926 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8927 }
8928 }
8929 else delayslot_alloc(&current,i+1);
8930 }
8931 else
8932 // Don't alloc the delay slot yet because we might not execute it
8933 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8934 {
8935 current.isconst=0;
8936 current.wasconst=0;
8937 regs[i].wasconst=0;
8938 alloc_cc(&current,i);
8939 dirty_reg(&current,CCREG);
8940 alloc_reg(&current,i,rs1[i]);
8941 if(!(current.is32>>rs1[i]&1))
8942 {
8943 alloc_reg64(&current,i,rs1[i]);
8944 }
8945 }
8946 ds=1;
8947 //current.isconst=0;
8948 break;
8949 case FJUMP:
8950 current.isconst=0;
8951 current.wasconst=0;
8952 regs[i].wasconst=0;
8953 if(likely[i]==0) // BC1F/BC1T
8954 {
8955 // TODO: Theoretically we can run out of registers here on x86.
8956 // The delay slot can allocate up to six, and we need to check
8957 // CSREG before executing the delay slot. Possibly we can drop
8958 // the cycle count and then reload it after checking that the
8959 // FPU is in a usable state, or don't do out-of-order execution.
8960 alloc_cc(&current,i);
8961 dirty_reg(&current,CCREG);
8962 alloc_reg(&current,i,FSREG);
8963 alloc_reg(&current,i,CSREG);
8964 if(itype[i+1]==FCOMP) {
8965 // The delay slot overwrites the branch condition.
8966 // Allocate the branch condition registers instead.
8967 // Note that such a sequence of instructions could
8968 // be considered a bug since the branch can not be
8969 // re-executed if an exception occurs.
8970 alloc_cc(&current,i);
8971 dirty_reg(&current,CCREG);
8972 alloc_reg(&current,i,CSREG);
8973 alloc_reg(&current,i,FSREG);
8974 }
8975 else {
8976 delayslot_alloc(&current,i+1);
8977 alloc_reg(&current,i+1,CSREG);
8978 }
8979 }
8980 else
8981 // Don't alloc the delay slot yet because we might not execute it
8982 if(likely[i]) // BC1FL/BC1TL
8983 {
8984 alloc_cc(&current,i);
8985 dirty_reg(&current,CCREG);
8986 alloc_reg(&current,i,CSREG);
8987 alloc_reg(&current,i,FSREG);
8988 }
8989 ds=1;
8990 current.isconst=0;
8991 break;
8992 case IMM16:
8993 imm16_alloc(&current,i);
8994 break;
8995 case LOAD:
8996 case LOADLR:
8997 load_alloc(&current,i);
8998 break;
8999 case STORE:
9000 case STORELR:
9001 store_alloc(&current,i);
9002 break;
9003 case ALU:
9004 alu_alloc(&current,i);
9005 break;
9006 case SHIFT:
9007 shift_alloc(&current,i);
9008 break;
9009 case MULTDIV:
9010 multdiv_alloc(&current,i);
9011 break;
9012 case SHIFTIMM:
9013 shiftimm_alloc(&current,i);
9014 break;
9015 case MOV:
9016 mov_alloc(&current,i);
9017 break;
9018 case COP0:
9019 cop0_alloc(&current,i);
9020 break;
9021 case COP1:
b9b61529 9022 case COP2:
57871462 9023 cop1_alloc(&current,i);
9024 break;
9025 case C1LS:
9026 c1ls_alloc(&current,i);
9027 break;
b9b61529 9028 case C2LS:
9029 c2ls_alloc(&current,i);
9030 break;
9031 case C2OP:
9032 c2op_alloc(&current,i);
9033 break;
57871462 9034 case FCONV:
9035 fconv_alloc(&current,i);
9036 break;
9037 case FLOAT:
9038 float_alloc(&current,i);
9039 break;
9040 case FCOMP:
9041 fcomp_alloc(&current,i);
9042 break;
9043 case SYSCALL:
7139f3c8 9044 case HLECALL:
1e973cb0 9045 case INTCALL:
57871462 9046 syscall_alloc(&current,i);
9047 break;
9048 case SPAN:
9049 pagespan_alloc(&current,i);
9050 break;
9051 }
9052
9053 // Drop the upper half of registers that have become 32-bit
9054 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9055 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9056 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9057 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9058 current.uu|=1;
9059 } else {
9060 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9061 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9062 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9063 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9064 current.uu|=1;
9065 }
9066
9067 // Create entry (branch target) regmap
9068 for(hr=0;hr<HOST_REGS;hr++)
9069 {
9070 int r,or,er;
9071 r=current.regmap[hr];
9072 if(r>=0) {
9073 if(r!=regmap_pre[i][hr]) {
9074 // TODO: delay slot (?)
9075 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9076 if(or<0||(r&63)>=TEMPREG){
9077 regs[i].regmap_entry[hr]=-1;
9078 }
9079 else
9080 {
9081 // Just move it to a different register
9082 regs[i].regmap_entry[hr]=r;
9083 // If it was dirty before, it's still dirty
9084 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9085 }
9086 }
9087 else
9088 {
9089 // Unneeded
9090 if(r==0){
9091 regs[i].regmap_entry[hr]=0;
9092 }
9093 else
9094 if(r<64){
9095 if((current.u>>r)&1) {
9096 regs[i].regmap_entry[hr]=-1;
9097 //regs[i].regmap[hr]=-1;
9098 current.regmap[hr]=-1;
9099 }else
9100 regs[i].regmap_entry[hr]=r;
9101 }
9102 else {
9103 if((current.uu>>(r&63))&1) {
9104 regs[i].regmap_entry[hr]=-1;
9105 //regs[i].regmap[hr]=-1;
9106 current.regmap[hr]=-1;
9107 }else
9108 regs[i].regmap_entry[hr]=r;
9109 }
9110 }
9111 } else {
9112 // Branches expect CCREG to be allocated at the target
9113 if(regmap_pre[i][hr]==CCREG)
9114 regs[i].regmap_entry[hr]=CCREG;
9115 else
9116 regs[i].regmap_entry[hr]=-1;
9117 }
9118 }
9119 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9120 }
9121 /* Branch post-alloc */
9122 if(i>0)
9123 {
9124 current.was32=current.is32;
9125 current.wasdirty=current.dirty;
9126 switch(itype[i-1]) {
9127 case UJUMP:
9128 memcpy(&branch_regs[i-1],&current,sizeof(current));
9129 branch_regs[i-1].isconst=0;
9130 branch_regs[i-1].wasconst=0;
9131 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9132 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9133 alloc_cc(&branch_regs[i-1],i-1);
9134 dirty_reg(&branch_regs[i-1],CCREG);
9135 if(rt1[i-1]==31) { // JAL
9136 alloc_reg(&branch_regs[i-1],i-1,31);
9137 dirty_reg(&branch_regs[i-1],31);
9138 branch_regs[i-1].is32|=1LL<<31;
9139 }
9140 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9141 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9142 break;
9143 case RJUMP:
9144 memcpy(&branch_regs[i-1],&current,sizeof(current));
9145 branch_regs[i-1].isconst=0;
9146 branch_regs[i-1].wasconst=0;
9147 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9148 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9149 alloc_cc(&branch_regs[i-1],i-1);
9150 dirty_reg(&branch_regs[i-1],CCREG);
9151 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9152 if(rt1[i-1]!=0) { // JALR
9153 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9154 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9155 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9156 }
9157 #ifdef USE_MINI_HT
9158 if(rs1[i-1]==31) { // JALR
9159 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9160 #ifndef HOST_IMM_ADDR32
9161 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9162 #endif
9163 }
9164 #endif
9165 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9166 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9167 break;
9168 case CJUMP:
9169 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9170 {
9171 alloc_cc(&current,i-1);
9172 dirty_reg(&current,CCREG);
9173 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9174 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9175 // The delay slot overwrote one of our conditions
9176 // Delay slot goes after the test (in order)
9177 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9178 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9179 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9180 current.u|=1;
9181 current.uu|=1;
9182 delayslot_alloc(&current,i);
9183 current.isconst=0;
9184 }
9185 else
9186 {
9187 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9188 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9189 // Alloc the branch condition registers
9190 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9191 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9192 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9193 {
9194 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9195 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9196 }
9197 }
9198 memcpy(&branch_regs[i-1],&current,sizeof(current));
9199 branch_regs[i-1].isconst=0;
9200 branch_regs[i-1].wasconst=0;
9201 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9202 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9203 }
9204 else
9205 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9206 {
9207 alloc_cc(&current,i-1);
9208 dirty_reg(&current,CCREG);
9209 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9210 // The delay slot overwrote the branch condition
9211 // Delay slot goes after the test (in order)
9212 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9213 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9214 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9215 current.u|=1;
9216 current.uu|=1;
9217 delayslot_alloc(&current,i);
9218 current.isconst=0;
9219 }
9220 else
9221 {
9222 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9223 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9224 // Alloc the branch condition register
9225 alloc_reg(&current,i-1,rs1[i-1]);
9226 if(!(current.is32>>rs1[i-1]&1))
9227 {
9228 alloc_reg64(&current,i-1,rs1[i-1]);
9229 }
9230 }
9231 memcpy(&branch_regs[i-1],&current,sizeof(current));
9232 branch_regs[i-1].isconst=0;
9233 branch_regs[i-1].wasconst=0;
9234 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9235 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9236 }
9237 else
9238 // Alloc the delay slot in case the branch is taken
9239 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9240 {
9241 memcpy(&branch_regs[i-1],&current,sizeof(current));
9242 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9243 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9244 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9245 alloc_cc(&branch_regs[i-1],i);
9246 dirty_reg(&branch_regs[i-1],CCREG);
9247 delayslot_alloc(&branch_regs[i-1],i);
9248 branch_regs[i-1].isconst=0;
9249 alloc_reg(&current,i,CCREG); // Not taken path
9250 dirty_reg(&current,CCREG);
9251 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9252 }
9253 else
9254 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9255 {
9256 memcpy(&branch_regs[i-1],&current,sizeof(current));
9257 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9258 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9259 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9260 alloc_cc(&branch_regs[i-1],i);
9261 dirty_reg(&branch_regs[i-1],CCREG);
9262 delayslot_alloc(&branch_regs[i-1],i);
9263 branch_regs[i-1].isconst=0;
9264 alloc_reg(&current,i,CCREG); // Not taken path
9265 dirty_reg(&current,CCREG);
9266 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9267 }
9268 break;
9269 case SJUMP:
9270 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9271 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9272 {
9273 alloc_cc(&current,i-1);
9274 dirty_reg(&current,CCREG);
9275 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9276 // The delay slot overwrote the branch condition
9277 // Delay slot goes after the test (in order)
9278 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9279 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9280 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9281 current.u|=1;
9282 current.uu|=1;
9283 delayslot_alloc(&current,i);
9284 current.isconst=0;
9285 }
9286 else
9287 {
9288 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9289 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9290 // Alloc the branch condition register
9291 alloc_reg(&current,i-1,rs1[i-1]);
9292 if(!(current.is32>>rs1[i-1]&1))
9293 {
9294 alloc_reg64(&current,i-1,rs1[i-1]);
9295 }
9296 }
9297 memcpy(&branch_regs[i-1],&current,sizeof(current));
9298 branch_regs[i-1].isconst=0;
9299 branch_regs[i-1].wasconst=0;
9300 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9301 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9302 }
9303 else
9304 // Alloc the delay slot in case the branch is taken
9305 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9306 {
9307 memcpy(&branch_regs[i-1],&current,sizeof(current));
9308 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9309 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9310 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9311 alloc_cc(&branch_regs[i-1],i);
9312 dirty_reg(&branch_regs[i-1],CCREG);
9313 delayslot_alloc(&branch_regs[i-1],i);
9314 branch_regs[i-1].isconst=0;
9315 alloc_reg(&current,i,CCREG); // Not taken path
9316 dirty_reg(&current,CCREG);
9317 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9318 }
9319 // FIXME: BLTZAL/BGEZAL
9320 if(opcode2[i-1]&0x10) { // BxxZAL
9321 alloc_reg(&branch_regs[i-1],i-1,31);
9322 dirty_reg(&branch_regs[i-1],31);
9323 branch_regs[i-1].is32|=1LL<<31;
9324 }
9325 break;
9326 case FJUMP:
9327 if(likely[i-1]==0) // BC1F/BC1T
9328 {
9329 alloc_cc(&current,i-1);
9330 dirty_reg(&current,CCREG);
9331 if(itype[i]==FCOMP) {
9332 // The delay slot overwrote the branch condition
9333 // Delay slot goes after the test (in order)
9334 delayslot_alloc(&current,i);
9335 current.isconst=0;
9336 }
9337 else
9338 {
9339 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9340 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9341 // Alloc the branch condition register
9342 alloc_reg(&current,i-1,FSREG);
9343 }
9344 memcpy(&branch_regs[i-1],&current,sizeof(current));
9345 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9346 }
9347 else // BC1FL/BC1TL
9348 {
9349 // Alloc the delay slot in case the branch is taken
9350 memcpy(&branch_regs[i-1],&current,sizeof(current));
9351 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9352 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9353 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9354 alloc_cc(&branch_regs[i-1],i);
9355 dirty_reg(&branch_regs[i-1],CCREG);
9356 delayslot_alloc(&branch_regs[i-1],i);
9357 branch_regs[i-1].isconst=0;
9358 alloc_reg(&current,i,CCREG); // Not taken path
9359 dirty_reg(&current,CCREG);
9360 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9361 }
9362 break;
9363 }
9364
9365 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9366 {
9367 if(rt1[i-1]==31) // JAL/JALR
9368 {
9369 // Subroutine call will return here, don't alloc any registers
9370 current.is32=1;
9371 current.dirty=0;
9372 clear_all_regs(current.regmap);
9373 alloc_reg(&current,i,CCREG);
9374 dirty_reg(&current,CCREG);
9375 }
9376 else if(i+1<slen)
9377 {
9378 // Internal branch will jump here, match registers to caller
9379 current.is32=0x3FFFFFFFFLL;
9380 current.dirty=0;
9381 clear_all_regs(current.regmap);
9382 alloc_reg(&current,i,CCREG);
9383 dirty_reg(&current,CCREG);
9384 for(j=i-1;j>=0;j--)
9385 {
9386 if(ba[j]==start+i*4+4) {
9387 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9388 current.is32=branch_regs[j].is32;
9389 current.dirty=branch_regs[j].dirty;
9390 break;
9391 }
9392 }
9393 while(j>=0) {
9394 if(ba[j]==start+i*4+4) {
9395 for(hr=0;hr<HOST_REGS;hr++) {
9396 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9397 current.regmap[hr]=-1;
9398 }
9399 current.is32&=branch_regs[j].is32;
9400 current.dirty&=branch_regs[j].dirty;
9401 }
9402 }
9403 j--;
9404 }
9405 }
9406 }
9407 }
9408
9409 // Count cycles in between branches
9410 ccadj[i]=cc;
7139f3c8 9411 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9412 {
9413 cc=0;
9414 }
9415 else
9416 {
9417 cc++;
9418 }
9419
9420 flush_dirty_uppers(&current);
9421 if(!is_ds[i]) {
9422 regs[i].is32=current.is32;
9423 regs[i].dirty=current.dirty;
9424 regs[i].isconst=current.isconst;
9425 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9426 }
9427 for(hr=0;hr<HOST_REGS;hr++) {
9428 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9429 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9430 regs[i].wasconst&=~(1<<hr);
9431 }
9432 }
9433 }
9434 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9435 }
9436
9437 /* Pass 4 - Cull unused host registers */
9438
9439 uint64_t nr=0;
9440
9441 for (i=slen-1;i>=0;i--)
9442 {
9443 int hr;
9444 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9445 {
9446 if(ba[i]<start || ba[i]>=(start+slen*4))
9447 {
9448 // Branch out of this block, don't need anything
9449 nr=0;
9450 }
9451 else
9452 {
9453 // Internal branch
9454 // Need whatever matches the target
9455 nr=0;
9456 int t=(ba[i]-start)>>2;
9457 for(hr=0;hr<HOST_REGS;hr++)
9458 {
9459 if(regs[i].regmap_entry[hr]>=0) {
9460 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9461 }
9462 }
9463 }
9464 // Conditional branch may need registers for following instructions
9465 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9466 {
9467 if(i<slen-2) {
9468 nr|=needed_reg[i+2];
9469 for(hr=0;hr<HOST_REGS;hr++)
9470 {
9471 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9472 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9473 }
9474 }
9475 }
9476 // Don't need stuff which is overwritten
9477 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9478 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9479 // Merge in delay slot
9480 for(hr=0;hr<HOST_REGS;hr++)
9481 {
9482 if(!likely[i]) {
9483 // These are overwritten unless the branch is "likely"
9484 // and the delay slot is nullified if not taken
9485 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9486 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9487 }
9488 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9489 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9490 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9491 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9492 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9493 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9494 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9495 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9496 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9497 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9498 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9499 }
9500 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9501 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9502 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9503 }
b9b61529 9504 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9505 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9506 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9507 }
9508 }
9509 }
1e973cb0 9510 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9511 {
9512 // SYSCALL instruction (software interrupt)
9513 nr=0;
9514 }
9515 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9516 {
9517 // ERET instruction (return from interrupt)
9518 nr=0;
9519 }
9520 else // Non-branch
9521 {
9522 if(i<slen-1) {
9523 for(hr=0;hr<HOST_REGS;hr++) {
9524 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9525 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9526 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9527 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9528 }
9529 }
9530 }
9531 for(hr=0;hr<HOST_REGS;hr++)
9532 {
9533 // Overwritten registers are not needed
9534 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9535 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9536 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9537 // Source registers are needed
9538 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9539 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9540 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9541 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9542 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9543 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9544 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9545 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9546 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9547 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9548 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9549 }
9550 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9551 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9552 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9553 }
b9b61529 9554 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9555 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9556 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9557 }
9558 // Don't store a register immediately after writing it,
9559 // may prevent dual-issue.
9560 // But do so if this is a branch target, otherwise we
9561 // might have to load the register before the branch.
9562 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9563 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9564 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9565 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9566 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9567 }
9568 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9569 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9570 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9571 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9572 }
9573 }
9574 }
9575 // Cycle count is needed at branches. Assume it is needed at the target too.
9576 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9577 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9578 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9579 }
9580 // Save it
9581 needed_reg[i]=nr;
9582
9583 // Deallocate unneeded registers
9584 for(hr=0;hr<HOST_REGS;hr++)
9585 {
9586 if(!((nr>>hr)&1)) {
9587 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9588 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9589 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9590 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9591 {
9592 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9593 {
9594 if(likely[i]) {
9595 regs[i].regmap[hr]=-1;
9596 regs[i].isconst&=~(1<<hr);
9597 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9598 }
9599 }
9600 }
9601 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9602 {
9603 int d1=0,d2=0,map=0,temp=0;
9604 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9605 {
9606 d1=dep1[i+1];
9607 d2=dep2[i+1];
9608 }
9609 if(using_tlb) {
9610 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9611 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9612 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9613 map=TLREG;
9614 } else
b9b61529 9615 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9616 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9617 map=INVCP;
9618 }
9619 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9620 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9621 temp=FTEMP;
9622 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9623 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9624 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9625 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9626 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9627 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9628 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9629 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9630 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9631 regs[i].regmap[hr]!=map )
9632 {
9633 regs[i].regmap[hr]=-1;
9634 regs[i].isconst&=~(1<<hr);
9635 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9636 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9637 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9638 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9639 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9640 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9641 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9642 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9643 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9644 branch_regs[i].regmap[hr]!=map)
9645 {
9646 branch_regs[i].regmap[hr]=-1;
9647 branch_regs[i].regmap_entry[hr]=-1;
9648 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9649 {
9650 if(!likely[i]&&i<slen-2) {
9651 regmap_pre[i+2][hr]=-1;
9652 }
9653 }
9654 }
9655 }
9656 }
9657 else
9658 {
9659 // Non-branch
9660 if(i>0)
9661 {
9662 int d1=0,d2=0,map=-1,temp=-1;
9663 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9664 {
9665 d1=dep1[i];
9666 d2=dep2[i];
9667 }
9668 if(using_tlb) {
9669 if(itype[i]==LOAD || itype[i]==LOADLR ||
9670 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9671 itype[i]==C1LS || itype[i]==C2LS)
57871462 9672 map=TLREG;
b9b61529 9673 } else if(itype[i]==STORE || itype[i]==STORELR ||
9674 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9675 map=INVCP;
9676 }
9677 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9678 itype[i]==C1LS || itype[i]==C2LS)
57871462 9679 temp=FTEMP;
9680 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9681 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9682 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9683 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9684 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9685 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9686 {
9687 if(i<slen-1&&!is_ds[i]) {
9688 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9689 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9690 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9691 {
9692 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9693 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9694 }
9695 regmap_pre[i+1][hr]=-1;
9696 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9697 }
9698 regs[i].regmap[hr]=-1;
9699 regs[i].isconst&=~(1<<hr);
9700 }
9701 }
9702 }
9703 }
9704 }
9705 }
9706
9707 /* Pass 5 - Pre-allocate registers */
9708
9709 // If a register is allocated during a loop, try to allocate it for the
9710 // entire loop, if possible. This avoids loading/storing registers
9711 // inside of the loop.
9712
9713 signed char f_regmap[HOST_REGS];
9714 clear_all_regs(f_regmap);
9715 for(i=0;i<slen-1;i++)
9716 {
9717 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9718 {
9719 if(ba[i]>=start && ba[i]<(start+i*4))
9720 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9721 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9722 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9723 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9724 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9725 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9726 {
9727 int t=(ba[i]-start)>>2;
9728 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9729 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9730 for(hr=0;hr<HOST_REGS;hr++)
9731 {
9732 if(regs[i].regmap[hr]>64) {
9733 if(!((regs[i].dirty>>hr)&1))
9734 f_regmap[hr]=regs[i].regmap[hr];
9735 else f_regmap[hr]=-1;
9736 }
b372a952 9737 else if(regs[i].regmap[hr]>=0) {
9738 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9739 // dealloc old register
9740 int n;
9741 for(n=0;n<HOST_REGS;n++)
9742 {
9743 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9744 }
9745 // and alloc new one
9746 f_regmap[hr]=regs[i].regmap[hr];
9747 }
9748 }
57871462 9749 if(branch_regs[i].regmap[hr]>64) {
9750 if(!((branch_regs[i].dirty>>hr)&1))
9751 f_regmap[hr]=branch_regs[i].regmap[hr];
9752 else f_regmap[hr]=-1;
9753 }
b372a952 9754 else if(branch_regs[i].regmap[hr]>=0) {
9755 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9756 // dealloc old register
9757 int n;
9758 for(n=0;n<HOST_REGS;n++)
9759 {
9760 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9761 }
9762 // and alloc new one
9763 f_regmap[hr]=branch_regs[i].regmap[hr];
9764 }
9765 }
57871462 9766 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9767 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9768 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9769 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9770 {
9771 // Test both in case the delay slot is ooo,
9772 // could be done better...
9773 if(count_free_regs(branch_regs[i].regmap)<2
9774 ||count_free_regs(regs[i].regmap)<2)
9775 f_regmap[hr]=branch_regs[i].regmap[hr];
9776 }
9777 // Avoid dirty->clean transition
9778 // #ifdef DESTRUCTIVE_WRITEBACK here?
9779 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9780 if(f_regmap[hr]>0) {
9781 if(regs[t].regmap_entry[hr]<0) {
9782 int r=f_regmap[hr];
9783 for(j=t;j<=i;j++)
9784 {
9785 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9786 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9787 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9788 if(r>63) {
9789 // NB This can exclude the case where the upper-half
9790 // register is lower numbered than the lower-half
9791 // register. Not sure if it's worth fixing...
9792 if(get_reg(regs[j].regmap,r&63)<0) break;
9793 if(regs[j].is32&(1LL<<(r&63))) break;
9794 }
9795 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9796 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9797 int k;
9798 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9799 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9800 if(r>63) {
9801 if(get_reg(regs[i].regmap,r&63)<0) break;
9802 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9803 }
9804 k=i;
9805 while(k>1&&regs[k-1].regmap[hr]==-1) {
9806 if(itype[k-1]==STORE||itype[k-1]==STORELR
9807 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
b9b61529 9808 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9809 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 9810 if(count_free_regs(regs[k-1].regmap)<2) {
9811 //printf("no free regs for store %x\n",start+(k-1)*4);
9812 break;
9813 }
9814 }
9815 else
9816 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9817 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9818 //printf("no-match due to different register\n");
9819 break;
9820 }
9821 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9822 //printf("no-match due to branch\n");
9823 break;
9824 }
9825 // call/ret fast path assumes no registers allocated
9826 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9827 break;
9828 }
9829 if(r>63) {
9830 // NB This can exclude the case where the upper-half
9831 // register is lower numbered than the lower-half
9832 // register. Not sure if it's worth fixing...
9833 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9834 if(regs[k-1].is32&(1LL<<(r&63))) break;
9835 }
9836 k--;
9837 }
9838 if(i<slen-1) {
9839 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9840 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9841 //printf("bad match after branch\n");
9842 break;
9843 }
9844 }
9845 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9846 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9847 while(k<i) {
9848 regs[k].regmap_entry[hr]=f_regmap[hr];
9849 regs[k].regmap[hr]=f_regmap[hr];
9850 regmap_pre[k+1][hr]=f_regmap[hr];
9851 regs[k].wasdirty&=~(1<<hr);
9852 regs[k].dirty&=~(1<<hr);
9853 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9854 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9855 regs[k].wasconst&=~(1<<hr);
9856 regs[k].isconst&=~(1<<hr);
9857 k++;
9858 }
9859 }
9860 else {
9861 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9862 break;
9863 }
9864 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9865 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9866 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9867 regs[i].regmap_entry[hr]=f_regmap[hr];
9868 regs[i].regmap[hr]=f_regmap[hr];
9869 regs[i].wasdirty&=~(1<<hr);
9870 regs[i].dirty&=~(1<<hr);
9871 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9872 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9873 regs[i].wasconst&=~(1<<hr);
9874 regs[i].isconst&=~(1<<hr);
9875 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9876 branch_regs[i].wasdirty&=~(1<<hr);
9877 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9878 branch_regs[i].regmap[hr]=f_regmap[hr];
9879 branch_regs[i].dirty&=~(1<<hr);
9880 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9881 branch_regs[i].wasconst&=~(1<<hr);
9882 branch_regs[i].isconst&=~(1<<hr);
9883 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9884 regmap_pre[i+2][hr]=f_regmap[hr];
9885 regs[i+2].wasdirty&=~(1<<hr);
9886 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9887 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9888 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9889 }
9890 }
9891 }
9892 for(k=t;k<j;k++) {
9893 regs[k].regmap_entry[hr]=f_regmap[hr];
9894 regs[k].regmap[hr]=f_regmap[hr];
9895 regmap_pre[k+1][hr]=f_regmap[hr];
9896 regs[k+1].wasdirty&=~(1<<hr);
9897 regs[k].dirty&=~(1<<hr);
9898 regs[k].wasconst&=~(1<<hr);
9899 regs[k].isconst&=~(1<<hr);
9900 }
9901 if(regs[j].regmap[hr]==f_regmap[hr])
9902 regs[j].regmap_entry[hr]=f_regmap[hr];
9903 break;
9904 }
9905 if(j==i) break;
9906 if(regs[j].regmap[hr]>=0)
9907 break;
9908 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9909 //printf("no-match due to different register\n");
9910 break;
9911 }
9912 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9913 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9914 break;
9915 }
9916 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9917 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9918 ||itype[j]==FCOMP||itype[j]==FCONV
9919 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9920 if(count_free_regs(regs[j].regmap)<2) {
9921 //printf("No free regs for store %x\n",start+j*4);
9922 break;
9923 }
9924 }
9925 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9926 if(f_regmap[hr]>=64) {
9927 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9928 break;
9929 }
9930 else
9931 {
9932 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9933 break;
9934 }
9935 }
9936 }
9937 }
9938 }
9939 }
9940 }
9941 }
9942 }else{
9943 int count=0;
9944 for(hr=0;hr<HOST_REGS;hr++)
9945 {
9946 if(hr!=EXCLUDE_REG) {
9947 if(regs[i].regmap[hr]>64) {
9948 if(!((regs[i].dirty>>hr)&1))
9949 f_regmap[hr]=regs[i].regmap[hr];
9950 }
b372a952 9951 else if(regs[i].regmap[hr]>=0) {
9952 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9953 // dealloc old register
9954 int n;
9955 for(n=0;n<HOST_REGS;n++)
9956 {
9957 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9958 }
9959 // and alloc new one
9960 f_regmap[hr]=regs[i].regmap[hr];
9961 }
9962 }
57871462 9963 else if(regs[i].regmap[hr]<0) count++;
9964 }
9965 }
9966 // Try to restore cycle count at branch targets
9967 if(bt[i]) {
9968 for(j=i;j<slen-1;j++) {
9969 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9970 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9971 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9972 ||itype[j]==FCOMP||itype[j]==FCONV
9973 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9974 if(count_free_regs(regs[j].regmap)<2) {
9975 //printf("no free regs for store %x\n",start+j*4);
9976 break;
9977 }
9978 }
9979 else
9980 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9981 }
9982 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9983 int k=i;
9984 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9985 while(k<j) {
9986 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9987 regs[k].regmap[HOST_CCREG]=CCREG;
9988 regmap_pre[k+1][HOST_CCREG]=CCREG;
9989 regs[k+1].wasdirty|=1<<HOST_CCREG;
9990 regs[k].dirty|=1<<HOST_CCREG;
9991 regs[k].wasconst&=~(1<<HOST_CCREG);
9992 regs[k].isconst&=~(1<<HOST_CCREG);
9993 k++;
9994 }
9995 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9996 }
9997 // Work backwards from the branch target
9998 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9999 {
10000 //printf("Extend backwards\n");
10001 int k;
10002 k=i;
10003 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10004 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10005 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
b9b61529 10006 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10007 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 10008 if(count_free_regs(regs[k-1].regmap)<2) {
10009 //printf("no free regs for store %x\n",start+(k-1)*4);
10010 break;
10011 }
10012 }
10013 else
10014 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10015 k--;
10016 }
10017 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10018 //printf("Extend CC, %x ->\n",start+k*4);
10019 while(k<=i) {
10020 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10021 regs[k].regmap[HOST_CCREG]=CCREG;
10022 regmap_pre[k+1][HOST_CCREG]=CCREG;
10023 regs[k+1].wasdirty|=1<<HOST_CCREG;
10024 regs[k].dirty|=1<<HOST_CCREG;
10025 regs[k].wasconst&=~(1<<HOST_CCREG);
10026 regs[k].isconst&=~(1<<HOST_CCREG);
10027 k++;
10028 }
10029 }
10030 else {
10031 //printf("Fail Extend CC, %x ->\n",start+k*4);
10032 }
10033 }
10034 }
10035 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10036 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10037 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
b9b61529 10038 itype[i]!=FCONV&&itype[i]!=FCOMP&&
10039 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
57871462 10040 {
10041 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10042 }
10043 }
10044 }
10045
10046 // This allocates registers (if possible) one instruction prior
10047 // to use, which can avoid a load-use penalty on certain CPUs.
10048 for(i=0;i<slen-1;i++)
10049 {
10050 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10051 {
10052 if(!bt[i+1])
10053 {
b9b61529 10054 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10055 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10056 {
10057 if(rs1[i+1]) {
10058 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10059 {
10060 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10061 {
10062 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10063 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10064 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10065 regs[i].isconst&=~(1<<hr);
10066 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10067 constmap[i][hr]=constmap[i+1][hr];
10068 regs[i+1].wasdirty&=~(1<<hr);
10069 regs[i].dirty&=~(1<<hr);
10070 }
10071 }
10072 }
10073 if(rs2[i+1]) {
10074 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10075 {
10076 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10077 {
10078 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10079 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10080 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10081 regs[i].isconst&=~(1<<hr);
10082 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10083 constmap[i][hr]=constmap[i+1][hr];
10084 regs[i+1].wasdirty&=~(1<<hr);
10085 regs[i].dirty&=~(1<<hr);
10086 }
10087 }
10088 }
10089 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10090 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10091 {
10092 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10093 {
10094 regs[i].regmap[hr]=rs1[i+1];
10095 regmap_pre[i+1][hr]=rs1[i+1];
10096 regs[i+1].regmap_entry[hr]=rs1[i+1];
10097 regs[i].isconst&=~(1<<hr);
10098 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10099 constmap[i][hr]=constmap[i+1][hr];
10100 regs[i+1].wasdirty&=~(1<<hr);
10101 regs[i].dirty&=~(1<<hr);
10102 }
10103 }
10104 }
10105 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10106 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10107 {
10108 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10109 {
10110 regs[i].regmap[hr]=rs1[i+1];
10111 regmap_pre[i+1][hr]=rs1[i+1];
10112 regs[i+1].regmap_entry[hr]=rs1[i+1];
10113 regs[i].isconst&=~(1<<hr);
10114 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10115 constmap[i][hr]=constmap[i+1][hr];
10116 regs[i+1].wasdirty&=~(1<<hr);
10117 regs[i].dirty&=~(1<<hr);
10118 }
10119 }
10120 }
10121 #ifndef HOST_IMM_ADDR32
b9b61529 10122 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10123 hr=get_reg(regs[i+1].regmap,TLREG);
10124 if(hr>=0) {
10125 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10126 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10127 int nr;
10128 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10129 {
10130 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10131 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10132 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10133 regs[i].isconst&=~(1<<hr);
10134 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10135 constmap[i][hr]=constmap[i+1][hr];
10136 regs[i+1].wasdirty&=~(1<<hr);
10137 regs[i].dirty&=~(1<<hr);
10138 }
10139 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10140 {
10141 // move it to another register
10142 regs[i+1].regmap[hr]=-1;
10143 regmap_pre[i+2][hr]=-1;
10144 regs[i+1].regmap[nr]=TLREG;
10145 regmap_pre[i+2][nr]=TLREG;
10146 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10147 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10148 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10149 regs[i].isconst&=~(1<<nr);
10150 regs[i+1].isconst&=~(1<<nr);
10151 regs[i].dirty&=~(1<<nr);
10152 regs[i+1].wasdirty&=~(1<<nr);
10153 regs[i+1].dirty&=~(1<<nr);
10154 regs[i+2].wasdirty&=~(1<<nr);
10155 }
10156 }
10157 }
10158 }
10159 #endif
b9b61529 10160 if(itype[i+1]==STORE||itype[i+1]==STORELR
10161 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10162 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10163 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10164 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10165 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10166 assert(hr>=0);
10167 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10168 {
10169 regs[i].regmap[hr]=rs1[i+1];
10170 regmap_pre[i+1][hr]=rs1[i+1];
10171 regs[i+1].regmap_entry[hr]=rs1[i+1];
10172 regs[i].isconst&=~(1<<hr);
10173 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10174 constmap[i][hr]=constmap[i+1][hr];
10175 regs[i+1].wasdirty&=~(1<<hr);
10176 regs[i].dirty&=~(1<<hr);
10177 }
10178 }
10179 }
b9b61529 10180 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10181 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10182 int nr;
10183 hr=get_reg(regs[i+1].regmap,FTEMP);
10184 assert(hr>=0);
10185 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10186 {
10187 regs[i].regmap[hr]=rs1[i+1];
10188 regmap_pre[i+1][hr]=rs1[i+1];
10189 regs[i+1].regmap_entry[hr]=rs1[i+1];
10190 regs[i].isconst&=~(1<<hr);
10191 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10192 constmap[i][hr]=constmap[i+1][hr];
10193 regs[i+1].wasdirty&=~(1<<hr);
10194 regs[i].dirty&=~(1<<hr);
10195 }
10196 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10197 {
10198 // move it to another register
10199 regs[i+1].regmap[hr]=-1;
10200 regmap_pre[i+2][hr]=-1;
10201 regs[i+1].regmap[nr]=FTEMP;
10202 regmap_pre[i+2][nr]=FTEMP;
10203 regs[i].regmap[nr]=rs1[i+1];
10204 regmap_pre[i+1][nr]=rs1[i+1];
10205 regs[i+1].regmap_entry[nr]=rs1[i+1];
10206 regs[i].isconst&=~(1<<nr);
10207 regs[i+1].isconst&=~(1<<nr);
10208 regs[i].dirty&=~(1<<nr);
10209 regs[i+1].wasdirty&=~(1<<nr);
10210 regs[i+1].dirty&=~(1<<nr);
10211 regs[i+2].wasdirty&=~(1<<nr);
10212 }
10213 }
10214 }
b9b61529 10215 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10216 if(itype[i+1]==LOAD)
10217 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10218 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10219 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10220 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10221 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10222 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10223 }
10224 if(hr>=0&&regs[i].regmap[hr]<0) {
10225 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10226 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10227 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10228 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10229 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10230 regs[i].isconst&=~(1<<hr);
10231 regs[i+1].wasdirty&=~(1<<hr);
10232 regs[i].dirty&=~(1<<hr);
10233 }
10234 }
10235 }
10236 }
10237 }
10238 }
10239 }
10240
10241 /* Pass 6 - Optimize clean/dirty state */
10242 clean_registers(0,slen-1,1);
10243
10244 /* Pass 7 - Identify 32-bit registers */
10245
10246 provisional_r32();
10247
10248 u_int r32=0;
10249
10250 for (i=slen-1;i>=0;i--)
10251 {
10252 int hr;
10253 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10254 {
10255 if(ba[i]<start || ba[i]>=(start+slen*4))
10256 {
10257 // Branch out of this block, don't need anything
10258 r32=0;
10259 }
10260 else
10261 {
10262 // Internal branch
10263 // Need whatever matches the target
10264 // (and doesn't get overwritten by the delay slot instruction)
10265 r32=0;
10266 int t=(ba[i]-start)>>2;
10267 if(ba[i]>start+i*4) {
10268 // Forward branch
10269 if(!(requires_32bit[t]&~regs[i].was32))
10270 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10271 }else{
10272 // Backward branch
10273 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10274 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10275 if(!(pr32[t]&~regs[i].was32))
10276 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10277 }
10278 }
10279 // Conditional branch may need registers for following instructions
10280 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10281 {
10282 if(i<slen-2) {
10283 r32|=requires_32bit[i+2];
10284 r32&=regs[i].was32;
10285 // Mark this address as a branch target since it may be called
10286 // upon return from interrupt
10287 bt[i+2]=1;
10288 }
10289 }
10290 // Merge in delay slot
10291 if(!likely[i]) {
10292 // These are overwritten unless the branch is "likely"
10293 // and the delay slot is nullified if not taken
10294 r32&=~(1LL<<rt1[i+1]);
10295 r32&=~(1LL<<rt2[i+1]);
10296 }
10297 // Assume these are needed (delay slot)
10298 if(us1[i+1]>0)
10299 {
10300 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10301 }
10302 if(us2[i+1]>0)
10303 {
10304 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10305 }
10306 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10307 {
10308 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10309 }
10310 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10311 {
10312 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10313 }
10314 }
1e973cb0 10315 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10316 {
10317 // SYSCALL instruction (software interrupt)
10318 r32=0;
10319 }
10320 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10321 {
10322 // ERET instruction (return from interrupt)
10323 r32=0;
10324 }
10325 // Check 32 bits
10326 r32&=~(1LL<<rt1[i]);
10327 r32&=~(1LL<<rt2[i]);
10328 if(us1[i]>0)
10329 {
10330 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10331 }
10332 if(us2[i]>0)
10333 {
10334 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10335 }
10336 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10337 {
10338 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10339 }
10340 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10341 {
10342 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10343 }
10344 requires_32bit[i]=r32;
10345
10346 // Dirty registers which are 32-bit, require 32-bit input
10347 // as they will be written as 32-bit values
10348 for(hr=0;hr<HOST_REGS;hr++)
10349 {
10350 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10351 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10352 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10353 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10354 }
10355 }
10356 }
10357 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10358 }
10359
10360 if(itype[slen-1]==SPAN) {
10361 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10362 }
10363
10364 /* Debug/disassembly */
10365 if((void*)assem_debug==(void*)printf)
10366 for(i=0;i<slen;i++)
10367 {
10368 printf("U:");
10369 int r;
10370 for(r=1;r<=CCREG;r++) {
10371 if((unneeded_reg[i]>>r)&1) {
10372 if(r==HIREG) printf(" HI");
10373 else if(r==LOREG) printf(" LO");
10374 else printf(" r%d",r);
10375 }
10376 }
90ae6d4e 10377#ifndef FORCE32
57871462 10378 printf(" UU:");
10379 for(r=1;r<=CCREG;r++) {
10380 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10381 if(r==HIREG) printf(" HI");
10382 else if(r==LOREG) printf(" LO");
10383 else printf(" r%d",r);
10384 }
10385 }
10386 printf(" 32:");
10387 for(r=0;r<=CCREG;r++) {
10388 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10389 if((regs[i].was32>>r)&1) {
10390 if(r==CCREG) printf(" CC");
10391 else if(r==HIREG) printf(" HI");
10392 else if(r==LOREG) printf(" LO");
10393 else printf(" r%d",r);
10394 }
10395 }
90ae6d4e 10396#endif
57871462 10397 printf("\n");
10398 #if defined(__i386__) || defined(__x86_64__)
10399 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10400 #endif
10401 #ifdef __arm__
10402 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10403 #endif
10404 printf("needs: ");
10405 if(needed_reg[i]&1) printf("eax ");
10406 if((needed_reg[i]>>1)&1) printf("ecx ");
10407 if((needed_reg[i]>>2)&1) printf("edx ");
10408 if((needed_reg[i]>>3)&1) printf("ebx ");
10409 if((needed_reg[i]>>5)&1) printf("ebp ");
10410 if((needed_reg[i]>>6)&1) printf("esi ");
10411 if((needed_reg[i]>>7)&1) printf("edi ");
10412 printf("r:");
10413 for(r=0;r<=CCREG;r++) {
10414 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10415 if((requires_32bit[i]>>r)&1) {
10416 if(r==CCREG) printf(" CC");
10417 else if(r==HIREG) printf(" HI");
10418 else if(r==LOREG) printf(" LO");
10419 else printf(" r%d",r);
10420 }
10421 }
10422 printf("\n");
10423 /*printf("pr:");
10424 for(r=0;r<=CCREG;r++) {
10425 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10426 if((pr32[i]>>r)&1) {
10427 if(r==CCREG) printf(" CC");
10428 else if(r==HIREG) printf(" HI");
10429 else if(r==LOREG) printf(" LO");
10430 else printf(" r%d",r);
10431 }
10432 }
10433 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10434 printf("\n");*/
10435 #if defined(__i386__) || defined(__x86_64__)
10436 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10437 printf("dirty: ");
10438 if(regs[i].wasdirty&1) printf("eax ");
10439 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10440 if((regs[i].wasdirty>>2)&1) printf("edx ");
10441 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10442 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10443 if((regs[i].wasdirty>>6)&1) printf("esi ");
10444 if((regs[i].wasdirty>>7)&1) printf("edi ");
10445 #endif
10446 #ifdef __arm__
10447 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10448 printf("dirty: ");
10449 if(regs[i].wasdirty&1) printf("r0 ");
10450 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10451 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10452 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10453 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10454 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10455 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10456 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10457 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10458 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10459 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10460 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10461 #endif
10462 printf("\n");
10463 disassemble_inst(i);
10464 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10465 #if defined(__i386__) || defined(__x86_64__)
10466 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10467 if(regs[i].dirty&1) printf("eax ");
10468 if((regs[i].dirty>>1)&1) printf("ecx ");
10469 if((regs[i].dirty>>2)&1) printf("edx ");
10470 if((regs[i].dirty>>3)&1) printf("ebx ");
10471 if((regs[i].dirty>>5)&1) printf("ebp ");
10472 if((regs[i].dirty>>6)&1) printf("esi ");
10473 if((regs[i].dirty>>7)&1) printf("edi ");
10474 #endif
10475 #ifdef __arm__
10476 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10477 if(regs[i].dirty&1) printf("r0 ");
10478 if((regs[i].dirty>>1)&1) printf("r1 ");
10479 if((regs[i].dirty>>2)&1) printf("r2 ");
10480 if((regs[i].dirty>>3)&1) printf("r3 ");
10481 if((regs[i].dirty>>4)&1) printf("r4 ");
10482 if((regs[i].dirty>>5)&1) printf("r5 ");
10483 if((regs[i].dirty>>6)&1) printf("r6 ");
10484 if((regs[i].dirty>>7)&1) printf("r7 ");
10485 if((regs[i].dirty>>8)&1) printf("r8 ");
10486 if((regs[i].dirty>>9)&1) printf("r9 ");
10487 if((regs[i].dirty>>10)&1) printf("r10 ");
10488 if((regs[i].dirty>>12)&1) printf("r12 ");
10489 #endif
10490 printf("\n");
10491 if(regs[i].isconst) {
10492 printf("constants: ");
10493 #if defined(__i386__) || defined(__x86_64__)
10494 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10495 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10496 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10497 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10498 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10499 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10500 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10501 #endif
10502 #ifdef __arm__
10503 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10504 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10505 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10506 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10507 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10508 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10509 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10510 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10511 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10512 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10513 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10514 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10515 #endif
10516 printf("\n");
10517 }
90ae6d4e 10518#ifndef FORCE32
57871462 10519 printf(" 32:");
10520 for(r=0;r<=CCREG;r++) {
10521 if((regs[i].is32>>r)&1) {
10522 if(r==CCREG) printf(" CC");
10523 else if(r==HIREG) printf(" HI");
10524 else if(r==LOREG) printf(" LO");
10525 else printf(" r%d",r);
10526 }
10527 }
10528 printf("\n");
90ae6d4e 10529#endif
57871462 10530 /*printf(" p32:");
10531 for(r=0;r<=CCREG;r++) {
10532 if((p32[i]>>r)&1) {
10533 if(r==CCREG) printf(" CC");
10534 else if(r==HIREG) printf(" HI");
10535 else if(r==LOREG) printf(" LO");
10536 else printf(" r%d",r);
10537 }
10538 }
10539 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10540 else printf("\n");*/
10541 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10542 #if defined(__i386__) || defined(__x86_64__)
10543 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10544 if(branch_regs[i].dirty&1) printf("eax ");
10545 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10546 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10547 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10548 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10549 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10550 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10551 #endif
10552 #ifdef __arm__
10553 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10554 if(branch_regs[i].dirty&1) printf("r0 ");
10555 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10556 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10557 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10558 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10559 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10560 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10561 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10562 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10563 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10564 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10565 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10566 #endif
90ae6d4e 10567#ifndef FORCE32
57871462 10568 printf(" 32:");
10569 for(r=0;r<=CCREG;r++) {
10570 if((branch_regs[i].is32>>r)&1) {
10571 if(r==CCREG) printf(" CC");
10572 else if(r==HIREG) printf(" HI");
10573 else if(r==LOREG) printf(" LO");
10574 else printf(" r%d",r);
10575 }
10576 }
10577 printf("\n");
90ae6d4e 10578#endif
57871462 10579 }
10580 }
10581
10582 /* Pass 8 - Assembly */
10583 linkcount=0;stubcount=0;
10584 ds=0;is_delayslot=0;
10585 cop1_usable=0;
10586 uint64_t is32_pre=0;
10587 u_int dirty_pre=0;
10588 u_int beginning=(u_int)out;
10589 if((u_int)addr&1) {
10590 ds=1;
10591 pagespan_ds();
10592 }
9ad4d757 10593 u_int instr_addr0_override=0;
10594
10595#ifdef PCSX
10596 if (start == 0x80030000) {
10597 // nasty hack for fastbios thing
10598 instr_addr0_override=(u_int)out;
10599 emit_movimm(start,0);
10600 emit_readword((int)&pcaddr,1);
10601 emit_writeword(0,(int)&pcaddr);
10602 emit_cmp(0,1);
10603 emit_jne((int)new_dyna_leave);
10604 }
10605#endif
57871462 10606 for(i=0;i<slen;i++)
10607 {
10608 //if(ds) printf("ds: ");
10609 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10610 if(ds) {
10611 ds=0; // Skip delay slot
10612 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10613 instr_addr[i]=0;
10614 } else {
10615 #ifndef DESTRUCTIVE_WRITEBACK
10616 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10617 {
10618 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10619 unneeded_reg[i],unneeded_reg_upper[i]);
10620 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10621 unneeded_reg[i],unneeded_reg_upper[i]);
10622 }
10623 is32_pre=regs[i].is32;
10624 dirty_pre=regs[i].dirty;
10625 #endif
10626 // write back
10627 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10628 {
10629 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10630 unneeded_reg[i],unneeded_reg_upper[i]);
10631 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10632 }
10633 // branch target entry point
10634 instr_addr[i]=(u_int)out;
10635 assem_debug("<->\n");
10636 // load regs
10637 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10638 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10639 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10640 address_generation(i,&regs[i],regs[i].regmap_entry);
10641 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10642 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10643 {
10644 // Load the delay slot registers if necessary
10645 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10646 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10647 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10648 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10649 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10650 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10651 }
10652 else if(i+1<slen)
10653 {
10654 // Preload registers for following instruction
10655 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10656 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10657 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10658 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10659 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10660 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10661 }
10662 // TODO: if(is_ooo(i)) address_generation(i+1);
10663 if(itype[i]==CJUMP||itype[i]==FJUMP)
10664 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10665 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10666 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10667 if(bt[i]) cop1_usable=0;
10668 // assemble
10669 switch(itype[i]) {
10670 case ALU:
10671 alu_assemble(i,&regs[i]);break;
10672 case IMM16:
10673 imm16_assemble(i,&regs[i]);break;
10674 case SHIFT:
10675 shift_assemble(i,&regs[i]);break;
10676 case SHIFTIMM:
10677 shiftimm_assemble(i,&regs[i]);break;
10678 case LOAD:
10679 load_assemble(i,&regs[i]);break;
10680 case LOADLR:
10681 loadlr_assemble(i,&regs[i]);break;
10682 case STORE:
10683 store_assemble(i,&regs[i]);break;
10684 case STORELR:
10685 storelr_assemble(i,&regs[i]);break;
10686 case COP0:
10687 cop0_assemble(i,&regs[i]);break;
10688 case COP1:
10689 cop1_assemble(i,&regs[i]);break;
10690 case C1LS:
10691 c1ls_assemble(i,&regs[i]);break;
b9b61529 10692 case COP2:
10693 cop2_assemble(i,&regs[i]);break;
10694 case C2LS:
10695 c2ls_assemble(i,&regs[i]);break;
10696 case C2OP:
10697 c2op_assemble(i,&regs[i]);break;
57871462 10698 case FCONV:
10699 fconv_assemble(i,&regs[i]);break;
10700 case FLOAT:
10701 float_assemble(i,&regs[i]);break;
10702 case FCOMP:
10703 fcomp_assemble(i,&regs[i]);break;
10704 case MULTDIV:
10705 multdiv_assemble(i,&regs[i]);break;
10706 case MOV:
10707 mov_assemble(i,&regs[i]);break;
10708 case SYSCALL:
10709 syscall_assemble(i,&regs[i]);break;
7139f3c8 10710 case HLECALL:
10711 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10712 case INTCALL:
10713 intcall_assemble(i,&regs[i]);break;
57871462 10714 case UJUMP:
10715 ujump_assemble(i,&regs[i]);ds=1;break;
10716 case RJUMP:
10717 rjump_assemble(i,&regs[i]);ds=1;break;
10718 case CJUMP:
10719 cjump_assemble(i,&regs[i]);ds=1;break;
10720 case SJUMP:
10721 sjump_assemble(i,&regs[i]);ds=1;break;
10722 case FJUMP:
10723 fjump_assemble(i,&regs[i]);ds=1;break;
10724 case SPAN:
10725 pagespan_assemble(i,&regs[i]);break;
10726 }
10727 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10728 literal_pool(1024);
10729 else
10730 literal_pool_jumpover(256);
10731 }
10732 }
10733 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10734 // If the block did not end with an unconditional branch,
10735 // add a jump to the next instruction.
10736 if(i>1) {
10737 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10738 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10739 assert(i==slen);
10740 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10741 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10742 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10743 emit_loadreg(CCREG,HOST_CCREG);
10744 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10745 }
10746 else if(!likely[i-2])
10747 {
10748 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10749 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10750 }
10751 else
10752 {
10753 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10754 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10755 }
10756 add_to_linker((int)out,start+i*4,0);
10757 emit_jmp(0);
10758 }
10759 }
10760 else
10761 {
10762 assert(i>0);
10763 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10764 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10765 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10766 emit_loadreg(CCREG,HOST_CCREG);
10767 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10768 add_to_linker((int)out,start+i*4,0);
10769 emit_jmp(0);
10770 }
10771
10772 // TODO: delay slot stubs?
10773 // Stubs
10774 for(i=0;i<stubcount;i++)
10775 {
10776 switch(stubs[i][0])
10777 {
10778 case LOADB_STUB:
10779 case LOADH_STUB:
10780 case LOADW_STUB:
10781 case LOADD_STUB:
10782 case LOADBU_STUB:
10783 case LOADHU_STUB:
10784 do_readstub(i);break;
10785 case STOREB_STUB:
10786 case STOREH_STUB:
10787 case STOREW_STUB:
10788 case STORED_STUB:
10789 do_writestub(i);break;
10790 case CC_STUB:
10791 do_ccstub(i);break;
10792 case INVCODE_STUB:
10793 do_invstub(i);break;
10794 case FP_STUB:
10795 do_cop1stub(i);break;
10796 case STORELR_STUB:
10797 do_unalignedwritestub(i);break;
10798 }
10799 }
10800
9ad4d757 10801 if (instr_addr0_override)
10802 instr_addr[0] = instr_addr0_override;
10803
57871462 10804 /* Pass 9 - Linker */
10805 for(i=0;i<linkcount;i++)
10806 {
10807 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10808 literal_pool(64);
10809 if(!link_addr[i][2])
10810 {
10811 void *stub=out;
10812 void *addr=check_addr(link_addr[i][1]);
10813 emit_extjump(link_addr[i][0],link_addr[i][1]);
10814 if(addr) {
10815 set_jump_target(link_addr[i][0],(int)addr);
10816 add_link(link_addr[i][1],stub);
10817 }
10818 else set_jump_target(link_addr[i][0],(int)stub);
10819 }
10820 else
10821 {
10822 // Internal branch
10823 int target=(link_addr[i][1]-start)>>2;
10824 assert(target>=0&&target<slen);
10825 assert(instr_addr[target]);
10826 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10827 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10828 //#else
10829 set_jump_target(link_addr[i][0],instr_addr[target]);
10830 //#endif
10831 }
10832 }
10833 // External Branch Targets (jump_in)
10834 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10835 for(i=0;i<slen;i++)
10836 {
10837 if(bt[i]||i==0)
10838 {
10839 if(instr_addr[i]) // TODO - delay slots (=null)
10840 {
10841 u_int vaddr=start+i*4;
94d23bb9 10842 u_int page=get_page(vaddr);
10843 u_int vpage=get_vpage(vaddr);
57871462 10844 literal_pool(256);
10845 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10846 if(!requires_32bit[i])
10847 {
10848 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10849 assem_debug("jump_in: %x\n",start+i*4);
10850 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10851 int entry_point=do_dirty_stub(i);
10852 ll_add(jump_in+page,vaddr,(void *)entry_point);
10853 // If there was an existing entry in the hash table,
10854 // replace it with the new address.
10855 // Don't add new entries. We'll insert the
10856 // ones that actually get used in check_addr().
10857 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10858 if(ht_bin[0]==vaddr) {
10859 ht_bin[1]=entry_point;
10860 }
10861 if(ht_bin[2]==vaddr) {
10862 ht_bin[3]=entry_point;
10863 }
10864 }
10865 else
10866 {
10867 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10868 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10869 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10870 //int entry_point=(int)out;
10871 ////assem_debug("entry_point: %x\n",entry_point);
10872 //load_regs_entry(i);
10873 //if(entry_point==(int)out)
10874 // entry_point=instr_addr[i];
10875 //else
10876 // emit_jmp(instr_addr[i]);
10877 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10878 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10879 int entry_point=do_dirty_stub(i);
10880 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10881 }
10882 }
10883 }
10884 }
10885 // Write out the literal pool if necessary
10886 literal_pool(0);
10887 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10888 // Align code
10889 if(((u_int)out)&7) emit_addnop(13);
10890 #endif
10891 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10892 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10893 memcpy(copy,source,slen*4);
10894 copy+=slen*4;
10895
10896 #ifdef __arm__
10897 __clear_cache((void *)beginning,out);
10898 #endif
10899
10900 // If we're within 256K of the end of the buffer,
10901 // start over from the beginning. (Is 256K enough?)
10902 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10903
10904 // Trap writes to any of the pages we compiled
10905 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10906 invalid_code[i]=0;
90ae6d4e 10907#ifndef DISABLE_TLB
57871462 10908 memory_map[i]|=0x40000000;
10909 if((signed int)start>=(signed int)0xC0000000) {
10910 assert(using_tlb);
10911 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10912 invalid_code[j]=0;
10913 memory_map[j]|=0x40000000;
10914 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10915 }
90ae6d4e 10916#endif
57871462 10917 }
10918
10919 /* Pass 10 - Free memory by expiring oldest blocks */
10920
10921 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10922 while(expirep!=end)
10923 {
10924 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10925 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10926 inv_debug("EXP: Phase %d\n",expirep);
10927 switch((expirep>>11)&3)
10928 {
10929 case 0:
10930 // Clear jump_in and jump_dirty
10931 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10932 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10933 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10934 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10935 break;
10936 case 1:
10937 // Clear pointers
10938 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10939 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10940 break;
10941 case 2:
10942 // Clear hash table
10943 for(i=0;i<32;i++) {
10944 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10945 if((ht_bin[3]>>shift)==(base>>shift) ||
10946 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10947 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10948 ht_bin[2]=ht_bin[3]=-1;
10949 }
10950 if((ht_bin[1]>>shift)==(base>>shift) ||
10951 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10952 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10953 ht_bin[0]=ht_bin[2];
10954 ht_bin[1]=ht_bin[3];
10955 ht_bin[2]=ht_bin[3]=-1;
10956 }
10957 }
10958 break;
10959 case 3:
10960 // Clear jump_out
57871462 10961 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10962 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10963 break;
10964 }
10965 expirep=(expirep+1)&65535;
10966 }
10967 return 0;
10968}
b9b61529 10969
10970// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork