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some work on PSP CLUT
[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
16\r
89fa852d 17//\r
18#define USE_POLL_DETECT\r
19\r
eff55556 20#ifndef PICO_INTERNAL\r
21#define PICO_INTERNAL\r
22#endif\r
23#ifndef PICO_INTERNAL_ASM\r
24#define PICO_INTERNAL_ASM\r
25#endif\r
cc68a136 26\r
70357ce5 27// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 28\r
29#ifdef __cplusplus\r
30extern "C" {\r
31#endif\r
32\r
33\r
34// ----------------------- 68000 CPU -----------------------\r
35#ifdef EMU_C68K\r
36#include "../cpu/Cyclone/Cyclone.h"\r
b837b69b 37extern struct Cyclone PicoCpu, PicoCpuS68k;\r
7336a99a 38#define SekCyclesLeftNoMCD PicoCpu.cycles // cycles left for this run\r
39#define SekCyclesLeft \\r
40 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 41#define SekCyclesLeftS68k \\r
42 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuS68k.cycles)\r
7336a99a 43#define SekSetCyclesLeftNoMCD(c) PicoCpu.cycles=c\r
44#define SekSetCyclesLeft(c) { \\r
45 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
46}\r
cc68a136 47#define SekPc (PicoCpu.pc-PicoCpu.membase)\r
b837b69b 48#define SekPcS68k (PicoCpuS68k.pc-PicoCpuS68k.membase)\r
0af33fe0 49#define SekSetStop(x) { PicoCpu.state_flags&=~1; if (x) { PicoCpu.state_flags|=1; PicoCpu.cycles=0; } }\r
50#define SekSetStopS68k(x) { PicoCpuS68k.state_flags&=~1; if (x) { PicoCpuS68k.state_flags|=1; PicoCpuS68k.cycles=0; } }\r
cc68a136 51#endif\r
52\r
70357ce5 53#ifdef EMU_F68K\r
54#include "../cpu/fame/fame.h"\r
55M68K_CONTEXT PicoCpuM68k, PicoCpuS68k;\r
56#define SekCyclesLeftNoMCD PicoCpuM68k.io_cycle_counter\r
57#define SekCyclesLeft \\r
58 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
59#define SekCyclesLeftS68k \\r
60 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuS68k.io_cycle_counter)\r
61#define SekSetCyclesLeftNoMCD(c) PicoCpuM68k.io_cycle_counter=c\r
62#define SekSetCyclesLeft(c) { \\r
63 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
64}\r
65#define SekPc m68k_get_pc(&PicoCpuM68k)\r
66#define SekPcS68k m68k_get_pc(&PicoCpuS68k)\r
67#define SekSetStop(x) { \\r
68 PicoCpuM68k.execinfo &= ~M68K_HALTED; \\r
69 if (x) { PicoCpuM68k.execinfo |= M68K_HALTED; PicoCpuM68k.io_cycle_counter = 0; } \\r
70}\r
71#define SekSetStopS68k(x) { \\r
72 PicoCpuS68k.execinfo &= ~M68K_HALTED; \\r
73 if (x) { PicoCpuS68k.execinfo |= M68K_HALTED; PicoCpuS68k.io_cycle_counter = 0; } \\r
74}\r
cc68a136 75#endif\r
76\r
77#ifdef EMU_M68K\r
78#include "../cpu/musashi/m68kcpu.h"\r
79extern m68ki_cpu_core PicoM68kCPU; // MD's CPU\r
80extern m68ki_cpu_core PicoS68kCPU; // Mega CD's CPU\r
81#ifndef SekCyclesLeft\r
7a1f6e45 82#define SekCyclesLeftNoMCD PicoM68kCPU.cyc_remaining_cycles\r
7336a99a 83#define SekCyclesLeft \\r
84 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 85#define SekCyclesLeftS68k \\r
86 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoS68kCPU.cyc_remaining_cycles)\r
7336a99a 87#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
88#define SekSetCyclesLeft(c) { \\r
89 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
90}\r
cc68a136 91#define SekPc m68k_get_reg(&PicoM68kCPU, M68K_REG_PC)\r
92#define SekPcS68k m68k_get_reg(&PicoS68kCPU, M68K_REG_PC)\r
7a1f6e45 93#define SekSetStop(x) { \\r
94 if(x) { SET_CYCLES(0); PicoM68kCPU.stopped=STOP_LEVEL_STOP; } \\r
95 else PicoM68kCPU.stopped=0; \\r
96}\r
97#define SekSetStopS68k(x) { \\r
98 if(x) { SET_CYCLES(0); PicoS68kCPU.stopped=STOP_LEVEL_STOP; } \\r
99 else PicoS68kCPU.stopped=0; \\r
100}\r
cc68a136 101#endif\r
102#endif\r
103\r
104extern int SekCycleCnt; // cycles done in this frame\r
105extern int SekCycleAim; // cycle aim\r
106extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
107\r
b8cbd802 108#define SekCyclesReset() { \\r
109 SekCycleCntT+=SekCycleAim; \\r
110 SekCycleCnt-=SekCycleAim; \\r
111 SekCycleAim=0; \\r
112}\r
cc68a136 113#define SekCyclesBurn(c) SekCycleCnt+=c\r
114#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
115#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
116\r
117#define SekEndRun(after) { \\r
118 SekCycleCnt -= SekCyclesLeft - after; \\r
119 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
120 SekSetCyclesLeft(after); \\r
121}\r
122\r
123extern int SekCycleCntS68k;\r
124extern int SekCycleAimS68k;\r
125\r
bf5fbbb4 126#define SekCyclesResetS68k() { \\r
127 SekCycleCntS68k-=SekCycleAimS68k; \\r
128 SekCycleAimS68k=0; \\r
129}\r
7a1f6e45 130#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 131\r
2d0b15bb 132// debug cyclone\r
133#if defined(EMU_C68K) && defined(EMU_M68K)\r
134#undef SekSetCyclesLeftNoMCD\r
135#undef SekSetCyclesLeft\r
136#undef SekCyclesBurn\r
137#undef SekEndRun\r
138#define SekSetCyclesLeftNoMCD(c)\r
139#define SekSetCyclesLeft(c)\r
2270612a 140#define SekCyclesBurn(c) c\r
2d0b15bb 141#define SekEndRun(c)\r
142#endif\r
cc68a136 143\r
cc68a136 144// ---------------------------------------------------------\r
145\r
70357ce5 146extern int PicoMCD;\r
147\r
cc68a136 148// main oscillator clock which controls timing\r
149#define OSC_NTSC 53693100\r
b8cbd802 150// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
151#define OSC_PAL 53203424\r
cc68a136 152\r
153struct PicoVideo\r
154{\r
155 unsigned char reg[0x20];\r
b8cbd802 156 unsigned int command; // 32-bit Command\r
157 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
158 unsigned char type; // Command type (v/c/vsram read/write)\r
159 unsigned short addr; // Read/Write address\r
160 int status; // Status bits\r
cc68a136 161 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 162 signed char lwrite_cnt; // VDP write count during active display line\r
163 unsigned char pad[0x12];\r
cc68a136 164};\r
165\r
166struct PicoMisc\r
167{\r
168 unsigned char rotate;\r
169 unsigned char z80Run;\r
e5503e2f 170 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
171 short scanline; // 04 0 to 261||311; -1 in fast mode\r
172 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
173 unsigned char hardware; // 07 Hardware value for country\r
174 unsigned char pal; // 08 1=PAL 0=NTSC\r
175 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
176 unsigned short z80_bank68k; // 0a\r
cc68a136 177 unsigned short z80_lastaddr; // this is for Z80 faking\r
178 unsigned char z80_fakeval;\r
179 unsigned char pad0;\r
e5503e2f 180 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 181 unsigned short eeprom_addr; // EEPROM address register\r
182 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
183 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 184 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 185 unsigned short dma_xfers;\r
312e9ce1 186 unsigned char pad[2];\r
187 unsigned int frame_count; // mainly for movies\r
cc68a136 188};\r
189\r
190// some assembly stuff depend on these, do not touch!\r
191struct Pico\r
192{\r
193 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
194 unsigned short vram[0x8000]; // 0x10000\r
195 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
196 unsigned char ioports[0x10];\r
197 unsigned int pad[0x3c]; // unused\r
198 unsigned short cram[0x40]; // 0x22100\r
199 unsigned short vsram[0x40]; // 0x22180\r
200\r
201 unsigned char *rom; // 0x22200\r
202 unsigned int romsize; // 0x22204\r
203\r
204 struct PicoMisc m;\r
205 struct PicoVideo video;\r
206};\r
207\r
208// sram\r
209struct PicoSRAM\r
210{\r
4ff2d527 211 unsigned char *data; // actual data\r
212 unsigned int start; // start address in 68k address space\r
cc68a136 213 unsigned int end;\r
1dceadae 214 unsigned char unused1; // 0c: unused\r
215 unsigned char unused2;\r
cc68a136 216 unsigned char changed;\r
1dceadae 217 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
218 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
219 unsigned char eeprom_bit_cl; // bit number for cl\r
220 unsigned char eeprom_bit_in; // bit number for in\r
221 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 222};\r
223\r
224// MCD\r
225#include "cd/cd_sys.h"\r
226#include "cd/LC89510.h"\r
d1df8786 227#include "cd/gfx_cd.h"\r
cc68a136 228\r
4f265db7 229struct mcd_pcm\r
230{\r
231 unsigned char control; // reg7\r
232 unsigned char enabled; // reg8\r
233 unsigned char cur_ch;\r
234 unsigned char bank;\r
235 int pad1;\r
236\r
4ff2d527 237 struct pcm_chan // 08, size 0x10\r
4f265db7 238 {\r
239 unsigned char regs[8];\r
4ff2d527 240 unsigned int addr; // .08: played sample address\r
4f265db7 241 int pad;\r
242 } ch[8];\r
243};\r
244\r
c459aefd 245struct mcd_misc\r
246{\r
247 unsigned short hint_vector;\r
248 unsigned char busreq;\r
51a902ae 249 unsigned char s68k_pend_ints;\r
89fa852d 250 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 251 unsigned int counter75hz;\r
4ff2d527 252 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 253 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 254 char pad1;\r
4ff2d527 255 int timer_int3; // 10\r
4f265db7 256 unsigned int timer_stopwatch;\r
6cadc2da 257 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
258 unsigned char pad2;\r
259 unsigned short pad3;\r
260 int pad[9];\r
c459aefd 261};\r
262\r
cc68a136 263typedef struct\r
264{\r
4ff2d527 265 unsigned char bios[0x20000]; // 000000: 128K\r
266 union { // 020000: 512K\r
fa1e5e29 267 unsigned char prg_ram[0x80000];\r
cc68a136 268 unsigned char prg_ram_b[4][0x20000];\r
269 };\r
4ff2d527 270 union { // 0a0000: 256K\r
fa1e5e29 271 struct {\r
272 unsigned char word_ram2M[0x40000];\r
273 unsigned char unused[0x20000];\r
274 };\r
275 struct {\r
276 unsigned char unused[0x20000];\r
277 unsigned char word_ram1M[2][0x20000];\r
278 };\r
279 };\r
4ff2d527 280 union { // 100000: 64K\r
fa1e5e29 281 unsigned char pcm_ram[0x10000];\r
4f265db7 282 unsigned char pcm_ram_b[0x10][0x1000];\r
283 };\r
4ff2d527 284 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
285 unsigned char bram[0x2000]; // 110200: 8K\r
286 struct mcd_misc m; // 112200: misc\r
287 struct mcd_pcm pcm; // 112240:\r
75736070 288 _scd_toc TOC; // not to be saved\r
cc68a136 289 CDD cdd;\r
290 CDC cdc;\r
291 _scd scd;\r
d1df8786 292 Rot_Comp rot_comp;\r
cc68a136 293} mcd_state;\r
294\r
295#define Pico_mcd ((mcd_state *)Pico.rom)\r
296\r
51a902ae 297// Area.c\r
eff55556 298PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
299PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae 300\r
301// cd/Area.c\r
eff55556 302PICO_INTERNAL int PicoCdSaveState(void *file);\r
303PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 304\r
1dceadae 305// Cart.c\r
306PICO_INTERNAL void PicoCartDetect(void);\r
307\r
cc68a136 308// Draw.c\r
eff55556 309PICO_INTERNAL int PicoLine(int scan);\r
310PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 311\r
312// Draw2.c\r
eff55556 313PICO_INTERNAL void PicoFrameFull();\r
cc68a136 314\r
315// Memory.c\r
eff55556 316PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
317PICO_INTERNAL_ASM unsigned int CPU_CALL PicoRead32(unsigned int a);\r
318PICO_INTERNAL void PicoMemSetup(void);\r
319PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f 320PICO_INTERNAL int PadRead(int i);\r
eff55556 321PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
322PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
323PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
324PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
cc68a136 325\r
326// cd/Memory.c\r
eff55556 327PICO_INTERNAL void PicoMemSetupCD(void);\r
328PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
329PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 330\r
331// Pico.c\r
332extern struct Pico Pico;\r
333extern struct PicoSRAM SRam;\r
334extern int emustatus;\r
d9153729 335extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556 336PICO_INTERNAL int CheckDMA(void);\r
cc68a136 337\r
338// cd/Pico.c\r
e5f426aa 339PICO_INTERNAL int PicoInitMCD(void);\r
340PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 341PICO_INTERNAL int PicoResetMCD(int hard);\r
342PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 343\r
344// Sek.c\r
eff55556 345PICO_INTERNAL int SekInit(void);\r
346PICO_INTERNAL int SekReset(void);\r
347PICO_INTERNAL int SekInterrupt(int irq);\r
348PICO_INTERNAL void SekState(unsigned char *data);\r
349PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 350\r
351// cd/Sek.c\r
eff55556 352PICO_INTERNAL int SekInitS68k(void);\r
353PICO_INTERNAL int SekResetS68k(void);\r
354PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 355\r
7a93adeb 356// sound/sound.c\r
357extern int PsndLen_exc_cnt;\r
358extern int PsndLen_exc_add;\r
359\r
cc68a136 360// VideoPort.c\r
eff55556 361PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
362PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136 363\r
364// Misc.c\r
eff55556 365PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
366PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
367PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
368PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
369PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
370PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
371PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 372\r
fa1e5e29 373// cd/Misc.c\r
eff55556 374PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
375PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
376\r
377// cd/buffering.c\r
378PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
379\r
380// sound/sound.c\r
381PICO_INTERNAL void sound_reset(void);\r
382PICO_INTERNAL void sound_timers_and_dac(int raster);\r
383PICO_INTERNAL int sound_render(int offset, int length);\r
384PICO_INTERNAL void sound_clear(void);\r
385// z80 functionality wrappers\r
386PICO_INTERNAL void z80_init(void);\r
387PICO_INTERNAL void z80_resetCycles(void);\r
388PICO_INTERNAL void z80_int(void);\r
389PICO_INTERNAL int z80_run(int cycles);\r
390PICO_INTERNAL void z80_pack(unsigned char *data);\r
391PICO_INTERNAL void z80_unpack(unsigned char *data);\r
392PICO_INTERNAL void z80_reset(void);\r
393PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 394\r
cc68a136 395\r
396#ifdef __cplusplus\r
397} // End of extern "C"\r
398#endif\r
eff55556 399\r
b8cbd802 400// emulation event logging\r
401#ifndef EL_LOGMASK\r
402#define EL_LOGMASK 0\r
403#endif\r
404\r
405#define EL_HVCNT 0x0001 /* hv counter reads */\r
406#define EL_SR 0x0002 /* SR reads */\r
407#define EL_INTS 0x0004 /* ints and acks */\r
408#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
409#define EL_INTSW 0x0010 /* log irq switching on/off */\r
410#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
411#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
5f20bb80 412#define EL_BUSREQ 0x0080 /* z80 busreq r/w or reset w */\r
b8cbd802 413#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae 414#define EL_SRAMIO 0x0200 /* sram i/o */\r
415#define EL_EEPROM 0x0400 /* eeprom debug */\r
416#define EL_UIO 0x0800 /* unmapped i/o */\r
5f20bb80 417#define EL_IO 0x1000 /* all i/o (TODO) */\r
b8cbd802 418\r
419#define EL_STATUS 0x4000 /* status messages */\r
420#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
421\r
422#if EL_LOGMASK\r
423#define elprintf(w,f,...) \\r
424{ \\r
425 if ((w) & EL_LOGMASK) \\r
426 printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
427}\r
428#else\r
429#define elprintf(w,f,...)\r
430#endif\r
431\r
eff55556 432#endif // PICO_INTERNAL_INCLUDED\r
433\r
fast MegaDrive/MegaCD/32X emulator