83ff19ec |
1 | /* |
cff531af |
2 | * PicoDrive |
65514d85 |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | * |
83ff19ec |
8 | * Register map: |
9 | * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm |
10 | * a15102 ........ ......SM ? 4002 // intS intM |
11 | * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint |
7eaa3812 |
12 | * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb] |
83ff19ec |
13 | * a15108 (32bit DREQ src) 4008 |
14 | * a1510c (32bit DREQ dst) 400c |
15 | * a15110 llllllll llllll00 4010 // DREQ Len |
16 | * a15112 (16bit FIFO reg) 4012 |
7eaa3812 |
17 | * a15114 0 (16bit VRES clr) 4014 |
18 | * a15116 0 (16bit Vint clr) 4016 |
19 | * a15118 0 (16bit Hint clr) 4018 |
20 | * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm |
21 | * a1511c 0 (16bit PWM clr) 401c |
22 | * a1511e 0 ? 401e |
83ff19ec |
23 | * a15120 (16 bytes comm) 2020 |
24 | * a15130 (PWM) 2030 |
65514d85 |
25 | * |
26 | * SH2 addr lines: |
27 | * iii. .cc. ..xx * // Internal, Cs, x |
28 | * |
29 | * sh2 map, wait/bus cycles (from docs): |
30 | * r w |
31 | * rom 0000000-0003fff 1 - |
32 | * sys reg 0004000-00040ff 1 1 |
33 | * vdp reg 0004100-00041ff 5 5 |
34 | * vdp pal 0004200-00043ff 5 5 |
8a847c12 |
35 | * cart 2000000-23fffff 6-15 |
65514d85 |
36 | * dram/fb 4000000-401ffff 5-12 1-3 |
37 | * fb ovr 4020000-403ffff |
38 | * sdram 6000000-603ffff 12 2 (cycles) |
39 | * d.a. c0000000-? |
83ff19ec |
40 | */ |
be2c4208 |
41 | #include "../pico_int.h" |
42 | #include "../memory.h" |
f4bb5d6b |
43 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
44 | |
45 | static const char str_mars[] = "MARS"; |
46 | |
83ff19ec |
47 | void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s; |
974fdb5b |
48 | struct Pico32xMem *Pico32xMem; |
49 | |
5e49c3a8 |
50 | static void bank_switch(int b); |
51 | |
7eaa3812 |
52 | // addressing byte in 16bit reg |
53 | #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1] |
54 | |
266c6afa |
55 | // poll detection |
19886062 |
56 | #define POLL_THRESHOLD 3 |
4ea707e1 |
57 | |
19886062 |
58 | static struct { |
59 | u32 addr, cycles; |
60 | int cnt; |
61 | } m68k_poll; |
266c6afa |
62 | |
19886062 |
63 | static int m68k_poll_detect(u32 a, u32 cycles, u32 flags) |
266c6afa |
64 | { |
19886062 |
65 | int ret = 0; |
66 | |
67 | if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2 |
68 | && cycles - m68k_poll.cycles <= 64) |
69 | { |
70 | if (m68k_poll.cnt++ > POLL_THRESHOLD) { |
71 | if (!(Pico32x.emu_flags & flags)) { |
72 | elprintf(EL_32X, "m68k poll addr %08x, cyc %u", |
73 | a, cycles - m68k_poll.cycles); |
266c6afa |
74 | ret = 1; |
75 | } |
19886062 |
76 | Pico32x.emu_flags |= flags; |
266c6afa |
77 | } |
78 | } |
c987bb5c |
79 | else { |
19886062 |
80 | m68k_poll.cnt = 0; |
81 | m68k_poll.addr = a; |
c987bb5c |
82 | } |
19886062 |
83 | m68k_poll.cycles = cycles; |
266c6afa |
84 | |
85 | return ret; |
86 | } |
87 | |
19886062 |
88 | void p32x_m68k_poll_event(u32 flags) |
89 | { |
90 | if (Pico32x.emu_flags & flags) { |
91 | elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags, |
92 | Pico32x.emu_flags & ~flags); |
93 | Pico32x.emu_flags &= ~flags; |
94 | SekSetStop(0); |
95 | } |
96 | m68k_poll.addr = m68k_poll.cnt = 0; |
97 | } |
98 | |
4a1fb183 |
99 | static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt) |
266c6afa |
100 | { |
19886062 |
101 | int cycles_left = sh2_cycles_left(sh2); |
102 | |
103 | if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) { |
4a1fb183 |
104 | if (sh2->poll_cnt++ > maxcnt) { |
19886062 |
105 | if (!(sh2->state & flags)) |
f8675e28 |
106 | elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", |
19886062 |
107 | sh2->state, sh2->state | flags); |
108 | |
109 | sh2->state |= flags; |
110 | sh2_end_run(sh2, 1); |
111 | pevt_log_sh2(sh2, EVT_POLL_START); |
112 | return; |
113 | } |
114 | } |
be20816c |
115 | else |
19886062 |
116 | sh2->poll_cnt = 0; |
117 | sh2->poll_addr = a; |
118 | sh2->poll_cycles = cycles_left; |
119 | } |
120 | |
121 | void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles) |
122 | { |
123 | if (sh2->state & flags) { |
f8675e28 |
124 | elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state, |
125 | sh2->state & ~flags); |
19886062 |
126 | |
127 | if (sh2->m68krcycles_done < m68k_cycles) |
128 | sh2->m68krcycles_done = m68k_cycles; |
129 | |
130 | pevt_log_sh2_o(sh2, EVT_POLL_END); |
be20816c |
131 | } |
19886062 |
132 | |
133 | sh2->state &= ~flags; |
134 | sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0; |
266c6afa |
135 | } |
136 | |
19886062 |
137 | static void sh2s_sync_on_read(SH2 *sh2) |
4ea707e1 |
138 | { |
19886062 |
139 | int cycles; |
140 | if (sh2->poll_cnt != 0) |
141 | return; |
142 | |
143 | cycles = sh2_cycles_done(sh2); |
144 | if (cycles > 600) |
145 | p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3); |
4ea707e1 |
146 | } |
147 | |
974fdb5b |
148 | // SH2 faking |
b78efee2 |
149 | //#define FAKE_SH2 |
acd35d4c |
150 | #ifdef FAKE_SH2 |
27e26273 |
151 | static int p32x_csum_faked; |
974fdb5b |
152 | static const u16 comm_fakevals[] = { |
153 | 0x4d5f, 0x4f4b, // M_OK |
154 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
155 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
156 | 0x5331, 0x4d31, // Darxide |
157 | 0x5332, 0x4d32, |
158 | 0x5333, 0x4d33, |
159 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
160 | 0x0002, // Mortal Kombat |
acd35d4c |
161 | // 0, // pad |
be2c4208 |
162 | }; |
acd35d4c |
163 | |
164 | static u32 sh2_comm_faker(u32 a) |
165 | { |
166 | static int f = 0; |
167 | if (a == 0x28 && !p32x_csum_faked) { |
168 | p32x_csum_faked = 1; |
169 | return *(unsigned short *)(Pico.rom + 0x18e); |
170 | } |
171 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
172 | f = 0; |
173 | return comm_fakevals[f++]; |
174 | } |
175 | #endif |
be2c4208 |
176 | |
4ea707e1 |
177 | // ------------------------------------------------------------------ |
b78efee2 |
178 | // 68k regs |
4ea707e1 |
179 | |
be2c4208 |
180 | static u32 p32x_reg_read16(u32 a) |
181 | { |
182 | a &= 0x3e; |
183 | |
3cf9570b |
184 | #if 0 |
974fdb5b |
185 | if ((a & 0x30) == 0x20) |
acd35d4c |
186 | return sh2_comm_faker(a); |
266c6afa |
187 | #else |
5fadfb1c |
188 | if ((a & 0x30) == 0x20) { |
5fadfb1c |
189 | static u32 dr2 = 0; |
a8fd6e37 |
190 | unsigned int cycles = SekCyclesDoneT(); |
191 | int comreg = 1 << (a & 0x0f) / 2; |
192 | |
193 | // evil X-Men proto polls in a dbra loop and expects it to expire.. |
5fadfb1c |
194 | if (SekDar(2) != dr2) |
195 | m68k_poll.cnt = 0; |
196 | dr2 = SekDar(2); |
197 | |
a8fd6e37 |
198 | if (cycles - msh2.m68krcycles_done > 500) |
199 | p32x_sync_sh2s(cycles); |
200 | if (Pico32x.comm_dirty_sh2 & comreg) |
201 | Pico32x.comm_dirty_sh2 &= ~comreg; |
19886062 |
202 | else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) { |
5fadfb1c |
203 | SekSetStop(1); |
3e5b912c |
204 | SekEndRun(16); |
5fadfb1c |
205 | } |
206 | dr2 = SekDar(2); |
a8fd6e37 |
207 | goto out; |
266c6afa |
208 | } |
acd35d4c |
209 | #endif |
87accdf7 |
210 | |
a8fd6e37 |
211 | if (a == 2) { // INTM, INTS |
212 | unsigned int cycles = SekCyclesDoneT(); |
213 | if (cycles - msh2.m68krcycles_done > 64) |
214 | p32x_sync_sh2s(cycles); |
215 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
216 | } |
217 | |
db1d3564 |
218 | if ((a & 0x30) == 0x30) |
c1931173 |
219 | return p32x_pwm_read16(a, NULL, SekCyclesDoneT()); |
974fdb5b |
220 | |
a8fd6e37 |
221 | out: |
be2c4208 |
222 | return Pico32x.regs[a / 2]; |
223 | } |
224 | |
7eaa3812 |
225 | static void dreq0_write(u16 *r, u32 d) |
226 | { |
227 | if (!(r[6 / 2] & P32XS_68S)) { |
228 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
229 | return; // ignored - tested |
230 | } |
231 | if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) { |
232 | Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d; |
233 | if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN) |
234 | r[6 / 2] |= P32XS_FULL; |
235 | // tested: len register decrements and 68S clears |
236 | // even if SH2s/DMAC aren't active.. |
237 | r[0x10 / 2]--; |
238 | if (r[0x10 / 2] == 0) |
239 | r[6 / 2] &= ~P32XS_68S; |
240 | |
241 | if ((Pico32x.dmac0_fifo_ptr & 3) == 0) { |
242 | p32x_sync_sh2s(SekCyclesDoneT()); |
243 | p32x_dreq0_trigger(); |
244 | } |
245 | } |
246 | else |
247 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!"); |
248 | } |
249 | |
250 | // writable bits tested |
be2c4208 |
251 | static void p32x_reg_write8(u32 a, u32 d) |
252 | { |
acd35d4c |
253 | u16 *r = Pico32x.regs; |
be2c4208 |
254 | a &= 0x3f; |
255 | |
97d3f47f |
256 | // for things like bset on comm port |
257 | m68k_poll.cnt = 0; |
258 | |
acd35d4c |
259 | switch (a) { |
7eaa3812 |
260 | case 0x00: // adapter ctl: FM writable |
261 | REG8IN16(r, 0x00) = d & 0x80; |
83ff19ec |
262 | return; |
7eaa3812 |
263 | case 0x01: // adapter ctl: RES and ADEN writable |
83ff19ec |
264 | if ((d ^ r[0]) & d & P32XS_nRES) |
265 | p32x_reset_sh2s(); |
7eaa3812 |
266 | REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN); |
267 | REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN); |
268 | return; |
269 | case 0x02: // ignored, always 0 |
1b3f5844 |
270 | return; |
7eaa3812 |
271 | case 0x03: // irq ctl |
4d5dfee8 |
272 | if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
a8fd6e37 |
273 | p32x_sync_sh2s(SekCyclesDoneT()); |
4d5dfee8 |
274 | if (d & 1) |
275 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
276 | else |
277 | Pico32x.sh2irqi[0] &= ~P32XI_CMD; |
278 | p32x_update_irls(NULL, SekCyclesDoneT2()); |
4ea707e1 |
279 | } |
4d5dfee8 |
280 | if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
a8fd6e37 |
281 | p32x_sync_sh2s(SekCyclesDoneT()); |
4d5dfee8 |
282 | if (d & 2) |
283 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
284 | else |
285 | Pico32x.sh2irqi[1] &= ~P32XI_CMD; |
286 | p32x_update_irls(NULL, SekCyclesDoneT2()); |
b78efee2 |
287 | } |
1b3f5844 |
288 | return; |
7eaa3812 |
289 | case 0x04: // ignored, always 0 |
290 | return; |
291 | case 0x05: // bank |
292 | d &= 3; |
293 | if (r[0x04 / 2] != d) { |
294 | r[0x04 / 2] = d; |
acd35d4c |
295 | bank_switch(d); |
296 | } |
1b3f5844 |
297 | return; |
7eaa3812 |
298 | case 0x06: // ignored, always 0 |
299 | return; |
300 | case 0x07: // DREQ ctl |
301 | REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV); |
302 | if (!(d & P32XS_68S)) { |
303 | Pico32x.dmac0_fifo_ptr = 0; |
304 | REG8IN16(r, 0x07) &= ~P32XS_FULL; |
305 | } |
306 | REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV); |
307 | return; |
308 | case 0x08: // ignored, always 0 |
309 | return; |
310 | case 0x09: // DREQ src |
311 | REG8IN16(r, 0x09) = d; |
312 | return; |
313 | case 0x0a: |
314 | REG8IN16(r, 0x0a) = d; |
315 | return; |
316 | case 0x0b: |
317 | REG8IN16(r, 0x0b) = d & 0xfe; |
318 | return; |
319 | case 0x0c: // ignored, always 0 |
320 | return; |
321 | case 0x0d: // DREQ dest |
322 | case 0x0e: |
323 | case 0x0f: |
324 | case 0x10: // DREQ len |
325 | REG8IN16(r, a) = d; |
326 | return; |
327 | case 0x11: |
328 | REG8IN16(r, a) = d & 0xfc; |
329 | return; |
330 | // DREQ FIFO - writes to odd addr go to fifo |
331 | // do writes to even work? Reads return 0 |
332 | case 0x12: |
333 | REG8IN16(r, a) = d; |
334 | return; |
335 | case 0x13: |
336 | d = (REG8IN16(r, 0x12) << 8) | (d & 0xff); |
337 | REG8IN16(r, 0x12) = 0; |
338 | dreq0_write(r, d); |
339 | return; |
340 | case 0x14: // ignored, always 0 |
341 | case 0x15: |
342 | case 0x16: |
343 | case 0x17: |
344 | case 0x18: |
345 | case 0x19: |
346 | return; |
347 | case 0x1a: // what's this? |
348 | elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d); |
349 | REG8IN16(r, a) = d & 0x01; |
1b3f5844 |
350 | return; |
87accdf7 |
351 | case 0x1b: // TV |
7eaa3812 |
352 | REG8IN16(r, a) = d & 0x01; |
353 | return; |
354 | case 0x1c: // ignored, always 0 |
355 | case 0x1d: |
356 | case 0x1e: |
357 | case 0x1f: |
358 | case 0x30: |
359 | return; |
360 | case 0x31: // PWM control |
361 | REG8IN16(r, a) &= ~0x0f; |
362 | REG8IN16(r, a) |= d & 0x0f; |
363 | goto pwm_write; |
364 | case 0x32: // PWM cycle |
365 | REG8IN16(r, a) = d & 0x0f; |
366 | goto pwm_write; |
367 | case 0x33: |
368 | REG8IN16(r, a) = d; |
369 | goto pwm_write; |
370 | // PWM pulse regs.. Only writes to odd address send a value |
371 | // to FIFO; reads are 0 (except status bits) |
372 | case 0x34: |
373 | case 0x36: |
374 | case 0x38: |
375 | REG8IN16(r, a) = d; |
376 | return; |
377 | case 0x35: |
378 | case 0x37: |
379 | case 0x39: |
380 | d = (REG8IN16(r, a) << 8) | (d & 0xff); |
381 | REG8IN16(r, a) = 0; |
382 | goto pwm_write; |
383 | case 0x3a: // ignored, always 0 |
384 | case 0x3b: |
385 | case 0x3c: |
386 | case 0x3d: |
387 | case 0x3e: |
388 | case 0x3f: |
389 | return; |
390 | pwm_write: |
391 | p32x_pwm_write16(a & ~1, r[a / 2], NULL, SekCyclesDoneT()); |
1b3f5844 |
392 | return; |
393 | } |
394 | |
395 | if ((a & 0x30) == 0x20) { |
a8fd6e37 |
396 | int cycles = SekCyclesDoneT(); |
397 | int comreg; |
398 | |
7eaa3812 |
399 | if (REG8IN16(r, a) == d) |
a8fd6e37 |
400 | return; |
19886062 |
401 | |
a8fd6e37 |
402 | comreg = 1 << (a & 0x0f) / 2; |
403 | if (Pico32x.comm_dirty_68k & comreg) |
404 | p32x_sync_sh2s(cycles); |
405 | |
7eaa3812 |
406 | REG8IN16(r, a) = d; |
19886062 |
407 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
408 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
a8fd6e37 |
409 | Pico32x.comm_dirty_68k |= comreg; |
410 | |
411 | if (cycles - (int)msh2.m68krcycles_done > 120) |
412 | p32x_sync_sh2s(cycles); |
1b3f5844 |
413 | return; |
5e49c3a8 |
414 | } |
415 | } |
416 | |
417 | static void p32x_reg_write16(u32 a, u32 d) |
418 | { |
acd35d4c |
419 | u16 *r = Pico32x.regs; |
420 | a &= 0x3e; |
421 | |
97d3f47f |
422 | // for things like bset on comm port |
423 | m68k_poll.cnt = 0; |
424 | |
acd35d4c |
425 | switch (a) { |
4ea707e1 |
426 | case 0x00: // adapter ctl |
83ff19ec |
427 | if ((d ^ r[0]) & d & P32XS_nRES) |
428 | p32x_reset_sh2s(); |
7eaa3812 |
429 | r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN); |
430 | r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN); |
431 | return; |
432 | case 0x08: // DREQ src |
433 | r[a / 2] = d & 0xff; |
434 | return; |
435 | case 0x0a: |
436 | r[a / 2] = d & ~1; |
437 | return; |
438 | case 0x0c: // DREQ dest |
439 | r[a / 2] = d & 0xff; |
440 | return; |
441 | case 0x0e: |
442 | r[a / 2] = d; |
acd35d4c |
443 | return; |
4ea707e1 |
444 | case 0x10: // DREQ len |
445 | r[a / 2] = d & ~3; |
446 | return; |
447 | case 0x12: // FIFO reg |
7eaa3812 |
448 | dreq0_write(r, d); |
449 | return; |
450 | case 0x1a: // TV + mystery bit |
451 | r[a / 2] = d & 0x0101; |
452 | return; |
acd35d4c |
453 | } |
454 | |
4ea707e1 |
455 | // comm port |
7eaa3812 |
456 | if ((a & 0x30) == 0x20) { |
a8fd6e37 |
457 | int cycles = SekCyclesDoneT(); |
458 | int comreg; |
459 | |
460 | if (r[a / 2] == d) |
461 | return; |
462 | |
463 | comreg = 1 << (a & 0x0f) / 2; |
464 | if (Pico32x.comm_dirty_68k & comreg) |
465 | p32x_sync_sh2s(cycles); |
466 | |
acd35d4c |
467 | r[a / 2] = d; |
19886062 |
468 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
469 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
a8fd6e37 |
470 | Pico32x.comm_dirty_68k |= comreg; |
471 | |
472 | if (cycles - (int)msh2.m68krcycles_done > 120) |
473 | p32x_sync_sh2s(cycles); |
acd35d4c |
474 | return; |
475 | } |
db1d3564 |
476 | // PWM |
477 | else if ((a & 0x30) == 0x30) { |
c1931173 |
478 | p32x_pwm_write16(a, d, NULL, SekCyclesDoneT()); |
db1d3564 |
479 | return; |
480 | } |
acd35d4c |
481 | |
5e49c3a8 |
482 | p32x_reg_write8(a + 1, d); |
be2c4208 |
483 | } |
484 | |
4ea707e1 |
485 | // ------------------------------------------------------------------ |
be2c4208 |
486 | // VDP regs |
487 | static u32 p32x_vdp_read16(u32 a) |
488 | { |
4a1fb183 |
489 | u32 d; |
be2c4208 |
490 | a &= 0x0e; |
491 | |
4a1fb183 |
492 | d = Pico32x.vdp_regs[a / 2]; |
493 | if (a == 0x0a) { |
494 | // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0, |
495 | // most often at 0xb1-0xb5, even during vblank, |
496 | // what's the deal with that? |
497 | // we'll just fake it along with hblank for now |
498 | Pico32x.vdp_fbcr_fake++; |
499 | if (Pico32x.vdp_fbcr_fake & 4) |
500 | d |= P32XV_HBLK; |
501 | if ((Pico32x.vdp_fbcr_fake & 7) == 0) |
502 | d |= P32XV_nFEN; |
503 | } |
504 | return d; |
be2c4208 |
505 | } |
506 | |
be2c4208 |
507 | static void p32x_vdp_write8(u32 a, u32 d) |
508 | { |
974fdb5b |
509 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
510 | a &= 0x0f; |
511 | |
974fdb5b |
512 | // TODO: verify what's writeable |
be2c4208 |
513 | switch (a) { |
974fdb5b |
514 | case 0x01: |
5e49c3a8 |
515 | // priority inversion is handled in palette |
516 | if ((r[0] ^ d) & P32XV_PRI) |
517 | Pico32x.dirty_pal = 1; |
974fdb5b |
518 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
519 | break; |
e51e5983 |
520 | case 0x03: // shift (for pp mode) |
521 | r[2 / 2] = d & 1; |
522 | break; |
be20816c |
523 | case 0x05: // fill len |
524 | r[4 / 2] = d & 0xff; |
974fdb5b |
525 | break; |
be2c4208 |
526 | case 0x0b: |
974fdb5b |
527 | d &= 1; |
528 | Pico32x.pending_fb = d; |
529 | // if we are blanking and FS bit is changing |
4ea707e1 |
530 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
b4db550e |
531 | r[0x0a/2] ^= P32XV_FS; |
5609d343 |
532 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
533 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
534 | } |
535 | break; |
536 | } |
537 | } |
538 | |
19886062 |
539 | static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2) |
974fdb5b |
540 | { |
be20816c |
541 | a &= 0x0e; |
542 | if (a == 6) { // fill start |
543 | Pico32x.vdp_regs[6 / 2] = d; |
544 | return; |
545 | } |
546 | if (a == 8) { // fill data |
547 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
548 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
a8fd6e37 |
549 | int len1 = len; |
be20816c |
550 | a = Pico32x.vdp_regs[6 / 2]; |
a8fd6e37 |
551 | while (len1--) { |
be20816c |
552 | dram[a] = d; |
553 | a = (a & 0xff00) | ((a + 1) & 0xff); |
554 | } |
a8fd6e37 |
555 | Pico32x.vdp_regs[0x06 / 2] = a; |
556 | Pico32x.vdp_regs[0x08 / 2] = d; |
19886062 |
557 | if (sh2 != NULL && len > 4) { |
a8fd6e37 |
558 | Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN; |
19886062 |
559 | // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles? |
560 | p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len); |
a8fd6e37 |
561 | } |
be20816c |
562 | return; |
563 | } |
564 | |
974fdb5b |
565 | p32x_vdp_write8(a | 1, d); |
566 | } |
567 | |
4ea707e1 |
568 | // ------------------------------------------------------------------ |
acd35d4c |
569 | // SH2 regs |
b78efee2 |
570 | |
f81107f5 |
571 | static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2) |
acd35d4c |
572 | { |
4ea707e1 |
573 | u16 *r = Pico32x.regs; |
574 | a &= 0xfe; // ? |
266c6afa |
575 | |
4ea707e1 |
576 | switch (a) { |
577 | case 0x00: // adapter/irq ctl |
f81107f5 |
578 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] |
579 | | Pico32x.sh2irq_mask[sh2->is_slave]; |
c987bb5c |
580 | case 0x04: // H count (often as comm too) |
4a1fb183 |
581 | sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3); |
f81107f5 |
582 | sh2s_sync_on_read(sh2); |
87accdf7 |
583 | return Pico32x.sh2_regs[4 / 2]; |
7eaa3812 |
584 | case 0x06: |
585 | return (r[a / 2] & ~P32XS_FULL) | 0x4000; |
586 | case 0x08: // DREQ src |
587 | case 0x0a: |
588 | case 0x0c: // DREQ dst |
589 | case 0x0e: |
4ea707e1 |
590 | case 0x10: // DREQ len |
591 | return r[a / 2]; |
7eaa3812 |
592 | case 0x12: // DREQ FIFO - does this work on hw? |
593 | if (Pico32x.dmac0_fifo_ptr > 0) { |
594 | Pico32x.dmac0_fifo_ptr--; |
595 | r[a / 2] = Pico32x.dmac_fifo[0]; |
596 | memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1], |
597 | Pico32x.dmac0_fifo_ptr * 2); |
598 | } |
599 | return r[a / 2]; |
600 | case 0x14: |
601 | case 0x16: |
602 | case 0x18: |
603 | case 0x1a: |
604 | case 0x1c: |
605 | return 0; // ? |
acd35d4c |
606 | } |
4ea707e1 |
607 | |
db1d3564 |
608 | // comm port |
609 | if ((a & 0x30) == 0x20) { |
a8fd6e37 |
610 | int comreg = 1 << (a & 0x0f) / 2; |
611 | if (Pico32x.comm_dirty_68k & comreg) |
612 | Pico32x.comm_dirty_68k &= ~comreg; |
19886062 |
613 | else |
4a1fb183 |
614 | sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3); |
f81107f5 |
615 | sh2s_sync_on_read(sh2); |
db1d3564 |
616 | return r[a / 2]; |
617 | } |
7eaa3812 |
618 | if ((a & 0x30) == 0x30) |
f81107f5 |
619 | return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2)); |
acd35d4c |
620 | |
7eaa3812 |
621 | elprintf_sh2(sh2, EL_32X|EL_ANOMALY, |
622 | "unhandled sysreg r16 [%06x] @%06x", a, SekPc); |
acd35d4c |
623 | return 0; |
624 | } |
625 | |
f81107f5 |
626 | static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
627 | { |
4ea707e1 |
628 | a &= 0xff; |
19886062 |
629 | |
f81107f5 |
630 | sh2->poll_addr = 0; |
19886062 |
631 | |
87accdf7 |
632 | switch (a) { |
633 | case 0: // FM |
634 | Pico32x.regs[0] &= ~P32XS_FM; |
635 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
636 | return; |
19886062 |
637 | case 1: // HEN/irq masks |
638 | if ((d ^ Pico32x.sh2_regs[0]) & 0x80) |
639 | elprintf(EL_ANOMALY|EL_32X, "HEN"); |
f81107f5 |
640 | Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x8f; |
87accdf7 |
641 | Pico32x.sh2_regs[0] &= ~0x80; |
642 | Pico32x.sh2_regs[0] |= d & 0x80; |
a8fd6e37 |
643 | if (d & 1) |
f81107f5 |
644 | p32x_pwm_schedule_sh2(sh2); |
645 | p32x_update_irls(sh2, 0); |
1b3f5844 |
646 | return; |
87accdf7 |
647 | case 5: // H count |
19886062 |
648 | d &= 0xff; |
649 | if (Pico32x.sh2_regs[4 / 2] != d) { |
650 | Pico32x.sh2_regs[4 / 2] = d; |
f81107f5 |
651 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
652 | sh2_cycles_done_m68k(sh2)); |
653 | sh2_end_run(sh2, 4); |
19886062 |
654 | } |
1b3f5844 |
655 | return; |
656 | } |
657 | |
658 | if ((a & 0x30) == 0x20) { |
659 | u8 *r8 = (u8 *)Pico32x.regs; |
a8fd6e37 |
660 | int comreg; |
661 | if (r8[a ^ 1] == d) |
662 | return; |
663 | |
1b3f5844 |
664 | r8[a ^ 1] = d; |
19886062 |
665 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
f81107f5 |
666 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
667 | sh2_cycles_done_m68k(sh2)); |
a8fd6e37 |
668 | comreg = 1 << (a & 0x0f) / 2; |
669 | Pico32x.comm_dirty_sh2 |= comreg; |
1b3f5844 |
670 | return; |
4ea707e1 |
671 | } |
acd35d4c |
672 | } |
673 | |
f81107f5 |
674 | static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
675 | { |
4ea707e1 |
676 | a &= 0xfe; |
acd35d4c |
677 | |
f81107f5 |
678 | sh2->poll_addr = 0; |
19886062 |
679 | |
db1d3564 |
680 | // comm |
a8fd6e37 |
681 | if ((a & 0x30) == 0x20) { |
682 | int comreg; |
683 | if (Pico32x.regs[a / 2] == d) |
684 | return; |
685 | |
b78efee2 |
686 | Pico32x.regs[a / 2] = d; |
19886062 |
687 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
f81107f5 |
688 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
689 | sh2_cycles_done_m68k(sh2)); |
a8fd6e37 |
690 | comreg = 1 << (a & 0x0f) / 2; |
691 | Pico32x.comm_dirty_sh2 |= comreg; |
acd35d4c |
692 | return; |
693 | } |
db1d3564 |
694 | // PWM |
695 | else if ((a & 0x30) == 0x30) { |
f81107f5 |
696 | p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2)); |
db1d3564 |
697 | return; |
698 | } |
acd35d4c |
699 | |
4ea707e1 |
700 | switch (a) { |
87accdf7 |
701 | case 0: // FM |
702 | Pico32x.regs[0] &= ~P32XS_FM; |
703 | Pico32x.regs[0] |= d & P32XS_FM; |
704 | break; |
4ea707e1 |
705 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
706 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
707 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
f81107f5 |
708 | case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls; |
be20816c |
709 | case 0x1c: |
710 | Pico32x.sh2irqs &= ~P32XI_PWM; |
f81107f5 |
711 | p32x_pwm_schedule_sh2(sh2); |
be20816c |
712 | goto irls; |
4ea707e1 |
713 | } |
714 | |
f81107f5 |
715 | p32x_sh2reg_write8(a | 1, d, sh2); |
4ea707e1 |
716 | return; |
717 | |
718 | irls: |
f81107f5 |
719 | p32x_update_irls(sh2, 0); |
4ea707e1 |
720 | } |
721 | |
4ea707e1 |
722 | // ------------------------------------------------------------------ |
34280f9b |
723 | // 32x 68k handlers |
83ff19ec |
724 | |
725 | // after ADEN |
726 | static u32 PicoRead8_32x_on(u32 a) |
be2c4208 |
727 | { |
728 | u32 d = 0; |
729 | if ((a & 0xffc0) == 0x5100) { // a15100 |
730 | d = p32x_reg_read16(a); |
731 | goto out_16to8; |
732 | } |
733 | |
83ff19ec |
734 | if ((a & 0xfc00) != 0x5000) |
735 | return PicoRead8_io(a); |
974fdb5b |
736 | |
737 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
738 | d = p32x_vdp_read16(a); |
739 | goto out_16to8; |
740 | } |
741 | |
974fdb5b |
742 | if ((a & 0xfe00) == 0x5200) { // a15200 |
743 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
744 | goto out_16to8; |
745 | } |
746 | |
be2c4208 |
747 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
748 | d = str_mars[a & 3]; |
749 | goto out; |
750 | } |
751 | |
752 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
753 | return d; |
754 | |
755 | out_16to8: |
756 | if (a & 1) |
757 | d &= 0xff; |
758 | else |
759 | d >>= 8; |
760 | |
761 | out: |
762 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
763 | return d; |
764 | } |
765 | |
83ff19ec |
766 | static u32 PicoRead16_32x_on(u32 a) |
be2c4208 |
767 | { |
768 | u32 d = 0; |
769 | if ((a & 0xffc0) == 0x5100) { // a15100 |
770 | d = p32x_reg_read16(a); |
771 | goto out; |
772 | } |
773 | |
83ff19ec |
774 | if ((a & 0xfc00) != 0x5000) |
775 | return PicoRead16_io(a); |
974fdb5b |
776 | |
777 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
778 | d = p32x_vdp_read16(a); |
779 | goto out; |
780 | } |
781 | |
974fdb5b |
782 | if ((a & 0xfe00) == 0x5200) { // a15200 |
783 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
784 | goto out; |
785 | } |
786 | |
be2c4208 |
787 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
788 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
789 | goto out; |
790 | } |
791 | |
792 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
793 | return d; |
794 | |
795 | out: |
796 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
797 | return d; |
798 | } |
799 | |
83ff19ec |
800 | static void PicoWrite8_32x_on(u32 a, u32 d) |
be2c4208 |
801 | { |
802 | if ((a & 0xfc00) == 0x5000) |
803 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
804 | |
805 | if ((a & 0xffc0) == 0x5100) { // a15100 |
806 | p32x_reg_write8(a, d); |
807 | return; |
808 | } |
809 | |
83ff19ec |
810 | if ((a & 0xfc00) != 0x5000) { |
811 | PicoWrite8_io(a, d); |
812 | return; |
813 | } |
974fdb5b |
814 | |
5609d343 |
815 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
816 | if ((a & 0xfff0) == 0x5180) { // a15180 |
817 | p32x_vdp_write8(a, d); |
818 | return; |
819 | } |
be2c4208 |
820 | |
5609d343 |
821 | // TODO: verify |
822 | if ((a & 0xfe00) == 0x5200) { // a15200 |
823 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
824 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
825 | Pico32x.dirty_pal = 1; |
826 | return; |
827 | } |
974fdb5b |
828 | } |
829 | |
be2c4208 |
830 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
831 | } |
832 | |
83ff19ec |
833 | static void PicoWrite16_32x_on(u32 a, u32 d) |
be2c4208 |
834 | { |
835 | if ((a & 0xfc00) == 0x5000) |
553c3eaa |
836 | elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
be2c4208 |
837 | |
838 | if ((a & 0xffc0) == 0x5100) { // a15100 |
839 | p32x_reg_write16(a, d); |
840 | return; |
841 | } |
842 | |
83ff19ec |
843 | if ((a & 0xfc00) != 0x5000) { |
844 | PicoWrite16_io(a, d); |
845 | return; |
846 | } |
974fdb5b |
847 | |
5609d343 |
848 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
849 | if ((a & 0xfff0) == 0x5180) { // a15180 |
850 | p32x_vdp_write16(a, d, NULL); // FIXME? |
851 | return; |
852 | } |
be2c4208 |
853 | |
5609d343 |
854 | if ((a & 0xfe00) == 0x5200) { // a15200 |
855 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
856 | Pico32x.dirty_pal = 1; |
857 | return; |
858 | } |
974fdb5b |
859 | } |
860 | |
be2c4208 |
861 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
862 | } |
863 | |
83ff19ec |
864 | // before ADEN |
865 | u32 PicoRead8_32x(u32 a) |
866 | { |
867 | u32 d = 0; |
868 | if ((a & 0xffc0) == 0x5100) { // a15100 |
869 | // regs are always readable |
870 | d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1]; |
871 | goto out; |
872 | } |
873 | |
874 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
875 | d = str_mars[a & 3]; |
876 | goto out; |
877 | } |
878 | |
879 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
880 | return d; |
881 | |
882 | out: |
883 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
884 | return d; |
885 | } |
886 | |
887 | u32 PicoRead16_32x(u32 a) |
888 | { |
889 | u32 d = 0; |
890 | if ((a & 0xffc0) == 0x5100) { // a15100 |
891 | d = Pico32x.regs[(a & 0x3f) / 2]; |
892 | goto out; |
893 | } |
894 | |
895 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
896 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
897 | goto out; |
898 | } |
899 | |
900 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
901 | return d; |
902 | |
903 | out: |
904 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
905 | return d; |
906 | } |
907 | |
908 | void PicoWrite8_32x(u32 a, u32 d) |
909 | { |
910 | if ((a & 0xffc0) == 0x5100) { // a15100 |
911 | u16 *r = Pico32x.regs; |
912 | |
913 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
914 | a &= 0x3f; |
915 | if (a == 1) { |
916 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
917 | Pico32xStartup(); |
918 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
919 | r[0] |= P32XS_ADEN; |
920 | p32x_reg_write8(a, d); // forward for reset processing |
921 | } |
922 | return; |
923 | } |
924 | |
925 | // allow only COMM for now |
926 | if ((a & 0x30) == 0x20) { |
927 | u8 *r8 = (u8 *)r; |
928 | r8[a ^ 1] = d; |
929 | } |
930 | return; |
931 | } |
932 | |
933 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
934 | } |
935 | |
936 | void PicoWrite16_32x(u32 a, u32 d) |
937 | { |
938 | if ((a & 0xffc0) == 0x5100) { // a15100 |
939 | u16 *r = Pico32x.regs; |
940 | |
941 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
942 | a &= 0x3e; |
943 | if (a == 0) { |
944 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
945 | Pico32xStartup(); |
946 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
947 | r[0] |= P32XS_ADEN; |
948 | p32x_reg_write16(a, d); // forward for reset processing |
949 | } |
950 | return; |
951 | } |
952 | |
953 | // allow only COMM for now |
954 | if ((a & 0x30) == 0x20) |
955 | r[a / 2] = d; |
956 | return; |
957 | } |
958 | |
959 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
960 | } |
961 | |
34280f9b |
962 | /* quirk: in both normal and overwrite areas only nonzero values go through */ |
963 | #define sh2_write8_dramN(n) \ |
964 | if ((d & 0xff) != 0) { \ |
965 | u8 *dram = (u8 *)Pico32xMem->dram[n]; \ |
966 | dram[(a & 0x1ffff) ^ 1] = d; \ |
967 | } |
968 | |
969 | static void m68k_write8_dram0_ow(u32 a, u32 d) |
970 | { |
971 | sh2_write8_dramN(0); |
972 | } |
973 | |
974 | static void m68k_write8_dram1_ow(u32 a, u32 d) |
975 | { |
976 | sh2_write8_dramN(1); |
977 | } |
978 | |
f81107f5 |
979 | #define sh2_write16_dramN(n) \ |
34280f9b |
980 | u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \ |
981 | if (!(a & 0x20000)) { \ |
982 | *pd = d; \ |
f81107f5 |
983 | return; \ |
34280f9b |
984 | } \ |
985 | /* overwrite */ \ |
986 | if (!(d & 0xff00)) d |= *pd & 0xff00; \ |
987 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; \ |
f81107f5 |
988 | *pd = d; |
34280f9b |
989 | |
990 | static void m68k_write16_dram0_ow(u32 a, u32 d) |
991 | { |
f81107f5 |
992 | sh2_write16_dramN(0); |
34280f9b |
993 | } |
994 | |
995 | static void m68k_write16_dram1_ow(u32 a, u32 d) |
996 | { |
f81107f5 |
997 | sh2_write16_dramN(1); |
34280f9b |
998 | } |
999 | |
83ff19ec |
1000 | // ----------------------------------------------------------------- |
1001 | |
be2c4208 |
1002 | // hint vector is writeable |
1003 | static void PicoWrite8_hint(u32 a, u32 d) |
1004 | { |
1005 | if ((a & 0xfffc) == 0x0070) { |
1006 | Pico32xMem->m68k_rom[a ^ 1] = d; |
1007 | return; |
1008 | } |
1009 | |
1010 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
1011 | } |
1012 | |
1013 | static void PicoWrite16_hint(u32 a, u32 d) |
1014 | { |
1015 | if ((a & 0xfffc) == 0x0070) { |
1016 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
1017 | return; |
1018 | } |
1019 | |
1020 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
1021 | } |
1022 | |
5e49c3a8 |
1023 | static void bank_switch(int b) |
1024 | { |
1025 | unsigned int rs, bank; |
1026 | |
1027 | bank = b << 20; |
1028 | if (bank >= Pico.romsize) { |
1029 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
1030 | return; |
1031 | } |
1032 | |
1033 | // 32X ROM (unbanked, XXX: consider mirroring?) |
1034 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1035 | rs -= bank; |
1036 | if (rs > 0x100000) |
1037 | rs = 0x100000; |
1038 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
1039 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
1040 | |
1041 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
602c28ca |
1042 | |
1043 | #ifdef EMU_F68K |
1044 | // setup FAME fetchmap |
1045 | for (rs = 0x90; rs < 0xa0; rs++) |
be26eb23 |
1046 | PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000; |
602c28ca |
1047 | #endif |
5e49c3a8 |
1048 | } |
1049 | |
acd35d4c |
1050 | // ----------------------------------------------------------------- |
1051 | // SH2 |
1052 | // ----------------------------------------------------------------- |
1053 | |
bcf65fd6 |
1054 | // read8 |
f81107f5 |
1055 | static u32 sh2_read8_unmapped(u32 a, SH2 *sh2) |
acd35d4c |
1056 | { |
f8675e28 |
1057 | elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x", |
1058 | a, 0, sh2_pc(sh2)); |
bcf65fd6 |
1059 | return 0; |
1060 | } |
b78efee2 |
1061 | |
f81107f5 |
1062 | static u32 sh2_read8_cs0(u32 a, SH2 *sh2) |
bcf65fd6 |
1063 | { |
1064 | u32 d = 0; |
97d3f47f |
1065 | |
8a847c12 |
1066 | sh2_burn_cycles(sh2, 1*2); |
1067 | |
bcf65fd6 |
1068 | // 0x3ff00 is veridied |
1069 | if ((a & 0x3ff00) == 0x4000) { |
f81107f5 |
1070 | d = p32x_sh2reg_read16(a, sh2); |
db1d3564 |
1071 | goto out_16to8; |
acd35d4c |
1072 | } |
1073 | |
bcf65fd6 |
1074 | if ((a & 0x3ff00) == 0x4100) { |
acd35d4c |
1075 | d = p32x_vdp_read16(a); |
4a1fb183 |
1076 | sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7); |
db1d3564 |
1077 | goto out_16to8; |
acd35d4c |
1078 | } |
1079 | |
bcf65fd6 |
1080 | // TODO: mirroring? |
f81107f5 |
1081 | if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m)) |
bcf65fd6 |
1082 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
f81107f5 |
1083 | if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s)) |
bcf65fd6 |
1084 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
1085 | |
1f1ff763 |
1086 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
1087 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
1088 | goto out_16to8; |
1089 | } |
1090 | |
f81107f5 |
1091 | return sh2_read8_unmapped(a, sh2); |
acd35d4c |
1092 | |
1093 | out_16to8: |
1094 | if (a & 1) |
1095 | d &= 0xff; |
1096 | else |
1097 | d >>= 8; |
1098 | |
f8675e28 |
1099 | elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x", |
1100 | a, d, sh2_pc(sh2)); |
acd35d4c |
1101 | return d; |
1102 | } |
1103 | |
f81107f5 |
1104 | static u32 sh2_read8_da(u32 a, SH2 *sh2) |
acd35d4c |
1105 | { |
f81107f5 |
1106 | return sh2->data_array[(a & 0xfff) ^ 1]; |
bcf65fd6 |
1107 | } |
acd35d4c |
1108 | |
bcf65fd6 |
1109 | // read16 |
f81107f5 |
1110 | static u32 sh2_read16_unmapped(u32 a, SH2 *sh2) |
bcf65fd6 |
1111 | { |
f8675e28 |
1112 | elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x", |
1113 | a, 0, sh2_pc(sh2)); |
bcf65fd6 |
1114 | return 0; |
1115 | } |
b78efee2 |
1116 | |
f81107f5 |
1117 | static u32 sh2_read16_cs0(u32 a, SH2 *sh2) |
bcf65fd6 |
1118 | { |
1119 | u32 d = 0; |
97d3f47f |
1120 | |
8a847c12 |
1121 | sh2_burn_cycles(sh2, 1*2); |
1122 | |
bcf65fd6 |
1123 | if ((a & 0x3ff00) == 0x4000) { |
f81107f5 |
1124 | d = p32x_sh2reg_read16(a, sh2); |
1b3f5844 |
1125 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
1126 | return d; |
db1d3564 |
1127 | goto out; |
acd35d4c |
1128 | } |
1129 | |
bcf65fd6 |
1130 | if ((a & 0x3ff00) == 0x4100) { |
acd35d4c |
1131 | d = p32x_vdp_read16(a); |
4a1fb183 |
1132 | sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7); |
db1d3564 |
1133 | goto out; |
acd35d4c |
1134 | } |
1135 | |
f81107f5 |
1136 | if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m)) |
bcf65fd6 |
1137 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
f81107f5 |
1138 | if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s)) |
bcf65fd6 |
1139 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
1140 | |
1f1ff763 |
1141 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
1142 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
1143 | goto out; |
1144 | } |
1145 | |
f81107f5 |
1146 | return sh2_read16_unmapped(a, sh2); |
acd35d4c |
1147 | |
1148 | out: |
f8675e28 |
1149 | elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x", |
1150 | a, d, sh2_pc(sh2)); |
acd35d4c |
1151 | return d; |
1152 | } |
1153 | |
f81107f5 |
1154 | static u32 sh2_read16_da(u32 a, SH2 *sh2) |
acd35d4c |
1155 | { |
f81107f5 |
1156 | return ((u16 *)sh2->data_array)[(a & 0xfff) / 2]; |
acd35d4c |
1157 | } |
1158 | |
f81107f5 |
1159 | // writes |
1160 | static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2) |
4b315c21 |
1161 | { |
1162 | } |
1163 | |
bcf65fd6 |
1164 | // write8 |
f81107f5 |
1165 | static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1166 | { |
f8675e28 |
1167 | elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x", |
1168 | a, d & 0xff, sh2_pc(sh2)); |
bcf65fd6 |
1169 | } |
266c6afa |
1170 | |
f81107f5 |
1171 | static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1172 | { |
f8675e28 |
1173 | elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x", |
1174 | a, d & 0xff, sh2_pc(sh2)); |
b78efee2 |
1175 | |
5609d343 |
1176 | if (Pico32x.regs[0] & P32XS_FM) { |
1177 | if ((a & 0x3ff00) == 0x4100) { |
f81107f5 |
1178 | sh2->poll_addr = 0; |
5609d343 |
1179 | p32x_vdp_write8(a, d); |
f81107f5 |
1180 | return; |
5609d343 |
1181 | } |
acd35d4c |
1182 | } |
1183 | |
bcf65fd6 |
1184 | if ((a & 0x3ff00) == 0x4000) { |
f81107f5 |
1185 | p32x_sh2reg_write8(a, d, sh2); |
1186 | return; |
acd35d4c |
1187 | } |
1188 | |
f81107f5 |
1189 | sh2_write8_unmapped(a, d, sh2); |
bcf65fd6 |
1190 | } |
1191 | |
f81107f5 |
1192 | static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1193 | { |
1194 | sh2_write8_dramN(0); |
acd35d4c |
1195 | } |
1196 | |
f81107f5 |
1197 | static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1198 | { |
bcf65fd6 |
1199 | sh2_write8_dramN(1); |
1200 | } |
87accdf7 |
1201 | |
f81107f5 |
1202 | static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2) |
f4bb5d6b |
1203 | { |
1204 | u32 a1 = a & 0x3ffff; |
1205 | #ifdef DRC_SH2 |
1206 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1207 | if (t) |
f81107f5 |
1208 | sh2_drc_wcheck_ram(a, t, sh2->is_slave); |
f4bb5d6b |
1209 | #endif |
1210 | Pico32xMem->sdram[a1 ^ 1] = d; |
1211 | } |
1212 | |
8a847c12 |
1213 | static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2) |
1214 | { |
1215 | // xmen sync hack.. |
1216 | if (a < 0x26000200) |
1217 | sh2_end_run(sh2, 32); |
1218 | |
1219 | sh2_write8_sdram(a, d, sh2); |
1220 | } |
1221 | |
f81107f5 |
1222 | static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1223 | { |
f4bb5d6b |
1224 | u32 a1 = a & 0xfff; |
1225 | #ifdef DRC_SH2 |
f81107f5 |
1226 | int id = sh2->is_slave; |
f4bb5d6b |
1227 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1228 | if (t) |
1229 | sh2_drc_wcheck_da(a, t, id); |
1230 | #endif |
f81107f5 |
1231 | sh2->data_array[a1 ^ 1] = d; |
bcf65fd6 |
1232 | } |
acd35d4c |
1233 | |
bcf65fd6 |
1234 | // write16 |
f81107f5 |
1235 | static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1236 | { |
f8675e28 |
1237 | elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x", |
1238 | a, d & 0xffff, sh2_pc(sh2)); |
bcf65fd6 |
1239 | } |
b78efee2 |
1240 | |
f81107f5 |
1241 | static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1242 | { |
1243 | if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
f8675e28 |
1244 | elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x", |
1245 | a, d & 0xffff, sh2_pc(sh2)); |
266c6afa |
1246 | |
5609d343 |
1247 | if (Pico32x.regs[0] & P32XS_FM) { |
1248 | if ((a & 0x3ff00) == 0x4100) { |
f81107f5 |
1249 | sh2->poll_addr = 0; |
1250 | p32x_vdp_write16(a, d, sh2); |
1251 | return; |
5609d343 |
1252 | } |
acd35d4c |
1253 | |
5609d343 |
1254 | if ((a & 0x3fe00) == 0x4200) { |
1255 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
1256 | Pico32x.dirty_pal = 1; |
f81107f5 |
1257 | return; |
5609d343 |
1258 | } |
acd35d4c |
1259 | } |
1260 | |
bcf65fd6 |
1261 | if ((a & 0x3ff00) == 0x4000) { |
f81107f5 |
1262 | p32x_sh2reg_write16(a, d, sh2); |
1263 | return; |
acd35d4c |
1264 | } |
1265 | |
f81107f5 |
1266 | sh2_write16_unmapped(a, d, sh2); |
bcf65fd6 |
1267 | } |
1268 | |
f81107f5 |
1269 | static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1270 | { |
f81107f5 |
1271 | sh2_write16_dramN(0); |
bcf65fd6 |
1272 | } |
1273 | |
f81107f5 |
1274 | static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1275 | { |
f81107f5 |
1276 | sh2_write16_dramN(1); |
bcf65fd6 |
1277 | } |
1278 | |
f81107f5 |
1279 | static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2) |
f4bb5d6b |
1280 | { |
1281 | u32 a1 = a & 0x3ffff; |
1282 | #ifdef DRC_SH2 |
1283 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1284 | if (t) |
f81107f5 |
1285 | sh2_drc_wcheck_ram(a, t, sh2->is_slave); |
f4bb5d6b |
1286 | #endif |
1287 | ((u16 *)Pico32xMem->sdram)[a1 / 2] = d; |
1288 | } |
1289 | |
f81107f5 |
1290 | static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1291 | { |
f4bb5d6b |
1292 | u32 a1 = a & 0xfff; |
1293 | #ifdef DRC_SH2 |
f81107f5 |
1294 | int id = sh2->is_slave; |
f4bb5d6b |
1295 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1296 | if (t) |
1297 | sh2_drc_wcheck_da(a, t, id); |
1298 | #endif |
f81107f5 |
1299 | ((u16 *)sh2->data_array)[a1 / 2] = d; |
bcf65fd6 |
1300 | } |
1301 | |
1302 | |
f81107f5 |
1303 | typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2); |
1304 | typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2); |
bcf65fd6 |
1305 | |
e05b81fc |
1306 | #define SH2MAP_ADDR2OFFS_R(a) \ |
f81107f5 |
1307 | ((u32)(a) >> SH2_READ_SHIFT) |
e05b81fc |
1308 | |
1309 | #define SH2MAP_ADDR2OFFS_W(a) \ |
1310 | ((u32)(a) >> SH2_WRITE_SHIFT) |
bcf65fd6 |
1311 | |
80599a42 |
1312 | u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2) |
bcf65fd6 |
1313 | { |
1314 | const sh2_memmap *sh2_map = sh2->read8_map; |
1315 | uptr p; |
1316 | |
e05b81fc |
1317 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1318 | p = sh2_map->addr; |
b8a1c09a |
1319 | if (map_flag_set(p)) |
f81107f5 |
1320 | return ((sh2_read_handler *)(p << 1))(a, sh2); |
bcf65fd6 |
1321 | else |
1322 | return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1)); |
1323 | } |
1324 | |
80599a42 |
1325 | u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2) |
bcf65fd6 |
1326 | { |
1327 | const sh2_memmap *sh2_map = sh2->read16_map; |
1328 | uptr p; |
1329 | |
e05b81fc |
1330 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1331 | p = sh2_map->addr; |
b8a1c09a |
1332 | if (map_flag_set(p)) |
f81107f5 |
1333 | return ((sh2_read_handler *)(p << 1))(a, sh2); |
bcf65fd6 |
1334 | else |
1335 | return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1336 | } |
1337 | |
80599a42 |
1338 | u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2) |
bcf65fd6 |
1339 | { |
1340 | const sh2_memmap *sh2_map = sh2->read16_map; |
1341 | sh2_read_handler *handler; |
1342 | u32 offs; |
1343 | uptr p; |
1344 | |
e05b81fc |
1345 | offs = SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1346 | sh2_map += offs; |
1347 | p = sh2_map->addr; |
b8a1c09a |
1348 | if (!map_flag_set(p)) { |
bcf65fd6 |
1349 | // XXX: maybe 32bit access instead with ror? |
1350 | u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1351 | return (pd[0] << 16) | pd[1]; |
1d7a28a7 |
1352 | } |
1353 | |
bcf65fd6 |
1354 | if (offs == 0x1f) |
f81107f5 |
1355 | return sh2_peripheral_read32(a, sh2); |
bcf65fd6 |
1356 | |
1357 | handler = (sh2_read_handler *)(p << 1); |
f81107f5 |
1358 | return (handler(a, sh2) << 16) | handler(a + 2, sh2); |
bcf65fd6 |
1359 | } |
1360 | |
f81107f5 |
1361 | void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1362 | { |
f4bb5d6b |
1363 | const void **sh2_wmap = sh2->write8_tab; |
1364 | sh2_write_handler *wh; |
bcf65fd6 |
1365 | |
e05b81fc |
1366 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
f81107f5 |
1367 | wh(a, d, sh2); |
bcf65fd6 |
1368 | } |
1369 | |
f81107f5 |
1370 | void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1371 | { |
f4bb5d6b |
1372 | const void **sh2_wmap = sh2->write16_tab; |
1373 | sh2_write_handler *wh; |
bcf65fd6 |
1374 | |
e05b81fc |
1375 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
f81107f5 |
1376 | wh(a, d, sh2); |
acd35d4c |
1377 | } |
1378 | |
f81107f5 |
1379 | void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1380 | { |
f4bb5d6b |
1381 | const void **sh2_wmap = sh2->write16_tab; |
f81107f5 |
1382 | sh2_write_handler *wh; |
bcf65fd6 |
1383 | u32 offs; |
bcf65fd6 |
1384 | |
e05b81fc |
1385 | offs = SH2MAP_ADDR2OFFS_W(a); |
bcf65fd6 |
1386 | |
e05b81fc |
1387 | if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) { |
f81107f5 |
1388 | sh2_peripheral_write32(a, d, sh2); |
1389 | return; |
4ea707e1 |
1390 | } |
1391 | |
f81107f5 |
1392 | wh = sh2_wmap[offs]; |
1393 | wh(a, d >> 16, sh2); |
1394 | wh(a + 2, d, sh2); |
acd35d4c |
1395 | } |
1396 | |
bcf65fd6 |
1397 | // ----------------------------------------------------------------- |
1398 | |
83ff19ec |
1399 | static const u16 msh2_code[] = { |
1400 | // trap instructions |
1401 | 0xaffe, // bra <self> |
1402 | 0x0009, // nop |
1403 | // have to wait a bit until m68k initial program finishes clearing stuff |
1404 | // to avoid races with game SH2 code, like in Tempo |
1405 | 0xd004, // mov.l @(_m_ok,pc), r0 |
1406 | 0xd105, // mov.l @(_cnt,pc), r1 |
1407 | 0xd205, // mov.l @(_start,pc), r2 |
1408 | 0x71ff, // add #-1, r1 |
1409 | 0x4115, // cmp/pl r1 |
1410 | 0x89fc, // bt -2 |
1411 | 0xc208, // mov.l r0, @(h'20,gbr) |
1412 | 0x6822, // mov.l @r2, r8 |
1413 | 0x482b, // jmp @r8 |
1414 | 0x0009, // nop |
1415 | ('M'<<8)|'_', ('O'<<8)|'K', |
1416 | 0x0001, 0x0000, |
1417 | 0x2200, 0x03e0 // master start pointer in ROM |
1418 | }; |
1419 | |
1420 | static const u16 ssh2_code[] = { |
1421 | 0xaffe, // bra <self> |
1422 | 0x0009, // nop |
1423 | // code to wait for master, in case authentic master BIOS is used |
1424 | 0xd104, // mov.l @(_m_ok,pc), r1 |
1425 | 0xd206, // mov.l @(_start,pc), r2 |
1426 | 0xc608, // mov.l @(h'20,gbr), r0 |
1427 | 0x3100, // cmp/eq r0, r1 |
1428 | 0x8bfc, // bf #-2 |
1429 | 0xd003, // mov.l @(_s_ok,pc), r0 |
1430 | 0xc209, // mov.l r0, @(h'24,gbr) |
1431 | 0x6822, // mov.l @r2, r8 |
1432 | 0x482b, // jmp @r8 |
1433 | 0x0009, // nop |
1434 | ('M'<<8)|'_', ('O'<<8)|'K', |
1435 | ('S'<<8)|'_', ('O'<<8)|'K', |
1436 | 0x2200, 0x03e4 // slave start pointer in ROM |
1437 | }; |
1438 | |
da77daa9 |
1439 | #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16)) |
83ff19ec |
1440 | static void get_bios(void) |
be2c4208 |
1441 | { |
83ff19ec |
1442 | u16 *ps; |
1443 | u32 *pl; |
be2c4208 |
1444 | int i; |
1445 | |
83ff19ec |
1446 | // M68K ROM |
1447 | if (p32x_bios_g != NULL) { |
1448 | elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS"); |
b4db550e |
1449 | Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1450 | } |
83ff19ec |
1451 | else { |
1452 | // generate 68k ROM |
1453 | ps = (u16 *)Pico32xMem->m68k_rom; |
1454 | pl = (u32 *)ps; |
1455 | for (i = 1; i < 0xc0/4; i++) |
1456 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
1457 | |
83ff19ec |
1458 | // fill with nops |
1459 | for (i = 0xc0/2; i < 0x100/2; i++) |
1460 | ps[i] = 0x4e71; |
be2c4208 |
1461 | |
5e49c3a8 |
1462 | #if 0 |
83ff19ec |
1463 | ps[0xc0/2] = 0x46fc; |
1464 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
1465 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
1466 | #else |
83ff19ec |
1467 | ps[0xfe/2] = 0x4e75; // rts |
5e49c3a8 |
1468 | #endif |
83ff19ec |
1469 | } |
1470 | // fill remaining m68k_rom page with game ROM |
b4db550e |
1471 | memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom), |
1472 | Pico.rom + sizeof(Pico32xMem->m68k_rom), |
1473 | sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1474 | |
83ff19ec |
1475 | // MSH2 |
1476 | if (p32x_bios_m != NULL) { |
1477 | elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS"); |
1478 | Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m)); |
acd35d4c |
1479 | } |
83ff19ec |
1480 | else { |
1481 | pl = (u32 *)Pico32xMem->sh2_rom_m; |
1482 | |
1483 | // fill exception vector table to our trap address |
1484 | for (i = 0; i < 128; i++) |
1485 | pl[i] = HWSWAP(0x200); |
1486 | |
1487 | // startup code |
1488 | memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code)); |
1489 | |
1490 | // reset SP |
1491 | pl[1] = pl[3] = HWSWAP(0x6040000); |
1492 | // start |
1493 | pl[0] = pl[2] = HWSWAP(0x204); |
1494 | } |
1495 | |
1496 | // SSH2 |
1497 | if (p32x_bios_s != NULL) { |
1498 | elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS"); |
1499 | Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s)); |
1500 | } |
1501 | else { |
1502 | pl = (u32 *)Pico32xMem->sh2_rom_s; |
1503 | |
1504 | // fill exception vector table to our trap address |
1505 | for (i = 0; i < 128; i++) |
1506 | pl[i] = HWSWAP(0x200); |
1507 | |
1508 | // startup code |
1509 | memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code)); |
1510 | |
1511 | // reset SP |
1512 | pl[1] = pl[3] = HWSWAP(0x603f800); |
1513 | // start |
1514 | pl[0] = pl[2] = HWSWAP(0x204); |
1515 | } |
1516 | } |
1517 | |
bcf65fd6 |
1518 | #define MAP_MEMORY(m) ((uptr)(m) >> 1) |
b8a1c09a |
1519 | #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) ) |
bcf65fd6 |
1520 | |
f81107f5 |
1521 | static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80]; |
f4bb5d6b |
1522 | // for writes we are using handlers only |
e05b81fc |
1523 | static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80]; |
bcf65fd6 |
1524 | |
1525 | void Pico32xSwapDRAM(int b) |
1526 | { |
1527 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
1528 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
34280f9b |
1529 | cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1530 | cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1531 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff, |
1532 | b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1); |
1533 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff, |
1534 | b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1); |
bcf65fd6 |
1535 | |
1536 | // SH2 |
f81107f5 |
1537 | sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr = |
1538 | sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]); |
bcf65fd6 |
1539 | |
e05b81fc |
1540 | sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0; |
1541 | sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0; |
bcf65fd6 |
1542 | } |
1543 | |
83ff19ec |
1544 | void PicoMemSetup32x(void) |
1545 | { |
1546 | unsigned int rs; |
bcf65fd6 |
1547 | int i; |
83ff19ec |
1548 | |
e743be20 |
1549 | Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0); |
83ff19ec |
1550 | if (Pico32xMem == NULL) { |
1551 | elprintf(EL_STATUS, "OOM"); |
1552 | return; |
1553 | } |
1554 | |
83ff19ec |
1555 | get_bios(); |
acd35d4c |
1556 | |
be2c4208 |
1557 | // cartridge area becomes unmapped |
1558 | // XXX: we take the easy way and don't unmap ROM, |
1559 | // so that we can avoid handling the RV bit. |
1560 | // m68k_map_unmap(0x000000, 0x3fffff); |
1561 | |
1562 | // MD ROM area |
b4db550e |
1563 | rs = sizeof(Pico32xMem->m68k_rom_bank); |
1564 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
1565 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
974fdb5b |
1566 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1567 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1568 | |
be2c4208 |
1569 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
1570 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1571 | if (rs > 0x80000) |
1572 | rs = 0x80000; |
1573 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1574 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
602c28ca |
1575 | #ifdef EMU_F68K |
1576 | // setup FAME fetchmap |
be26eb23 |
1577 | PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom; |
602c28ca |
1578 | for (rs = 0x88; rs < 0x90; rs++) |
be26eb23 |
1579 | PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000; |
602c28ca |
1580 | #endif |
be2c4208 |
1581 | |
1582 | // 32X ROM (banked) |
5e49c3a8 |
1583 | bank_switch(0); |
b78efee2 |
1584 | |
83ff19ec |
1585 | // SYS regs |
1586 | cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1); |
1587 | cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1); |
1588 | cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1); |
1589 | cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1); |
1590 | |
bcf65fd6 |
1591 | // SH2 maps: A31,A30,A29,CS1,CS0 |
1592 | // all unmapped by default |
e05b81fc |
1593 | for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) { |
bcf65fd6 |
1594 | sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped); |
1595 | sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped); |
e05b81fc |
1596 | } |
1597 | |
1598 | for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) { |
f4bb5d6b |
1599 | sh2_write8_map[i] = sh2_write8_unmapped; |
1600 | sh2_write16_map[i] = sh2_write16_unmapped; |
bcf65fd6 |
1601 | } |
1602 | |
4b315c21 |
1603 | // "purge area" |
e05b81fc |
1604 | for (i = 0x40; i <= 0x5f; i++) { |
1605 | sh2_write8_map[i >> 1] = |
1606 | sh2_write16_map[i >> 1] = sh2_write_ignore; |
4b315c21 |
1607 | } |
1608 | |
bcf65fd6 |
1609 | // CS0 |
f81107f5 |
1610 | sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0); |
1611 | sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0); |
e05b81fc |
1612 | sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0; |
1613 | sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0; |
bcf65fd6 |
1614 | // CS1 - ROM |
f81107f5 |
1615 | sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = |
1616 | sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom); |
1617 | sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask = |
1618 | sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME |
bcf65fd6 |
1619 | // CS2 - DRAM - done by Pico32xSwapDRAM() |
f81107f5 |
1620 | sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask = |
1621 | sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff; |
bcf65fd6 |
1622 | // CS3 - SDRAM |
f81107f5 |
1623 | sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr = |
1624 | sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram); |
8a847c12 |
1625 | sh2_write8_map[0x06/2] = sh2_write8_sdram; |
1626 | sh2_write8_map[0x26/2] = sh2_write8_sdram_wt; |
f81107f5 |
1627 | sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram; |
1628 | sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask = |
1629 | sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff; |
bcf65fd6 |
1630 | // SH2 data array |
f81107f5 |
1631 | sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da); |
1632 | sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da); |
1633 | sh2_write8_map[0xc0/2] = sh2_write8_da; |
1634 | sh2_write16_map[0xc0/2] = sh2_write16_da; |
bcf65fd6 |
1635 | // SH2 IO |
f81107f5 |
1636 | sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8); |
1637 | sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16); |
1638 | sh2_write8_map[0xff/2] = sh2_peripheral_write8; |
1639 | sh2_write16_map[0xff/2] = sh2_peripheral_write16; |
bcf65fd6 |
1640 | |
1641 | // map DRAM area, both 68k and SH2 |
1642 | Pico32xSwapDRAM(1); |
1643 | |
1644 | msh2.read8_map = ssh2.read8_map = sh2_read8_map; |
1645 | msh2.read16_map = ssh2.read16_map = sh2_read16_map; |
23686515 |
1646 | msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map; |
1647 | msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map; |
bcf65fd6 |
1648 | |
23686515 |
1649 | sh2_drc_mem_setup(&msh2); |
1650 | sh2_drc_mem_setup(&ssh2); |
be2c4208 |
1651 | } |
1652 | |
27e26273 |
1653 | void Pico32xMemStateLoaded(void) |
b4db550e |
1654 | { |
1655 | bank_switch(Pico32x.regs[4 / 2]); |
1656 | Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS); |
b4db550e |
1657 | memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm)); |
27e26273 |
1658 | Pico32x.dirty_pal = 1; |
51d86e55 |
1659 | |
19886062 |
1660 | Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL); |
1661 | memset(&m68k_poll, 0, sizeof(m68k_poll)); |
1662 | msh2.state = 0; |
1663 | msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0; |
1664 | ssh2.state = 0; |
1665 | ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0; |
1666 | |
b4db550e |
1667 | sh2_drc_flush_all(); |
b4db550e |
1668 | } |
1669 | |
ed4402a7 |
1670 | // vim:shiftwidth=2:ts=2:expandtab |