83ff19ec |
1 | /* |
cff531af |
2 | * PicoDrive |
65514d85 |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | * |
83ff19ec |
8 | * Register map: |
9 | * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm |
10 | * a15102 ........ ......SM ? 4002 // intS intM |
11 | * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint |
12 | * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb] |
13 | * a15108 (32bit DREQ src) 4008 |
14 | * a1510c (32bit DREQ dst) 400c |
15 | * a15110 llllllll llllll00 4010 // DREQ Len |
16 | * a15112 (16bit FIFO reg) 4012 |
17 | * a15114 ? (16bit VRES clr) 4014 |
18 | * a15116 ? (16bit Vint clr) 4016 |
19 | * a15118 ? (16bit Hint clr) 4018 |
20 | * a1511a ........ .......C (16bit CMD clr) 401a // Cm |
21 | * a1511c ? (16bit PWM clr) 401c |
22 | * a1511e ? ? 401e |
23 | * a15120 (16 bytes comm) 2020 |
24 | * a15130 (PWM) 2030 |
65514d85 |
25 | * |
26 | * SH2 addr lines: |
27 | * iii. .cc. ..xx * // Internal, Cs, x |
28 | * |
29 | * sh2 map, wait/bus cycles (from docs): |
30 | * r w |
31 | * rom 0000000-0003fff 1 - |
32 | * sys reg 0004000-00040ff 1 1 |
33 | * vdp reg 0004100-00041ff 5 5 |
34 | * vdp pal 0004200-00043ff 5 5 |
35 | * rom 2000000-23fffff 6-15 |
36 | * dram/fb 4000000-401ffff 5-12 1-3 |
37 | * fb ovr 4020000-403ffff |
38 | * sdram 6000000-603ffff 12 2 (cycles) |
39 | * d.a. c0000000-? |
83ff19ec |
40 | */ |
be2c4208 |
41 | #include "../pico_int.h" |
42 | #include "../memory.h" |
f4bb5d6b |
43 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
44 | |
45 | static const char str_mars[] = "MARS"; |
46 | |
83ff19ec |
47 | void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s; |
974fdb5b |
48 | struct Pico32xMem *Pico32xMem; |
49 | |
5e49c3a8 |
50 | static void bank_switch(int b); |
51 | |
266c6afa |
52 | // poll detection |
19886062 |
53 | #define POLL_THRESHOLD 3 |
4ea707e1 |
54 | |
19886062 |
55 | static struct { |
56 | u32 addr, cycles; |
57 | int cnt; |
58 | } m68k_poll; |
266c6afa |
59 | |
19886062 |
60 | static int m68k_poll_detect(u32 a, u32 cycles, u32 flags) |
266c6afa |
61 | { |
19886062 |
62 | int ret = 0; |
63 | |
64 | if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2 |
65 | && cycles - m68k_poll.cycles <= 64) |
66 | { |
67 | if (m68k_poll.cnt++ > POLL_THRESHOLD) { |
68 | if (!(Pico32x.emu_flags & flags)) { |
69 | elprintf(EL_32X, "m68k poll addr %08x, cyc %u", |
70 | a, cycles - m68k_poll.cycles); |
266c6afa |
71 | ret = 1; |
72 | } |
19886062 |
73 | Pico32x.emu_flags |= flags; |
266c6afa |
74 | } |
75 | } |
c987bb5c |
76 | else { |
19886062 |
77 | m68k_poll.cnt = 0; |
78 | m68k_poll.addr = a; |
c987bb5c |
79 | } |
19886062 |
80 | m68k_poll.cycles = cycles; |
266c6afa |
81 | |
82 | return ret; |
83 | } |
84 | |
19886062 |
85 | void p32x_m68k_poll_event(u32 flags) |
86 | { |
87 | if (Pico32x.emu_flags & flags) { |
88 | elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags, |
89 | Pico32x.emu_flags & ~flags); |
90 | Pico32x.emu_flags &= ~flags; |
91 | SekSetStop(0); |
92 | } |
93 | m68k_poll.addr = m68k_poll.cnt = 0; |
94 | } |
95 | |
96 | static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags) |
266c6afa |
97 | { |
19886062 |
98 | int cycles_left = sh2_cycles_left(sh2); |
99 | |
100 | if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) { |
101 | if (sh2->poll_cnt++ > 3) { |
102 | if (!(sh2->state & flags)) |
103 | elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m', |
104 | sh2->state, sh2->state | flags); |
105 | |
106 | sh2->state |= flags; |
107 | sh2_end_run(sh2, 1); |
108 | pevt_log_sh2(sh2, EVT_POLL_START); |
109 | return; |
110 | } |
111 | } |
be20816c |
112 | else |
19886062 |
113 | sh2->poll_cnt = 0; |
114 | sh2->poll_addr = a; |
115 | sh2->poll_cycles = cycles_left; |
116 | } |
117 | |
118 | void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles) |
119 | { |
120 | if (sh2->state & flags) { |
121 | elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m', |
122 | sh2->state, sh2->state & ~flags); |
123 | |
124 | if (sh2->m68krcycles_done < m68k_cycles) |
125 | sh2->m68krcycles_done = m68k_cycles; |
126 | |
127 | pevt_log_sh2_o(sh2, EVT_POLL_END); |
be20816c |
128 | } |
19886062 |
129 | |
130 | sh2->state &= ~flags; |
131 | sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0; |
266c6afa |
132 | } |
133 | |
19886062 |
134 | static void sh2s_sync_on_read(SH2 *sh2) |
4ea707e1 |
135 | { |
19886062 |
136 | int cycles; |
137 | if (sh2->poll_cnt != 0) |
138 | return; |
139 | |
140 | cycles = sh2_cycles_done(sh2); |
141 | if (cycles > 600) |
142 | p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3); |
4ea707e1 |
143 | } |
144 | |
974fdb5b |
145 | // SH2 faking |
b78efee2 |
146 | //#define FAKE_SH2 |
acd35d4c |
147 | #ifdef FAKE_SH2 |
27e26273 |
148 | static int p32x_csum_faked; |
974fdb5b |
149 | static const u16 comm_fakevals[] = { |
150 | 0x4d5f, 0x4f4b, // M_OK |
151 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
152 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
153 | 0x5331, 0x4d31, // Darxide |
154 | 0x5332, 0x4d32, |
155 | 0x5333, 0x4d33, |
156 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
157 | 0x0002, // Mortal Kombat |
acd35d4c |
158 | // 0, // pad |
be2c4208 |
159 | }; |
acd35d4c |
160 | |
161 | static u32 sh2_comm_faker(u32 a) |
162 | { |
163 | static int f = 0; |
164 | if (a == 0x28 && !p32x_csum_faked) { |
165 | p32x_csum_faked = 1; |
166 | return *(unsigned short *)(Pico.rom + 0x18e); |
167 | } |
168 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
169 | f = 0; |
170 | return comm_fakevals[f++]; |
171 | } |
172 | #endif |
be2c4208 |
173 | |
4ea707e1 |
174 | // ------------------------------------------------------------------ |
b78efee2 |
175 | // 68k regs |
4ea707e1 |
176 | |
be2c4208 |
177 | static u32 p32x_reg_read16(u32 a) |
178 | { |
179 | a &= 0x3e; |
180 | |
3cf9570b |
181 | #if 0 |
974fdb5b |
182 | if ((a & 0x30) == 0x20) |
acd35d4c |
183 | return sh2_comm_faker(a); |
266c6afa |
184 | #else |
5fadfb1c |
185 | if ((a & 0x30) == 0x20) { |
5fadfb1c |
186 | static u32 dr2 = 0; |
a8fd6e37 |
187 | unsigned int cycles = SekCyclesDoneT(); |
188 | int comreg = 1 << (a & 0x0f) / 2; |
189 | |
190 | // evil X-Men proto polls in a dbra loop and expects it to expire.. |
5fadfb1c |
191 | if (SekDar(2) != dr2) |
192 | m68k_poll.cnt = 0; |
193 | dr2 = SekDar(2); |
194 | |
a8fd6e37 |
195 | if (cycles - msh2.m68krcycles_done > 500) |
196 | p32x_sync_sh2s(cycles); |
197 | if (Pico32x.comm_dirty_sh2 & comreg) |
198 | Pico32x.comm_dirty_sh2 &= ~comreg; |
19886062 |
199 | else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) { |
5fadfb1c |
200 | SekSetStop(1); |
201 | SekEndTimeslice(16); |
202 | } |
203 | dr2 = SekDar(2); |
a8fd6e37 |
204 | goto out; |
266c6afa |
205 | } |
acd35d4c |
206 | #endif |
87accdf7 |
207 | |
a8fd6e37 |
208 | if (a == 2) { // INTM, INTS |
209 | unsigned int cycles = SekCyclesDoneT(); |
210 | if (cycles - msh2.m68krcycles_done > 64) |
211 | p32x_sync_sh2s(cycles); |
212 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
213 | } |
214 | |
db1d3564 |
215 | if ((a & 0x30) == 0x30) |
df63f1a6 |
216 | return p32x_pwm_read16(a, SekCyclesDoneT()); |
974fdb5b |
217 | |
a8fd6e37 |
218 | out: |
be2c4208 |
219 | return Pico32x.regs[a / 2]; |
220 | } |
221 | |
be2c4208 |
222 | static void p32x_reg_write8(u32 a, u32 d) |
223 | { |
acd35d4c |
224 | u16 *r = Pico32x.regs; |
be2c4208 |
225 | a &= 0x3f; |
226 | |
97d3f47f |
227 | // for things like bset on comm port |
228 | m68k_poll.cnt = 0; |
229 | |
acd35d4c |
230 | switch (a) { |
4ea707e1 |
231 | case 0: // adapter ctl |
83ff19ec |
232 | r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM); |
233 | return; |
234 | case 1: // adapter ctl, RES bit writeable |
235 | if ((d ^ r[0]) & d & P32XS_nRES) |
236 | p32x_reset_sh2s(); |
237 | r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES); |
1b3f5844 |
238 | return; |
4ea707e1 |
239 | case 3: // irq ctl |
240 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
a8fd6e37 |
241 | p32x_sync_sh2s(SekCyclesDoneT()); |
4ea707e1 |
242 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
19886062 |
243 | p32x_update_irls(NULL); |
4ea707e1 |
244 | } |
b78efee2 |
245 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
a8fd6e37 |
246 | p32x_sync_sh2s(SekCyclesDoneT()); |
b78efee2 |
247 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
19886062 |
248 | p32x_update_irls(NULL); |
b78efee2 |
249 | } |
1b3f5844 |
250 | return; |
4ea707e1 |
251 | case 5: // bank |
acd35d4c |
252 | d &= 7; |
4ea707e1 |
253 | if (r[4 / 2] != d) { |
254 | r[4 / 2] = d; |
acd35d4c |
255 | bank_switch(d); |
256 | } |
1b3f5844 |
257 | return; |
4ea707e1 |
258 | case 7: // DREQ ctl |
97d3f47f |
259 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
1b3f5844 |
260 | return; |
87accdf7 |
261 | case 0x1b: // TV |
262 | r[0x1a / 2] = d; |
1b3f5844 |
263 | return; |
264 | } |
265 | |
266 | if ((a & 0x30) == 0x20) { |
267 | u8 *r8 = (u8 *)r; |
a8fd6e37 |
268 | int cycles = SekCyclesDoneT(); |
269 | int comreg; |
270 | |
271 | if (r8[a ^ 1] == d) |
272 | return; |
19886062 |
273 | |
a8fd6e37 |
274 | comreg = 1 << (a & 0x0f) / 2; |
275 | if (Pico32x.comm_dirty_68k & comreg) |
276 | p32x_sync_sh2s(cycles); |
277 | |
1b3f5844 |
278 | r8[a ^ 1] = d; |
19886062 |
279 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
280 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
a8fd6e37 |
281 | Pico32x.comm_dirty_68k |= comreg; |
282 | |
283 | if (cycles - (int)msh2.m68krcycles_done > 120) |
284 | p32x_sync_sh2s(cycles); |
1b3f5844 |
285 | return; |
5e49c3a8 |
286 | } |
287 | } |
288 | |
289 | static void p32x_reg_write16(u32 a, u32 d) |
290 | { |
acd35d4c |
291 | u16 *r = Pico32x.regs; |
292 | a &= 0x3e; |
293 | |
97d3f47f |
294 | // for things like bset on comm port |
295 | m68k_poll.cnt = 0; |
296 | |
acd35d4c |
297 | switch (a) { |
4ea707e1 |
298 | case 0x00: // adapter ctl |
83ff19ec |
299 | if ((d ^ r[0]) & d & P32XS_nRES) |
300 | p32x_reset_sh2s(); |
301 | r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES)); |
acd35d4c |
302 | return; |
4ea707e1 |
303 | case 0x10: // DREQ len |
304 | r[a / 2] = d & ~3; |
305 | return; |
306 | case 0x12: // FIFO reg |
307 | if (!(r[6 / 2] & P32XS_68S)) { |
308 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
5609d343 |
309 | return; |
4ea707e1 |
310 | } |
df63f1a6 |
311 | if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) { |
312 | Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d; |
313 | if ((Pico32x.dmac0_fifo_ptr & 3) == 0) |
045a4c52 |
314 | p32x_dreq0_trigger(); |
df63f1a6 |
315 | if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN) |
4ea707e1 |
316 | r[6 / 2] |= P32XS_FULL; |
317 | } |
318 | break; |
acd35d4c |
319 | } |
320 | |
4ea707e1 |
321 | // DREQ src, dst |
322 | if ((a & 0x38) == 0x08) { |
323 | r[a / 2] = d; |
324 | return; |
325 | } |
326 | // comm port |
a8fd6e37 |
327 | else if ((a & 0x30) == 0x20) { |
328 | int cycles = SekCyclesDoneT(); |
329 | int comreg; |
330 | |
331 | if (r[a / 2] == d) |
332 | return; |
333 | |
334 | comreg = 1 << (a & 0x0f) / 2; |
335 | if (Pico32x.comm_dirty_68k & comreg) |
336 | p32x_sync_sh2s(cycles); |
337 | |
acd35d4c |
338 | r[a / 2] = d; |
19886062 |
339 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
340 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
a8fd6e37 |
341 | Pico32x.comm_dirty_68k |= comreg; |
342 | |
343 | if (cycles - (int)msh2.m68krcycles_done > 120) |
344 | p32x_sync_sh2s(cycles); |
acd35d4c |
345 | return; |
346 | } |
db1d3564 |
347 | // PWM |
348 | else if ((a & 0x30) == 0x30) { |
df63f1a6 |
349 | p32x_pwm_write16(a, d, SekCyclesDoneT()); |
db1d3564 |
350 | return; |
351 | } |
acd35d4c |
352 | |
5e49c3a8 |
353 | p32x_reg_write8(a + 1, d); |
be2c4208 |
354 | } |
355 | |
4ea707e1 |
356 | // ------------------------------------------------------------------ |
be2c4208 |
357 | // VDP regs |
358 | static u32 p32x_vdp_read16(u32 a) |
359 | { |
360 | a &= 0x0e; |
361 | |
362 | return Pico32x.vdp_regs[a / 2]; |
363 | } |
364 | |
be2c4208 |
365 | static void p32x_vdp_write8(u32 a, u32 d) |
366 | { |
974fdb5b |
367 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
368 | a &= 0x0f; |
369 | |
974fdb5b |
370 | // TODO: verify what's writeable |
be2c4208 |
371 | switch (a) { |
974fdb5b |
372 | case 0x01: |
5e49c3a8 |
373 | // priority inversion is handled in palette |
374 | if ((r[0] ^ d) & P32XV_PRI) |
375 | Pico32x.dirty_pal = 1; |
974fdb5b |
376 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
377 | break; |
e51e5983 |
378 | case 0x03: // shift (for pp mode) |
379 | r[2 / 2] = d & 1; |
380 | break; |
be20816c |
381 | case 0x05: // fill len |
382 | r[4 / 2] = d & 0xff; |
974fdb5b |
383 | break; |
be2c4208 |
384 | case 0x0b: |
974fdb5b |
385 | d &= 1; |
386 | Pico32x.pending_fb = d; |
387 | // if we are blanking and FS bit is changing |
4ea707e1 |
388 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
b4db550e |
389 | r[0x0a/2] ^= P32XV_FS; |
5609d343 |
390 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
391 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
392 | } |
393 | break; |
394 | } |
395 | } |
396 | |
19886062 |
397 | static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2) |
974fdb5b |
398 | { |
be20816c |
399 | a &= 0x0e; |
400 | if (a == 6) { // fill start |
401 | Pico32x.vdp_regs[6 / 2] = d; |
402 | return; |
403 | } |
404 | if (a == 8) { // fill data |
405 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
406 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
a8fd6e37 |
407 | int len1 = len; |
be20816c |
408 | a = Pico32x.vdp_regs[6 / 2]; |
a8fd6e37 |
409 | while (len1--) { |
be20816c |
410 | dram[a] = d; |
411 | a = (a & 0xff00) | ((a + 1) & 0xff); |
412 | } |
a8fd6e37 |
413 | Pico32x.vdp_regs[0x06 / 2] = a; |
414 | Pico32x.vdp_regs[0x08 / 2] = d; |
19886062 |
415 | if (sh2 != NULL && len > 4) { |
a8fd6e37 |
416 | Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN; |
19886062 |
417 | // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles? |
418 | p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len); |
a8fd6e37 |
419 | } |
be20816c |
420 | return; |
421 | } |
422 | |
974fdb5b |
423 | p32x_vdp_write8(a | 1, d); |
424 | } |
425 | |
4ea707e1 |
426 | // ------------------------------------------------------------------ |
acd35d4c |
427 | // SH2 regs |
b78efee2 |
428 | |
429 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
430 | { |
4ea707e1 |
431 | u16 *r = Pico32x.regs; |
432 | a &= 0xfe; // ? |
266c6afa |
433 | |
4ea707e1 |
434 | switch (a) { |
435 | case 0x00: // adapter/irq ctl |
87accdf7 |
436 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; |
c987bb5c |
437 | case 0x04: // H count (often as comm too) |
19886062 |
438 | sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL); |
439 | sh2s_sync_on_read(&sh2s[cpuid]); |
87accdf7 |
440 | return Pico32x.sh2_regs[4 / 2]; |
4ea707e1 |
441 | case 0x10: // DREQ len |
442 | return r[a / 2]; |
acd35d4c |
443 | } |
4ea707e1 |
444 | |
db1d3564 |
445 | // DREQ src, dst |
446 | if ((a & 0x38) == 0x08) |
4ea707e1 |
447 | return r[a / 2]; |
db1d3564 |
448 | // comm port |
449 | if ((a & 0x30) == 0x20) { |
a8fd6e37 |
450 | int comreg = 1 << (a & 0x0f) / 2; |
451 | if (Pico32x.comm_dirty_68k & comreg) |
452 | Pico32x.comm_dirty_68k &= ~comreg; |
19886062 |
453 | else |
454 | sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL); |
455 | sh2s_sync_on_read(&sh2s[cpuid]); |
db1d3564 |
456 | return r[a / 2]; |
457 | } |
458 | if ((a & 0x30) == 0x30) { |
df63f1a6 |
459 | return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid])); |
db1d3564 |
460 | } |
acd35d4c |
461 | |
462 | return 0; |
463 | } |
464 | |
b78efee2 |
465 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
466 | { |
4ea707e1 |
467 | a &= 0xff; |
19886062 |
468 | |
469 | sh2s[cpuid].poll_addr = 0; |
470 | |
87accdf7 |
471 | switch (a) { |
472 | case 0: // FM |
473 | Pico32x.regs[0] &= ~P32XS_FM; |
474 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
475 | return; |
19886062 |
476 | case 1: // HEN/irq masks |
477 | if ((d ^ Pico32x.sh2_regs[0]) & 0x80) |
478 | elprintf(EL_ANOMALY|EL_32X, "HEN"); |
87accdf7 |
479 | Pico32x.sh2irq_mask[cpuid] = d & 0x8f; |
480 | Pico32x.sh2_regs[0] &= ~0x80; |
481 | Pico32x.sh2_regs[0] |= d & 0x80; |
a8fd6e37 |
482 | if (d & 1) |
19886062 |
483 | p32x_pwm_schedule_sh2(&sh2s[cpuid]); |
484 | p32x_update_irls(&sh2s[cpuid]); |
1b3f5844 |
485 | return; |
87accdf7 |
486 | case 5: // H count |
19886062 |
487 | d &= 0xff; |
488 | if (Pico32x.sh2_regs[4 / 2] != d) { |
489 | Pico32x.sh2_regs[4 / 2] = d; |
490 | p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, |
491 | sh2_cycles_done_m68k(&sh2s[cpuid])); |
492 | sh2_end_run(&sh2s[cpuid], 4); |
493 | } |
1b3f5844 |
494 | return; |
495 | } |
496 | |
497 | if ((a & 0x30) == 0x20) { |
498 | u8 *r8 = (u8 *)Pico32x.regs; |
a8fd6e37 |
499 | int comreg; |
500 | if (r8[a ^ 1] == d) |
501 | return; |
502 | |
1b3f5844 |
503 | r8[a ^ 1] = d; |
19886062 |
504 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
505 | p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, |
506 | sh2_cycles_done_m68k(&sh2s[cpuid])); |
a8fd6e37 |
507 | comreg = 1 << (a & 0x0f) / 2; |
508 | Pico32x.comm_dirty_sh2 |= comreg; |
1b3f5844 |
509 | return; |
4ea707e1 |
510 | } |
acd35d4c |
511 | } |
512 | |
b78efee2 |
513 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
514 | { |
4ea707e1 |
515 | a &= 0xfe; |
acd35d4c |
516 | |
19886062 |
517 | sh2s[cpuid].poll_addr = 0; |
518 | |
db1d3564 |
519 | // comm |
a8fd6e37 |
520 | if ((a & 0x30) == 0x20) { |
521 | int comreg; |
522 | if (Pico32x.regs[a / 2] == d) |
523 | return; |
524 | |
b78efee2 |
525 | Pico32x.regs[a / 2] = d; |
19886062 |
526 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
527 | p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, |
528 | sh2_cycles_done_m68k(&sh2s[cpuid])); |
a8fd6e37 |
529 | comreg = 1 << (a & 0x0f) / 2; |
530 | Pico32x.comm_dirty_sh2 |= comreg; |
acd35d4c |
531 | return; |
532 | } |
db1d3564 |
533 | // PWM |
534 | else if ((a & 0x30) == 0x30) { |
df63f1a6 |
535 | p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid])); |
db1d3564 |
536 | return; |
537 | } |
acd35d4c |
538 | |
4ea707e1 |
539 | switch (a) { |
87accdf7 |
540 | case 0: // FM |
541 | Pico32x.regs[0] &= ~P32XS_FM; |
542 | Pico32x.regs[0] |= d & P32XS_FM; |
543 | break; |
4ea707e1 |
544 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
545 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
546 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
547 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
be20816c |
548 | case 0x1c: |
549 | Pico32x.sh2irqs &= ~P32XI_PWM; |
df63f1a6 |
550 | p32x_pwm_schedule_sh2(&sh2s[cpuid]); |
be20816c |
551 | goto irls; |
4ea707e1 |
552 | } |
553 | |
b78efee2 |
554 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
555 | return; |
556 | |
557 | irls: |
19886062 |
558 | p32x_update_irls(&sh2s[cpuid]); |
4ea707e1 |
559 | } |
560 | |
4ea707e1 |
561 | // ------------------------------------------------------------------ |
34280f9b |
562 | // 32x 68k handlers |
83ff19ec |
563 | |
564 | // after ADEN |
565 | static u32 PicoRead8_32x_on(u32 a) |
be2c4208 |
566 | { |
567 | u32 d = 0; |
568 | if ((a & 0xffc0) == 0x5100) { // a15100 |
569 | d = p32x_reg_read16(a); |
570 | goto out_16to8; |
571 | } |
572 | |
83ff19ec |
573 | if ((a & 0xfc00) != 0x5000) |
574 | return PicoRead8_io(a); |
974fdb5b |
575 | |
576 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
577 | d = p32x_vdp_read16(a); |
578 | goto out_16to8; |
579 | } |
580 | |
974fdb5b |
581 | if ((a & 0xfe00) == 0x5200) { // a15200 |
582 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
583 | goto out_16to8; |
584 | } |
585 | |
be2c4208 |
586 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
587 | d = str_mars[a & 3]; |
588 | goto out; |
589 | } |
590 | |
591 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
592 | return d; |
593 | |
594 | out_16to8: |
595 | if (a & 1) |
596 | d &= 0xff; |
597 | else |
598 | d >>= 8; |
599 | |
600 | out: |
601 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
602 | return d; |
603 | } |
604 | |
83ff19ec |
605 | static u32 PicoRead16_32x_on(u32 a) |
be2c4208 |
606 | { |
607 | u32 d = 0; |
608 | if ((a & 0xffc0) == 0x5100) { // a15100 |
609 | d = p32x_reg_read16(a); |
610 | goto out; |
611 | } |
612 | |
83ff19ec |
613 | if ((a & 0xfc00) != 0x5000) |
614 | return PicoRead16_io(a); |
974fdb5b |
615 | |
616 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
617 | d = p32x_vdp_read16(a); |
618 | goto out; |
619 | } |
620 | |
974fdb5b |
621 | if ((a & 0xfe00) == 0x5200) { // a15200 |
622 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
623 | goto out; |
624 | } |
625 | |
be2c4208 |
626 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
627 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
628 | goto out; |
629 | } |
630 | |
631 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
632 | return d; |
633 | |
634 | out: |
635 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
636 | return d; |
637 | } |
638 | |
83ff19ec |
639 | static void PicoWrite8_32x_on(u32 a, u32 d) |
be2c4208 |
640 | { |
641 | if ((a & 0xfc00) == 0x5000) |
642 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
643 | |
644 | if ((a & 0xffc0) == 0x5100) { // a15100 |
645 | p32x_reg_write8(a, d); |
646 | return; |
647 | } |
648 | |
83ff19ec |
649 | if ((a & 0xfc00) != 0x5000) { |
650 | PicoWrite8_io(a, d); |
651 | return; |
652 | } |
974fdb5b |
653 | |
5609d343 |
654 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
655 | if ((a & 0xfff0) == 0x5180) { // a15180 |
656 | p32x_vdp_write8(a, d); |
657 | return; |
658 | } |
be2c4208 |
659 | |
5609d343 |
660 | // TODO: verify |
661 | if ((a & 0xfe00) == 0x5200) { // a15200 |
662 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
663 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
664 | Pico32x.dirty_pal = 1; |
665 | return; |
666 | } |
974fdb5b |
667 | } |
668 | |
be2c4208 |
669 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
670 | } |
671 | |
83ff19ec |
672 | static void PicoWrite16_32x_on(u32 a, u32 d) |
be2c4208 |
673 | { |
674 | if ((a & 0xfc00) == 0x5000) |
553c3eaa |
675 | elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
be2c4208 |
676 | |
677 | if ((a & 0xffc0) == 0x5100) { // a15100 |
678 | p32x_reg_write16(a, d); |
679 | return; |
680 | } |
681 | |
83ff19ec |
682 | if ((a & 0xfc00) != 0x5000) { |
683 | PicoWrite16_io(a, d); |
684 | return; |
685 | } |
974fdb5b |
686 | |
5609d343 |
687 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
688 | if ((a & 0xfff0) == 0x5180) { // a15180 |
689 | p32x_vdp_write16(a, d, NULL); // FIXME? |
690 | return; |
691 | } |
be2c4208 |
692 | |
5609d343 |
693 | if ((a & 0xfe00) == 0x5200) { // a15200 |
694 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
695 | Pico32x.dirty_pal = 1; |
696 | return; |
697 | } |
974fdb5b |
698 | } |
699 | |
be2c4208 |
700 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
701 | } |
702 | |
83ff19ec |
703 | // before ADEN |
704 | u32 PicoRead8_32x(u32 a) |
705 | { |
706 | u32 d = 0; |
707 | if ((a & 0xffc0) == 0x5100) { // a15100 |
708 | // regs are always readable |
709 | d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1]; |
710 | goto out; |
711 | } |
712 | |
713 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
714 | d = str_mars[a & 3]; |
715 | goto out; |
716 | } |
717 | |
718 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
719 | return d; |
720 | |
721 | out: |
722 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
723 | return d; |
724 | } |
725 | |
726 | u32 PicoRead16_32x(u32 a) |
727 | { |
728 | u32 d = 0; |
729 | if ((a & 0xffc0) == 0x5100) { // a15100 |
730 | d = Pico32x.regs[(a & 0x3f) / 2]; |
731 | goto out; |
732 | } |
733 | |
734 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
735 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
736 | goto out; |
737 | } |
738 | |
739 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
740 | return d; |
741 | |
742 | out: |
743 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
744 | return d; |
745 | } |
746 | |
747 | void PicoWrite8_32x(u32 a, u32 d) |
748 | { |
749 | if ((a & 0xffc0) == 0x5100) { // a15100 |
750 | u16 *r = Pico32x.regs; |
751 | |
752 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
753 | a &= 0x3f; |
754 | if (a == 1) { |
755 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
756 | Pico32xStartup(); |
757 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
758 | r[0] |= P32XS_ADEN; |
759 | p32x_reg_write8(a, d); // forward for reset processing |
760 | } |
761 | return; |
762 | } |
763 | |
764 | // allow only COMM for now |
765 | if ((a & 0x30) == 0x20) { |
766 | u8 *r8 = (u8 *)r; |
767 | r8[a ^ 1] = d; |
768 | } |
769 | return; |
770 | } |
771 | |
772 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
773 | } |
774 | |
775 | void PicoWrite16_32x(u32 a, u32 d) |
776 | { |
777 | if ((a & 0xffc0) == 0x5100) { // a15100 |
778 | u16 *r = Pico32x.regs; |
779 | |
780 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
781 | a &= 0x3e; |
782 | if (a == 0) { |
783 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
784 | Pico32xStartup(); |
785 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
786 | r[0] |= P32XS_ADEN; |
787 | p32x_reg_write16(a, d); // forward for reset processing |
788 | } |
789 | return; |
790 | } |
791 | |
792 | // allow only COMM for now |
793 | if ((a & 0x30) == 0x20) |
794 | r[a / 2] = d; |
795 | return; |
796 | } |
797 | |
798 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
799 | } |
800 | |
34280f9b |
801 | /* quirk: in both normal and overwrite areas only nonzero values go through */ |
802 | #define sh2_write8_dramN(n) \ |
803 | if ((d & 0xff) != 0) { \ |
804 | u8 *dram = (u8 *)Pico32xMem->dram[n]; \ |
805 | dram[(a & 0x1ffff) ^ 1] = d; \ |
806 | } |
807 | |
808 | static void m68k_write8_dram0_ow(u32 a, u32 d) |
809 | { |
810 | sh2_write8_dramN(0); |
811 | } |
812 | |
813 | static void m68k_write8_dram1_ow(u32 a, u32 d) |
814 | { |
815 | sh2_write8_dramN(1); |
816 | } |
817 | |
818 | #define sh2_write16_dramN(n, ret) \ |
819 | u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \ |
820 | if (!(a & 0x20000)) { \ |
821 | *pd = d; \ |
822 | return ret; \ |
823 | } \ |
824 | /* overwrite */ \ |
825 | if (!(d & 0xff00)) d |= *pd & 0xff00; \ |
826 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; \ |
827 | *pd = d; \ |
828 | return ret |
829 | |
830 | static void m68k_write16_dram0_ow(u32 a, u32 d) |
831 | { |
832 | sh2_write16_dramN(0,); |
833 | } |
834 | |
835 | static void m68k_write16_dram1_ow(u32 a, u32 d) |
836 | { |
837 | sh2_write16_dramN(1,); |
838 | } |
839 | |
83ff19ec |
840 | // ----------------------------------------------------------------- |
841 | |
be2c4208 |
842 | // hint vector is writeable |
843 | static void PicoWrite8_hint(u32 a, u32 d) |
844 | { |
845 | if ((a & 0xfffc) == 0x0070) { |
846 | Pico32xMem->m68k_rom[a ^ 1] = d; |
847 | return; |
848 | } |
849 | |
850 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
851 | } |
852 | |
853 | static void PicoWrite16_hint(u32 a, u32 d) |
854 | { |
855 | if ((a & 0xfffc) == 0x0070) { |
856 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
857 | return; |
858 | } |
859 | |
860 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
861 | } |
862 | |
5e49c3a8 |
863 | static void bank_switch(int b) |
864 | { |
865 | unsigned int rs, bank; |
866 | |
867 | bank = b << 20; |
868 | if (bank >= Pico.romsize) { |
869 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
870 | return; |
871 | } |
872 | |
873 | // 32X ROM (unbanked, XXX: consider mirroring?) |
874 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
875 | rs -= bank; |
876 | if (rs > 0x100000) |
877 | rs = 0x100000; |
878 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
879 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
880 | |
881 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
602c28ca |
882 | |
883 | #ifdef EMU_F68K |
884 | // setup FAME fetchmap |
885 | for (rs = 0x90; rs < 0xa0; rs++) |
be26eb23 |
886 | PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000; |
602c28ca |
887 | #endif |
5e49c3a8 |
888 | } |
889 | |
acd35d4c |
890 | // ----------------------------------------------------------------- |
891 | // SH2 |
892 | // ----------------------------------------------------------------- |
893 | |
bcf65fd6 |
894 | // read8 |
895 | static u32 sh2_read8_unmapped(u32 a, int id) |
acd35d4c |
896 | { |
bcf65fd6 |
897 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
898 | id ? 's' : 'm', a, 0, sh2_pc(id)); |
899 | return 0; |
900 | } |
b78efee2 |
901 | |
bcf65fd6 |
902 | static u32 sh2_read8_cs0(u32 a, int id) |
903 | { |
904 | u32 d = 0; |
97d3f47f |
905 | |
bcf65fd6 |
906 | // 0x3ff00 is veridied |
907 | if ((a & 0x3ff00) == 0x4000) { |
b78efee2 |
908 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
909 | goto out_16to8; |
acd35d4c |
910 | } |
911 | |
bcf65fd6 |
912 | if ((a & 0x3ff00) == 0x4100) { |
acd35d4c |
913 | d = p32x_vdp_read16(a); |
19886062 |
914 | sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL); |
db1d3564 |
915 | goto out_16to8; |
acd35d4c |
916 | } |
917 | |
bcf65fd6 |
918 | // TODO: mirroring? |
919 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
920 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
921 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
922 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
923 | |
1f1ff763 |
924 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
925 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
926 | goto out_16to8; |
927 | } |
928 | |
bcf65fd6 |
929 | return sh2_read8_unmapped(a, id); |
acd35d4c |
930 | |
931 | out_16to8: |
932 | if (a & 1) |
933 | d &= 0xff; |
934 | else |
935 | d >>= 8; |
936 | |
b78efee2 |
937 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
938 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
939 | return d; |
940 | } |
941 | |
bcf65fd6 |
942 | static u32 sh2_read8_da(u32 a, int id) |
acd35d4c |
943 | { |
bcf65fd6 |
944 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
945 | } |
acd35d4c |
946 | |
bcf65fd6 |
947 | // read16 |
948 | static u32 sh2_read16_unmapped(u32 a, int id) |
949 | { |
950 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
951 | id ? 's' : 'm', a, 0, sh2_pc(id)); |
952 | return 0; |
953 | } |
b78efee2 |
954 | |
bcf65fd6 |
955 | static u32 sh2_read16_cs0(u32 a, int id) |
956 | { |
957 | u32 d = 0; |
97d3f47f |
958 | |
bcf65fd6 |
959 | if ((a & 0x3ff00) == 0x4000) { |
b78efee2 |
960 | d = p32x_sh2reg_read16(a, id); |
1b3f5844 |
961 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
962 | return d; |
db1d3564 |
963 | goto out; |
acd35d4c |
964 | } |
965 | |
bcf65fd6 |
966 | if ((a & 0x3ff00) == 0x4100) { |
acd35d4c |
967 | d = p32x_vdp_read16(a); |
19886062 |
968 | sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL); |
db1d3564 |
969 | goto out; |
acd35d4c |
970 | } |
971 | |
bcf65fd6 |
972 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
973 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
974 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
975 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
976 | |
1f1ff763 |
977 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
978 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
979 | goto out; |
980 | } |
981 | |
bcf65fd6 |
982 | return sh2_read16_unmapped(a, id); |
acd35d4c |
983 | |
984 | out: |
b78efee2 |
985 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
986 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
987 | return d; |
988 | } |
989 | |
bcf65fd6 |
990 | static u32 sh2_read16_da(u32 a, int id) |
acd35d4c |
991 | { |
bcf65fd6 |
992 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
acd35d4c |
993 | } |
994 | |
e05b81fc |
995 | static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id) |
4b315c21 |
996 | { |
e05b81fc |
997 | return 0; |
4b315c21 |
998 | } |
999 | |
bcf65fd6 |
1000 | // write8 |
e05b81fc |
1001 | static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id) |
acd35d4c |
1002 | { |
bcf65fd6 |
1003 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
1004 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
e05b81fc |
1005 | return 0; |
bcf65fd6 |
1006 | } |
266c6afa |
1007 | |
e05b81fc |
1008 | static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id) |
bcf65fd6 |
1009 | { |
1010 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
1011 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
b78efee2 |
1012 | |
5609d343 |
1013 | if (Pico32x.regs[0] & P32XS_FM) { |
1014 | if ((a & 0x3ff00) == 0x4100) { |
1015 | sh2s[id].poll_addr = 0; |
1016 | p32x_vdp_write8(a, d); |
1017 | return 0; |
1018 | } |
acd35d4c |
1019 | } |
1020 | |
bcf65fd6 |
1021 | if ((a & 0x3ff00) == 0x4000) { |
b78efee2 |
1022 | p32x_sh2reg_write8(a, d, id); |
e05b81fc |
1023 | return 1; |
acd35d4c |
1024 | } |
1025 | |
e05b81fc |
1026 | return sh2_write8_unmapped(a, d, id); |
bcf65fd6 |
1027 | } |
1028 | |
e05b81fc |
1029 | static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id) |
bcf65fd6 |
1030 | { |
1031 | sh2_write8_dramN(0); |
34280f9b |
1032 | return 0; |
acd35d4c |
1033 | } |
1034 | |
e05b81fc |
1035 | static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id) |
acd35d4c |
1036 | { |
bcf65fd6 |
1037 | sh2_write8_dramN(1); |
34280f9b |
1038 | return 0; |
bcf65fd6 |
1039 | } |
87accdf7 |
1040 | |
e05b81fc |
1041 | static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id) |
f4bb5d6b |
1042 | { |
1043 | u32 a1 = a & 0x3ffff; |
1044 | #ifdef DRC_SH2 |
1045 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1046 | if (t) |
1047 | sh2_drc_wcheck_ram(a, t, id); |
1048 | #endif |
1049 | Pico32xMem->sdram[a1 ^ 1] = d; |
e05b81fc |
1050 | return 0; |
f4bb5d6b |
1051 | } |
1052 | |
e05b81fc |
1053 | static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id) |
bcf65fd6 |
1054 | { |
f4bb5d6b |
1055 | u32 a1 = a & 0xfff; |
1056 | #ifdef DRC_SH2 |
1057 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1058 | if (t) |
1059 | sh2_drc_wcheck_da(a, t, id); |
1060 | #endif |
1061 | Pico32xMem->data_array[id][a1 ^ 1] = d; |
e05b81fc |
1062 | return 0; |
bcf65fd6 |
1063 | } |
acd35d4c |
1064 | |
bcf65fd6 |
1065 | // write16 |
e05b81fc |
1066 | static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id) |
bcf65fd6 |
1067 | { |
1068 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
1069 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
e05b81fc |
1070 | return 0; |
bcf65fd6 |
1071 | } |
b78efee2 |
1072 | |
e05b81fc |
1073 | static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id) |
bcf65fd6 |
1074 | { |
1075 | if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
1076 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
1077 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
266c6afa |
1078 | |
5609d343 |
1079 | if (Pico32x.regs[0] & P32XS_FM) { |
1080 | if ((a & 0x3ff00) == 0x4100) { |
1081 | sh2s[id].poll_addr = 0; |
1082 | p32x_vdp_write16(a, d, &sh2s[id]); |
1083 | return 0; |
1084 | } |
acd35d4c |
1085 | |
5609d343 |
1086 | if ((a & 0x3fe00) == 0x4200) { |
1087 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
1088 | Pico32x.dirty_pal = 1; |
1089 | return 0; |
1090 | } |
acd35d4c |
1091 | } |
1092 | |
bcf65fd6 |
1093 | if ((a & 0x3ff00) == 0x4000) { |
b78efee2 |
1094 | p32x_sh2reg_write16(a, d, id); |
e05b81fc |
1095 | return 1; |
acd35d4c |
1096 | } |
1097 | |
e05b81fc |
1098 | return sh2_write16_unmapped(a, d, id); |
bcf65fd6 |
1099 | } |
1100 | |
e05b81fc |
1101 | static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id) |
bcf65fd6 |
1102 | { |
34280f9b |
1103 | sh2_write16_dramN(0, 0); |
bcf65fd6 |
1104 | } |
1105 | |
e05b81fc |
1106 | static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id) |
bcf65fd6 |
1107 | { |
34280f9b |
1108 | sh2_write16_dramN(1, 0); |
bcf65fd6 |
1109 | } |
1110 | |
e05b81fc |
1111 | static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id) |
f4bb5d6b |
1112 | { |
1113 | u32 a1 = a & 0x3ffff; |
1114 | #ifdef DRC_SH2 |
1115 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1116 | if (t) |
1117 | sh2_drc_wcheck_ram(a, t, id); |
1118 | #endif |
1119 | ((u16 *)Pico32xMem->sdram)[a1 / 2] = d; |
e05b81fc |
1120 | return 0; |
f4bb5d6b |
1121 | } |
1122 | |
e05b81fc |
1123 | static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id) |
bcf65fd6 |
1124 | { |
f4bb5d6b |
1125 | u32 a1 = a & 0xfff; |
1126 | #ifdef DRC_SH2 |
1127 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1128 | if (t) |
1129 | sh2_drc_wcheck_da(a, t, id); |
1130 | #endif |
1131 | ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d; |
e05b81fc |
1132 | return 0; |
bcf65fd6 |
1133 | } |
1134 | |
1135 | |
e05b81fc |
1136 | typedef u32 (sh2_read_handler)(u32 a, int id); |
1137 | typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id); |
bcf65fd6 |
1138 | |
e05b81fc |
1139 | #define SH2MAP_ADDR2OFFS_R(a) \ |
1140 | ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c)) |
1141 | |
1142 | #define SH2MAP_ADDR2OFFS_W(a) \ |
1143 | ((u32)(a) >> SH2_WRITE_SHIFT) |
bcf65fd6 |
1144 | |
80599a42 |
1145 | u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2) |
bcf65fd6 |
1146 | { |
1147 | const sh2_memmap *sh2_map = sh2->read8_map; |
1148 | uptr p; |
1149 | |
e05b81fc |
1150 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1151 | p = sh2_map->addr; |
b8a1c09a |
1152 | if (map_flag_set(p)) |
bcf65fd6 |
1153 | return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave); |
1154 | else |
1155 | return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1)); |
1156 | } |
1157 | |
80599a42 |
1158 | u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2) |
bcf65fd6 |
1159 | { |
1160 | const sh2_memmap *sh2_map = sh2->read16_map; |
1161 | uptr p; |
1162 | |
e05b81fc |
1163 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1164 | p = sh2_map->addr; |
b8a1c09a |
1165 | if (map_flag_set(p)) |
bcf65fd6 |
1166 | return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave); |
1167 | else |
1168 | return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1169 | } |
1170 | |
80599a42 |
1171 | u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2) |
bcf65fd6 |
1172 | { |
1173 | const sh2_memmap *sh2_map = sh2->read16_map; |
1174 | sh2_read_handler *handler; |
1175 | u32 offs; |
1176 | uptr p; |
1177 | |
e05b81fc |
1178 | offs = SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1179 | sh2_map += offs; |
1180 | p = sh2_map->addr; |
b8a1c09a |
1181 | if (!map_flag_set(p)) { |
bcf65fd6 |
1182 | // XXX: maybe 32bit access instead with ror? |
1183 | u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1184 | return (pd[0] << 16) | pd[1]; |
1d7a28a7 |
1185 | } |
1186 | |
bcf65fd6 |
1187 | if (offs == 0x1f) |
1188 | return sh2_peripheral_read32(a, sh2->is_slave); |
1189 | |
1190 | handler = (sh2_read_handler *)(p << 1); |
1191 | return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave); |
1192 | } |
1193 | |
e05b81fc |
1194 | // return nonzero if write potentially causes an interrupt (used by drc) |
1195 | int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1196 | { |
f4bb5d6b |
1197 | const void **sh2_wmap = sh2->write8_tab; |
1198 | sh2_write_handler *wh; |
bcf65fd6 |
1199 | |
e05b81fc |
1200 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
1201 | return wh(a, d, sh2->is_slave); |
bcf65fd6 |
1202 | } |
1203 | |
e05b81fc |
1204 | int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1205 | { |
f4bb5d6b |
1206 | const void **sh2_wmap = sh2->write16_tab; |
1207 | sh2_write_handler *wh; |
bcf65fd6 |
1208 | |
e05b81fc |
1209 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
1210 | return wh(a, d, sh2->is_slave); |
acd35d4c |
1211 | } |
1212 | |
e05b81fc |
1213 | int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1214 | { |
f4bb5d6b |
1215 | const void **sh2_wmap = sh2->write16_tab; |
bcf65fd6 |
1216 | sh2_write_handler *handler; |
1217 | u32 offs; |
bcf65fd6 |
1218 | |
e05b81fc |
1219 | offs = SH2MAP_ADDR2OFFS_W(a); |
bcf65fd6 |
1220 | |
e05b81fc |
1221 | if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) { |
bcf65fd6 |
1222 | sh2_peripheral_write32(a, d, sh2->is_slave); |
e05b81fc |
1223 | return 0; |
4ea707e1 |
1224 | } |
1225 | |
f4bb5d6b |
1226 | handler = sh2_wmap[offs]; |
bcf65fd6 |
1227 | handler(a, d >> 16, sh2->is_slave); |
1228 | handler(a + 2, d, sh2->is_slave); |
e05b81fc |
1229 | return 0; |
acd35d4c |
1230 | } |
1231 | |
bcf65fd6 |
1232 | // ----------------------------------------------------------------- |
1233 | |
83ff19ec |
1234 | static const u16 msh2_code[] = { |
1235 | // trap instructions |
1236 | 0xaffe, // bra <self> |
1237 | 0x0009, // nop |
1238 | // have to wait a bit until m68k initial program finishes clearing stuff |
1239 | // to avoid races with game SH2 code, like in Tempo |
1240 | 0xd004, // mov.l @(_m_ok,pc), r0 |
1241 | 0xd105, // mov.l @(_cnt,pc), r1 |
1242 | 0xd205, // mov.l @(_start,pc), r2 |
1243 | 0x71ff, // add #-1, r1 |
1244 | 0x4115, // cmp/pl r1 |
1245 | 0x89fc, // bt -2 |
1246 | 0xc208, // mov.l r0, @(h'20,gbr) |
1247 | 0x6822, // mov.l @r2, r8 |
1248 | 0x482b, // jmp @r8 |
1249 | 0x0009, // nop |
1250 | ('M'<<8)|'_', ('O'<<8)|'K', |
1251 | 0x0001, 0x0000, |
1252 | 0x2200, 0x03e0 // master start pointer in ROM |
1253 | }; |
1254 | |
1255 | static const u16 ssh2_code[] = { |
1256 | 0xaffe, // bra <self> |
1257 | 0x0009, // nop |
1258 | // code to wait for master, in case authentic master BIOS is used |
1259 | 0xd104, // mov.l @(_m_ok,pc), r1 |
1260 | 0xd206, // mov.l @(_start,pc), r2 |
1261 | 0xc608, // mov.l @(h'20,gbr), r0 |
1262 | 0x3100, // cmp/eq r0, r1 |
1263 | 0x8bfc, // bf #-2 |
1264 | 0xd003, // mov.l @(_s_ok,pc), r0 |
1265 | 0xc209, // mov.l r0, @(h'24,gbr) |
1266 | 0x6822, // mov.l @r2, r8 |
1267 | 0x482b, // jmp @r8 |
1268 | 0x0009, // nop |
1269 | ('M'<<8)|'_', ('O'<<8)|'K', |
1270 | ('S'<<8)|'_', ('O'<<8)|'K', |
1271 | 0x2200, 0x03e4 // slave start pointer in ROM |
1272 | }; |
1273 | |
da77daa9 |
1274 | #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16)) |
83ff19ec |
1275 | static void get_bios(void) |
be2c4208 |
1276 | { |
83ff19ec |
1277 | u16 *ps; |
1278 | u32 *pl; |
be2c4208 |
1279 | int i; |
1280 | |
83ff19ec |
1281 | // M68K ROM |
1282 | if (p32x_bios_g != NULL) { |
1283 | elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS"); |
b4db550e |
1284 | Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1285 | } |
83ff19ec |
1286 | else { |
1287 | // generate 68k ROM |
1288 | ps = (u16 *)Pico32xMem->m68k_rom; |
1289 | pl = (u32 *)ps; |
1290 | for (i = 1; i < 0xc0/4; i++) |
1291 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
1292 | |
83ff19ec |
1293 | // fill with nops |
1294 | for (i = 0xc0/2; i < 0x100/2; i++) |
1295 | ps[i] = 0x4e71; |
be2c4208 |
1296 | |
5e49c3a8 |
1297 | #if 0 |
83ff19ec |
1298 | ps[0xc0/2] = 0x46fc; |
1299 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
1300 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
1301 | #else |
83ff19ec |
1302 | ps[0xfe/2] = 0x4e75; // rts |
5e49c3a8 |
1303 | #endif |
83ff19ec |
1304 | } |
1305 | // fill remaining m68k_rom page with game ROM |
b4db550e |
1306 | memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom), |
1307 | Pico.rom + sizeof(Pico32xMem->m68k_rom), |
1308 | sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1309 | |
83ff19ec |
1310 | // MSH2 |
1311 | if (p32x_bios_m != NULL) { |
1312 | elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS"); |
1313 | Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m)); |
acd35d4c |
1314 | } |
83ff19ec |
1315 | else { |
1316 | pl = (u32 *)Pico32xMem->sh2_rom_m; |
1317 | |
1318 | // fill exception vector table to our trap address |
1319 | for (i = 0; i < 128; i++) |
1320 | pl[i] = HWSWAP(0x200); |
1321 | |
1322 | // startup code |
1323 | memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code)); |
1324 | |
1325 | // reset SP |
1326 | pl[1] = pl[3] = HWSWAP(0x6040000); |
1327 | // start |
1328 | pl[0] = pl[2] = HWSWAP(0x204); |
1329 | } |
1330 | |
1331 | // SSH2 |
1332 | if (p32x_bios_s != NULL) { |
1333 | elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS"); |
1334 | Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s)); |
1335 | } |
1336 | else { |
1337 | pl = (u32 *)Pico32xMem->sh2_rom_s; |
1338 | |
1339 | // fill exception vector table to our trap address |
1340 | for (i = 0; i < 128; i++) |
1341 | pl[i] = HWSWAP(0x200); |
1342 | |
1343 | // startup code |
1344 | memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code)); |
1345 | |
1346 | // reset SP |
1347 | pl[1] = pl[3] = HWSWAP(0x603f800); |
1348 | // start |
1349 | pl[0] = pl[2] = HWSWAP(0x204); |
1350 | } |
1351 | } |
1352 | |
bcf65fd6 |
1353 | #define MAP_MEMORY(m) ((uptr)(m) >> 1) |
b8a1c09a |
1354 | #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) ) |
bcf65fd6 |
1355 | |
1356 | static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20]; |
f4bb5d6b |
1357 | // for writes we are using handlers only |
e05b81fc |
1358 | static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80]; |
bcf65fd6 |
1359 | |
1360 | void Pico32xSwapDRAM(int b) |
1361 | { |
1362 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
1363 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
34280f9b |
1364 | cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1365 | cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1366 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff, |
1367 | b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1); |
1368 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff, |
1369 | b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1); |
bcf65fd6 |
1370 | |
1371 | // SH2 |
1372 | sh2_read8_map[2].addr = sh2_read8_map[6].addr = |
1373 | sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]); |
1374 | |
e05b81fc |
1375 | sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0; |
1376 | sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0; |
bcf65fd6 |
1377 | } |
1378 | |
83ff19ec |
1379 | void PicoMemSetup32x(void) |
1380 | { |
1381 | unsigned int rs; |
bcf65fd6 |
1382 | int i; |
83ff19ec |
1383 | |
e743be20 |
1384 | Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0); |
83ff19ec |
1385 | if (Pico32xMem == NULL) { |
1386 | elprintf(EL_STATUS, "OOM"); |
1387 | return; |
1388 | } |
1389 | |
83ff19ec |
1390 | get_bios(); |
acd35d4c |
1391 | |
be2c4208 |
1392 | // cartridge area becomes unmapped |
1393 | // XXX: we take the easy way and don't unmap ROM, |
1394 | // so that we can avoid handling the RV bit. |
1395 | // m68k_map_unmap(0x000000, 0x3fffff); |
1396 | |
1397 | // MD ROM area |
b4db550e |
1398 | rs = sizeof(Pico32xMem->m68k_rom_bank); |
1399 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
1400 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
974fdb5b |
1401 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1402 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1403 | |
be2c4208 |
1404 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
1405 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1406 | if (rs > 0x80000) |
1407 | rs = 0x80000; |
1408 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1409 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
602c28ca |
1410 | #ifdef EMU_F68K |
1411 | // setup FAME fetchmap |
be26eb23 |
1412 | PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom; |
602c28ca |
1413 | for (rs = 0x88; rs < 0x90; rs++) |
be26eb23 |
1414 | PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000; |
602c28ca |
1415 | #endif |
be2c4208 |
1416 | |
1417 | // 32X ROM (banked) |
5e49c3a8 |
1418 | bank_switch(0); |
b78efee2 |
1419 | |
83ff19ec |
1420 | // SYS regs |
1421 | cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1); |
1422 | cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1); |
1423 | cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1); |
1424 | cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1); |
1425 | |
bcf65fd6 |
1426 | // SH2 maps: A31,A30,A29,CS1,CS0 |
1427 | // all unmapped by default |
e05b81fc |
1428 | for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) { |
bcf65fd6 |
1429 | sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped); |
1430 | sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped); |
e05b81fc |
1431 | } |
1432 | |
1433 | for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) { |
f4bb5d6b |
1434 | sh2_write8_map[i] = sh2_write8_unmapped; |
1435 | sh2_write16_map[i] = sh2_write16_unmapped; |
bcf65fd6 |
1436 | } |
1437 | |
4b315c21 |
1438 | // "purge area" |
e05b81fc |
1439 | for (i = 0x40; i <= 0x5f; i++) { |
1440 | sh2_write8_map[i >> 1] = |
1441 | sh2_write16_map[i >> 1] = sh2_write_ignore; |
4b315c21 |
1442 | } |
1443 | |
bcf65fd6 |
1444 | // CS0 |
1445 | sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0); |
1446 | sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0); |
e05b81fc |
1447 | sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0; |
1448 | sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0; |
bcf65fd6 |
1449 | // CS1 - ROM |
1450 | sh2_read8_map[1].addr = sh2_read8_map[5].addr = |
1451 | sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom); |
1452 | sh2_read8_map[1].mask = sh2_read8_map[5].mask = |
1453 | sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME |
1454 | // CS2 - DRAM - done by Pico32xSwapDRAM() |
1455 | sh2_read8_map[2].mask = sh2_read8_map[6].mask = |
1456 | sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff; |
1457 | // CS3 - SDRAM |
1458 | sh2_read8_map[3].addr = sh2_read8_map[7].addr = |
f4bb5d6b |
1459 | sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram); |
e05b81fc |
1460 | sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram; |
1461 | sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram; |
bcf65fd6 |
1462 | sh2_read8_map[3].mask = sh2_read8_map[7].mask = |
f4bb5d6b |
1463 | sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff; |
bcf65fd6 |
1464 | // SH2 data array |
1465 | sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da); |
1466 | sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da); |
e05b81fc |
1467 | sh2_write8_map[0xc0/2] = sh2_write8_da; |
1468 | sh2_write16_map[0xc0/2] = sh2_write16_da; |
bcf65fd6 |
1469 | // SH2 IO |
1470 | sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8); |
1471 | sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16); |
e05b81fc |
1472 | sh2_write8_map[0xff/2] = sh2_peripheral_write8; |
1473 | sh2_write16_map[0xff/2] = sh2_peripheral_write16; |
bcf65fd6 |
1474 | |
1475 | // map DRAM area, both 68k and SH2 |
1476 | Pico32xSwapDRAM(1); |
1477 | |
1478 | msh2.read8_map = ssh2.read8_map = sh2_read8_map; |
1479 | msh2.read16_map = ssh2.read16_map = sh2_read16_map; |
23686515 |
1480 | msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map; |
1481 | msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map; |
bcf65fd6 |
1482 | |
23686515 |
1483 | sh2_drc_mem_setup(&msh2); |
1484 | sh2_drc_mem_setup(&ssh2); |
be2c4208 |
1485 | } |
1486 | |
27e26273 |
1487 | void Pico32xMemStateLoaded(void) |
b4db550e |
1488 | { |
1489 | bank_switch(Pico32x.regs[4 / 2]); |
1490 | Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS); |
b4db550e |
1491 | memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm)); |
27e26273 |
1492 | Pico32x.dirty_pal = 1; |
51d86e55 |
1493 | |
19886062 |
1494 | Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL); |
1495 | memset(&m68k_poll, 0, sizeof(m68k_poll)); |
1496 | msh2.state = 0; |
1497 | msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0; |
1498 | ssh2.state = 0; |
1499 | ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0; |
1500 | |
b4db550e |
1501 | sh2_drc_flush_all(); |
b4db550e |
1502 | } |
1503 | |
ed4402a7 |
1504 | // vim:shiftwidth=2:ts=2:expandtab |