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[picodrive.git] / Pico / PicoInt.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
6cadc2da 4// (c) Copyright 2006,2007 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "Pico.h"\r
16\r
89fa852d 17//\r
18#define USE_POLL_DETECT\r
19\r
eff55556 20#ifndef PICO_INTERNAL\r
21#define PICO_INTERNAL\r
22#endif\r
23#ifndef PICO_INTERNAL_ASM\r
24#define PICO_INTERNAL_ASM\r
25#endif\r
cc68a136 26\r
70357ce5 27// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 28\r
29#ifdef __cplusplus\r
30extern "C" {\r
31#endif\r
32\r
33\r
34// ----------------------- 68000 CPU -----------------------\r
35#ifdef EMU_C68K\r
36#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 37extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
38#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 39#define SekCyclesLeft \\r
40 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 41#define SekCyclesLeftS68k \\r
3aa1e148 42 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
43#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
7336a99a 44#define SekSetCyclesLeft(c) { \\r
45 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
46}\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
49#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
50#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
cc68a136 51#endif\r
52\r
70357ce5 53#ifdef EMU_F68K\r
54#include "../cpu/fame/fame.h"\r
3aa1e148 55M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
56#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 57#define SekCyclesLeft \\r
58 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
59#define SekCyclesLeftS68k \\r
3aa1e148 60 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
61#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
70357ce5 62#define SekSetCyclesLeft(c) { \\r
63 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
64}\r
3aa1e148 65#define SekPc m68k_get_pc(&PicoCpuFM68k)\r
66#define SekPcS68k m68k_get_pc(&PicoCpuFS68k)\r
70357ce5 67#define SekSetStop(x) { \\r
3aa1e148 68 PicoCpuFM68k.execinfo &= ~M68K_HALTED; \\r
69 if (x) { PicoCpuFM68k.execinfo |= M68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 70}\r
71#define SekSetStopS68k(x) { \\r
3aa1e148 72 PicoCpuFS68k.execinfo &= ~M68K_HALTED; \\r
73 if (x) { PicoCpuFS68k.execinfo |= M68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 74}\r
cc68a136 75#endif\r
76\r
77#ifdef EMU_M68K\r
78#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 79extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 80#ifndef SekCyclesLeft\r
3aa1e148 81#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 82#define SekCyclesLeft \\r
83 (((PicoMCD&1) && (PicoOpt & 0x2000)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 84#define SekCyclesLeftS68k \\r
3aa1e148 85 ((PicoOpt & 0x2000) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
7336a99a 86#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
87#define SekSetCyclesLeft(c) { \\r
88 if ((PicoMCD&1) && (PicoOpt & 0x2000)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
89}\r
3aa1e148 90#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
91#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 92#define SekSetStop(x) { \\r
3aa1e148 93 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
94 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 95}\r
96#define SekSetStopS68k(x) { \\r
3aa1e148 97 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
98 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 99}\r
cc68a136 100#endif\r
101#endif\r
102\r
103extern int SekCycleCnt; // cycles done in this frame\r
104extern int SekCycleAim; // cycle aim\r
105extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
106\r
b8cbd802 107#define SekCyclesReset() { \\r
108 SekCycleCntT+=SekCycleAim; \\r
109 SekCycleCnt-=SekCycleAim; \\r
110 SekCycleAim=0; \\r
111}\r
cc68a136 112#define SekCyclesBurn(c) SekCycleCnt+=c\r
113#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // nuber of cycles done in this frame (can be checked anywhere)\r
114#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
115\r
116#define SekEndRun(after) { \\r
117 SekCycleCnt -= SekCyclesLeft - after; \\r
118 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
119 SekSetCyclesLeft(after); \\r
120}\r
121\r
122extern int SekCycleCntS68k;\r
123extern int SekCycleAimS68k;\r
124\r
bf5fbbb4 125#define SekCyclesResetS68k() { \\r
126 SekCycleCntS68k-=SekCycleAimS68k; \\r
127 SekCycleAimS68k=0; \\r
128}\r
7a1f6e45 129#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 130\r
2d0b15bb 131// debug cyclone\r
132#if defined(EMU_C68K) && defined(EMU_M68K)\r
133#undef SekSetCyclesLeftNoMCD\r
134#undef SekSetCyclesLeft\r
135#undef SekCyclesBurn\r
136#undef SekEndRun\r
137#define SekSetCyclesLeftNoMCD(c)\r
138#define SekSetCyclesLeft(c)\r
2270612a 139#define SekCyclesBurn(c) c\r
2d0b15bb 140#define SekEndRun(c)\r
141#endif\r
cc68a136 142\r
cc68a136 143// ---------------------------------------------------------\r
144\r
70357ce5 145extern int PicoMCD;\r
146\r
cc68a136 147// main oscillator clock which controls timing\r
148#define OSC_NTSC 53693100\r
b8cbd802 149// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
150#define OSC_PAL 53203424\r
cc68a136 151\r
152struct PicoVideo\r
153{\r
154 unsigned char reg[0x20];\r
b8cbd802 155 unsigned int command; // 32-bit Command\r
156 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
157 unsigned char type; // Command type (v/c/vsram read/write)\r
158 unsigned short addr; // Read/Write address\r
159 int status; // Status bits\r
cc68a136 160 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 161 signed char lwrite_cnt; // VDP write count during active display line\r
162 unsigned char pad[0x12];\r
cc68a136 163};\r
164\r
165struct PicoMisc\r
166{\r
167 unsigned char rotate;\r
168 unsigned char z80Run;\r
e5503e2f 169 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
170 short scanline; // 04 0 to 261||311; -1 in fast mode\r
171 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
172 unsigned char hardware; // 07 Hardware value for country\r
173 unsigned char pal; // 08 1=PAL 0=NTSC\r
174 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
175 unsigned short z80_bank68k; // 0a\r
cc68a136 176 unsigned short z80_lastaddr; // this is for Z80 faking\r
177 unsigned char z80_fakeval;\r
178 unsigned char pad0;\r
e5503e2f 179 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 180 unsigned short eeprom_addr; // EEPROM address register\r
181 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
182 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 183 unsigned char prot_bytes[2]; // simple protection faking\r
b8cbd802 184 unsigned short dma_xfers;\r
312e9ce1 185 unsigned char pad[2];\r
186 unsigned int frame_count; // mainly for movies\r
cc68a136 187};\r
188\r
189// some assembly stuff depend on these, do not touch!\r
190struct Pico\r
191{\r
192 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
193 unsigned short vram[0x8000]; // 0x10000\r
194 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
195 unsigned char ioports[0x10];\r
196 unsigned int pad[0x3c]; // unused\r
197 unsigned short cram[0x40]; // 0x22100\r
198 unsigned short vsram[0x40]; // 0x22180\r
199\r
200 unsigned char *rom; // 0x22200\r
201 unsigned int romsize; // 0x22204\r
202\r
203 struct PicoMisc m;\r
204 struct PicoVideo video;\r
205};\r
206\r
207// sram\r
208struct PicoSRAM\r
209{\r
4ff2d527 210 unsigned char *data; // actual data\r
211 unsigned int start; // start address in 68k address space\r
cc68a136 212 unsigned int end;\r
1dceadae 213 unsigned char unused1; // 0c: unused\r
214 unsigned char unused2;\r
cc68a136 215 unsigned char changed;\r
1dceadae 216 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
217 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
218 unsigned char eeprom_bit_cl; // bit number for cl\r
219 unsigned char eeprom_bit_in; // bit number for in\r
220 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 221};\r
222\r
223// MCD\r
224#include "cd/cd_sys.h"\r
225#include "cd/LC89510.h"\r
d1df8786 226#include "cd/gfx_cd.h"\r
cc68a136 227\r
4f265db7 228struct mcd_pcm\r
229{\r
230 unsigned char control; // reg7\r
231 unsigned char enabled; // reg8\r
232 unsigned char cur_ch;\r
233 unsigned char bank;\r
234 int pad1;\r
235\r
4ff2d527 236 struct pcm_chan // 08, size 0x10\r
4f265db7 237 {\r
238 unsigned char regs[8];\r
4ff2d527 239 unsigned int addr; // .08: played sample address\r
4f265db7 240 int pad;\r
241 } ch[8];\r
242};\r
243\r
c459aefd 244struct mcd_misc\r
245{\r
246 unsigned short hint_vector;\r
247 unsigned char busreq;\r
51a902ae 248 unsigned char s68k_pend_ints;\r
89fa852d 249 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
51a902ae 250 unsigned int counter75hz;\r
4ff2d527 251 unsigned short audio_offset; // 0c: for savestates: play pointer offset (0-1023)\r
75736070 252 unsigned char audio_track; // playing audio track # (zero based)\r
6cadc2da 253 char pad1;\r
4ff2d527 254 int timer_int3; // 10\r
4f265db7 255 unsigned int timer_stopwatch;\r
6cadc2da 256 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
257 unsigned char pad2;\r
258 unsigned short pad3;\r
259 int pad[9];\r
c459aefd 260};\r
261\r
cc68a136 262typedef struct\r
263{\r
4ff2d527 264 unsigned char bios[0x20000]; // 000000: 128K\r
265 union { // 020000: 512K\r
fa1e5e29 266 unsigned char prg_ram[0x80000];\r
cc68a136 267 unsigned char prg_ram_b[4][0x20000];\r
268 };\r
4ff2d527 269 union { // 0a0000: 256K\r
fa1e5e29 270 struct {\r
271 unsigned char word_ram2M[0x40000];\r
272 unsigned char unused[0x20000];\r
273 };\r
274 struct {\r
275 unsigned char unused[0x20000];\r
276 unsigned char word_ram1M[2][0x20000];\r
277 };\r
278 };\r
4ff2d527 279 union { // 100000: 64K\r
fa1e5e29 280 unsigned char pcm_ram[0x10000];\r
4f265db7 281 unsigned char pcm_ram_b[0x10][0x1000];\r
282 };\r
4ff2d527 283 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
284 unsigned char bram[0x2000]; // 110200: 8K\r
285 struct mcd_misc m; // 112200: misc\r
286 struct mcd_pcm pcm; // 112240:\r
75736070 287 _scd_toc TOC; // not to be saved\r
cc68a136 288 CDD cdd;\r
289 CDC cdc;\r
290 _scd scd;\r
d1df8786 291 Rot_Comp rot_comp;\r
cc68a136 292} mcd_state;\r
293\r
294#define Pico_mcd ((mcd_state *)Pico.rom)\r
295\r
51a902ae 296// Area.c\r
eff55556 297PICO_INTERNAL int PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
298PICO_INTERNAL int PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
51a902ae 299\r
300// cd/Area.c\r
eff55556 301PICO_INTERNAL int PicoCdSaveState(void *file);\r
302PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 303\r
1dceadae 304// Cart.c\r
305PICO_INTERNAL void PicoCartDetect(void);\r
306\r
cc68a136 307// Draw.c\r
eff55556 308PICO_INTERNAL int PicoLine(int scan);\r
309PICO_INTERNAL void PicoFrameStart(void);\r
cc68a136 310\r
311// Draw2.c\r
eff55556 312PICO_INTERNAL void PicoFrameFull();\r
cc68a136 313\r
314// Memory.c\r
eff55556 315PICO_INTERNAL int PicoInitPc(unsigned int pc);\r
8ab3e3c1 316PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 317PICO_INTERNAL void PicoMemSetup(void);\r
318PICO_INTERNAL_ASM void PicoMemReset(void);\r
e5503e2f 319PICO_INTERNAL int PadRead(int i);\r
eff55556 320PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 321#ifndef _USE_CZ80\r
eff55556 322PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
323PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 324PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
325#else\r
326PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
327#endif\r
cc68a136 328\r
329// cd/Memory.c\r
eff55556 330PICO_INTERNAL void PicoMemSetupCD(void);\r
331PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
332PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 333\r
334// Pico.c\r
335extern struct Pico Pico;\r
336extern struct PicoSRAM SRam;\r
337extern int emustatus;\r
d9153729 338extern int z80startCycle, z80stopCycle; // in 68k cycles\r
eff55556 339PICO_INTERNAL int CheckDMA(void);\r
cc68a136 340\r
341// cd/Pico.c\r
e5f426aa 342PICO_INTERNAL int PicoInitMCD(void);\r
343PICO_INTERNAL void PicoExitMCD(void);\r
eff55556 344PICO_INTERNAL int PicoResetMCD(int hard);\r
345PICO_INTERNAL int PicoFrameMCD(void);\r
cc68a136 346\r
347// Sek.c\r
eff55556 348PICO_INTERNAL int SekInit(void);\r
349PICO_INTERNAL int SekReset(void);\r
350PICO_INTERNAL int SekInterrupt(int irq);\r
3aa1e148 351PICO_INTERNAL void SekState(int *data);\r
eff55556 352PICO_INTERNAL void SekSetRealTAS(int use_real);\r
cc68a136 353\r
354// cd/Sek.c\r
eff55556 355PICO_INTERNAL int SekInitS68k(void);\r
356PICO_INTERNAL int SekResetS68k(void);\r
357PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 358\r
7a93adeb 359// sound/sound.c\r
360extern int PsndLen_exc_cnt;\r
361extern int PsndLen_exc_add;\r
362\r
cc68a136 363// VideoPort.c\r
eff55556 364PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
365PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
cc68a136 366\r
367// Misc.c\r
eff55556 368PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
369PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
370PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
371PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
372PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
373PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
374PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 375\r
fa1e5e29 376// cd/Misc.c\r
eff55556 377PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
378PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
379\r
380// cd/buffering.c\r
381PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
382\r
383// sound/sound.c\r
384PICO_INTERNAL void sound_reset(void);\r
385PICO_INTERNAL void sound_timers_and_dac(int raster);\r
386PICO_INTERNAL int sound_render(int offset, int length);\r
387PICO_INTERNAL void sound_clear(void);\r
388// z80 functionality wrappers\r
389PICO_INTERNAL void z80_init(void);\r
390PICO_INTERNAL void z80_resetCycles(void);\r
391PICO_INTERNAL void z80_int(void);\r
392PICO_INTERNAL int z80_run(int cycles);\r
393PICO_INTERNAL void z80_pack(unsigned char *data);\r
394PICO_INTERNAL void z80_unpack(unsigned char *data);\r
395PICO_INTERNAL void z80_reset(void);\r
396PICO_INTERNAL void z80_exit(void);\r
fa1e5e29 397\r
cc68a136 398\r
399#ifdef __cplusplus\r
400} // End of extern "C"\r
401#endif\r
eff55556 402\r
b8cbd802 403// emulation event logging\r
404#ifndef EL_LOGMASK\r
405#define EL_LOGMASK 0\r
406#endif\r
407\r
408#define EL_HVCNT 0x0001 /* hv counter reads */\r
409#define EL_SR 0x0002 /* SR reads */\r
410#define EL_INTS 0x0004 /* ints and acks */\r
411#define EL_YM2612R 0x0008 /* 68k ym2612 reads */\r
412#define EL_INTSW 0x0010 /* log irq switching on/off */\r
413#define EL_ASVDP 0x0020 /* VDP accesses during active scan */\r
414#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
5f20bb80 415#define EL_BUSREQ 0x0080 /* z80 busreq r/w or reset w */\r
b8cbd802 416#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
1dceadae 417#define EL_SRAMIO 0x0200 /* sram i/o */\r
418#define EL_EEPROM 0x0400 /* eeprom debug */\r
419#define EL_UIO 0x0800 /* unmapped i/o */\r
5f20bb80 420#define EL_IO 0x1000 /* all i/o (TODO) */\r
b8cbd802 421\r
422#define EL_STATUS 0x4000 /* status messages */\r
423#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
424\r
425#if EL_LOGMASK\r
426#define elprintf(w,f,...) \\r
427{ \\r
428 if ((w) & EL_LOGMASK) \\r
429 printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
430}\r
431#else\r
432#define elprintf(w,f,...)\r
433#endif\r
434\r
eff55556 435#endif // PICO_INTERNAL_INCLUDED\r
436\r
fast MegaDrive/MegaCD/32X emulator