83ff19ec |
1 | /* |
cff531af |
2 | * PicoDrive |
65514d85 |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | * |
83ff19ec |
8 | * Register map: |
9 | * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm |
10 | * a15102 ........ ......SM ? 4002 // intS intM |
11 | * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint |
7eaa3812 |
12 | * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb] |
83ff19ec |
13 | * a15108 (32bit DREQ src) 4008 |
14 | * a1510c (32bit DREQ dst) 400c |
15 | * a15110 llllllll llllll00 4010 // DREQ Len |
16 | * a15112 (16bit FIFO reg) 4012 |
7eaa3812 |
17 | * a15114 0 (16bit VRES clr) 4014 |
18 | * a15116 0 (16bit Vint clr) 4016 |
19 | * a15118 0 (16bit Hint clr) 4018 |
20 | * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm |
21 | * a1511c 0 (16bit PWM clr) 401c |
22 | * a1511e 0 ? 401e |
83ff19ec |
23 | * a15120 (16 bytes comm) 2020 |
24 | * a15130 (PWM) 2030 |
65514d85 |
25 | * |
26 | * SH2 addr lines: |
27 | * iii. .cc. ..xx * // Internal, Cs, x |
28 | * |
29 | * sh2 map, wait/bus cycles (from docs): |
30 | * r w |
31 | * rom 0000000-0003fff 1 - |
32 | * sys reg 0004000-00040ff 1 1 |
33 | * vdp reg 0004100-00041ff 5 5 |
34 | * vdp pal 0004200-00043ff 5 5 |
8a847c12 |
35 | * cart 2000000-23fffff 6-15 |
65514d85 |
36 | * dram/fb 4000000-401ffff 5-12 1-3 |
37 | * fb ovr 4020000-403ffff |
38 | * sdram 6000000-603ffff 12 2 (cycles) |
39 | * d.a. c0000000-? |
83ff19ec |
40 | */ |
be2c4208 |
41 | #include "../pico_int.h" |
42 | #include "../memory.h" |
f4bb5d6b |
43 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
44 | |
45 | static const char str_mars[] = "MARS"; |
46 | |
83ff19ec |
47 | void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s; |
974fdb5b |
48 | struct Pico32xMem *Pico32xMem; |
49 | |
8b9dbcde |
50 | static void bank_switch_rom_68k(int b); |
5e49c3a8 |
51 | |
7eaa3812 |
52 | // addressing byte in 16bit reg |
53 | #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1] |
54 | |
266c6afa |
55 | // poll detection |
19886062 |
56 | #define POLL_THRESHOLD 3 |
4ea707e1 |
57 | |
19886062 |
58 | static struct { |
59 | u32 addr, cycles; |
60 | int cnt; |
61 | } m68k_poll; |
266c6afa |
62 | |
19886062 |
63 | static int m68k_poll_detect(u32 a, u32 cycles, u32 flags) |
266c6afa |
64 | { |
19886062 |
65 | int ret = 0; |
66 | |
67 | if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2 |
ecc8036e |
68 | && cycles - m68k_poll.cycles <= 64 && !SekNotPolling) |
19886062 |
69 | { |
70 | if (m68k_poll.cnt++ > POLL_THRESHOLD) { |
71 | if (!(Pico32x.emu_flags & flags)) { |
72 | elprintf(EL_32X, "m68k poll addr %08x, cyc %u", |
73 | a, cycles - m68k_poll.cycles); |
266c6afa |
74 | ret = 1; |
75 | } |
19886062 |
76 | Pico32x.emu_flags |= flags; |
266c6afa |
77 | } |
78 | } |
c987bb5c |
79 | else { |
19886062 |
80 | m68k_poll.cnt = 0; |
81 | m68k_poll.addr = a; |
ecc8036e |
82 | SekNotPolling = 0; |
c987bb5c |
83 | } |
19886062 |
84 | m68k_poll.cycles = cycles; |
266c6afa |
85 | |
86 | return ret; |
87 | } |
88 | |
19886062 |
89 | void p32x_m68k_poll_event(u32 flags) |
90 | { |
91 | if (Pico32x.emu_flags & flags) { |
92 | elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags, |
93 | Pico32x.emu_flags & ~flags); |
94 | Pico32x.emu_flags &= ~flags; |
95 | SekSetStop(0); |
96 | } |
97 | m68k_poll.addr = m68k_poll.cnt = 0; |
98 | } |
99 | |
4a1fb183 |
100 | static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt) |
266c6afa |
101 | { |
19886062 |
102 | int cycles_left = sh2_cycles_left(sh2); |
103 | |
104 | if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) { |
4a1fb183 |
105 | if (sh2->poll_cnt++ > maxcnt) { |
19886062 |
106 | if (!(sh2->state & flags)) |
f8675e28 |
107 | elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", |
19886062 |
108 | sh2->state, sh2->state | flags); |
109 | |
110 | sh2->state |= flags; |
111 | sh2_end_run(sh2, 1); |
112 | pevt_log_sh2(sh2, EVT_POLL_START); |
113 | return; |
114 | } |
115 | } |
be20816c |
116 | else |
19886062 |
117 | sh2->poll_cnt = 0; |
118 | sh2->poll_addr = a; |
119 | sh2->poll_cycles = cycles_left; |
120 | } |
121 | |
122 | void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles) |
123 | { |
124 | if (sh2->state & flags) { |
f8675e28 |
125 | elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state, |
126 | sh2->state & ~flags); |
19886062 |
127 | |
128 | if (sh2->m68krcycles_done < m68k_cycles) |
129 | sh2->m68krcycles_done = m68k_cycles; |
130 | |
131 | pevt_log_sh2_o(sh2, EVT_POLL_END); |
be20816c |
132 | } |
19886062 |
133 | |
134 | sh2->state &= ~flags; |
135 | sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0; |
266c6afa |
136 | } |
137 | |
19886062 |
138 | static void sh2s_sync_on_read(SH2 *sh2) |
4ea707e1 |
139 | { |
19886062 |
140 | int cycles; |
141 | if (sh2->poll_cnt != 0) |
142 | return; |
143 | |
144 | cycles = sh2_cycles_done(sh2); |
145 | if (cycles > 600) |
146 | p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3); |
4ea707e1 |
147 | } |
148 | |
974fdb5b |
149 | // SH2 faking |
b78efee2 |
150 | //#define FAKE_SH2 |
acd35d4c |
151 | #ifdef FAKE_SH2 |
27e26273 |
152 | static int p32x_csum_faked; |
974fdb5b |
153 | static const u16 comm_fakevals[] = { |
154 | 0x4d5f, 0x4f4b, // M_OK |
155 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
156 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
157 | 0x5331, 0x4d31, // Darxide |
158 | 0x5332, 0x4d32, |
159 | 0x5333, 0x4d33, |
160 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
161 | 0x0002, // Mortal Kombat |
acd35d4c |
162 | // 0, // pad |
be2c4208 |
163 | }; |
acd35d4c |
164 | |
165 | static u32 sh2_comm_faker(u32 a) |
166 | { |
167 | static int f = 0; |
168 | if (a == 0x28 && !p32x_csum_faked) { |
169 | p32x_csum_faked = 1; |
170 | return *(unsigned short *)(Pico.rom + 0x18e); |
171 | } |
172 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
173 | f = 0; |
174 | return comm_fakevals[f++]; |
175 | } |
176 | #endif |
be2c4208 |
177 | |
4ea707e1 |
178 | // ------------------------------------------------------------------ |
b78efee2 |
179 | // 68k regs |
4ea707e1 |
180 | |
be2c4208 |
181 | static u32 p32x_reg_read16(u32 a) |
182 | { |
183 | a &= 0x3e; |
184 | |
3cf9570b |
185 | #if 0 |
974fdb5b |
186 | if ((a & 0x30) == 0x20) |
acd35d4c |
187 | return sh2_comm_faker(a); |
266c6afa |
188 | #else |
5fadfb1c |
189 | if ((a & 0x30) == 0x20) { |
ae214f1c |
190 | unsigned int cycles = SekCyclesDone(); |
a8fd6e37 |
191 | int comreg = 1 << (a & 0x0f) / 2; |
192 | |
419973a6 |
193 | if (cycles - msh2.m68krcycles_done > 244 |
31fbc691 |
194 | || (Pico32x.comm_dirty & comreg)) |
a8fd6e37 |
195 | p32x_sync_sh2s(cycles); |
419973a6 |
196 | |
31fbc691 |
197 | if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) { |
5fadfb1c |
198 | SekSetStop(1); |
3e5b912c |
199 | SekEndRun(16); |
5fadfb1c |
200 | } |
a8fd6e37 |
201 | goto out; |
266c6afa |
202 | } |
acd35d4c |
203 | #endif |
87accdf7 |
204 | |
a8fd6e37 |
205 | if (a == 2) { // INTM, INTS |
ae214f1c |
206 | unsigned int cycles = SekCyclesDone(); |
a8fd6e37 |
207 | if (cycles - msh2.m68krcycles_done > 64) |
208 | p32x_sync_sh2s(cycles); |
9e1fa0a6 |
209 | goto out; |
a8fd6e37 |
210 | } |
211 | |
db1d3564 |
212 | if ((a & 0x30) == 0x30) |
ae214f1c |
213 | return p32x_pwm_read16(a, NULL, SekCyclesDone()); |
974fdb5b |
214 | |
a8fd6e37 |
215 | out: |
be2c4208 |
216 | return Pico32x.regs[a / 2]; |
217 | } |
218 | |
7eaa3812 |
219 | static void dreq0_write(u16 *r, u32 d) |
220 | { |
221 | if (!(r[6 / 2] & P32XS_68S)) { |
222 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
223 | return; // ignored - tested |
224 | } |
225 | if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) { |
226 | Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d; |
227 | if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN) |
228 | r[6 / 2] |= P32XS_FULL; |
229 | // tested: len register decrements and 68S clears |
230 | // even if SH2s/DMAC aren't active.. |
231 | r[0x10 / 2]--; |
232 | if (r[0x10 / 2] == 0) |
233 | r[6 / 2] &= ~P32XS_68S; |
234 | |
235 | if ((Pico32x.dmac0_fifo_ptr & 3) == 0) { |
ae214f1c |
236 | p32x_sync_sh2s(SekCyclesDone()); |
7eaa3812 |
237 | p32x_dreq0_trigger(); |
238 | } |
239 | } |
240 | else |
241 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!"); |
242 | } |
243 | |
244 | // writable bits tested |
be2c4208 |
245 | static void p32x_reg_write8(u32 a, u32 d) |
246 | { |
acd35d4c |
247 | u16 *r = Pico32x.regs; |
be2c4208 |
248 | a &= 0x3f; |
249 | |
97d3f47f |
250 | // for things like bset on comm port |
251 | m68k_poll.cnt = 0; |
252 | |
acd35d4c |
253 | switch (a) { |
7eaa3812 |
254 | case 0x00: // adapter ctl: FM writable |
255 | REG8IN16(r, 0x00) = d & 0x80; |
83ff19ec |
256 | return; |
7eaa3812 |
257 | case 0x01: // adapter ctl: RES and ADEN writable |
83ff19ec |
258 | if ((d ^ r[0]) & d & P32XS_nRES) |
259 | p32x_reset_sh2s(); |
7eaa3812 |
260 | REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN); |
261 | REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN); |
262 | return; |
263 | case 0x02: // ignored, always 0 |
1b3f5844 |
264 | return; |
7eaa3812 |
265 | case 0x03: // irq ctl |
9e1fa0a6 |
266 | if ((d ^ r[0x02 / 2]) & 3) { |
ae214f1c |
267 | int cycles = SekCyclesDone(); |
9e1fa0a6 |
268 | p32x_sync_sh2s(cycles); |
269 | r[0x02 / 2] = d & 3; |
270 | p32x_update_cmd_irq(NULL, cycles); |
b78efee2 |
271 | } |
1b3f5844 |
272 | return; |
7eaa3812 |
273 | case 0x04: // ignored, always 0 |
274 | return; |
275 | case 0x05: // bank |
276 | d &= 3; |
277 | if (r[0x04 / 2] != d) { |
278 | r[0x04 / 2] = d; |
8b9dbcde |
279 | bank_switch_rom_68k(d); |
acd35d4c |
280 | } |
1b3f5844 |
281 | return; |
7eaa3812 |
282 | case 0x06: // ignored, always 0 |
283 | return; |
284 | case 0x07: // DREQ ctl |
285 | REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV); |
286 | if (!(d & P32XS_68S)) { |
287 | Pico32x.dmac0_fifo_ptr = 0; |
288 | REG8IN16(r, 0x07) &= ~P32XS_FULL; |
289 | } |
290 | REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV); |
291 | return; |
292 | case 0x08: // ignored, always 0 |
293 | return; |
294 | case 0x09: // DREQ src |
295 | REG8IN16(r, 0x09) = d; |
296 | return; |
297 | case 0x0a: |
298 | REG8IN16(r, 0x0a) = d; |
299 | return; |
300 | case 0x0b: |
301 | REG8IN16(r, 0x0b) = d & 0xfe; |
302 | return; |
303 | case 0x0c: // ignored, always 0 |
304 | return; |
305 | case 0x0d: // DREQ dest |
306 | case 0x0e: |
307 | case 0x0f: |
308 | case 0x10: // DREQ len |
309 | REG8IN16(r, a) = d; |
310 | return; |
311 | case 0x11: |
312 | REG8IN16(r, a) = d & 0xfc; |
313 | return; |
314 | // DREQ FIFO - writes to odd addr go to fifo |
315 | // do writes to even work? Reads return 0 |
316 | case 0x12: |
317 | REG8IN16(r, a) = d; |
318 | return; |
319 | case 0x13: |
320 | d = (REG8IN16(r, 0x12) << 8) | (d & 0xff); |
321 | REG8IN16(r, 0x12) = 0; |
322 | dreq0_write(r, d); |
323 | return; |
324 | case 0x14: // ignored, always 0 |
325 | case 0x15: |
326 | case 0x16: |
327 | case 0x17: |
328 | case 0x18: |
329 | case 0x19: |
330 | return; |
331 | case 0x1a: // what's this? |
332 | elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d); |
333 | REG8IN16(r, a) = d & 0x01; |
1b3f5844 |
334 | return; |
87accdf7 |
335 | case 0x1b: // TV |
7eaa3812 |
336 | REG8IN16(r, a) = d & 0x01; |
337 | return; |
338 | case 0x1c: // ignored, always 0 |
339 | case 0x1d: |
340 | case 0x1e: |
341 | case 0x1f: |
342 | case 0x30: |
343 | return; |
344 | case 0x31: // PWM control |
345 | REG8IN16(r, a) &= ~0x0f; |
346 | REG8IN16(r, a) |= d & 0x0f; |
77e58d93 |
347 | d = r[0x30 / 2]; |
7eaa3812 |
348 | goto pwm_write; |
349 | case 0x32: // PWM cycle |
350 | REG8IN16(r, a) = d & 0x0f; |
77e58d93 |
351 | d = r[0x32 / 2]; |
7eaa3812 |
352 | goto pwm_write; |
353 | case 0x33: |
354 | REG8IN16(r, a) = d; |
77e58d93 |
355 | d = r[0x32 / 2]; |
7eaa3812 |
356 | goto pwm_write; |
357 | // PWM pulse regs.. Only writes to odd address send a value |
358 | // to FIFO; reads are 0 (except status bits) |
359 | case 0x34: |
360 | case 0x36: |
361 | case 0x38: |
362 | REG8IN16(r, a) = d; |
363 | return; |
364 | case 0x35: |
365 | case 0x37: |
366 | case 0x39: |
77e58d93 |
367 | d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff); |
368 | REG8IN16(r, a ^ 1) = 0; |
7eaa3812 |
369 | goto pwm_write; |
370 | case 0x3a: // ignored, always 0 |
371 | case 0x3b: |
372 | case 0x3c: |
373 | case 0x3d: |
374 | case 0x3e: |
375 | case 0x3f: |
376 | return; |
377 | pwm_write: |
ae214f1c |
378 | p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone()); |
1b3f5844 |
379 | return; |
380 | } |
381 | |
382 | if ((a & 0x30) == 0x20) { |
ae214f1c |
383 | int cycles = SekCyclesDone(); |
a8fd6e37 |
384 | int comreg; |
385 | |
7eaa3812 |
386 | if (REG8IN16(r, a) == d) |
a8fd6e37 |
387 | return; |
19886062 |
388 | |
31fbc691 |
389 | p32x_sync_sh2s(cycles); |
a8fd6e37 |
390 | |
7eaa3812 |
391 | REG8IN16(r, a) = d; |
19886062 |
392 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
393 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
31fbc691 |
394 | comreg = 1 << (a & 0x0f) / 2; |
395 | Pico32x.comm_dirty |= comreg; |
a8fd6e37 |
396 | |
397 | if (cycles - (int)msh2.m68krcycles_done > 120) |
398 | p32x_sync_sh2s(cycles); |
1b3f5844 |
399 | return; |
5e49c3a8 |
400 | } |
401 | } |
402 | |
403 | static void p32x_reg_write16(u32 a, u32 d) |
404 | { |
acd35d4c |
405 | u16 *r = Pico32x.regs; |
406 | a &= 0x3e; |
407 | |
97d3f47f |
408 | // for things like bset on comm port |
409 | m68k_poll.cnt = 0; |
410 | |
acd35d4c |
411 | switch (a) { |
4ea707e1 |
412 | case 0x00: // adapter ctl |
83ff19ec |
413 | if ((d ^ r[0]) & d & P32XS_nRES) |
414 | p32x_reset_sh2s(); |
7eaa3812 |
415 | r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN); |
416 | r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN); |
417 | return; |
418 | case 0x08: // DREQ src |
419 | r[a / 2] = d & 0xff; |
420 | return; |
421 | case 0x0a: |
422 | r[a / 2] = d & ~1; |
423 | return; |
424 | case 0x0c: // DREQ dest |
425 | r[a / 2] = d & 0xff; |
426 | return; |
427 | case 0x0e: |
428 | r[a / 2] = d; |
acd35d4c |
429 | return; |
4ea707e1 |
430 | case 0x10: // DREQ len |
431 | r[a / 2] = d & ~3; |
432 | return; |
433 | case 0x12: // FIFO reg |
7eaa3812 |
434 | dreq0_write(r, d); |
435 | return; |
436 | case 0x1a: // TV + mystery bit |
437 | r[a / 2] = d & 0x0101; |
438 | return; |
77e58d93 |
439 | case 0x30: // PWM control |
440 | d = (r[a / 2] & ~0x0f) | (d & 0x0f); |
441 | r[a / 2] = d; |
ae214f1c |
442 | p32x_pwm_write16(a, d, NULL, SekCyclesDone()); |
77e58d93 |
443 | return; |
acd35d4c |
444 | } |
445 | |
4ea707e1 |
446 | // comm port |
7eaa3812 |
447 | if ((a & 0x30) == 0x20) { |
ae214f1c |
448 | int cycles = SekCyclesDone(); |
a8fd6e37 |
449 | int comreg; |
450 | |
31fbc691 |
451 | p32x_sync_sh2s(cycles); |
a8fd6e37 |
452 | |
acd35d4c |
453 | r[a / 2] = d; |
19886062 |
454 | p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); |
455 | p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); |
31fbc691 |
456 | comreg = 1 << (a & 0x0f) / 2; |
457 | Pico32x.comm_dirty |= comreg; |
acd35d4c |
458 | return; |
459 | } |
db1d3564 |
460 | // PWM |
461 | else if ((a & 0x30) == 0x30) { |
ae214f1c |
462 | p32x_pwm_write16(a, d, NULL, SekCyclesDone()); |
db1d3564 |
463 | return; |
464 | } |
acd35d4c |
465 | |
5e49c3a8 |
466 | p32x_reg_write8(a + 1, d); |
be2c4208 |
467 | } |
468 | |
4ea707e1 |
469 | // ------------------------------------------------------------------ |
be2c4208 |
470 | // VDP regs |
471 | static u32 p32x_vdp_read16(u32 a) |
472 | { |
4a1fb183 |
473 | u32 d; |
be2c4208 |
474 | a &= 0x0e; |
475 | |
4a1fb183 |
476 | d = Pico32x.vdp_regs[a / 2]; |
477 | if (a == 0x0a) { |
478 | // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0, |
479 | // most often at 0xb1-0xb5, even during vblank, |
480 | // what's the deal with that? |
481 | // we'll just fake it along with hblank for now |
482 | Pico32x.vdp_fbcr_fake++; |
483 | if (Pico32x.vdp_fbcr_fake & 4) |
484 | d |= P32XV_HBLK; |
485 | if ((Pico32x.vdp_fbcr_fake & 7) == 0) |
486 | d |= P32XV_nFEN; |
487 | } |
488 | return d; |
be2c4208 |
489 | } |
490 | |
be2c4208 |
491 | static void p32x_vdp_write8(u32 a, u32 d) |
492 | { |
974fdb5b |
493 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
494 | a &= 0x0f; |
495 | |
974fdb5b |
496 | // TODO: verify what's writeable |
be2c4208 |
497 | switch (a) { |
974fdb5b |
498 | case 0x01: |
5e49c3a8 |
499 | // priority inversion is handled in palette |
500 | if ((r[0] ^ d) & P32XV_PRI) |
501 | Pico32x.dirty_pal = 1; |
974fdb5b |
502 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
503 | break; |
e51e5983 |
504 | case 0x03: // shift (for pp mode) |
505 | r[2 / 2] = d & 1; |
506 | break; |
be20816c |
507 | case 0x05: // fill len |
508 | r[4 / 2] = d & 0xff; |
974fdb5b |
509 | break; |
be2c4208 |
510 | case 0x0b: |
974fdb5b |
511 | d &= 1; |
512 | Pico32x.pending_fb = d; |
513 | // if we are blanking and FS bit is changing |
4ea707e1 |
514 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
b4db550e |
515 | r[0x0a/2] ^= P32XV_FS; |
5609d343 |
516 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
517 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
518 | } |
519 | break; |
520 | } |
521 | } |
522 | |
19886062 |
523 | static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2) |
974fdb5b |
524 | { |
be20816c |
525 | a &= 0x0e; |
526 | if (a == 6) { // fill start |
527 | Pico32x.vdp_regs[6 / 2] = d; |
528 | return; |
529 | } |
530 | if (a == 8) { // fill data |
531 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
532 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
a8fd6e37 |
533 | int len1 = len; |
be20816c |
534 | a = Pico32x.vdp_regs[6 / 2]; |
a8fd6e37 |
535 | while (len1--) { |
be20816c |
536 | dram[a] = d; |
537 | a = (a & 0xff00) | ((a + 1) & 0xff); |
538 | } |
a8fd6e37 |
539 | Pico32x.vdp_regs[0x06 / 2] = a; |
540 | Pico32x.vdp_regs[0x08 / 2] = d; |
19886062 |
541 | if (sh2 != NULL && len > 4) { |
a8fd6e37 |
542 | Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN; |
19886062 |
543 | // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles? |
544 | p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len); |
a8fd6e37 |
545 | } |
be20816c |
546 | return; |
547 | } |
548 | |
974fdb5b |
549 | p32x_vdp_write8(a | 1, d); |
550 | } |
551 | |
4ea707e1 |
552 | // ------------------------------------------------------------------ |
acd35d4c |
553 | // SH2 regs |
b78efee2 |
554 | |
f81107f5 |
555 | static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2) |
acd35d4c |
556 | { |
4ea707e1 |
557 | u16 *r = Pico32x.regs; |
eb35ce15 |
558 | a &= 0x3e; |
266c6afa |
559 | |
4ea707e1 |
560 | switch (a) { |
561 | case 0x00: // adapter/irq ctl |
f81107f5 |
562 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] |
563 | | Pico32x.sh2irq_mask[sh2->is_slave]; |
c987bb5c |
564 | case 0x04: // H count (often as comm too) |
4a1fb183 |
565 | sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3); |
f81107f5 |
566 | sh2s_sync_on_read(sh2); |
87accdf7 |
567 | return Pico32x.sh2_regs[4 / 2]; |
7eaa3812 |
568 | case 0x06: |
569 | return (r[a / 2] & ~P32XS_FULL) | 0x4000; |
570 | case 0x08: // DREQ src |
571 | case 0x0a: |
572 | case 0x0c: // DREQ dst |
573 | case 0x0e: |
4ea707e1 |
574 | case 0x10: // DREQ len |
575 | return r[a / 2]; |
7eaa3812 |
576 | case 0x12: // DREQ FIFO - does this work on hw? |
577 | if (Pico32x.dmac0_fifo_ptr > 0) { |
578 | Pico32x.dmac0_fifo_ptr--; |
579 | r[a / 2] = Pico32x.dmac_fifo[0]; |
580 | memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1], |
581 | Pico32x.dmac0_fifo_ptr * 2); |
582 | } |
583 | return r[a / 2]; |
584 | case 0x14: |
585 | case 0x16: |
586 | case 0x18: |
587 | case 0x1a: |
588 | case 0x1c: |
589 | return 0; // ? |
acd35d4c |
590 | } |
4ea707e1 |
591 | |
db1d3564 |
592 | // comm port |
593 | if ((a & 0x30) == 0x20) { |
31fbc691 |
594 | sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3); |
f81107f5 |
595 | sh2s_sync_on_read(sh2); |
db1d3564 |
596 | return r[a / 2]; |
597 | } |
7eaa3812 |
598 | if ((a & 0x30) == 0x30) |
f81107f5 |
599 | return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2)); |
acd35d4c |
600 | |
7eaa3812 |
601 | elprintf_sh2(sh2, EL_32X|EL_ANOMALY, |
77e58d93 |
602 | "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2)); |
acd35d4c |
603 | return 0; |
604 | } |
605 | |
f81107f5 |
606 | static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
607 | { |
77e58d93 |
608 | u16 *r = Pico32x.regs; |
9e1fa0a6 |
609 | u32 old; |
19886062 |
610 | |
eb35ce15 |
611 | a &= 0x3f; |
f81107f5 |
612 | sh2->poll_addr = 0; |
19886062 |
613 | |
87accdf7 |
614 | switch (a) { |
77e58d93 |
615 | case 0x00: // FM |
616 | r[0] &= ~P32XS_FM; |
617 | r[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
618 | return; |
77e58d93 |
619 | case 0x01: // HEN/irq masks |
9e1fa0a6 |
620 | old = Pico32x.sh2irq_mask[sh2->is_slave]; |
621 | if ((d ^ old) & 1) |
622 | p32x_pwm_sync_to_sh2(sh2); |
623 | |
5ac99d9a |
624 | Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f; |
87accdf7 |
625 | Pico32x.sh2_regs[0] &= ~0x80; |
626 | Pico32x.sh2_regs[0] |= d & 0x80; |
9e1fa0a6 |
627 | |
628 | if ((d ^ old) & 1) |
f81107f5 |
629 | p32x_pwm_schedule_sh2(sh2); |
9e1fa0a6 |
630 | if ((old ^ d) & 2) |
631 | p32x_update_cmd_irq(sh2, 0); |
632 | if ((old ^ d) & 4) |
5ac99d9a |
633 | p32x_schedule_hint(sh2, 0); |
1b3f5844 |
634 | return; |
77e58d93 |
635 | case 0x04: // ignored? |
636 | return; |
637 | case 0x05: // H count |
19886062 |
638 | d &= 0xff; |
639 | if (Pico32x.sh2_regs[4 / 2] != d) { |
640 | Pico32x.sh2_regs[4 / 2] = d; |
f81107f5 |
641 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
642 | sh2_cycles_done_m68k(sh2)); |
643 | sh2_end_run(sh2, 4); |
19886062 |
644 | } |
1b3f5844 |
645 | return; |
77e58d93 |
646 | case 0x30: |
647 | REG8IN16(r, a) = d & 0x0f; |
648 | d = r[0x30 / 2]; |
649 | goto pwm_write; |
650 | case 0x31: // PWM control |
651 | REG8IN16(r, a) = d & 0x8f; |
652 | d = r[0x30 / 2]; |
653 | goto pwm_write; |
654 | case 0x32: // PWM cycle |
655 | REG8IN16(r, a) = d & 0x0f; |
656 | d = r[0x32 / 2]; |
657 | goto pwm_write; |
658 | case 0x33: |
659 | REG8IN16(r, a) = d; |
660 | d = r[0x32 / 2]; |
661 | goto pwm_write; |
662 | // PWM pulse regs.. Only writes to odd address send a value |
663 | // to FIFO; reads are 0 (except status bits) |
664 | case 0x34: |
665 | case 0x36: |
666 | case 0x38: |
667 | REG8IN16(r, a) = d; |
668 | return; |
669 | case 0x35: |
670 | case 0x37: |
671 | case 0x39: |
672 | d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff); |
673 | REG8IN16(r, a ^ 1) = 0; |
674 | goto pwm_write; |
675 | case 0x3a: // ignored, always 0? |
676 | case 0x3b: |
677 | case 0x3c: |
678 | case 0x3d: |
679 | case 0x3e: |
680 | case 0x3f: |
681 | return; |
682 | pwm_write: |
683 | p32x_pwm_write16(a & ~1, d, sh2, 0); |
684 | return; |
1b3f5844 |
685 | } |
686 | |
687 | if ((a & 0x30) == 0x20) { |
a8fd6e37 |
688 | int comreg; |
77e58d93 |
689 | if (REG8IN16(r, a) == d) |
a8fd6e37 |
690 | return; |
691 | |
77e58d93 |
692 | REG8IN16(r, a) = d; |
19886062 |
693 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
f81107f5 |
694 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
695 | sh2_cycles_done_m68k(sh2)); |
a8fd6e37 |
696 | comreg = 1 << (a & 0x0f) / 2; |
31fbc691 |
697 | Pico32x.comm_dirty |= comreg; |
1b3f5844 |
698 | return; |
4ea707e1 |
699 | } |
77e58d93 |
700 | |
701 | elprintf(EL_32X|EL_ANOMALY, |
702 | "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2)); |
acd35d4c |
703 | } |
704 | |
f81107f5 |
705 | static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
706 | { |
eb35ce15 |
707 | a &= 0x3e; |
acd35d4c |
708 | |
f81107f5 |
709 | sh2->poll_addr = 0; |
19886062 |
710 | |
db1d3564 |
711 | // comm |
a8fd6e37 |
712 | if ((a & 0x30) == 0x20) { |
713 | int comreg; |
714 | if (Pico32x.regs[a / 2] == d) |
715 | return; |
716 | |
b78efee2 |
717 | Pico32x.regs[a / 2] = d; |
19886062 |
718 | p32x_m68k_poll_event(P32XF_68KCPOLL); |
f81107f5 |
719 | p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, |
720 | sh2_cycles_done_m68k(sh2)); |
a8fd6e37 |
721 | comreg = 1 << (a & 0x0f) / 2; |
31fbc691 |
722 | Pico32x.comm_dirty |= comreg; |
acd35d4c |
723 | return; |
724 | } |
db1d3564 |
725 | // PWM |
726 | else if ((a & 0x30) == 0x30) { |
f81107f5 |
727 | p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2)); |
db1d3564 |
728 | return; |
729 | } |
acd35d4c |
730 | |
4ea707e1 |
731 | switch (a) { |
87accdf7 |
732 | case 0: // FM |
733 | Pico32x.regs[0] &= ~P32XS_FM; |
734 | Pico32x.regs[0] |= d & P32XS_FM; |
735 | break; |
9e1fa0a6 |
736 | case 0x14: |
737 | Pico32x.sh2irqs &= ~P32XI_VRES; |
738 | goto irls; |
739 | case 0x16: |
740 | Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT; |
741 | goto irls; |
742 | case 0x18: |
743 | Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT; |
744 | goto irls; |
745 | case 0x1a: |
746 | Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave); |
747 | p32x_update_cmd_irq(sh2, 0); |
748 | return; |
be20816c |
749 | case 0x1c: |
9e1fa0a6 |
750 | p32x_pwm_sync_to_sh2(sh2); |
751 | Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM; |
f81107f5 |
752 | p32x_pwm_schedule_sh2(sh2); |
be20816c |
753 | goto irls; |
4ea707e1 |
754 | } |
755 | |
f81107f5 |
756 | p32x_sh2reg_write8(a | 1, d, sh2); |
4ea707e1 |
757 | return; |
758 | |
759 | irls: |
f81107f5 |
760 | p32x_update_irls(sh2, 0); |
4ea707e1 |
761 | } |
762 | |
4ea707e1 |
763 | // ------------------------------------------------------------------ |
34280f9b |
764 | // 32x 68k handlers |
83ff19ec |
765 | |
766 | // after ADEN |
767 | static u32 PicoRead8_32x_on(u32 a) |
be2c4208 |
768 | { |
769 | u32 d = 0; |
770 | if ((a & 0xffc0) == 0x5100) { // a15100 |
771 | d = p32x_reg_read16(a); |
772 | goto out_16to8; |
773 | } |
774 | |
fa8fb754 |
775 | if ((a & 0xfc00) != 0x5000) { |
93f9619e |
776 | if (PicoIn.AHW & PAHW_MCD) |
fa8fb754 |
777 | return PicoRead8_mcd_io(a); |
778 | else |
779 | return PicoRead8_io(a); |
780 | } |
974fdb5b |
781 | |
782 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
783 | d = p32x_vdp_read16(a); |
784 | goto out_16to8; |
785 | } |
786 | |
974fdb5b |
787 | if ((a & 0xfe00) == 0x5200) { // a15200 |
788 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
789 | goto out_16to8; |
790 | } |
791 | |
be2c4208 |
792 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
793 | d = str_mars[a & 3]; |
794 | goto out; |
795 | } |
796 | |
797 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
798 | return d; |
799 | |
800 | out_16to8: |
801 | if (a & 1) |
802 | d &= 0xff; |
803 | else |
804 | d >>= 8; |
805 | |
806 | out: |
807 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
808 | return d; |
809 | } |
810 | |
83ff19ec |
811 | static u32 PicoRead16_32x_on(u32 a) |
be2c4208 |
812 | { |
813 | u32 d = 0; |
814 | if ((a & 0xffc0) == 0x5100) { // a15100 |
815 | d = p32x_reg_read16(a); |
816 | goto out; |
817 | } |
818 | |
fa8fb754 |
819 | if ((a & 0xfc00) != 0x5000) { |
93f9619e |
820 | if (PicoIn.AHW & PAHW_MCD) |
fa8fb754 |
821 | return PicoRead16_mcd_io(a); |
822 | else |
823 | return PicoRead16_io(a); |
824 | } |
974fdb5b |
825 | |
826 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
827 | d = p32x_vdp_read16(a); |
828 | goto out; |
829 | } |
830 | |
974fdb5b |
831 | if ((a & 0xfe00) == 0x5200) { // a15200 |
832 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
833 | goto out; |
834 | } |
835 | |
be2c4208 |
836 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
837 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
838 | goto out; |
839 | } |
840 | |
841 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
842 | return d; |
843 | |
844 | out: |
845 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
846 | return d; |
847 | } |
848 | |
83ff19ec |
849 | static void PicoWrite8_32x_on(u32 a, u32 d) |
be2c4208 |
850 | { |
851 | if ((a & 0xfc00) == 0x5000) |
852 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
853 | |
854 | if ((a & 0xffc0) == 0x5100) { // a15100 |
855 | p32x_reg_write8(a, d); |
856 | return; |
857 | } |
858 | |
83ff19ec |
859 | if ((a & 0xfc00) != 0x5000) { |
93f9619e |
860 | if (PicoIn.AHW & PAHW_MCD) |
fa8fb754 |
861 | PicoWrite8_mcd_io(a, d); |
862 | else |
863 | PicoWrite8_io(a, d); |
77e58d93 |
864 | if (a == 0xa130f1) |
8b9dbcde |
865 | bank_switch_rom_68k(Pico32x.regs[4 / 2]); |
83ff19ec |
866 | return; |
867 | } |
974fdb5b |
868 | |
5609d343 |
869 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
870 | if ((a & 0xfff0) == 0x5180) { // a15180 |
871 | p32x_vdp_write8(a, d); |
872 | return; |
873 | } |
be2c4208 |
874 | |
5609d343 |
875 | // TODO: verify |
876 | if ((a & 0xfe00) == 0x5200) { // a15200 |
877 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
878 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
879 | Pico32x.dirty_pal = 1; |
880 | return; |
881 | } |
974fdb5b |
882 | } |
883 | |
be2c4208 |
884 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
885 | } |
886 | |
83ff19ec |
887 | static void PicoWrite16_32x_on(u32 a, u32 d) |
be2c4208 |
888 | { |
889 | if ((a & 0xfc00) == 0x5000) |
553c3eaa |
890 | elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
be2c4208 |
891 | |
892 | if ((a & 0xffc0) == 0x5100) { // a15100 |
893 | p32x_reg_write16(a, d); |
894 | return; |
895 | } |
896 | |
83ff19ec |
897 | if ((a & 0xfc00) != 0x5000) { |
93f9619e |
898 | if (PicoIn.AHW & PAHW_MCD) |
fa8fb754 |
899 | PicoWrite16_mcd_io(a, d); |
900 | else |
901 | PicoWrite16_io(a, d); |
77e58d93 |
902 | if (a == 0xa130f0) |
8b9dbcde |
903 | bank_switch_rom_68k(Pico32x.regs[4 / 2]); |
83ff19ec |
904 | return; |
905 | } |
974fdb5b |
906 | |
5609d343 |
907 | if (!(Pico32x.regs[0] & P32XS_FM)) { |
908 | if ((a & 0xfff0) == 0x5180) { // a15180 |
909 | p32x_vdp_write16(a, d, NULL); // FIXME? |
910 | return; |
911 | } |
be2c4208 |
912 | |
5609d343 |
913 | if ((a & 0xfe00) == 0x5200) { // a15200 |
914 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
915 | Pico32x.dirty_pal = 1; |
916 | return; |
917 | } |
974fdb5b |
918 | } |
919 | |
be2c4208 |
920 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
921 | } |
922 | |
83ff19ec |
923 | // before ADEN |
924 | u32 PicoRead8_32x(u32 a) |
925 | { |
926 | u32 d = 0; |
83ff19ec |
927 | |
93f9619e |
928 | if (PicoIn.opt & POPT_EN_32X) { |
929 | if ((a & 0xffc0) == 0x5100) { // a15100 |
930 | // regs are always readable |
931 | d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1]; |
932 | goto out; |
933 | } |
934 | |
935 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
936 | d = str_mars[a & 3]; |
937 | goto out; |
938 | } |
83ff19ec |
939 | } |
940 | |
941 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
942 | return d; |
943 | |
944 | out: |
945 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
946 | return d; |
947 | } |
948 | |
949 | u32 PicoRead16_32x(u32 a) |
950 | { |
951 | u32 d = 0; |
83ff19ec |
952 | |
93f9619e |
953 | if (PicoIn.opt & POPT_EN_32X) { |
954 | if ((a & 0xffc0) == 0x5100) { // a15100 |
955 | d = Pico32x.regs[(a & 0x3f) / 2]; |
956 | goto out; |
957 | } |
958 | |
959 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
960 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
961 | goto out; |
962 | } |
83ff19ec |
963 | } |
964 | |
965 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
966 | return d; |
967 | |
968 | out: |
969 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
970 | return d; |
971 | } |
972 | |
973 | void PicoWrite8_32x(u32 a, u32 d) |
974 | { |
93f9619e |
975 | if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100 |
976 | { |
83ff19ec |
977 | u16 *r = Pico32x.regs; |
978 | |
979 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
980 | a &= 0x3f; |
981 | if (a == 1) { |
982 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
983 | Pico32xStartup(); |
984 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
985 | r[0] |= P32XS_ADEN; |
986 | p32x_reg_write8(a, d); // forward for reset processing |
987 | } |
988 | return; |
989 | } |
990 | |
991 | // allow only COMM for now |
992 | if ((a & 0x30) == 0x20) { |
993 | u8 *r8 = (u8 *)r; |
994 | r8[a ^ 1] = d; |
995 | } |
996 | return; |
997 | } |
998 | |
999 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
1000 | } |
1001 | |
1002 | void PicoWrite16_32x(u32 a, u32 d) |
1003 | { |
93f9619e |
1004 | if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100 |
1005 | { |
83ff19ec |
1006 | u16 *r = Pico32x.regs; |
1007 | |
1008 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
1009 | a &= 0x3e; |
1010 | if (a == 0) { |
1011 | if ((d ^ r[0]) & d & P32XS_ADEN) { |
1012 | Pico32xStartup(); |
1013 | r[0] &= ~P32XS_nRES; // causes reset if specified by this write |
1014 | r[0] |= P32XS_ADEN; |
1015 | p32x_reg_write16(a, d); // forward for reset processing |
1016 | } |
1017 | return; |
1018 | } |
1019 | |
1020 | // allow only COMM for now |
1021 | if ((a & 0x30) == 0x20) |
1022 | r[a / 2] = d; |
1023 | return; |
1024 | } |
1025 | |
1026 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
1027 | } |
1028 | |
34280f9b |
1029 | /* quirk: in both normal and overwrite areas only nonzero values go through */ |
1030 | #define sh2_write8_dramN(n) \ |
1031 | if ((d & 0xff) != 0) { \ |
1032 | u8 *dram = (u8 *)Pico32xMem->dram[n]; \ |
1033 | dram[(a & 0x1ffff) ^ 1] = d; \ |
1034 | } |
1035 | |
1036 | static void m68k_write8_dram0_ow(u32 a, u32 d) |
1037 | { |
1038 | sh2_write8_dramN(0); |
1039 | } |
1040 | |
1041 | static void m68k_write8_dram1_ow(u32 a, u32 d) |
1042 | { |
1043 | sh2_write8_dramN(1); |
1044 | } |
1045 | |
f81107f5 |
1046 | #define sh2_write16_dramN(n) \ |
34280f9b |
1047 | u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \ |
1048 | if (!(a & 0x20000)) { \ |
1049 | *pd = d; \ |
f81107f5 |
1050 | return; \ |
34280f9b |
1051 | } \ |
1052 | /* overwrite */ \ |
1053 | if (!(d & 0xff00)) d |= *pd & 0xff00; \ |
1054 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; \ |
f81107f5 |
1055 | *pd = d; |
34280f9b |
1056 | |
1057 | static void m68k_write16_dram0_ow(u32 a, u32 d) |
1058 | { |
f81107f5 |
1059 | sh2_write16_dramN(0); |
34280f9b |
1060 | } |
1061 | |
1062 | static void m68k_write16_dram1_ow(u32 a, u32 d) |
1063 | { |
f81107f5 |
1064 | sh2_write16_dramN(1); |
34280f9b |
1065 | } |
1066 | |
83ff19ec |
1067 | // ----------------------------------------------------------------- |
1068 | |
be2c4208 |
1069 | // hint vector is writeable |
1070 | static void PicoWrite8_hint(u32 a, u32 d) |
1071 | { |
1072 | if ((a & 0xfffc) == 0x0070) { |
1073 | Pico32xMem->m68k_rom[a ^ 1] = d; |
1074 | return; |
1075 | } |
1076 | |
77e58d93 |
1077 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", |
1078 | a, d & 0xff, SekPc); |
be2c4208 |
1079 | } |
1080 | |
1081 | static void PicoWrite16_hint(u32 a, u32 d) |
1082 | { |
1083 | if ((a & 0xfffc) == 0x0070) { |
1084 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
1085 | return; |
1086 | } |
1087 | |
77e58d93 |
1088 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", |
1089 | a, d & 0xffff, SekPc); |
1090 | } |
1091 | |
1092 | // normally not writable, but somebody could make a RAM cart |
1093 | static void PicoWrite8_cart(u32 a, u32 d) |
1094 | { |
1095 | elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
1096 | |
1097 | a &= 0xfffff; |
1098 | m68k_write8(a, d); |
1099 | } |
1100 | |
1101 | static void PicoWrite16_cart(u32 a, u32 d) |
1102 | { |
1103 | elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
1104 | |
1105 | a &= 0xfffff; |
1106 | m68k_write16(a, d); |
1107 | } |
1108 | |
1109 | // same with bank, but save ram is sometimes here |
1110 | static u32 PicoRead8_bank(u32 a) |
1111 | { |
1112 | a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff); |
1113 | return m68k_read8(a); |
1114 | } |
1115 | |
1116 | static u32 PicoRead16_bank(u32 a) |
1117 | { |
1118 | a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff); |
1119 | return m68k_read16(a); |
1120 | } |
1121 | |
1122 | static void PicoWrite8_bank(u32 a, u32 d) |
1123 | { |
1124 | if (!(Pico.m.sram_reg & SRR_MAPPED)) |
1125 | elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", |
1126 | a, d & 0xff, SekPc); |
1127 | |
1128 | a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff); |
1129 | m68k_write8(a, d); |
1130 | } |
1131 | |
1132 | static void PicoWrite16_bank(u32 a, u32 d) |
1133 | { |
1134 | if (!(Pico.m.sram_reg & SRR_MAPPED)) |
1135 | elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", |
1136 | a, d & 0xffff, SekPc); |
1137 | |
1138 | a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff); |
1139 | m68k_write16(a, d); |
1140 | } |
1141 | |
1142 | static void bank_map_handler(void) |
1143 | { |
1144 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1); |
1145 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1); |
be2c4208 |
1146 | } |
1147 | |
8b9dbcde |
1148 | static void bank_switch_rom_68k(int b) |
5e49c3a8 |
1149 | { |
8b9dbcde |
1150 | unsigned int rs, bank, bank2; |
5e49c3a8 |
1151 | |
fa8fb754 |
1152 | if (Pico.m.ncart_in) |
1153 | return; |
1154 | |
5e49c3a8 |
1155 | bank = b << 20; |
88fd63ad |
1156 | if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) { |
77e58d93 |
1157 | bank_map_handler(); |
1158 | return; |
1159 | } |
1160 | |
5e49c3a8 |
1161 | if (bank >= Pico.romsize) { |
1162 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
77e58d93 |
1163 | bank_map_handler(); |
5e49c3a8 |
1164 | return; |
1165 | } |
1166 | |
8b9dbcde |
1167 | // 32X ROM (XXX: consider mirroring?) |
5e49c3a8 |
1168 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
8b9dbcde |
1169 | if (!carthw_ssf2_active) { |
1170 | rs -= bank; |
1171 | if (rs > 0x100000) |
1172 | rs = 0x100000; |
1173 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
1174 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
1175 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
1176 | } |
1177 | else { |
1178 | bank = bank >> 19; |
1179 | bank2 = carthw_ssf2_banks[bank + 0] << 19; |
1180 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0); |
1181 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0); |
1182 | bank2 = carthw_ssf2_banks[bank + 1] << 19; |
1183 | cpu68k_map_set(m68k_read8_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0); |
1184 | cpu68k_map_set(m68k_read16_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0); |
1185 | } |
5e49c3a8 |
1186 | } |
1187 | |
acd35d4c |
1188 | // ----------------------------------------------------------------- |
1189 | // SH2 |
1190 | // ----------------------------------------------------------------- |
1191 | |
bcf65fd6 |
1192 | // read8 |
f81107f5 |
1193 | static u32 sh2_read8_unmapped(u32 a, SH2 *sh2) |
acd35d4c |
1194 | { |
f8675e28 |
1195 | elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x", |
1196 | a, 0, sh2_pc(sh2)); |
bcf65fd6 |
1197 | return 0; |
1198 | } |
b78efee2 |
1199 | |
f81107f5 |
1200 | static u32 sh2_read8_cs0(u32 a, SH2 *sh2) |
bcf65fd6 |
1201 | { |
1202 | u32 d = 0; |
97d3f47f |
1203 | |
8a847c12 |
1204 | sh2_burn_cycles(sh2, 1*2); |
1205 | |
eb35ce15 |
1206 | // 0x3ffc0 is veridied |
1207 | if ((a & 0x3ffc0) == 0x4000) { |
f81107f5 |
1208 | d = p32x_sh2reg_read16(a, sh2); |
db1d3564 |
1209 | goto out_16to8; |
acd35d4c |
1210 | } |
1211 | |
eb35ce15 |
1212 | if ((a & 0x3fff0) == 0x4100) { |
acd35d4c |
1213 | d = p32x_vdp_read16(a); |
4a1fb183 |
1214 | sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7); |
db1d3564 |
1215 | goto out_16to8; |
acd35d4c |
1216 | } |
1217 | |
bcf65fd6 |
1218 | // TODO: mirroring? |
f81107f5 |
1219 | if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m)) |
895d1512 |
1220 | return Pico32xMem->sh2_rom_m.b[a ^ 1]; |
f81107f5 |
1221 | if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s)) |
895d1512 |
1222 | return Pico32xMem->sh2_rom_s.b[a ^ 1]; |
bcf65fd6 |
1223 | |
1f1ff763 |
1224 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
1225 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
1226 | goto out_16to8; |
1227 | } |
1228 | |
f81107f5 |
1229 | return sh2_read8_unmapped(a, sh2); |
acd35d4c |
1230 | |
1231 | out_16to8: |
1232 | if (a & 1) |
1233 | d &= 0xff; |
1234 | else |
1235 | d >>= 8; |
1236 | |
f8675e28 |
1237 | elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x", |
1238 | a, d, sh2_pc(sh2)); |
acd35d4c |
1239 | return d; |
1240 | } |
1241 | |
f81107f5 |
1242 | static u32 sh2_read8_da(u32 a, SH2 *sh2) |
acd35d4c |
1243 | { |
f81107f5 |
1244 | return sh2->data_array[(a & 0xfff) ^ 1]; |
bcf65fd6 |
1245 | } |
acd35d4c |
1246 | |
8b9dbcde |
1247 | // for ssf2 |
1248 | static u32 sh2_read8_rom(u32 a, SH2 *sh2) |
1249 | { |
1250 | u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19; |
1251 | return Pico.rom[(bank + (a & 0x7ffff)) ^ 1]; |
1252 | } |
1253 | |
bcf65fd6 |
1254 | // read16 |
f81107f5 |
1255 | static u32 sh2_read16_unmapped(u32 a, SH2 *sh2) |
bcf65fd6 |
1256 | { |
f8675e28 |
1257 | elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x", |
1258 | a, 0, sh2_pc(sh2)); |
bcf65fd6 |
1259 | return 0; |
1260 | } |
b78efee2 |
1261 | |
f81107f5 |
1262 | static u32 sh2_read16_cs0(u32 a, SH2 *sh2) |
bcf65fd6 |
1263 | { |
1264 | u32 d = 0; |
97d3f47f |
1265 | |
8a847c12 |
1266 | sh2_burn_cycles(sh2, 1*2); |
1267 | |
eb35ce15 |
1268 | if ((a & 0x3ffc0) == 0x4000) { |
f81107f5 |
1269 | d = p32x_sh2reg_read16(a, sh2); |
1b3f5844 |
1270 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
1271 | return d; |
db1d3564 |
1272 | goto out; |
acd35d4c |
1273 | } |
1274 | |
eb35ce15 |
1275 | if ((a & 0x3fff0) == 0x4100) { |
acd35d4c |
1276 | d = p32x_vdp_read16(a); |
4a1fb183 |
1277 | sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7); |
db1d3564 |
1278 | goto out; |
acd35d4c |
1279 | } |
1280 | |
f81107f5 |
1281 | if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m)) |
895d1512 |
1282 | return Pico32xMem->sh2_rom_m.w[a / 2]; |
f81107f5 |
1283 | if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s)) |
895d1512 |
1284 | return Pico32xMem->sh2_rom_s.w[a / 2]; |
bcf65fd6 |
1285 | |
1f1ff763 |
1286 | if ((a & 0x3fe00) == 0x4200) { |
acd35d4c |
1287 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
1288 | goto out; |
1289 | } |
1290 | |
f81107f5 |
1291 | return sh2_read16_unmapped(a, sh2); |
acd35d4c |
1292 | |
1293 | out: |
f8675e28 |
1294 | elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x", |
1295 | a, d, sh2_pc(sh2)); |
acd35d4c |
1296 | return d; |
1297 | } |
1298 | |
f81107f5 |
1299 | static u32 sh2_read16_da(u32 a, SH2 *sh2) |
acd35d4c |
1300 | { |
f81107f5 |
1301 | return ((u16 *)sh2->data_array)[(a & 0xfff) / 2]; |
acd35d4c |
1302 | } |
1303 | |
8b9dbcde |
1304 | static u32 sh2_read16_rom(u32 a, SH2 *sh2) |
1305 | { |
1306 | u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19; |
1307 | return *(u16 *)(Pico.rom + bank + (a & 0x7fffe)); |
1308 | } |
1309 | |
f81107f5 |
1310 | // writes |
1311 | static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2) |
4b315c21 |
1312 | { |
1313 | } |
1314 | |
bcf65fd6 |
1315 | // write8 |
f81107f5 |
1316 | static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1317 | { |
f8675e28 |
1318 | elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x", |
1319 | a, d & 0xff, sh2_pc(sh2)); |
bcf65fd6 |
1320 | } |
266c6afa |
1321 | |
f81107f5 |
1322 | static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1323 | { |
f8675e28 |
1324 | elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x", |
1325 | a, d & 0xff, sh2_pc(sh2)); |
b78efee2 |
1326 | |
5609d343 |
1327 | if (Pico32x.regs[0] & P32XS_FM) { |
eb35ce15 |
1328 | if ((a & 0x3fff0) == 0x4100) { |
f81107f5 |
1329 | sh2->poll_addr = 0; |
5609d343 |
1330 | p32x_vdp_write8(a, d); |
f81107f5 |
1331 | return; |
5609d343 |
1332 | } |
acd35d4c |
1333 | } |
1334 | |
eb35ce15 |
1335 | if ((a & 0x3ffc0) == 0x4000) { |
f81107f5 |
1336 | p32x_sh2reg_write8(a, d, sh2); |
1337 | return; |
acd35d4c |
1338 | } |
1339 | |
f81107f5 |
1340 | sh2_write8_unmapped(a, d, sh2); |
bcf65fd6 |
1341 | } |
1342 | |
f81107f5 |
1343 | static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1344 | { |
1345 | sh2_write8_dramN(0); |
acd35d4c |
1346 | } |
1347 | |
f81107f5 |
1348 | static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1349 | { |
bcf65fd6 |
1350 | sh2_write8_dramN(1); |
1351 | } |
87accdf7 |
1352 | |
f81107f5 |
1353 | static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2) |
f4bb5d6b |
1354 | { |
1355 | u32 a1 = a & 0x3ffff; |
1356 | #ifdef DRC_SH2 |
1357 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1358 | if (t) |
f81107f5 |
1359 | sh2_drc_wcheck_ram(a, t, sh2->is_slave); |
f4bb5d6b |
1360 | #endif |
1361 | Pico32xMem->sdram[a1 ^ 1] = d; |
1362 | } |
1363 | |
8a847c12 |
1364 | static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2) |
1365 | { |
1366 | // xmen sync hack.. |
1367 | if (a < 0x26000200) |
1368 | sh2_end_run(sh2, 32); |
1369 | |
1370 | sh2_write8_sdram(a, d, sh2); |
1371 | } |
1372 | |
f81107f5 |
1373 | static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1374 | { |
f4bb5d6b |
1375 | u32 a1 = a & 0xfff; |
1376 | #ifdef DRC_SH2 |
f81107f5 |
1377 | int id = sh2->is_slave; |
f4bb5d6b |
1378 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1379 | if (t) |
1380 | sh2_drc_wcheck_da(a, t, id); |
1381 | #endif |
f81107f5 |
1382 | sh2->data_array[a1 ^ 1] = d; |
bcf65fd6 |
1383 | } |
acd35d4c |
1384 | |
bcf65fd6 |
1385 | // write16 |
f81107f5 |
1386 | static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1387 | { |
f8675e28 |
1388 | elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x", |
1389 | a, d & 0xffff, sh2_pc(sh2)); |
bcf65fd6 |
1390 | } |
b78efee2 |
1391 | |
f81107f5 |
1392 | static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1393 | { |
1394 | if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
f8675e28 |
1395 | elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x", |
1396 | a, d & 0xffff, sh2_pc(sh2)); |
266c6afa |
1397 | |
5609d343 |
1398 | if (Pico32x.regs[0] & P32XS_FM) { |
eb35ce15 |
1399 | if ((a & 0x3fff0) == 0x4100) { |
f81107f5 |
1400 | sh2->poll_addr = 0; |
1401 | p32x_vdp_write16(a, d, sh2); |
1402 | return; |
5609d343 |
1403 | } |
acd35d4c |
1404 | |
5609d343 |
1405 | if ((a & 0x3fe00) == 0x4200) { |
1406 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
1407 | Pico32x.dirty_pal = 1; |
f81107f5 |
1408 | return; |
5609d343 |
1409 | } |
acd35d4c |
1410 | } |
1411 | |
eb35ce15 |
1412 | if ((a & 0x3ffc0) == 0x4000) { |
f81107f5 |
1413 | p32x_sh2reg_write16(a, d, sh2); |
1414 | return; |
acd35d4c |
1415 | } |
1416 | |
f81107f5 |
1417 | sh2_write16_unmapped(a, d, sh2); |
bcf65fd6 |
1418 | } |
1419 | |
f81107f5 |
1420 | static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1421 | { |
f81107f5 |
1422 | sh2_write16_dramN(0); |
bcf65fd6 |
1423 | } |
1424 | |
f81107f5 |
1425 | static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1426 | { |
f81107f5 |
1427 | sh2_write16_dramN(1); |
bcf65fd6 |
1428 | } |
1429 | |
f81107f5 |
1430 | static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2) |
f4bb5d6b |
1431 | { |
1432 | u32 a1 = a & 0x3ffff; |
1433 | #ifdef DRC_SH2 |
1434 | int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; |
1435 | if (t) |
f81107f5 |
1436 | sh2_drc_wcheck_ram(a, t, sh2->is_slave); |
f4bb5d6b |
1437 | #endif |
1438 | ((u16 *)Pico32xMem->sdram)[a1 / 2] = d; |
1439 | } |
1440 | |
f81107f5 |
1441 | static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1442 | { |
f4bb5d6b |
1443 | u32 a1 = a & 0xfff; |
1444 | #ifdef DRC_SH2 |
f81107f5 |
1445 | int id = sh2->is_slave; |
f4bb5d6b |
1446 | int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; |
1447 | if (t) |
1448 | sh2_drc_wcheck_da(a, t, id); |
1449 | #endif |
f81107f5 |
1450 | ((u16 *)sh2->data_array)[a1 / 2] = d; |
bcf65fd6 |
1451 | } |
1452 | |
1453 | |
f81107f5 |
1454 | typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2); |
1455 | typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2); |
bcf65fd6 |
1456 | |
e05b81fc |
1457 | #define SH2MAP_ADDR2OFFS_R(a) \ |
f81107f5 |
1458 | ((u32)(a) >> SH2_READ_SHIFT) |
e05b81fc |
1459 | |
1460 | #define SH2MAP_ADDR2OFFS_W(a) \ |
1461 | ((u32)(a) >> SH2_WRITE_SHIFT) |
bcf65fd6 |
1462 | |
80599a42 |
1463 | u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2) |
bcf65fd6 |
1464 | { |
1465 | const sh2_memmap *sh2_map = sh2->read8_map; |
1466 | uptr p; |
1467 | |
e05b81fc |
1468 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1469 | p = sh2_map->addr; |
b8a1c09a |
1470 | if (map_flag_set(p)) |
f81107f5 |
1471 | return ((sh2_read_handler *)(p << 1))(a, sh2); |
bcf65fd6 |
1472 | else |
1473 | return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1)); |
1474 | } |
1475 | |
80599a42 |
1476 | u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2) |
bcf65fd6 |
1477 | { |
1478 | const sh2_memmap *sh2_map = sh2->read16_map; |
1479 | uptr p; |
1480 | |
e05b81fc |
1481 | sh2_map += SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1482 | p = sh2_map->addr; |
b8a1c09a |
1483 | if (map_flag_set(p)) |
f81107f5 |
1484 | return ((sh2_read_handler *)(p << 1))(a, sh2); |
bcf65fd6 |
1485 | else |
1486 | return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1487 | } |
1488 | |
80599a42 |
1489 | u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2) |
bcf65fd6 |
1490 | { |
1491 | const sh2_memmap *sh2_map = sh2->read16_map; |
1492 | sh2_read_handler *handler; |
1493 | u32 offs; |
1494 | uptr p; |
1495 | |
e05b81fc |
1496 | offs = SH2MAP_ADDR2OFFS_R(a); |
bcf65fd6 |
1497 | sh2_map += offs; |
1498 | p = sh2_map->addr; |
b8a1c09a |
1499 | if (!map_flag_set(p)) { |
bcf65fd6 |
1500 | // XXX: maybe 32bit access instead with ror? |
1501 | u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); |
1502 | return (pd[0] << 16) | pd[1]; |
1d7a28a7 |
1503 | } |
1504 | |
77e58d93 |
1505 | if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000)) |
f81107f5 |
1506 | return sh2_peripheral_read32(a, sh2); |
bcf65fd6 |
1507 | |
1508 | handler = (sh2_read_handler *)(p << 1); |
f81107f5 |
1509 | return (handler(a, sh2) << 16) | handler(a + 2, sh2); |
bcf65fd6 |
1510 | } |
1511 | |
f81107f5 |
1512 | void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1513 | { |
f4bb5d6b |
1514 | const void **sh2_wmap = sh2->write8_tab; |
1515 | sh2_write_handler *wh; |
bcf65fd6 |
1516 | |
e05b81fc |
1517 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
f81107f5 |
1518 | wh(a, d, sh2); |
bcf65fd6 |
1519 | } |
1520 | |
f81107f5 |
1521 | void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2) |
bcf65fd6 |
1522 | { |
f4bb5d6b |
1523 | const void **sh2_wmap = sh2->write16_tab; |
1524 | sh2_write_handler *wh; |
bcf65fd6 |
1525 | |
e05b81fc |
1526 | wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; |
f81107f5 |
1527 | wh(a, d, sh2); |
acd35d4c |
1528 | } |
1529 | |
f81107f5 |
1530 | void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2) |
acd35d4c |
1531 | { |
f4bb5d6b |
1532 | const void **sh2_wmap = sh2->write16_tab; |
f81107f5 |
1533 | sh2_write_handler *wh; |
bcf65fd6 |
1534 | u32 offs; |
bcf65fd6 |
1535 | |
e05b81fc |
1536 | offs = SH2MAP_ADDR2OFFS_W(a); |
bcf65fd6 |
1537 | |
e05b81fc |
1538 | if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) { |
f81107f5 |
1539 | sh2_peripheral_write32(a, d, sh2); |
1540 | return; |
4ea707e1 |
1541 | } |
1542 | |
f81107f5 |
1543 | wh = sh2_wmap[offs]; |
1544 | wh(a, d >> 16, sh2); |
1545 | wh(a + 2, d, sh2); |
acd35d4c |
1546 | } |
1547 | |
bcf65fd6 |
1548 | // ----------------------------------------------------------------- |
1549 | |
419973a6 |
1550 | static void z80_md_bank_write_32x(unsigned int a, unsigned char d) |
1551 | { |
1552 | unsigned int addr68k; |
1553 | |
1554 | addr68k = Pico.m.z80_bank68k << 15; |
1555 | addr68k += a & 0x7fff; |
1556 | if ((addr68k & 0xfff000) == 0xa15000) |
1557 | Pico32x.emu_flags |= P32XF_Z80_32X_IO; |
1558 | |
1559 | elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d); |
1560 | m68k_write8(addr68k, d); |
1561 | } |
1562 | |
1563 | // ----------------------------------------------------------------- |
1564 | |
83ff19ec |
1565 | static const u16 msh2_code[] = { |
1566 | // trap instructions |
fa8fb754 |
1567 | 0xaffe, // 200 bra <self> |
1568 | 0x0009, // 202 nop |
83ff19ec |
1569 | // have to wait a bit until m68k initial program finishes clearing stuff |
1570 | // to avoid races with game SH2 code, like in Tempo |
fa8fb754 |
1571 | 0xd406, // 204 mov.l @(_m_ok,pc), r4 |
1572 | 0xc400, // 206 mov.b @(h'0,gbr),r0 |
1573 | 0xc801, // 208 tst #1, r0 |
1574 | 0x8b0f, // 20a bf cd_start |
1575 | 0xd105, // 20c mov.l @(_cnt,pc), r1 |
1576 | 0xd206, // 20e mov.l @(_start,pc), r2 |
1577 | 0x71ff, // 210 add #-1, r1 |
1578 | 0x4115, // 212 cmp/pl r1 |
1579 | 0x89fc, // 214 bt -2 |
1580 | 0x6043, // 216 mov r4, r0 |
1581 | 0xc208, // 218 mov.l r0, @(h'20,gbr) |
1582 | 0x6822, // 21a mov.l @r2, r8 |
1583 | 0x482b, // 21c jmp @r8 |
1584 | 0x0009, // 21e nop |
1585 | ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok |
1586 | 0x0001, 0x0000, // 224 _cnt |
1587 | 0x2200, 0x03e0, // master start pointer in ROM |
1588 | // cd_start: |
1589 | 0xd20d, // 22c mov.l @(__cd_,pc), r2 |
1590 | 0xc608, // 22e mov.l @(h'20,gbr), r0 |
1591 | 0x3200, // 230 cmp/eq r0, r2 |
1592 | 0x8bfc, // 232 bf #-2 |
1593 | 0xe000, // 234 mov #0, r0 |
1594 | 0xcf80, // 236 or.b #0x80,@(r0,gbr) |
1595 | 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018 |
1596 | 0xd30c, // 23a mov.l @(_max_len,pc), r3 |
1597 | 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr |
1598 | 0x5a82, // 23e mov.l @(8,r8), r10 // entry |
1599 | 0x5081, // 240 mov.l @(4,r8), r0 // len |
1600 | 0x5980, // 242 mov.l @(0,r8), r9 // dst |
1601 | 0x3036, // 244 cmp/hi r3,r0 |
1602 | 0x8b00, // 246 bf #1 |
1603 | 0x6033, // 248 mov r3,r0 |
1604 | 0x7820, // 24a add #0x20, r8 |
1605 | // ipl_copy: |
1606 | 0x6286, // 24c mov.l @r8+, r2 |
1607 | 0x2922, // 24e mov.l r2, @r9 |
1608 | 0x7904, // 250 add #4, r9 |
1609 | 0x70fc, // 252 add #-4, r0 |
1610 | 0x8800, // 254 cmp/eq #0, r0 |
1611 | 0x8bf9, // 256 bf #-5 |
1612 | // |
1613 | 0x4b2e, // 258 ldc r11, vbr |
1614 | 0x6043, // 25a mov r4, r0 // M_OK |
1615 | 0xc208, // 25c mov.l r0, @(h'20,gbr) |
1616 | 0x4a2b, // 25e jmp @r10 |
1617 | 0x0009, // 260 nop |
1618 | 0x0009, // 262 nop // pad |
1619 | ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_ |
1620 | 0x2400, 0x0018, // 268 _start_cd |
1621 | 0x0001, 0xffe0, // 26c _max_len |
83ff19ec |
1622 | }; |
1623 | |
1624 | static const u16 ssh2_code[] = { |
fa8fb754 |
1625 | 0xaffe, // 200 bra <self> |
1626 | 0x0009, // 202 nop |
83ff19ec |
1627 | // code to wait for master, in case authentic master BIOS is used |
fa8fb754 |
1628 | 0xd106, // 204 mov.l @(_m_ok,pc), r1 |
1629 | 0xd208, // 206 mov.l @(_start,pc), r2 |
1630 | 0xc608, // 208 mov.l @(h'20,gbr), r0 |
1631 | 0x3100, // 20a cmp/eq r0, r1 |
1632 | 0x8bfc, // 20c bf #-2 |
1633 | 0xc400, // 20e mov.b @(h'0,gbr),r0 |
1634 | 0xc801, // 210 tst #1, r0 |
1635 | 0xd004, // 212 mov.l @(_s_ok,pc), r0 |
1636 | 0x8b0a, // 214 bf cd_start |
1637 | 0xc209, // 216 mov.l r0, @(h'24,gbr) |
1638 | 0x6822, // 218 mov.l @r2, r8 |
1639 | 0x482b, // 21a jmp @r8 |
1640 | 0x0009, // 21c nop |
1641 | 0x0009, // 21e nop |
1642 | ('M'<<8)|'_', ('O'<<8)|'K', // 220 |
1643 | ('S'<<8)|'_', ('O'<<8)|'K', // 224 |
1644 | 0x2200, 0x03e4, // slave start pointer in ROM |
1645 | // cd_start: |
1646 | 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018 |
1647 | 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr |
1648 | 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry |
1649 | 0x4b2e, // 232 ldc r11, vbr |
1650 | 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK |
1651 | 0x4a2b, // 236 jmp @r10 |
1652 | 0x0009, // 238 nop |
1653 | 0x0009, // 23a nop |
1654 | 0x2400, 0x0018, // 23c _start_cd |
83ff19ec |
1655 | }; |
1656 | |
da77daa9 |
1657 | #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16)) |
83ff19ec |
1658 | static void get_bios(void) |
be2c4208 |
1659 | { |
83ff19ec |
1660 | u16 *ps; |
1661 | u32 *pl; |
be2c4208 |
1662 | int i; |
1663 | |
83ff19ec |
1664 | // M68K ROM |
1665 | if (p32x_bios_g != NULL) { |
1666 | elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS"); |
b4db550e |
1667 | Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1668 | } |
83ff19ec |
1669 | else { |
eefdb8a5 |
1670 | static const u16 andb[] = { 0x0239, 0x00fe, 0x00a1, 0x5107 }; |
1671 | static const u16 p_d4[] = { |
1672 | 0x48e7, 0x8040, // movem.l d0/a1, -(sp) |
1673 | 0x227c, 0x00a1, 0x30f1, // movea.l #0xa130f1, a1 |
1674 | 0x7007, // moveq.l #7, d0 |
1675 | 0x12d8, //0: move.b (a0)+, (a1)+ |
1676 | 0x5289, // addq.l #1, a1 |
1677 | 0x51c8, 0xfffa, // dbra d0, 0b |
1678 | 0x0239, 0x00fe, 0x00a1, // and.b #0xfe, (0xa15107).l |
1679 | 0x5107, |
1680 | 0x4cdf, 0x0201 // movem.l (sp)+, d0/a1 |
1681 | }; |
1682 | |
83ff19ec |
1683 | // generate 68k ROM |
1684 | ps = (u16 *)Pico32xMem->m68k_rom; |
1685 | pl = (u32 *)ps; |
1686 | for (i = 1; i < 0xc0/4; i++) |
1687 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
eefdb8a5 |
1688 | pl[0x70/4] = 0; |
be2c4208 |
1689 | |
83ff19ec |
1690 | // fill with nops |
1691 | for (i = 0xc0/2; i < 0x100/2; i++) |
1692 | ps[i] = 0x4e71; |
be2c4208 |
1693 | |
eefdb8a5 |
1694 | // c0: don't need to care about RV - not emulated |
1695 | ps[0xc8/2] = 0x1280; // move.b d0, (a1) |
1696 | memcpy(ps + 0xca/2, andb, sizeof(andb)); // and.b #0xfe, (a15107) |
1697 | ps[0xd2/2] = 0x4e75; // rts |
1698 | // d4: |
1699 | memcpy(ps + 0xd4/2, p_d4, sizeof(p_d4)); |
83ff19ec |
1700 | ps[0xfe/2] = 0x4e75; // rts |
83ff19ec |
1701 | } |
1702 | // fill remaining m68k_rom page with game ROM |
b4db550e |
1703 | memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom), |
1704 | Pico.rom + sizeof(Pico32xMem->m68k_rom), |
1705 | sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom)); |
be2c4208 |
1706 | |
83ff19ec |
1707 | // MSH2 |
1708 | if (p32x_bios_m != NULL) { |
1709 | elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS"); |
895d1512 |
1710 | Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m)); |
acd35d4c |
1711 | } |
83ff19ec |
1712 | else { |
895d1512 |
1713 | pl = (u32 *)&Pico32xMem->sh2_rom_m; |
83ff19ec |
1714 | |
1715 | // fill exception vector table to our trap address |
1716 | for (i = 0; i < 128; i++) |
1717 | pl[i] = HWSWAP(0x200); |
1718 | |
83ff19ec |
1719 | // start |
1720 | pl[0] = pl[2] = HWSWAP(0x204); |
fa8fb754 |
1721 | // reset SP |
1722 | pl[1] = pl[3] = HWSWAP(0x6040000); |
1723 | |
1724 | // startup code |
1725 | memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code)); |
83ff19ec |
1726 | } |
1727 | |
1728 | // SSH2 |
1729 | if (p32x_bios_s != NULL) { |
1730 | elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS"); |
895d1512 |
1731 | Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s)); |
83ff19ec |
1732 | } |
1733 | else { |
895d1512 |
1734 | pl = (u32 *)&Pico32xMem->sh2_rom_s; |
83ff19ec |
1735 | |
1736 | // fill exception vector table to our trap address |
1737 | for (i = 0; i < 128; i++) |
1738 | pl[i] = HWSWAP(0x200); |
1739 | |
83ff19ec |
1740 | // start |
1741 | pl[0] = pl[2] = HWSWAP(0x204); |
fa8fb754 |
1742 | // reset SP |
1743 | pl[1] = pl[3] = HWSWAP(0x603f800); |
1744 | |
1745 | // startup code |
1746 | memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code)); |
83ff19ec |
1747 | } |
1748 | } |
1749 | |
bcf65fd6 |
1750 | #define MAP_MEMORY(m) ((uptr)(m) >> 1) |
b8a1c09a |
1751 | #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) ) |
bcf65fd6 |
1752 | |
f81107f5 |
1753 | static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80]; |
f4bb5d6b |
1754 | // for writes we are using handlers only |
e05b81fc |
1755 | static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80]; |
bcf65fd6 |
1756 | |
1757 | void Pico32xSwapDRAM(int b) |
1758 | { |
1759 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
1760 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
34280f9b |
1761 | cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1762 | cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); |
1763 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff, |
1764 | b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1); |
1765 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff, |
1766 | b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1); |
bcf65fd6 |
1767 | |
1768 | // SH2 |
f81107f5 |
1769 | sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr = |
1770 | sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]); |
bcf65fd6 |
1771 | |
e05b81fc |
1772 | sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0; |
1773 | sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0; |
bcf65fd6 |
1774 | } |
1775 | |
8b9dbcde |
1776 | static void bank_switch_rom_sh2(void) |
1777 | { |
1778 | if (!carthw_ssf2_active) { |
1779 | // easy |
1780 | sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = |
1781 | sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom); |
1782 | } |
1783 | else { |
1784 | sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = MAP_HANDLER(sh2_read8_rom); |
1785 | sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_HANDLER(sh2_read16_rom); |
1786 | } |
1787 | } |
1788 | |
83ff19ec |
1789 | void PicoMemSetup32x(void) |
1790 | { |
1791 | unsigned int rs; |
bcf65fd6 |
1792 | int i; |
83ff19ec |
1793 | |
e743be20 |
1794 | Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0); |
83ff19ec |
1795 | if (Pico32xMem == NULL) { |
1796 | elprintf(EL_STATUS, "OOM"); |
1797 | return; |
1798 | } |
1799 | |
83ff19ec |
1800 | get_bios(); |
acd35d4c |
1801 | |
be2c4208 |
1802 | // cartridge area becomes unmapped |
1803 | // XXX: we take the easy way and don't unmap ROM, |
1804 | // so that we can avoid handling the RV bit. |
1805 | // m68k_map_unmap(0x000000, 0x3fffff); |
1806 | |
fa8fb754 |
1807 | if (!Pico.m.ncart_in) { |
1808 | // MD ROM area |
1809 | rs = sizeof(Pico32xMem->m68k_rom_bank); |
1810 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
1811 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); |
1812 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1813 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1814 | |
1815 | // 32X ROM (unbanked, XXX: consider mirroring?) |
1816 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1817 | if (rs > 0x80000) |
1818 | rs = 0x80000; |
1819 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1820 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1821 | cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1); |
1822 | cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1); |
be2c4208 |
1823 | |
fa8fb754 |
1824 | // 32X ROM (banked) |
8b9dbcde |
1825 | bank_switch_rom_68k(0); |
fa8fb754 |
1826 | cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1); |
1827 | cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1); |
1828 | } |
b78efee2 |
1829 | |
83ff19ec |
1830 | // SYS regs |
1831 | cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1); |
1832 | cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1); |
1833 | cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1); |
1834 | cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1); |
1835 | |
bcf65fd6 |
1836 | // SH2 maps: A31,A30,A29,CS1,CS0 |
1837 | // all unmapped by default |
e05b81fc |
1838 | for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) { |
bcf65fd6 |
1839 | sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped); |
1840 | sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped); |
e05b81fc |
1841 | } |
1842 | |
1843 | for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) { |
f4bb5d6b |
1844 | sh2_write8_map[i] = sh2_write8_unmapped; |
1845 | sh2_write16_map[i] = sh2_write16_unmapped; |
bcf65fd6 |
1846 | } |
1847 | |
4b315c21 |
1848 | // "purge area" |
e05b81fc |
1849 | for (i = 0x40; i <= 0x5f; i++) { |
1850 | sh2_write8_map[i >> 1] = |
1851 | sh2_write16_map[i >> 1] = sh2_write_ignore; |
4b315c21 |
1852 | } |
1853 | |
bcf65fd6 |
1854 | // CS0 |
f81107f5 |
1855 | sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0); |
1856 | sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0); |
e05b81fc |
1857 | sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0; |
1858 | sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0; |
bcf65fd6 |
1859 | // CS1 - ROM |
8b9dbcde |
1860 | bank_switch_rom_sh2(); |
f81107f5 |
1861 | sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask = |
1862 | sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME |
bcf65fd6 |
1863 | // CS2 - DRAM - done by Pico32xSwapDRAM() |
f81107f5 |
1864 | sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask = |
1865 | sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff; |
bcf65fd6 |
1866 | // CS3 - SDRAM |
f81107f5 |
1867 | sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr = |
1868 | sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram); |
8a847c12 |
1869 | sh2_write8_map[0x06/2] = sh2_write8_sdram; |
1870 | sh2_write8_map[0x26/2] = sh2_write8_sdram_wt; |
f81107f5 |
1871 | sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram; |
1872 | sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask = |
1873 | sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff; |
bcf65fd6 |
1874 | // SH2 data array |
f81107f5 |
1875 | sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da); |
1876 | sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da); |
1877 | sh2_write8_map[0xc0/2] = sh2_write8_da; |
1878 | sh2_write16_map[0xc0/2] = sh2_write16_da; |
bcf65fd6 |
1879 | // SH2 IO |
f81107f5 |
1880 | sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8); |
1881 | sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16); |
1882 | sh2_write8_map[0xff/2] = sh2_peripheral_write8; |
1883 | sh2_write16_map[0xff/2] = sh2_peripheral_write16; |
bcf65fd6 |
1884 | |
1885 | // map DRAM area, both 68k and SH2 |
1886 | Pico32xSwapDRAM(1); |
1887 | |
1888 | msh2.read8_map = ssh2.read8_map = sh2_read8_map; |
1889 | msh2.read16_map = ssh2.read16_map = sh2_read16_map; |
23686515 |
1890 | msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map; |
1891 | msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map; |
bcf65fd6 |
1892 | |
23686515 |
1893 | sh2_drc_mem_setup(&msh2); |
1894 | sh2_drc_mem_setup(&ssh2); |
419973a6 |
1895 | |
1896 | // z80 hack |
1897 | z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1); |
be2c4208 |
1898 | } |
1899 | |
8b9dbcde |
1900 | void p32x_update_banks(void) |
1901 | { |
1902 | bank_switch_rom_68k(Pico32x.regs[4 / 2]); |
1903 | bank_switch_rom_sh2(); |
1904 | if (Pico32x.emu_flags & P32XF_DRC_ROM_C) |
1905 | sh2_drc_flush_all(); |
1906 | } |
1907 | |
27e26273 |
1908 | void Pico32xMemStateLoaded(void) |
b4db550e |
1909 | { |
8b9dbcde |
1910 | bank_switch_rom_68k(Pico32x.regs[4 / 2]); |
b4db550e |
1911 | Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS); |
b4db550e |
1912 | memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm)); |
27e26273 |
1913 | Pico32x.dirty_pal = 1; |
51d86e55 |
1914 | |
19886062 |
1915 | Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL); |
1916 | memset(&m68k_poll, 0, sizeof(m68k_poll)); |
1917 | msh2.state = 0; |
1918 | msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0; |
1919 | ssh2.state = 0; |
1920 | ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0; |
1921 | |
b4db550e |
1922 | sh2_drc_flush_all(); |
b4db550e |
1923 | } |
1924 | |
ed4402a7 |
1925 | // vim:shiftwidth=2:ts=2:expandtab |