[picodrive.git] / pico / memory.c

/*\r
 * memory handling\r
 * (c) Copyright Dave, 2004\r
 * (C) notaz, 2006-2010\r
 * (C) irixxxx, 2019-2024\r
 *\r
 * This work is licensed under the terms of MAME license.\r
 * See COPYING file in the top-level directory.\r
 */\r
\r
#include "pico_int.h"\r
#include "memory.h"\r
\r
#include "sound/ym2612.h"\r
#include "sound/sn76496.h"\r
\r
extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
\r
uptr m68k_read8_map  [0x1000000 >> M68K_MEM_SHIFT];\r
uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
\r
static void xmap_set(uptr *map, int shift, u32 start_addr, u32 end_addr,\r
    const void *func_or_mh, int is_func)\r
{\r
#ifdef __clang__\r
  // workaround bug (segfault) in \r
  // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
  volatile \r
#endif\r
  uptr addr = (uptr)func_or_mh;\r
  int mask = (1 << shift) - 1;\r
  int i;\r
\r
  if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r
    elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r
      start_addr, end_addr);\r
    return;\r
  }\r
\r
  if (addr & 1) {\r
    elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r
    return;\r
  }\r
\r
  if (!is_func)\r
    addr -= start_addr;\r
\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
    map[i] = addr >> 1;\r
    if (is_func)\r
      map[i] |= MAP_FLAG;\r
  }\r
}\r
\r
void z80_map_set(uptr *map, u16 start_addr, u16 end_addr,\r
    const void *func_or_mh, int is_func)\r
{\r
  xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
#ifdef _USE_CZ80\r
  if (!is_func)\r
    Cz80_Set_Fetch(&CZ80, start_addr, end_addr, (FPTR)func_or_mh);\r
#endif\r
}\r
\r
void cpu68k_map_set(uptr *map, u32 start_addr, u32 end_addr,\r
    const void *func_or_mh, int is_func)\r
{\r
  xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func & 1);\r
#ifdef EMU_F68K\r
  // setup FAME fetchmap\r
  if (!(is_func & 1))\r
  {\r
    M68K_CONTEXT *ctx = is_func & 2 ? &PicoCpuFS68k : &PicoCpuFM68k;\r
    int shiftout = 24 - FAMEC_FETCHBITS;\r
    int i = start_addr >> shiftout;\r
    uptr base = (uptr)func_or_mh - (i << shiftout);\r
    for (; i <= (end_addr >> shiftout); i++)\r
      ctx->Fetch[i] = base;\r
  }\r
#endif\r
}\r
\r
// more specialized/optimized function (does same as above)\r
void cpu68k_map_read_mem(u32 start_addr, u32 end_addr, void *ptr, int is_sub)\r
{\r
  uptr *r8map, *r16map;\r
  uptr addr = (uptr)ptr;\r
  int shift = M68K_MEM_SHIFT;\r
  int i;\r
\r
  if (!is_sub) {\r
    r8map = m68k_read8_map;\r
    r16map = m68k_read16_map;\r
  } else {\r
    r8map = s68k_read8_map;\r
    r16map = s68k_read16_map;\r
  }\r
\r
  addr -= start_addr;\r
  addr >>= 1;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    r8map[i] = r16map[i] = addr;\r
#ifdef EMU_F68K\r
  // setup FAME fetchmap\r
  {\r
    M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;\r
    int shiftout = 24 - FAMEC_FETCHBITS;\r
    i = start_addr >> shiftout;\r
    addr = (uptr)ptr - (i << shiftout);\r
    for (; i <= (end_addr >> shiftout); i++)\r
      ctx->Fetch[i] = addr;\r
  }\r
#endif\r
}\r
\r
void cpu68k_map_all_ram(u32 start_addr, u32 end_addr, void *ptr, int is_sub)\r
{\r
  uptr *r8map, *r16map, *w8map, *w16map;\r
  uptr addr = (uptr)ptr;\r
  int shift = M68K_MEM_SHIFT;\r
  int i;\r
\r
  if (!is_sub) {\r
    r8map = m68k_read8_map;\r
    r16map = m68k_read16_map;\r
    w8map = m68k_write8_map;\r
    w16map = m68k_write16_map;\r
  } else {\r
    r8map = s68k_read8_map;\r
    r16map = s68k_read16_map;\r
    w8map = s68k_write8_map;\r
    w16map = s68k_write16_map;\r
  }\r
\r
  addr -= start_addr;\r
  addr >>= 1;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r
#ifdef EMU_F68K\r
  // setup FAME fetchmap\r
  {\r
    M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;\r
    int shiftout = 24 - FAMEC_FETCHBITS;\r
    i = start_addr >> shiftout;\r
    addr = (uptr)ptr - (i << shiftout);\r
    for (; i <= (end_addr >> shiftout); i++)\r
      ctx->Fetch[i] = addr;\r
  }\r
#endif\r
}\r
\r
void cpu68k_map_read_funcs(u32 start_addr, u32 end_addr, u32 (*r8)(u32), u32 (*r16)(u32), int is_sub)\r
{\r
  uptr *r8map, *r16map;\r
  uptr ar8 = (uptr)r8, ar16 = (uptr)r16;\r
  int shift = M68K_MEM_SHIFT;\r
  int i;\r
\r
  if (!is_sub) {\r
    r8map = m68k_read8_map;\r
    r16map = m68k_read16_map;\r
  } else {\r
    r8map = s68k_read8_map;\r
    r16map = s68k_read16_map;\r
  }\r
\r
  ar8 = (ar8 >> 1 ) | MAP_FLAG;\r
  ar16 = (ar16 >> 1 ) | MAP_FLAG;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    r8map[i] = ar8, r16map[i] = ar16;\r
}\r
\r
void cpu68k_map_all_funcs(u32 start_addr, u32 end_addr, u32 (*r8)(u32), u32 (*r16)(u32), void (*w8)(u32, u32), void (*w16)(u32, u32), int is_sub)\r
{\r
  uptr *r8map, *r16map, *w8map, *w16map;\r
  uptr ar8 = (uptr)r8, ar16 = (uptr)r16;\r
  uptr aw8 = (uptr)w8, aw16 = (uptr)w16;\r
  int shift = M68K_MEM_SHIFT;\r
  int i;\r
\r
  if (!is_sub) {\r
    r8map = m68k_read8_map;\r
    r16map = m68k_read16_map;\r
    w8map = m68k_write8_map;\r
    w16map = m68k_write16_map;\r
  } else {\r
    r8map = s68k_read8_map;\r
    r16map = s68k_read16_map;\r
    w8map = s68k_write8_map;\r
    w16map = s68k_write16_map;\r
  }\r
\r
  ar8 = (ar8 >> 1 ) | MAP_FLAG;\r
  ar16 = (ar16 >> 1 ) | MAP_FLAG;\r
  aw8 = (aw8 >> 1 ) | MAP_FLAG;\r
  aw16 = (aw16 >> 1 ) | MAP_FLAG;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    r8map[i] = ar8, r16map[i] = ar16, w8map[i] = aw8, w16map[i] = aw16;\r
}\r
\r
u32 PicoRead16_floating(u32 a)\r
{\r
  // faking open bus\r
  u32 d = (Pico.m.rotate += 0x41);\r
  d ^= (d << 5) ^ (d << 8);\r
  if ((a & 0xff0000) == 0xa10000) return d; // MegaCD pulldowns don't work here curiously\r
  return (PicoIn.AHW & PAHW_MCD) ? 0x00 : d; // pulldown if MegaCD2 attached\r
}\r
\r
static u32 m68k_unmapped_read8(u32 a)\r
{\r
  elprintf(EL_UIO, "m68k unmapped r8  [%06x] @%06x", a, SekPc);\r
  return a < 0x400000 ? 0 : (u8)PicoRead16_floating(a);\r
}\r
\r
static u32 m68k_unmapped_read16(u32 a)\r
{\r
  elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r
  return a < 0x400000 ? 0 : PicoRead16_floating(a);\r
}\r
\r
static void m68k_unmapped_write8(u32 a, u32 d)\r
{\r
  elprintf(EL_UIO, "m68k unmapped w8  [%06x]   %02x @%06x", a, d & 0xff, SekPc);\r
}\r
\r
static void m68k_unmapped_write16(u32 a, u32 d)\r
{\r
  elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
}\r
\r
void m68k_map_unmap(u32 start_addr, u32 end_addr)\r
{\r
#ifdef __clang__\r
  // workaround bug (segfault) in \r
  // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)\r
  volatile \r
#endif\r
  uptr addr;\r
  int shift = M68K_MEM_SHIFT;\r
  int i;\r
\r
  addr = (uptr)m68k_unmapped_read8;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;\r
\r
  addr = (uptr)m68k_unmapped_read16;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;\r
\r
  addr = (uptr)m68k_unmapped_write8;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;\r
\r
  addr = (uptr)m68k_unmapped_write16;\r
  for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
    m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;\r
}\r
\r
#ifndef _ASM_MEMORY_C\r
MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r
MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r
MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r
MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r
MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r
MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r
#endif\r
\r
// -----------------------------------------------------------------\r
\r
static u32 ym2612_read_local_68k(void);\r
static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
static void z80_mem_setup(void);\r
\r
#ifdef _ASM_MEMORY_C\r
u32 PicoRead8_sram(u32 a);\r
u32 PicoRead16_sram(u32 a);\r
#endif\r
\r
#ifdef EMU_CORE_DEBUG\r
u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
extern unsigned int ppop;\r
#endif\r
\r
#ifdef IO_STATS\r
void log_io(unsigned int addr, int bits, int rw);\r
#elif defined(_MSC_VER)\r
#define log_io\r
#else\r
#define log_io(...)\r
#endif\r
\r
#if defined(EMU_C68K)\r
void cyclone_crashed(u32 pc, struct Cyclone *context)\r
{\r
    elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",\r
      context == &PicoCpuCM68k ? 'm' : 's', pc);\r
    context->membase = (u32)Pico.rom;\r
    context->pc = (u32)Pico.rom + Pico.romsize;\r
}\r
#endif\r
\r
// -----------------------------------------------------------------\r
// memmap helpers\r
\r
static u32 read_pad_3btn(int i, u32 out_bits)\r
{\r
  u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
  u32 value;\r
\r
  if (out_bits & 0x40) // TH\r
    value = pad & 0x3f;                      // ?1CB RLDU\r
  else\r
    value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU\r
\r
  value |= out_bits & 0x40;\r
  return value;\r
}\r
\r
static u32 read_pad_6btn(int i, u32 out_bits)\r
{\r
  u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
  int phase = Pico.m.padTHPhase[i];\r
  u32 value;\r
\r
  if (phase == 2 && !(out_bits & 0x40)) {\r
    value = (pad & 0xc0) >> 2;                   // ?0SA 0000\r
    goto out;\r
  }\r
  else if(phase == 3) {\r
    if (out_bits & 0x40)\r
      value = (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ\r
    else\r
      value = ((pad & 0xc0) >> 2) | 0x0f;        // ?0SA 1111\r
    goto out;\r
  }\r
\r
  if (out_bits & 0x40) // TH\r
    value = pad & 0x3f;                          // ?1CB RLDU\r
  else\r
    value = ((pad & 0xc0) >> 2) | (pad & 3);     // ?0SA 00DU\r
\r
out:\r
  value |= out_bits & 0x40;\r
  return value;\r
}\r
\r
static u32 read_pad_team(int i, u32 out_bits)\r
{\r
  u32 pad;\r
  int phase = Pico.m.padTHPhase[i];\r
  u32 value;\r
\r
  switch (phase) {\r
  case 0:\r
    value = 0x03;\r
    break;\r
  case 1:\r
    value = 0x0f;\r
    break;\r
  case 4: case 5: case 6: case 7: // controller IDs, all 3 btn for now\r
    value = 0x00;\r
    break;\r
  case 8: case 10: case 12: case 14:\r
    pad = ~PicoIn.padInt[(phase-8) >> 1];\r
    value = pad & 0x0f;                          // ?x?x RLDU\r
    break;\r
  case 9: case 11: case 13: case 15:\r
    pad = ~PicoIn.padInt[(phase-8) >> 1];\r
    value = (pad & 0xf0) >>  4;                  // ?x?x SACB\r
    break;\r
  default:\r
    value = 0;\r
    break;\r
  }\r
\r
  value |= (out_bits & 0x40) | ((out_bits & 0x20)>>1);\r
  return value;\r
}\r
\r
static u32 read_pad_4way(int i, u32 out_bits)\r
{\r
  u32 pad = (PicoMem.ioports[2] & 0x70) >> 4;\r
  u32 value = 0;\r
\r
  if (i == 0 && pad <= 3)\r
    value = read_pad_3btn(pad, out_bits);\r
\r
  value |= (out_bits & 0x40);\r
  return value;\r
}\r
\r
static u32 read_nothing(int i, u32 out_bits)\r
{\r
  return 0xff;\r
}\r
\r
typedef u32 (port_read_func)(int index, u32 out_bits);\r
\r
static port_read_func *port_readers[3] = {\r
  read_pad_3btn,\r
  read_pad_3btn,\r
  read_nothing\r
};\r
\r
static int padTHLatency[3]; // TODO this should be in the save file structures\r
\r
static NOINLINE u32 port_read(int i)\r
{\r
  u32 data_reg = PicoMem.ioports[i + 1];\r
  u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;\r
  u32 in, out;\r
\r
  out = data_reg & ctrl_reg;\r
\r
  // pull-ups: should be 0x7f, but Decap Attack has a bug where it temp.\r
  // disables output before doing TH-low read, so emulate RC filter for TH.\r
  // Decap Attack reportedly doesn't work on Nomad but works on must\r
  // other MD revisions (different pull-up strength?).\r
  u32 mask = 0x3f;\r
  if (CYCLES_GE(padTHLatency[i], SekCyclesDone()+100))\r
    padTHLatency[i] = SekCyclesDone(); // kludge to cope with cycle wrap\r
  if (CYCLES_GE(SekCyclesDone(), padTHLatency[i])) {\r
    mask |= 0x40;\r
    padTHLatency[i] = SekCyclesDone();\r
  }\r
  out |= mask & ~ctrl_reg;\r
\r
  in = port_readers[i](i, out);\r
\r
  return (in & ~ctrl_reg) | (data_reg & ctrl_reg);\r
}\r
\r
void PicoSetInputDevice(int port, enum input_device device)\r
{\r
  port_read_func *func;\r
\r
  if (port < 0 || port > 2)\r
    return;\r
\r
  if (port == 1 && port_readers[0] == read_pad_team)\r
    func = read_nothing;\r
\r
  else switch (device) {\r
  case PICO_INPUT_PAD_3BTN:\r
    func = read_pad_3btn;\r
    break;\r
\r
  case PICO_INPUT_PAD_6BTN:\r
    func = read_pad_6btn;\r
    break;\r
\r
  case PICO_INPUT_PAD_TEAM:\r
    func = read_pad_team;\r
    break;\r
\r
  case PICO_INPUT_PAD_4WAY:\r
    func = read_pad_4way;\r
    break;\r
\r
  default:\r
    func = read_nothing;\r
    break;\r
  }\r
\r
  port_readers[port] = func;\r
}\r
\r
NOINLINE u32 io_ports_read(u32 a)\r
{\r
  u32 d;\r
  a = (a>>1) & 0xf;\r
  switch (a) {\r
    case 0:  d = Pico.m.hardware; break; // Hardware value (Version register)\r
    case 1:  d = port_read(0); break;\r
    case 2:  d = port_read(1); break;\r
    case 3:  d = port_read(2); break;\r
    default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM\r
  }\r
  return d;\r
}\r
\r
NOINLINE void io_ports_write(u32 a, u32 d)\r
{\r
  a = (a>>1) & 0xf;\r
\r
  // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
  if (1 <= a && a <= 2)\r
  {\r
    Pico.m.padDelay[a - 1] = 0;\r
    if (port_readers[a - 1] == read_pad_team) {\r
      if (d & 0x40)\r
        Pico.m.padTHPhase[a - 1] = 0;\r
      else if ((d^PicoMem.ioports[a]) & 0x60)\r
        Pico.m.padTHPhase[a - 1]++;\r
    } else if (port_readers[0] == read_pad_4way) {\r
      if (a == 2 && ((PicoMem.ioports[a] ^ d) & 0x70))\r
        Pico.m.padTHPhase[0] = 0;\r
      if (a == 1 && !(PicoMem.ioports[a] & 0x40) && (d & 0x40))\r
        Pico.m.padTHPhase[0]++;\r
    } else if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))\r
      Pico.m.padTHPhase[a - 1]++;\r
  }\r
\r
  // after switching TH to input there's a latency before the pullup value is \r
  // read back as input (see Decap Attack, not in Samurai Showdown, 32x WWF Raw)\r
  if (4 <= a && a <= 5) {\r
    if ((PicoMem.ioports[a] & 0x40) && !(d & 0x40) && !(PicoMem.ioports[a - 3] & 0x40))\r
      // latency after switching to input and output was low\r
      padTHLatency[a - 4] = SekCyclesDone() + 25;\r
  }\r
\r
  // certain IO ports can be used as RAM\r
  PicoMem.ioports[a] = d;\r
}\r
\r
static int z80_cycles_from_68k(void)\r
{\r
  int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;\r
  return cycles_68k_to_z80(m68k_cnt);\r
}\r
\r
void NOINLINE ctl_write_z80busreq(u32 d)\r
{\r
  d&=1; d^=1;\r
  elprintf(EL_BUSREQ, "set_zrun: %i->%i [%u] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
  if (d ^ Pico.m.z80Run)\r
  {\r
    if (d)\r
    {\r
      Pico.t.z80c_aim = Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
      Pico.t.z80c_cnt += Pico.t.z80_busdelay >> 8;\r
      Pico.t.z80_busdelay &= 0xff;\r
    }\r
    else\r
    {\r
      if ((PicoIn.opt & POPT_EN_Z80) && !Pico.m.z80_reset) {\r
        // Z80 grants bus after the current M cycle, even within an insn\r
        // simulate this by accumulating the last insn overhang in busdelay\r
        unsigned granted;\r
        pprof_start(m68k);\r
        PicoSyncZ80(SekCyclesDone());\r
        pprof_end_sub(m68k);\r
        granted = Pico.t.z80c_aim + 6; // M cycle is 3-6 cycles \r
        Pico.t.z80_busdelay += (Pico.t.z80c_cnt - granted) << 8;\r
        Pico.t.z80c_cnt = granted;\r
      }\r
    }\r
    Pico.m.z80Run = d;\r
  }\r
}\r
\r
void NOINLINE ctl_write_z80reset(u32 d)\r
{\r
  d&=1; d^=1;\r
  elprintf(EL_BUSREQ, "set_zreset: %i->%i [%u] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
  if (d ^ Pico.m.z80_reset)\r
  {\r
    if (d)\r
    {\r
      if ((PicoIn.opt & POPT_EN_Z80) && Pico.m.z80Run) {\r
        pprof_start(m68k);\r
        PicoSyncZ80(SekCyclesDone());\r
        pprof_end_sub(m68k);\r
      }\r
      Pico.t.z80_busdelay &= 0xff; // also resets bus request\r
      YM2612ResetChip();\r
      timers_reset();\r
    }\r
    else\r
    {\r
      Pico.t.z80c_aim = Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
      z80_reset();\r
    }\r
    Pico.m.z80_reset = d;\r
  }\r
}\r
\r
static void psg_write_68k(u32 d)\r
{\r
  PsndDoPSG(z80_cycles_from_68k());\r
  SN76496Write(d);\r
}\r
\r
static void psg_write_z80(u32 d)\r
{\r
  PsndDoPSG(z80_cyclesDone());\r
  SN76496Write(d);\r
}\r
\r
// -----------------------------------------------------------------\r
\r
#ifndef _ASM_MEMORY_C\r
\r
// cart (save) RAM area (usually 0x200000 - ...)\r
static u32 PicoRead8_sram(u32 a)\r
{\r
  u32 d;\r
  if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))\r
  {\r
    if (Pico.sv.flags & SRF_EEPROM) {\r
      d = EEPROM_read();\r
      if (!(a & 1))\r
        d >>= 8;\r
      d &= 0xff;\r
    } else\r
      d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);\r
    elprintf(EL_SRAMIO, "sram r8  [%06x]   %02x @ %06x", a, d, SekPc);\r
    return d;\r
  }\r
\r
  // XXX: this is banking unfriendly\r
  if (a < Pico.romsize)\r
    return Pico.rom[MEM_BE2(a)];\r
  \r
  return m68k_unmapped_read8(a);\r
}\r
\r
static u32 PicoRead16_sram(u32 a)\r
{\r
  u32 d;\r
  if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))\r
  {\r
    if (Pico.sv.flags & SRF_EEPROM)\r
      d = EEPROM_read();\r
    else {\r
      u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
      d  = pm[0] << 8;\r
      d |= pm[1];\r
    }\r
    elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
    return d;\r
  }\r
\r
  if (a < Pico.romsize)\r
    return *(u16 *)(Pico.rom + a);\r
\r
  return m68k_unmapped_read16(a);\r
}\r
\r
#endif // _ASM_MEMORY_C\r
\r
static void PicoWrite8_sram(u32 a, u32 d)\r
{\r
  if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
    m68k_unmapped_write8(a, d);\r
    return;\r
  }\r
\r
  elprintf(EL_SRAMIO, "sram w8  [%06x]   %02x @ %06x", a, d & 0xff, SekPc);\r
  if (Pico.sv.flags & SRF_EEPROM)\r
  {\r
    EEPROM_write8(a, d);\r
  }\r
  else {\r
    u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
    if (*pm != (u8)d) {\r
      Pico.sv.changed = 1;\r
      *pm = (u8)d;\r
    }\r
  }\r
}\r
\r
static void PicoWrite16_sram(u32 a, u32 d)\r
{\r
  if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
    m68k_unmapped_write16(a, d);\r
    return;\r
  }\r
\r
  elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r
  if (Pico.sv.flags & SRF_EEPROM)\r
  {\r
    EEPROM_write16(d);\r
  }\r
  else {\r
    u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
    if (pm[0] != (u8)(d >> 8)) {\r
      Pico.sv.changed = 1;\r
      pm[0] = (u8)(d >> 8);\r
    }\r
    if (pm[1] != (u8)d) {\r
      Pico.sv.changed = 1;\r
      pm[1] = (u8)d;\r
    }\r
  }\r
}\r
\r
// z80 area (0xa00000 - 0xa0ffff)\r
// TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r
static u32 PicoRead8_z80(u32 a)\r
{\r
  u32 d;\r
  if ((Pico.m.z80Run | Pico.m.z80_reset | (z80_cycles_from_68k() < Pico.t.z80c_cnt)) &&\r
      !(PicoIn.quirks & PQUIRK_NO_Z80_BUS_LOCK)) {\r
    elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r
    return (u8)PicoRead16_floating(a);\r
  }\r
  SekCyclesBurnRun(1);\r
\r
  if ((a & 0x4000) == 0x0000) {\r
    d = PicoMem.zram[a & 0x1fff];\r
  } else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
    d = ym2612_read_local_68k(); \r
  else {\r
    elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
    d = (u8)PicoRead16_floating(a);\r
  }\r
  return d;\r
}\r
\r
static u32 PicoRead16_z80(u32 a)\r
{\r
  u32 d = PicoRead8_z80(a);\r
  return d | (d << 8);\r
}\r
\r
static void PicoWrite8_z80(u32 a, u32 d)\r
{\r
  if ((Pico.m.z80Run | Pico.m.z80_reset) && !(PicoIn.quirks & PQUIRK_NO_Z80_BUS_LOCK)) {\r
    // verified on real hw\r
    elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
    return;\r
  }\r
  SekCyclesBurnRun(1);\r
\r
  if ((a & 0x4000) == 0x0000) { // z80 RAM\r
    PicoMem.zram[a & 0x1fff] = (u8)d;\r
    return;\r
  }\r
  if ((a & 0x6000) == 0x4000) { // FM Sound\r
    if (PicoIn.opt & POPT_EN_FM)\r
      ym2612_write_local(a & 3, d & 0xff, 0);\r
    return;\r
  }\r
  // TODO: probably other VDP access too? Maybe more mirrors?\r
  if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r
    psg_write_68k(d);\r
    return;\r
  }\r
  if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
  {\r
    Pico.m.z80_bank68k >>= 1;\r
    Pico.m.z80_bank68k |= d << 8;\r
    Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
    elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
    return;\r
  }\r
  elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
}\r
\r
static void PicoWrite16_z80(u32 a, u32 d)\r
{\r
  // for RAM, only most significant byte is sent\r
  // TODO: verify remaining accesses\r
  PicoWrite8_z80(a, d >> 8);\r
}\r
\r
#ifndef _ASM_MEMORY_C\r
\r
// IO/control area (0xa10000 - 0xa1ffff)\r
u32 PicoRead8_io(u32 a)\r
{\r
  u32 d;\r
\r
  if ((a & 0xffe0) == 0x0000) { // I/O ports\r
    d = io_ports_read(a);\r
    goto end;\r
  }\r
\r
  d = PicoRead16_floating(a);\r
\r
  if ((a & 0xfc00) == 0x1000) {\r
    if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
      // bit8 seems to be readable in this range\r
      if (!(a & 1)) {\r
        d &= ~0x01;\r
        // Z80 ahead of 68K only if in BUSREQ, BUSACK only after 68K reached Z80\r
        d |= (z80_cycles_from_68k() < Pico.t.z80c_cnt);\r
        d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
        elprintf(EL_BUSREQ, "get_zrun: %02x [%u] @%06x", d, SekCyclesDone(), SekPc);\r
      }\r
    }\r
    goto end;\r
  }\r
\r
  d = PicoRead8_32x(a);\r
\r
end:\r
  return d;\r
}\r
\r
u32 PicoRead16_io(u32 a)\r
{\r
  u32 d;\r
\r
  if ((a & 0xffe0) == 0x0000) { // I/O ports\r
    d = io_ports_read(a);\r
    d |= d << 8;\r
    goto end;\r
  }\r
\r
  d = PicoRead16_floating(a);\r
\r
  // bit8 seems to be readable in this range\r
  if ((a & 0xfc00) == 0x1000) {\r
    if ((a & 0xff00) == 0x1100) { // z80 busreq\r
      d &= ~0x0100;\r
      d |= (z80_cycles_from_68k() < Pico.t.z80c_cnt) << 8;\r
      d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
      elprintf(EL_BUSREQ, "get_zrun: %04x [%u] @%06x", d, SekCyclesDone(), SekPc);\r
    }\r
    goto end;\r
  }\r
\r
  d = PicoRead16_32x(a);\r
\r
end:\r
  return d;\r
}\r
\r
void PicoWrite8_io(u32 a, u32 d)\r
{\r
  if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r
    io_ports_write(a, d);\r
    return;\r
  }\r
  if ((a & 0xff01) == 0x1100) { // z80 busreq\r
    ctl_write_z80busreq(d);\r
    return;\r
  }\r
  if ((a & 0xff01) == 0x1200) { // z80 reset\r
    ctl_write_z80reset(d);\r
    return;\r
  }\r
  if (a == 0xa130f1) { // sram access register\r
    elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
    Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
    Pico.m.sram_reg |= (u8)(d & 3);\r
    return;\r
  }\r
  PicoWrite8_32x(a, d);\r
}\r
\r
void PicoWrite16_io(u32 a, u32 d)\r
{\r
  if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r
    io_ports_write(a, d);\r
    return;\r
  }\r
  if ((a & 0xff00) == 0x1100) { // z80 busreq\r
    ctl_write_z80busreq(d >> 8);\r
    return;\r
  }\r
  if ((a & 0xff00) == 0x1200) { // z80 reset\r
    ctl_write_z80reset(d >> 8);\r
    return;\r
  }\r
  if (a == 0xa130f0) { // sram access register\r
    elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
    Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);\r
    Pico.m.sram_reg |= (u8)(d & 3);\r
    return;\r
  }\r
  PicoWrite16_32x(a, d);\r
}\r
\r
#endif // _ASM_MEMORY_C\r
\r
// VDP area (0xc00000 - 0xdfffff)\r
// TODO: verify if lower byte goes to PSG on word writes\r
u32 PicoRead8_vdp(u32 a)\r
{\r
  u32 d;\r
  if ((a & 0x00f0) == 0x0000) {\r
    switch (a & 0x0d)\r
    {\r
      case 0x00: d = PicoVideoRead8DataH(0); break;\r
      case 0x01: d = PicoVideoRead8DataL(0); break;\r
      case 0x04: d = PicoVideoRead8CtlH(0); break;\r
      case 0x05: d = PicoVideoRead8CtlL(0); break;\r
      case 0x08:\r
      case 0x0c: d = PicoVideoRead8HV_H(0); break;\r
      case 0x09:\r
      case 0x0d: d = PicoVideoRead8HV_L(0); break;\r
      default:   d = (u8)PicoRead16_floating(a); break;\r
    }\r
  } else {\r
    elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
    d = (u8)PicoRead16_floating(a);\r
  }\r
  return d;\r
}\r
\r
static u32 PicoRead16_vdp(u32 a)\r
{\r
  if ((a & 0x00e0) == 0x0000)\r
    return PicoVideoRead(a);\r
\r
  elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
  return 0;\r
}\r
\r
static void PicoWrite8_vdp(u32 a, u32 d)\r
{\r
  if ((a & 0x00f9) == 0x0011) { // PSG Sound\r
    psg_write_68k(d);\r
    return;\r
  }\r
  if ((a & 0x00e0) == 0x0000) {\r
    d &= 0xff;\r
    PicoVideoWrite(a, d | (d << 8));\r
    return;\r
  }\r
\r
  elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
}\r
\r
static void PicoWrite16_vdp(u32 a, u32 d)\r
{\r
  if ((a & 0x00f9) == 0x0010) { // PSG Sound\r
    psg_write_68k(d);\r
    return;\r
  }\r
  if ((a & 0x00e0) == 0x0000) {\r
    PicoVideoWrite(a, d);\r
    return;\r
  }\r
\r
  elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
}\r
\r
// -----------------------------------------------------------------\r
\r
#ifdef EMU_M68K\r
static void m68k_mem_setup(void);\r
#endif\r
\r
PICO_INTERNAL void PicoMemSetup(void)\r
{\r
  int mask, rs, sstart, a;\r
\r
  // setup the memory map\r
  cpu68k_map_set(m68k_read8_map,   0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
  cpu68k_map_set(m68k_read16_map,  0x000000, 0xffffff, m68k_unmapped_read16, 1);\r
  cpu68k_map_set(m68k_write8_map,  0x000000, 0xffffff, m68k_unmapped_write8, 1);\r
  cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r
\r
  // ROM\r
  // align to bank size. We know ROM loader allocated enough for this\r
  mask = (1 << M68K_MEM_SHIFT) - 1;\r
  rs = (Pico.romsize + mask) & ~mask;\r
  if (rs > 0xa00000) rs = 0xa00000; // max cartridge area\r
  cpu68k_map_set(m68k_read8_map,  0x000000, rs - 1, Pico.rom, 0);\r
  cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
\r
  // Common case of on-cart (save) RAM, usually at 0x200000-...\r
  if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {\r
    sstart = Pico.sv.start & ~mask;\r
    rs = Pico.sv.end - sstart;\r
    rs = (rs + mask) & ~mask;\r
    if (sstart + rs >= 0x1000000)\r
      rs = 0x1000000 - sstart;\r
    cpu68k_map_set(m68k_read8_map,   sstart, sstart + rs - 1, PicoRead8_sram, 1);\r
    cpu68k_map_set(m68k_read16_map,  sstart, sstart + rs - 1, PicoRead16_sram, 1);\r
    cpu68k_map_set(m68k_write8_map,  sstart, sstart + rs - 1, PicoWrite8_sram, 1);\r
    cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);\r
  }\r
\r
  // Z80 region\r
  cpu68k_map_set(m68k_read8_map,   0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r
  cpu68k_map_set(m68k_read16_map,  0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r
  cpu68k_map_set(m68k_write8_map,  0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r
  cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r
\r
  // IO/control region\r
  cpu68k_map_set(m68k_read8_map,   0xa10000, 0xa1ffff, PicoRead8_io, 1);\r
  cpu68k_map_set(m68k_read16_map,  0xa10000, 0xa1ffff, PicoRead16_io, 1);\r
  cpu68k_map_set(m68k_write8_map,  0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r
  cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r
\r
  // VDP region\r
  for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r
    if ((a & 0xe700e0) != 0xc00000)\r
      continue;\r
    cpu68k_map_set(m68k_read8_map,   a, a + 0xffff, PicoRead8_vdp, 1);\r
    cpu68k_map_set(m68k_read16_map,  a, a + 0xffff, PicoRead16_vdp, 1);\r
    cpu68k_map_set(m68k_write8_map,  a, a + 0xffff, PicoWrite8_vdp, 1);\r
    cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r
  }\r
\r
  // RAM and it's mirrors\r
  for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
    cpu68k_map_set(m68k_read8_map,   a, a + 0xffff, PicoMem.ram, 0);\r
    cpu68k_map_set(m68k_read16_map,  a, a + 0xffff, PicoMem.ram, 0);\r
    cpu68k_map_set(m68k_write8_map,  a, a + 0xffff, PicoMem.ram, 0);\r
    cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);\r
  }\r
\r
  // Setup memory callbacks:\r
#ifdef EMU_C68K\r
  PicoCpuCM68k.read8  = (void *)m68k_read8_map;\r
  PicoCpuCM68k.read16 = (void *)m68k_read16_map;\r
  PicoCpuCM68k.read32 = (void *)m68k_read16_map;\r
  PicoCpuCM68k.write8  = (void *)m68k_write8_map;\r
  PicoCpuCM68k.write16 = (void *)m68k_write16_map;\r
  PicoCpuCM68k.write32 = (void *)m68k_write16_map;\r
  PicoCpuCM68k.checkpc = NULL; /* unused */\r
  PicoCpuCM68k.fetch8  = NULL;\r
  PicoCpuCM68k.fetch16 = NULL;\r
  PicoCpuCM68k.fetch32 = NULL;\r
#endif\r
#ifdef EMU_F68K\r
  PicoCpuFM68k.read_byte  = (void *)m68k_read8;\r
  PicoCpuFM68k.read_word  = (void *)m68k_read16;\r
  PicoCpuFM68k.read_long  = (void *)m68k_read32;\r
  PicoCpuFM68k.write_byte = (void *)m68k_write8;\r
  PicoCpuFM68k.write_word = (void *)m68k_write16;\r
  PicoCpuFM68k.write_long = (void *)m68k_write32;\r
#endif\r
#ifdef EMU_M68K\r
  m68k_mem_setup();\r
#endif\r
\r
  z80_mem_setup();\r
}\r
\r
#ifdef EMU_M68K\r
unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;\r
unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;\r
void (*pm68k_write_memory_8) (unsigned int address, unsigned char  value) = NULL;\r
void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;\r
void (*pm68k_write_memory_32)(unsigned int address, unsigned int   value) = NULL;\r
\r
/* it appears that Musashi doesn't always mask the unused bits */\r
unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }\r
unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }\r
unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }\r
void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }\r
void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }\r
void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }\r
\r
static void m68k_mem_setup(void)\r
{\r
  pm68k_read_memory_8  = m68k_read8;\r
  pm68k_read_memory_16 = m68k_read16;\r
  pm68k_read_memory_32 = m68k_read32;\r
  pm68k_write_memory_8  = m68k_write8;\r
  pm68k_write_memory_16 = m68k_write16;\r
  pm68k_write_memory_32 = m68k_write32;\r
}\r
#endif // EMU_M68K\r
\r
\r
// -----------------------------------------------------------------\r
\r
static int get_scanline(int is_from_z80)\r
{\r
  if (is_from_z80) {\r
    // ugh... compute by dividing cycles since frame start by cycles per line\r
    // need some fractional resolution here, else there may be an extra line\r
    int cycles_line = cycles_68k_to_z80((unsigned)(488.5*256))+1; // cycles per line, Q8\r
    int cycles_z80 = (z80_cyclesLeft<0 ? Pico.t.z80c_aim:z80_cyclesDone())<<8;\r
    int cycles = cycles_line * Pico.t.z80_scanline;\r
    // approximation by multiplying with inverse\r
    if (cycles_z80 - cycles >= 4*cycles_line) {\r
      // compute 1/cycles_line, storing the result to avoid future dividing\r
      static int cycles_line_o, cycles_line_i;\r
      if (cycles_line_o != cycles_line)\r
        { cycles_line_o = cycles_line, cycles_line_i = (1<<22) / cycles_line; }\r
      // compute lines = diff/cycles_line = diff*(1/cycles_line)\r
      int lines = ((cycles_z80 - cycles) * cycles_line_i) >> 22;\r
      Pico.t.z80_scanline += lines, cycles += cycles_line * lines;\r
    }\r
    // handle any rounding leftover\r
    while (cycles_z80 - cycles >= cycles_line)\r
      Pico.t.z80_scanline ++, cycles += cycles_line;\r
    return Pico.t.z80_scanline;\r
  }\r
\r
  return Pico.m.scanline;\r
}\r
\r
#define ym2612_update_status(xcycles) \\r
  ym2612.OPN.ST.status &= ~0x80; \\r
  ym2612.OPN.ST.status |= (xcycles < Pico.t.ym2612_busy) * 0x80; \\r
  if (xcycles >= Pico.t.timer_a_next_oflow) \\r
    ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \\r
  if (xcycles >= Pico.t.timer_b_next_oflow) \\r
    ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
\r
/* probably should not be in this file, but it's near related code here */\r
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)\r
{\r
  int xcycles = z80_cycles << 8;\r
\r
  // update timer status\r
  ym2612_update_status(xcycles);\r
\r
  // update timer a\r
  if (mode_old & 1)\r
    while (xcycles >= Pico.t.timer_a_next_oflow)\r
      Pico.t.timer_a_next_oflow += Pico.t.timer_a_step;\r
\r
  // turning on/off\r
  if ((mode_old ^ mode_new) & 1)\r
  {\r
    if (mode_old & 1)\r
      Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;\r
    else {\r
      /* The internal tick of the YM2612 takes 144 clock cycles (with clock\r
       * being OSC/7), or 67.2 z80 cycles. Timers are run once each tick.\r
       * Starting a timer takes place at the next tick, so xcycles needs to be\r
       * rounded up to that: t = next tick# = (xcycles / TICK_ZCYCLES) + 1\r
       */\r
      unsigned t = ((xcycles * (((1LL<<32)/TIMER_A_TICK_ZCYCLES)+1))>>32) + 1;\r
      Pico.t.timer_a_next_oflow = t*TIMER_A_TICK_ZCYCLES + Pico.t.timer_a_step;\r
    }\r
  }\r
\r
  if (mode_new & 1)\r
    elprintf(EL_YMTIMER, "timer a upd to %i @ %i", Pico.t.timer_a_next_oflow>>8, z80_cycles);\r
\r
  // update timer b\r
  if (mode_old & 2)\r
    while (xcycles >= Pico.t.timer_b_next_oflow)\r
      Pico.t.timer_b_next_oflow += Pico.t.timer_b_step;\r
\r
  // turning on/off\r
  if ((mode_old ^ mode_new) & 2)\r
  {\r
    if (mode_old & 2)\r
      Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;\r
    else {\r
      /* timer b has a divider of 16 which runs in its own counter. It is not\r
       * reset by loading timer b. The first run of timer b after loading is\r
       * therefore shorter by up to 15 ticks.\r
       */\r
      unsigned t = ((xcycles * (((1LL<<32)/TIMER_A_TICK_ZCYCLES)+1))>>32) + 1;\r
      int step = Pico.t.timer_b_step - TIMER_A_TICK_ZCYCLES*(t&15);\r
      Pico.t.timer_b_next_oflow = t*TIMER_A_TICK_ZCYCLES + step;\r
    }\r
  }\r
\r
  if (mode_new & 2)\r
    elprintf(EL_YMTIMER, "timer b upd to %i @ %i", Pico.t.timer_b_next_oflow>>8, z80_cycles);\r
}\r
\r
// ym2612 DAC and timer I/O handlers for z80\r
static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
{\r
  int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
  int addr;\r
\r
  a &= 3;\r
  switch (a)\r
  {\r
    case 0: /* address port 0 */\r
    case 2: /* address port 1 */\r
      ym2612.OPN.ST.address = d;\r
      ym2612.addr_A1 = (a & 2) >> 1;\r
#ifdef __GP2X__\r
      if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);\r
#endif\r
      return 0;\r
\r
    case 1: /* data port 0    */\r
    case 3: /* data port 1    */\r
      addr = ym2612.OPN.ST.address | ((int)ym2612.addr_A1 << 8);\r
      ym2612.REGS[addr] = d;\r
\r
      // the busy flag in the YM2612 status is actually a 32 cycle timer\r
      // (89.6 Z80 cycles), triggered by any write to the data port.\r
      Pico.t.ym2612_busy = (cycles << 8) + YMBUSY_ZCYCLES; // Q8 for convenience\r
\r
      switch (addr)\r
      {\r
        case 0x24: // timer A High 8\r
        case 0x25: { // timer A Low 2\r
          int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))\r
                                     : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));\r
          if (ym2612.OPN.ST.TA != TAnew)\r
          {\r
            ym2612_sync_timers(cycles, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
            //elprintf(EL_STATUS, "timer a set %i", TAnew);\r
            ym2612.OPN.ST.TA = TAnew;\r
            //ym2612.OPN.ST.TAC = (1024-TAnew)*18;\r
            //ym2612.OPN.ST.TAT = 0;\r
            Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
            elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, Pico.t.timer_a_next_oflow>>8);\r
          }\r
          return 0;\r
        }\r
        case 0x26: // timer B\r
          if (ym2612.OPN.ST.TB != d) {\r
            ym2612_sync_timers(cycles, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
            //elprintf(EL_STATUS, "timer b set %i", d);\r
            ym2612.OPN.ST.TB = d;\r
            //ym2612.OPN.ST.TBC = (256-d) * 288;\r
            //ym2612.OPN.ST.TBT  = 0;\r
            Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d);\r
            elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, Pico.t.timer_b_next_oflow>>8);\r
          }\r
          return 0;\r
        case 0x27: { /* mode, timer control */\r
          int old_mode = ym2612.OPN.ST.mode;\r
\r
          elprintf(EL_YMTIMER, "st mode %02x", d);\r
          ym2612_sync_timers(cycles, old_mode, d);\r
\r
          ym2612.OPN.ST.mode = d;\r
\r
          /* reset Timer a flag */\r
          if (d & 0x10)\r
            ym2612.OPN.ST.status &= ~1;\r
\r
          /* reset Timer b flag */\r
          if (d & 0x20)\r
            ym2612.OPN.ST.status &= ~2;\r
\r
          if ((d ^ old_mode) & 0xc0) {\r
#ifdef __GP2X__\r
            if (PicoIn.opt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
#endif\r
            PsndDoFM(cycles);\r
            return 1;\r
          }\r
          return 0;\r
        }\r
        case 0x2a: { /* DAC data */\r
          //elprintf(EL_STATUS, "%03i dac w %08x z80 %i", cycles, d, is_from_z80);\r
          if (ym2612.dacen)\r
            PsndDoDAC(cycles);\r
          ym2612.dacout = ((int)d - 0x80) << 6;\r
          return 0;\r
        }\r
        case 0x2b: { /* DAC Sel  (YM2612) */\r
          ym2612.dacen = d & 0x80;\r
#ifdef __GP2X__\r
          if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, get_scanline(is_from_z80));\r
#endif\r
          return 0;\r
        }\r
      }\r
      break;\r
  }\r
\r
#ifdef __GP2X__\r
  if (PicoIn.opt & POPT_EXT_FM)\r
    return YM2612Write_940(a, d, get_scanline(is_from_z80));\r
#endif\r
  PsndDoFM(cycles);\r
  return YM2612Write_(a, d);\r
}\r
\r
\r
static u32 ym2612_read_local_z80(void)\r
{\r
  int xcycles = z80_cyclesDone() << 8;\r
\r
  ym2612_update_status(xcycles);\r
\r
  elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i",\r
    ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,\r
    Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);\r
  return ym2612.OPN.ST.status;\r
}\r
\r
static u32 ym2612_read_local_68k(void)\r
{\r
  int xcycles = z80_cycles_from_68k() << 8;\r
\r
  ym2612_update_status(xcycles);\r
\r
  elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i",\r
    ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,\r
    Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);\r
  return ym2612.OPN.ST.status;\r
}\r
\r
void ym2612_pack_state(void)\r
{\r
  // timers are saved as tick counts, in 16.16 int format\r
  int tac, tat = 0, tbc, tbt = 0, busy = 0;\r
  tac = 1024 - ym2612.OPN.ST.TA;\r
  tbc = 256  - ym2612.OPN.ST.TB;\r
  if (Pico.t.ym2612_busy > 0)\r
    busy = cycles_z80_to_68k(Pico.t.ym2612_busy);\r
  if (Pico.t.timer_a_next_oflow != TIMER_NO_OFLOW)\r
    tat = (int)((double)(Pico.t.timer_a_step - Pico.t.timer_a_next_oflow)\r
          / (double)Pico.t.timer_a_step * tac * 65536);\r
  if (Pico.t.timer_b_next_oflow != TIMER_NO_OFLOW)\r
    tbt = (int)((double)(Pico.t.timer_b_step - Pico.t.timer_b_next_oflow)\r
          / (double)Pico.t.timer_b_step * tbc * 65536);\r
  elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);\r
  elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);\r
\r
#ifdef __GP2X__\r
  if (PicoIn.opt & POPT_EXT_FM)\r
    YM2612PicoStateSave2_940(tat, tbt);\r
  else\r
#endif\r
    YM2612PicoStateSave2(tat, tbt, busy);\r
}\r
\r
void ym2612_unpack_state(void)\r
{\r
  int i, ret, tac, tat, tbc, tbt, busy = 0;\r
  YM2612PicoStateLoad();\r
\r
  // feed all the registers and update internal state\r
  for (i = 0x20; i < 0xA0; i++) {\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
  }\r
  for (i = 0x30; i < 0xA0; i++) {\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
  }\r
  for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
  }\r
  for (i = 0xB0; i < 0xB8; i++) {\r
    ym2612_write_local(0, i, 0);\r
    ym2612_write_local(1, ym2612.REGS[i], 0);\r
    ym2612_write_local(2, i, 0);\r
    ym2612_write_local(3, ym2612.REGS[i|0x100], 0);\r
  }\r
\r
#ifdef __GP2X__\r
  if (PicoIn.opt & POPT_EXT_FM)\r
    ret = YM2612PicoStateLoad2_940(&tat, &tbt);\r
  else\r
#endif\r
    ret = YM2612PicoStateLoad2(&tat, &tbt, &busy);\r
  if (ret != 0) {\r
    elprintf(EL_STATUS, "old ym2612 state");\r
    return; // no saved timers\r
  }\r
\r
  Pico.t.ym2612_busy = cycles_68k_to_z80(busy);\r
  tac = (1024 - ym2612.OPN.ST.TA) << 16;\r
  tbc = (256  - ym2612.OPN.ST.TB) << 16;\r
  if (ym2612.OPN.ST.mode & 1)\r
    Pico.t.timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * Pico.t.timer_a_step);\r
  else\r
    Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;\r
  if (ym2612.OPN.ST.mode & 2)\r
    Pico.t.timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * Pico.t.timer_b_step);\r
  else\r
    Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;\r
  elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, Pico.t.timer_a_next_oflow >> 8);\r
  elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, Pico.t.timer_b_next_oflow >> 8);\r
}\r
\r
#if defined(NO_32X) && defined(_ASM_MEMORY_C)\r
// referenced by asm code\r
u32 PicoRead8_32x(u32 a) { return 0; }\r
u32 PicoRead16_32x(u32 a) { return 0; }\r
void PicoWrite8_32x(u32 a, u32 d) {}\r
void PicoWrite16_32x(u32 a, u32 d) {}\r
#endif\r
\r
// -----------------------------------------------------------------\r
//                        z80 memhandlers\r
\r
static void access_68k_bus(int delay) // bus delay as Q8\r
{\r
  // TODO: if the 68K is in DMA wait, Z80 has to wait until DMA ends\r
\r
  // 68k bus access delay for z80. The fractional part needs to be accumulated\r
  // until an additional cycle is full. That is then added to the integer part.\r
  Pico.t.z80_busdelay += (delay&0xff); // accumulate\r
  z80_subCLeft((delay>>8) + (Pico.t.z80_busdelay>>8));\r
  Pico.t.z80_busdelay &= 0xff; // leftover cycle fraction\r
  // don't use SekCyclesBurn() here since the Z80 doesn't run in cycle lock to\r
  // the 68K. Count the stolen cycles to be accounted later in the 68k CPU runs\r
  Pico.t.z80_buscycles += 8; // TODO <=8.4 for Rick 2, but >=8.9 for misc_test\r
}\r
\r
static unsigned char z80_md_vdp_read(unsigned short a)\r
{\r
  if ((a & 0xff00) == 0x7f00) {\r
    // 68k bus access delay=3.3 per kabuto, for notaz picotest 2.42<delay<2.57?\r
    access_68k_bus(0x280); // Q8, picotest: 0x26d(>2.42) - 0x292(<2.57)\r
\r
    switch (a & 0x0d)\r
    {\r
      case 0x00: return PicoVideoRead8DataH(1);\r
      case 0x01: return PicoVideoRead8DataL(1);\r
      case 0x04: return PicoVideoRead8CtlH(1);\r
      case 0x05: return PicoVideoRead8CtlL(1);\r
      case 0x08:\r
      case 0x0c: return PicoVideoGetV(get_scanline(1), 1);\r
      case 0x09:\r
      case 0x0d: return Pico.m.rotate++;\r
    }\r
  }\r
\r
  elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
  return 0xff;\r
}\r
\r
static unsigned char z80_md_bank_read(unsigned short a)\r
{\r
  unsigned int addr68k;\r
  unsigned char ret = 0xff;\r
\r
  // 68k bus access delay=3.3 per kabuto, but for notaz picotest 3.02<delay<3.32\r
  access_68k_bus(0x340); // Q8, picotest: 0x306(>3.02)-0x351(<3.32)\r
\r
  addr68k = Pico.m.z80_bank68k << 15;\r
  addr68k |= a & 0x7fff;\r
\r
  if (addr68k < 0xe00000) // can't read from 68K RAM\r
    ret = m68k_read8(addr68k);\r
\r
  elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
  return ret;\r
}\r
\r
static void z80_md_ym2612_write(unsigned int a, unsigned char data)\r
{\r
  if (PicoIn.opt & POPT_EN_FM)\r
    ym2612_write_local(a, data, 1);\r
}\r
\r
static void z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
{\r
  if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
  {\r
    psg_write_z80(data);\r
    return;\r
  }\r
  // at least VDP data writes hang my machine\r
\r
  if ((a>>8) == 0x60)\r
  {\r
    Pico.m.z80_bank68k >>= 1;\r
    Pico.m.z80_bank68k |= data << 8;\r
    Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
    return;\r
  }\r
\r
  elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
static void z80_md_bank_write(unsigned int a, unsigned char data)\r
{\r
  unsigned int addr68k;\r
\r
  // 68k bus access delay=3.3 per kabuto, but for notaz picotest 3.02<delay<3.32\r
  access_68k_bus(0x340); // Q8, picotest: 0x306(>3.02)-0x351(<3.32)\r
\r
  addr68k = Pico.m.z80_bank68k << 15;\r
  addr68k += a & 0x7fff;\r
\r
  elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
  m68k_write8(addr68k, data);\r
}\r
\r
// -----------------------------------------------------------------\r
\r
static unsigned char z80_md_in(unsigned short p)\r
{\r
  elprintf(EL_ANOMALY, "Z80 port %04x read", p);\r
  return 0xff;\r
}\r
\r
static void z80_md_out(unsigned short p, unsigned char d)\r
{\r
  elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
}\r
\r
static void z80_mem_setup(void)\r
{\r
  z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);\r
  z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);\r
  z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
  z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
  z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
\r
  z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);\r
  z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);\r
  z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
  z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
  z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
\r
#ifdef _USE_DRZ80\r
  drZ80.z80_in = z80_md_in;\r
  drZ80.z80_out = z80_md_out;\r
#endif\r
#ifdef _USE_CZ80\r
  Cz80_Set_INPort(&CZ80, z80_md_in);\r
  Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
#endif\r
}\r
\r
// vim:shiftwidth=2:ts=2:expandtab\r