drc: merge Ari64's patch: 05_dont_write_r0
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
1e973cb0 182#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 183
184 /* stubs */
185#define CC_STUB 1
186#define FP_STUB 2
187#define LOADB_STUB 3
188#define LOADH_STUB 4
189#define LOADW_STUB 5
190#define LOADD_STUB 6
191#define LOADBU_STUB 7
192#define LOADHU_STUB 8
193#define STOREB_STUB 9
194#define STOREH_STUB 10
195#define STOREW_STUB 11
196#define STORED_STUB 12
197#define STORELR_STUB 13
198#define INVCODE_STUB 14
199
200 /* branch codes */
201#define TAKEN 1
202#define NOTTAKEN 2
203#define NULLDS 3
204
205// asm linkage
206int new_recompile_block(int addr);
207void *get_addr_ht(u_int vaddr);
208void invalidate_block(u_int block);
209void invalidate_addr(u_int addr);
210void remove_hash(int vaddr);
211void jump_vaddr();
212void dyna_linker();
213void dyna_linker_ds();
214void verify_code();
215void verify_code_vm();
216void verify_code_ds();
217void cc_interrupt();
218void fp_exception();
219void fp_exception_ds();
220void jump_syscall();
7139f3c8 221void jump_syscall_hle();
57871462 222void jump_eret();
7139f3c8 223void jump_hlecall();
1e973cb0 224void jump_intcall();
7139f3c8 225void new_dyna_leave();
57871462 226
227// TLB
228void TLBWI_new();
229void TLBWR_new();
230void read_nomem_new();
231void read_nomemb_new();
232void read_nomemh_new();
233void read_nomemd_new();
234void write_nomem_new();
235void write_nomemb_new();
236void write_nomemh_new();
237void write_nomemd_new();
238void write_rdram_new();
239void write_rdramb_new();
240void write_rdramh_new();
241void write_rdramd_new();
242extern u_int memory_map[1048576];
243
244// Needed by assembler
245void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248void load_all_regs(signed char i_regmap[]);
249void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250void load_regs_entry(int t);
251void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253int tracedebug=0;
254
255//#define DEBUG_CYCLE_COUNT 1
256
257void nullf() {}
258//#define assem_debug printf
259//#define inv_debug printf
260#define assem_debug nullf
261#define inv_debug nullf
262
94d23bb9 263static void tlb_hacks()
57871462 264{
94d23bb9 265#ifndef DISABLE_TLB
57871462 266 // Goldeneye hack
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268 {
269 u_int addr;
270 int n;
271 switch (ROM_HEADER->Country_code&0xFF)
272 {
273 case 0x45: // U
274 addr=0x34b30;
275 break;
276 case 0x4A: // J
277 addr=0x34b70;
278 break;
279 case 0x50: // E
280 addr=0x329f0;
281 break;
282 default:
283 // Unknown country code
284 addr=0;
285 break;
286 }
287 u_int rom_addr=(u_int)rom;
288 #ifdef ROM_COPY
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
299 }
300 #endif
301 if(addr) {
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304 }
305 }
306 }
94d23bb9 307#endif
57871462 308}
309
94d23bb9 310static u_int get_page(u_int vaddr)
57871462 311{
0ce47d46 312#ifndef PCSX
57871462 313 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 314#else
315 u_int page=vaddr&~0xe0000000;
316 if (page < 0x1000000)
317 page &= ~0x0e00000; // RAM mirrors
318 page>>=12;
319#endif
94d23bb9 320#ifndef DISABLE_TLB
57871462 321 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 322#endif
57871462 323 if(page>2048) page=2048+(page&2047);
94d23bb9 324 return page;
325}
326
327static u_int get_vpage(u_int vaddr)
328{
329 u_int vpage=(vaddr^0x80000000)>>12;
330#ifndef DISABLE_TLB
57871462 331 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 332#endif
57871462 333 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 334 return vpage;
335}
336
337// Get address from virtual address
338// This is called from the recompiled JR/JALR instructions
339void *get_addr(u_int vaddr)
340{
341 u_int page=get_page(vaddr);
342 u_int vpage=get_vpage(vaddr);
57871462 343 struct ll_entry *head;
344 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
345 head=jump_in[page];
346 while(head!=NULL) {
347 if(head->vaddr==vaddr&&head->reg32==0) {
348 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
349 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
350 ht_bin[3]=ht_bin[1];
351 ht_bin[2]=ht_bin[0];
352 ht_bin[1]=(int)head->addr;
353 ht_bin[0]=vaddr;
354 return head->addr;
355 }
356 head=head->next;
357 }
358 head=jump_dirty[vpage];
359 while(head!=NULL) {
360 if(head->vaddr==vaddr&&head->reg32==0) {
361 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
362 // Don't restore blocks which are about to expire from the cache
363 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
364 if(verify_dirty(head->addr)) {
365 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
366 invalid_code[vaddr>>12]=0;
367 memory_map[vaddr>>12]|=0x40000000;
368 if(vpage<2048) {
94d23bb9 369#ifndef DISABLE_TLB
57871462 370 if(tlb_LUT_r[vaddr>>12]) {
371 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
372 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
373 }
94d23bb9 374#endif
57871462 375 restore_candidate[vpage>>3]|=1<<(vpage&7);
376 }
377 else restore_candidate[page>>3]|=1<<(page&7);
378 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
379 if(ht_bin[0]==vaddr) {
380 ht_bin[1]=(int)head->addr; // Replace existing entry
381 }
382 else
383 {
384 ht_bin[3]=ht_bin[1];
385 ht_bin[2]=ht_bin[0];
386 ht_bin[1]=(int)head->addr;
387 ht_bin[0]=vaddr;
388 }
389 return head->addr;
390 }
391 }
392 head=head->next;
393 }
394 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
395 int r=new_recompile_block(vaddr);
396 if(r==0) return get_addr(vaddr);
397 // Execute in unmapped page, generate pagefault execption
398 Status|=2;
399 Cause=(vaddr<<31)|0x8;
400 EPC=(vaddr&1)?vaddr-5:vaddr;
401 BadVAddr=(vaddr&~1);
402 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
403 EntryHi=BadVAddr&0xFFFFE000;
404 return get_addr_ht(0x80000000);
405}
406// Look up address in hash table first
407void *get_addr_ht(u_int vaddr)
408{
409 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
410 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
411 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
412 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
413 return get_addr(vaddr);
414}
415
416void *get_addr_32(u_int vaddr,u_int flags)
417{
7139f3c8 418#ifdef FORCE32
419 return get_addr(vaddr);
560e4a12 420#else
57871462 421 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 425 u_int page=get_page(vaddr);
426 u_int vpage=get_vpage(vaddr);
57871462 427 struct ll_entry *head;
428 head=jump_in[page];
429 while(head!=NULL) {
430 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
431 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
432 if(head->reg32==0) {
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434 if(ht_bin[0]==-1) {
435 ht_bin[1]=(int)head->addr;
436 ht_bin[0]=vaddr;
437 }else if(ht_bin[2]==-1) {
438 ht_bin[3]=(int)head->addr;
439 ht_bin[2]=vaddr;
440 }
441 //ht_bin[3]=ht_bin[1];
442 //ht_bin[2]=ht_bin[0];
443 //ht_bin[1]=(int)head->addr;
444 //ht_bin[0]=vaddr;
445 }
446 return head->addr;
447 }
448 head=head->next;
449 }
450 head=jump_dirty[vpage];
451 while(head!=NULL) {
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 // Don't restore blocks which are about to expire from the cache
455 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
456 if(verify_dirty(head->addr)) {
457 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
458 invalid_code[vaddr>>12]=0;
459 memory_map[vaddr>>12]|=0x40000000;
460 if(vpage<2048) {
94d23bb9 461#ifndef DISABLE_TLB
57871462 462 if(tlb_LUT_r[vaddr>>12]) {
463 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
464 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
465 }
94d23bb9 466#endif
57871462 467 restore_candidate[vpage>>3]|=1<<(vpage&7);
468 }
469 else restore_candidate[page>>3]|=1<<(page&7);
470 if(head->reg32==0) {
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472 if(ht_bin[0]==-1) {
473 ht_bin[1]=(int)head->addr;
474 ht_bin[0]=vaddr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
477 ht_bin[2]=vaddr;
478 }
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
482 //ht_bin[0]=vaddr;
483 }
484 return head->addr;
485 }
486 }
487 head=head->next;
488 }
489 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
490 int r=new_recompile_block(vaddr);
491 if(r==0) return get_addr(vaddr);
492 // Execute in unmapped page, generate pagefault execption
493 Status|=2;
494 Cause=(vaddr<<31)|0x8;
495 EPC=(vaddr&1)?vaddr-5:vaddr;
496 BadVAddr=(vaddr&~1);
497 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
498 EntryHi=BadVAddr&0xFFFFE000;
499 return get_addr_ht(0x80000000);
560e4a12 500#endif
57871462 501}
502
503void clear_all_regs(signed char regmap[])
504{
505 int hr;
506 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
507}
508
509signed char get_reg(signed char regmap[],int r)
510{
511 int hr;
512 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
513 return -1;
514}
515
516// Find a register that is available for two consecutive cycles
517signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
518{
519 int hr;
520 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
521 return -1;
522}
523
524int count_free_regs(signed char regmap[])
525{
526 int count=0;
527 int hr;
528 for(hr=0;hr<HOST_REGS;hr++)
529 {
530 if(hr!=EXCLUDE_REG) {
531 if(regmap[hr]<0) count++;
532 }
533 }
534 return count;
535}
536
537void dirty_reg(struct regstat *cur,signed char reg)
538{
539 int hr;
540 if(!reg) return;
541 for (hr=0;hr<HOST_REGS;hr++) {
542 if((cur->regmap[hr]&63)==reg) {
543 cur->dirty|=1<<hr;
544 }
545 }
546}
547
548// If we dirty the lower half of a 64 bit register which is now being
549// sign-extended, we need to dump the upper half.
550// Note: Do this only after completion of the instruction, because
551// some instructions may need to read the full 64-bit value even if
552// overwriting it (eg SLTI, DSRA32).
553static void flush_dirty_uppers(struct regstat *cur)
554{
555 int hr,reg;
556 for (hr=0;hr<HOST_REGS;hr++) {
557 if((cur->dirty>>hr)&1) {
558 reg=cur->regmap[hr];
559 if(reg>=64)
560 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
561 }
562 }
563}
564
565void set_const(struct regstat *cur,signed char reg,uint64_t value)
566{
567 int hr;
568 if(!reg) return;
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if(cur->regmap[hr]==reg) {
571 cur->isconst|=1<<hr;
572 cur->constmap[hr]=value;
573 }
574 else if((cur->regmap[hr]^64)==reg) {
575 cur->isconst|=1<<hr;
576 cur->constmap[hr]=value>>32;
577 }
578 }
579}
580
581void clear_const(struct regstat *cur,signed char reg)
582{
583 int hr;
584 if(!reg) return;
585 for (hr=0;hr<HOST_REGS;hr++) {
586 if((cur->regmap[hr]&63)==reg) {
587 cur->isconst&=~(1<<hr);
588 }
589 }
590}
591
592int is_const(struct regstat *cur,signed char reg)
593{
594 int hr;
595 if(!reg) return 1;
596 for (hr=0;hr<HOST_REGS;hr++) {
597 if((cur->regmap[hr]&63)==reg) {
598 return (cur->isconst>>hr)&1;
599 }
600 }
601 return 0;
602}
603uint64_t get_const(struct regstat *cur,signed char reg)
604{
605 int hr;
606 if(!reg) return 0;
607 for (hr=0;hr<HOST_REGS;hr++) {
608 if(cur->regmap[hr]==reg) {
609 return cur->constmap[hr];
610 }
611 }
612 printf("Unknown constant in r%d\n",reg);
613 exit(1);
614}
615
616// Least soon needed registers
617// Look at the next ten instructions and see which registers
618// will be used. Try not to reallocate these.
619void lsn(u_char hsn[], int i, int *preferred_reg)
620{
621 int j;
622 int b=-1;
623 for(j=0;j<9;j++)
624 {
625 if(i+j>=slen) {
626 j=slen-i-1;
627 break;
628 }
629 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
630 {
631 // Don't go past an unconditonal jump
632 j++;
633 break;
634 }
635 }
636 for(;j>=0;j--)
637 {
638 if(rs1[i+j]) hsn[rs1[i+j]]=j;
639 if(rs2[i+j]) hsn[rs2[i+j]]=j;
640 if(rt1[i+j]) hsn[rt1[i+j]]=j;
641 if(rt2[i+j]) hsn[rt2[i+j]]=j;
642 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
643 // Stores can allocate zero
644 hsn[rs1[i+j]]=j;
645 hsn[rs2[i+j]]=j;
646 }
647 // On some architectures stores need invc_ptr
648 #if defined(HOST_IMM8)
b9b61529 649 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 650 hsn[INVCP]=j;
651 }
652 #endif
653 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 {
655 hsn[CCREG]=j;
656 b=j;
657 }
658 }
659 if(b>=0)
660 {
661 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
662 {
663 // Follow first branch
664 int t=(ba[i+b]-start)>>2;
665 j=7-b;if(t+j>=slen) j=slen-t-1;
666 for(;j>=0;j--)
667 {
668 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
669 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
670 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
671 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
672 }
673 }
674 // TODO: preferred register based on backward branch
675 }
676 // Delay slot should preferably not overwrite branch conditions or cycle count
677 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
678 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
679 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
680 hsn[CCREG]=1;
681 // ...or hash tables
682 hsn[RHASH]=1;
683 hsn[RHTBL]=1;
684 }
685 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 686 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 687 hsn[FTEMP]=0;
688 }
689 // Load L/R also uses FTEMP as a temporary register
690 if(itype[i]==LOADLR) {
691 hsn[FTEMP]=0;
692 }
b7918751 693 // Also SWL/SWR/SDL/SDR
694 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Don't remove the TLB registers either
b9b61529 698 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 699 hsn[TLREG]=0;
700 }
701 // Don't remove the miniht registers
702 if(itype[i]==UJUMP||itype[i]==RJUMP)
703 {
704 hsn[RHASH]=0;
705 hsn[RHTBL]=0;
706 }
707}
708
709// We only want to allocate registers if we're going to use them again soon
710int needed_again(int r, int i)
711{
712 int j;
713 int b=-1;
714 int rn=10;
715 int hr;
716 u_char hsn[MAXREG+1];
717 int preferred_reg;
718
719 memset(hsn,10,sizeof(hsn));
720 lsn(hsn,i,&preferred_reg);
721
722 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
723 {
724 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
725 return 0; // Don't need any registers if exiting the block
726 }
727 for(j=0;j<9;j++)
728 {
729 if(i+j>=slen) {
730 j=slen-i-1;
731 break;
732 }
733 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
734 {
735 // Don't go past an unconditonal jump
736 j++;
737 break;
738 }
1e973cb0 739 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 740 {
741 break;
742 }
743 }
744 for(;j>=1;j--)
745 {
746 if(rs1[i+j]==r) rn=j;
747 if(rs2[i+j]==r) rn=j;
748 if((unneeded_reg[i+j]>>r)&1) rn=10;
749 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 {
751 b=j;
752 }
753 }
754 /*
755 if(b>=0)
756 {
757 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
758 {
759 // Follow first branch
760 int o=rn;
761 int t=(ba[i+b]-start)>>2;
762 j=7-b;if(t+j>=slen) j=slen-t-1;
763 for(;j>=0;j--)
764 {
765 if(!((unneeded_reg[t+j]>>r)&1)) {
766 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
767 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
768 }
769 else rn=o;
770 }
771 }
772 }*/
773 for(hr=0;hr<HOST_REGS;hr++) {
774 if(hr!=EXCLUDE_REG) {
775 if(rn<hsn[hr]) return 1;
776 }
777 }
778 return 0;
779}
780
781// Try to match register allocations at the end of a loop with those
782// at the beginning
783int loop_reg(int i, int r, int hr)
784{
785 int j,k;
786 for(j=0;j<9;j++)
787 {
788 if(i+j>=slen) {
789 j=slen-i-1;
790 break;
791 }
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
793 {
794 // Don't go past an unconditonal jump
795 j++;
796 break;
797 }
798 }
799 k=0;
800 if(i>0){
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
802 k--;
803 }
804 for(;k<j;k++)
805 {
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
809 {
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
811 {
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
817 }
818 }
819 }
820 return hr;
821}
822
823
824// Allocate every register, preserving source/target regs
825void alloc_all(struct regstat *cur,int i)
826{
827 int hr;
828
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 {
834 cur->regmap[hr]=-1;
835 cur->dirty&=~(1<<hr);
836 }
837 // Don't need zeros
838 if((cur->regmap[hr]&63)==0)
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 }
844 }
845}
846
847
848void div64(int64_t dividend,int64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855void divu64(uint64_t dividend,uint64_t divisor)
856{
857 lo=dividend/divisor;
858 hi=dividend%divisor;
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861}
862
863void mult64(uint64_t m1,uint64_t m2)
864{
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
868 int sign = 0;
869
870 if (m1 < 0)
871 {
872 op2 = -m1;
873 sign = 1 - sign;
874 }
875 else op2 = m1;
876 if (m2 < 0)
877 {
878 op4 = -m2;
879 sign = 1 - sign;
880 }
881 else op4 = m2;
882
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
887
888 temp1 = op1 * op3;
889 temp2 = (temp1 >> 32) + op1 * op4;
890 temp3 = op2 * op3;
891 temp4 = (temp3 >> 32) + op2 * op4;
892
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
897
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
900 if (sign)
901 {
902 hi = ~hi;
903 if (!lo) hi++;
904 else lo = ~lo + 1;
905 }
906}
907
908void multu64(uint64_t m1,uint64_t m2)
909{
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
913
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
918
919 temp1 = op1 * op3;
920 temp2 = (temp1 >> 32) + op1 * op4;
921 temp3 = op2 * op3;
922 temp4 = (temp3 >> 32) + op2 * op4;
923
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
928
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
931
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934}
935
936uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937{
938 if(bits) {
939 original<<=64-bits;
940 original>>=64-bits;
941 loaded<<=bits;
942 original|=loaded;
943 }
944 else original=loaded;
945 return original;
946}
947uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948{
949 if(bits^56) {
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
952 loaded>>=bits^56;
953 original|=loaded;
954 }
955 else original=loaded;
956 return original;
957}
958
959#ifdef __i386__
960#include "assem_x86.c"
961#endif
962#ifdef __x86_64__
963#include "assem_x64.c"
964#endif
965#ifdef __arm__
966#include "assem_arm.c"
967#endif
968
969// Add virtual address mapping to linked list
970void ll_add(struct ll_entry **head,int vaddr,void *addr)
971{
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
976 new_entry->reg32=0;
977 new_entry->addr=addr;
978 new_entry->next=*head;
979 *head=new_entry;
980}
981
982// Add virtual address mapping for 32-bit compiled block
983void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
984{
7139f3c8 985 ll_add(head,vaddr,addr);
986#ifndef FORCE32
987 (*head)->reg32=reg32;
988#endif
57871462 989}
990
991// Check if an address is already compiled
992// but don't return addresses which are about to expire from the cache
993void *check_addr(u_int vaddr)
994{
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
999 }
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003 }
94d23bb9 1004 u_int page=get_page(vaddr);
57871462 1005 struct ll_entry *head;
1006 head=jump_in[page];
1007 while(head!=NULL) {
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1013 return head->addr;
1014 }
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1017 return head->addr;
1018 }
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1022 if(ht_bin[0]==-1) {
1023 ht_bin[1]=(int)head->addr;
1024 ht_bin[0]=vaddr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1027 ht_bin[2]=vaddr;
1028 }
1029 return head->addr;
1030 }
1031 }
1032 head=head->next;
1033 }
1034 return 0;
1035}
1036
1037void remove_hash(int vaddr)
1038{
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1043 }
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1048 }
1049}
1050
1051void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052{
1053 struct ll_entry *next;
1054 while(*head) {
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057 {
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1060 next=(*head)->next;
1061 free(*head);
1062 *head=next;
1063 }
1064 else
1065 {
1066 head=&((*head)->next);
1067 }
1068 }
1069}
1070
1071// Remove all entries from linked list
1072void ll_clear(struct ll_entry **head)
1073{
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1076 if(cur=*head) {
1077 *head=0;
1078 while(cur) {
1079 next=cur->next;
1080 free(cur);
1081 cur=next;
1082 }
1083 }
1084}
1085
1086// Dereference the pointers and remove if it matches
1087void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088{
f76eeef9 1089 u_int old_host_addr=0;
57871462 1090 while(head) {
1091 int ptr=get_pointer(head->addr);
1092 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1093 if(((ptr>>shift)==(addr>>shift)) ||
1094 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095 {
5088bb70 1096 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1097 u_int host_addr=(u_int)kill_pointer(head->addr);
1098
1099 if((host_addr>>12)!=(old_host_addr>>12)) {
1100 #ifdef __arm__
1101 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1102 #endif
1103 old_host_addr=host_addr;
1104 }
57871462 1105 }
1106 head=head->next;
1107 }
f76eeef9 1108 #ifdef __arm__
1109 if (old_host_addr)
1110 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1111 #endif
57871462 1112}
1113
1114// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1115void invalidate_page(u_int page)
57871462 1116{
57871462 1117 struct ll_entry *head;
1118 struct ll_entry *next;
f76eeef9 1119 u_int old_host_addr=0;
57871462 1120 head=jump_in[page];
1121 jump_in[page]=0;
1122 while(head!=NULL) {
1123 inv_debug("INVALIDATE: %x\n",head->vaddr);
1124 remove_hash(head->vaddr);
1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
1129 head=jump_out[page];
1130 jump_out[page]=0;
1131 while(head!=NULL) {
1132 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1133 u_int host_addr=(u_int)kill_pointer(head->addr);
1134
1135 if((host_addr>>12)!=(old_host_addr>>12)) {
1136 #ifdef __arm__
1137 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1138 #endif
1139 old_host_addr=host_addr;
1140 }
57871462 1141 next=head->next;
1142 free(head);
1143 head=next;
1144 }
f76eeef9 1145 #ifdef __arm__
1146 if (old_host_addr)
1147 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1148 #endif
57871462 1149}
1150void invalidate_block(u_int block)
1151{
94d23bb9 1152 u_int page=get_page(block<<12);
1153 u_int vpage=get_vpage(block<<12);
57871462 1154 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1155 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1156 u_int first,last;
1157 first=last=page;
1158 struct ll_entry *head;
1159 head=jump_dirty[vpage];
1160 //printf("page=%d vpage=%d\n",page,vpage);
1161 while(head!=NULL) {
1162 u_int start,end;
1163 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1164 get_bounds((int)head->addr,&start,&end);
1165 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1166 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1167 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1168 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1169 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1170 }
1171 }
90ae6d4e 1172#ifndef DISABLE_TLB
57871462 1173 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1174 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1175 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1176 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1177 }
1178 }
90ae6d4e 1179#endif
57871462 1180 }
1181 head=head->next;
1182 }
1183 //printf("first=%d last=%d\n",first,last);
f76eeef9 1184 invalidate_page(page);
57871462 1185 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186 assert(last<page+5);
1187 // Invalidate the adjacent pages if a block crosses a 4K boundary
1188 while(first<page) {
1189 invalidate_page(first);
1190 first++;
1191 }
1192 for(first=page+1;first<last;first++) {
1193 invalidate_page(first);
1194 }
1195
1196 // Don't trap writes
1197 invalid_code[block]=1;
94d23bb9 1198#ifndef DISABLE_TLB
57871462 1199 // If there is a valid TLB entry for this page, remove write protect
1200 if(tlb_LUT_w[block]) {
1201 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1202 // CHECK: Is this right?
1203 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1204 u_int real_block=tlb_LUT_w[block]>>12;
1205 invalid_code[real_block]=1;
1206 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1207 }
1208 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1209#endif
f76eeef9 1210
57871462 1211 #ifdef USE_MINI_HT
1212 memset(mini_ht,-1,sizeof(mini_ht));
1213 #endif
1214}
1215void invalidate_addr(u_int addr)
1216{
1217 invalidate_block(addr>>12);
1218}
1219void invalidate_all_pages()
1220{
1221 u_int page,n;
1222 for(page=0;page<4096;page++)
1223 invalidate_page(page);
1224 for(page=0;page<1048576;page++)
1225 if(!invalid_code[page]) {
1226 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1227 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1228 }
1229 #ifdef __arm__
1230 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1231 #endif
1232 #ifdef USE_MINI_HT
1233 memset(mini_ht,-1,sizeof(mini_ht));
1234 #endif
94d23bb9 1235 #ifndef DISABLE_TLB
57871462 1236 // TLB
1237 for(page=0;page<0x100000;page++) {
1238 if(tlb_LUT_r[page]) {
1239 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1240 if(!tlb_LUT_w[page]||!invalid_code[page])
1241 memory_map[page]|=0x40000000; // Write protect
1242 }
1243 else memory_map[page]=-1;
1244 if(page==0x80000) page=0xC0000;
1245 }
1246 tlb_hacks();
94d23bb9 1247 #endif
57871462 1248}
1249
1250// Add an entry to jump_out after making a link
1251void add_link(u_int vaddr,void *src)
1252{
94d23bb9 1253 u_int page=get_page(vaddr);
57871462 1254 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1255 ll_add(jump_out+page,vaddr,src);
1256 //int ptr=get_pointer(src);
1257 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1258}
1259
1260// If a code block was found to be unmodified (bit was set in
1261// restore_candidate) and it remains unmodified (bit is clear
1262// in invalid_code) then move the entries for that 4K page from
1263// the dirty list to the clean list.
1264void clean_blocks(u_int page)
1265{
1266 struct ll_entry *head;
1267 inv_debug("INV: clean_blocks page=%d\n",page);
1268 head=jump_dirty[page];
1269 while(head!=NULL) {
1270 if(!invalid_code[head->vaddr>>12]) {
1271 // Don't restore blocks which are about to expire from the cache
1272 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1273 u_int start,end;
1274 if(verify_dirty((int)head->addr)) {
1275 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1276 u_int i;
1277 u_int inv=0;
1278 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1279 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1280 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1281 inv|=invalid_code[i];
1282 }
1283 }
1284 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1285 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1286 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1287 if(addr<start||addr>=end) inv=1;
1288 }
4cb76aa4 1289 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1290 inv=1;
1291 }
1292 if(!inv) {
1293 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1294 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1295 u_int ppage=page;
94d23bb9 1296#ifndef DISABLE_TLB
57871462 1297 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1298#endif
57871462 1299 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1300 //printf("page=%x, addr=%x\n",page,head->vaddr);
1301 //assert(head->vaddr>>12==(page|0x80000));
1302 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1303 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1304 if(!head->reg32) {
1305 if(ht_bin[0]==head->vaddr) {
1306 ht_bin[1]=(int)clean_addr; // Replace existing entry
1307 }
1308 if(ht_bin[2]==head->vaddr) {
1309 ht_bin[3]=(int)clean_addr; // Replace existing entry
1310 }
1311 }
1312 }
1313 }
1314 }
1315 }
1316 }
1317 head=head->next;
1318 }
1319}
1320
1321
1322void mov_alloc(struct regstat *current,int i)
1323{
1324 // Note: Don't need to actually alloc the source registers
1325 if((~current->is32>>rs1[i])&1) {
1326 //alloc_reg64(current,i,rs1[i]);
1327 alloc_reg64(current,i,rt1[i]);
1328 current->is32&=~(1LL<<rt1[i]);
1329 } else {
1330 //alloc_reg(current,i,rs1[i]);
1331 alloc_reg(current,i,rt1[i]);
1332 current->is32|=(1LL<<rt1[i]);
1333 }
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 dirty_reg(current,rt1[i]);
1337}
1338
1339void shiftimm_alloc(struct regstat *current,int i)
1340{
1341 clear_const(current,rs1[i]);
1342 clear_const(current,rt1[i]);
1343 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1344 {
1345 if(rt1[i]) {
1346 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1347 else lt1[i]=rs1[i];
1348 alloc_reg(current,i,rt1[i]);
1349 current->is32|=1LL<<rt1[i];
1350 dirty_reg(current,rt1[i]);
1351 }
1352 }
1353 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1354 {
1355 if(rt1[i]) {
1356 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1357 alloc_reg64(current,i,rt1[i]);
1358 current->is32&=~(1LL<<rt1[i]);
1359 dirty_reg(current,rt1[i]);
1360 }
1361 }
1362 if(opcode2[i]==0x3c) // DSLL32
1363 {
1364 if(rt1[i]) {
1365 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1366 alloc_reg64(current,i,rt1[i]);
1367 current->is32&=~(1LL<<rt1[i]);
1368 dirty_reg(current,rt1[i]);
1369 }
1370 }
1371 if(opcode2[i]==0x3e) // DSRL32
1372 {
1373 if(rt1[i]) {
1374 alloc_reg64(current,i,rs1[i]);
1375 if(imm[i]==32) {
1376 alloc_reg64(current,i,rt1[i]);
1377 current->is32&=~(1LL<<rt1[i]);
1378 } else {
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=1LL<<rt1[i];
1381 }
1382 dirty_reg(current,rt1[i]);
1383 }
1384 }
1385 if(opcode2[i]==0x3f) // DSRA32
1386 {
1387 if(rt1[i]) {
1388 alloc_reg64(current,i,rs1[i]);
1389 alloc_reg(current,i,rt1[i]);
1390 current->is32|=1LL<<rt1[i];
1391 dirty_reg(current,rt1[i]);
1392 }
1393 }
1394}
1395
1396void shift_alloc(struct regstat *current,int i)
1397{
1398 if(rt1[i]) {
1399 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1400 {
1401 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1402 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1403 alloc_reg(current,i,rt1[i]);
1404 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1405 current->is32|=1LL<<rt1[i];
1406 } else { // DSLLV/DSRLV/DSRAV
1407 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1408 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1412 alloc_reg_temp(current,i,-1);
1413 }
1414 clear_const(current,rs1[i]);
1415 clear_const(current,rs2[i]);
1416 clear_const(current,rt1[i]);
1417 dirty_reg(current,rt1[i]);
1418 }
1419}
1420
1421void alu_alloc(struct regstat *current,int i)
1422{
1423 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1424 if(rt1[i]) {
1425 if(rs1[i]&&rs2[i]) {
1426 alloc_reg(current,i,rs1[i]);
1427 alloc_reg(current,i,rs2[i]);
1428 }
1429 else {
1430 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1431 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1432 }
1433 alloc_reg(current,i,rt1[i]);
1434 }
1435 current->is32|=1LL<<rt1[i];
1436 }
1437 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1438 if(rt1[i]) {
1439 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1440 {
1441 alloc_reg64(current,i,rs1[i]);
1442 alloc_reg64(current,i,rs2[i]);
1443 alloc_reg(current,i,rt1[i]);
1444 } else {
1445 alloc_reg(current,i,rs1[i]);
1446 alloc_reg(current,i,rs2[i]);
1447 alloc_reg(current,i,rt1[i]);
1448 }
1449 }
1450 current->is32|=1LL<<rt1[i];
1451 }
1452 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1453 if(rt1[i]) {
1454 if(rs1[i]&&rs2[i]) {
1455 alloc_reg(current,i,rs1[i]);
1456 alloc_reg(current,i,rs2[i]);
1457 }
1458 else
1459 {
1460 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1461 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1462 }
1463 alloc_reg(current,i,rt1[i]);
1464 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1465 {
1466 if(!((current->uu>>rt1[i])&1)) {
1467 alloc_reg64(current,i,rt1[i]);
1468 }
1469 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1470 if(rs1[i]&&rs2[i]) {
1471 alloc_reg64(current,i,rs1[i]);
1472 alloc_reg64(current,i,rs2[i]);
1473 }
1474 else
1475 {
1476 // Is is really worth it to keep 64-bit values in registers?
1477 #ifdef NATIVE_64BIT
1478 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1479 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1480 #endif
1481 }
1482 }
1483 current->is32&=~(1LL<<rt1[i]);
1484 } else {
1485 current->is32|=1LL<<rt1[i];
1486 }
1487 }
1488 }
1489 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1490 if(rt1[i]) {
1491 if(rs1[i]&&rs2[i]) {
1492 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1493 alloc_reg64(current,i,rs1[i]);
1494 alloc_reg64(current,i,rs2[i]);
1495 alloc_reg64(current,i,rt1[i]);
1496 } else {
1497 alloc_reg(current,i,rs1[i]);
1498 alloc_reg(current,i,rs2[i]);
1499 alloc_reg(current,i,rt1[i]);
1500 }
1501 }
1502 else {
1503 alloc_reg(current,i,rt1[i]);
1504 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1505 // DADD used as move, or zeroing
1506 // If we have a 64-bit source, then make the target 64 bits too
1507 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1508 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1509 alloc_reg64(current,i,rt1[i]);
1510 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 if(opcode2[i]>=0x2e&&rs2[i]) {
1515 // DSUB used as negation - 64-bit result
1516 // If we have a 32-bit register, extend it to 64 bits
1517 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1518 alloc_reg64(current,i,rt1[i]);
1519 }
1520 }
1521 }
1522 if(rs1[i]&&rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 } else if(rs1[i]) {
1525 current->is32&=~(1LL<<rt1[i]);
1526 if((current->is32>>rs1[i])&1)
1527 current->is32|=1LL<<rt1[i];
1528 } else if(rs2[i]) {
1529 current->is32&=~(1LL<<rt1[i]);
1530 if((current->is32>>rs2[i])&1)
1531 current->is32|=1LL<<rt1[i];
1532 } else {
1533 current->is32|=1LL<<rt1[i];
1534 }
1535 }
1536 }
1537 clear_const(current,rs1[i]);
1538 clear_const(current,rs2[i]);
1539 clear_const(current,rt1[i]);
1540 dirty_reg(current,rt1[i]);
1541}
1542
1543void imm16_alloc(struct regstat *current,int i)
1544{
1545 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1546 else lt1[i]=rs1[i];
1547 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1548 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1549 current->is32&=~(1LL<<rt1[i]);
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 // TODO: Could preserve the 32-bit flag if the immediate is zero
1552 alloc_reg64(current,i,rt1[i]);
1553 alloc_reg64(current,i,rs1[i]);
1554 }
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1559 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1560 current->is32|=1LL<<rt1[i];
1561 clear_const(current,rs1[i]);
1562 clear_const(current,rt1[i]);
1563 }
1564 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1565 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1566 if(rs1[i]!=rt1[i]) {
1567 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1568 alloc_reg64(current,i,rt1[i]);
1569 current->is32&=~(1LL<<rt1[i]);
1570 }
1571 }
1572 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1573 if(is_const(current,rs1[i])) {
1574 int v=get_const(current,rs1[i]);
1575 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1576 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1577 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1578 }
1579 else clear_const(current,rt1[i]);
1580 }
1581 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1582 if(is_const(current,rs1[i])) {
1583 int v=get_const(current,rs1[i]);
1584 set_const(current,rt1[i],v+imm[i]);
1585 }
1586 else clear_const(current,rt1[i]);
1587 current->is32|=1LL<<rt1[i];
1588 }
1589 else {
1590 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1591 current->is32|=1LL<<rt1[i];
1592 }
1593 dirty_reg(current,rt1[i]);
1594}
1595
1596void load_alloc(struct regstat *current,int i)
1597{
1598 clear_const(current,rt1[i]);
1599 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1600 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1601 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1602 if(rt1[i]) {
1603 alloc_reg(current,i,rt1[i]);
535d208a 1604 if(get_reg(current->regmap,rt1[i])<0) {
1605 // dummy load, but we still need a register to calculate the address
1606 alloc_reg_temp(current,i,-1);
1607 }
57871462 1608 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1609 {
1610 current->is32&=~(1LL<<rt1[i]);
1611 alloc_reg64(current,i,rt1[i]);
1612 }
1613 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1614 {
1615 current->is32&=~(1LL<<rt1[i]);
1616 alloc_reg64(current,i,rt1[i]);
1617 alloc_all(current,i);
1618 alloc_reg64(current,i,FTEMP);
1619 }
1620 else current->is32|=1LL<<rt1[i];
1621 dirty_reg(current,rt1[i]);
1622 // If using TLB, need a register for pointer to the mapping table
1623 if(using_tlb) alloc_reg(current,i,TLREG);
1624 // LWL/LWR need a temporary register for the old value
1625 if(opcode[i]==0x22||opcode[i]==0x26)
1626 {
1627 alloc_reg(current,i,FTEMP);
1628 alloc_reg_temp(current,i,-1);
1629 }
1630 }
1631 else
1632 {
1633 // Load to r0 (dummy load)
1634 // but we still need a register to calculate the address
535d208a 1635 if(opcode[i]==0x22||opcode[i]==0x26)
1636 {
1637 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1638 }
57871462 1639 alloc_reg_temp(current,i,-1);
535d208a 1640 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641 {
1642 alloc_all(current,i);
1643 alloc_reg64(current,i,FTEMP);
1644 }
57871462 1645 }
1646}
1647
1648void store_alloc(struct regstat *current,int i)
1649{
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1657 }
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1663 #endif
b7918751 1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1665 alloc_reg(current,i,FTEMP);
1666 }
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
1669}
1670
1671void c1ls_alloc(struct regstat *current,int i)
1672{
1673 //clear_const(current,rs1[i]); // FIXME
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,CSREG); // Status
1677 alloc_reg(current,i,FTEMP);
1678 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1679 alloc_reg64(current,i,FTEMP);
1680 }
1681 // If using TLB, need a register for pointer to the mapping table
1682 if(using_tlb) alloc_reg(current,i,TLREG);
1683 #if defined(HOST_IMM8)
1684 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1685 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1686 alloc_reg(current,i,INVCP);
1687 #endif
1688 // We need a temporary register for address generation
1689 alloc_reg_temp(current,i,-1);
1690}
1691
b9b61529 1692void c2ls_alloc(struct regstat *current,int i)
1693{
1694 clear_const(current,rt1[i]);
1695 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1696 alloc_reg(current,i,FTEMP);
1697 // If using TLB, need a register for pointer to the mapping table
1698 if(using_tlb) alloc_reg(current,i,TLREG);
1699 #if defined(HOST_IMM8)
1700 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1701 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1702 alloc_reg(current,i,INVCP);
1703 #endif
1704 // We need a temporary register for address generation
1705 alloc_reg_temp(current,i,-1);
1706}
1707
57871462 1708#ifndef multdiv_alloc
1709void multdiv_alloc(struct regstat *current,int i)
1710{
1711 // case 0x18: MULT
1712 // case 0x19: MULTU
1713 // case 0x1A: DIV
1714 // case 0x1B: DIVU
1715 // case 0x1C: DMULT
1716 // case 0x1D: DMULTU
1717 // case 0x1E: DDIV
1718 // case 0x1F: DDIVU
1719 clear_const(current,rs1[i]);
1720 clear_const(current,rs2[i]);
1721 if(rs1[i]&&rs2[i])
1722 {
1723 if((opcode2[i]&4)==0) // 32-bit
1724 {
1725 current->u&=~(1LL<<HIREG);
1726 current->u&=~(1LL<<LOREG);
1727 alloc_reg(current,i,HIREG);
1728 alloc_reg(current,i,LOREG);
1729 alloc_reg(current,i,rs1[i]);
1730 alloc_reg(current,i,rs2[i]);
1731 current->is32|=1LL<<HIREG;
1732 current->is32|=1LL<<LOREG;
1733 dirty_reg(current,HIREG);
1734 dirty_reg(current,LOREG);
1735 }
1736 else // 64-bit
1737 {
1738 current->u&=~(1LL<<HIREG);
1739 current->u&=~(1LL<<LOREG);
1740 current->uu&=~(1LL<<HIREG);
1741 current->uu&=~(1LL<<LOREG);
1742 alloc_reg64(current,i,HIREG);
1743 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744 alloc_reg64(current,i,rs1[i]);
1745 alloc_reg64(current,i,rs2[i]);
1746 alloc_all(current,i);
1747 current->is32&=~(1LL<<HIREG);
1748 current->is32&=~(1LL<<LOREG);
1749 dirty_reg(current,HIREG);
1750 dirty_reg(current,LOREG);
1751 }
1752 }
1753 else
1754 {
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1764 }
1765}
1766#endif
1767
1768void cop0_alloc(struct regstat *current,int i)
1769{
1770 if(opcode2[i]==0) // MFC0
1771 {
1772 if(rt1[i]) {
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1778 }
1779 }
1780 else if(opcode2[i]==4) // MTC0
1781 {
1782 if(rs1[i]){
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1786 }
1787 else {
1788 alloc_all(current,i); // FIXME: Keep r0
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 }
1792 }
1793 else
1794 {
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1798 }
1799}
1800
1801void cop1_alloc(struct regstat *current,int i)
1802{
1803 alloc_reg(current,i,CSREG); // Load status
1804 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1805 {
7de557a6 1806 if(rt1[i]){
1807 clear_const(current,rt1[i]);
1808 if(opcode2[i]==1) {
1809 alloc_reg64(current,i,rt1[i]); // DMFC1
1810 current->is32&=~(1LL<<rt1[i]);
1811 }else{
1812 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1813 current->is32|=1LL<<rt1[i];
1814 }
1815 dirty_reg(current,rt1[i]);
57871462 1816 }
57871462 1817 alloc_reg_temp(current,i,-1);
1818 }
1819 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1820 {
1821 if(rs1[i]){
1822 clear_const(current,rs1[i]);
1823 if(opcode2[i]==5)
1824 alloc_reg64(current,i,rs1[i]); // DMTC1
1825 else
1826 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1827 alloc_reg_temp(current,i,-1);
1828 }
1829 else {
1830 current->u&=~1LL;
1831 alloc_reg(current,i,0);
1832 alloc_reg_temp(current,i,-1);
1833 }
1834 }
1835}
1836void fconv_alloc(struct regstat *current,int i)
1837{
1838 alloc_reg(current,i,CSREG); // Load status
1839 alloc_reg_temp(current,i,-1);
1840}
1841void float_alloc(struct regstat *current,int i)
1842{
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
1845}
b9b61529 1846void c2op_alloc(struct regstat *current,int i)
1847{
1848 alloc_reg_temp(current,i,-1);
1849}
57871462 1850void fcomp_alloc(struct regstat *current,int i)
1851{
1852 alloc_reg(current,i,CSREG); // Load status
1853 alloc_reg(current,i,FSREG); // Load flags
1854 dirty_reg(current,FSREG); // Flag will be modified
1855 alloc_reg_temp(current,i,-1);
1856}
1857
1858void syscall_alloc(struct regstat *current,int i)
1859{
1860 alloc_cc(current,i);
1861 dirty_reg(current,CCREG);
1862 alloc_all(current,i);
1863 current->isconst=0;
1864}
1865
1866void delayslot_alloc(struct regstat *current,int i)
1867{
1868 switch(itype[i]) {
1869 case UJUMP:
1870 case CJUMP:
1871 case SJUMP:
1872 case RJUMP:
1873 case FJUMP:
1874 case SYSCALL:
7139f3c8 1875 case HLECALL:
57871462 1876 case SPAN:
1877 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1878 printf("Disabled speculative precompilation\n");
1879 stop_after_jal=1;
1880 break;
1881 case IMM16:
1882 imm16_alloc(current,i);
1883 break;
1884 case LOAD:
1885 case LOADLR:
1886 load_alloc(current,i);
1887 break;
1888 case STORE:
1889 case STORELR:
1890 store_alloc(current,i);
1891 break;
1892 case ALU:
1893 alu_alloc(current,i);
1894 break;
1895 case SHIFT:
1896 shift_alloc(current,i);
1897 break;
1898 case MULTDIV:
1899 multdiv_alloc(current,i);
1900 break;
1901 case SHIFTIMM:
1902 shiftimm_alloc(current,i);
1903 break;
1904 case MOV:
1905 mov_alloc(current,i);
1906 break;
1907 case COP0:
1908 cop0_alloc(current,i);
1909 break;
1910 case COP1:
b9b61529 1911 case COP2:
57871462 1912 cop1_alloc(current,i);
1913 break;
1914 case C1LS:
1915 c1ls_alloc(current,i);
1916 break;
b9b61529 1917 case C2LS:
1918 c2ls_alloc(current,i);
1919 break;
57871462 1920 case FCONV:
1921 fconv_alloc(current,i);
1922 break;
1923 case FLOAT:
1924 float_alloc(current,i);
1925 break;
1926 case FCOMP:
1927 fcomp_alloc(current,i);
1928 break;
b9b61529 1929 case C2OP:
1930 c2op_alloc(current,i);
1931 break;
57871462 1932 }
1933}
1934
1935// Special case where a branch and delay slot span two pages in virtual memory
1936static void pagespan_alloc(struct regstat *current,int i)
1937{
1938 current->isconst=0;
1939 current->wasconst=0;
1940 regs[i].wasconst=0;
1941 alloc_all(current,i);
1942 alloc_cc(current,i);
1943 dirty_reg(current,CCREG);
1944 if(opcode[i]==3) // JAL
1945 {
1946 alloc_reg(current,i,31);
1947 dirty_reg(current,31);
1948 }
1949 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1950 {
1951 alloc_reg(current,i,rs1[i]);
5067f341 1952 if (rt1[i]!=0) {
1953 alloc_reg(current,i,rt1[i]);
1954 dirty_reg(current,rt1[i]);
57871462 1955 }
1956 }
1957 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1958 {
1959 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1960 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1961 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1962 {
1963 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1964 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1965 }
1966 }
1967 else
1968 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1969 {
1970 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1971 if(!((current->is32>>rs1[i])&1))
1972 {
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 }
1975 }
1976 else
1977 if(opcode[i]==0x11) // BC1
1978 {
1979 alloc_reg(current,i,FSREG);
1980 alloc_reg(current,i,CSREG);
1981 }
1982 //else ...
1983}
1984
1985add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1986{
1987 stubs[stubcount][0]=type;
1988 stubs[stubcount][1]=addr;
1989 stubs[stubcount][2]=retaddr;
1990 stubs[stubcount][3]=a;
1991 stubs[stubcount][4]=b;
1992 stubs[stubcount][5]=c;
1993 stubs[stubcount][6]=d;
1994 stubs[stubcount][7]=e;
1995 stubcount++;
1996}
1997
1998// Write out a single register
1999void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2000{
2001 int hr;
2002 for(hr=0;hr<HOST_REGS;hr++) {
2003 if(hr!=EXCLUDE_REG) {
2004 if((regmap[hr]&63)==r) {
2005 if((dirty>>hr)&1) {
2006 if(regmap[hr]<64) {
2007 emit_storereg(r,hr);
24385cae 2008#ifndef FORCE32
57871462 2009 if((is32>>regmap[hr])&1) {
2010 emit_sarimm(hr,31,hr);
2011 emit_storereg(r|64,hr);
2012 }
24385cae 2013#endif
57871462 2014 }else{
2015 emit_storereg(r|64,hr);
2016 }
2017 }
2018 }
2019 }
2020 }
2021}
2022
2023int mchecksum()
2024{
2025 //if(!tracedebug) return 0;
2026 int i;
2027 int sum=0;
2028 for(i=0;i<2097152;i++) {
2029 unsigned int temp=sum;
2030 sum<<=1;
2031 sum|=(~temp)>>31;
2032 sum^=((u_int *)rdram)[i];
2033 }
2034 return sum;
2035}
2036int rchecksum()
2037{
2038 int i;
2039 int sum=0;
2040 for(i=0;i<64;i++)
2041 sum^=((u_int *)reg)[i];
2042 return sum;
2043}
57871462 2044void rlist()
2045{
2046 int i;
2047 printf("TRACE: ");
2048 for(i=0;i<32;i++)
2049 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2050 printf("\n");
3d624f89 2051#ifndef DISABLE_COP1
57871462 2052 printf("TRACE: ");
2053 for(i=0;i<32;i++)
2054 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2055 printf("\n");
3d624f89 2056#endif
57871462 2057}
2058
2059void enabletrace()
2060{
2061 tracedebug=1;
2062}
2063
2064void memdebug(int i)
2065{
2066 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2067 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2068 //rlist();
2069 //if(tracedebug) {
2070 //if(Count>=-2084597794) {
2071 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2072 //if(0) {
2073 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2074 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2075 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2076 rlist();
2077 #ifdef __i386__
2078 printf("TRACE: %x\n",(&i)[-1]);
2079 #endif
2080 #ifdef __arm__
2081 int j;
2082 printf("TRACE: %x \n",(&j)[10]);
2083 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2084 #endif
2085 //fflush(stdout);
2086 }
2087 //printf("TRACE: %x\n",(&i)[-1]);
2088}
2089
2090void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2091{
2092 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2093}
2094
2095void alu_assemble(int i,struct regstat *i_regs)
2096{
2097 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2098 if(rt1[i]) {
2099 signed char s1,s2,t;
2100 t=get_reg(i_regs->regmap,rt1[i]);
2101 if(t>=0) {
2102 s1=get_reg(i_regs->regmap,rs1[i]);
2103 s2=get_reg(i_regs->regmap,rs2[i]);
2104 if(rs1[i]&&rs2[i]) {
2105 assert(s1>=0);
2106 assert(s2>=0);
2107 if(opcode2[i]&2) emit_sub(s1,s2,t);
2108 else emit_add(s1,s2,t);
2109 }
2110 else if(rs1[i]) {
2111 if(s1>=0) emit_mov(s1,t);
2112 else emit_loadreg(rs1[i],t);
2113 }
2114 else if(rs2[i]) {
2115 if(s2>=0) {
2116 if(opcode2[i]&2) emit_neg(s2,t);
2117 else emit_mov(s2,t);
2118 }
2119 else {
2120 emit_loadreg(rs2[i],t);
2121 if(opcode2[i]&2) emit_neg(t,t);
2122 }
2123 }
2124 else emit_zeroreg(t);
2125 }
2126 }
2127 }
2128 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2129 if(rt1[i]) {
2130 signed char s1l,s2l,s1h,s2h,tl,th;
2131 tl=get_reg(i_regs->regmap,rt1[i]);
2132 th=get_reg(i_regs->regmap,rt1[i]|64);
2133 if(tl>=0) {
2134 s1l=get_reg(i_regs->regmap,rs1[i]);
2135 s2l=get_reg(i_regs->regmap,rs2[i]);
2136 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2137 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2138 if(rs1[i]&&rs2[i]) {
2139 assert(s1l>=0);
2140 assert(s2l>=0);
2141 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2142 else emit_adds(s1l,s2l,tl);
2143 if(th>=0) {
2144 #ifdef INVERTED_CARRY
2145 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2146 #else
2147 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2148 #endif
2149 else emit_add(s1h,s2h,th);
2150 }
2151 }
2152 else if(rs1[i]) {
2153 if(s1l>=0) emit_mov(s1l,tl);
2154 else emit_loadreg(rs1[i],tl);
2155 if(th>=0) {
2156 if(s1h>=0) emit_mov(s1h,th);
2157 else emit_loadreg(rs1[i]|64,th);
2158 }
2159 }
2160 else if(rs2[i]) {
2161 if(s2l>=0) {
2162 if(opcode2[i]&2) emit_negs(s2l,tl);
2163 else emit_mov(s2l,tl);
2164 }
2165 else {
2166 emit_loadreg(rs2[i],tl);
2167 if(opcode2[i]&2) emit_negs(tl,tl);
2168 }
2169 if(th>=0) {
2170 #ifdef INVERTED_CARRY
2171 if(s2h>=0) emit_mov(s2h,th);
2172 else emit_loadreg(rs2[i]|64,th);
2173 if(opcode2[i]&2) {
2174 emit_adcimm(-1,th); // x86 has inverted carry flag
2175 emit_not(th,th);
2176 }
2177 #else
2178 if(opcode2[i]&2) {
2179 if(s2h>=0) emit_rscimm(s2h,0,th);
2180 else {
2181 emit_loadreg(rs2[i]|64,th);
2182 emit_rscimm(th,0,th);
2183 }
2184 }else{
2185 if(s2h>=0) emit_mov(s2h,th);
2186 else emit_loadreg(rs2[i]|64,th);
2187 }
2188 #endif
2189 }
2190 }
2191 else {
2192 emit_zeroreg(tl);
2193 if(th>=0) emit_zeroreg(th);
2194 }
2195 }
2196 }
2197 }
2198 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2199 if(rt1[i]) {
2200 signed char s1l,s1h,s2l,s2h,t;
2201 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2202 {
2203 t=get_reg(i_regs->regmap,rt1[i]);
2204 //assert(t>=0);
2205 if(t>=0) {
2206 s1l=get_reg(i_regs->regmap,rs1[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2l=get_reg(i_regs->regmap,rs2[i]);
2209 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2210 if(rs2[i]==0) // rx<r0
2211 {
2212 assert(s1h>=0);
2213 if(opcode2[i]==0x2a) // SLT
2214 emit_shrimm(s1h,31,t);
2215 else // SLTU (unsigned can not be less than zero)
2216 emit_zeroreg(t);
2217 }
2218 else if(rs1[i]==0) // r0<rx
2219 {
2220 assert(s2h>=0);
2221 if(opcode2[i]==0x2a) // SLT
2222 emit_set_gz64_32(s2h,s2l,t);
2223 else // SLTU (set if not zero)
2224 emit_set_nz64_32(s2h,s2l,t);
2225 }
2226 else {
2227 assert(s1l>=0);assert(s1h>=0);
2228 assert(s2l>=0);assert(s2h>=0);
2229 if(opcode2[i]==0x2a) // SLT
2230 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2231 else // SLTU
2232 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2233 }
2234 }
2235 } else {
2236 t=get_reg(i_regs->regmap,rt1[i]);
2237 //assert(t>=0);
2238 if(t>=0) {
2239 s1l=get_reg(i_regs->regmap,rs1[i]);
2240 s2l=get_reg(i_regs->regmap,rs2[i]);
2241 if(rs2[i]==0) // rx<r0
2242 {
2243 assert(s1l>=0);
2244 if(opcode2[i]==0x2a) // SLT
2245 emit_shrimm(s1l,31,t);
2246 else // SLTU (unsigned can not be less than zero)
2247 emit_zeroreg(t);
2248 }
2249 else if(rs1[i]==0) // r0<rx
2250 {
2251 assert(s2l>=0);
2252 if(opcode2[i]==0x2a) // SLT
2253 emit_set_gz32(s2l,t);
2254 else // SLTU (set if not zero)
2255 emit_set_nz32(s2l,t);
2256 }
2257 else{
2258 assert(s1l>=0);assert(s2l>=0);
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_if_less32(s1l,s2l,t);
2261 else // SLTU
2262 emit_set_if_carry32(s1l,s2l,t);
2263 }
2264 }
2265 }
2266 }
2267 }
2268 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2269 if(rt1[i]) {
2270 signed char s1l,s1h,s2l,s2h,th,tl;
2271 tl=get_reg(i_regs->regmap,rt1[i]);
2272 th=get_reg(i_regs->regmap,rt1[i]|64);
2273 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2274 {
2275 assert(tl>=0);
2276 if(tl>=0) {
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs1[i]&&rs2[i]) {
2282 assert(s1l>=0);assert(s1h>=0);
2283 assert(s2l>=0);assert(s2h>=0);
2284 if(opcode2[i]==0x24) { // AND
2285 emit_and(s1l,s2l,tl);
2286 emit_and(s1h,s2h,th);
2287 } else
2288 if(opcode2[i]==0x25) { // OR
2289 emit_or(s1l,s2l,tl);
2290 emit_or(s1h,s2h,th);
2291 } else
2292 if(opcode2[i]==0x26) { // XOR
2293 emit_xor(s1l,s2l,tl);
2294 emit_xor(s1h,s2h,th);
2295 } else
2296 if(opcode2[i]==0x27) { // NOR
2297 emit_or(s1l,s2l,tl);
2298 emit_or(s1h,s2h,th);
2299 emit_not(tl,tl);
2300 emit_not(th,th);
2301 }
2302 }
2303 else
2304 {
2305 if(opcode2[i]==0x24) { // AND
2306 emit_zeroreg(tl);
2307 emit_zeroreg(th);
2308 } else
2309 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2310 if(rs1[i]){
2311 if(s1l>=0) emit_mov(s1l,tl);
2312 else emit_loadreg(rs1[i],tl);
2313 if(s1h>=0) emit_mov(s1h,th);
2314 else emit_loadreg(rs1[i]|64,th);
2315 }
2316 else
2317 if(rs2[i]){
2318 if(s2l>=0) emit_mov(s2l,tl);
2319 else emit_loadreg(rs2[i],tl);
2320 if(s2h>=0) emit_mov(s2h,th);
2321 else emit_loadreg(rs2[i]|64,th);
2322 }
2323 else{
2324 emit_zeroreg(tl);
2325 emit_zeroreg(th);
2326 }
2327 } else
2328 if(opcode2[i]==0x27) { // NOR
2329 if(rs1[i]){
2330 if(s1l>=0) emit_not(s1l,tl);
2331 else{
2332 emit_loadreg(rs1[i],tl);
2333 emit_not(tl,tl);
2334 }
2335 if(s1h>=0) emit_not(s1h,th);
2336 else{
2337 emit_loadreg(rs1[i]|64,th);
2338 emit_not(th,th);
2339 }
2340 }
2341 else
2342 if(rs2[i]){
2343 if(s2l>=0) emit_not(s2l,tl);
2344 else{
2345 emit_loadreg(rs2[i],tl);
2346 emit_not(tl,tl);
2347 }
2348 if(s2h>=0) emit_not(s2h,th);
2349 else{
2350 emit_loadreg(rs2[i]|64,th);
2351 emit_not(th,th);
2352 }
2353 }
2354 else {
2355 emit_movimm(-1,tl);
2356 emit_movimm(-1,th);
2357 }
2358 }
2359 }
2360 }
2361 }
2362 else
2363 {
2364 // 32 bit
2365 if(tl>=0) {
2366 s1l=get_reg(i_regs->regmap,rs1[i]);
2367 s2l=get_reg(i_regs->regmap,rs2[i]);
2368 if(rs1[i]&&rs2[i]) {
2369 assert(s1l>=0);
2370 assert(s2l>=0);
2371 if(opcode2[i]==0x24) { // AND
2372 emit_and(s1l,s2l,tl);
2373 } else
2374 if(opcode2[i]==0x25) { // OR
2375 emit_or(s1l,s2l,tl);
2376 } else
2377 if(opcode2[i]==0x26) { // XOR
2378 emit_xor(s1l,s2l,tl);
2379 } else
2380 if(opcode2[i]==0x27) { // NOR
2381 emit_or(s1l,s2l,tl);
2382 emit_not(tl,tl);
2383 }
2384 }
2385 else
2386 {
2387 if(opcode2[i]==0x24) { // AND
2388 emit_zeroreg(tl);
2389 } else
2390 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2391 if(rs1[i]){
2392 if(s1l>=0) emit_mov(s1l,tl);
2393 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2394 }
2395 else
2396 if(rs2[i]){
2397 if(s2l>=0) emit_mov(s2l,tl);
2398 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2399 }
2400 else emit_zeroreg(tl);
2401 } else
2402 if(opcode2[i]==0x27) { // NOR
2403 if(rs1[i]){
2404 if(s1l>=0) emit_not(s1l,tl);
2405 else {
2406 emit_loadreg(rs1[i],tl);
2407 emit_not(tl,tl);
2408 }
2409 }
2410 else
2411 if(rs2[i]){
2412 if(s2l>=0) emit_not(s2l,tl);
2413 else {
2414 emit_loadreg(rs2[i],tl);
2415 emit_not(tl,tl);
2416 }
2417 }
2418 else emit_movimm(-1,tl);
2419 }
2420 }
2421 }
2422 }
2423 }
2424 }
2425}
2426
2427void imm16_assemble(int i,struct regstat *i_regs)
2428{
2429 if (opcode[i]==0x0f) { // LUI
2430 if(rt1[i]) {
2431 signed char t;
2432 t=get_reg(i_regs->regmap,rt1[i]);
2433 //assert(t>=0);
2434 if(t>=0) {
2435 if(!((i_regs->isconst>>t)&1))
2436 emit_movimm(imm[i]<<16,t);
2437 }
2438 }
2439 }
2440 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2441 if(rt1[i]) {
2442 signed char s,t;
2443 t=get_reg(i_regs->regmap,rt1[i]);
2444 s=get_reg(i_regs->regmap,rs1[i]);
2445 if(rs1[i]) {
2446 //assert(t>=0);
2447 //assert(s>=0);
2448 if(t>=0) {
2449 if(!((i_regs->isconst>>t)&1)) {
2450 if(s<0) {
2451 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2452 emit_addimm(t,imm[i],t);
2453 }else{
2454 if(!((i_regs->wasconst>>s)&1))
2455 emit_addimm(s,imm[i],t);
2456 else
2457 emit_movimm(constmap[i][s]+imm[i],t);
2458 }
2459 }
2460 }
2461 } else {
2462 if(t>=0) {
2463 if(!((i_regs->isconst>>t)&1))
2464 emit_movimm(imm[i],t);
2465 }
2466 }
2467 }
2468 }
2469 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2470 if(rt1[i]) {
2471 signed char sh,sl,th,tl;
2472 th=get_reg(i_regs->regmap,rt1[i]|64);
2473 tl=get_reg(i_regs->regmap,rt1[i]);
2474 sh=get_reg(i_regs->regmap,rs1[i]|64);
2475 sl=get_reg(i_regs->regmap,rs1[i]);
2476 if(tl>=0) {
2477 if(rs1[i]) {
2478 assert(sh>=0);
2479 assert(sl>=0);
2480 if(th>=0) {
2481 emit_addimm64_32(sh,sl,imm[i],th,tl);
2482 }
2483 else {
2484 emit_addimm(sl,imm[i],tl);
2485 }
2486 } else {
2487 emit_movimm(imm[i],tl);
2488 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2489 }
2490 }
2491 }
2492 }
2493 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2494 if(rt1[i]) {
2495 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2496 signed char sh,sl,t;
2497 t=get_reg(i_regs->regmap,rt1[i]);
2498 sh=get_reg(i_regs->regmap,rs1[i]|64);
2499 sl=get_reg(i_regs->regmap,rs1[i]);
2500 //assert(t>=0);
2501 if(t>=0) {
2502 if(rs1[i]>0) {
2503 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2504 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2505 if(opcode[i]==0x0a) { // SLTI
2506 if(sl<0) {
2507 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2508 emit_slti32(t,imm[i],t);
2509 }else{
2510 emit_slti32(sl,imm[i],t);
2511 }
2512 }
2513 else { // SLTIU
2514 if(sl<0) {
2515 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516 emit_sltiu32(t,imm[i],t);
2517 }else{
2518 emit_sltiu32(sl,imm[i],t);
2519 }
2520 }
2521 }else{ // 64-bit
2522 assert(sl>=0);
2523 if(opcode[i]==0x0a) // SLTI
2524 emit_slti64_32(sh,sl,imm[i],t);
2525 else // SLTIU
2526 emit_sltiu64_32(sh,sl,imm[i],t);
2527 }
2528 }else{
2529 // SLTI(U) with r0 is just stupid,
2530 // nonetheless examples can be found
2531 if(opcode[i]==0x0a) // SLTI
2532 if(0<imm[i]) emit_movimm(1,t);
2533 else emit_zeroreg(t);
2534 else // SLTIU
2535 {
2536 if(imm[i]) emit_movimm(1,t);
2537 else emit_zeroreg(t);
2538 }
2539 }
2540 }
2541 }
2542 }
2543 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2544 if(rt1[i]) {
2545 signed char sh,sl,th,tl;
2546 th=get_reg(i_regs->regmap,rt1[i]|64);
2547 tl=get_reg(i_regs->regmap,rt1[i]);
2548 sh=get_reg(i_regs->regmap,rs1[i]|64);
2549 sl=get_reg(i_regs->regmap,rs1[i]);
2550 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2551 if(opcode[i]==0x0c) //ANDI
2552 {
2553 if(rs1[i]) {
2554 if(sl<0) {
2555 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2556 emit_andimm(tl,imm[i],tl);
2557 }else{
2558 if(!((i_regs->wasconst>>sl)&1))
2559 emit_andimm(sl,imm[i],tl);
2560 else
2561 emit_movimm(constmap[i][sl]&imm[i],tl);
2562 }
2563 }
2564 else
2565 emit_zeroreg(tl);
2566 if(th>=0) emit_zeroreg(th);
2567 }
2568 else
2569 {
2570 if(rs1[i]) {
2571 if(sl<0) {
2572 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573 }
2574 if(th>=0) {
2575 if(sh<0) {
2576 emit_loadreg(rs1[i]|64,th);
2577 }else{
2578 emit_mov(sh,th);
2579 }
2580 }
2581 if(opcode[i]==0x0d) //ORI
2582 if(sl<0) {
2583 emit_orimm(tl,imm[i],tl);
2584 }else{
2585 if(!((i_regs->wasconst>>sl)&1))
2586 emit_orimm(sl,imm[i],tl);
2587 else
2588 emit_movimm(constmap[i][sl]|imm[i],tl);
2589 }
2590 if(opcode[i]==0x0e) //XORI
2591 if(sl<0) {
2592 emit_xorimm(tl,imm[i],tl);
2593 }else{
2594 if(!((i_regs->wasconst>>sl)&1))
2595 emit_xorimm(sl,imm[i],tl);
2596 else
2597 emit_movimm(constmap[i][sl]^imm[i],tl);
2598 }
2599 }
2600 else {
2601 emit_movimm(imm[i],tl);
2602 if(th>=0) emit_zeroreg(th);
2603 }
2604 }
2605 }
2606 }
2607 }
2608}
2609
2610void shiftimm_assemble(int i,struct regstat *i_regs)
2611{
2612 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2613 {
2614 if(rt1[i]) {
2615 signed char s,t;
2616 t=get_reg(i_regs->regmap,rt1[i]);
2617 s=get_reg(i_regs->regmap,rs1[i]);
2618 //assert(t>=0);
2619 if(t>=0){
2620 if(rs1[i]==0)
2621 {
2622 emit_zeroreg(t);
2623 }
2624 else
2625 {
2626 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2627 if(imm[i]) {
2628 if(opcode2[i]==0) // SLL
2629 {
2630 emit_shlimm(s<0?t:s,imm[i],t);
2631 }
2632 if(opcode2[i]==2) // SRL
2633 {
2634 emit_shrimm(s<0?t:s,imm[i],t);
2635 }
2636 if(opcode2[i]==3) // SRA
2637 {
2638 emit_sarimm(s<0?t:s,imm[i],t);
2639 }
2640 }else{
2641 // Shift by zero
2642 if(s>=0 && s!=t) emit_mov(s,t);
2643 }
2644 }
2645 }
2646 //emit_storereg(rt1[i],t); //DEBUG
2647 }
2648 }
2649 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2650 {
2651 if(rt1[i]) {
2652 signed char sh,sl,th,tl;
2653 th=get_reg(i_regs->regmap,rt1[i]|64);
2654 tl=get_reg(i_regs->regmap,rt1[i]);
2655 sh=get_reg(i_regs->regmap,rs1[i]|64);
2656 sl=get_reg(i_regs->regmap,rs1[i]);
2657 if(tl>=0) {
2658 if(rs1[i]==0)
2659 {
2660 emit_zeroreg(tl);
2661 if(th>=0) emit_zeroreg(th);
2662 }
2663 else
2664 {
2665 assert(sl>=0);
2666 assert(sh>=0);
2667 if(imm[i]) {
2668 if(opcode2[i]==0x38) // DSLL
2669 {
2670 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2671 emit_shlimm(sl,imm[i],tl);
2672 }
2673 if(opcode2[i]==0x3a) // DSRL
2674 {
2675 emit_shrdimm(sl,sh,imm[i],tl);
2676 if(th>=0) emit_shrimm(sh,imm[i],th);
2677 }
2678 if(opcode2[i]==0x3b) // DSRA
2679 {
2680 emit_shrdimm(sl,sh,imm[i],tl);
2681 if(th>=0) emit_sarimm(sh,imm[i],th);
2682 }
2683 }else{
2684 // Shift by zero
2685 if(sl!=tl) emit_mov(sl,tl);
2686 if(th>=0&&sh!=th) emit_mov(sh,th);
2687 }
2688 }
2689 }
2690 }
2691 }
2692 if(opcode2[i]==0x3c) // DSLL32
2693 {
2694 if(rt1[i]) {
2695 signed char sl,tl,th;
2696 tl=get_reg(i_regs->regmap,rt1[i]);
2697 th=get_reg(i_regs->regmap,rt1[i]|64);
2698 sl=get_reg(i_regs->regmap,rs1[i]);
2699 if(th>=0||tl>=0){
2700 assert(tl>=0);
2701 assert(th>=0);
2702 assert(sl>=0);
2703 emit_mov(sl,th);
2704 emit_zeroreg(tl);
2705 if(imm[i]>32)
2706 {
2707 emit_shlimm(th,imm[i]&31,th);
2708 }
2709 }
2710 }
2711 }
2712 if(opcode2[i]==0x3e) // DSRL32
2713 {
2714 if(rt1[i]) {
2715 signed char sh,tl,th;
2716 tl=get_reg(i_regs->regmap,rt1[i]);
2717 th=get_reg(i_regs->regmap,rt1[i]|64);
2718 sh=get_reg(i_regs->regmap,rs1[i]|64);
2719 if(tl>=0){
2720 assert(sh>=0);
2721 emit_mov(sh,tl);
2722 if(th>=0) emit_zeroreg(th);
2723 if(imm[i]>32)
2724 {
2725 emit_shrimm(tl,imm[i]&31,tl);
2726 }
2727 }
2728 }
2729 }
2730 if(opcode2[i]==0x3f) // DSRA32
2731 {
2732 if(rt1[i]) {
2733 signed char sh,tl;
2734 tl=get_reg(i_regs->regmap,rt1[i]);
2735 sh=get_reg(i_regs->regmap,rs1[i]|64);
2736 if(tl>=0){
2737 assert(sh>=0);
2738 emit_mov(sh,tl);
2739 if(imm[i]>32)
2740 {
2741 emit_sarimm(tl,imm[i]&31,tl);
2742 }
2743 }
2744 }
2745 }
2746}
2747
2748#ifndef shift_assemble
2749void shift_assemble(int i,struct regstat *i_regs)
2750{
2751 printf("Need shift_assemble for this architecture.\n");
2752 exit(1);
2753}
2754#endif
2755
2756void load_assemble(int i,struct regstat *i_regs)
2757{
2758 int s,th,tl,addr,map=-1;
2759 int offset;
2760 int jaddr=0;
5bf843dc 2761 int memtarget=0,c=0;
57871462 2762 u_int hr,reglist=0;
2763 th=get_reg(i_regs->regmap,rt1[i]|64);
2764 tl=get_reg(i_regs->regmap,rt1[i]);
2765 s=get_reg(i_regs->regmap,rs1[i]);
2766 offset=imm[i];
2767 for(hr=0;hr<HOST_REGS;hr++) {
2768 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2769 }
2770 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2771 if(s>=0) {
2772 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2773 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2774 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2775 }
57871462 2776 //printf("load_assemble: c=%d\n",c);
2777 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2778 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2779#ifdef PCSX
f18c0f46 2780 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2781 ||rt1[i]==0) {
5bf843dc 2782 // could be FIFO, must perform the read
f18c0f46 2783 // ||dummy read
5bf843dc 2784 assem_debug("(forced read)\n");
2785 tl=get_reg(i_regs->regmap,-1);
2786 assert(tl>=0);
5bf843dc 2787 }
f18c0f46 2788#endif
5bf843dc 2789 if(offset||s<0||c) addr=tl;
2790 else addr=s;
535d208a 2791 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2792 if(tl>=0) {
2793 //printf("load_assemble: c=%d\n",c);
2794 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2795 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2796 reglist&=~(1<<tl);
2797 if(th>=0) reglist&=~(1<<th);
2798 if(!using_tlb) {
2799 if(!c) {
2800 #ifdef RAM_OFFSET
2801 map=get_reg(i_regs->regmap,ROREG);
2802 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2803 #endif
57871462 2804//#define R29_HACK 1
535d208a 2805 #ifdef R29_HACK
2806 // Strmnnrmn's speed hack
2807 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2808 #endif
2809 {
2810 emit_cmpimm(addr,RAM_SIZE);
2811 jaddr=(int)out;
2812 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2813 // Hint to branch predictor that the branch is unlikely to be taken
2814 if(rs1[i]>=28)
2815 emit_jno_unlikely(0);
2816 else
57871462 2817 #endif
535d208a 2818 emit_jno(0);
57871462 2819 }
535d208a 2820 }
2821 }else{ // using tlb
2822 int x=0;
2823 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2824 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2825 map=get_reg(i_regs->regmap,TLREG);
2826 assert(map>=0);
2827 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2828 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2829 }
2830 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2831 if (opcode[i]==0x20) { // LB
2832 if(!c||memtarget) {
2833 if(!dummy) {
57871462 2834 #ifdef HOST_IMM_ADDR32
2835 if(c)
2836 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2837 else
2838 #endif
2839 {
2840 //emit_xorimm(addr,3,tl);
2841 //gen_tlb_addr_r(tl,map);
2842 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2843 int x=0,a=tl;
2002a1db 2844#ifdef BIG_ENDIAN_MIPS
57871462 2845 if(!c) emit_xorimm(addr,3,tl);
2846 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2847#else
535d208a 2848 if(!c) a=addr;
2002a1db 2849#endif
535d208a 2850 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2851 }
57871462 2852 }
535d208a 2853 if(jaddr)
2854 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2855 }
535d208a 2856 else
2857 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2858 }
2859 if (opcode[i]==0x21) { // LH
2860 if(!c||memtarget) {
2861 if(!dummy) {
57871462 2862 #ifdef HOST_IMM_ADDR32
2863 if(c)
2864 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2865 else
2866 #endif
2867 {
535d208a 2868 int x=0,a=tl;
2002a1db 2869#ifdef BIG_ENDIAN_MIPS
57871462 2870 if(!c) emit_xorimm(addr,2,tl);
2871 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2872#else
535d208a 2873 if(!c) a=addr;
2002a1db 2874#endif
57871462 2875 //#ifdef
2876 //emit_movswl_indexed_tlb(x,tl,map,tl);
2877 //else
2878 if(map>=0) {
535d208a 2879 gen_tlb_addr_r(a,map);
2880 emit_movswl_indexed(x,a,tl);
2881 }else{
2882 #ifdef RAM_OFFSET
2883 emit_movswl_indexed(x,a,tl);
2884 #else
2885 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2886 #endif
2887 }
57871462 2888 }
57871462 2889 }
535d208a 2890 if(jaddr)
2891 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2892 }
535d208a 2893 else
2894 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2895 }
2896 if (opcode[i]==0x23) { // LW
2897 if(!c||memtarget) {
2898 if(!dummy) {
57871462 2899 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2900 #ifdef HOST_IMM_ADDR32
2901 if(c)
2902 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2903 else
2904 #endif
2905 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2906 }
535d208a 2907 if(jaddr)
2908 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2909 }
535d208a 2910 else
2911 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2912 }
2913 if (opcode[i]==0x24) { // LBU
2914 if(!c||memtarget) {
2915 if(!dummy) {
57871462 2916 #ifdef HOST_IMM_ADDR32
2917 if(c)
2918 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2919 else
2920 #endif
2921 {
2922 //emit_xorimm(addr,3,tl);
2923 //gen_tlb_addr_r(tl,map);
2924 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2925 int x=0,a=tl;
2002a1db 2926#ifdef BIG_ENDIAN_MIPS
57871462 2927 if(!c) emit_xorimm(addr,3,tl);
2928 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2929#else
535d208a 2930 if(!c) a=addr;
2002a1db 2931#endif
535d208a 2932 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2933 }
57871462 2934 }
535d208a 2935 if(jaddr)
2936 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2937 }
535d208a 2938 else
2939 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940 }
2941 if (opcode[i]==0x25) { // LHU
2942 if(!c||memtarget) {
2943 if(!dummy) {
57871462 2944 #ifdef HOST_IMM_ADDR32
2945 if(c)
2946 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2947 else
2948 #endif
2949 {
535d208a 2950 int x=0,a=tl;
2002a1db 2951#ifdef BIG_ENDIAN_MIPS
57871462 2952 if(!c) emit_xorimm(addr,2,tl);
2953 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2954#else
535d208a 2955 if(!c) a=addr;
2002a1db 2956#endif
57871462 2957 //#ifdef
2958 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2959 //#else
2960 if(map>=0) {
535d208a 2961 gen_tlb_addr_r(a,map);
2962 emit_movzwl_indexed(x,a,tl);
2963 }else{
2964 #ifdef RAM_OFFSET
2965 emit_movzwl_indexed(x,a,tl);
2966 #else
2967 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2968 #endif
2969 }
57871462 2970 }
2971 }
535d208a 2972 if(jaddr)
2973 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2974 }
535d208a 2975 else
2976 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2977 }
2978 if (opcode[i]==0x27) { // LWU
2979 assert(th>=0);
2980 if(!c||memtarget) {
2981 if(!dummy) {
57871462 2982 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2983 #ifdef HOST_IMM_ADDR32
2984 if(c)
2985 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2986 else
2987 #endif
2988 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2989 }
535d208a 2990 if(jaddr)
2991 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2992 }
2993 else {
2994 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2995 }
535d208a 2996 emit_zeroreg(th);
2997 }
2998 if (opcode[i]==0x37) { // LD
2999 if(!c||memtarget) {
3000 if(!dummy) {
57871462 3001 //gen_tlb_addr_r(tl,map);
3002 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3003 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3004 #ifdef HOST_IMM_ADDR32
3005 if(c)
3006 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3007 else
3008 #endif
3009 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 3010 }
535d208a 3011 if(jaddr)
3012 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3013 }
535d208a 3014 else
3015 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3016 }
535d208a 3017 }
3018 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3019 //if(opcode[i]==0x23)
3020 //if(opcode[i]==0x24)
3021 //if(opcode[i]==0x23||opcode[i]==0x24)
3022 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3023 {
3024 //emit_pusha();
3025 save_regs(0x100f);
3026 emit_readword((int)&last_count,ECX);
3027 #ifdef __i386__
3028 if(get_reg(i_regs->regmap,CCREG)<0)
3029 emit_loadreg(CCREG,HOST_CCREG);
3030 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3031 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3032 emit_writeword(HOST_CCREG,(int)&Count);
3033 #endif
3034 #ifdef __arm__
3035 if(get_reg(i_regs->regmap,CCREG)<0)
3036 emit_loadreg(CCREG,0);
3037 else
3038 emit_mov(HOST_CCREG,0);
3039 emit_add(0,ECX,0);
3040 emit_addimm(0,2*ccadj[i],0);
3041 emit_writeword(0,(int)&Count);
3042 #endif
3043 emit_call((int)memdebug);
3044 //emit_popa();
3045 restore_regs(0x100f);
3046 }/**/
3047}
3048
3049#ifndef loadlr_assemble
3050void loadlr_assemble(int i,struct regstat *i_regs)
3051{
3052 printf("Need loadlr_assemble for this architecture.\n");
3053 exit(1);
3054}
3055#endif
3056
3057void store_assemble(int i,struct regstat *i_regs)
3058{
3059 int s,th,tl,map=-1;
3060 int addr,temp;
3061 int offset;
3062 int jaddr=0,jaddr2,type;
666a299d 3063 int memtarget=0,c=0;
57871462 3064 int agr=AGEN1+(i&1);
3065 u_int hr,reglist=0;
3066 th=get_reg(i_regs->regmap,rs2[i]|64);
3067 tl=get_reg(i_regs->regmap,rs2[i]);
3068 s=get_reg(i_regs->regmap,rs1[i]);
3069 temp=get_reg(i_regs->regmap,agr);
3070 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3071 offset=imm[i];
3072 if(s>=0) {
3073 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3074 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3075 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3076 }
3077 assert(tl>=0);
3078 assert(temp>=0);
3079 for(hr=0;hr<HOST_REGS;hr++) {
3080 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3081 }
3082 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3083 if(offset||s<0||c) addr=temp;
3084 else addr=s;
3085 if(!using_tlb) {
3086 if(!c) {
3087 #ifdef R29_HACK
3088 // Strmnnrmn's speed hack
3089 memtarget=1;
4cb76aa4 3090 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3091 #endif
4cb76aa4 3092 emit_cmpimm(addr,RAM_SIZE);
57871462 3093 #ifdef DESTRUCTIVE_SHIFT
3094 if(s==addr) emit_mov(s,temp);
3095 #endif
3096 #ifdef R29_HACK
4cb76aa4 3097 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3098 #endif
3099 {
3100 jaddr=(int)out;
3101 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3102 // Hint to branch predictor that the branch is unlikely to be taken
3103 if(rs1[i]>=28)
3104 emit_jno_unlikely(0);
3105 else
3106 #endif
3107 emit_jno(0);
3108 }
3109 }
3110 }else{ // using tlb
3111 int x=0;
3112 if (opcode[i]==0x28) x=3; // SB
3113 if (opcode[i]==0x29) x=2; // SH
3114 map=get_reg(i_regs->regmap,TLREG);
3115 assert(map>=0);
3116 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3117 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3118 }
3119
3120 if (opcode[i]==0x28) { // SB
3121 if(!c||memtarget) {
3122 int x=0;
2002a1db 3123#ifdef BIG_ENDIAN_MIPS
57871462 3124 if(!c) emit_xorimm(addr,3,temp);
3125 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3126#else
3127 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3128 else if (addr!=temp) emit_mov(addr,temp);
3129#endif
57871462 3130 //gen_tlb_addr_w(temp,map);
3131 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3132 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3133 }
3134 type=STOREB_STUB;
3135 }
3136 if (opcode[i]==0x29) { // SH
3137 if(!c||memtarget) {
3138 int x=0;
2002a1db 3139#ifdef BIG_ENDIAN_MIPS
57871462 3140 if(!c) emit_xorimm(addr,2,temp);
3141 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3142#else
3143 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3144 else if (addr!=temp) emit_mov(addr,temp);
3145#endif
57871462 3146 //#ifdef
3147 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3148 //#else
3149 if(map>=0) {
3150 gen_tlb_addr_w(temp,map);
3151 emit_writehword_indexed(tl,x,temp);
3152 }else
3153 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3154 }
3155 type=STOREH_STUB;
3156 }
3157 if (opcode[i]==0x2B) { // SW
3158 if(!c||memtarget)
3159 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3160 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3161 type=STOREW_STUB;
3162 }
3163 if (opcode[i]==0x3F) { // SD
3164 if(!c||memtarget) {
3165 if(rs2[i]) {
3166 assert(th>=0);
3167 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3168 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3169 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3170 }else{
3171 // Store zero
3172 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3173 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3174 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3175 }
3176 }
3177 type=STORED_STUB;
3178 }
666a299d 3179 if(!using_tlb&&(!c||memtarget))
3180 // addr could be a temp, make sure it survives STORE*_STUB
3181 reglist|=1<<addr;
57871462 3182 if(jaddr) {
3183 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3184 } else if(!memtarget) {
3185 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3186 }
3187 if(!using_tlb) {
3188 if(!c||memtarget) {
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3192 addr=temp;
3193 #endif
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3196 assert(ir>=0);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198 #else
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200 #endif
3201 jaddr2=(int)out;
3202 emit_jne(0);
3203 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3204 }
3205 }
3206 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3207 //if(opcode[i]==0x2B || opcode[i]==0x28)
3208 //if(opcode[i]==0x2B || opcode[i]==0x29)
3209 //if(opcode[i]==0x2B)
3210 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3211 {
3212 //emit_pusha();
3213 save_regs(0x100f);
3214 emit_readword((int)&last_count,ECX);
3215 #ifdef __i386__
3216 if(get_reg(i_regs->regmap,CCREG)<0)
3217 emit_loadreg(CCREG,HOST_CCREG);
3218 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3219 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3220 emit_writeword(HOST_CCREG,(int)&Count);
3221 #endif
3222 #ifdef __arm__
3223 if(get_reg(i_regs->regmap,CCREG)<0)
3224 emit_loadreg(CCREG,0);
3225 else
3226 emit_mov(HOST_CCREG,0);
3227 emit_add(0,ECX,0);
3228 emit_addimm(0,2*ccadj[i],0);
3229 emit_writeword(0,(int)&Count);
3230 #endif
3231 emit_call((int)memdebug);
3232 //emit_popa();
3233 restore_regs(0x100f);
3234 }/**/
3235}
3236
3237void storelr_assemble(int i,struct regstat *i_regs)
3238{
3239 int s,th,tl;
3240 int temp;
3241 int temp2;
3242 int offset;
3243 int jaddr=0,jaddr2;
3244 int case1,case2,case3;
3245 int done0,done1,done2;
3246 int memtarget,c=0;
fab5d06d 3247 int agr=AGEN1+(i&1);
57871462 3248 u_int hr,reglist=0;
3249 th=get_reg(i_regs->regmap,rs2[i]|64);
3250 tl=get_reg(i_regs->regmap,rs2[i]);
3251 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3252 temp=get_reg(i_regs->regmap,agr);
3253 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3254 offset=imm[i];
3255 if(s>=0) {
3256 c=(i_regs->isconst>>s)&1;
4cb76aa4 3257 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3258 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3259 }
3260 assert(tl>=0);
3261 for(hr=0;hr<HOST_REGS;hr++) {
3262 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3263 }
535d208a 3264 assert(temp>=0);
3265 if(!using_tlb) {
3266 if(!c) {
3267 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3268 if(!offset&&s!=temp) emit_mov(s,temp);
3269 jaddr=(int)out;
3270 emit_jno(0);
3271 }
3272 else
3273 {
3274 if(!memtarget||!rs1[i]) {
57871462 3275 jaddr=(int)out;
3276 emit_jmp(0);
3277 }
57871462 3278 }
535d208a 3279 #ifdef RAM_OFFSET
3280 int map=get_reg(i_regs->regmap,ROREG);
3281 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3282 gen_tlb_addr_w(temp,map);
3283 #else
3284 if((u_int)rdram!=0x80000000)
3285 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3286 #endif
3287 }else{ // using tlb
3288 int map=get_reg(i_regs->regmap,TLREG);
3289 assert(map>=0);
3290 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3291 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3292 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3293 if(!jaddr&&!memtarget) {
3294 jaddr=(int)out;
3295 emit_jmp(0);
57871462 3296 }
535d208a 3297 gen_tlb_addr_w(temp,map);
3298 }
3299
3300 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3301 temp2=get_reg(i_regs->regmap,FTEMP);
3302 if(!rs2[i]) temp2=th=tl;
3303 }
57871462 3304
2002a1db 3305#ifndef BIG_ENDIAN_MIPS
3306 emit_xorimm(temp,3,temp);
3307#endif
535d208a 3308 emit_testimm(temp,2);
3309 case2=(int)out;
3310 emit_jne(0);
3311 emit_testimm(temp,1);
3312 case1=(int)out;
3313 emit_jne(0);
3314 // 0
3315 if (opcode[i]==0x2A) { // SWL
3316 emit_writeword_indexed(tl,0,temp);
3317 }
3318 if (opcode[i]==0x2E) { // SWR
3319 emit_writebyte_indexed(tl,3,temp);
3320 }
3321 if (opcode[i]==0x2C) { // SDL
3322 emit_writeword_indexed(th,0,temp);
3323 if(rs2[i]) emit_mov(tl,temp2);
3324 }
3325 if (opcode[i]==0x2D) { // SDR
3326 emit_writebyte_indexed(tl,3,temp);
3327 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3328 }
3329 done0=(int)out;
3330 emit_jmp(0);
3331 // 1
3332 set_jump_target(case1,(int)out);
3333 if (opcode[i]==0x2A) { // SWL
3334 // Write 3 msb into three least significant bytes
3335 if(rs2[i]) emit_rorimm(tl,8,tl);
3336 emit_writehword_indexed(tl,-1,temp);
3337 if(rs2[i]) emit_rorimm(tl,16,tl);
3338 emit_writebyte_indexed(tl,1,temp);
3339 if(rs2[i]) emit_rorimm(tl,8,tl);
3340 }
3341 if (opcode[i]==0x2E) { // SWR
3342 // Write two lsb into two most significant bytes
3343 emit_writehword_indexed(tl,1,temp);
3344 }
3345 if (opcode[i]==0x2C) { // SDL
3346 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3347 // Write 3 msb into three least significant bytes
3348 if(rs2[i]) emit_rorimm(th,8,th);
3349 emit_writehword_indexed(th,-1,temp);
3350 if(rs2[i]) emit_rorimm(th,16,th);
3351 emit_writebyte_indexed(th,1,temp);
3352 if(rs2[i]) emit_rorimm(th,8,th);
3353 }
3354 if (opcode[i]==0x2D) { // SDR
3355 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3356 // Write two lsb into two most significant bytes
3357 emit_writehword_indexed(tl,1,temp);
3358 }
3359 done1=(int)out;
3360 emit_jmp(0);
3361 // 2
3362 set_jump_target(case2,(int)out);
3363 emit_testimm(temp,1);
3364 case3=(int)out;
3365 emit_jne(0);
3366 if (opcode[i]==0x2A) { // SWL
3367 // Write two msb into two least significant bytes
3368 if(rs2[i]) emit_rorimm(tl,16,tl);
3369 emit_writehword_indexed(tl,-2,temp);
3370 if(rs2[i]) emit_rorimm(tl,16,tl);
3371 }
3372 if (opcode[i]==0x2E) { // SWR
3373 // Write 3 lsb into three most significant bytes
3374 emit_writebyte_indexed(tl,-1,temp);
3375 if(rs2[i]) emit_rorimm(tl,8,tl);
3376 emit_writehword_indexed(tl,0,temp);
3377 if(rs2[i]) emit_rorimm(tl,24,tl);
3378 }
3379 if (opcode[i]==0x2C) { // SDL
3380 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3381 // Write two msb into two least significant bytes
3382 if(rs2[i]) emit_rorimm(th,16,th);
3383 emit_writehword_indexed(th,-2,temp);