drc: merge Ari64's patch: 07_clear_cache
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
1e973cb0 182#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 183
184 /* stubs */
185#define CC_STUB 1
186#define FP_STUB 2
187#define LOADB_STUB 3
188#define LOADH_STUB 4
189#define LOADW_STUB 5
190#define LOADD_STUB 6
191#define LOADBU_STUB 7
192#define LOADHU_STUB 8
193#define STOREB_STUB 9
194#define STOREH_STUB 10
195#define STOREW_STUB 11
196#define STORED_STUB 12
197#define STORELR_STUB 13
198#define INVCODE_STUB 14
199
200 /* branch codes */
201#define TAKEN 1
202#define NOTTAKEN 2
203#define NULLDS 3
204
205// asm linkage
206int new_recompile_block(int addr);
207void *get_addr_ht(u_int vaddr);
208void invalidate_block(u_int block);
209void invalidate_addr(u_int addr);
210void remove_hash(int vaddr);
211void jump_vaddr();
212void dyna_linker();
213void dyna_linker_ds();
214void verify_code();
215void verify_code_vm();
216void verify_code_ds();
217void cc_interrupt();
218void fp_exception();
219void fp_exception_ds();
220void jump_syscall();
7139f3c8 221void jump_syscall_hle();
57871462 222void jump_eret();
7139f3c8 223void jump_hlecall();
1e973cb0 224void jump_intcall();
7139f3c8 225void new_dyna_leave();
57871462 226
227// TLB
228void TLBWI_new();
229void TLBWR_new();
230void read_nomem_new();
231void read_nomemb_new();
232void read_nomemh_new();
233void read_nomemd_new();
234void write_nomem_new();
235void write_nomemb_new();
236void write_nomemh_new();
237void write_nomemd_new();
238void write_rdram_new();
239void write_rdramb_new();
240void write_rdramh_new();
241void write_rdramd_new();
242extern u_int memory_map[1048576];
243
244// Needed by assembler
245void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248void load_all_regs(signed char i_regmap[]);
249void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250void load_regs_entry(int t);
251void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253int tracedebug=0;
254
255//#define DEBUG_CYCLE_COUNT 1
256
257void nullf() {}
258//#define assem_debug printf
259//#define inv_debug printf
260#define assem_debug nullf
261#define inv_debug nullf
262
94d23bb9 263static void tlb_hacks()
57871462 264{
94d23bb9 265#ifndef DISABLE_TLB
57871462 266 // Goldeneye hack
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268 {
269 u_int addr;
270 int n;
271 switch (ROM_HEADER->Country_code&0xFF)
272 {
273 case 0x45: // U
274 addr=0x34b30;
275 break;
276 case 0x4A: // J
277 addr=0x34b70;
278 break;
279 case 0x50: // E
280 addr=0x329f0;
281 break;
282 default:
283 // Unknown country code
284 addr=0;
285 break;
286 }
287 u_int rom_addr=(u_int)rom;
288 #ifdef ROM_COPY
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
299 }
300 #endif
301 if(addr) {
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304 }
305 }
306 }
94d23bb9 307#endif
57871462 308}
309
94d23bb9 310static u_int get_page(u_int vaddr)
57871462 311{
0ce47d46 312#ifndef PCSX
57871462 313 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 314#else
315 u_int page=vaddr&~0xe0000000;
316 if (page < 0x1000000)
317 page &= ~0x0e00000; // RAM mirrors
318 page>>=12;
319#endif
94d23bb9 320#ifndef DISABLE_TLB
57871462 321 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 322#endif
57871462 323 if(page>2048) page=2048+(page&2047);
94d23bb9 324 return page;
325}
326
327static u_int get_vpage(u_int vaddr)
328{
329 u_int vpage=(vaddr^0x80000000)>>12;
330#ifndef DISABLE_TLB
57871462 331 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 332#endif
57871462 333 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 334 return vpage;
335}
336
337// Get address from virtual address
338// This is called from the recompiled JR/JALR instructions
339void *get_addr(u_int vaddr)
340{
341 u_int page=get_page(vaddr);
342 u_int vpage=get_vpage(vaddr);
57871462 343 struct ll_entry *head;
344 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
345 head=jump_in[page];
346 while(head!=NULL) {
347 if(head->vaddr==vaddr&&head->reg32==0) {
348 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
349 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
350 ht_bin[3]=ht_bin[1];
351 ht_bin[2]=ht_bin[0];
352 ht_bin[1]=(int)head->addr;
353 ht_bin[0]=vaddr;
354 return head->addr;
355 }
356 head=head->next;
357 }
358 head=jump_dirty[vpage];
359 while(head!=NULL) {
360 if(head->vaddr==vaddr&&head->reg32==0) {
361 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
362 // Don't restore blocks which are about to expire from the cache
363 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
364 if(verify_dirty(head->addr)) {
365 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
366 invalid_code[vaddr>>12]=0;
367 memory_map[vaddr>>12]|=0x40000000;
368 if(vpage<2048) {
94d23bb9 369#ifndef DISABLE_TLB
57871462 370 if(tlb_LUT_r[vaddr>>12]) {
371 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
372 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
373 }
94d23bb9 374#endif
57871462 375 restore_candidate[vpage>>3]|=1<<(vpage&7);
376 }
377 else restore_candidate[page>>3]|=1<<(page&7);
378 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
379 if(ht_bin[0]==vaddr) {
380 ht_bin[1]=(int)head->addr; // Replace existing entry
381 }
382 else
383 {
384 ht_bin[3]=ht_bin[1];
385 ht_bin[2]=ht_bin[0];
386 ht_bin[1]=(int)head->addr;
387 ht_bin[0]=vaddr;
388 }
389 return head->addr;
390 }
391 }
392 head=head->next;
393 }
394 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
395 int r=new_recompile_block(vaddr);
396 if(r==0) return get_addr(vaddr);
397 // Execute in unmapped page, generate pagefault execption
398 Status|=2;
399 Cause=(vaddr<<31)|0x8;
400 EPC=(vaddr&1)?vaddr-5:vaddr;
401 BadVAddr=(vaddr&~1);
402 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
403 EntryHi=BadVAddr&0xFFFFE000;
404 return get_addr_ht(0x80000000);
405}
406// Look up address in hash table first
407void *get_addr_ht(u_int vaddr)
408{
409 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
410 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
411 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
412 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
413 return get_addr(vaddr);
414}
415
416void *get_addr_32(u_int vaddr,u_int flags)
417{
7139f3c8 418#ifdef FORCE32
419 return get_addr(vaddr);
560e4a12 420#else
57871462 421 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 425 u_int page=get_page(vaddr);
426 u_int vpage=get_vpage(vaddr);
57871462 427 struct ll_entry *head;
428 head=jump_in[page];
429 while(head!=NULL) {
430 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
431 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
432 if(head->reg32==0) {
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434 if(ht_bin[0]==-1) {
435 ht_bin[1]=(int)head->addr;
436 ht_bin[0]=vaddr;
437 }else if(ht_bin[2]==-1) {
438 ht_bin[3]=(int)head->addr;
439 ht_bin[2]=vaddr;
440 }
441 //ht_bin[3]=ht_bin[1];
442 //ht_bin[2]=ht_bin[0];
443 //ht_bin[1]=(int)head->addr;
444 //ht_bin[0]=vaddr;
445 }
446 return head->addr;
447 }
448 head=head->next;
449 }
450 head=jump_dirty[vpage];
451 while(head!=NULL) {
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 // Don't restore blocks which are about to expire from the cache
455 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
456 if(verify_dirty(head->addr)) {
457 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
458 invalid_code[vaddr>>12]=0;
459 memory_map[vaddr>>12]|=0x40000000;
460 if(vpage<2048) {
94d23bb9 461#ifndef DISABLE_TLB
57871462 462 if(tlb_LUT_r[vaddr>>12]) {
463 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
464 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
465 }
94d23bb9 466#endif
57871462 467 restore_candidate[vpage>>3]|=1<<(vpage&7);
468 }
469 else restore_candidate[page>>3]|=1<<(page&7);
470 if(head->reg32==0) {
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472 if(ht_bin[0]==-1) {
473 ht_bin[1]=(int)head->addr;
474 ht_bin[0]=vaddr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
477 ht_bin[2]=vaddr;
478 }
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
482 //ht_bin[0]=vaddr;
483 }
484 return head->addr;
485 }
486 }
487 head=head->next;
488 }
489 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
490 int r=new_recompile_block(vaddr);
491 if(r==0) return get_addr(vaddr);
492 // Execute in unmapped page, generate pagefault execption
493 Status|=2;
494 Cause=(vaddr<<31)|0x8;
495 EPC=(vaddr&1)?vaddr-5:vaddr;
496 BadVAddr=(vaddr&~1);
497 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
498 EntryHi=BadVAddr&0xFFFFE000;
499 return get_addr_ht(0x80000000);
560e4a12 500#endif
57871462 501}
502
503void clear_all_regs(signed char regmap[])
504{
505 int hr;
506 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
507}
508
509signed char get_reg(signed char regmap[],int r)
510{
511 int hr;
512 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
513 return -1;
514}
515
516// Find a register that is available for two consecutive cycles
517signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
518{
519 int hr;
520 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
521 return -1;
522}
523
524int count_free_regs(signed char regmap[])
525{
526 int count=0;
527 int hr;
528 for(hr=0;hr<HOST_REGS;hr++)
529 {
530 if(hr!=EXCLUDE_REG) {
531 if(regmap[hr]<0) count++;
532 }
533 }
534 return count;
535}
536
537void dirty_reg(struct regstat *cur,signed char reg)
538{
539 int hr;
540 if(!reg) return;
541 for (hr=0;hr<HOST_REGS;hr++) {
542 if((cur->regmap[hr]&63)==reg) {
543 cur->dirty|=1<<hr;
544 }
545 }
546}
547
548// If we dirty the lower half of a 64 bit register which is now being
549// sign-extended, we need to dump the upper half.
550// Note: Do this only after completion of the instruction, because
551// some instructions may need to read the full 64-bit value even if
552// overwriting it (eg SLTI, DSRA32).
553static void flush_dirty_uppers(struct regstat *cur)
554{
555 int hr,reg;
556 for (hr=0;hr<HOST_REGS;hr++) {
557 if((cur->dirty>>hr)&1) {
558 reg=cur->regmap[hr];
559 if(reg>=64)
560 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
561 }
562 }
563}
564
565void set_const(struct regstat *cur,signed char reg,uint64_t value)
566{
567 int hr;
568 if(!reg) return;
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if(cur->regmap[hr]==reg) {
571 cur->isconst|=1<<hr;
572 cur->constmap[hr]=value;
573 }
574 else if((cur->regmap[hr]^64)==reg) {
575 cur->isconst|=1<<hr;
576 cur->constmap[hr]=value>>32;
577 }
578 }
579}
580
581void clear_const(struct regstat *cur,signed char reg)
582{
583 int hr;
584 if(!reg) return;
585 for (hr=0;hr<HOST_REGS;hr++) {
586 if((cur->regmap[hr]&63)==reg) {
587 cur->isconst&=~(1<<hr);
588 }
589 }
590}
591
592int is_const(struct regstat *cur,signed char reg)
593{
594 int hr;
595 if(!reg) return 1;
596 for (hr=0;hr<HOST_REGS;hr++) {
597 if((cur->regmap[hr]&63)==reg) {
598 return (cur->isconst>>hr)&1;
599 }
600 }
601 return 0;
602}
603uint64_t get_const(struct regstat *cur,signed char reg)
604{
605 int hr;
606 if(!reg) return 0;
607 for (hr=0;hr<HOST_REGS;hr++) {
608 if(cur->regmap[hr]==reg) {
609 return cur->constmap[hr];
610 }
611 }
612 printf("Unknown constant in r%d\n",reg);
613 exit(1);
614}
615
616// Least soon needed registers
617// Look at the next ten instructions and see which registers
618// will be used. Try not to reallocate these.
619void lsn(u_char hsn[], int i, int *preferred_reg)
620{
621 int j;
622 int b=-1;
623 for(j=0;j<9;j++)
624 {
625 if(i+j>=slen) {
626 j=slen-i-1;
627 break;
628 }
629 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
630 {
631 // Don't go past an unconditonal jump
632 j++;
633 break;
634 }
635 }
636 for(;j>=0;j--)
637 {
638 if(rs1[i+j]) hsn[rs1[i+j]]=j;
639 if(rs2[i+j]) hsn[rs2[i+j]]=j;
640 if(rt1[i+j]) hsn[rt1[i+j]]=j;
641 if(rt2[i+j]) hsn[rt2[i+j]]=j;
642 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
643 // Stores can allocate zero
644 hsn[rs1[i+j]]=j;
645 hsn[rs2[i+j]]=j;
646 }
647 // On some architectures stores need invc_ptr
648 #if defined(HOST_IMM8)
b9b61529 649 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 650 hsn[INVCP]=j;
651 }
652 #endif
653 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 {
655 hsn[CCREG]=j;
656 b=j;
657 }
658 }
659 if(b>=0)
660 {
661 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
662 {
663 // Follow first branch
664 int t=(ba[i+b]-start)>>2;
665 j=7-b;if(t+j>=slen) j=slen-t-1;
666 for(;j>=0;j--)
667 {
668 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
669 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
670 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
671 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
672 }
673 }
674 // TODO: preferred register based on backward branch
675 }
676 // Delay slot should preferably not overwrite branch conditions or cycle count
677 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
678 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
679 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
680 hsn[CCREG]=1;
681 // ...or hash tables
682 hsn[RHASH]=1;
683 hsn[RHTBL]=1;
684 }
685 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 686 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 687 hsn[FTEMP]=0;
688 }
689 // Load L/R also uses FTEMP as a temporary register
690 if(itype[i]==LOADLR) {
691 hsn[FTEMP]=0;
692 }
b7918751 693 // Also SWL/SWR/SDL/SDR
694 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Don't remove the TLB registers either
b9b61529 698 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 699 hsn[TLREG]=0;
700 }
701 // Don't remove the miniht registers
702 if(itype[i]==UJUMP||itype[i]==RJUMP)
703 {
704 hsn[RHASH]=0;
705 hsn[RHTBL]=0;
706 }
707}
708
709// We only want to allocate registers if we're going to use them again soon
710int needed_again(int r, int i)
711{
712 int j;
713 int b=-1;
714 int rn=10;
715 int hr;
716 u_char hsn[MAXREG+1];
717 int preferred_reg;
718
719 memset(hsn,10,sizeof(hsn));
720 lsn(hsn,i,&preferred_reg);
721
722 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
723 {
724 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
725 return 0; // Don't need any registers if exiting the block
726 }
727 for(j=0;j<9;j++)
728 {
729 if(i+j>=slen) {
730 j=slen-i-1;
731 break;
732 }
733 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
734 {
735 // Don't go past an unconditonal jump
736 j++;
737 break;
738 }
1e973cb0 739 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 740 {
741 break;
742 }
743 }
744 for(;j>=1;j--)
745 {
746 if(rs1[i+j]==r) rn=j;
747 if(rs2[i+j]==r) rn=j;
748 if((unneeded_reg[i+j]>>r)&1) rn=10;
749 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 {
751 b=j;
752 }
753 }
754 /*
755 if(b>=0)
756 {
757 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
758 {
759 // Follow first branch
760 int o=rn;
761 int t=(ba[i+b]-start)>>2;
762 j=7-b;if(t+j>=slen) j=slen-t-1;
763 for(;j>=0;j--)
764 {
765 if(!((unneeded_reg[t+j]>>r)&1)) {
766 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
767 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
768 }
769 else rn=o;
770 }
771 }
772 }*/
773 for(hr=0;hr<HOST_REGS;hr++) {
774 if(hr!=EXCLUDE_REG) {
775 if(rn<hsn[hr]) return 1;
776 }
777 }
778 return 0;
779}
780
781// Try to match register allocations at the end of a loop with those
782// at the beginning
783int loop_reg(int i, int r, int hr)
784{
785 int j,k;
786 for(j=0;j<9;j++)
787 {
788 if(i+j>=slen) {
789 j=slen-i-1;
790 break;
791 }
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
793 {
794 // Don't go past an unconditonal jump
795 j++;
796 break;
797 }
798 }
799 k=0;
800 if(i>0){
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
802 k--;
803 }
804 for(;k<j;k++)
805 {
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
809 {
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
811 {
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
817 }
818 }
819 }
820 return hr;
821}
822
823
824// Allocate every register, preserving source/target regs
825void alloc_all(struct regstat *cur,int i)
826{
827 int hr;
828
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 {
834 cur->regmap[hr]=-1;
835 cur->dirty&=~(1<<hr);
836 }
837 // Don't need zeros
838 if((cur->regmap[hr]&63)==0)
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 }
844 }
845}
846
847
848void div64(int64_t dividend,int64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855void divu64(uint64_t dividend,uint64_t divisor)
856{
857 lo=dividend/divisor;
858 hi=dividend%divisor;
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861}
862
863void mult64(uint64_t m1,uint64_t m2)
864{
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
868 int sign = 0;
869
870 if (m1 < 0)
871 {
872 op2 = -m1;
873 sign = 1 - sign;
874 }
875 else op2 = m1;
876 if (m2 < 0)
877 {
878 op4 = -m2;
879 sign = 1 - sign;
880 }
881 else op4 = m2;
882
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
887
888 temp1 = op1 * op3;
889 temp2 = (temp1 >> 32) + op1 * op4;
890 temp3 = op2 * op3;
891 temp4 = (temp3 >> 32) + op2 * op4;
892
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
897
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
900 if (sign)
901 {
902 hi = ~hi;
903 if (!lo) hi++;
904 else lo = ~lo + 1;
905 }
906}
907
908void multu64(uint64_t m1,uint64_t m2)
909{
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
913
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
918
919 temp1 = op1 * op3;
920 temp2 = (temp1 >> 32) + op1 * op4;
921 temp3 = op2 * op3;
922 temp4 = (temp3 >> 32) + op2 * op4;
923
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
928
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
931
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934}
935
936uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937{
938 if(bits) {
939 original<<=64-bits;
940 original>>=64-bits;
941 loaded<<=bits;
942 original|=loaded;
943 }
944 else original=loaded;
945 return original;
946}
947uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948{
949 if(bits^56) {
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
952 loaded>>=bits^56;
953 original|=loaded;
954 }
955 else original=loaded;
956 return original;
957}
958
959#ifdef __i386__
960#include "assem_x86.c"
961#endif
962#ifdef __x86_64__
963#include "assem_x64.c"
964#endif
965#ifdef __arm__
966#include "assem_arm.c"
967#endif
968
969// Add virtual address mapping to linked list
970void ll_add(struct ll_entry **head,int vaddr,void *addr)
971{
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
976 new_entry->reg32=0;
977 new_entry->addr=addr;
978 new_entry->next=*head;
979 *head=new_entry;
980}
981
982// Add virtual address mapping for 32-bit compiled block
983void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
984{
7139f3c8 985 ll_add(head,vaddr,addr);
986#ifndef FORCE32
987 (*head)->reg32=reg32;
988#endif
57871462 989}
990
991// Check if an address is already compiled
992// but don't return addresses which are about to expire from the cache
993void *check_addr(u_int vaddr)
994{
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
999 }
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003 }
94d23bb9 1004 u_int page=get_page(vaddr);
57871462 1005 struct ll_entry *head;
1006 head=jump_in[page];
1007 while(head!=NULL) {
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1013 return head->addr;
1014 }
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1017 return head->addr;
1018 }
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1022 if(ht_bin[0]==-1) {
1023 ht_bin[1]=(int)head->addr;
1024 ht_bin[0]=vaddr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1027 ht_bin[2]=vaddr;
1028 }
1029 return head->addr;
1030 }
1031 }
1032 head=head->next;
1033 }
1034 return 0;
1035}
1036
1037void remove_hash(int vaddr)
1038{
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1043 }
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1048 }
1049}
1050
1051void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052{
1053 struct ll_entry *next;
1054 while(*head) {
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057 {
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1060 next=(*head)->next;
1061 free(*head);
1062 *head=next;
1063 }
1064 else
1065 {
1066 head=&((*head)->next);
1067 }
1068 }
1069}
1070
1071// Remove all entries from linked list
1072void ll_clear(struct ll_entry **head)
1073{
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1076 if(cur=*head) {
1077 *head=0;
1078 while(cur) {
1079 next=cur->next;
1080 free(cur);
1081 cur=next;
1082 }
1083 }
1084}
1085
1086// Dereference the pointers and remove if it matches
1087void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088{
1089 while(head) {
1090 int ptr=get_pointer(head->addr);
1091 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092 if(((ptr>>shift)==(addr>>shift)) ||
1093 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1094 {
5088bb70 1095 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1096 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1097 #ifdef __arm__
1098 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1099 #endif
57871462 1100 }
1101 head=head->next;
1102 }
1103}
1104
1105// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1106void invalidate_page(u_int page)
57871462 1107{
57871462 1108 struct ll_entry *head;
1109 struct ll_entry *next;
1110 head=jump_in[page];
1111 jump_in[page]=0;
1112 while(head!=NULL) {
1113 inv_debug("INVALIDATE: %x\n",head->vaddr);
1114 remove_hash(head->vaddr);
1115 next=head->next;
1116 free(head);
1117 head=next;
1118 }
1119 head=jump_out[page];
1120 jump_out[page]=0;
1121 while(head!=NULL) {
1122 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1123 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1124 #ifdef __arm__
1125 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1126 #endif
57871462 1127 next=head->next;
1128 free(head);
1129 head=next;
1130 }
57871462 1131}
1132void invalidate_block(u_int block)
1133{
94d23bb9 1134 u_int page=get_page(block<<12);
1135 u_int vpage=get_vpage(block<<12);
57871462 1136 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1137 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1138 u_int first,last;
1139 first=last=page;
1140 struct ll_entry *head;
1141 head=jump_dirty[vpage];
1142 //printf("page=%d vpage=%d\n",page,vpage);
1143 while(head!=NULL) {
1144 u_int start,end;
1145 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1146 get_bounds((int)head->addr,&start,&end);
1147 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1148 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1149 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1150 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1151 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1152 }
1153 }
90ae6d4e 1154#ifndef DISABLE_TLB
57871462 1155 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1156 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1157 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1158 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1159 }
1160 }
90ae6d4e 1161#endif
57871462 1162 }
1163 head=head->next;
1164 }
1165 //printf("first=%d last=%d\n",first,last);
f76eeef9 1166 invalidate_page(page);
57871462 1167 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1168 assert(last<page+5);
1169 // Invalidate the adjacent pages if a block crosses a 4K boundary
1170 while(first<page) {
1171 invalidate_page(first);
1172 first++;
1173 }
1174 for(first=page+1;first<last;first++) {
1175 invalidate_page(first);
1176 }
dd3a91a1 1177 #ifdef __arm__
1178 do_clear_cache();
1179 #endif
57871462 1180
1181 // Don't trap writes
1182 invalid_code[block]=1;
94d23bb9 1183#ifndef DISABLE_TLB
57871462 1184 // If there is a valid TLB entry for this page, remove write protect
1185 if(tlb_LUT_w[block]) {
1186 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1187 // CHECK: Is this right?
1188 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1189 u_int real_block=tlb_LUT_w[block]>>12;
1190 invalid_code[real_block]=1;
1191 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1192 }
1193 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1194#endif
f76eeef9 1195
57871462 1196 #ifdef USE_MINI_HT
1197 memset(mini_ht,-1,sizeof(mini_ht));
1198 #endif
1199}
1200void invalidate_addr(u_int addr)
1201{
1202 invalidate_block(addr>>12);
1203}
dd3a91a1 1204// This is called when loading a save state.
1205// Anything could have changed, so invalidate everything.
57871462 1206void invalidate_all_pages()
1207{
1208 u_int page,n;
1209 for(page=0;page<4096;page++)
1210 invalidate_page(page);
1211 for(page=0;page<1048576;page++)
1212 if(!invalid_code[page]) {
1213 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1214 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1215 }
1216 #ifdef __arm__
1217 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1218 #endif
1219 #ifdef USE_MINI_HT
1220 memset(mini_ht,-1,sizeof(mini_ht));
1221 #endif
94d23bb9 1222 #ifndef DISABLE_TLB
57871462 1223 // TLB
1224 for(page=0;page<0x100000;page++) {
1225 if(tlb_LUT_r[page]) {
1226 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1227 if(!tlb_LUT_w[page]||!invalid_code[page])
1228 memory_map[page]|=0x40000000; // Write protect
1229 }
1230 else memory_map[page]=-1;
1231 if(page==0x80000) page=0xC0000;
1232 }
1233 tlb_hacks();
94d23bb9 1234 #endif
57871462 1235}
1236
1237// Add an entry to jump_out after making a link
1238void add_link(u_int vaddr,void *src)
1239{
94d23bb9 1240 u_int page=get_page(vaddr);
57871462 1241 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1242 ll_add(jump_out+page,vaddr,src);
1243 //int ptr=get_pointer(src);
1244 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1245}
1246
1247// If a code block was found to be unmodified (bit was set in
1248// restore_candidate) and it remains unmodified (bit is clear
1249// in invalid_code) then move the entries for that 4K page from
1250// the dirty list to the clean list.
1251void clean_blocks(u_int page)
1252{
1253 struct ll_entry *head;
1254 inv_debug("INV: clean_blocks page=%d\n",page);
1255 head=jump_dirty[page];
1256 while(head!=NULL) {
1257 if(!invalid_code[head->vaddr>>12]) {
1258 // Don't restore blocks which are about to expire from the cache
1259 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260 u_int start,end;
1261 if(verify_dirty((int)head->addr)) {
1262 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1263 u_int i;
1264 u_int inv=0;
1265 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1266 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1267 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1268 inv|=invalid_code[i];
1269 }
1270 }
1271 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1272 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1273 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1274 if(addr<start||addr>=end) inv=1;
1275 }
4cb76aa4 1276 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1277 inv=1;
1278 }
1279 if(!inv) {
1280 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1281 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1282 u_int ppage=page;
94d23bb9 1283#ifndef DISABLE_TLB
57871462 1284 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1285#endif
57871462 1286 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1287 //printf("page=%x, addr=%x\n",page,head->vaddr);
1288 //assert(head->vaddr>>12==(page|0x80000));
1289 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1290 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1291 if(!head->reg32) {
1292 if(ht_bin[0]==head->vaddr) {
1293 ht_bin[1]=(int)clean_addr; // Replace existing entry
1294 }
1295 if(ht_bin[2]==head->vaddr) {
1296 ht_bin[3]=(int)clean_addr; // Replace existing entry
1297 }
1298 }
1299 }
1300 }
1301 }
1302 }
1303 }
1304 head=head->next;
1305 }
1306}
1307
1308
1309void mov_alloc(struct regstat *current,int i)
1310{
1311 // Note: Don't need to actually alloc the source registers
1312 if((~current->is32>>rs1[i])&1) {
1313 //alloc_reg64(current,i,rs1[i]);
1314 alloc_reg64(current,i,rt1[i]);
1315 current->is32&=~(1LL<<rt1[i]);
1316 } else {
1317 //alloc_reg(current,i,rs1[i]);
1318 alloc_reg(current,i,rt1[i]);
1319 current->is32|=(1LL<<rt1[i]);
1320 }
1321 clear_const(current,rs1[i]);
1322 clear_const(current,rt1[i]);
1323 dirty_reg(current,rt1[i]);
1324}
1325
1326void shiftimm_alloc(struct regstat *current,int i)
1327{
1328 clear_const(current,rs1[i]);
1329 clear_const(current,rt1[i]);
1330 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1331 {
1332 if(rt1[i]) {
1333 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1334 else lt1[i]=rs1[i];
1335 alloc_reg(current,i,rt1[i]);
1336 current->is32|=1LL<<rt1[i];
1337 dirty_reg(current,rt1[i]);
1338 }
1339 }
1340 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1341 {
1342 if(rt1[i]) {
1343 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1344 alloc_reg64(current,i,rt1[i]);
1345 current->is32&=~(1LL<<rt1[i]);
1346 dirty_reg(current,rt1[i]);
1347 }
1348 }
1349 if(opcode2[i]==0x3c) // DSLL32
1350 {
1351 if(rt1[i]) {
1352 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1353 alloc_reg64(current,i,rt1[i]);
1354 current->is32&=~(1LL<<rt1[i]);
1355 dirty_reg(current,rt1[i]);
1356 }
1357 }
1358 if(opcode2[i]==0x3e) // DSRL32
1359 {
1360 if(rt1[i]) {
1361 alloc_reg64(current,i,rs1[i]);
1362 if(imm[i]==32) {
1363 alloc_reg64(current,i,rt1[i]);
1364 current->is32&=~(1LL<<rt1[i]);
1365 } else {
1366 alloc_reg(current,i,rt1[i]);
1367 current->is32|=1LL<<rt1[i];
1368 }
1369 dirty_reg(current,rt1[i]);
1370 }
1371 }
1372 if(opcode2[i]==0x3f) // DSRA32
1373 {
1374 if(rt1[i]) {
1375 alloc_reg64(current,i,rs1[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 current->is32|=1LL<<rt1[i];
1378 dirty_reg(current,rt1[i]);
1379 }
1380 }
1381}
1382
1383void shift_alloc(struct regstat *current,int i)
1384{
1385 if(rt1[i]) {
1386 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1387 {
1388 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1390 alloc_reg(current,i,rt1[i]);
1391 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1392 current->is32|=1LL<<rt1[i];
1393 } else { // DSLLV/DSRLV/DSRAV
1394 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg64(current,i,rt1[i]);
1397 current->is32&=~(1LL<<rt1[i]);
1398 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1399 alloc_reg_temp(current,i,-1);
1400 }
1401 clear_const(current,rs1[i]);
1402 clear_const(current,rs2[i]);
1403 clear_const(current,rt1[i]);
1404 dirty_reg(current,rt1[i]);
1405 }
1406}
1407
1408void alu_alloc(struct regstat *current,int i)
1409{
1410 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1411 if(rt1[i]) {
1412 if(rs1[i]&&rs2[i]) {
1413 alloc_reg(current,i,rs1[i]);
1414 alloc_reg(current,i,rs2[i]);
1415 }
1416 else {
1417 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1418 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1419 }
1420 alloc_reg(current,i,rt1[i]);
1421 }
1422 current->is32|=1LL<<rt1[i];
1423 }
1424 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1425 if(rt1[i]) {
1426 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1427 {
1428 alloc_reg64(current,i,rs1[i]);
1429 alloc_reg64(current,i,rs2[i]);
1430 alloc_reg(current,i,rt1[i]);
1431 } else {
1432 alloc_reg(current,i,rs1[i]);
1433 alloc_reg(current,i,rs2[i]);
1434 alloc_reg(current,i,rt1[i]);
1435 }
1436 }
1437 current->is32|=1LL<<rt1[i];
1438 }
1439 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1440 if(rt1[i]) {
1441 if(rs1[i]&&rs2[i]) {
1442 alloc_reg(current,i,rs1[i]);
1443 alloc_reg(current,i,rs2[i]);
1444 }
1445 else
1446 {
1447 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1448 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1449 }
1450 alloc_reg(current,i,rt1[i]);
1451 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1452 {
1453 if(!((current->uu>>rt1[i])&1)) {
1454 alloc_reg64(current,i,rt1[i]);
1455 }
1456 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1457 if(rs1[i]&&rs2[i]) {
1458 alloc_reg64(current,i,rs1[i]);
1459 alloc_reg64(current,i,rs2[i]);
1460 }
1461 else
1462 {
1463 // Is is really worth it to keep 64-bit values in registers?
1464 #ifdef NATIVE_64BIT
1465 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1466 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1467 #endif
1468 }
1469 }
1470 current->is32&=~(1LL<<rt1[i]);
1471 } else {
1472 current->is32|=1LL<<rt1[i];
1473 }
1474 }
1475 }
1476 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1477 if(rt1[i]) {
1478 if(rs1[i]&&rs2[i]) {
1479 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1480 alloc_reg64(current,i,rs1[i]);
1481 alloc_reg64(current,i,rs2[i]);
1482 alloc_reg64(current,i,rt1[i]);
1483 } else {
1484 alloc_reg(current,i,rs1[i]);
1485 alloc_reg(current,i,rs2[i]);
1486 alloc_reg(current,i,rt1[i]);
1487 }
1488 }
1489 else {
1490 alloc_reg(current,i,rt1[i]);
1491 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1492 // DADD used as move, or zeroing
1493 // If we have a 64-bit source, then make the target 64 bits too
1494 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1495 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1496 alloc_reg64(current,i,rt1[i]);
1497 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1498 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1499 alloc_reg64(current,i,rt1[i]);
1500 }
1501 if(opcode2[i]>=0x2e&&rs2[i]) {
1502 // DSUB used as negation - 64-bit result
1503 // If we have a 32-bit register, extend it to 64 bits
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1506 }
1507 }
1508 }
1509 if(rs1[i]&&rs2[i]) {
1510 current->is32&=~(1LL<<rt1[i]);
1511 } else if(rs1[i]) {
1512 current->is32&=~(1LL<<rt1[i]);
1513 if((current->is32>>rs1[i])&1)
1514 current->is32|=1LL<<rt1[i];
1515 } else if(rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1517 if((current->is32>>rs2[i])&1)
1518 current->is32|=1LL<<rt1[i];
1519 } else {
1520 current->is32|=1LL<<rt1[i];
1521 }
1522 }
1523 }
1524 clear_const(current,rs1[i]);
1525 clear_const(current,rs2[i]);
1526 clear_const(current,rt1[i]);
1527 dirty_reg(current,rt1[i]);
1528}
1529
1530void imm16_alloc(struct regstat *current,int i)
1531{
1532 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1533 else lt1[i]=rs1[i];
1534 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1535 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1536 current->is32&=~(1LL<<rt1[i]);
1537 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1538 // TODO: Could preserve the 32-bit flag if the immediate is zero
1539 alloc_reg64(current,i,rt1[i]);
1540 alloc_reg64(current,i,rs1[i]);
1541 }
1542 clear_const(current,rs1[i]);
1543 clear_const(current,rt1[i]);
1544 }
1545 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1546 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1547 current->is32|=1LL<<rt1[i];
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1550 }
1551 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1552 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1553 if(rs1[i]!=rt1[i]) {
1554 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1555 alloc_reg64(current,i,rt1[i]);
1556 current->is32&=~(1LL<<rt1[i]);
1557 }
1558 }
1559 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1560 if(is_const(current,rs1[i])) {
1561 int v=get_const(current,rs1[i]);
1562 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1563 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1564 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1565 }
1566 else clear_const(current,rt1[i]);
1567 }
1568 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1569 if(is_const(current,rs1[i])) {
1570 int v=get_const(current,rs1[i]);
1571 set_const(current,rt1[i],v+imm[i]);
1572 }
1573 else clear_const(current,rt1[i]);
1574 current->is32|=1LL<<rt1[i];
1575 }
1576 else {
1577 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1578 current->is32|=1LL<<rt1[i];
1579 }
1580 dirty_reg(current,rt1[i]);
1581}
1582
1583void load_alloc(struct regstat *current,int i)
1584{
1585 clear_const(current,rt1[i]);
1586 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1587 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1588 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1589 if(rt1[i]) {
1590 alloc_reg(current,i,rt1[i]);
535d208a 1591 if(get_reg(current->regmap,rt1[i])<0) {
1592 // dummy load, but we still need a register to calculate the address
1593 alloc_reg_temp(current,i,-1);
1594 }
57871462 1595 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1596 {
1597 current->is32&=~(1LL<<rt1[i]);
1598 alloc_reg64(current,i,rt1[i]);
1599 }
1600 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1601 {
1602 current->is32&=~(1LL<<rt1[i]);
1603 alloc_reg64(current,i,rt1[i]);
1604 alloc_all(current,i);
1605 alloc_reg64(current,i,FTEMP);
1606 }
1607 else current->is32|=1LL<<rt1[i];
1608 dirty_reg(current,rt1[i]);
1609 // If using TLB, need a register for pointer to the mapping table
1610 if(using_tlb) alloc_reg(current,i,TLREG);
1611 // LWL/LWR need a temporary register for the old value
1612 if(opcode[i]==0x22||opcode[i]==0x26)
1613 {
1614 alloc_reg(current,i,FTEMP);
1615 alloc_reg_temp(current,i,-1);
1616 }
1617 }
1618 else
1619 {
1620 // Load to r0 (dummy load)
1621 // but we still need a register to calculate the address
535d208a 1622 if(opcode[i]==0x22||opcode[i]==0x26)
1623 {
1624 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1625 }
57871462 1626 alloc_reg_temp(current,i,-1);
535d208a 1627 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1628 {
1629 alloc_all(current,i);
1630 alloc_reg64(current,i,FTEMP);
1631 }
57871462 1632 }
1633}
1634
1635void store_alloc(struct regstat *current,int i)
1636{
1637 clear_const(current,rs2[i]);
1638 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1639 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1640 alloc_reg(current,i,rs2[i]);
1641 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1642 alloc_reg64(current,i,rs2[i]);
1643 if(rs2[i]) alloc_reg(current,i,FTEMP);
1644 }
1645 // If using TLB, need a register for pointer to the mapping table
1646 if(using_tlb) alloc_reg(current,i,TLREG);
1647 #if defined(HOST_IMM8)
1648 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1649 else alloc_reg(current,i,INVCP);
1650 #endif
b7918751 1651 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1652 alloc_reg(current,i,FTEMP);
1653 }
1654 // We need a temporary register for address generation
1655 alloc_reg_temp(current,i,-1);
1656}
1657
1658void c1ls_alloc(struct regstat *current,int i)
1659{
1660 //clear_const(current,rs1[i]); // FIXME
1661 clear_const(current,rt1[i]);
1662 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1663 alloc_reg(current,i,CSREG); // Status
1664 alloc_reg(current,i,FTEMP);
1665 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1666 alloc_reg64(current,i,FTEMP);
1667 }
1668 // If using TLB, need a register for pointer to the mapping table
1669 if(using_tlb) alloc_reg(current,i,TLREG);
1670 #if defined(HOST_IMM8)
1671 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1672 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1673 alloc_reg(current,i,INVCP);
1674 #endif
1675 // We need a temporary register for address generation
1676 alloc_reg_temp(current,i,-1);
1677}
1678
b9b61529 1679void c2ls_alloc(struct regstat *current,int i)
1680{
1681 clear_const(current,rt1[i]);
1682 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683 alloc_reg(current,i,FTEMP);
1684 // If using TLB, need a register for pointer to the mapping table
1685 if(using_tlb) alloc_reg(current,i,TLREG);
1686 #if defined(HOST_IMM8)
1687 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1688 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1689 alloc_reg(current,i,INVCP);
1690 #endif
1691 // We need a temporary register for address generation
1692 alloc_reg_temp(current,i,-1);
1693}
1694
57871462 1695#ifndef multdiv_alloc
1696void multdiv_alloc(struct regstat *current,int i)
1697{
1698 // case 0x18: MULT
1699 // case 0x19: MULTU
1700 // case 0x1A: DIV
1701 // case 0x1B: DIVU
1702 // case 0x1C: DMULT
1703 // case 0x1D: DMULTU
1704 // case 0x1E: DDIV
1705 // case 0x1F: DDIVU
1706 clear_const(current,rs1[i]);
1707 clear_const(current,rs2[i]);
1708 if(rs1[i]&&rs2[i])
1709 {
1710 if((opcode2[i]&4)==0) // 32-bit
1711 {
1712 current->u&=~(1LL<<HIREG);
1713 current->u&=~(1LL<<LOREG);
1714 alloc_reg(current,i,HIREG);
1715 alloc_reg(current,i,LOREG);
1716 alloc_reg(current,i,rs1[i]);
1717 alloc_reg(current,i,rs2[i]);
1718 current->is32|=1LL<<HIREG;
1719 current->is32|=1LL<<LOREG;
1720 dirty_reg(current,HIREG);
1721 dirty_reg(current,LOREG);
1722 }
1723 else // 64-bit
1724 {
1725 current->u&=~(1LL<<HIREG);
1726 current->u&=~(1LL<<LOREG);
1727 current->uu&=~(1LL<<HIREG);
1728 current->uu&=~(1LL<<LOREG);
1729 alloc_reg64(current,i,HIREG);
1730 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1731 alloc_reg64(current,i,rs1[i]);
1732 alloc_reg64(current,i,rs2[i]);
1733 alloc_all(current,i);
1734 current->is32&=~(1LL<<HIREG);
1735 current->is32&=~(1LL<<LOREG);
1736 dirty_reg(current,HIREG);
1737 dirty_reg(current,LOREG);
1738 }
1739 }
1740 else
1741 {
1742 // Multiply by zero is zero.
1743 // MIPS does not have a divide by zero exception.
1744 // The result is undefined, we return zero.
1745 alloc_reg(current,i,HIREG);
1746 alloc_reg(current,i,LOREG);
1747 current->is32|=1LL<<HIREG;
1748 current->is32|=1LL<<LOREG;
1749 dirty_reg(current,HIREG);
1750 dirty_reg(current,LOREG);
1751 }
1752}
1753#endif
1754
1755void cop0_alloc(struct regstat *current,int i)
1756{
1757 if(opcode2[i]==0) // MFC0
1758 {
1759 if(rt1[i]) {
1760 clear_const(current,rt1[i]);
1761 alloc_all(current,i);
1762 alloc_reg(current,i,rt1[i]);
1763 current->is32|=1LL<<rt1[i];
1764 dirty_reg(current,rt1[i]);
1765 }
1766 }
1767 else if(opcode2[i]==4) // MTC0
1768 {
1769 if(rs1[i]){
1770 clear_const(current,rs1[i]);
1771 alloc_reg(current,i,rs1[i]);
1772 alloc_all(current,i);
1773 }
1774 else {
1775 alloc_all(current,i); // FIXME: Keep r0
1776 current->u&=~1LL;
1777 alloc_reg(current,i,0);
1778 }
1779 }
1780 else
1781 {
1782 // TLBR/TLBWI/TLBWR/TLBP/ERET
1783 assert(opcode2[i]==0x10);
1784 alloc_all(current,i);
1785 }
1786}
1787
1788void cop1_alloc(struct regstat *current,int i)
1789{
1790 alloc_reg(current,i,CSREG); // Load status
1791 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1792 {
7de557a6 1793 if(rt1[i]){
1794 clear_const(current,rt1[i]);
1795 if(opcode2[i]==1) {
1796 alloc_reg64(current,i,rt1[i]); // DMFC1
1797 current->is32&=~(1LL<<rt1[i]);
1798 }else{
1799 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1800 current->is32|=1LL<<rt1[i];
1801 }
1802 dirty_reg(current,rt1[i]);
57871462 1803 }
57871462 1804 alloc_reg_temp(current,i,-1);
1805 }
1806 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1807 {
1808 if(rs1[i]){
1809 clear_const(current,rs1[i]);
1810 if(opcode2[i]==5)
1811 alloc_reg64(current,i,rs1[i]); // DMTC1
1812 else
1813 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1814 alloc_reg_temp(current,i,-1);
1815 }
1816 else {
1817 current->u&=~1LL;
1818 alloc_reg(current,i,0);
1819 alloc_reg_temp(current,i,-1);
1820 }
1821 }
1822}
1823void fconv_alloc(struct regstat *current,int i)
1824{
1825 alloc_reg(current,i,CSREG); // Load status
1826 alloc_reg_temp(current,i,-1);
1827}
1828void float_alloc(struct regstat *current,int i)
1829{
1830 alloc_reg(current,i,CSREG); // Load status
1831 alloc_reg_temp(current,i,-1);
1832}
b9b61529 1833void c2op_alloc(struct regstat *current,int i)
1834{
1835 alloc_reg_temp(current,i,-1);
1836}
57871462 1837void fcomp_alloc(struct regstat *current,int i)
1838{
1839 alloc_reg(current,i,CSREG); // Load status
1840 alloc_reg(current,i,FSREG); // Load flags
1841 dirty_reg(current,FSREG); // Flag will be modified
1842 alloc_reg_temp(current,i,-1);
1843}
1844
1845void syscall_alloc(struct regstat *current,int i)
1846{
1847 alloc_cc(current,i);
1848 dirty_reg(current,CCREG);
1849 alloc_all(current,i);
1850 current->isconst=0;
1851}
1852
1853void delayslot_alloc(struct regstat *current,int i)
1854{
1855 switch(itype[i]) {
1856 case UJUMP:
1857 case CJUMP:
1858 case SJUMP:
1859 case RJUMP:
1860 case FJUMP:
1861 case SYSCALL:
7139f3c8 1862 case HLECALL:
57871462 1863 case SPAN:
1864 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1865 printf("Disabled speculative precompilation\n");
1866 stop_after_jal=1;
1867 break;
1868 case IMM16:
1869 imm16_alloc(current,i);
1870 break;
1871 case LOAD:
1872 case LOADLR:
1873 load_alloc(current,i);
1874 break;
1875 case STORE:
1876 case STORELR:
1877 store_alloc(current,i);
1878 break;
1879 case ALU:
1880 alu_alloc(current,i);
1881 break;
1882 case SHIFT:
1883 shift_alloc(current,i);
1884 break;
1885 case MULTDIV:
1886 multdiv_alloc(current,i);
1887 break;
1888 case SHIFTIMM:
1889 shiftimm_alloc(current,i);
1890 break;
1891 case MOV:
1892 mov_alloc(current,i);
1893 break;
1894 case COP0:
1895 cop0_alloc(current,i);
1896 break;
1897 case COP1:
b9b61529 1898 case COP2:
57871462 1899 cop1_alloc(current,i);
1900 break;
1901 case C1LS:
1902 c1ls_alloc(current,i);
1903 break;
b9b61529 1904 case C2LS:
1905 c2ls_alloc(current,i);
1906 break;
57871462 1907 case FCONV:
1908 fconv_alloc(current,i);
1909 break;
1910 case FLOAT:
1911 float_alloc(current,i);
1912 break;
1913 case FCOMP:
1914 fcomp_alloc(current,i);
1915 break;
b9b61529 1916 case C2OP:
1917 c2op_alloc(current,i);
1918 break;
57871462 1919 }
1920}
1921
1922// Special case where a branch and delay slot span two pages in virtual memory
1923static void pagespan_alloc(struct regstat *current,int i)
1924{
1925 current->isconst=0;
1926 current->wasconst=0;
1927 regs[i].wasconst=0;
1928 alloc_all(current,i);
1929 alloc_cc(current,i);
1930 dirty_reg(current,CCREG);
1931 if(opcode[i]==3) // JAL
1932 {
1933 alloc_reg(current,i,31);
1934 dirty_reg(current,31);
1935 }
1936 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1937 {
1938 alloc_reg(current,i,rs1[i]);
5067f341 1939 if (rt1[i]!=0) {
1940 alloc_reg(current,i,rt1[i]);
1941 dirty_reg(current,rt1[i]);
57871462 1942 }
1943 }
1944 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1945 {
1946 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1947 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1948 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1949 {
1950 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1951 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1952 }
1953 }
1954 else
1955 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1956 {
1957 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1958 if(!((current->is32>>rs1[i])&1))
1959 {
1960 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1961 }
1962 }
1963 else
1964 if(opcode[i]==0x11) // BC1
1965 {
1966 alloc_reg(current,i,FSREG);
1967 alloc_reg(current,i,CSREG);
1968 }
1969 //else ...
1970}
1971
1972add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1973{
1974 stubs[stubcount][0]=type;
1975 stubs[stubcount][1]=addr;
1976 stubs[stubcount][2]=retaddr;
1977 stubs[stubcount][3]=a;
1978 stubs[stubcount][4]=b;
1979 stubs[stubcount][5]=c;
1980 stubs[stubcount][6]=d;
1981 stubs[stubcount][7]=e;
1982 stubcount++;
1983}
1984
1985// Write out a single register
1986void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1987{
1988 int hr;
1989 for(hr=0;hr<HOST_REGS;hr++) {
1990 if(hr!=EXCLUDE_REG) {
1991 if((regmap[hr]&63)==r) {
1992 if((dirty>>hr)&1) {
1993 if(regmap[hr]<64) {
1994 emit_storereg(r,hr);
24385cae 1995#ifndef FORCE32
57871462 1996 if((is32>>regmap[hr])&1) {
1997 emit_sarimm(hr,31,hr);
1998 emit_storereg(r|64,hr);
1999 }
24385cae 2000#endif
57871462 2001 }else{
2002 emit_storereg(r|64,hr);
2003 }
2004 }
2005 }
2006 }
2007 }
2008}
2009
2010int mchecksum()
2011{
2012 //if(!tracedebug) return 0;
2013 int i;
2014 int sum=0;
2015 for(i=0;i<2097152;i++) {
2016 unsigned int temp=sum;
2017 sum<<=1;
2018 sum|=(~temp)>>31;
2019 sum^=((u_int *)rdram)[i];
2020 }
2021 return sum;
2022}
2023int rchecksum()
2024{
2025 int i;
2026 int sum=0;
2027 for(i=0;i<64;i++)
2028 sum^=((u_int *)reg)[i];
2029 return sum;
2030}
57871462 2031void rlist()
2032{
2033 int i;
2034 printf("TRACE: ");
2035 for(i=0;i<32;i++)
2036 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2037 printf("\n");
3d624f89 2038#ifndef DISABLE_COP1
57871462 2039 printf("TRACE: ");
2040 for(i=0;i<32;i++)
2041 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2042 printf("\n");
3d624f89 2043#endif
57871462 2044}
2045
2046void enabletrace()
2047{
2048 tracedebug=1;
2049}
2050
2051void memdebug(int i)
2052{
2053 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2054 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2055 //rlist();
2056 //if(tracedebug) {
2057 //if(Count>=-2084597794) {
2058 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2059 //if(0) {
2060 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2061 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2062 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2063 rlist();
2064 #ifdef __i386__
2065 printf("TRACE: %x\n",(&i)[-1]);
2066 #endif
2067 #ifdef __arm__
2068 int j;
2069 printf("TRACE: %x \n",(&j)[10]);
2070 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2071 #endif
2072 //fflush(stdout);
2073 }
2074 //printf("TRACE: %x\n",(&i)[-1]);
2075}
2076
2077void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2078{
2079 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2080}
2081
2082void alu_assemble(int i,struct regstat *i_regs)
2083{
2084 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2085 if(rt1[i]) {
2086 signed char s1,s2,t;
2087 t=get_reg(i_regs->regmap,rt1[i]);
2088 if(t>=0) {
2089 s1=get_reg(i_regs->regmap,rs1[i]);
2090 s2=get_reg(i_regs->regmap,rs2[i]);
2091 if(rs1[i]&&rs2[i]) {
2092 assert(s1>=0);
2093 assert(s2>=0);
2094 if(opcode2[i]&2) emit_sub(s1,s2,t);
2095 else emit_add(s1,s2,t);
2096 }
2097 else if(rs1[i]) {
2098 if(s1>=0) emit_mov(s1,t);
2099 else emit_loadreg(rs1[i],t);
2100 }
2101 else if(rs2[i]) {
2102 if(s2>=0) {
2103 if(opcode2[i]&2) emit_neg(s2,t);
2104 else emit_mov(s2,t);
2105 }
2106 else {
2107 emit_loadreg(rs2[i],t);
2108 if(opcode2[i]&2) emit_neg(t,t);
2109 }
2110 }
2111 else emit_zeroreg(t);
2112 }
2113 }
2114 }
2115 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2116 if(rt1[i]) {
2117 signed char s1l,s2l,s1h,s2h,tl,th;
2118 tl=get_reg(i_regs->regmap,rt1[i]);
2119 th=get_reg(i_regs->regmap,rt1[i]|64);
2120 if(tl>=0) {
2121 s1l=get_reg(i_regs->regmap,rs1[i]);
2122 s2l=get_reg(i_regs->regmap,rs2[i]);
2123 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2124 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2125 if(rs1[i]&&rs2[i]) {
2126 assert(s1l>=0);
2127 assert(s2l>=0);
2128 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2129 else emit_adds(s1l,s2l,tl);
2130 if(th>=0) {
2131 #ifdef INVERTED_CARRY
2132 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2133 #else
2134 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2135 #endif
2136 else emit_add(s1h,s2h,th);
2137 }
2138 }
2139 else if(rs1[i]) {
2140 if(s1l>=0) emit_mov(s1l,tl);
2141 else emit_loadreg(rs1[i],tl);
2142 if(th>=0) {
2143 if(s1h>=0) emit_mov(s1h,th);
2144 else emit_loadreg(rs1[i]|64,th);
2145 }
2146 }
2147 else if(rs2[i]) {
2148 if(s2l>=0) {
2149 if(opcode2[i]&2) emit_negs(s2l,tl);
2150 else emit_mov(s2l,tl);
2151 }
2152 else {
2153 emit_loadreg(rs2[i],tl);
2154 if(opcode2[i]&2) emit_negs(tl,tl);
2155 }
2156 if(th>=0) {
2157 #ifdef INVERTED_CARRY
2158 if(s2h>=0) emit_mov(s2h,th);
2159 else emit_loadreg(rs2[i]|64,th);
2160 if(opcode2[i]&2) {
2161 emit_adcimm(-1,th); // x86 has inverted carry flag
2162 emit_not(th,th);
2163 }
2164 #else
2165 if(opcode2[i]&2) {
2166 if(s2h>=0) emit_rscimm(s2h,0,th);
2167 else {
2168 emit_loadreg(rs2[i]|64,th);
2169 emit_rscimm(th,0,th);
2170 }
2171 }else{
2172 if(s2h>=0) emit_mov(s2h,th);
2173 else emit_loadreg(rs2[i]|64,th);
2174 }
2175 #endif
2176 }
2177 }
2178 else {
2179 emit_zeroreg(tl);
2180 if(th>=0) emit_zeroreg(th);
2181 }
2182 }
2183 }
2184 }
2185 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2186 if(rt1[i]) {
2187 signed char s1l,s1h,s2l,s2h,t;
2188 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2189 {
2190 t=get_reg(i_regs->regmap,rt1[i]);
2191 //assert(t>=0);
2192 if(t>=0) {
2193 s1l=get_reg(i_regs->regmap,rs1[i]);
2194 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2195 s2l=get_reg(i_regs->regmap,rs2[i]);
2196 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2197 if(rs2[i]==0) // rx<r0
2198 {
2199 assert(s1h>=0);
2200 if(opcode2[i]==0x2a) // SLT
2201 emit_shrimm(s1h,31,t);
2202 else // SLTU (unsigned can not be less than zero)
2203 emit_zeroreg(t);
2204 }
2205 else if(rs1[i]==0) // r0<rx
2206 {
2207 assert(s2h>=0);
2208 if(opcode2[i]==0x2a) // SLT
2209 emit_set_gz64_32(s2h,s2l,t);
2210 else // SLTU (set if not zero)
2211 emit_set_nz64_32(s2h,s2l,t);
2212 }
2213 else {
2214 assert(s1l>=0);assert(s1h>=0);
2215 assert(s2l>=0);assert(s2h>=0);
2216 if(opcode2[i]==0x2a) // SLT
2217 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2218 else // SLTU
2219 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2220 }
2221 }
2222 } else {
2223 t=get_reg(i_regs->regmap,rt1[i]);
2224 //assert(t>=0);
2225 if(t>=0) {
2226 s1l=get_reg(i_regs->regmap,rs1[i]);
2227 s2l=get_reg(i_regs->regmap,rs2[i]);
2228 if(rs2[i]==0) // rx<r0
2229 {
2230 assert(s1l>=0);
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_shrimm(s1l,31,t);
2233 else // SLTU (unsigned can not be less than zero)
2234 emit_zeroreg(t);
2235 }
2236 else if(rs1[i]==0) // r0<rx
2237 {
2238 assert(s2l>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_gz32(s2l,t);
2241 else // SLTU (set if not zero)
2242 emit_set_nz32(s2l,t);
2243 }
2244 else{
2245 assert(s1l>=0);assert(s2l>=0);
2246 if(opcode2[i]==0x2a) // SLT
2247 emit_set_if_less32(s1l,s2l,t);
2248 else // SLTU
2249 emit_set_if_carry32(s1l,s2l,t);
2250 }
2251 }
2252 }
2253 }
2254 }
2255 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2256 if(rt1[i]) {
2257 signed char s1l,s1h,s2l,s2h,th,tl;
2258 tl=get_reg(i_regs->regmap,rt1[i]);
2259 th=get_reg(i_regs->regmap,rt1[i]|64);
2260 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2261 {
2262 assert(tl>=0);
2263 if(tl>=0) {
2264 s1l=get_reg(i_regs->regmap,rs1[i]);
2265 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2266 s2l=get_reg(i_regs->regmap,rs2[i]);
2267 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2268 if(rs1[i]&&rs2[i]) {
2269 assert(s1l>=0);assert(s1h>=0);
2270 assert(s2l>=0);assert(s2h>=0);
2271 if(opcode2[i]==0x24) { // AND
2272 emit_and(s1l,s2l,tl);
2273 emit_and(s1h,s2h,th);
2274 } else
2275 if(opcode2[i]==0x25) { // OR
2276 emit_or(s1l,s2l,tl);
2277 emit_or(s1h,s2h,th);
2278 } else
2279 if(opcode2[i]==0x26) { // XOR
2280 emit_xor(s1l,s2l,tl);
2281 emit_xor(s1h,s2h,th);
2282 } else
2283 if(opcode2[i]==0x27) { // NOR
2284 emit_or(s1l,s2l,tl);
2285 emit_or(s1h,s2h,th);
2286 emit_not(tl,tl);
2287 emit_not(th,th);
2288 }
2289 }
2290 else
2291 {
2292 if(opcode2[i]==0x24) { // AND
2293 emit_zeroreg(tl);
2294 emit_zeroreg(th);
2295 } else
2296 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2297 if(rs1[i]){
2298 if(s1l>=0) emit_mov(s1l,tl);
2299 else emit_loadreg(rs1[i],tl);
2300 if(s1h>=0) emit_mov(s1h,th);
2301 else emit_loadreg(rs1[i]|64,th);
2302 }
2303 else
2304 if(rs2[i]){
2305 if(s2l>=0) emit_mov(s2l,tl);
2306 else emit_loadreg(rs2[i],tl);
2307 if(s2h>=0) emit_mov(s2h,th);
2308 else emit_loadreg(rs2[i]|64,th);
2309 }
2310 else{
2311 emit_zeroreg(tl);
2312 emit_zeroreg(th);
2313 }
2314 } else
2315 if(opcode2[i]==0x27) { // NOR
2316 if(rs1[i]){
2317 if(s1l>=0) emit_not(s1l,tl);
2318 else{
2319 emit_loadreg(rs1[i],tl);
2320 emit_not(tl,tl);
2321 }
2322 if(s1h>=0) emit_not(s1h,th);
2323 else{
2324 emit_loadreg(rs1[i]|64,th);
2325 emit_not(th,th);
2326 }
2327 }
2328 else
2329 if(rs2[i]){
2330 if(s2l>=0) emit_not(s2l,tl);
2331 else{
2332 emit_loadreg(rs2[i],tl);
2333 emit_not(tl,tl);
2334 }
2335 if(s2h>=0) emit_not(s2h,th);
2336 else{
2337 emit_loadreg(rs2[i]|64,th);
2338 emit_not(th,th);
2339 }
2340 }
2341 else {
2342 emit_movimm(-1,tl);
2343 emit_movimm(-1,th);
2344 }
2345 }
2346 }
2347 }
2348 }
2349 else
2350 {
2351 // 32 bit
2352 if(tl>=0) {
2353 s1l=get_reg(i_regs->regmap,rs1[i]);
2354 s2l=get_reg(i_regs->regmap,rs2[i]);
2355 if(rs1[i]&&rs2[i]) {
2356 assert(s1l>=0);
2357 assert(s2l>=0);
2358 if(opcode2[i]==0x24) { // AND
2359 emit_and(s1l,s2l,tl);
2360 } else
2361 if(opcode2[i]==0x25) { // OR
2362 emit_or(s1l,s2l,tl);
2363 } else
2364 if(opcode2[i]==0x26) { // XOR
2365 emit_xor(s1l,s2l,tl);
2366 } else
2367 if(opcode2[i]==0x27) { // NOR
2368 emit_or(s1l,s2l,tl);
2369 emit_not(tl,tl);
2370 }
2371 }
2372 else
2373 {
2374 if(opcode2[i]==0x24) { // AND
2375 emit_zeroreg(tl);
2376 } else
2377 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2378 if(rs1[i]){
2379 if(s1l>=0) emit_mov(s1l,tl);
2380 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2381 }
2382 else
2383 if(rs2[i]){
2384 if(s2l>=0) emit_mov(s2l,tl);
2385 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2386 }
2387 else emit_zeroreg(tl);
2388 } else
2389 if(opcode2[i]==0x27) { // NOR
2390 if(rs1[i]){
2391 if(s1l>=0) emit_not(s1l,tl);
2392 else {
2393 emit_loadreg(rs1[i],tl);
2394 emit_not(tl,tl);
2395 }
2396 }
2397 else
2398 if(rs2[i]){
2399 if(s2l>=0) emit_not(s2l,tl);
2400 else {
2401 emit_loadreg(rs2[i],tl);
2402 emit_not(tl,tl);
2403 }
2404 }
2405 else emit_movimm(-1,tl);
2406 }
2407 }
2408 }
2409 }
2410 }
2411 }
2412}
2413
2414void imm16_assemble(int i,struct regstat *i_regs)
2415{
2416 if (opcode[i]==0x0f) { // LUI
2417 if(rt1[i]) {
2418 signed char t;
2419 t=get_reg(i_regs->regmap,rt1[i]);
2420 //assert(t>=0);
2421 if(t>=0) {
2422 if(!((i_regs->isconst>>t)&1))
2423 emit_movimm(imm[i]<<16,t);
2424 }
2425 }
2426 }
2427 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2428 if(rt1[i]) {
2429 signed char s,t;
2430 t=get_reg(i_regs->regmap,rt1[i]);
2431 s=get_reg(i_regs->regmap,rs1[i]);
2432 if(rs1[i]) {
2433 //assert(t>=0);
2434 //assert(s>=0);
2435 if(t>=0) {
2436 if(!((i_regs->isconst>>t)&1)) {
2437 if(s<0) {
2438 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2439 emit_addimm(t,imm[i],t);
2440 }else{
2441 if(!((i_regs->wasconst>>s)&1))
2442 emit_addimm(s,imm[i],t);
2443 else
2444 emit_movimm(constmap[i][s]+imm[i],t);
2445 }
2446 }
2447 }
2448 } else {
2449 if(t>=0) {
2450 if(!((i_regs->isconst>>t)&1))
2451 emit_movimm(imm[i],t);
2452 }
2453 }
2454 }
2455 }
2456 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2457 if(rt1[i]) {
2458 signed char sh,sl,th,tl;
2459 th=get_reg(i_regs->regmap,rt1[i]|64);
2460 tl=get_reg(i_regs->regmap,rt1[i]);
2461 sh=get_reg(i_regs->regmap,rs1[i]|64);
2462 sl=get_reg(i_regs->regmap,rs1[i]);
2463 if(tl>=0) {
2464 if(rs1[i]) {
2465 assert(sh>=0);
2466 assert(sl>=0);
2467 if(th>=0) {
2468 emit_addimm64_32(sh,sl,imm[i],th,tl);
2469 }
2470 else {
2471 emit_addimm(sl,imm[i],tl);
2472 }
2473 } else {
2474 emit_movimm(imm[i],tl);
2475 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2476 }
2477 }
2478 }
2479 }
2480 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2481 if(rt1[i]) {
2482 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2483 signed char sh,sl,t;
2484 t=get_reg(i_regs->regmap,rt1[i]);
2485 sh=get_reg(i_regs->regmap,rs1[i]|64);
2486 sl=get_reg(i_regs->regmap,rs1[i]);
2487 //assert(t>=0);
2488 if(t>=0) {
2489 if(rs1[i]>0) {
2490 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2491 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2492 if(opcode[i]==0x0a) { // SLTI
2493 if(sl<0) {
2494 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495 emit_slti32(t,imm[i],t);
2496 }else{
2497 emit_slti32(sl,imm[i],t);
2498 }
2499 }
2500 else { // SLTIU
2501 if(sl<0) {
2502 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2503 emit_sltiu32(t,imm[i],t);
2504 }else{
2505 emit_sltiu32(sl,imm[i],t);
2506 }
2507 }
2508 }else{ // 64-bit
2509 assert(sl>=0);
2510 if(opcode[i]==0x0a) // SLTI
2511 emit_slti64_32(sh,sl,imm[i],t);
2512 else // SLTIU
2513 emit_sltiu64_32(sh,sl,imm[i],t);
2514 }
2515 }else{
2516 // SLTI(U) with r0 is just stupid,
2517 // nonetheless examples can be found
2518 if(opcode[i]==0x0a) // SLTI
2519 if(0<imm[i]) emit_movimm(1,t);
2520 else emit_zeroreg(t);
2521 else // SLTIU
2522 {
2523 if(imm[i]) emit_movimm(1,t);
2524 else emit_zeroreg(t);
2525 }
2526 }
2527 }
2528 }
2529 }
2530 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2531 if(rt1[i]) {
2532 signed char sh,sl,th,tl;
2533 th=get_reg(i_regs->regmap,rt1[i]|64);
2534 tl=get_reg(i_regs->regmap,rt1[i]);
2535 sh=get_reg(i_regs->regmap,rs1[i]|64);
2536 sl=get_reg(i_regs->regmap,rs1[i]);
2537 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2538 if(opcode[i]==0x0c) //ANDI
2539 {
2540 if(rs1[i]) {
2541 if(sl<0) {
2542 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2543 emit_andimm(tl,imm[i],tl);
2544 }else{
2545 if(!((i_regs->wasconst>>sl)&1))
2546 emit_andimm(sl,imm[i],tl);
2547 else
2548 emit_movimm(constmap[i][sl]&imm[i],tl);
2549 }
2550 }
2551 else
2552 emit_zeroreg(tl);
2553 if(th>=0) emit_zeroreg(th);
2554 }
2555 else
2556 {
2557 if(rs1[i]) {
2558 if(sl<0) {
2559 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2560 }
2561 if(th>=0) {
2562 if(sh<0) {
2563 emit_loadreg(rs1[i]|64,th);
2564 }else{
2565 emit_mov(sh,th);
2566 }
2567 }
2568 if(opcode[i]==0x0d) //ORI
2569 if(sl<0) {
2570 emit_orimm(tl,imm[i],tl);
2571 }else{
2572 if(!((i_regs->wasconst>>sl)&1))
2573 emit_orimm(sl,imm[i],tl);
2574 else
2575 emit_movimm(constmap[i][sl]|imm[i],tl);
2576 }
2577 if(opcode[i]==0x0e) //XORI
2578 if(sl<0) {
2579 emit_xorimm(tl,imm[i],tl);
2580 }else{
2581 if(!((i_regs->wasconst>>sl)&1))
2582 emit_xorimm(sl,imm[i],tl);
2583 else
2584 emit_movimm(constmap[i][sl]^imm[i],tl);
2585 }
2586 }
2587 else {
2588 emit_movimm(imm[i],tl);
2589 if(th>=0) emit_zeroreg(th);
2590 }
2591 }
2592 }
2593 }
2594 }
2595}
2596
2597void shiftimm_assemble(int i,struct regstat *i_regs)
2598{
2599 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2600 {
2601 if(rt1[i]) {
2602 signed char s,t;
2603 t=get_reg(i_regs->regmap,rt1[i]);
2604 s=get_reg(i_regs->regmap,rs1[i]);
2605 //assert(t>=0);
2606 if(t>=0){
2607 if(rs1[i]==0)
2608 {
2609 emit_zeroreg(t);
2610 }
2611 else
2612 {
2613 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2614 if(imm[i]) {
2615 if(opcode2[i]==0) // SLL
2616 {
2617 emit_shlimm(s<0?t:s,imm[i],t);
2618 }
2619 if(opcode2[i]==2) // SRL
2620 {
2621 emit_shrimm(s<0?t:s,imm[i],t);
2622 }
2623 if(opcode2[i]==3) // SRA
2624 {
2625 emit_sarimm(s<0?t:s,imm[i],t);
2626 }
2627 }else{
2628 // Shift by zero
2629 if(s>=0 && s!=t) emit_mov(s,t);
2630 }
2631 }
2632 }
2633 //emit_storereg(rt1[i],t); //DEBUG
2634 }
2635 }
2636 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2637 {
2638 if(rt1[i]) {
2639 signed char sh,sl,th,tl;
2640 th=get_reg(i_regs->regmap,rt1[i]|64);
2641 tl=get_reg(i_regs->regmap,rt1[i]);
2642 sh=get_reg(i_regs->regmap,rs1[i]|64);
2643 sl=get_reg(i_regs->regmap,rs1[i]);
2644 if(tl>=0) {
2645 if(rs1[i]==0)
2646 {
2647 emit_zeroreg(tl);
2648 if(th>=0) emit_zeroreg(th);
2649 }
2650 else
2651 {
2652 assert(sl>=0);
2653 assert(sh>=0);
2654 if(imm[i]) {
2655 if(opcode2[i]==0x38) // DSLL
2656 {
2657 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2658 emit_shlimm(sl,imm[i],tl);
2659 }
2660 if(opcode2[i]==0x3a) // DSRL
2661 {
2662 emit_shrdimm(sl,sh,imm[i],tl);
2663 if(th>=0) emit_shrimm(sh,imm[i],th);
2664 }
2665 if(opcode2[i]==0x3b) // DSRA
2666 {
2667 emit_shrdimm(sl,sh,imm[i],tl);
2668 if(th>=0) emit_sarimm(sh,imm[i],th);
2669 }
2670 }else{
2671 // Shift by zero
2672 if(sl!=tl) emit_mov(sl,tl);
2673 if(th>=0&&sh!=th) emit_mov(sh,th);
2674 }
2675 }
2676 }
2677 }
2678 }
2679 if(opcode2[i]==0x3c) // DSLL32
2680 {
2681 if(rt1[i]) {
2682 signed char sl,tl,th;
2683 tl=get_reg(i_regs->regmap,rt1[i]);
2684 th=get_reg(i_regs->regmap,rt1[i]|64);
2685 sl=get_reg(i_regs->regmap,rs1[i]);
2686 if(th>=0||tl>=0){
2687 assert(tl>=0);
2688 assert(th>=0);
2689 assert(sl>=0);
2690 emit_mov(sl,th);
2691 emit_zeroreg(tl);
2692 if(imm[i]>32)
2693 {
2694 emit_shlimm(th,imm[i]&31,th);
2695 }
2696 }
2697 }
2698 }
2699 if(opcode2[i]==0x3e) // DSRL32
2700 {
2701 if(rt1[i]) {
2702 signed char sh,tl,th;
2703 tl=get_reg(i_regs->regmap,rt1[i]);
2704 th=get_reg(i_regs->regmap,rt1[i]|64);
2705 sh=get_reg(i_regs->regmap,rs1[i]|64);
2706 if(tl>=0){
2707 assert(sh>=0);
2708 emit_mov(sh,tl);
2709 if(th>=0) emit_zeroreg(th);
2710 if(imm[i]>32)
2711 {
2712 emit_shrimm(tl,imm[i]&31,tl);
2713 }
2714 }
2715 }
2716 }
2717 if(opcode2[i]==0x3f) // DSRA32
2718 {
2719 if(rt1[i]) {
2720 signed char sh,tl;
2721 tl=get_reg(i_regs->regmap,rt1[i]);
2722 sh=get_reg(i_regs->regmap,rs1[i]|64);
2723 if(tl>=0){
2724 assert(sh>=0);
2725 emit_mov(sh,tl);
2726 if(imm[i]>32)
2727 {
2728 emit_sarimm(tl,imm[i]&31,tl);
2729 }
2730 }
2731 }
2732 }
2733}
2734
2735#ifndef shift_assemble
2736void shift_assemble(int i,struct regstat *i_regs)
2737{
2738 printf("Need shift_assemble for this architecture.\n");
2739 exit(1);
2740}
2741#endif
2742
2743void load_assemble(int i,struct regstat *i_regs)
2744{
2745 int s,th,tl,addr,map=-1;
2746 int offset;
2747 int jaddr=0;
5bf843dc 2748 int memtarget=0,c=0;
57871462 2749 u_int hr,reglist=0;
2750 th=get_reg(i_regs->regmap,rt1[i]|64);
2751 tl=get_reg(i_regs->regmap,rt1[i]);
2752 s=get_reg(i_regs->regmap,rs1[i]);
2753 offset=imm[i];
2754 for(hr=0;hr<HOST_REGS;hr++) {
2755 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2756 }
2757 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2758 if(s>=0) {
2759 c=(i_regs->wasconst>>s)&1;
4cb76aa4 2760 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 2761 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2762 }
57871462 2763 //printf("load_assemble: c=%d\n",c);
2764 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2765 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2766#ifdef PCSX
f18c0f46 2767 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2768 ||rt1[i]==0) {
5bf843dc 2769 // could be FIFO, must perform the read
f18c0f46 2770 // ||dummy read
5bf843dc 2771 assem_debug("(forced read)\n");
2772 tl=get_reg(i_regs->regmap,-1);
2773 assert(tl>=0);
5bf843dc 2774 }
f18c0f46 2775#endif
5bf843dc 2776 if(offset||s<0||c) addr=tl;
2777 else addr=s;
535d208a 2778 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2779 if(tl>=0) {
2780 //printf("load_assemble: c=%d\n",c);
2781 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2782 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2783 reglist&=~(1<<tl);
2784 if(th>=0) reglist&=~(1<<th);
2785 if(!using_tlb) {
2786 if(!c) {
2787 #ifdef RAM_OFFSET
2788 map=get_reg(i_regs->regmap,ROREG);
2789 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2790 #endif
57871462 2791//#define R29_HACK 1
535d208a 2792 #ifdef R29_HACK
2793 // Strmnnrmn's speed hack
2794 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2795 #endif
2796 {
2797 emit_cmpimm(addr,RAM_SIZE);
2798 jaddr=(int)out;
2799 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2800 // Hint to branch predictor that the branch is unlikely to be taken
2801 if(rs1[i]>=28)
2802 emit_jno_unlikely(0);
2803 else
57871462 2804 #endif
535d208a 2805 emit_jno(0);
57871462 2806 }
535d208a 2807 }
2808 }else{ // using tlb
2809 int x=0;
2810 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2811 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2812 map=get_reg(i_regs->regmap,TLREG);
2813 assert(map>=0);
2814 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2815 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2816 }
2817 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2818 if (opcode[i]==0x20) { // LB
2819 if(!c||memtarget) {
2820 if(!dummy) {
57871462 2821 #ifdef HOST_IMM_ADDR32
2822 if(c)
2823 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2824 else
2825 #endif
2826 {
2827 //emit_xorimm(addr,3,tl);
2828 //gen_tlb_addr_r(tl,map);
2829 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2830 int x=0,a=tl;
2002a1db 2831#ifdef BIG_ENDIAN_MIPS
57871462 2832 if(!c) emit_xorimm(addr,3,tl);
2833 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2834#else
535d208a 2835 if(!c) a=addr;
2002a1db 2836#endif
535d208a 2837 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2838 }
57871462 2839 }
535d208a 2840 if(jaddr)
2841 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2842 }
535d208a 2843 else
2844 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845 }
2846 if (opcode[i]==0x21) { // LH
2847 if(!c||memtarget) {
2848 if(!dummy) {
57871462 2849 #ifdef HOST_IMM_ADDR32
2850 if(c)
2851 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2852 else
2853 #endif
2854 {
535d208a 2855 int x=0,a=tl;
2002a1db 2856#ifdef BIG_ENDIAN_MIPS
57871462 2857 if(!c) emit_xorimm(addr,2,tl);
2858 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2859#else
535d208a 2860 if(!c) a=addr;
2002a1db 2861#endif
57871462 2862 //#ifdef
2863 //emit_movswl_indexed_tlb(x,tl,map,tl);
2864 //else
2865 if(map>=0) {
535d208a 2866 gen_tlb_addr_r(a,map);
2867 emit_movswl_indexed(x,a,tl);
2868 }else{
2869 #ifdef RAM_OFFSET
2870 emit_movswl_indexed(x,a,tl);
2871 #else
2872 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2873 #endif
2874 }
57871462 2875 }
57871462 2876 }
535d208a 2877 if(jaddr)
2878 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2879 }
535d208a 2880 else
2881 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2882 }
2883 if (opcode[i]==0x23) { // LW
2884 if(!c||memtarget) {
2885 if(!dummy) {
57871462 2886 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2887 #ifdef HOST_IMM_ADDR32
2888 if(c)
2889 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2890 else
2891 #endif
2892 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2893 }
535d208a 2894 if(jaddr)
2895 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2896 }
535d208a 2897 else
2898 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2899 }
2900 if (opcode[i]==0x24) { // LBU
2901 if(!c||memtarget) {
2902 if(!dummy) {
57871462 2903 #ifdef HOST_IMM_ADDR32
2904 if(c)
2905 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2906 else
2907 #endif
2908 {
2909 //emit_xorimm(addr,3,tl);
2910 //gen_tlb_addr_r(tl,map);
2911 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2912 int x=0,a=tl;
2002a1db 2913#ifdef BIG_ENDIAN_MIPS
57871462 2914 if(!c) emit_xorimm(addr,3,tl);
2915 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2916#else
535d208a 2917 if(!c) a=addr;
2002a1db 2918#endif
535d208a 2919 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2920 }
57871462 2921 }
535d208a 2922 if(jaddr)
2923 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2924 }
535d208a 2925 else
2926 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2927 }
2928 if (opcode[i]==0x25) { // LHU
2929 if(!c||memtarget) {
2930 if(!dummy) {
57871462 2931 #ifdef HOST_IMM_ADDR32
2932 if(c)
2933 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2934 else
2935 #endif
2936 {
535d208a 2937 int x=0,a=tl;
2002a1db 2938#ifdef BIG_ENDIAN_MIPS
57871462 2939 if(!c) emit_xorimm(addr,2,tl);
2940 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2941#else
535d208a 2942 if(!c) a=addr;
2002a1db 2943#endif
57871462 2944 //#ifdef
2945 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2946 //#else
2947 if(map>=0) {
535d208a 2948 gen_tlb_addr_r(a,map);
2949 emit_movzwl_indexed(x,a,tl);
2950 }else{
2951 #ifdef RAM_OFFSET
2952 emit_movzwl_indexed(x,a,tl);
2953 #else
2954 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2955 #endif
2956 }
57871462 2957 }
2958 }
535d208a 2959 if(jaddr)
2960 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2961 }
535d208a 2962 else
2963 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2964 }
2965 if (opcode[i]==0x27) { // LWU
2966 assert(th>=0);
2967 if(!c||memtarget) {
2968 if(!dummy) {
57871462 2969 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2970 #ifdef HOST_IMM_ADDR32
2971 if(c)
2972 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2973 else
2974 #endif
2975 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2976 }
535d208a 2977 if(jaddr)
2978 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2979 }
2980 else {
2981 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2982 }
535d208a 2983 emit_zeroreg(th);
2984 }
2985 if (opcode[i]==0x37) { // LD
2986 if(!c||memtarget) {
2987 if(!dummy) {
57871462 2988 //gen_tlb_addr_r(tl,map);
2989 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2990 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2991 #ifdef HOST_IMM_ADDR32
2992 if(c)
2993 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2994 else
2995 #endif
2996 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 2997 }
535d208a 2998 if(jaddr)
2999 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3000 }
535d208a 3001 else
3002 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3003 }
535d208a 3004 }
3005 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3006 //if(opcode[i]==0x23)
3007 //if(opcode[i]==0x24)
3008 //if(opcode[i]==0x23||opcode[i]==0x24)
3009 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3010 {
3011 //emit_pusha();
3012 save_regs(0x100f);
3013 emit_readword((int)&last_count,ECX);
3014 #ifdef __i386__
3015 if(get_reg(i_regs->regmap,CCREG)<0)
3016 emit_loadreg(CCREG,HOST_CCREG);
3017 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3018 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3019 emit_writeword(HOST_CCREG,(int)&Count);
3020 #endif
3021 #ifdef __arm__
3022 if(get_reg(i_regs->regmap,CCREG)<0)
3023 emit_loadreg(CCREG,0);
3024 else
3025 emit_mov(HOST_CCREG,0);
3026 emit_add(0,ECX,0);
3027 emit_addimm(0,2*ccadj[i],0);
3028 emit_writeword(0,(int)&Count);
3029 #endif
3030 emit_call((int)memdebug);
3031 //emit_popa();
3032 restore_regs(0x100f);
3033 }/**/
3034}
3035
3036#ifndef loadlr_assemble
3037void loadlr_assemble(int i,struct regstat *i_regs)
3038{
3039 printf("Need loadlr_assemble for this architecture.\n");
3040 exit(1);
3041}
3042#endif
3043
3044void store_assemble(int i,struct regstat *i_regs)
3045{
3046 int s,th,tl,map=-1;
3047 int addr,temp;
3048 int offset;
3049 int jaddr=0,jaddr2,type;
666a299d 3050 int memtarget=0,c=0;
57871462 3051 int agr=AGEN1+(i&1);
3052 u_int hr,reglist=0;
3053 th=get_reg(i_regs->regmap,rs2[i]|64);
3054 tl=get_reg(i_regs->regmap,rs2[i]);
3055 s=get_reg(i_regs->regmap,rs1[i]);
3056 temp=get_reg(i_regs->regmap,agr);
3057 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3058 offset=imm[i];
3059 if(s>=0) {
3060 c=(i_regs->wasconst>>s)&1;
4cb76aa4 3061 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3062 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3063 }
3064 assert(tl>=0);
3065 assert(temp>=0);
3066 for(hr=0;hr<HOST_REGS;hr++) {
3067 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3068 }
3069 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3070 if(offset||s<0||c) addr=temp;
3071 else addr=s;
3072 if(!using_tlb) {
3073 if(!c) {
3074 #ifdef R29_HACK
3075 // Strmnnrmn's speed hack
3076 memtarget=1;
4cb76aa4 3077 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3078 #endif
4cb76aa4 3079 emit_cmpimm(addr,RAM_SIZE);
57871462 3080 #ifdef DESTRUCTIVE_SHIFT
3081 if(s==addr) emit_mov(s,temp);
3082 #endif
3083 #ifdef R29_HACK
4cb76aa4 3084 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3085 #endif
3086 {
3087 jaddr=(int)out;
3088 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3089 // Hint to branch predictor that the branch is unlikely to be taken
3090 if(rs1[i]>=28)
3091 emit_jno_unlikely(0);
3092 else
3093 #endif
3094 emit_jno(0);
3095 }
3096 }
3097 }else{ // using tlb
3098 int x=0;
3099 if (opcode[i]==0x28) x=3; // SB
3100 if (opcode[i]==0x29) x=2; // SH
3101 map=get_reg(i_regs->regmap,TLREG);
3102 assert(map>=0);
3103 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3104 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3105 }
3106
3107 if (opcode[i]==0x28) { // SB
3108 if(!c||memtarget) {
3109 int x=0;
2002a1db 3110#ifdef BIG_ENDIAN_MIPS
57871462 3111 if(!c) emit_xorimm(addr,3,temp);
3112 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3113#else
3114 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3115 else if (addr!=temp) emit_mov(addr,temp);
3116#endif
57871462 3117 //gen_tlb_addr_w(temp,map);
3118 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3119 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3120 }
3121 type=STOREB_STUB;
3122 }
3123 if (opcode[i]==0x29) { // SH
3124 if(!c||memtarget) {
3125 int x=0;
2002a1db 3126#ifdef BIG_ENDIAN_MIPS
57871462 3127 if(!c) emit_xorimm(addr,2,temp);
3128 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3129#else
3130 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3131 else if (addr!=temp) emit_mov(addr,temp);
3132#endif
57871462 3133 //#ifdef
3134 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3135 //#else
3136 if(map>=0) {
3137 gen_tlb_addr_w(temp,map);
3138 emit_writehword_indexed(tl,x,temp);
3139 }else
3140 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3141 }
3142 type=STOREH_STUB;
3143 }
3144 if (opcode[i]==0x2B) { // SW
3145 if(!c||memtarget)
3146 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3147 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3148 type=STOREW_STUB;
3149 }
3150 if (opcode[i]==0x3F) { // SD
3151 if(!c||memtarget) {
3152 if(rs2[i]) {
3153 assert(th>=0);
3154 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3155 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3156 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3157 }else{
3158 // Store zero
3159 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3160 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3161 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3162 }
3163 }
3164 type=STORED_STUB;
3165 }
666a299d 3166 if(!using_tlb&&(!c||memtarget))
3167 // addr could be a temp, make sure it survives STORE*_STUB
3168 reglist|=1<<addr;
57871462 3169 if(jaddr) {
3170 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3171 } else if(!memtarget) {
3172 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3173 }
3174 if(!using_tlb) {
3175 if(!c||memtarget) {
3176 #ifdef DESTRUCTIVE_SHIFT
3177 // The x86 shift operation is 'destructive'; it overwrites the
3178 // source register, so we need to make a copy first and use that.
3179 addr=temp;
3180 #endif
3181 #if defined(HOST_IMM8)
3182 int ir=get_reg(i_regs->regmap,INVCP);
3183 assert(ir>=0);
3184 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3185 #else
3186 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3187 #endif
3188 jaddr2=(int)out;
3189 emit_jne(0);
3190 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3191 }
3192 }
3193 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3194 //if(opcode[i]==0x2B || opcode[i]==0x28)
3195 //if(opcode[i]==0x2B || opcode[i]==0x29)
3196 //if(opcode[i]==0x2B)
3197 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3198 {
3199 //emit_pusha();
3200 save_regs(0x100f);
3201 emit_readword((int)&last_count,ECX);
3202 #ifdef __i386__
3203 if(get_reg(i_regs->regmap,CCREG)<0)
3204 emit_loadreg(CCREG,HOST_CCREG);
3205 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3206 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3207 emit_writeword(HOST_CCREG,(int)&Count);
3208 #endif
3209 #ifdef __arm__
3210 if(get_reg(i_regs->regmap,CCREG)<0)
3211 emit_loadreg(CCREG,0);
3212 else
3213 emit_mov(HOST_CCREG,0);
3214 emit_add(0,ECX,0);
3215 emit_addimm(0,2*ccadj[i],0);
3216 emit_writeword(0,(int)&Count);
3217 #endif
3218 emit_call((int)memdebug);
3219 //emit_popa();
3220 restore_regs(0x100f);
3221 }/**/
3222}
3223
3224void storelr_assemble(int i,struct regstat *i_regs)
3225{
3226 int s,th,tl;
3227 int temp;
3228 int temp2;
3229 int offset;
3230 int jaddr=0,jaddr2;
3231 int case1,case2,case3;
3232 int done0,done1,done2;
3233 int memtarget,c=0;
fab5d06d 3234 int agr=AGEN1+(i&1);
57871462 3235 u_int hr,reglist=0;
3236 th=get_reg(i_regs->regmap,rs2[i]|64);
3237 tl=get_reg(i_regs->regmap,rs2[i]);
3238 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3239 temp=get_reg(i_regs->regmap,agr);
3240 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3241 offset=imm[i];
3242 if(s>=0) {
3243 c=(i_regs->isconst>>s)&1;
4cb76aa4 3244 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
57871462 3245 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3246 }
3247 assert(tl>=0);
3248 for(hr=0;hr<HOST_REGS;hr++) {
3249 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3250 }
535d208a 3251 assert(temp>=0);
3252 if(!using_tlb) {
3253 if(!c) {
3254 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3255 if(!offset&&s!=temp) emit_mov(s,temp);
3256 jaddr=(int)out;
3257 emit_jno(0);
3258 }
3259 else
3260 {
3261 if(!memtarget||!rs1[i]) {
57871462 3262 jaddr=(int)out;
3263 emit_jmp(0);
3264 }
57871462 3265 }
535d208a 3266 #ifdef RAM_OFFSET
3267 int map=get_reg(i_regs->regmap,ROREG);
3268 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3269 gen_tlb_addr_w(temp,map);
3270 #else
3271 if((u_int)rdram!=0x80000000)
3272 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3273 #endif
3274 }else{ // using tlb
3275 int map=get_reg(i_regs->regmap,TLREG);
3276 assert(map>=0);
3277 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3278 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3279 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3280 if(!jaddr&&!memtarget) {
3281 jaddr=(int)out;
3282 emit_jmp(0);
57871462 3283 }
535d208a 3284 gen_tlb_addr_w(temp,map);
3285 }
3286
3287 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3288 temp2=get_reg(i_regs->regmap,FTEMP);
3289 if(!rs2[i]) temp2=th=tl;
3290 }
57871462 3291
2002a1db 3292#ifndef BIG_ENDIAN_MIPS
3293 emit_xorimm(temp,3,temp);
3294#endif
535d208a 3295 emit_testimm(temp,2);
3296 case2=(int)out;
3297 emit_jne(0);
3298 emit_testimm(temp,1);
3299 case1=(int)out;
3300 emit_jne(0);
3301 // 0
3302 if (opcode[i]==0x2A) { // SWL
3303 emit_writeword_indexed(tl,0,temp);
3304 }
3305 if (opcode[i]==0x2E) { // SWR
3306 emit_writebyte_indexed(tl,3,temp);
3307 }
3308 if (opcode[i]==0x2C) { // SDL
3309 emit_writeword_indexed(th,0,temp);
3310 if(rs2[i]) emit_mov(tl,temp2);
3311 }
3312 if (opcode[i]==0x2D) { // SDR
3313 emit_writebyte_indexed(tl,3,temp);
3314 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3315 }
3316 done0=(int)out;
3317 emit_jmp(0);
3318 // 1
3319 set_jump_target(case1,(int)out);
3320 if (opcode[i]==0x2A) { // SWL
3321 // Write 3 msb into three least significant bytes
3322 if(rs2[i]) emit_rorimm(tl,8,tl);
3323 emit_writehword_indexed(tl,-1,temp);
3324 if(rs2[i]) emit_rorimm(tl,16,tl);
3325 emit_writebyte_indexed(tl,1,temp);
3326 if(rs2[i]) emit_rorimm(tl,8,tl);
3327 }
3328 if (opcode[i]==0x2E) { // SWR
3329 // Write two lsb into two most significant bytes
3330 emit_writehword_indexed(tl,1,temp);
3331 }
3332 if (opcode[i]==0x2C) { // SDL
3333 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3334 // Write 3 msb into three least significant bytes
3335 if(rs2[i]) emit_rorimm(th,8,th);
3336 emit_writehword_indexed(th,-1,temp);
3337 if(rs2[i]) emit_rorimm(th,16,th);
3338 emit_writebyte_indexed(th,1,temp);
3339 if(rs2[i]) emit_rorimm(th,8,th);
3340 }
3341 if (opcode[i]==0x2D) { // SDR
3342 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3343 // Write two lsb into two most significant bytes
3344 emit_writehword_indexed(tl,1,temp);
3345 }
3346 done1=(int)out;
3347 emit_jmp(0);
3348 // 2
3349 set_jump_target(case2,(int)out);
3350 emit_testimm(temp,1);
3351 case3=(int)out;
3352 emit_jne(0);
3353 if (opcode[i]==0x2A) { // SWL
3354 // Write two msb into two least significant bytes
3355 if(rs2[i]) emit_rorimm(tl,16,tl);
3356 emit_writehword_indexed(tl,-2,temp);
3357 if(rs2[i]) emit_rorimm(tl,16,tl);
3358 }
3359 if (opcode[i]==0x2E) { // SWR
3360 // Write 3 lsb into three most significant bytes
3361 emit_writebyte_indexed(tl,-1,temp);
3362 if(rs2[i]) emit_rorimm(tl,8,tl);
3363 emit_writehword_indexed(tl,0,temp);
3364 if(rs2[i]) emit_rorimm(tl,24,tl);
3365 }
3366 if (opcode[i]==0x2C) { // SDL
3367 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3368 // Write two msb into two least significant bytes
3369 if(rs2[i]) emit_rorimm(th,16,th);
3370 emit_writehword_indexed(th,-2,temp);
3371 if(rs2[i]) emit_rorimm(th,16,th);
3372 }
3373 if (opcode[i]==0x2D) { // SDR
3374 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3375 // Write 3 lsb into three most significant bytes
3376 emit_writebyte_indexed(tl,-1,temp);
3377 if(rs2[i]) emit_rorimm(tl,8,tl);
3378 emit_writehword_indexed(tl,0,temp);
3379 if(rs2[i]) emit_rorimm(tl,24,tl);
3380 }
3381 done2=(int)out;
3382 emit_jmp(0);
3383 // 3
3384 set_jump_target(case3,(int)out);
3385 if (opcode[i]==0x2A) { // SWL
3386 // Write msb into least significant byte
3387 if(rs2[i]) emit_rorimm(tl,24,tl);